firewire: ohci: do not enable interrupts without the handler

On 26 Apr 2010, Clemens Ladisch wrote:
> In theory, none of the interrupts should occur before the link is
> enabled.  In practice, I'd rather make sure to not set the master
> interrupt enable bit until we have installed the interrupt handler.

and proposed to move OHCI1394_masterIntEnable out of the present
reg_write() into a new one before the HCControl.linkEnable reg_write().

Why not defer setting /all/ of the bits until right before linkEnable?

Reviewed-by: Clemens Ladisch <clemens@ladisch.de>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>

diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 07deac7..9743a40 100644 (file)
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -1594,7 +1594,7 @@ static int ohci_enable(struct fw_card *card,
 {
        struct fw_ohci *ohci = fw_ohci(card);
        struct pci_dev *dev = to_pci_dev(card->device);
-       u32 lps;
+       u32 lps, irqs;
        int i, ret;
 
        if (software_reset(ohci)) {
@@ -1648,16 +1648,6 @@ static int ohci_enable(struct fw_card *card,
        reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
        reg_write(ohci, OHCI1394_IntEventClear, ~0);
        reg_write(ohci, OHCI1394_IntMaskClear, ~0);
-       reg_write(ohci, OHCI1394_IntMaskSet,
-                 OHCI1394_selfIDComplete |
-                 OHCI1394_RQPkt | OHCI1394_RSPkt |
-                 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
-                 OHCI1394_isochRx | OHCI1394_isochTx |
-                 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
-                 OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
-                 OHCI1394_masterIntEnable);
-       if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
-               reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
 
        ret = configure_1394a_enhancements(ohci);
        if (ret < 0)
@@ -1723,6 +1713,18 @@ static int ohci_enable(struct fw_card *card,
                return -EIO;
        }
 
+       irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
+               OHCI1394_RQPkt | OHCI1394_RSPkt |
+               OHCI1394_isochTx | OHCI1394_isochRx |
+               OHCI1394_postedWriteErr |
+               OHCI1394_selfIDComplete |
+               OHCI1394_regAccessFail |
+               OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
+               OHCI1394_masterIntEnable;
+       if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
+               irqs |= OHCI1394_busReset;
+       reg_write(ohci, OHCI1394_IntMaskSet, irqs);
+
        reg_write(ohci, OHCI1394_HCControlSet,
                  OHCI1394_HCControl_linkEnable |
                  OHCI1394_HCControl_BIBimageValid);