2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
23 int mindelta, int main_rssi_avg,
24 int alt_rssi_avg, int pkt_count)
26 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
27 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
28 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
33 return sc->ps_enabled &&
34 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
38 struct ieee80211_hdr *hdr)
40 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
43 spin_lock_bh(&sc->wiphy_lock);
44 for (i = 0; i < sc->num_sec_wiphy; i++) {
45 struct ath_wiphy *aphy = sc->sec_wiphy[i];
48 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
54 spin_unlock_bh(&sc->wiphy_lock);
59 * Setup and link descriptors.
61 * 11N: we can no longer afford to self link the last descriptor.
62 * MAC acknowledges BA status as long as it copies frames to host
63 * buffer (or rx fifo). This can incorrectly acknowledge packets
64 * to a sender if last desc is self-linked.
66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
68 struct ath_hw *ah = sc->sc_ah;
69 struct ath_common *common = ath9k_hw_common(ah);
76 ds->ds_link = 0; /* link to null */
77 ds->ds_data = bf->bf_buf_addr;
79 /* virtual addr of the beginning of the buffer. */
82 ds->ds_vdata = skb->data;
85 * setup rx descriptors. The rx_bufsize here tells the hardware
86 * how much data it can DMA to us and that we are prepared
89 ath9k_hw_setuprxdesc(ah, ds,
93 if (sc->rx.rxlink == NULL)
94 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
96 *sc->rx.rxlink = bf->bf_daddr;
98 sc->rx.rxlink = &ds->ds_link;
102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
104 /* XXX block beacon interrupts */
105 ath9k_hw_setantenna(sc->sc_ah, antenna);
106 sc->rx.defant = antenna;
107 sc->rx.rxotherant = 0;
110 static void ath_opmode_init(struct ath_softc *sc)
112 struct ath_hw *ah = sc->sc_ah;
113 struct ath_common *common = ath9k_hw_common(ah);
117 /* configure rx filter */
118 rfilt = ath_calcrxfilter(sc);
119 ath9k_hw_setrxfilter(ah, rfilt);
121 /* configure bssid mask */
122 ath_hw_setbssidmask(common);
124 /* configure operational mode */
125 ath9k_hw_setopmode(ah);
127 /* calculate and install multicast filter */
128 mfilt[0] = mfilt[1] = ~0;
129 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
132 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
133 enum ath9k_rx_qtype qtype)
135 struct ath_hw *ah = sc->sc_ah;
136 struct ath_rx_edma *rx_edma;
140 rx_edma = &sc->rx.rx_edma[qtype];
141 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
144 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
145 list_del_init(&bf->list);
150 memset(skb->data, 0, ah->caps.rx_status_len);
151 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
152 ah->caps.rx_status_len, DMA_TO_DEVICE);
154 SKB_CB_ATHBUF(skb) = bf;
155 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
156 skb_queue_tail(&rx_edma->rx_fifo, skb);
161 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
162 enum ath9k_rx_qtype qtype, int size)
164 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
167 if (list_empty(&sc->rx.rxbuf)) {
168 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
172 while (!list_empty(&sc->rx.rxbuf)) {
175 if (!ath_rx_edma_buf_link(sc, qtype))
183 static void ath_rx_remove_buffer(struct ath_softc *sc,
184 enum ath9k_rx_qtype qtype)
187 struct ath_rx_edma *rx_edma;
190 rx_edma = &sc->rx.rx_edma[qtype];
192 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
193 bf = SKB_CB_ATHBUF(skb);
195 list_add_tail(&bf->list, &sc->rx.rxbuf);
199 static void ath_rx_edma_cleanup(struct ath_softc *sc)
203 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
204 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
206 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
208 dev_kfree_skb_any(bf->bf_mpdu);
211 INIT_LIST_HEAD(&sc->rx.rxbuf);
213 kfree(sc->rx.rx_bufptr);
214 sc->rx.rx_bufptr = NULL;
217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
219 skb_queue_head_init(&rx_edma->rx_fifo);
220 skb_queue_head_init(&rx_edma->rx_buffers);
221 rx_edma->rx_fifo_hwsize = size;
224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
226 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
227 struct ath_hw *ah = sc->sc_ah;
234 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
235 ah->caps.rx_status_len,
236 min(common->cachelsz, (u16)64));
238 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
239 ah->caps.rx_status_len);
241 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
242 ah->caps.rx_lp_qdepth);
243 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
244 ah->caps.rx_hp_qdepth);
246 size = sizeof(struct ath_buf) * nbufs;
247 bf = kzalloc(size, GFP_KERNEL);
251 INIT_LIST_HEAD(&sc->rx.rxbuf);
252 sc->rx.rx_bufptr = bf;
254 for (i = 0; i < nbufs; i++, bf++) {
255 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
261 memset(skb->data, 0, common->rx_bufsize);
264 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
267 if (unlikely(dma_mapping_error(sc->dev,
269 dev_kfree_skb_any(skb);
273 "dma_mapping_error() on RX init\n");
278 list_add_tail(&bf->list, &sc->rx.rxbuf);
284 ath_rx_edma_cleanup(sc);
288 static void ath_edma_start_recv(struct ath_softc *sc)
290 spin_lock_bh(&sc->rx.rxbuflock);
292 ath9k_hw_rxena(sc->sc_ah);
294 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
295 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
297 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
298 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
302 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
304 spin_unlock_bh(&sc->rx.rxbuflock);
307 static void ath_edma_stop_recv(struct ath_softc *sc)
309 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
310 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
313 int ath_rx_init(struct ath_softc *sc, int nbufs)
315 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
320 spin_lock_init(&sc->sc_pcu_lock);
321 sc->sc_flags &= ~SC_OP_RXFLUSH;
322 spin_lock_init(&sc->rx.rxbuflock);
324 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
325 return ath_rx_edma_init(sc, nbufs);
327 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
328 min(common->cachelsz, (u16)64));
330 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
331 common->cachelsz, common->rx_bufsize);
333 /* Initialize rx descriptors */
335 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
339 "failed to allocate rx descriptors: %d\n",
344 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
345 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
353 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
356 if (unlikely(dma_mapping_error(sc->dev,
358 dev_kfree_skb_any(skb);
362 "dma_mapping_error() on RX init\n");
367 sc->rx.rxlink = NULL;
377 void ath_rx_cleanup(struct ath_softc *sc)
379 struct ath_hw *ah = sc->sc_ah;
380 struct ath_common *common = ath9k_hw_common(ah);
384 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
385 ath_rx_edma_cleanup(sc);
388 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
391 dma_unmap_single(sc->dev, bf->bf_buf_addr,
400 if (sc->rx.rxdma.dd_desc_len != 0)
401 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
406 * Calculate the receive filter according to the
407 * operating mode and state:
409 * o always accept unicast, broadcast, and multicast traffic
410 * o maintain current state of phy error reception (the hal
411 * may enable phy error frames for noise immunity work)
412 * o probe request frames are accepted only when operating in
413 * hostap, adhoc, or monitor modes
414 * o enable promiscuous mode according to the interface state
416 * - when operating in adhoc mode so the 802.11 layer creates
417 * node table entries for peers,
418 * - when operating in station mode for collecting rssi data when
419 * the station is otherwise quiet, or
420 * - when operating as a repeater so we see repeater-sta beacons
424 u32 ath_calcrxfilter(struct ath_softc *sc)
426 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
430 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
431 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
432 | ATH9K_RX_FILTER_MCAST;
434 if (sc->rx.rxfilter & FIF_PROBE_REQ)
435 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
438 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
439 * mode interface or when in monitor mode. AP mode does not need this
440 * since it receives all in-BSS frames anyway.
442 if (sc->sc_ah->is_monitoring)
443 rfilt |= ATH9K_RX_FILTER_PROM;
445 if (sc->rx.rxfilter & FIF_CONTROL)
446 rfilt |= ATH9K_RX_FILTER_CONTROL;
448 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
450 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
451 rfilt |= ATH9K_RX_FILTER_MYBEACON;
453 rfilt |= ATH9K_RX_FILTER_BEACON;
455 if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) ||
456 AR_SREV_9285_12_OR_LATER(sc->sc_ah)) &&
457 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
458 (sc->rx.rxfilter & FIF_PSPOLL))
459 rfilt |= ATH9K_RX_FILTER_PSPOLL;
461 if (conf_is_ht(&sc->hw->conf))
462 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
464 if (sc->sec_wiphy || (sc->nvifs > 1) ||
465 (sc->rx.rxfilter & FIF_OTHER_BSS)) {
466 /* The following may also be needed for other older chips */
467 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
468 rfilt |= ATH9K_RX_FILTER_PROM;
469 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
474 #undef RX_FILTER_PRESERVE
477 int ath_startrecv(struct ath_softc *sc)
479 struct ath_hw *ah = sc->sc_ah;
480 struct ath_buf *bf, *tbf;
482 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
483 ath_edma_start_recv(sc);
487 spin_lock_bh(&sc->rx.rxbuflock);
488 if (list_empty(&sc->rx.rxbuf))
491 sc->rx.rxlink = NULL;
492 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
493 ath_rx_buf_link(sc, bf);
496 /* We could have deleted elements so the list may be empty now */
497 if (list_empty(&sc->rx.rxbuf))
500 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
501 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
506 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
508 spin_unlock_bh(&sc->rx.rxbuflock);
513 bool ath_stoprecv(struct ath_softc *sc)
515 struct ath_hw *ah = sc->sc_ah;
516 bool stopped, reset = false;
518 spin_lock_bh(&sc->rx.rxbuflock);
519 ath9k_hw_abortpcurecv(ah);
520 ath9k_hw_setrxfilter(ah, 0);
521 stopped = ath9k_hw_stopdmarecv(ah, &reset);
523 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
524 ath_edma_stop_recv(sc);
526 sc->rx.rxlink = NULL;
527 spin_unlock_bh(&sc->rx.rxbuflock);
529 if (!(ah->ah_flags & AH_UNPLUGGED) &&
530 unlikely(!stopped)) {
531 ath_err(ath9k_hw_common(sc->sc_ah),
532 "Could not stop RX, we could be "
533 "confusing the DMA engine when we start RX up\n");
534 ATH_DBG_WARN_ON_ONCE(!stopped);
536 return stopped && !reset;
539 void ath_flushrecv(struct ath_softc *sc)
541 sc->sc_flags |= SC_OP_RXFLUSH;
542 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
543 ath_rx_tasklet(sc, 1, true);
544 ath_rx_tasklet(sc, 1, false);
545 sc->sc_flags &= ~SC_OP_RXFLUSH;
548 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
550 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
551 struct ieee80211_mgmt *mgmt;
552 u8 *pos, *end, id, elen;
553 struct ieee80211_tim_ie *tim;
555 mgmt = (struct ieee80211_mgmt *)skb->data;
556 pos = mgmt->u.beacon.variable;
557 end = skb->data + skb->len;
559 while (pos + 2 < end) {
562 if (pos + elen > end)
565 if (id == WLAN_EID_TIM) {
566 if (elen < sizeof(*tim))
568 tim = (struct ieee80211_tim_ie *) pos;
569 if (tim->dtim_count != 0)
571 return tim->bitmap_ctrl & 0x01;
580 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
582 struct ieee80211_mgmt *mgmt;
583 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
585 if (skb->len < 24 + 8 + 2 + 2)
588 mgmt = (struct ieee80211_mgmt *)skb->data;
589 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
590 return; /* not from our current AP */
592 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
594 if (sc->ps_flags & PS_BEACON_SYNC) {
595 sc->ps_flags &= ~PS_BEACON_SYNC;
596 ath_dbg(common, ATH_DBG_PS,
597 "Reconfigure Beacon timers based on timestamp from the AP\n");
598 ath_beacon_config(sc, NULL);
601 if (ath_beacon_dtim_pending_cab(skb)) {
603 * Remain awake waiting for buffered broadcast/multicast
604 * frames. If the last broadcast/multicast frame is not
605 * received properly, the next beacon frame will work as
606 * a backup trigger for returning into NETWORK SLEEP state,
607 * so we are waiting for it as well.
609 ath_dbg(common, ATH_DBG_PS,
610 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
611 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
615 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
617 * This can happen if a broadcast frame is dropped or the AP
618 * fails to send a frame indicating that all CAB frames have
621 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
622 ath_dbg(common, ATH_DBG_PS,
623 "PS wait for CAB frames timed out\n");
627 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
629 struct ieee80211_hdr *hdr;
630 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
632 hdr = (struct ieee80211_hdr *)skb->data;
634 /* Process Beacon and CAB receive in PS state */
635 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
636 && ieee80211_is_beacon(hdr->frame_control))
637 ath_rx_ps_beacon(sc, skb);
638 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
639 (ieee80211_is_data(hdr->frame_control) ||
640 ieee80211_is_action(hdr->frame_control)) &&
641 is_multicast_ether_addr(hdr->addr1) &&
642 !ieee80211_has_moredata(hdr->frame_control)) {
644 * No more broadcast/multicast frames to be received at this
647 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
648 ath_dbg(common, ATH_DBG_PS,
649 "All PS CAB frames received, back to sleep\n");
650 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
651 !is_multicast_ether_addr(hdr->addr1) &&
652 !ieee80211_has_morefrags(hdr->frame_control)) {
653 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
654 ath_dbg(common, ATH_DBG_PS,
655 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
656 sc->ps_flags & (PS_WAIT_FOR_BEACON |
658 PS_WAIT_FOR_PSPOLL_DATA |
659 PS_WAIT_FOR_TX_ACK));
663 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
664 struct ath_softc *sc, struct sk_buff *skb)
666 struct ieee80211_hdr *hdr;
668 hdr = (struct ieee80211_hdr *)skb->data;
670 /* Send the frame to mac80211 */
671 if (is_multicast_ether_addr(hdr->addr1)) {
674 * Deliver broadcast/multicast frames to all suitable
677 /* TODO: filter based on channel configuration */
678 for (i = 0; i < sc->num_sec_wiphy; i++) {
679 struct ath_wiphy *aphy = sc->sec_wiphy[i];
680 struct sk_buff *nskb;
683 nskb = skb_copy(skb, GFP_ATOMIC);
686 ieee80211_rx(aphy->hw, nskb);
688 ieee80211_rx(sc->hw, skb);
690 /* Deliver unicast frames based on receiver address */
691 ieee80211_rx(hw, skb);
694 static bool ath_edma_get_buffers(struct ath_softc *sc,
695 enum ath9k_rx_qtype qtype)
697 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
698 struct ath_hw *ah = sc->sc_ah;
699 struct ath_common *common = ath9k_hw_common(ah);
704 skb = skb_peek(&rx_edma->rx_fifo);
708 bf = SKB_CB_ATHBUF(skb);
711 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
712 common->rx_bufsize, DMA_FROM_DEVICE);
714 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
715 if (ret == -EINPROGRESS) {
716 /*let device gain the buffer again*/
717 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
718 common->rx_bufsize, DMA_FROM_DEVICE);
722 __skb_unlink(skb, &rx_edma->rx_fifo);
723 if (ret == -EINVAL) {
724 /* corrupt descriptor, skip this one and the following one */
725 list_add_tail(&bf->list, &sc->rx.rxbuf);
726 ath_rx_edma_buf_link(sc, qtype);
727 skb = skb_peek(&rx_edma->rx_fifo);
731 bf = SKB_CB_ATHBUF(skb);
734 __skb_unlink(skb, &rx_edma->rx_fifo);
735 list_add_tail(&bf->list, &sc->rx.rxbuf);
736 ath_rx_edma_buf_link(sc, qtype);
739 skb_queue_tail(&rx_edma->rx_buffers, skb);
744 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
745 struct ath_rx_status *rs,
746 enum ath9k_rx_qtype qtype)
748 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
752 while (ath_edma_get_buffers(sc, qtype));
753 skb = __skb_dequeue(&rx_edma->rx_buffers);
757 bf = SKB_CB_ATHBUF(skb);
758 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
762 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
763 struct ath_rx_status *rs)
765 struct ath_hw *ah = sc->sc_ah;
766 struct ath_common *common = ath9k_hw_common(ah);
771 if (list_empty(&sc->rx.rxbuf)) {
772 sc->rx.rxlink = NULL;
776 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
780 * Must provide the virtual address of the current
781 * descriptor, the physical address, and the virtual
782 * address of the next descriptor in the h/w chain.
783 * This allows the HAL to look ahead to see if the
784 * hardware is done with a descriptor by checking the
785 * done bit in the following descriptor and the address
786 * of the current descriptor the DMA engine is working
787 * on. All this is necessary because of our use of
788 * a self-linked list to avoid rx overruns.
790 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
791 if (ret == -EINPROGRESS) {
792 struct ath_rx_status trs;
794 struct ath_desc *tds;
796 memset(&trs, 0, sizeof(trs));
797 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
798 sc->rx.rxlink = NULL;
802 tbf = list_entry(bf->list.next, struct ath_buf, list);
805 * On some hardware the descriptor status words could
806 * get corrupted, including the done bit. Because of
807 * this, check if the next descriptor's done bit is
810 * If the next descriptor's done bit is set, the current
811 * descriptor has been corrupted. Force s/w to discard
812 * this descriptor and continue...
816 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
817 if (ret == -EINPROGRESS)
825 * Synchronize the DMA transfer with CPU before
826 * 1. accessing the frame
827 * 2. requeueing the same buffer to h/w
829 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
836 /* Assumes you've already done the endian to CPU conversion */
837 static bool ath9k_rx_accept(struct ath_common *common,
838 struct ieee80211_hdr *hdr,
839 struct ieee80211_rx_status *rxs,
840 struct ath_rx_status *rx_stats,
843 #define is_mc_or_valid_tkip_keyix ((is_mc || \
844 (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
845 test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
847 struct ath_hw *ah = common->ah;
849 u8 rx_status_len = ah->caps.rx_status_len;
851 fc = hdr->frame_control;
853 if (!rx_stats->rs_datalen)
856 * rs_status follows rs_datalen so if rs_datalen is too large
857 * we can take a hint that hardware corrupted it, so ignore
860 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
864 * rs_more indicates chained descriptors which can be used
865 * to link buffers together for a sort of scatter-gather
867 * reject the frame, we don't support scatter-gather yet and
868 * the frame is probably corrupt anyway
870 if (rx_stats->rs_more)
874 * The rx_stats->rs_status will not be set until the end of the
875 * chained descriptors so it can be ignored if rs_more is set. The
876 * rs_more will be false at the last element of the chained
879 if (rx_stats->rs_status != 0) {
880 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
881 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
882 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
885 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
886 *decrypt_error = true;
887 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
890 * The MIC error bit is only valid if the frame
891 * is not a control frame or fragment, and it was
892 * decrypted using a valid TKIP key.
894 is_mc = !!is_multicast_ether_addr(hdr->addr1);
896 if (!ieee80211_is_ctl(fc) &&
897 !ieee80211_has_morefrags(fc) &&
898 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
899 is_mc_or_valid_tkip_keyix)
900 rxs->flag |= RX_FLAG_MMIC_ERROR;
902 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
905 * Reject error frames with the exception of
906 * decryption and MIC failures. For monitor mode,
907 * we also ignore the CRC error.
909 if (ah->is_monitoring) {
910 if (rx_stats->rs_status &
911 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
915 if (rx_stats->rs_status &
916 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
924 static int ath9k_process_rate(struct ath_common *common,
925 struct ieee80211_hw *hw,
926 struct ath_rx_status *rx_stats,
927 struct ieee80211_rx_status *rxs)
929 struct ieee80211_supported_band *sband;
930 enum ieee80211_band band;
933 band = hw->conf.channel->band;
934 sband = hw->wiphy->bands[band];
936 if (rx_stats->rs_rate & 0x80) {
938 rxs->flag |= RX_FLAG_HT;
939 if (rx_stats->rs_flags & ATH9K_RX_2040)
940 rxs->flag |= RX_FLAG_40MHZ;
941 if (rx_stats->rs_flags & ATH9K_RX_GI)
942 rxs->flag |= RX_FLAG_SHORT_GI;
943 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
947 for (i = 0; i < sband->n_bitrates; i++) {
948 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
952 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
953 rxs->flag |= RX_FLAG_SHORTPRE;
960 * No valid hardware bitrate found -- we should not get here
961 * because hardware has already validated this frame as OK.
963 ath_dbg(common, ATH_DBG_XMIT,
964 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
970 static void ath9k_process_rssi(struct ath_common *common,
971 struct ieee80211_hw *hw,
972 struct ieee80211_hdr *hdr,
973 struct ath_rx_status *rx_stats)
975 struct ath_wiphy *aphy = hw->priv;
976 struct ath_hw *ah = common->ah;
980 if (ah->opmode != NL80211_IFTYPE_STATION)
983 fc = hdr->frame_control;
984 if (!ieee80211_is_beacon(fc) ||
985 compare_ether_addr(hdr->addr3, common->curbssid))
988 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
989 ATH_RSSI_LPF(aphy->last_rssi, rx_stats->rs_rssi);
991 last_rssi = aphy->last_rssi;
992 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
993 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
994 ATH_RSSI_EP_MULTIPLIER);
995 if (rx_stats->rs_rssi < 0)
996 rx_stats->rs_rssi = 0;
998 /* Update Beacon RSSI, this is used by ANI. */
999 ah->stats.avgbrssi = rx_stats->rs_rssi;
1003 * For Decrypt or Demic errors, we only mark packet status here and always push
1004 * up the frame up to let mac80211 handle the actual error case, be it no
1005 * decryption key or real decryption error. This let us keep statistics there.
1007 static int ath9k_rx_skb_preprocess(struct ath_common *common,
1008 struct ieee80211_hw *hw,
1009 struct ieee80211_hdr *hdr,
1010 struct ath_rx_status *rx_stats,
1011 struct ieee80211_rx_status *rx_status,
1012 bool *decrypt_error)
1014 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1017 * everything but the rate is checked here, the rate check is done
1018 * separately to avoid doing two lookups for a rate for each frame.
1020 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1023 ath9k_process_rssi(common, hw, hdr, rx_stats);
1025 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1028 rx_status->band = hw->conf.channel->band;
1029 rx_status->freq = hw->conf.channel->center_freq;
1030 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1031 rx_status->antenna = rx_stats->rs_antenna;
1032 rx_status->flag |= RX_FLAG_TSFT;
1037 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1038 struct sk_buff *skb,
1039 struct ath_rx_status *rx_stats,
1040 struct ieee80211_rx_status *rxs,
1043 struct ath_hw *ah = common->ah;
1044 struct ieee80211_hdr *hdr;
1045 int hdrlen, padpos, padsize;
1049 /* see if any padding is done by the hw and remove it */
1050 hdr = (struct ieee80211_hdr *) skb->data;
1051 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1052 fc = hdr->frame_control;
1053 padpos = ath9k_cmn_padpos(hdr->frame_control);
1055 /* The MAC header is padded to have 32-bit boundary if the
1056 * packet payload is non-zero. The general calculation for
1057 * padsize would take into account odd header lengths:
1058 * padsize = (4 - padpos % 4) % 4; However, since only
1059 * even-length headers are used, padding can only be 0 or 2
1060 * bytes and we can optimize this a bit. In addition, we must
1061 * not try to remove padding from short control frames that do
1062 * not have payload. */
1063 padsize = padpos & 3;
1064 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1065 memmove(skb->data + padsize, skb->data, padpos);
1066 skb_pull(skb, padsize);
1069 keyix = rx_stats->rs_keyix;
1071 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1072 ieee80211_has_protected(fc)) {
1073 rxs->flag |= RX_FLAG_DECRYPTED;
1074 } else if (ieee80211_has_protected(fc)
1075 && !decrypt_error && skb->len >= hdrlen + 4) {
1076 keyix = skb->data[hdrlen + 3] >> 6;
1078 if (test_bit(keyix, common->keymap))
1079 rxs->flag |= RX_FLAG_DECRYPTED;
1081 if (ah->sw_mgmt_crypto &&
1082 (rxs->flag & RX_FLAG_DECRYPTED) &&
1083 ieee80211_is_mgmt(fc))
1084 /* Use software decrypt for management frames. */
1085 rxs->flag &= ~RX_FLAG_DECRYPTED;
1088 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1089 struct ath_hw_antcomb_conf ant_conf,
1092 antcomb->quick_scan_cnt = 0;
1094 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1095 antcomb->rssi_lna2 = main_rssi_avg;
1096 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1097 antcomb->rssi_lna1 = main_rssi_avg;
1099 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1100 case (0x10): /* LNA2 A-B */
1101 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1102 antcomb->first_quick_scan_conf =
1103 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1104 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1106 case (0x20): /* LNA1 A-B */
1107 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1108 antcomb->first_quick_scan_conf =
1109 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1110 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1112 case (0x21): /* LNA1 LNA2 */
1113 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1114 antcomb->first_quick_scan_conf =
1115 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1116 antcomb->second_quick_scan_conf =
1117 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1119 case (0x12): /* LNA2 LNA1 */
1120 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1121 antcomb->first_quick_scan_conf =
1122 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1123 antcomb->second_quick_scan_conf =
1124 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1126 case (0x13): /* LNA2 A+B */
1127 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1128 antcomb->first_quick_scan_conf =
1129 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1130 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1132 case (0x23): /* LNA1 A+B */
1133 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1134 antcomb->first_quick_scan_conf =
1135 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1136 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1143 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1144 struct ath_hw_antcomb_conf *div_ant_conf,
1145 int main_rssi_avg, int alt_rssi_avg,
1149 switch (antcomb->quick_scan_cnt) {
1151 /* set alt to main, and alt to first conf */
1152 div_ant_conf->main_lna_conf = antcomb->main_conf;
1153 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1156 /* set alt to main, and alt to first conf */
1157 div_ant_conf->main_lna_conf = antcomb->main_conf;
1158 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1159 antcomb->rssi_first = main_rssi_avg;
1160 antcomb->rssi_second = alt_rssi_avg;
1162 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1164 if (ath_is_alt_ant_ratio_better(alt_ratio,
1165 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1166 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1167 main_rssi_avg, alt_rssi_avg,
1168 antcomb->total_pkt_count))
1169 antcomb->first_ratio = true;
1171 antcomb->first_ratio = false;
1172 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1173 if (ath_is_alt_ant_ratio_better(alt_ratio,
1174 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1175 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1176 main_rssi_avg, alt_rssi_avg,
1177 antcomb->total_pkt_count))
1178 antcomb->first_ratio = true;
1180 antcomb->first_ratio = false;
1182 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1183 (alt_rssi_avg > main_rssi_avg +
1184 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1185 (alt_rssi_avg > main_rssi_avg)) &&
1186 (antcomb->total_pkt_count > 50))
1187 antcomb->first_ratio = true;
1189 antcomb->first_ratio = false;
1193 antcomb->alt_good = false;
1194 antcomb->scan_not_start = false;
1195 antcomb->scan = false;
1196 antcomb->rssi_first = main_rssi_avg;
1197 antcomb->rssi_third = alt_rssi_avg;
1199 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1200 antcomb->rssi_lna1 = alt_rssi_avg;
1201 else if (antcomb->second_quick_scan_conf ==
1202 ATH_ANT_DIV_COMB_LNA2)
1203 antcomb->rssi_lna2 = alt_rssi_avg;
1204 else if (antcomb->second_quick_scan_conf ==
1205 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1206 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1207 antcomb->rssi_lna2 = main_rssi_avg;
1208 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1209 antcomb->rssi_lna1 = main_rssi_avg;
1212 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1213 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1214 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1216 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1218 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1219 if (ath_is_alt_ant_ratio_better(alt_ratio,
1220 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1221 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1222 main_rssi_avg, alt_rssi_avg,
1223 antcomb->total_pkt_count))
1224 antcomb->second_ratio = true;
1226 antcomb->second_ratio = false;
1227 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1228 if (ath_is_alt_ant_ratio_better(alt_ratio,
1229 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1230 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1231 main_rssi_avg, alt_rssi_avg,
1232 antcomb->total_pkt_count))
1233 antcomb->second_ratio = true;
1235 antcomb->second_ratio = false;
1237 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1238 (alt_rssi_avg > main_rssi_avg +
1239 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1240 (alt_rssi_avg > main_rssi_avg)) &&
1241 (antcomb->total_pkt_count > 50))
1242 antcomb->second_ratio = true;
1244 antcomb->second_ratio = false;
1247 /* set alt to the conf with maximun ratio */
1248 if (antcomb->first_ratio && antcomb->second_ratio) {
1249 if (antcomb->rssi_second > antcomb->rssi_third) {
1251 if ((antcomb->first_quick_scan_conf ==
1252 ATH_ANT_DIV_COMB_LNA1) ||
1253 (antcomb->first_quick_scan_conf ==
1254 ATH_ANT_DIV_COMB_LNA2))
1255 /* Set alt LNA1 or LNA2*/
1256 if (div_ant_conf->main_lna_conf ==
1257 ATH_ANT_DIV_COMB_LNA2)
1258 div_ant_conf->alt_lna_conf =
1259 ATH_ANT_DIV_COMB_LNA1;
1261 div_ant_conf->alt_lna_conf =
1262 ATH_ANT_DIV_COMB_LNA2;
1264 /* Set alt to A+B or A-B */
1265 div_ant_conf->alt_lna_conf =
1266 antcomb->first_quick_scan_conf;
1267 } else if ((antcomb->second_quick_scan_conf ==
1268 ATH_ANT_DIV_COMB_LNA1) ||
1269 (antcomb->second_quick_scan_conf ==
1270 ATH_ANT_DIV_COMB_LNA2)) {
1271 /* Set alt LNA1 or LNA2 */
1272 if (div_ant_conf->main_lna_conf ==
1273 ATH_ANT_DIV_COMB_LNA2)
1274 div_ant_conf->alt_lna_conf =
1275 ATH_ANT_DIV_COMB_LNA1;
1277 div_ant_conf->alt_lna_conf =
1278 ATH_ANT_DIV_COMB_LNA2;
1280 /* Set alt to A+B or A-B */
1281 div_ant_conf->alt_lna_conf =
1282 antcomb->second_quick_scan_conf;
1284 } else if (antcomb->first_ratio) {
1286 if ((antcomb->first_quick_scan_conf ==
1287 ATH_ANT_DIV_COMB_LNA1) ||
1288 (antcomb->first_quick_scan_conf ==
1289 ATH_ANT_DIV_COMB_LNA2))
1290 /* Set alt LNA1 or LNA2 */
1291 if (div_ant_conf->main_lna_conf ==
1292 ATH_ANT_DIV_COMB_LNA2)
1293 div_ant_conf->alt_lna_conf =
1294 ATH_ANT_DIV_COMB_LNA1;
1296 div_ant_conf->alt_lna_conf =
1297 ATH_ANT_DIV_COMB_LNA2;
1299 /* Set alt to A+B or A-B */
1300 div_ant_conf->alt_lna_conf =
1301 antcomb->first_quick_scan_conf;
1302 } else if (antcomb->second_ratio) {
1304 if ((antcomb->second_quick_scan_conf ==
1305 ATH_ANT_DIV_COMB_LNA1) ||
1306 (antcomb->second_quick_scan_conf ==
1307 ATH_ANT_DIV_COMB_LNA2))
1308 /* Set alt LNA1 or LNA2 */
1309 if (div_ant_conf->main_lna_conf ==
1310 ATH_ANT_DIV_COMB_LNA2)
1311 div_ant_conf->alt_lna_conf =
1312 ATH_ANT_DIV_COMB_LNA1;
1314 div_ant_conf->alt_lna_conf =
1315 ATH_ANT_DIV_COMB_LNA2;
1317 /* Set alt to A+B or A-B */
1318 div_ant_conf->alt_lna_conf =
1319 antcomb->second_quick_scan_conf;
1321 /* main is largest */
1322 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1323 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1324 /* Set alt LNA1 or LNA2 */
1325 if (div_ant_conf->main_lna_conf ==
1326 ATH_ANT_DIV_COMB_LNA2)
1327 div_ant_conf->alt_lna_conf =
1328 ATH_ANT_DIV_COMB_LNA1;
1330 div_ant_conf->alt_lna_conf =
1331 ATH_ANT_DIV_COMB_LNA2;
1333 /* Set alt to A+B or A-B */
1334 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1342 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1344 /* Adjust the fast_div_bias based on main and alt lna conf */
1345 switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1346 case (0x01): /* A-B LNA2 */
1347 ant_conf->fast_div_bias = 0x3b;
1349 case (0x02): /* A-B LNA1 */
1350 ant_conf->fast_div_bias = 0x3d;
1352 case (0x03): /* A-B A+B */
1353 ant_conf->fast_div_bias = 0x1;
1355 case (0x10): /* LNA2 A-B */
1356 ant_conf->fast_div_bias = 0x7;
1358 case (0x12): /* LNA2 LNA1 */
1359 ant_conf->fast_div_bias = 0x2;
1361 case (0x13): /* LNA2 A+B */
1362 ant_conf->fast_div_bias = 0x7;
1364 case (0x20): /* LNA1 A-B */
1365 ant_conf->fast_div_bias = 0x6;
1367 case (0x21): /* LNA1 LNA2 */
1368 ant_conf->fast_div_bias = 0x0;
1370 case (0x23): /* LNA1 A+B */
1371 ant_conf->fast_div_bias = 0x6;
1373 case (0x30): /* A+B A-B */
1374 ant_conf->fast_div_bias = 0x1;
1376 case (0x31): /* A+B LNA2 */
1377 ant_conf->fast_div_bias = 0x3b;
1379 case (0x32): /* A+B LNA1 */
1380 ant_conf->fast_div_bias = 0x3d;
1387 /* Antenna diversity and combining */
1388 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1390 struct ath_hw_antcomb_conf div_ant_conf;
1391 struct ath_ant_comb *antcomb = &sc->ant_comb;
1392 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1393 int curr_main_set, curr_bias;
1394 int main_rssi = rs->rs_rssi_ctl0;
1395 int alt_rssi = rs->rs_rssi_ctl1;
1396 int rx_ant_conf, main_ant_conf;
1397 bool short_scan = false;
1399 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1401 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1404 /* Record packet only when alt_rssi is positive */
1406 antcomb->total_pkt_count++;
1407 antcomb->main_total_rssi += main_rssi;
1408 antcomb->alt_total_rssi += alt_rssi;
1409 if (main_ant_conf == rx_ant_conf)
1410 antcomb->main_recv_cnt++;
1412 antcomb->alt_recv_cnt++;
1415 /* Short scan check */
1416 if (antcomb->scan && antcomb->alt_good) {
1417 if (time_after(jiffies, antcomb->scan_start_time +
1418 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1421 if (antcomb->total_pkt_count ==
1422 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1423 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1424 antcomb->total_pkt_count);
1425 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1430 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1431 rs->rs_moreaggr) && !short_scan)
1434 if (antcomb->total_pkt_count) {
1435 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1436 antcomb->total_pkt_count);
1437 main_rssi_avg = (antcomb->main_total_rssi /
1438 antcomb->total_pkt_count);
1439 alt_rssi_avg = (antcomb->alt_total_rssi /
1440 antcomb->total_pkt_count);
1444 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1445 curr_alt_set = div_ant_conf.alt_lna_conf;
1446 curr_main_set = div_ant_conf.main_lna_conf;
1447 curr_bias = div_ant_conf.fast_div_bias;
1451 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1452 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1453 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1455 antcomb->alt_good = true;
1457 antcomb->alt_good = false;
1461 antcomb->scan = true;
1462 antcomb->scan_not_start = true;
1465 if (!antcomb->scan) {
1466 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1467 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1468 /* Switch main and alt LNA */
1469 div_ant_conf.main_lna_conf =
1470 ATH_ANT_DIV_COMB_LNA2;
1471 div_ant_conf.alt_lna_conf =
1472 ATH_ANT_DIV_COMB_LNA1;
1473 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1474 div_ant_conf.main_lna_conf =
1475 ATH_ANT_DIV_COMB_LNA1;
1476 div_ant_conf.alt_lna_conf =
1477 ATH_ANT_DIV_COMB_LNA2;
1481 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1482 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1483 /* Set alt to another LNA */
1484 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1485 div_ant_conf.alt_lna_conf =
1486 ATH_ANT_DIV_COMB_LNA1;
1487 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1488 div_ant_conf.alt_lna_conf =
1489 ATH_ANT_DIV_COMB_LNA2;
1494 if ((alt_rssi_avg < (main_rssi_avg +
1495 ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1499 if (!antcomb->scan_not_start) {
1500 switch (curr_alt_set) {
1501 case ATH_ANT_DIV_COMB_LNA2:
1502 antcomb->rssi_lna2 = alt_rssi_avg;
1503 antcomb->rssi_lna1 = main_rssi_avg;
1504 antcomb->scan = true;
1506 div_ant_conf.main_lna_conf =
1507 ATH_ANT_DIV_COMB_LNA1;
1508 div_ant_conf.alt_lna_conf =
1509 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1511 case ATH_ANT_DIV_COMB_LNA1:
1512 antcomb->rssi_lna1 = alt_rssi_avg;
1513 antcomb->rssi_lna2 = main_rssi_avg;
1514 antcomb->scan = true;
1516 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1517 div_ant_conf.alt_lna_conf =
1518 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1520 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1521 antcomb->rssi_add = alt_rssi_avg;
1522 antcomb->scan = true;
1524 div_ant_conf.alt_lna_conf =
1525 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1527 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1528 antcomb->rssi_sub = alt_rssi_avg;
1529 antcomb->scan = false;
1530 if (antcomb->rssi_lna2 >
1531 (antcomb->rssi_lna1 +
1532 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1533 /* use LNA2 as main LNA */
1534 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1535 (antcomb->rssi_add > antcomb->rssi_sub)) {
1537 div_ant_conf.main_lna_conf =
1538 ATH_ANT_DIV_COMB_LNA2;
1539 div_ant_conf.alt_lna_conf =
1540 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1541 } else if (antcomb->rssi_sub >
1542 antcomb->rssi_lna1) {
1544 div_ant_conf.main_lna_conf =
1545 ATH_ANT_DIV_COMB_LNA2;
1546 div_ant_conf.alt_lna_conf =
1547 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1550 div_ant_conf.main_lna_conf =
1551 ATH_ANT_DIV_COMB_LNA2;
1552 div_ant_conf.alt_lna_conf =
1553 ATH_ANT_DIV_COMB_LNA1;
1556 /* use LNA1 as main LNA */
1557 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1558 (antcomb->rssi_add > antcomb->rssi_sub)) {
1560 div_ant_conf.main_lna_conf =
1561 ATH_ANT_DIV_COMB_LNA1;
1562 div_ant_conf.alt_lna_conf =
1563 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1564 } else if (antcomb->rssi_sub >
1565 antcomb->rssi_lna1) {
1567 div_ant_conf.main_lna_conf =
1568 ATH_ANT_DIV_COMB_LNA1;
1569 div_ant_conf.alt_lna_conf =
1570 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1573 div_ant_conf.main_lna_conf =
1574 ATH_ANT_DIV_COMB_LNA1;
1575 div_ant_conf.alt_lna_conf =
1576 ATH_ANT_DIV_COMB_LNA2;
1584 if (!antcomb->alt_good) {
1585 antcomb->scan_not_start = false;
1586 /* Set alt to another LNA */
1587 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1588 div_ant_conf.main_lna_conf =
1589 ATH_ANT_DIV_COMB_LNA2;
1590 div_ant_conf.alt_lna_conf =
1591 ATH_ANT_DIV_COMB_LNA1;
1592 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1593 div_ant_conf.main_lna_conf =
1594 ATH_ANT_DIV_COMB_LNA1;
1595 div_ant_conf.alt_lna_conf =
1596 ATH_ANT_DIV_COMB_LNA2;
1602 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1603 main_rssi_avg, alt_rssi_avg,
1606 antcomb->quick_scan_cnt++;
1609 ath_ant_div_conf_fast_divbias(&div_ant_conf);
1611 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1613 antcomb->scan_start_time = jiffies;
1614 antcomb->total_pkt_count = 0;
1615 antcomb->main_total_rssi = 0;
1616 antcomb->alt_total_rssi = 0;
1617 antcomb->main_recv_cnt = 0;
1618 antcomb->alt_recv_cnt = 0;
1621 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1624 struct sk_buff *skb = NULL, *requeue_skb;
1625 struct ieee80211_rx_status *rxs;
1626 struct ath_hw *ah = sc->sc_ah;
1627 struct ath_common *common = ath9k_hw_common(ah);
1629 * The hw can technically differ from common->hw when using ath9k
1630 * virtual wiphy so to account for that we iterate over the active
1631 * wiphys and find the appropriate wiphy and therefore hw.
1633 struct ieee80211_hw *hw = NULL;
1634 struct ieee80211_hdr *hdr;
1636 bool decrypt_error = false;
1637 struct ath_rx_status rs;
1638 enum ath9k_rx_qtype qtype;
1639 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1641 u8 rx_status_len = ah->caps.rx_status_len;
1644 unsigned long flags;
1647 dma_type = DMA_BIDIRECTIONAL;
1649 dma_type = DMA_FROM_DEVICE;
1651 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1652 spin_lock_bh(&sc->rx.rxbuflock);
1654 tsf = ath9k_hw_gettsf64(ah);
1655 tsf_lower = tsf & 0xffffffff;
1658 /* If handling rx interrupt and flush is in progress => exit */
1659 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1662 memset(&rs, 0, sizeof(rs));
1664 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1666 bf = ath_get_next_rx_buf(sc, &rs);
1675 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
1676 rxs = IEEE80211_SKB_RXCB(skb);
1678 hw = ath_get_virt_hw(sc, hdr);
1680 ath_debug_stat_rx(sc, &rs);
1683 * If we're asked to flush receive queue, directly
1684 * chain it back at the queue without processing it.
1689 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1690 rxs, &decrypt_error);
1694 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1695 if (rs.rs_tstamp > tsf_lower &&
1696 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1697 rxs->mactime -= 0x100000000ULL;
1699 if (rs.rs_tstamp < tsf_lower &&
1700 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1701 rxs->mactime += 0x100000000ULL;
1703 /* Ensure we always have an skb to requeue once we are done
1704 * processing the current buffer's skb */
1705 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1707 /* If there is no memory we ignore the current RX'd frame,
1708 * tell hardware it can give us a new frame using the old
1709 * skb and put it at the tail of the sc->rx.rxbuf list for
1714 /* Unmap the frame */
1715 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1719 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1720 if (ah->caps.rx_status_len)
1721 skb_pull(skb, ah->caps.rx_status_len);
1723 ath9k_rx_skb_postprocess(common, skb, &rs,
1724 rxs, decrypt_error);
1726 /* We will now give hardware our shiny new allocated skb */
1727 bf->bf_mpdu = requeue_skb;
1728 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1731 if (unlikely(dma_mapping_error(sc->dev,
1732 bf->bf_buf_addr))) {
1733 dev_kfree_skb_any(requeue_skb);
1735 bf->bf_buf_addr = 0;
1736 ath_err(common, "dma_mapping_error() on RX\n");
1737 ath_rx_send_to_mac80211(hw, sc, skb);
1742 * change the default rx antenna if rx diversity chooses the
1743 * other antenna 3 times in a row.
1745 if (sc->rx.defant != rs.rs_antenna) {
1746 if (++sc->rx.rxotherant >= 3)
1747 ath_setdefantenna(sc, rs.rs_antenna);
1749 sc->rx.rxotherant = 0;
1752 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1754 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1756 PS_WAIT_FOR_PSPOLL_DATA)) ||
1757 unlikely(ath9k_check_auto_sleep(sc)))
1759 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1761 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1762 ath_ant_comb_scan(sc, &rs);
1764 ath_rx_send_to_mac80211(hw, sc, skb);
1768 list_add_tail(&bf->list, &sc->rx.rxbuf);
1769 ath_rx_edma_buf_link(sc, qtype);
1771 list_move_tail(&bf->list, &sc->rx.rxbuf);
1772 ath_rx_buf_link(sc, bf);
1776 spin_unlock_bh(&sc->rx.rxbuflock);