drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj = intel_fb->obj;
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj = intel_fb->obj;
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj = intel_fb->obj;
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj = intel_fb->obj;
1388
1389         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_i915_gem_object *obj,
1437                            struct intel_ring_buffer *pipelined)
1438 {
1439         u32 alignment;
1440         int ret;
1441
1442         switch (obj->tiling_mode) {
1443         case I915_TILING_NONE:
1444                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1445                         alignment = 128 * 1024;
1446                 else if (INTEL_INFO(dev)->gen >= 4)
1447                         alignment = 4 * 1024;
1448                 else
1449                         alignment = 64 * 1024;
1450                 break;
1451         case I915_TILING_X:
1452                 /* pin() will align the object as required by fence */
1453                 alignment = 0;
1454                 break;
1455         case I915_TILING_Y:
1456                 /* FIXME: Is this true? */
1457                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1458                 return -EINVAL;
1459         default:
1460                 BUG();
1461         }
1462
1463         ret = i915_gem_object_pin(obj, alignment, true);
1464         if (ret)
1465                 return ret;
1466
1467         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1468         if (ret)
1469                 goto err_unpin;
1470
1471         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1472          * fence, whereas 965+ only requires a fence if using
1473          * framebuffer compression.  For simplicity, we always install
1474          * a fence as the cost is not that onerous.
1475          */
1476         if (obj->tiling_mode != I915_TILING_NONE) {
1477                 ret = i915_gem_object_get_fence(obj, pipelined, false);
1478                 if (ret)
1479                         goto err_unpin;
1480         }
1481
1482         return 0;
1483
1484 err_unpin:
1485         i915_gem_object_unpin(obj);
1486         return ret;
1487 }
1488
1489 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1490 static int
1491 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1492                            int x, int y, enum mode_set_atomic state)
1493 {
1494         struct drm_device *dev = crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1497         struct intel_framebuffer *intel_fb;
1498         struct drm_i915_gem_object *obj;
1499         int plane = intel_crtc->plane;
1500         unsigned long Start, Offset;
1501         u32 dspcntr;
1502         u32 reg;
1503
1504         switch (plane) {
1505         case 0:
1506         case 1:
1507                 break;
1508         default:
1509                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1510                 return -EINVAL;
1511         }
1512
1513         intel_fb = to_intel_framebuffer(fb);
1514         obj = intel_fb->obj;
1515
1516         reg = DSPCNTR(plane);
1517         dspcntr = I915_READ(reg);
1518         /* Mask out pixel format bits in case we change it */
1519         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1520         switch (fb->bits_per_pixel) {
1521         case 8:
1522                 dspcntr |= DISPPLANE_8BPP;
1523                 break;
1524         case 16:
1525                 if (fb->depth == 15)
1526                         dspcntr |= DISPPLANE_15_16BPP;
1527                 else
1528                         dspcntr |= DISPPLANE_16BPP;
1529                 break;
1530         case 24:
1531         case 32:
1532                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1533                 break;
1534         default:
1535                 DRM_ERROR("Unknown color depth\n");
1536                 return -EINVAL;
1537         }
1538         if (INTEL_INFO(dev)->gen >= 4) {
1539                 if (obj->tiling_mode != I915_TILING_NONE)
1540                         dspcntr |= DISPPLANE_TILED;
1541                 else
1542                         dspcntr &= ~DISPPLANE_TILED;
1543         }
1544
1545         if (HAS_PCH_SPLIT(dev))
1546                 /* must disable */
1547                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1548
1549         I915_WRITE(reg, dspcntr);
1550
1551         Start = obj->gtt_offset;
1552         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1553
1554         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1555                       Start, Offset, x, y, fb->pitch);
1556         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1557         if (INTEL_INFO(dev)->gen >= 4) {
1558                 I915_WRITE(DSPSURF(plane), Start);
1559                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1560                 I915_WRITE(DSPADDR(plane), Offset);
1561         } else
1562                 I915_WRITE(DSPADDR(plane), Start + Offset);
1563         POSTING_READ(reg);
1564
1565         intel_update_fbc(dev);
1566         intel_increase_pllclock(crtc);
1567
1568         return 0;
1569 }
1570
1571 static int
1572 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1573                     struct drm_framebuffer *old_fb)
1574 {
1575         struct drm_device *dev = crtc->dev;
1576         struct drm_i915_master_private *master_priv;
1577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1578         int ret;
1579
1580         /* no fb bound */
1581         if (!crtc->fb) {
1582                 DRM_DEBUG_KMS("No FB bound\n");
1583                 return 0;
1584         }
1585
1586         switch (intel_crtc->plane) {
1587         case 0:
1588         case 1:
1589                 break;
1590         default:
1591                 return -EINVAL;
1592         }
1593
1594         mutex_lock(&dev->struct_mutex);
1595         ret = intel_pin_and_fence_fb_obj(dev,
1596                                          to_intel_framebuffer(crtc->fb)->obj,
1597                                          NULL);
1598         if (ret != 0) {
1599                 mutex_unlock(&dev->struct_mutex);
1600                 return ret;
1601         }
1602
1603         if (old_fb) {
1604                 struct drm_i915_private *dev_priv = dev->dev_private;
1605                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1606
1607                 wait_event(dev_priv->pending_flip_queue,
1608                            atomic_read(&obj->pending_flip) == 0);
1609
1610                 /* Big Hammer, we also need to ensure that any pending
1611                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1612                  * current scanout is retired before unpinning the old
1613                  * framebuffer.
1614                  */
1615                 ret = i915_gem_object_flush_gpu(obj, false);
1616                 if (ret) {
1617                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1618                         mutex_unlock(&dev->struct_mutex);
1619                         return ret;
1620                 }
1621         }
1622
1623         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1624                                          LEAVE_ATOMIC_MODE_SET);
1625         if (ret) {
1626                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1627                 mutex_unlock(&dev->struct_mutex);
1628                 return ret;
1629         }
1630
1631         if (old_fb)
1632                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1633
1634         mutex_unlock(&dev->struct_mutex);
1635
1636         if (!dev->primary->master)
1637                 return 0;
1638
1639         master_priv = dev->primary->master->driver_priv;
1640         if (!master_priv->sarea_priv)
1641                 return 0;
1642
1643         if (intel_crtc->pipe) {
1644                 master_priv->sarea_priv->pipeB_x = x;
1645                 master_priv->sarea_priv->pipeB_y = y;
1646         } else {
1647                 master_priv->sarea_priv->pipeA_x = x;
1648                 master_priv->sarea_priv->pipeA_y = y;
1649         }
1650
1651         return 0;
1652 }
1653
1654 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1655 {
1656         struct drm_device *dev = crtc->dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         u32 dpa_ctl;
1659
1660         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1661         dpa_ctl = I915_READ(DP_A);
1662         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1663
1664         if (clock < 200000) {
1665                 u32 temp;
1666                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1667                 /* workaround for 160Mhz:
1668                    1) program 0x4600c bits 15:0 = 0x8124
1669                    2) program 0x46010 bit 0 = 1
1670                    3) program 0x46034 bit 24 = 1
1671                    4) program 0x64000 bit 14 = 1
1672                    */
1673                 temp = I915_READ(0x4600c);
1674                 temp &= 0xffff0000;
1675                 I915_WRITE(0x4600c, temp | 0x8124);
1676
1677                 temp = I915_READ(0x46010);
1678                 I915_WRITE(0x46010, temp | 1);
1679
1680                 temp = I915_READ(0x46034);
1681                 I915_WRITE(0x46034, temp | (1 << 24));
1682         } else {
1683                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1684         }
1685         I915_WRITE(DP_A, dpa_ctl);
1686
1687         POSTING_READ(DP_A);
1688         udelay(500);
1689 }
1690
1691 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1692 {
1693         struct drm_device *dev = crtc->dev;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1696         int pipe = intel_crtc->pipe;
1697         u32 reg, temp;
1698
1699         /* enable normal train */
1700         reg = FDI_TX_CTL(pipe);
1701         temp = I915_READ(reg);
1702         temp &= ~FDI_LINK_TRAIN_NONE;
1703         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1704         I915_WRITE(reg, temp);
1705
1706         reg = FDI_RX_CTL(pipe);
1707         temp = I915_READ(reg);
1708         if (HAS_PCH_CPT(dev)) {
1709                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1710                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1711         } else {
1712                 temp &= ~FDI_LINK_TRAIN_NONE;
1713                 temp |= FDI_LINK_TRAIN_NONE;
1714         }
1715         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1716
1717         /* wait one idle pattern time */
1718         POSTING_READ(reg);
1719         udelay(1000);
1720 }
1721
1722 /* The FDI link training functions for ILK/Ibexpeak. */
1723 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1724 {
1725         struct drm_device *dev = crtc->dev;
1726         struct drm_i915_private *dev_priv = dev->dev_private;
1727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1728         int pipe = intel_crtc->pipe;
1729         u32 reg, temp, tries;
1730
1731         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1732            for train result */
1733         reg = FDI_RX_IMR(pipe);
1734         temp = I915_READ(reg);
1735         temp &= ~FDI_RX_SYMBOL_LOCK;
1736         temp &= ~FDI_RX_BIT_LOCK;
1737         I915_WRITE(reg, temp);
1738         I915_READ(reg);
1739         udelay(150);
1740
1741         /* enable CPU FDI TX and PCH FDI RX */
1742         reg = FDI_TX_CTL(pipe);
1743         temp = I915_READ(reg);
1744         temp &= ~(7 << 19);
1745         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1746         temp &= ~FDI_LINK_TRAIN_NONE;
1747         temp |= FDI_LINK_TRAIN_PATTERN_1;
1748         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1749
1750         reg = FDI_RX_CTL(pipe);
1751         temp = I915_READ(reg);
1752         temp &= ~FDI_LINK_TRAIN_NONE;
1753         temp |= FDI_LINK_TRAIN_PATTERN_1;
1754         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1755
1756         POSTING_READ(reg);
1757         udelay(150);
1758
1759         /* Ironlake workaround, enable clock pointer after FDI enable*/
1760         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1761
1762         reg = FDI_RX_IIR(pipe);
1763         for (tries = 0; tries < 5; tries++) {
1764                 temp = I915_READ(reg);
1765                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1766
1767                 if ((temp & FDI_RX_BIT_LOCK)) {
1768                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1769                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1770                         break;
1771                 }
1772         }
1773         if (tries == 5)
1774                 DRM_ERROR("FDI train 1 fail!\n");
1775
1776         /* Train 2 */
1777         reg = FDI_TX_CTL(pipe);
1778         temp = I915_READ(reg);
1779         temp &= ~FDI_LINK_TRAIN_NONE;
1780         temp |= FDI_LINK_TRAIN_PATTERN_2;
1781         I915_WRITE(reg, temp);
1782
1783         reg = FDI_RX_CTL(pipe);
1784         temp = I915_READ(reg);
1785         temp &= ~FDI_LINK_TRAIN_NONE;
1786         temp |= FDI_LINK_TRAIN_PATTERN_2;
1787         I915_WRITE(reg, temp);
1788
1789         POSTING_READ(reg);
1790         udelay(150);
1791
1792         reg = FDI_RX_IIR(pipe);
1793         for (tries = 0; tries < 5; tries++) {
1794                 temp = I915_READ(reg);
1795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1796
1797                 if (temp & FDI_RX_SYMBOL_LOCK) {
1798                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1799                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1800                         break;
1801                 }
1802         }
1803         if (tries == 5)
1804                 DRM_ERROR("FDI train 2 fail!\n");
1805
1806         DRM_DEBUG_KMS("FDI train done\n");
1807
1808 }
1809
1810 static const int const snb_b_fdi_train_param [] = {
1811         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1812         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1813         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1814         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1815 };
1816
1817 /* The FDI link training functions for SNB/Cougarpoint. */
1818 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1819 {
1820         struct drm_device *dev = crtc->dev;
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823         int pipe = intel_crtc->pipe;
1824         u32 reg, temp, i;
1825
1826         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1827            for train result */
1828         reg = FDI_RX_IMR(pipe);
1829         temp = I915_READ(reg);
1830         temp &= ~FDI_RX_SYMBOL_LOCK;
1831         temp &= ~FDI_RX_BIT_LOCK;
1832         I915_WRITE(reg, temp);
1833
1834         POSTING_READ(reg);
1835         udelay(150);
1836
1837         /* enable CPU FDI TX and PCH FDI RX */
1838         reg = FDI_TX_CTL(pipe);
1839         temp = I915_READ(reg);
1840         temp &= ~(7 << 19);
1841         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1842         temp &= ~FDI_LINK_TRAIN_NONE;
1843         temp |= FDI_LINK_TRAIN_PATTERN_1;
1844         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1845         /* SNB-B */
1846         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1847         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1848
1849         reg = FDI_RX_CTL(pipe);
1850         temp = I915_READ(reg);
1851         if (HAS_PCH_CPT(dev)) {
1852                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1853                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1854         } else {
1855                 temp &= ~FDI_LINK_TRAIN_NONE;
1856                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1857         }
1858         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1859
1860         POSTING_READ(reg);
1861         udelay(150);
1862
1863         for (i = 0; i < 4; i++ ) {
1864                 reg = FDI_TX_CTL(pipe);
1865                 temp = I915_READ(reg);
1866                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1867                 temp |= snb_b_fdi_train_param[i];
1868                 I915_WRITE(reg, temp);
1869
1870                 POSTING_READ(reg);
1871                 udelay(500);
1872
1873                 reg = FDI_RX_IIR(pipe);
1874                 temp = I915_READ(reg);
1875                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1876
1877                 if (temp & FDI_RX_BIT_LOCK) {
1878                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1879                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1880                         break;
1881                 }
1882         }
1883         if (i == 4)
1884                 DRM_ERROR("FDI train 1 fail!\n");
1885
1886         /* Train 2 */
1887         reg = FDI_TX_CTL(pipe);
1888         temp = I915_READ(reg);
1889         temp &= ~FDI_LINK_TRAIN_NONE;
1890         temp |= FDI_LINK_TRAIN_PATTERN_2;
1891         if (IS_GEN6(dev)) {
1892                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1893                 /* SNB-B */
1894                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1895         }
1896         I915_WRITE(reg, temp);
1897
1898         reg = FDI_RX_CTL(pipe);
1899         temp = I915_READ(reg);
1900         if (HAS_PCH_CPT(dev)) {
1901                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1902                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1903         } else {
1904                 temp &= ~FDI_LINK_TRAIN_NONE;
1905                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1906         }
1907         I915_WRITE(reg, temp);
1908
1909         POSTING_READ(reg);
1910         udelay(150);
1911
1912         for (i = 0; i < 4; i++ ) {
1913                 reg = FDI_TX_CTL(pipe);
1914                 temp = I915_READ(reg);
1915                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1916                 temp |= snb_b_fdi_train_param[i];
1917                 I915_WRITE(reg, temp);
1918
1919                 POSTING_READ(reg);
1920                 udelay(500);
1921
1922                 reg = FDI_RX_IIR(pipe);
1923                 temp = I915_READ(reg);
1924                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1925
1926                 if (temp & FDI_RX_SYMBOL_LOCK) {
1927                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1928                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1929                         break;
1930                 }
1931         }
1932         if (i == 4)
1933                 DRM_ERROR("FDI train 2 fail!\n");
1934
1935         DRM_DEBUG_KMS("FDI train done.\n");
1936 }
1937
1938 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1939 {
1940         struct drm_device *dev = crtc->dev;
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1943         int pipe = intel_crtc->pipe;
1944         u32 reg, temp;
1945
1946         /* Write the TU size bits so error detection works */
1947         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1948                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1949
1950         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1951         reg = FDI_RX_CTL(pipe);
1952         temp = I915_READ(reg);
1953         temp &= ~((0x7 << 19) | (0x7 << 16));
1954         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1955         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1956         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1957
1958         POSTING_READ(reg);
1959         udelay(200);
1960
1961         /* Switch from Rawclk to PCDclk */
1962         temp = I915_READ(reg);
1963         I915_WRITE(reg, temp | FDI_PCDCLK);
1964
1965         POSTING_READ(reg);
1966         udelay(200);
1967
1968         /* Enable CPU FDI TX PLL, always on for Ironlake */
1969         reg = FDI_TX_CTL(pipe);
1970         temp = I915_READ(reg);
1971         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1972                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1973
1974                 POSTING_READ(reg);
1975                 udelay(100);
1976         }
1977 }
1978
1979 static void intel_flush_display_plane(struct drm_device *dev,
1980                                       int plane)
1981 {
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         u32 reg = DSPADDR(plane);
1984         I915_WRITE(reg, I915_READ(reg));
1985 }
1986
1987 /*
1988  * When we disable a pipe, we need to clear any pending scanline wait events
1989  * to avoid hanging the ring, which we assume we are waiting on.
1990  */
1991 static void intel_clear_scanline_wait(struct drm_device *dev)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         struct intel_ring_buffer *ring;
1995         u32 tmp;
1996
1997         if (IS_GEN2(dev))
1998                 /* Can't break the hang on i8xx */
1999                 return;
2000
2001         ring = &dev_priv->render_ring;
2002         tmp = I915_READ_CTL(ring);
2003         if (tmp & RING_WAIT)
2004                 I915_WRITE_CTL(ring, tmp);
2005 }
2006
2007 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2008 {
2009         struct drm_i915_gem_object *obj;
2010         struct drm_i915_private *dev_priv;
2011
2012         if (crtc->fb == NULL)
2013                 return;
2014
2015         obj = to_intel_framebuffer(crtc->fb)->obj;
2016         dev_priv = crtc->dev->dev_private;
2017         wait_event(dev_priv->pending_flip_queue,
2018                    atomic_read(&obj->pending_flip) == 0);
2019 }
2020
2021 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2022 {
2023         struct drm_device *dev = crtc->dev;
2024         struct drm_i915_private *dev_priv = dev->dev_private;
2025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2026         int pipe = intel_crtc->pipe;
2027         int plane = intel_crtc->plane;
2028         u32 reg, temp;
2029
2030         if (intel_crtc->active)
2031                 return;
2032
2033         intel_crtc->active = true;
2034         intel_update_watermarks(dev);
2035
2036         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2037                 temp = I915_READ(PCH_LVDS);
2038                 if ((temp & LVDS_PORT_EN) == 0)
2039                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2040         }
2041
2042         ironlake_fdi_enable(crtc);
2043
2044         /* Enable panel fitting for LVDS */
2045         if (dev_priv->pch_pf_size &&
2046             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2047                 /* Force use of hard-coded filter coefficients
2048                  * as some pre-programmed values are broken,
2049                  * e.g. x201.
2050                  */
2051                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2052                            PF_ENABLE | PF_FILTER_MED_3x3);
2053                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2054                            dev_priv->pch_pf_pos);
2055                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2056                            dev_priv->pch_pf_size);
2057         }
2058
2059         /* Enable CPU pipe */
2060         reg = PIPECONF(pipe);
2061         temp = I915_READ(reg);
2062         if ((temp & PIPECONF_ENABLE) == 0) {
2063                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2064                 POSTING_READ(reg);
2065                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2066         }
2067
2068         /* configure and enable CPU plane */
2069         reg = DSPCNTR(plane);
2070         temp = I915_READ(reg);
2071         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2072                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2073                 intel_flush_display_plane(dev, plane);
2074         }
2075
2076         /* For PCH output, training FDI link */
2077         if (IS_GEN6(dev))
2078                 gen6_fdi_link_train(crtc);
2079         else
2080                 ironlake_fdi_link_train(crtc);
2081
2082         /* enable PCH DPLL */
2083         reg = PCH_DPLL(pipe);
2084         temp = I915_READ(reg);
2085         if ((temp & DPLL_VCO_ENABLE) == 0) {
2086                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2087                 POSTING_READ(reg);
2088                 udelay(200);
2089         }
2090
2091         if (HAS_PCH_CPT(dev)) {
2092                 /* Be sure PCH DPLL SEL is set */
2093                 temp = I915_READ(PCH_DPLL_SEL);
2094                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2095                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2096                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2097                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2098                 I915_WRITE(PCH_DPLL_SEL, temp);
2099         }
2100
2101         /* set transcoder timing */
2102         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2103         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2104         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2105
2106         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2107         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2108         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2109
2110         intel_fdi_normal_train(crtc);
2111
2112         /* For PCH DP, enable TRANS_DP_CTL */
2113         if (HAS_PCH_CPT(dev) &&
2114             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2115                 reg = TRANS_DP_CTL(pipe);
2116                 temp = I915_READ(reg);
2117                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2118                           TRANS_DP_SYNC_MASK |
2119                           TRANS_DP_BPC_MASK);
2120                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2121                          TRANS_DP_ENH_FRAMING);
2122                 temp |= TRANS_DP_8BPC;
2123
2124                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2125                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2126                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2127                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2128
2129                 switch (intel_trans_dp_port_sel(crtc)) {
2130                 case PCH_DP_B:
2131                         temp |= TRANS_DP_PORT_SEL_B;
2132                         break;
2133                 case PCH_DP_C:
2134                         temp |= TRANS_DP_PORT_SEL_C;
2135                         break;
2136                 case PCH_DP_D:
2137                         temp |= TRANS_DP_PORT_SEL_D;
2138                         break;
2139                 default:
2140                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2141                         temp |= TRANS_DP_PORT_SEL_B;
2142                         break;
2143                 }
2144
2145                 I915_WRITE(reg, temp);
2146         }
2147
2148         /* enable PCH transcoder */
2149         reg = TRANSCONF(pipe);
2150         temp = I915_READ(reg);
2151         /*
2152          * make the BPC in transcoder be consistent with
2153          * that in pipeconf reg.
2154          */
2155         temp &= ~PIPE_BPC_MASK;
2156         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2157         I915_WRITE(reg, temp | TRANS_ENABLE);
2158         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2159                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2160
2161         intel_crtc_load_lut(crtc);
2162         intel_update_fbc(dev);
2163         intel_crtc_update_cursor(crtc, true);
2164 }
2165
2166 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2167 {
2168         struct drm_device *dev = crtc->dev;
2169         struct drm_i915_private *dev_priv = dev->dev_private;
2170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171         int pipe = intel_crtc->pipe;
2172         int plane = intel_crtc->plane;
2173         u32 reg, temp;
2174
2175         if (!intel_crtc->active)
2176                 return;
2177
2178         intel_crtc_wait_for_pending_flips(crtc);
2179         drm_vblank_off(dev, pipe);
2180         intel_crtc_update_cursor(crtc, false);
2181
2182         /* Disable display plane */
2183         reg = DSPCNTR(plane);
2184         temp = I915_READ(reg);
2185         if (temp & DISPLAY_PLANE_ENABLE) {
2186                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2187                 intel_flush_display_plane(dev, plane);
2188         }
2189
2190         if (dev_priv->cfb_plane == plane &&
2191             dev_priv->display.disable_fbc)
2192                 dev_priv->display.disable_fbc(dev);
2193
2194         /* disable cpu pipe, disable after all planes disabled */
2195         reg = PIPECONF(pipe);
2196         temp = I915_READ(reg);
2197         if (temp & PIPECONF_ENABLE) {
2198                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2199                 POSTING_READ(reg);
2200                 /* wait for cpu pipe off, pipe state */
2201                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2202         }
2203
2204         /* Disable PF */
2205         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2206         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2207
2208         /* disable CPU FDI tx and PCH FDI rx */
2209         reg = FDI_TX_CTL(pipe);
2210         temp = I915_READ(reg);
2211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2212         POSTING_READ(reg);
2213
2214         reg = FDI_RX_CTL(pipe);
2215         temp = I915_READ(reg);
2216         temp &= ~(0x7 << 16);
2217         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2219
2220         POSTING_READ(reg);
2221         udelay(100);
2222
2223         /* Ironlake workaround, disable clock pointer after downing FDI */
2224         if (HAS_PCH_IBX(dev))
2225                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2226                            I915_READ(FDI_RX_CHICKEN(pipe) &
2227                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2228
2229         /* still set train pattern 1 */
2230         reg = FDI_TX_CTL(pipe);
2231         temp = I915_READ(reg);
2232         temp &= ~FDI_LINK_TRAIN_NONE;
2233         temp |= FDI_LINK_TRAIN_PATTERN_1;
2234         I915_WRITE(reg, temp);
2235
2236         reg = FDI_RX_CTL(pipe);
2237         temp = I915_READ(reg);
2238         if (HAS_PCH_CPT(dev)) {
2239                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2240                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2241         } else {
2242                 temp &= ~FDI_LINK_TRAIN_NONE;
2243                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2244         }
2245         /* BPC in FDI rx is consistent with that in PIPECONF */
2246         temp &= ~(0x07 << 16);
2247         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2248         I915_WRITE(reg, temp);
2249
2250         POSTING_READ(reg);
2251         udelay(100);
2252
2253         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2254                 temp = I915_READ(PCH_LVDS);
2255                 if (temp & LVDS_PORT_EN) {
2256                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2257                         POSTING_READ(PCH_LVDS);
2258                         udelay(100);
2259                 }
2260         }
2261
2262         /* disable PCH transcoder */
2263         reg = TRANSCONF(plane);
2264         temp = I915_READ(reg);
2265         if (temp & TRANS_ENABLE) {
2266                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2267                 /* wait for PCH transcoder off, transcoder state */
2268                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2269                         DRM_ERROR("failed to disable transcoder\n");
2270         }
2271
2272         if (HAS_PCH_CPT(dev)) {
2273                 /* disable TRANS_DP_CTL */
2274                 reg = TRANS_DP_CTL(pipe);
2275                 temp = I915_READ(reg);
2276                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2277                 I915_WRITE(reg, temp);
2278
2279                 /* disable DPLL_SEL */
2280                 temp = I915_READ(PCH_DPLL_SEL);
2281                 if (pipe == 0)
2282                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2283                 else
2284                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2285                 I915_WRITE(PCH_DPLL_SEL, temp);
2286         }
2287
2288         /* disable PCH DPLL */
2289         reg = PCH_DPLL(pipe);
2290         temp = I915_READ(reg);
2291         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2292
2293         /* Switch from PCDclk to Rawclk */
2294         reg = FDI_RX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2297
2298         /* Disable CPU FDI TX PLL */
2299         reg = FDI_TX_CTL(pipe);
2300         temp = I915_READ(reg);
2301         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2302
2303         POSTING_READ(reg);
2304         udelay(100);
2305
2306         reg = FDI_RX_CTL(pipe);
2307         temp = I915_READ(reg);
2308         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2309
2310         /* Wait for the clocks to turn off. */
2311         POSTING_READ(reg);
2312         udelay(100);
2313
2314         intel_crtc->active = false;
2315         intel_update_watermarks(dev);
2316         intel_update_fbc(dev);
2317         intel_clear_scanline_wait(dev);
2318 }
2319
2320 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2321 {
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         int plane = intel_crtc->plane;
2325
2326         /* XXX: When our outputs are all unaware of DPMS modes other than off
2327          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2328          */
2329         switch (mode) {
2330         case DRM_MODE_DPMS_ON:
2331         case DRM_MODE_DPMS_STANDBY:
2332         case DRM_MODE_DPMS_SUSPEND:
2333                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2334                 ironlake_crtc_enable(crtc);
2335                 break;
2336
2337         case DRM_MODE_DPMS_OFF:
2338                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2339                 ironlake_crtc_disable(crtc);
2340                 break;
2341         }
2342 }
2343
2344 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2345 {
2346         if (!enable && intel_crtc->overlay) {
2347                 struct drm_device *dev = intel_crtc->base.dev;
2348
2349                 mutex_lock(&dev->struct_mutex);
2350                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2351                 mutex_unlock(&dev->struct_mutex);
2352         }
2353
2354         /* Let userspace switch the overlay on again. In most cases userspace
2355          * has to recompute where to put it anyway.
2356          */
2357 }
2358
2359 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2360 {
2361         struct drm_device *dev = crtc->dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364         int pipe = intel_crtc->pipe;
2365         int plane = intel_crtc->plane;
2366         u32 reg, temp;
2367
2368         if (intel_crtc->active)
2369                 return;
2370
2371         intel_crtc->active = true;
2372         intel_update_watermarks(dev);
2373
2374         /* Enable the DPLL */
2375         reg = DPLL(pipe);
2376         temp = I915_READ(reg);
2377         if ((temp & DPLL_VCO_ENABLE) == 0) {
2378                 I915_WRITE(reg, temp);
2379
2380                 /* Wait for the clocks to stabilize. */
2381                 POSTING_READ(reg);
2382                 udelay(150);
2383
2384                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2385
2386                 /* Wait for the clocks to stabilize. */
2387                 POSTING_READ(reg);
2388                 udelay(150);
2389
2390                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2391
2392                 /* Wait for the clocks to stabilize. */
2393                 POSTING_READ(reg);
2394                 udelay(150);
2395         }
2396
2397         /* Enable the pipe */
2398         reg = PIPECONF(pipe);
2399         temp = I915_READ(reg);
2400         if ((temp & PIPECONF_ENABLE) == 0)
2401                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2402
2403         /* Enable the plane */
2404         reg = DSPCNTR(plane);
2405         temp = I915_READ(reg);
2406         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2407                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2408                 intel_flush_display_plane(dev, plane);
2409         }
2410
2411         intel_crtc_load_lut(crtc);
2412         intel_update_fbc(dev);
2413
2414         /* Give the overlay scaler a chance to enable if it's on this pipe */
2415         intel_crtc_dpms_overlay(intel_crtc, true);
2416         intel_crtc_update_cursor(crtc, true);
2417 }
2418
2419 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2420 {
2421         struct drm_device *dev = crtc->dev;
2422         struct drm_i915_private *dev_priv = dev->dev_private;
2423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2424         int pipe = intel_crtc->pipe;
2425         int plane = intel_crtc->plane;
2426         u32 reg, temp;
2427
2428         if (!intel_crtc->active)
2429                 return;
2430
2431         /* Give the overlay scaler a chance to disable if it's on this pipe */
2432         intel_crtc_wait_for_pending_flips(crtc);
2433         drm_vblank_off(dev, pipe);
2434         intel_crtc_dpms_overlay(intel_crtc, false);
2435         intel_crtc_update_cursor(crtc, false);
2436
2437         if (dev_priv->cfb_plane == plane &&
2438             dev_priv->display.disable_fbc)
2439                 dev_priv->display.disable_fbc(dev);
2440
2441         /* Disable display plane */
2442         reg = DSPCNTR(plane);
2443         temp = I915_READ(reg);
2444         if (temp & DISPLAY_PLANE_ENABLE) {
2445                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2446                 /* Flush the plane changes */
2447                 intel_flush_display_plane(dev, plane);
2448
2449                 /* Wait for vblank for the disable to take effect */
2450                 if (IS_GEN2(dev))
2451                         intel_wait_for_vblank(dev, pipe);
2452         }
2453
2454         /* Don't disable pipe A or pipe A PLLs if needed */
2455         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2456                 goto done;
2457
2458         /* Next, disable display pipes */
2459         reg = PIPECONF(pipe);
2460         temp = I915_READ(reg);
2461         if (temp & PIPECONF_ENABLE) {
2462                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2463
2464                 /* Wait for the pipe to turn off */
2465                 POSTING_READ(reg);
2466                 intel_wait_for_pipe_off(dev, pipe);
2467         }
2468
2469         reg = DPLL(pipe);
2470         temp = I915_READ(reg);
2471         if (temp & DPLL_VCO_ENABLE) {
2472                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2473
2474                 /* Wait for the clocks to turn off. */
2475                 POSTING_READ(reg);
2476                 udelay(150);
2477         }
2478
2479 done:
2480         intel_crtc->active = false;
2481         intel_update_fbc(dev);
2482         intel_update_watermarks(dev);
2483         intel_clear_scanline_wait(dev);
2484 }
2485
2486 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2487 {
2488         /* XXX: When our outputs are all unaware of DPMS modes other than off
2489          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2490          */
2491         switch (mode) {
2492         case DRM_MODE_DPMS_ON:
2493         case DRM_MODE_DPMS_STANDBY:
2494         case DRM_MODE_DPMS_SUSPEND:
2495                 i9xx_crtc_enable(crtc);
2496                 break;
2497         case DRM_MODE_DPMS_OFF:
2498                 i9xx_crtc_disable(crtc);
2499                 break;
2500         }
2501 }
2502
2503 /**
2504  * Sets the power management mode of the pipe and plane.
2505  */
2506 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct drm_i915_master_private *master_priv;
2511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2512         int pipe = intel_crtc->pipe;
2513         bool enabled;
2514
2515         if (intel_crtc->dpms_mode == mode)
2516                 return;
2517
2518         intel_crtc->dpms_mode = mode;
2519
2520         dev_priv->display.dpms(crtc, mode);
2521
2522         if (!dev->primary->master)
2523                 return;
2524
2525         master_priv = dev->primary->master->driver_priv;
2526         if (!master_priv->sarea_priv)
2527                 return;
2528
2529         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2530
2531         switch (pipe) {
2532         case 0:
2533                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2534                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2535                 break;
2536         case 1:
2537                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2538                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2539                 break;
2540         default:
2541                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2542                 break;
2543         }
2544 }
2545
2546 static void intel_crtc_disable(struct drm_crtc *crtc)
2547 {
2548         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2549         struct drm_device *dev = crtc->dev;
2550
2551         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2552
2553         if (crtc->fb) {
2554                 mutex_lock(&dev->struct_mutex);
2555                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2556                 mutex_unlock(&dev->struct_mutex);
2557         }
2558 }
2559
2560 /* Prepare for a mode set.
2561  *
2562  * Note we could be a lot smarter here.  We need to figure out which outputs
2563  * will be enabled, which disabled (in short, how the config will changes)
2564  * and perform the minimum necessary steps to accomplish that, e.g. updating
2565  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2566  * panel fitting is in the proper state, etc.
2567  */
2568 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2569 {
2570         i9xx_crtc_disable(crtc);
2571 }
2572
2573 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2574 {
2575         i9xx_crtc_enable(crtc);
2576 }
2577
2578 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2579 {
2580         ironlake_crtc_disable(crtc);
2581 }
2582
2583 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2584 {
2585         ironlake_crtc_enable(crtc);
2586 }
2587
2588 void intel_encoder_prepare (struct drm_encoder *encoder)
2589 {
2590         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2591         /* lvds has its own version of prepare see intel_lvds_prepare */
2592         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2593 }
2594
2595 void intel_encoder_commit (struct drm_encoder *encoder)
2596 {
2597         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2598         /* lvds has its own version of commit see intel_lvds_commit */
2599         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2600 }
2601
2602 void intel_encoder_destroy(struct drm_encoder *encoder)
2603 {
2604         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2605
2606         drm_encoder_cleanup(encoder);
2607         kfree(intel_encoder);
2608 }
2609
2610 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2611                                   struct drm_display_mode *mode,
2612                                   struct drm_display_mode *adjusted_mode)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615
2616         if (HAS_PCH_SPLIT(dev)) {
2617                 /* FDI link clock is fixed at 2.7G */
2618                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2619                         return false;
2620         }
2621
2622         /* XXX some encoders set the crtcinfo, others don't.
2623          * Obviously we need some form of conflict resolution here...
2624          */
2625         if (adjusted_mode->crtc_htotal == 0)
2626                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2627
2628         return true;
2629 }
2630
2631 static int i945_get_display_clock_speed(struct drm_device *dev)
2632 {
2633         return 400000;
2634 }
2635
2636 static int i915_get_display_clock_speed(struct drm_device *dev)
2637 {
2638         return 333000;
2639 }
2640
2641 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2642 {
2643         return 200000;
2644 }
2645
2646 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2647 {
2648         u16 gcfgc = 0;
2649
2650         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2651
2652         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2653                 return 133000;
2654         else {
2655                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2656                 case GC_DISPLAY_CLOCK_333_MHZ:
2657                         return 333000;
2658                 default:
2659                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2660                         return 190000;
2661                 }
2662         }
2663 }
2664
2665 static int i865_get_display_clock_speed(struct drm_device *dev)
2666 {
2667         return 266000;
2668 }
2669
2670 static int i855_get_display_clock_speed(struct drm_device *dev)
2671 {
2672         u16 hpllcc = 0;
2673         /* Assume that the hardware is in the high speed state.  This
2674          * should be the default.
2675          */
2676         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2677         case GC_CLOCK_133_200:
2678         case GC_CLOCK_100_200:
2679                 return 200000;
2680         case GC_CLOCK_166_250:
2681                 return 250000;
2682         case GC_CLOCK_100_133:
2683                 return 133000;
2684         }
2685
2686         /* Shouldn't happen */
2687         return 0;
2688 }
2689
2690 static int i830_get_display_clock_speed(struct drm_device *dev)
2691 {
2692         return 133000;
2693 }
2694
2695 struct fdi_m_n {
2696         u32        tu;
2697         u32        gmch_m;
2698         u32        gmch_n;
2699         u32        link_m;
2700         u32        link_n;
2701 };
2702
2703 static void
2704 fdi_reduce_ratio(u32 *num, u32 *den)
2705 {
2706         while (*num > 0xffffff || *den > 0xffffff) {
2707                 *num >>= 1;
2708                 *den >>= 1;
2709         }
2710 }
2711
2712 #define DATA_N 0x800000
2713 #define LINK_N 0x80000
2714
2715 static void
2716 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2717                      int link_clock, struct fdi_m_n *m_n)
2718 {
2719         u64 temp;
2720
2721         m_n->tu = 64; /* default size */
2722
2723         temp = (u64) DATA_N * pixel_clock;
2724         temp = div_u64(temp, link_clock);
2725         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2726         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2727         m_n->gmch_n = DATA_N;
2728         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2729
2730         temp = (u64) LINK_N * pixel_clock;
2731         m_n->link_m = div_u64(temp, link_clock);
2732         m_n->link_n = LINK_N;
2733         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2734 }
2735
2736
2737 struct intel_watermark_params {
2738         unsigned long fifo_size;
2739         unsigned long max_wm;
2740         unsigned long default_wm;
2741         unsigned long guard_size;
2742         unsigned long cacheline_size;
2743 };
2744
2745 /* Pineview has different values for various configs */
2746 static struct intel_watermark_params pineview_display_wm = {
2747         PINEVIEW_DISPLAY_FIFO,
2748         PINEVIEW_MAX_WM,
2749         PINEVIEW_DFT_WM,
2750         PINEVIEW_GUARD_WM,
2751         PINEVIEW_FIFO_LINE_SIZE
2752 };
2753 static struct intel_watermark_params pineview_display_hplloff_wm = {
2754         PINEVIEW_DISPLAY_FIFO,
2755         PINEVIEW_MAX_WM,
2756         PINEVIEW_DFT_HPLLOFF_WM,
2757         PINEVIEW_GUARD_WM,
2758         PINEVIEW_FIFO_LINE_SIZE
2759 };
2760 static struct intel_watermark_params pineview_cursor_wm = {
2761         PINEVIEW_CURSOR_FIFO,
2762         PINEVIEW_CURSOR_MAX_WM,
2763         PINEVIEW_CURSOR_DFT_WM,
2764         PINEVIEW_CURSOR_GUARD_WM,
2765         PINEVIEW_FIFO_LINE_SIZE,
2766 };
2767 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2768         PINEVIEW_CURSOR_FIFO,
2769         PINEVIEW_CURSOR_MAX_WM,
2770         PINEVIEW_CURSOR_DFT_WM,
2771         PINEVIEW_CURSOR_GUARD_WM,
2772         PINEVIEW_FIFO_LINE_SIZE
2773 };
2774 static struct intel_watermark_params g4x_wm_info = {
2775         G4X_FIFO_SIZE,
2776         G4X_MAX_WM,
2777         G4X_MAX_WM,
2778         2,
2779         G4X_FIFO_LINE_SIZE,
2780 };
2781 static struct intel_watermark_params g4x_cursor_wm_info = {
2782         I965_CURSOR_FIFO,
2783         I965_CURSOR_MAX_WM,
2784         I965_CURSOR_DFT_WM,
2785         2,
2786         G4X_FIFO_LINE_SIZE,
2787 };
2788 static struct intel_watermark_params i965_cursor_wm_info = {
2789         I965_CURSOR_FIFO,
2790         I965_CURSOR_MAX_WM,
2791         I965_CURSOR_DFT_WM,
2792         2,
2793         I915_FIFO_LINE_SIZE,
2794 };
2795 static struct intel_watermark_params i945_wm_info = {
2796         I945_FIFO_SIZE,
2797         I915_MAX_WM,
2798         1,
2799         2,
2800         I915_FIFO_LINE_SIZE
2801 };
2802 static struct intel_watermark_params i915_wm_info = {
2803         I915_FIFO_SIZE,
2804         I915_MAX_WM,
2805         1,
2806         2,
2807         I915_FIFO_LINE_SIZE
2808 };
2809 static struct intel_watermark_params i855_wm_info = {
2810         I855GM_FIFO_SIZE,
2811         I915_MAX_WM,
2812         1,
2813         2,
2814         I830_FIFO_LINE_SIZE
2815 };
2816 static struct intel_watermark_params i830_wm_info = {
2817         I830_FIFO_SIZE,
2818         I915_MAX_WM,
2819         1,
2820         2,
2821         I830_FIFO_LINE_SIZE
2822 };
2823
2824 static struct intel_watermark_params ironlake_display_wm_info = {
2825         ILK_DISPLAY_FIFO,
2826         ILK_DISPLAY_MAXWM,
2827         ILK_DISPLAY_DFTWM,
2828         2,
2829         ILK_FIFO_LINE_SIZE
2830 };
2831
2832 static struct intel_watermark_params ironlake_cursor_wm_info = {
2833         ILK_CURSOR_FIFO,
2834         ILK_CURSOR_MAXWM,
2835         ILK_CURSOR_DFTWM,
2836         2,
2837         ILK_FIFO_LINE_SIZE
2838 };
2839
2840 static struct intel_watermark_params ironlake_display_srwm_info = {
2841         ILK_DISPLAY_SR_FIFO,
2842         ILK_DISPLAY_MAX_SRWM,
2843         ILK_DISPLAY_DFT_SRWM,
2844         2,
2845         ILK_FIFO_LINE_SIZE
2846 };
2847
2848 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2849         ILK_CURSOR_SR_FIFO,
2850         ILK_CURSOR_MAX_SRWM,
2851         ILK_CURSOR_DFT_SRWM,
2852         2,
2853         ILK_FIFO_LINE_SIZE
2854 };
2855
2856 /**
2857  * intel_calculate_wm - calculate watermark level
2858  * @clock_in_khz: pixel clock
2859  * @wm: chip FIFO params
2860  * @pixel_size: display pixel size
2861  * @latency_ns: memory latency for the platform
2862  *
2863  * Calculate the watermark level (the level at which the display plane will
2864  * start fetching from memory again).  Each chip has a different display
2865  * FIFO size and allocation, so the caller needs to figure that out and pass
2866  * in the correct intel_watermark_params structure.
2867  *
2868  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2869  * on the pixel size.  When it reaches the watermark level, it'll start
2870  * fetching FIFO line sized based chunks from memory until the FIFO fills
2871  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2872  * will occur, and a display engine hang could result.
2873  */
2874 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2875                                         struct intel_watermark_params *wm,
2876                                         int pixel_size,
2877                                         unsigned long latency_ns)
2878 {
2879         long entries_required, wm_size;
2880
2881         /*
2882          * Note: we need to make sure we don't overflow for various clock &
2883          * latency values.
2884          * clocks go from a few thousand to several hundred thousand.
2885          * latency is usually a few thousand
2886          */
2887         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2888                 1000;
2889         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2890
2891         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2892
2893         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2894
2895         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2896
2897         /* Don't promote wm_size to unsigned... */
2898         if (wm_size > (long)wm->max_wm)
2899                 wm_size = wm->max_wm;
2900         if (wm_size <= 0)
2901                 wm_size = wm->default_wm;
2902         return wm_size;
2903 }
2904
2905 struct cxsr_latency {
2906         int is_desktop;
2907         int is_ddr3;
2908         unsigned long fsb_freq;
2909         unsigned long mem_freq;
2910         unsigned long display_sr;
2911         unsigned long display_hpll_disable;
2912         unsigned long cursor_sr;
2913         unsigned long cursor_hpll_disable;
2914 };
2915
2916 static const struct cxsr_latency cxsr_latency_table[] = {
2917         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2918         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2919         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2920         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2921         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2922
2923         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2924         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2925         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2926         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2927         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2928
2929         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2930         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2931         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2932         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2933         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2934
2935         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2936         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2937         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2938         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2939         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2940
2941         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2942         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2943         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2944         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2945         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2946
2947         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2948         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2949         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2950         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2951         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2952 };
2953
2954 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2955                                                          int is_ddr3,
2956                                                          int fsb,
2957                                                          int mem)
2958 {
2959         const struct cxsr_latency *latency;
2960         int i;
2961
2962         if (fsb == 0 || mem == 0)
2963                 return NULL;
2964
2965         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2966                 latency = &cxsr_latency_table[i];
2967                 if (is_desktop == latency->is_desktop &&
2968                     is_ddr3 == latency->is_ddr3 &&
2969                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2970                         return latency;
2971         }
2972
2973         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2974
2975         return NULL;
2976 }
2977
2978 static void pineview_disable_cxsr(struct drm_device *dev)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981
2982         /* deactivate cxsr */
2983         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2984 }
2985
2986 /*
2987  * Latency for FIFO fetches is dependent on several factors:
2988  *   - memory configuration (speed, channels)
2989  *   - chipset
2990  *   - current MCH state
2991  * It can be fairly high in some situations, so here we assume a fairly
2992  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2993  * set this value too high, the FIFO will fetch frequently to stay full)
2994  * and power consumption (set it too low to save power and we might see
2995  * FIFO underruns and display "flicker").
2996  *
2997  * A value of 5us seems to be a good balance; safe for very low end
2998  * platforms but not overly aggressive on lower latency configs.
2999  */
3000 static const int latency_ns = 5000;
3001
3002 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3003 {
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         uint32_t dsparb = I915_READ(DSPARB);
3006         int size;
3007
3008         size = dsparb & 0x7f;
3009         if (plane)
3010                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3011
3012         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3013                       plane ? "B" : "A", size);
3014
3015         return size;
3016 }
3017
3018 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3019 {
3020         struct drm_i915_private *dev_priv = dev->dev_private;
3021         uint32_t dsparb = I915_READ(DSPARB);
3022         int size;
3023
3024         size = dsparb & 0x1ff;
3025         if (plane)
3026                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3027         size >>= 1; /* Convert to cachelines */
3028
3029         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3030                       plane ? "B" : "A", size);
3031
3032         return size;
3033 }
3034
3035 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3036 {
3037         struct drm_i915_private *dev_priv = dev->dev_private;
3038         uint32_t dsparb = I915_READ(DSPARB);
3039         int size;
3040
3041         size = dsparb & 0x7f;
3042         size >>= 2; /* Convert to cachelines */
3043
3044         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3045                       plane ? "B" : "A",
3046                       size);
3047
3048         return size;
3049 }
3050
3051 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3052 {
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         uint32_t dsparb = I915_READ(DSPARB);
3055         int size;
3056
3057         size = dsparb & 0x7f;
3058         size >>= 1; /* Convert to cachelines */
3059
3060         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3061                       plane ? "B" : "A", size);
3062
3063         return size;
3064 }
3065
3066 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3067                                int planeb_clock, int sr_hdisplay, int unused,
3068                                int pixel_size)
3069 {
3070         struct drm_i915_private *dev_priv = dev->dev_private;
3071         const struct cxsr_latency *latency;
3072         u32 reg;
3073         unsigned long wm;
3074         int sr_clock;
3075
3076         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3077                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3078         if (!latency) {
3079                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3080                 pineview_disable_cxsr(dev);
3081                 return;
3082         }
3083
3084         if (!planea_clock || !planeb_clock) {
3085                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3086
3087                 /* Display SR */
3088                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3089                                         pixel_size, latency->display_sr);
3090                 reg = I915_READ(DSPFW1);
3091                 reg &= ~DSPFW_SR_MASK;
3092                 reg |= wm << DSPFW_SR_SHIFT;
3093                 I915_WRITE(DSPFW1, reg);
3094                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3095
3096                 /* cursor SR */
3097                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3098                                         pixel_size, latency->cursor_sr);
3099                 reg = I915_READ(DSPFW3);
3100                 reg &= ~DSPFW_CURSOR_SR_MASK;
3101                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3102                 I915_WRITE(DSPFW3, reg);
3103
3104                 /* Display HPLL off SR */
3105                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3106                                         pixel_size, latency->display_hpll_disable);
3107                 reg = I915_READ(DSPFW3);
3108                 reg &= ~DSPFW_HPLL_SR_MASK;
3109                 reg |= wm & DSPFW_HPLL_SR_MASK;
3110                 I915_WRITE(DSPFW3, reg);
3111
3112                 /* cursor HPLL off SR */
3113                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3114                                         pixel_size, latency->cursor_hpll_disable);
3115                 reg = I915_READ(DSPFW3);
3116                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3117                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3118                 I915_WRITE(DSPFW3, reg);
3119                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3120
3121                 /* activate cxsr */
3122                 I915_WRITE(DSPFW3,
3123                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3124                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3125         } else {
3126                 pineview_disable_cxsr(dev);
3127                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3128         }
3129 }
3130
3131 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3132                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3133                           int pixel_size)
3134 {
3135         struct drm_i915_private *dev_priv = dev->dev_private;
3136         int total_size, cacheline_size;
3137         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3138         struct intel_watermark_params planea_params, planeb_params;
3139         unsigned long line_time_us;
3140         int sr_clock, sr_entries = 0, entries_required;
3141
3142         /* Create copies of the base settings for each pipe */
3143         planea_params = planeb_params = g4x_wm_info;
3144
3145         /* Grab a couple of global values before we overwrite them */
3146         total_size = planea_params.fifo_size;
3147         cacheline_size = planea_params.cacheline_size;
3148
3149         /*
3150          * Note: we need to make sure we don't overflow for various clock &
3151          * latency values.
3152          * clocks go from a few thousand to several hundred thousand.
3153          * latency is usually a few thousand
3154          */
3155         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3156                 1000;
3157         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3158         planea_wm = entries_required + planea_params.guard_size;
3159
3160         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3161                 1000;
3162         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3163         planeb_wm = entries_required + planeb_params.guard_size;
3164
3165         cursora_wm = cursorb_wm = 16;
3166         cursor_sr = 32;
3167
3168         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3169
3170         /* Calc sr entries for one plane configs */
3171         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3172                 /* self-refresh has much higher latency */
3173                 static const int sr_latency_ns = 12000;
3174
3175                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3176                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3177
3178                 /* Use ns/us then divide to preserve precision */
3179                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3180                         pixel_size * sr_hdisplay;
3181                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3182
3183                 entries_required = (((sr_latency_ns / line_time_us) +
3184                                      1000) / 1000) * pixel_size * 64;
3185                 entries_required = DIV_ROUND_UP(entries_required,
3186                                                 g4x_cursor_wm_info.cacheline_size);
3187                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3188
3189                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3190                         cursor_sr = g4x_cursor_wm_info.max_wm;
3191                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3192                               "cursor %d\n", sr_entries, cursor_sr);
3193
3194                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3195         } else {
3196                 /* Turn off self refresh if both pipes are enabled */
3197                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3198                            & ~FW_BLC_SELF_EN);
3199         }
3200
3201         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3202                   planea_wm, planeb_wm, sr_entries);
3203
3204         planea_wm &= 0x3f;
3205         planeb_wm &= 0x3f;
3206
3207         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3208                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3209                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3210         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3211                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3212         /* HPLL off in SR has some issues on G4x... disable it */
3213         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3214                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3215 }
3216
3217 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3218                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3219                            int pixel_size)
3220 {
3221         struct drm_i915_private *dev_priv = dev->dev_private;
3222         unsigned long line_time_us;
3223         int sr_clock, sr_entries, srwm = 1;
3224         int cursor_sr = 16;
3225
3226         /* Calc sr entries for one plane configs */
3227         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3228                 /* self-refresh has much higher latency */
3229                 static const int sr_latency_ns = 12000;
3230
3231                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3232                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3233
3234                 /* Use ns/us then divide to preserve precision */
3235                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3236                         pixel_size * sr_hdisplay;
3237                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3238                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3239                 srwm = I965_FIFO_SIZE - sr_entries;
3240                 if (srwm < 0)
3241                         srwm = 1;
3242                 srwm &= 0x1ff;
3243
3244                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3245                         pixel_size * 64;
3246                 sr_entries = DIV_ROUND_UP(sr_entries,
3247                                           i965_cursor_wm_info.cacheline_size);
3248                 cursor_sr = i965_cursor_wm_info.fifo_size -
3249                         (sr_entries + i965_cursor_wm_info.guard_size);
3250
3251                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3252                         cursor_sr = i965_cursor_wm_info.max_wm;
3253
3254                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3255                               "cursor %d\n", srwm, cursor_sr);
3256
3257                 if (IS_CRESTLINE(dev))
3258                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3259         } else {
3260                 /* Turn off self refresh if both pipes are enabled */
3261                 if (IS_CRESTLINE(dev))
3262                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3263                                    & ~FW_BLC_SELF_EN);
3264         }
3265
3266         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3267                       srwm);
3268
3269         /* 965 has limitations... */
3270         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3271                    (8 << 0));
3272         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3273         /* update cursor SR watermark */
3274         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3275 }
3276
3277 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3278                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3279                            int pixel_size)
3280 {
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         uint32_t fwater_lo;
3283         uint32_t fwater_hi;
3284         int total_size, cacheline_size, cwm, srwm = 1;
3285         int planea_wm, planeb_wm;
3286         struct intel_watermark_params planea_params, planeb_params;
3287         unsigned long line_time_us;
3288         int sr_clock, sr_entries = 0;
3289
3290         /* Create copies of the base settings for each pipe */
3291         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3292                 planea_params = planeb_params = i945_wm_info;
3293         else if (!IS_GEN2(dev))
3294                 planea_params = planeb_params = i915_wm_info;
3295         else
3296                 planea_params = planeb_params = i855_wm_info;
3297
3298         /* Grab a couple of global values before we overwrite them */
3299         total_size = planea_params.fifo_size;
3300         cacheline_size = planea_params.cacheline_size;
3301
3302         /* Update per-plane FIFO sizes */
3303         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3304         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3305
3306         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3307                                        pixel_size, latency_ns);
3308         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3309                                        pixel_size, latency_ns);
3310         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3311
3312         /*
3313          * Overlay gets an aggressive default since video jitter is bad.
3314          */
3315         cwm = 2;
3316
3317         /* Calc sr entries for one plane configs */
3318         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3319             (!planea_clock || !planeb_clock)) {
3320                 /* self-refresh has much higher latency */
3321                 static const int sr_latency_ns = 6000;
3322
3323                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3324                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3325
3326                 /* Use ns/us then divide to preserve precision */
3327                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3328                         pixel_size * sr_hdisplay;
3329                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3330                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3331                 srwm = total_size - sr_entries;
3332                 if (srwm < 0)
3333                         srwm = 1;
3334
3335                 if (IS_I945G(dev) || IS_I945GM(dev))
3336                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3337                 else if (IS_I915GM(dev)) {
3338                         /* 915M has a smaller SRWM field */
3339                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3340                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3341                 }
3342         } else {
3343                 /* Turn off self refresh if both pipes are enabled */
3344                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3345                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3346                                    & ~FW_BLC_SELF_EN);
3347                 } else if (IS_I915GM(dev)) {
3348                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3349                 }
3350         }
3351
3352         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3353                       planea_wm, planeb_wm, cwm, srwm);
3354
3355         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3356         fwater_hi = (cwm & 0x1f);
3357
3358         /* Set request length to 8 cachelines per fetch */
3359         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3360         fwater_hi = fwater_hi | (1 << 8);
3361
3362         I915_WRITE(FW_BLC, fwater_lo);
3363         I915_WRITE(FW_BLC2, fwater_hi);
3364 }
3365
3366 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3367                            int unused2, int unused3, int pixel_size)
3368 {
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3371         int planea_wm;
3372
3373         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3374
3375         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3376                                        pixel_size, latency_ns);
3377         fwater_lo |= (3<<8) | planea_wm;
3378
3379         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3380
3381         I915_WRITE(FW_BLC, fwater_lo);
3382 }
3383
3384 #define ILK_LP0_PLANE_LATENCY           700
3385 #define ILK_LP0_CURSOR_LATENCY          1300
3386
3387 static bool ironlake_compute_wm0(struct drm_device *dev,
3388                                  int pipe,
3389                                  int *plane_wm,
3390                                  int *cursor_wm)
3391 {
3392         struct drm_crtc *crtc;
3393         int htotal, hdisplay, clock, pixel_size = 0;
3394         int line_time_us, line_count, entries;
3395
3396         crtc = intel_get_crtc_for_pipe(dev, pipe);
3397         if (crtc->fb == NULL || !crtc->enabled)
3398                 return false;
3399
3400         htotal = crtc->mode.htotal;
3401         hdisplay = crtc->mode.hdisplay;
3402         clock = crtc->mode.clock;
3403         pixel_size = crtc->fb->bits_per_pixel / 8;
3404
3405         /* Use the small buffer method to calculate plane watermark */
3406         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3407         entries = DIV_ROUND_UP(entries,
3408                                ironlake_display_wm_info.cacheline_size);
3409         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3410         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3411                 *plane_wm = ironlake_display_wm_info.max_wm;
3412
3413         /* Use the large buffer method to calculate cursor watermark */
3414         line_time_us = ((htotal * 1000) / clock);
3415         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3416         entries = line_count * 64 * pixel_size;
3417         entries = DIV_ROUND_UP(entries,
3418                                ironlake_cursor_wm_info.cacheline_size);
3419         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3420         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3421                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3422
3423         return true;
3424 }
3425
3426 static void ironlake_update_wm(struct drm_device *dev,
3427                                int planea_clock, int planeb_clock,
3428                                int sr_hdisplay, int sr_htotal,
3429                                int pixel_size)
3430 {
3431         struct drm_i915_private *dev_priv = dev->dev_private;
3432         int plane_wm, cursor_wm, enabled;
3433         int tmp;
3434
3435         enabled = 0;
3436         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3437                 I915_WRITE(WM0_PIPEA_ILK,
3438                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3439                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3440                               " plane %d, " "cursor: %d\n",
3441                               plane_wm, cursor_wm);
3442                 enabled++;
3443         }
3444
3445         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3446                 I915_WRITE(WM0_PIPEB_ILK,
3447                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3448                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3449                               " plane %d, cursor: %d\n",
3450                               plane_wm, cursor_wm);
3451                 enabled++;
3452         }
3453
3454         /*
3455          * Calculate and update the self-refresh watermark only when one
3456          * display plane is used.
3457          */
3458         tmp = 0;
3459         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3460                 unsigned long line_time_us;
3461                 int small, large, plane_fbc;
3462                 int sr_clock, entries;
3463                 int line_count, line_size;
3464                 /* Read the self-refresh latency. The unit is 0.5us */
3465                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3466
3467                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3468                 line_time_us = (sr_htotal * 1000) / sr_clock;
3469
3470                 /* Use ns/us then divide to preserve precision */
3471                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3472                         / 1000;
3473                 line_size = sr_hdisplay * pixel_size;
3474
3475                 /* Use the minimum of the small and large buffer method for primary */
3476                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3477                 large = line_count * line_size;
3478
3479                 entries = DIV_ROUND_UP(min(small, large),
3480                                        ironlake_display_srwm_info.cacheline_size);
3481
3482                 plane_fbc = entries * 64;
3483                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3484
3485                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3486                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3487                         plane_wm = ironlake_display_srwm_info.max_wm;
3488
3489                 /* calculate the self-refresh watermark for display cursor */
3490                 entries = line_count * pixel_size * 64;
3491                 entries = DIV_ROUND_UP(entries,
3492                                        ironlake_cursor_srwm_info.cacheline_size);
3493
3494                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3495                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3496                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3497
3498                 /* configure watermark and enable self-refresh */
3499                 tmp = (WM1_LP_SR_EN |
3500                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3501                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3502                        (plane_wm << WM1_LP_SR_SHIFT) |
3503                        cursor_wm);
3504                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3505                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3506         }
3507         I915_WRITE(WM1_LP_ILK, tmp);
3508         /* XXX setup WM2 and WM3 */
3509 }
3510
3511 /**
3512  * intel_update_watermarks - update FIFO watermark values based on current modes
3513  *
3514  * Calculate watermark values for the various WM regs based on current mode
3515  * and plane configuration.
3516  *
3517  * There are several cases to deal with here:
3518  *   - normal (i.e. non-self-refresh)
3519  *   - self-refresh (SR) mode
3520  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3521  *   - lines are small relative to FIFO size (buffer can hold more than 2
3522  *     lines), so need to account for TLB latency
3523  *
3524  *   The normal calculation is:
3525  *     watermark = dotclock * bytes per pixel * latency
3526  *   where latency is platform & configuration dependent (we assume pessimal
3527  *   values here).
3528  *
3529  *   The SR calculation is:
3530  *     watermark = (trunc(latency/line time)+1) * surface width *
3531  *       bytes per pixel
3532  *   where
3533  *     line time = htotal / dotclock
3534  *     surface width = hdisplay for normal plane and 64 for cursor
3535  *   and latency is assumed to be high, as above.
3536  *
3537  * The final value programmed to the register should always be rounded up,
3538  * and include an extra 2 entries to account for clock crossings.
3539  *
3540  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3541  * to set the non-SR watermarks to 8.
3542  */
3543 static void intel_update_watermarks(struct drm_device *dev)
3544 {
3545         struct drm_i915_private *dev_priv = dev->dev_private;
3546         struct drm_crtc *crtc;
3547         int sr_hdisplay = 0;
3548         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3549         int enabled = 0, pixel_size = 0;
3550         int sr_htotal = 0;
3551
3552         if (!dev_priv->display.update_wm)
3553                 return;
3554
3555         /* Get the clock config from both planes */
3556         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3557                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558                 if (intel_crtc->active) {
3559                         enabled++;
3560                         if (intel_crtc->plane == 0) {
3561                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3562                                               intel_crtc->pipe, crtc->mode.clock);
3563                                 planea_clock = crtc->mode.clock;
3564                         } else {
3565                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3566                                               intel_crtc->pipe, crtc->mode.clock);
3567                                 planeb_clock = crtc->mode.clock;
3568                         }
3569                         sr_hdisplay = crtc->mode.hdisplay;
3570                         sr_clock = crtc->mode.clock;
3571                         sr_htotal = crtc->mode.htotal;
3572                         if (crtc->fb)
3573                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3574                         else
3575                                 pixel_size = 4; /* by default */
3576                 }
3577         }
3578
3579         if (enabled <= 0)
3580                 return;
3581
3582         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3583                                     sr_hdisplay, sr_htotal, pixel_size);
3584 }
3585
3586 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3587                                struct drm_display_mode *mode,
3588                                struct drm_display_mode *adjusted_mode,
3589                                int x, int y,
3590                                struct drm_framebuffer *old_fb)
3591 {
3592         struct drm_device *dev = crtc->dev;
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595         int pipe = intel_crtc->pipe;
3596         int plane = intel_crtc->plane;
3597         u32 fp_reg, dpll_reg;
3598         int refclk, num_connectors = 0;
3599         intel_clock_t clock, reduced_clock;
3600         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3601         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3602         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3603         struct intel_encoder *has_edp_encoder = NULL;
3604         struct drm_mode_config *mode_config = &dev->mode_config;
3605         struct intel_encoder *encoder;
3606         const intel_limit_t *limit;
3607         int ret;
3608         struct fdi_m_n m_n = {0};
3609         u32 reg, temp;
3610         int target_clock;
3611
3612         drm_vblank_pre_modeset(dev, pipe);
3613
3614         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3615                 if (encoder->base.crtc != crtc)
3616                         continue;
3617
3618                 switch (encoder->type) {
3619                 case INTEL_OUTPUT_LVDS:
3620                         is_lvds = true;
3621                         break;
3622                 case INTEL_OUTPUT_SDVO:
3623                 case INTEL_OUTPUT_HDMI:
3624                         is_sdvo = true;
3625                         if (encoder->needs_tv_clock)
3626                                 is_tv = true;
3627                         break;
3628                 case INTEL_OUTPUT_DVO:
3629                         is_dvo = true;
3630                         break;
3631                 case INTEL_OUTPUT_TVOUT:
3632                         is_tv = true;
3633                         break;
3634                 case INTEL_OUTPUT_ANALOG:
3635                         is_crt = true;
3636                         break;
3637                 case INTEL_OUTPUT_DISPLAYPORT:
3638                         is_dp = true;
3639                         break;
3640                 case INTEL_OUTPUT_EDP:
3641                         has_edp_encoder = encoder;
3642                         break;
3643                 }
3644
3645                 num_connectors++;
3646         }
3647
3648         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3649                 refclk = dev_priv->lvds_ssc_freq * 1000;
3650                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3651                               refclk / 1000);
3652         } else if (!IS_GEN2(dev)) {
3653                 refclk = 96000;
3654                 if (HAS_PCH_SPLIT(dev) &&
3655                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3656                         refclk = 120000; /* 120Mhz refclk */
3657         } else {
3658                 refclk = 48000;
3659         }
3660
3661         /*
3662          * Returns a set of divisors for the desired target clock with the given
3663          * refclk, or FALSE.  The returned values represent the clock equation:
3664          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3665          */
3666         limit = intel_limit(crtc);
3667         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3668         if (!ok) {
3669                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3670                 drm_vblank_post_modeset(dev, pipe);
3671                 return -EINVAL;
3672         }
3673
3674         /* Ensure that the cursor is valid for the new mode before changing... */
3675         intel_crtc_update_cursor(crtc, true);
3676
3677         if (is_lvds && dev_priv->lvds_downclock_avail) {
3678                 has_reduced_clock = limit->find_pll(limit, crtc,
3679                                                     dev_priv->lvds_downclock,
3680                                                     refclk,
3681                                                     &reduced_clock);
3682                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3683                         /*
3684                          * If the different P is found, it means that we can't
3685                          * switch the display clock by using the FP0/FP1.
3686                          * In such case we will disable the LVDS downclock
3687                          * feature.
3688                          */
3689                         DRM_DEBUG_KMS("Different P is found for "
3690                                       "LVDS clock/downclock\n");
3691                         has_reduced_clock = 0;
3692                 }
3693         }
3694         /* SDVO TV has fixed PLL values depend on its clock range,
3695            this mirrors vbios setting. */
3696         if (is_sdvo && is_tv) {
3697                 if (adjusted_mode->clock >= 100000
3698                     && adjusted_mode->clock < 140500) {
3699                         clock.p1 = 2;
3700                         clock.p2 = 10;
3701                         clock.n = 3;
3702                         clock.m1 = 16;
3703                         clock.m2 = 8;
3704                 } else if (adjusted_mode->clock >= 140500
3705                            && adjusted_mode->clock <= 200000) {
3706                         clock.p1 = 1;
3707                         clock.p2 = 10;
3708                         clock.n = 6;
3709                         clock.m1 = 12;
3710                         clock.m2 = 8;
3711                 }
3712         }
3713
3714         /* FDI link */
3715         if (HAS_PCH_SPLIT(dev)) {
3716                 int lane = 0, link_bw, bpp;
3717                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3718                    according to current link config */
3719                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3720                         target_clock = mode->clock;
3721                         intel_edp_link_config(has_edp_encoder,
3722                                               &lane, &link_bw);
3723                 } else {
3724                         /* [e]DP over FDI requires target mode clock
3725                            instead of link clock */
3726                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3727                                 target_clock = mode->clock;
3728                         else
3729                                 target_clock = adjusted_mode->clock;
3730
3731                         /* FDI is a binary signal running at ~2.7GHz, encoding
3732                          * each output octet as 10 bits. The actual frequency
3733                          * is stored as a divider into a 100MHz clock, and the
3734                          * mode pixel clock is stored in units of 1KHz.
3735                          * Hence the bw of each lane in terms of the mode signal
3736                          * is:
3737                          */
3738                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3739                 }
3740
3741                 /* determine panel color depth */
3742                 temp = I915_READ(PIPECONF(pipe));
3743                 temp &= ~PIPE_BPC_MASK;
3744                 if (is_lvds) {
3745                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3746                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3747                                 temp |= PIPE_8BPC;
3748                         else
3749                                 temp |= PIPE_6BPC;
3750                 } else if (has_edp_encoder) {
3751                         switch (dev_priv->edp.bpp/3) {
3752                         case 8:
3753                                 temp |= PIPE_8BPC;
3754                                 break;
3755                         case 10:
3756                                 temp |= PIPE_10BPC;
3757                                 break;
3758                         case 6:
3759                                 temp |= PIPE_6BPC;
3760                                 break;
3761                         case 12:
3762                                 temp |= PIPE_12BPC;
3763                                 break;
3764                         }
3765                 } else
3766                         temp |= PIPE_8BPC;
3767                 I915_WRITE(PIPECONF(pipe), temp);
3768
3769                 switch (temp & PIPE_BPC_MASK) {
3770                 case PIPE_8BPC:
3771                         bpp = 24;
3772                         break;
3773                 case PIPE_10BPC:
3774                         bpp = 30;
3775                         break;
3776                 case PIPE_6BPC:
3777                         bpp = 18;
3778                         break;
3779                 case PIPE_12BPC:
3780                         bpp = 36;
3781                         break;
3782                 default:
3783                         DRM_ERROR("unknown pipe bpc value\n");
3784                         bpp = 24;
3785                 }
3786
3787                 if (!lane) {
3788                         /*
3789                          * Account for spread spectrum to avoid
3790                          * oversubscribing the link. Max center spread
3791                          * is 2.5%; use 5% for safety's sake.
3792                          */
3793                         u32 bps = target_clock * bpp * 21 / 20;
3794                         lane = bps / (link_bw * 8) + 1;
3795                 }
3796
3797                 intel_crtc->fdi_lanes = lane;
3798
3799                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3800         }
3801
3802         /* Ironlake: try to setup display ref clock before DPLL
3803          * enabling. This is only under driver's control after
3804          * PCH B stepping, previous chipset stepping should be
3805          * ignoring this setting.
3806          */
3807         if (HAS_PCH_SPLIT(dev)) {
3808                 temp = I915_READ(PCH_DREF_CONTROL);
3809                 /* Always enable nonspread source */
3810                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3811                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3812                 temp &= ~DREF_SSC_SOURCE_MASK;
3813                 temp |= DREF_SSC_SOURCE_ENABLE;
3814                 I915_WRITE(PCH_DREF_CONTROL, temp);
3815
3816                 POSTING_READ(PCH_DREF_CONTROL);
3817                 udelay(200);
3818
3819                 if (has_edp_encoder) {
3820                         if (dev_priv->lvds_use_ssc) {
3821                                 temp |= DREF_SSC1_ENABLE;
3822                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3823
3824                                 POSTING_READ(PCH_DREF_CONTROL);
3825                                 udelay(200);
3826                         }
3827                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3828
3829                         /* Enable CPU source on CPU attached eDP */
3830                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3831                                 if (dev_priv->lvds_use_ssc)
3832                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3833                                 else
3834                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3835                         } else {
3836                                 /* Enable SSC on PCH eDP if needed */
3837                                 if (dev_priv->lvds_use_ssc) {
3838                                         DRM_ERROR("enabling SSC on PCH\n");
3839                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3840                                 }
3841                         }
3842                         I915_WRITE(PCH_DREF_CONTROL, temp);
3843                         POSTING_READ(PCH_DREF_CONTROL);
3844                         udelay(200);
3845                 }
3846         }
3847
3848         if (IS_PINEVIEW(dev)) {
3849                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3850                 if (has_reduced_clock)
3851                         fp2 = (1 << reduced_clock.n) << 16 |
3852                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3853         } else {
3854                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3855                 if (has_reduced_clock)
3856                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3857                                 reduced_clock.m2;
3858         }
3859
3860         /* Enable autotuning of the PLL clock (if permissible) */
3861         if (HAS_PCH_SPLIT(dev)) {
3862                 int factor = 21;
3863
3864                 if (is_lvds) {
3865                         if ((dev_priv->lvds_use_ssc &&
3866                              dev_priv->lvds_ssc_freq == 100) ||
3867                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
3868                                 factor = 25;
3869                 } else if (is_sdvo && is_tv)
3870                         factor = 20;
3871
3872                 if (clock.m1 < factor * clock.n)
3873                         fp |= FP_CB_TUNE;
3874         }
3875
3876         dpll = 0;
3877         if (!HAS_PCH_SPLIT(dev))
3878                 dpll = DPLL_VGA_MODE_DIS;
3879
3880         if (!IS_GEN2(dev)) {
3881                 if (is_lvds)
3882                         dpll |= DPLLB_MODE_LVDS;
3883                 else
3884                         dpll |= DPLLB_MODE_DAC_SERIAL;
3885                 if (is_sdvo) {
3886                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3887                         if (pixel_multiplier > 1) {
3888                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3889                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3890                                 else if (HAS_PCH_SPLIT(dev))
3891                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3892                         }
3893                         dpll |= DPLL_DVO_HIGH_SPEED;
3894                 }
3895                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3896                         dpll |= DPLL_DVO_HIGH_SPEED;
3897
3898                 /* compute bitmask from p1 value */
3899                 if (IS_PINEVIEW(dev))
3900                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3901                 else {
3902                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3903                         /* also FPA1 */
3904                         if (HAS_PCH_SPLIT(dev))
3905                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3906                         if (IS_G4X(dev) && has_reduced_clock)
3907                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3908                 }
3909                 switch (clock.p2) {
3910                 case 5:
3911                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3912                         break;
3913                 case 7:
3914                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3915                         break;
3916                 case 10:
3917                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3918                         break;
3919                 case 14:
3920                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3921                         break;
3922                 }
3923                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3924                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3925         } else {
3926                 if (is_lvds) {
3927                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3928                 } else {
3929                         if (clock.p1 == 2)
3930                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3931                         else
3932                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3933                         if (clock.p2 == 4)
3934                                 dpll |= PLL_P2_DIVIDE_BY_4;
3935                 }
3936         }
3937
3938         if (is_sdvo && is_tv)
3939                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3940         else if (is_tv)
3941                 /* XXX: just matching BIOS for now */
3942                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3943                 dpll |= 3;
3944         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3945                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3946         else
3947                 dpll |= PLL_REF_INPUT_DREFCLK;
3948
3949         /* setup pipeconf */
3950         pipeconf = I915_READ(PIPECONF(pipe));
3951
3952         /* Set up the display plane register */
3953         dspcntr = DISPPLANE_GAMMA_ENABLE;
3954
3955         /* Ironlake's plane is forced to pipe, bit 24 is to
3956            enable color space conversion */
3957         if (!HAS_PCH_SPLIT(dev)) {
3958                 if (pipe == 0)
3959                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3960                 else
3961                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3962         }
3963
3964         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3965                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3966                  * core speed.
3967                  *
3968                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3969                  * pipe == 0 check?
3970                  */
3971                 if (mode->clock >
3972                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3973                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3974                 else
3975                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3976         }
3977
3978         dspcntr |= DISPLAY_PLANE_ENABLE;
3979         pipeconf |= PIPECONF_ENABLE;
3980         dpll |= DPLL_VCO_ENABLE;
3981
3982         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3983         drm_mode_debug_printmodeline(mode);
3984
3985         /* assign to Ironlake registers */
3986         if (HAS_PCH_SPLIT(dev)) {
3987                 fp_reg = PCH_FP0(pipe);
3988                 dpll_reg = PCH_DPLL(pipe);
3989         } else {
3990                 fp_reg = FP0(pipe);
3991                 dpll_reg = DPLL(pipe);
3992         }
3993
3994         /* PCH eDP needs FDI, but CPU eDP does not */
3995         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3996                 I915_WRITE(fp_reg, fp);
3997                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3998
3999                 POSTING_READ(dpll_reg);
4000                 udelay(150);
4001         }
4002
4003         /* enable transcoder DPLL */
4004         if (HAS_PCH_CPT(dev)) {
4005                 temp = I915_READ(PCH_DPLL_SEL);
4006                 if (pipe == 0)
4007                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4008                 else
4009                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4010                 I915_WRITE(PCH_DPLL_SEL, temp);
4011
4012                 POSTING_READ(PCH_DPLL_SEL);
4013                 udelay(150);
4014         }
4015
4016         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4017          * This is an exception to the general rule that mode_set doesn't turn
4018          * things on.
4019          */
4020         if (is_lvds) {
4021                 reg = LVDS;
4022                 if (HAS_PCH_SPLIT(dev))
4023                         reg = PCH_LVDS;
4024
4025                 temp = I915_READ(reg);
4026                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4027                 if (pipe == 1) {
4028                         if (HAS_PCH_CPT(dev))
4029                                 temp |= PORT_TRANS_B_SEL_CPT;
4030                         else
4031                                 temp |= LVDS_PIPEB_SELECT;
4032                 } else {
4033                         if (HAS_PCH_CPT(dev))
4034                                 temp &= ~PORT_TRANS_SEL_MASK;
4035                         else
4036                                 temp &= ~LVDS_PIPEB_SELECT;
4037                 }
4038                 /* set the corresponsding LVDS_BORDER bit */
4039                 temp |= dev_priv->lvds_border_bits;
4040                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4041                  * set the DPLLs for dual-channel mode or not.
4042                  */
4043                 if (clock.p2 == 7)
4044                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4045                 else
4046                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4047
4048                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4049                  * appropriately here, but we need to look more thoroughly into how
4050                  * panels behave in the two modes.
4051                  */
4052                 /* set the dithering flag on non-PCH LVDS as needed */
4053                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4054                         if (dev_priv->lvds_dither)
4055                                 temp |= LVDS_ENABLE_DITHER;
4056                         else
4057                                 temp &= ~LVDS_ENABLE_DITHER;
4058                 }
4059                 I915_WRITE(reg, temp);
4060         }
4061
4062         /* set the dithering flag and clear for anything other than a panel. */
4063         if (HAS_PCH_SPLIT(dev)) {
4064                 pipeconf &= ~PIPECONF_DITHER_EN;
4065                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4066                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4067                         pipeconf |= PIPECONF_DITHER_EN;
4068                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4069                 }
4070         }
4071
4072         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4073                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4074         } else if (HAS_PCH_SPLIT(dev)) {
4075                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4076                 if (pipe == 0) {
4077                         I915_WRITE(TRANSA_DATA_M1, 0);
4078                         I915_WRITE(TRANSA_DATA_N1, 0);
4079                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4080                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4081                 } else {
4082                         I915_WRITE(TRANSB_DATA_M1, 0);
4083                         I915_WRITE(TRANSB_DATA_N1, 0);
4084                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4085                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4086                 }
4087         }
4088
4089         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4090                 I915_WRITE(dpll_reg, dpll);
4091
4092                 /* Wait for the clocks to stabilize. */
4093                 POSTING_READ(dpll_reg);
4094                 udelay(150);
4095
4096                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4097                         temp = 0;
4098                         if (is_sdvo) {
4099                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4100                                 if (temp > 1)
4101                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4102                                 else
4103                                         temp = 0;
4104                         }
4105                         I915_WRITE(DPLL_MD(pipe), temp);
4106                 } else {
4107                         /* The pixel multiplier can only be updated once the
4108                          * DPLL is enabled and the clocks are stable.
4109                          *
4110                          * So write it again.
4111                          */
4112                         I915_WRITE(dpll_reg, dpll);
4113                 }
4114         }
4115
4116         intel_crtc->lowfreq_avail = false;
4117         if (is_lvds && has_reduced_clock && i915_powersave) {
4118                 I915_WRITE(fp_reg + 4, fp2);
4119                 intel_crtc->lowfreq_avail = true;
4120                 if (HAS_PIPE_CXSR(dev)) {
4121                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4122                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4123                 }
4124         } else {
4125                 I915_WRITE(fp_reg + 4, fp);
4126                 if (HAS_PIPE_CXSR(dev)) {
4127                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4128                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4129                 }
4130         }
4131
4132         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4133                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4134                 /* the chip adds 2 halflines automatically */
4135                 adjusted_mode->crtc_vdisplay -= 1;
4136                 adjusted_mode->crtc_vtotal -= 1;
4137                 adjusted_mode->crtc_vblank_start -= 1;
4138                 adjusted_mode->crtc_vblank_end -= 1;
4139                 adjusted_mode->crtc_vsync_end -= 1;
4140                 adjusted_mode->crtc_vsync_start -= 1;
4141         } else
4142                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4143
4144         I915_WRITE(HTOTAL(pipe),
4145                    (adjusted_mode->crtc_hdisplay - 1) |
4146                    ((adjusted_mode->crtc_htotal - 1) << 16));
4147         I915_WRITE(HBLANK(pipe),
4148                    (adjusted_mode->crtc_hblank_start - 1) |
4149                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4150         I915_WRITE(HSYNC(pipe),
4151                    (adjusted_mode->crtc_hsync_start - 1) |
4152                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4153
4154         I915_WRITE(VTOTAL(pipe),
4155                    (adjusted_mode->crtc_vdisplay - 1) |
4156                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4157         I915_WRITE(VBLANK(pipe),
4158                    (adjusted_mode->crtc_vblank_start - 1) |
4159                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4160         I915_WRITE(VSYNC(pipe),
4161                    (adjusted_mode->crtc_vsync_start - 1) |
4162                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4163
4164         /* pipesrc and dspsize control the size that is scaled from,
4165          * which should always be the user's requested size.
4166          */
4167         if (!HAS_PCH_SPLIT(dev)) {
4168                 I915_WRITE(DSPSIZE(plane),
4169                            ((mode->vdisplay - 1) << 16) |
4170                            (mode->hdisplay - 1));
4171                 I915_WRITE(DSPPOS(plane), 0);
4172         }
4173         I915_WRITE(PIPESRC(pipe),
4174                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4175
4176         if (HAS_PCH_SPLIT(dev)) {
4177                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4178                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4179                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4180                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4181
4182                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4183                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4184                 }
4185         }
4186
4187         I915_WRITE(PIPECONF(pipe), pipeconf);
4188         POSTING_READ(PIPECONF(pipe));
4189
4190         intel_wait_for_vblank(dev, pipe);
4191
4192         if (IS_GEN5(dev)) {
4193                 /* enable address swizzle for tiling buffer */
4194                 temp = I915_READ(DISP_ARB_CTL);
4195                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4196         }
4197
4198         I915_WRITE(DSPCNTR(plane), dspcntr);
4199
4200         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4201
4202         intel_update_watermarks(dev);
4203
4204         drm_vblank_post_modeset(dev, pipe);
4205
4206         return ret;
4207 }
4208
4209 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4210 void intel_crtc_load_lut(struct drm_crtc *crtc)
4211 {
4212         struct drm_device *dev = crtc->dev;
4213         struct drm_i915_private *dev_priv = dev->dev_private;
4214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4215         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4216         int i;
4217
4218         /* The clocks have to be on to load the palette. */
4219         if (!crtc->enabled)
4220                 return;
4221
4222         /* use legacy palette for Ironlake */
4223         if (HAS_PCH_SPLIT(dev))
4224                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4225                                                    LGC_PALETTE_B;
4226
4227         for (i = 0; i < 256; i++) {
4228                 I915_WRITE(palreg + 4 * i,
4229                            (intel_crtc->lut_r[i] << 16) |
4230                            (intel_crtc->lut_g[i] << 8) |
4231                            intel_crtc->lut_b[i]);
4232         }
4233 }
4234
4235 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4236 {
4237         struct drm_device *dev = crtc->dev;
4238         struct drm_i915_private *dev_priv = dev->dev_private;
4239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4240         bool visible = base != 0;
4241         u32 cntl;
4242
4243         if (intel_crtc->cursor_visible == visible)
4244                 return;
4245
4246         cntl = I915_READ(CURACNTR);
4247         if (visible) {
4248                 /* On these chipsets we can only modify the base whilst
4249                  * the cursor is disabled.
4250                  */
4251                 I915_WRITE(CURABASE, base);
4252
4253                 cntl &= ~(CURSOR_FORMAT_MASK);
4254                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4255                 cntl |= CURSOR_ENABLE |
4256                         CURSOR_GAMMA_ENABLE |
4257                         CURSOR_FORMAT_ARGB;
4258         } else
4259                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4260         I915_WRITE(CURACNTR, cntl);
4261
4262         intel_crtc->cursor_visible = visible;
4263 }
4264
4265 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4266 {
4267         struct drm_device *dev = crtc->dev;
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4270         int pipe = intel_crtc->pipe;
4271         bool visible = base != 0;
4272
4273         if (intel_crtc->cursor_visible != visible) {
4274                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4275                 if (base) {
4276                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4277                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4278                         cntl |= pipe << 28; /* Connect to correct pipe */
4279                 } else {
4280                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4281                         cntl |= CURSOR_MODE_DISABLE;
4282                 }
4283                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4284
4285                 intel_crtc->cursor_visible = visible;
4286         }
4287         /* and commit changes on next vblank */
4288         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4289 }
4290
4291 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4292 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4293                                      bool on)
4294 {
4295         struct drm_device *dev = crtc->dev;
4296         struct drm_i915_private *dev_priv = dev->dev_private;
4297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4298         int pipe = intel_crtc->pipe;
4299         int x = intel_crtc->cursor_x;
4300         int y = intel_crtc->cursor_y;
4301         u32 base, pos;
4302         bool visible;
4303
4304         pos = 0;
4305
4306         if (on && crtc->enabled && crtc->fb) {
4307                 base = intel_crtc->cursor_addr;
4308                 if (x > (int) crtc->fb->width)
4309                         base = 0;
4310
4311                 if (y > (int) crtc->fb->height)
4312                         base = 0;
4313         } else
4314                 base = 0;
4315
4316         if (x < 0) {
4317                 if (x + intel_crtc->cursor_width < 0)
4318                         base = 0;
4319
4320                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4321                 x = -x;
4322         }
4323         pos |= x << CURSOR_X_SHIFT;
4324
4325         if (y < 0) {
4326                 if (y + intel_crtc->cursor_height < 0)
4327                         base = 0;
4328
4329                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4330                 y = -y;
4331         }
4332         pos |= y << CURSOR_Y_SHIFT;
4333
4334         visible = base != 0;
4335         if (!visible && !intel_crtc->cursor_visible)
4336                 return;
4337
4338         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4339         if (IS_845G(dev) || IS_I865G(dev))
4340                 i845_update_cursor(crtc, base);
4341         else
4342                 i9xx_update_cursor(crtc, base);
4343
4344         if (visible)
4345                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4346 }
4347
4348 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4349                                  struct drm_file *file,
4350                                  uint32_t handle,
4351                                  uint32_t width, uint32_t height)
4352 {
4353         struct drm_device *dev = crtc->dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4356         struct drm_i915_gem_object *obj;
4357         uint32_t addr;
4358         int ret;
4359
4360         DRM_DEBUG_KMS("\n");
4361
4362         /* if we want to turn off the cursor ignore width and height */
4363         if (!handle) {
4364                 DRM_DEBUG_KMS("cursor off\n");
4365                 addr = 0;
4366                 obj = NULL;
4367                 mutex_lock(&dev->struct_mutex);
4368                 goto finish;
4369         }
4370
4371         /* Currently we only support 64x64 cursors */
4372         if (width != 64 || height != 64) {
4373                 DRM_ERROR("we currently only support 64x64 cursors\n");
4374                 return -EINVAL;
4375         }
4376
4377         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4378         if (!obj)
4379                 return -ENOENT;
4380
4381         if (obj->base.size < width * height * 4) {
4382                 DRM_ERROR("buffer is to small\n");
4383                 ret = -ENOMEM;
4384                 goto fail;
4385         }
4386
4387         /* we only need to pin inside GTT if cursor is non-phy */
4388         mutex_lock(&dev->struct_mutex);
4389         if (!dev_priv->info->cursor_needs_physical) {
4390                 if (obj->tiling_mode) {
4391                         DRM_ERROR("cursor cannot be tiled\n");
4392                         ret = -EINVAL;
4393                         goto fail_locked;
4394                 }
4395
4396                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4397                 if (ret) {
4398                         DRM_ERROR("failed to pin cursor bo\n");
4399                         goto fail_locked;
4400                 }
4401
4402                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4403                 if (ret) {
4404                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4405                         goto fail_unpin;
4406                 }
4407
4408                 ret = i915_gem_object_put_fence(obj);
4409                 if (ret) {
4410                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4411                         goto fail_unpin;
4412                 }
4413
4414                 addr = obj->gtt_offset;
4415         } else {
4416                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4417                 ret = i915_gem_attach_phys_object(dev, obj,
4418                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4419                                                   align);
4420                 if (ret) {
4421                         DRM_ERROR("failed to attach phys object\n");
4422                         goto fail_locked;
4423                 }
4424                 addr = obj->phys_obj->handle->busaddr;
4425         }
4426
4427         if (IS_GEN2(dev))
4428                 I915_WRITE(CURSIZE, (height << 12) | width);
4429
4430  finish:
4431         if (intel_crtc->cursor_bo) {
4432                 if (dev_priv->info->cursor_needs_physical) {
4433                         if (intel_crtc->cursor_bo != obj)
4434                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4435                 } else
4436                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4437                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4438         }
4439
4440         mutex_unlock(&dev->struct_mutex);
4441
4442         intel_crtc->cursor_addr = addr;
4443         intel_crtc->cursor_bo = obj;
4444         intel_crtc->cursor_width = width;
4445         intel_crtc->cursor_height = height;
4446
4447         intel_crtc_update_cursor(crtc, true);
4448
4449         return 0;
4450 fail_unpin:
4451         i915_gem_object_unpin(obj);
4452 fail_locked:
4453         mutex_unlock(&dev->struct_mutex);
4454 fail:
4455         drm_gem_object_unreference_unlocked(&obj->base);
4456         return ret;
4457 }
4458
4459 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4460 {
4461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4462
4463         intel_crtc->cursor_x = x;
4464         intel_crtc->cursor_y = y;
4465
4466         intel_crtc_update_cursor(crtc, true);
4467
4468         return 0;
4469 }
4470
4471 /** Sets the color ramps on behalf of RandR */
4472 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4473                                  u16 blue, int regno)
4474 {
4475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4476
4477         intel_crtc->lut_r[regno] = red >> 8;
4478         intel_crtc->lut_g[regno] = green >> 8;
4479         intel_crtc->lut_b[regno] = blue >> 8;
4480 }
4481
4482 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4483                              u16 *blue, int regno)
4484 {
4485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4486
4487         *red = intel_crtc->lut_r[regno] << 8;
4488         *green = intel_crtc->lut_g[regno] << 8;
4489         *blue = intel_crtc->lut_b[regno] << 8;
4490 }
4491
4492 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4493                                  u16 *blue, uint32_t start, uint32_t size)
4494 {
4495         int end = (start + size > 256) ? 256 : start + size, i;
4496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4497
4498         for (i = start; i < end; i++) {
4499                 intel_crtc->lut_r[i] = red[i] >> 8;
4500                 intel_crtc->lut_g[i] = green[i] >> 8;
4501                 intel_crtc->lut_b[i] = blue[i] >> 8;
4502         }
4503
4504         intel_crtc_load_lut(crtc);
4505 }
4506
4507 /**
4508  * Get a pipe with a simple mode set on it for doing load-based monitor
4509  * detection.
4510  *
4511  * It will be up to the load-detect code to adjust the pipe as appropriate for
4512  * its requirements.  The pipe will be connected to no other encoders.
4513  *
4514  * Currently this code will only succeed if there is a pipe with no encoders
4515  * configured for it.  In the future, it could choose to temporarily disable
4516  * some outputs to free up a pipe for its use.
4517  *
4518  * \return crtc, or NULL if no pipes are available.
4519  */
4520
4521 /* VESA 640x480x72Hz mode to set on the pipe */
4522 static struct drm_display_mode load_detect_mode = {
4523         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4524                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4525 };
4526
4527 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4528                                             struct drm_connector *connector,
4529                                             struct drm_display_mode *mode,
4530                                             int *dpms_mode)
4531 {
4532         struct intel_crtc *intel_crtc;
4533         struct drm_crtc *possible_crtc;
4534         struct drm_crtc *supported_crtc =NULL;
4535         struct drm_encoder *encoder = &intel_encoder->base;
4536         struct drm_crtc *crtc = NULL;
4537         struct drm_device *dev = encoder->dev;
4538         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4539         struct drm_crtc_helper_funcs *crtc_funcs;
4540         int i = -1;
4541
4542         /*
4543          * Algorithm gets a little messy:
4544          *   - if the connector already has an assigned crtc, use it (but make
4545          *     sure it's on first)
4546          *   - try to find the first unused crtc that can drive this connector,
4547          *     and use that if we find one
4548          *   - if there are no unused crtcs available, try to use the first
4549          *     one we found that supports the connector
4550          */
4551
4552         /* See if we already have a CRTC for this connector */
4553         if (encoder->crtc) {
4554                 crtc = encoder->crtc;
4555                 /* Make sure the crtc and connector are running */
4556                 intel_crtc = to_intel_crtc(crtc);
4557                 *dpms_mode = intel_crtc->dpms_mode;
4558                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4559                         crtc_funcs = crtc->helper_private;
4560                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4561                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4562                 }
4563                 return crtc;
4564         }
4565
4566         /* Find an unused one (if possible) */
4567         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4568                 i++;
4569                 if (!(encoder->possible_crtcs & (1 << i)))
4570                         continue;
4571                 if (!possible_crtc->enabled) {
4572                         crtc = possible_crtc;
4573                         break;
4574                 }
4575                 if (!supported_crtc)
4576                         supported_crtc = possible_crtc;
4577         }
4578
4579         /*
4580          * If we didn't find an unused CRTC, don't use any.
4581          */
4582         if (!crtc) {
4583                 return NULL;
4584         }
4585
4586         encoder->crtc = crtc;
4587         connector->encoder = encoder;
4588         intel_encoder->load_detect_temp = true;
4589
4590         intel_crtc = to_intel_crtc(crtc);
4591         *dpms_mode = intel_crtc->dpms_mode;
4592
4593         if (!crtc->enabled) {
4594                 if (!mode)
4595                         mode = &load_detect_mode;
4596                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4597         } else {
4598                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4599                         crtc_funcs = crtc->helper_private;
4600                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4601                 }
4602
4603                 /* Add this connector to the crtc */
4604                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4605                 encoder_funcs->commit(encoder);
4606         }
4607         /* let the connector get through one full cycle before testing */
4608         intel_wait_for_vblank(dev, intel_crtc->pipe);
4609
4610         return crtc;
4611 }
4612
4613 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4614                                     struct drm_connector *connector, int dpms_mode)
4615 {
4616         struct drm_encoder *encoder = &intel_encoder->base;
4617         struct drm_device *dev = encoder->dev;
4618         struct drm_crtc *crtc = encoder->crtc;
4619         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4620         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4621
4622         if (intel_encoder->load_detect_temp) {
4623                 encoder->crtc = NULL;
4624                 connector->encoder = NULL;
4625                 intel_encoder->load_detect_temp = false;
4626                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4627                 drm_helper_disable_unused_functions(dev);
4628         }
4629
4630         /* Switch crtc and encoder back off if necessary */
4631         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4632                 if (encoder->crtc == crtc)
4633                         encoder_funcs->dpms(encoder, dpms_mode);
4634                 crtc_funcs->dpms(crtc, dpms_mode);
4635         }
4636 }
4637
4638 /* Returns the clock of the currently programmed mode of the given pipe. */
4639 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4640 {
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4643         int pipe = intel_crtc->pipe;
4644         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4645         u32 fp;
4646         intel_clock_t clock;
4647
4648         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4649                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4650         else
4651                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4652
4653         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4654         if (IS_PINEVIEW(dev)) {
4655                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4656                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4657         } else {
4658                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4659                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4660         }
4661
4662         if (!IS_GEN2(dev)) {
4663                 if (IS_PINEVIEW(dev))
4664                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4665                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4666                 else
4667                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4668                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4669
4670                 switch (dpll & DPLL_MODE_MASK) {
4671                 case DPLLB_MODE_DAC_SERIAL:
4672                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4673                                 5 : 10;
4674                         break;
4675                 case DPLLB_MODE_LVDS:
4676                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4677                                 7 : 14;
4678                         break;
4679                 default:
4680                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4681                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4682                         return 0;
4683                 }
4684
4685                 /* XXX: Handle the 100Mhz refclk */
4686                 intel_clock(dev, 96000, &clock);
4687         } else {
4688                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4689
4690                 if (is_lvds) {
4691                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4692                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4693                         clock.p2 = 14;
4694
4695                         if ((dpll & PLL_REF_INPUT_MASK) ==
4696                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4697                                 /* XXX: might not be 66MHz */
4698                                 intel_clock(dev, 66000, &clock);
4699                         } else
4700                                 intel_clock(dev, 48000, &clock);
4701                 } else {
4702                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4703                                 clock.p1 = 2;
4704                         else {
4705                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4706                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4707                         }
4708                         if (dpll & PLL_P2_DIVIDE_BY_4)
4709                                 clock.p2 = 4;
4710                         else
4711                                 clock.p2 = 2;
4712
4713                         intel_clock(dev, 48000, &clock);
4714                 }
4715         }
4716
4717         /* XXX: It would be nice to validate the clocks, but we can't reuse
4718          * i830PllIsValid() because it relies on the xf86_config connector
4719          * configuration being accurate, which it isn't necessarily.
4720          */
4721
4722         return clock.dot;
4723 }
4724
4725 /** Returns the currently programmed mode of the given pipe. */
4726 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4727                                              struct drm_crtc *crtc)
4728 {
4729         struct drm_i915_private *dev_priv = dev->dev_private;
4730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4731         int pipe = intel_crtc->pipe;
4732         struct drm_display_mode *mode;
4733         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4734         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4735         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4736         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4737
4738         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4739         if (!mode)
4740                 return NULL;
4741
4742         mode->clock = intel_crtc_clock_get(dev, crtc);
4743         mode->hdisplay = (htot & 0xffff) + 1;
4744         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4745         mode->hsync_start = (hsync & 0xffff) + 1;
4746         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4747         mode->vdisplay = (vtot & 0xffff) + 1;
4748         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4749         mode->vsync_start = (vsync & 0xffff) + 1;
4750         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4751
4752         drm_mode_set_name(mode);
4753         drm_mode_set_crtcinfo(mode, 0);
4754
4755         return mode;
4756 }
4757
4758 #define GPU_IDLE_TIMEOUT 500 /* ms */
4759
4760 /* When this timer fires, we've been idle for awhile */
4761 static void intel_gpu_idle_timer(unsigned long arg)
4762 {
4763         struct drm_device *dev = (struct drm_device *)arg;
4764         drm_i915_private_t *dev_priv = dev->dev_private;
4765
4766         dev_priv->busy = false;
4767
4768         queue_work(dev_priv->wq, &dev_priv->idle_work);
4769 }
4770
4771 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4772
4773 static void intel_crtc_idle_timer(unsigned long arg)
4774 {
4775         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4776         struct drm_crtc *crtc = &intel_crtc->base;
4777         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4778
4779         intel_crtc->busy = false;
4780
4781         queue_work(dev_priv->wq, &dev_priv->idle_work);
4782 }
4783
4784 static void intel_increase_pllclock(struct drm_crtc *crtc)
4785 {
4786         struct drm_device *dev = crtc->dev;
4787         drm_i915_private_t *dev_priv = dev->dev_private;
4788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4789         int pipe = intel_crtc->pipe;
4790         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4791         int dpll = I915_READ(dpll_reg);
4792
4793         if (HAS_PCH_SPLIT(dev))
4794                 return;
4795
4796         if (!dev_priv->lvds_downclock_avail)
4797                 return;
4798
4799         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4800                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4801
4802                 /* Unlock panel regs */
4803                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4804                            PANEL_UNLOCK_REGS);
4805
4806                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4807                 I915_WRITE(dpll_reg, dpll);
4808                 dpll = I915_READ(dpll_reg);
4809                 intel_wait_for_vblank(dev, pipe);
4810                 dpll = I915_READ(dpll_reg);
4811                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4812                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4813
4814                 /* ...and lock them again */
4815                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4816         }
4817
4818         /* Schedule downclock */
4819         mod_timer(&intel_crtc->idle_timer, jiffies +
4820                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4821 }
4822
4823 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4824 {
4825         struct drm_device *dev = crtc->dev;
4826         drm_i915_private_t *dev_priv = dev->dev_private;
4827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4828         int pipe = intel_crtc->pipe;
4829         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4830         int dpll = I915_READ(dpll_reg);
4831
4832         if (HAS_PCH_SPLIT(dev))
4833                 return;
4834
4835         if (!dev_priv->lvds_downclock_avail)
4836                 return;
4837
4838         /*
4839          * Since this is called by a timer, we should never get here in
4840          * the manual case.
4841          */
4842         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4843                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4844
4845                 /* Unlock panel regs */
4846                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4847                            PANEL_UNLOCK_REGS);
4848
4849                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4850                 I915_WRITE(dpll_reg, dpll);
4851                 dpll = I915_READ(dpll_reg);
4852                 intel_wait_for_vblank(dev, pipe);
4853                 dpll = I915_READ(dpll_reg);
4854                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4855                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4856
4857                 /* ...and lock them again */
4858                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4859         }
4860
4861 }
4862
4863 /**
4864  * intel_idle_update - adjust clocks for idleness
4865  * @work: work struct
4866  *
4867  * Either the GPU or display (or both) went idle.  Check the busy status
4868  * here and adjust the CRTC and GPU clocks as necessary.
4869  */
4870 static void intel_idle_update(struct work_struct *work)
4871 {
4872         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4873                                                     idle_work);
4874         struct drm_device *dev = dev_priv->dev;
4875         struct drm_crtc *crtc;
4876         struct intel_crtc *intel_crtc;
4877         int enabled = 0;
4878
4879         if (!i915_powersave)
4880                 return;
4881
4882         mutex_lock(&dev->struct_mutex);
4883
4884         i915_update_gfx_val(dev_priv);
4885
4886         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4887                 /* Skip inactive CRTCs */
4888                 if (!crtc->fb)
4889                         continue;
4890
4891                 enabled++;
4892                 intel_crtc = to_intel_crtc(crtc);
4893                 if (!intel_crtc->busy)
4894                         intel_decrease_pllclock(crtc);
4895         }
4896
4897         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4898                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4899                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4900         }
4901
4902         mutex_unlock(&dev->struct_mutex);
4903 }
4904
4905 /**
4906  * intel_mark_busy - mark the GPU and possibly the display busy
4907  * @dev: drm device
4908  * @obj: object we're operating on
4909  *
4910  * Callers can use this function to indicate that the GPU is busy processing
4911  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4912  * buffer), we'll also mark the display as busy, so we know to increase its
4913  * clock frequency.
4914  */
4915 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
4916 {
4917         drm_i915_private_t *dev_priv = dev->dev_private;
4918         struct drm_crtc *crtc = NULL;
4919         struct intel_framebuffer *intel_fb;
4920         struct intel_crtc *intel_crtc;
4921
4922         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4923                 return;
4924
4925         if (!dev_priv->busy) {
4926                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4927                         u32 fw_blc_self;
4928
4929                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4930                         fw_blc_self = I915_READ(FW_BLC_SELF);
4931                         fw_blc_self &= ~FW_BLC_SELF_EN;
4932                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4933                 }
4934                 dev_priv->busy = true;
4935         } else
4936                 mod_timer(&dev_priv->idle_timer, jiffies +
4937                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4938
4939         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4940                 if (!crtc->fb)
4941                         continue;
4942
4943                 intel_crtc = to_intel_crtc(crtc);
4944                 intel_fb = to_intel_framebuffer(crtc->fb);
4945                 if (intel_fb->obj == obj) {
4946                         if (!intel_crtc->busy) {
4947                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4948                                         u32 fw_blc_self;
4949
4950                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4951                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4952                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4953                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4954                                 }
4955                                 /* Non-busy -> busy, upclock */
4956                                 intel_increase_pllclock(crtc);
4957                                 intel_crtc->busy = true;
4958                         } else {
4959                                 /* Busy -> busy, put off timer */
4960                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4961                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4962                         }
4963                 }
4964         }
4965 }
4966
4967 static void intel_crtc_destroy(struct drm_crtc *crtc)
4968 {
4969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970         struct drm_device *dev = crtc->dev;
4971         struct intel_unpin_work *work;
4972         unsigned long flags;
4973
4974         spin_lock_irqsave(&dev->event_lock, flags);
4975         work = intel_crtc->unpin_work;
4976         intel_crtc->unpin_work = NULL;
4977         spin_unlock_irqrestore(&dev->event_lock, flags);
4978
4979         if (work) {
4980                 cancel_work_sync(&work->work);
4981                 kfree(work);
4982         }
4983
4984         drm_crtc_cleanup(crtc);
4985
4986         kfree(intel_crtc);
4987 }
4988
4989 static void intel_unpin_work_fn(struct work_struct *__work)
4990 {
4991         struct intel_unpin_work *work =
4992                 container_of(__work, struct intel_unpin_work, work);
4993
4994         mutex_lock(&work->dev->struct_mutex);
4995         i915_gem_object_unpin(work->old_fb_obj);
4996         drm_gem_object_unreference(&work->pending_flip_obj->base);
4997         drm_gem_object_unreference(&work->old_fb_obj->base);
4998
4999         mutex_unlock(&work->dev->struct_mutex);
5000         kfree(work);
5001 }
5002
5003 static void do_intel_finish_page_flip(struct drm_device *dev,
5004                                       struct drm_crtc *crtc)
5005 {
5006         drm_i915_private_t *dev_priv = dev->dev_private;
5007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5008         struct intel_unpin_work *work;
5009         struct drm_i915_gem_object *obj;
5010         struct drm_pending_vblank_event *e;
5011         struct timeval now;
5012         unsigned long flags;
5013
5014         /* Ignore early vblank irqs */
5015         if (intel_crtc == NULL)
5016                 return;
5017
5018         spin_lock_irqsave(&dev->event_lock, flags);
5019         work = intel_crtc->unpin_work;
5020         if (work == NULL || !work->pending) {
5021                 spin_unlock_irqrestore(&dev->event_lock, flags);
5022                 return;
5023         }
5024
5025         intel_crtc->unpin_work = NULL;
5026         drm_vblank_put(dev, intel_crtc->pipe);
5027
5028         if (work->event) {
5029                 e = work->event;
5030                 do_gettimeofday(&now);
5031                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5032                 e->event.tv_sec = now.tv_sec;
5033                 e->event.tv_usec = now.tv_usec;
5034                 list_add_tail(&e->base.link,
5035                               &e->base.file_priv->event_list);
5036                 wake_up_interruptible(&e->base.file_priv->event_wait);
5037         }
5038
5039         spin_unlock_irqrestore(&dev->event_lock, flags);
5040
5041         obj = work->old_fb_obj;
5042
5043         atomic_clear_mask(1 << intel_crtc->plane,
5044                           &obj->pending_flip.counter);
5045         if (atomic_read(&obj->pending_flip) == 0)
5046                 wake_up(&dev_priv->pending_flip_queue);
5047
5048         schedule_work(&work->work);
5049
5050         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5051 }
5052
5053 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5054 {
5055         drm_i915_private_t *dev_priv = dev->dev_private;
5056         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5057
5058         do_intel_finish_page_flip(dev, crtc);
5059 }
5060
5061 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5062 {
5063         drm_i915_private_t *dev_priv = dev->dev_private;
5064         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5065
5066         do_intel_finish_page_flip(dev, crtc);
5067 }
5068
5069 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5070 {
5071         drm_i915_private_t *dev_priv = dev->dev_private;
5072         struct intel_crtc *intel_crtc =
5073                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5074         unsigned long flags;
5075
5076         spin_lock_irqsave(&dev->event_lock, flags);
5077         if (intel_crtc->unpin_work) {
5078                 if ((++intel_crtc->unpin_work->pending) > 1)
5079                         DRM_ERROR("Prepared flip multiple times\n");
5080         } else {
5081                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5082         }
5083         spin_unlock_irqrestore(&dev->event_lock, flags);
5084 }
5085
5086 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5087                                 struct drm_framebuffer *fb,
5088                                 struct drm_pending_vblank_event *event)
5089 {
5090         struct drm_device *dev = crtc->dev;
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092         struct intel_framebuffer *intel_fb;
5093         struct drm_i915_gem_object *obj;
5094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095         struct intel_unpin_work *work;
5096         unsigned long flags, offset;
5097         int pipe = intel_crtc->pipe;
5098         u32 pf, pipesrc;
5099         int ret;
5100
5101         work = kzalloc(sizeof *work, GFP_KERNEL);
5102         if (work == NULL)
5103                 return -ENOMEM;
5104
5105         work->event = event;
5106         work->dev = crtc->dev;
5107         intel_fb = to_intel_framebuffer(crtc->fb);
5108         work->old_fb_obj = intel_fb->obj;
5109         INIT_WORK(&work->work, intel_unpin_work_fn);
5110
5111         /* We borrow the event spin lock for protecting unpin_work */
5112         spin_lock_irqsave(&dev->event_lock, flags);
5113         if (intel_crtc->unpin_work) {
5114                 spin_unlock_irqrestore(&dev->event_lock, flags);
5115                 kfree(work);
5116
5117                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5118                 return -EBUSY;
5119         }
5120         intel_crtc->unpin_work = work;
5121         spin_unlock_irqrestore(&dev->event_lock, flags);
5122
5123         intel_fb = to_intel_framebuffer(fb);
5124         obj = intel_fb->obj;
5125
5126         mutex_lock(&dev->struct_mutex);
5127         ret = intel_pin_and_fence_fb_obj(dev, obj, &dev_priv->render_ring);
5128         if (ret)
5129                 goto cleanup_work;
5130
5131         /* Reference the objects for the scheduled work. */
5132         drm_gem_object_reference(&work->old_fb_obj->base);
5133         drm_gem_object_reference(&obj->base);
5134
5135         crtc->fb = fb;
5136
5137         ret = drm_vblank_get(dev, intel_crtc->pipe);
5138         if (ret)
5139                 goto cleanup_objs;
5140
5141         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5142                 u32 flip_mask;
5143
5144                 /* Can't queue multiple flips, so wait for the previous
5145                  * one to finish before executing the next.
5146                  */
5147                 ret = BEGIN_LP_RING(2);
5148                 if (ret)
5149                         goto cleanup_objs;
5150
5151                 if (intel_crtc->plane)
5152                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5153                 else
5154                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5155                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5156                 OUT_RING(MI_NOOP);
5157                 ADVANCE_LP_RING();
5158         }
5159
5160         work->pending_flip_obj = obj;
5161
5162         work->enable_stall_check = true;
5163
5164         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5165         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5166
5167         ret = BEGIN_LP_RING(4);
5168         if (ret)
5169                 goto cleanup_objs;
5170
5171         /* Block clients from rendering to the new back buffer until
5172          * the flip occurs and the object is no longer visible.
5173          */
5174         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5175
5176         switch (INTEL_INFO(dev)->gen) {
5177         case 2:
5178                 OUT_RING(MI_DISPLAY_FLIP |
5179                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5180                 OUT_RING(fb->pitch);
5181                 OUT_RING(obj->gtt_offset + offset);
5182                 OUT_RING(MI_NOOP);
5183                 break;
5184
5185         case 3:
5186                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5187                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5188                 OUT_RING(fb->pitch);
5189                 OUT_RING(obj->gtt_offset + offset);
5190                 OUT_RING(MI_NOOP);
5191                 break;
5192
5193         case 4:
5194         case 5:
5195                 /* i965+ uses the linear or tiled offsets from the
5196                  * Display Registers (which do not change across a page-flip)
5197                  * so we need only reprogram the base address.
5198                  */
5199                 OUT_RING(MI_DISPLAY_FLIP |
5200                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5201                 OUT_RING(fb->pitch);
5202                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5203
5204                 /* XXX Enabling the panel-fitter across page-flip is so far
5205                  * untested on non-native modes, so ignore it for now.
5206                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5207                  */
5208                 pf = 0;
5209                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5210                 OUT_RING(pf | pipesrc);
5211                 break;
5212
5213         case 6:
5214                 OUT_RING(MI_DISPLAY_FLIP |
5215                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5216                 OUT_RING(fb->pitch | obj->tiling_mode);
5217                 OUT_RING(obj->gtt_offset);
5218
5219                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5220                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5221                 OUT_RING(pf | pipesrc);
5222                 break;
5223         }
5224         ADVANCE_LP_RING();
5225
5226         mutex_unlock(&dev->struct_mutex);
5227
5228         trace_i915_flip_request(intel_crtc->plane, obj);
5229
5230         return 0;
5231
5232 cleanup_objs:
5233         drm_gem_object_unreference(&work->old_fb_obj->base);
5234         drm_gem_object_unreference(&obj->base);
5235 cleanup_work:
5236         mutex_unlock(&dev->struct_mutex);
5237
5238         spin_lock_irqsave(&dev->event_lock, flags);
5239         intel_crtc->unpin_work = NULL;
5240         spin_unlock_irqrestore(&dev->event_lock, flags);
5241
5242         kfree(work);
5243
5244         return ret;
5245 }
5246
5247 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5248         .dpms = intel_crtc_dpms,
5249         .mode_fixup = intel_crtc_mode_fixup,
5250         .mode_set = intel_crtc_mode_set,
5251         .mode_set_base = intel_pipe_set_base,
5252         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5253         .load_lut = intel_crtc_load_lut,
5254         .disable = intel_crtc_disable,
5255 };
5256
5257 static const struct drm_crtc_funcs intel_crtc_funcs = {
5258         .cursor_set = intel_crtc_cursor_set,
5259         .cursor_move = intel_crtc_cursor_move,
5260         .gamma_set = intel_crtc_gamma_set,
5261         .set_config = drm_crtc_helper_set_config,
5262         .destroy = intel_crtc_destroy,
5263         .page_flip = intel_crtc_page_flip,
5264 };
5265
5266
5267 static void intel_crtc_init(struct drm_device *dev, int pipe)
5268 {
5269         drm_i915_private_t *dev_priv = dev->dev_private;
5270         struct intel_crtc *intel_crtc;
5271         int i;
5272
5273         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5274         if (intel_crtc == NULL)
5275                 return;
5276
5277         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5278
5279         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5280         for (i = 0; i < 256; i++) {
5281                 intel_crtc->lut_r[i] = i;
5282                 intel_crtc->lut_g[i] = i;
5283                 intel_crtc->lut_b[i] = i;
5284         }
5285
5286         /* Swap pipes & planes for FBC on pre-965 */
5287         intel_crtc->pipe = pipe;
5288         intel_crtc->plane = pipe;
5289         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5290                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5291                 intel_crtc->plane = !pipe;
5292         }
5293
5294         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5295                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5296         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5297         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5298
5299         intel_crtc->cursor_addr = 0;
5300         intel_crtc->dpms_mode = -1;
5301         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5302
5303         if (HAS_PCH_SPLIT(dev)) {
5304                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5305                 intel_helper_funcs.commit = ironlake_crtc_commit;
5306         } else {
5307                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5308                 intel_helper_funcs.commit = i9xx_crtc_commit;
5309         }
5310
5311         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5312
5313         intel_crtc->busy = false;
5314
5315         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5316                     (unsigned long)intel_crtc);
5317 }
5318
5319 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5320                                 struct drm_file *file)
5321 {
5322         drm_i915_private_t *dev_priv = dev->dev_private;
5323         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5324         struct drm_mode_object *drmmode_obj;
5325         struct intel_crtc *crtc;
5326
5327         if (!dev_priv) {
5328                 DRM_ERROR("called with no initialization\n");
5329                 return -EINVAL;
5330         }
5331
5332         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5333                         DRM_MODE_OBJECT_CRTC);
5334
5335         if (!drmmode_obj) {
5336                 DRM_ERROR("no such CRTC id\n");
5337                 return -EINVAL;
5338         }
5339
5340         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5341         pipe_from_crtc_id->pipe = crtc->pipe;
5342
5343         return 0;
5344 }
5345
5346 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5347 {
5348         struct intel_encoder *encoder;
5349         int index_mask = 0;
5350         int entry = 0;
5351
5352         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5353                 if (type_mask & encoder->clone_mask)
5354                         index_mask |= (1 << entry);
5355                 entry++;
5356         }
5357
5358         return index_mask;
5359 }
5360
5361 static void intel_setup_outputs(struct drm_device *dev)
5362 {
5363         struct drm_i915_private *dev_priv = dev->dev_private;
5364         struct intel_encoder *encoder;
5365         bool dpd_is_edp = false;
5366         bool has_lvds = false;
5367
5368         if (IS_MOBILE(dev) && !IS_I830(dev))
5369                 has_lvds = intel_lvds_init(dev);
5370         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5371                 /* disable the panel fitter on everything but LVDS */
5372                 I915_WRITE(PFIT_CONTROL, 0);
5373         }
5374
5375         if (HAS_PCH_SPLIT(dev)) {
5376                 dpd_is_edp = intel_dpd_is_edp(dev);
5377
5378                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5379                         intel_dp_init(dev, DP_A);
5380
5381                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5382                         intel_dp_init(dev, PCH_DP_D);
5383         }
5384
5385         intel_crt_init(dev);
5386
5387         if (HAS_PCH_SPLIT(dev)) {
5388                 int found;
5389
5390                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5391                         /* PCH SDVOB multiplex with HDMIB */
5392                         found = intel_sdvo_init(dev, PCH_SDVOB);
5393                         if (!found)
5394                                 intel_hdmi_init(dev, HDMIB);
5395                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5396                                 intel_dp_init(dev, PCH_DP_B);
5397                 }
5398
5399                 if (I915_READ(HDMIC) & PORT_DETECTED)
5400                         intel_hdmi_init(dev, HDMIC);
5401
5402                 if (I915_READ(HDMID) & PORT_DETECTED)
5403                         intel_hdmi_init(dev, HDMID);
5404
5405                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5406                         intel_dp_init(dev, PCH_DP_C);
5407
5408                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5409                         intel_dp_init(dev, PCH_DP_D);
5410
5411         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5412                 bool found = false;
5413
5414                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5415                         DRM_DEBUG_KMS("probing SDVOB\n");
5416                         found = intel_sdvo_init(dev, SDVOB);
5417                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5418                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5419                                 intel_hdmi_init(dev, SDVOB);
5420                         }
5421
5422                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5423                                 DRM_DEBUG_KMS("probing DP_B\n");
5424                                 intel_dp_init(dev, DP_B);
5425                         }
5426                 }
5427
5428                 /* Before G4X SDVOC doesn't have its own detect register */
5429
5430                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5431                         DRM_DEBUG_KMS("probing SDVOC\n");
5432                         found = intel_sdvo_init(dev, SDVOC);
5433                 }
5434
5435                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5436
5437                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5438                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5439                                 intel_hdmi_init(dev, SDVOC);
5440                         }
5441                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5442                                 DRM_DEBUG_KMS("probing DP_C\n");
5443                                 intel_dp_init(dev, DP_C);
5444                         }
5445                 }
5446
5447                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5448                     (I915_READ(DP_D) & DP_DETECTED)) {
5449                         DRM_DEBUG_KMS("probing DP_D\n");
5450                         intel_dp_init(dev, DP_D);
5451                 }
5452         } else if (IS_GEN2(dev))
5453                 intel_dvo_init(dev);
5454
5455         if (SUPPORTS_TV(dev))
5456                 intel_tv_init(dev);
5457
5458         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5459                 encoder->base.possible_crtcs = encoder->crtc_mask;
5460                 encoder->base.possible_clones =
5461                         intel_encoder_clones(dev, encoder->clone_mask);
5462         }
5463 }
5464
5465 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5466 {
5467         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5468
5469         drm_framebuffer_cleanup(fb);
5470         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5471
5472         kfree(intel_fb);
5473 }
5474
5475 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5476                                                 struct drm_file *file,
5477                                                 unsigned int *handle)
5478 {
5479         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5480         struct drm_i915_gem_object *obj = intel_fb->obj;
5481
5482         return drm_gem_handle_create(file, &obj->base, handle);
5483 }
5484
5485 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5486         .destroy = intel_user_framebuffer_destroy,
5487         .create_handle = intel_user_framebuffer_create_handle,
5488 };
5489
5490 int intel_framebuffer_init(struct drm_device *dev,
5491                            struct intel_framebuffer *intel_fb,
5492                            struct drm_mode_fb_cmd *mode_cmd,
5493                            struct drm_i915_gem_object *obj)
5494 {
5495         int ret;
5496
5497         if (obj->tiling_mode == I915_TILING_Y)
5498                 return -EINVAL;
5499
5500         if (mode_cmd->pitch & 63)
5501                 return -EINVAL;
5502
5503         switch (mode_cmd->bpp) {
5504         case 8:
5505         case 16:
5506         case 24:
5507         case 32:
5508                 break;
5509         default:
5510                 return -EINVAL;
5511         }
5512
5513         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5514         if (ret) {
5515                 DRM_ERROR("framebuffer init failed %d\n", ret);
5516                 return ret;
5517         }
5518
5519         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5520         intel_fb->obj = obj;
5521         return 0;
5522 }
5523
5524 static struct drm_framebuffer *
5525 intel_user_framebuffer_create(struct drm_device *dev,
5526                               struct drm_file *filp,
5527                               struct drm_mode_fb_cmd *mode_cmd)
5528 {
5529         struct drm_i915_gem_object *obj;
5530         struct intel_framebuffer *intel_fb;
5531         int ret;
5532
5533         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
5534         if (!obj)
5535                 return ERR_PTR(-ENOENT);
5536
5537         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5538         if (!intel_fb)
5539                 return ERR_PTR(-ENOMEM);
5540
5541         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5542         if (ret) {
5543                 drm_gem_object_unreference_unlocked(&obj->base);
5544                 kfree(intel_fb);
5545                 return ERR_PTR(ret);
5546         }
5547
5548         return &intel_fb->base;
5549 }
5550
5551 static const struct drm_mode_config_funcs intel_mode_funcs = {
5552         .fb_create = intel_user_framebuffer_create,
5553         .output_poll_changed = intel_fb_output_poll_changed,
5554 };
5555
5556 static struct drm_i915_gem_object *
5557 intel_alloc_context_page(struct drm_device *dev)
5558 {
5559         struct drm_i915_gem_object *ctx;
5560         int ret;
5561
5562         ctx = i915_gem_alloc_object(dev, 4096);
5563         if (!ctx) {
5564                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5565                 return NULL;
5566         }
5567
5568         mutex_lock(&dev->struct_mutex);
5569         ret = i915_gem_object_pin(ctx, 4096, true);
5570         if (ret) {
5571                 DRM_ERROR("failed to pin power context: %d\n", ret);
5572                 goto err_unref;
5573         }
5574
5575         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5576         if (ret) {
5577                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5578                 goto err_unpin;
5579         }
5580         mutex_unlock(&dev->struct_mutex);
5581
5582         return ctx;
5583
5584 err_unpin:
5585         i915_gem_object_unpin(ctx);
5586 err_unref:
5587         drm_gem_object_unreference(&ctx->base);
5588         mutex_unlock(&dev->struct_mutex);
5589         return NULL;
5590 }
5591
5592 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5593 {
5594         struct drm_i915_private *dev_priv = dev->dev_private;
5595         u16 rgvswctl;
5596
5597         rgvswctl = I915_READ16(MEMSWCTL);
5598         if (rgvswctl & MEMCTL_CMD_STS) {
5599                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5600                 return false; /* still busy with another command */
5601         }
5602
5603         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5604                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5605         I915_WRITE16(MEMSWCTL, rgvswctl);
5606         POSTING_READ16(MEMSWCTL);
5607
5608         rgvswctl |= MEMCTL_CMD_STS;
5609         I915_WRITE16(MEMSWCTL, rgvswctl);
5610
5611         return true;
5612 }
5613
5614 void ironlake_enable_drps(struct drm_device *dev)
5615 {
5616         struct drm_i915_private *dev_priv = dev->dev_private;
5617         u32 rgvmodectl = I915_READ(MEMMODECTL);
5618         u8 fmax, fmin, fstart, vstart;
5619
5620         /* Enable temp reporting */
5621         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5622         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5623
5624         /* 100ms RC evaluation intervals */
5625         I915_WRITE(RCUPEI, 100000);
5626         I915_WRITE(RCDNEI, 100000);
5627
5628         /* Set max/min thresholds to 90ms and 80ms respectively */
5629         I915_WRITE(RCBMAXAVG, 90000);
5630         I915_WRITE(RCBMINAVG, 80000);
5631
5632         I915_WRITE(MEMIHYST, 1);
5633
5634         /* Set up min, max, and cur for interrupt handling */
5635         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5636         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5637         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5638                 MEMMODE_FSTART_SHIFT;
5639
5640         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5641                 PXVFREQ_PX_SHIFT;
5642
5643         dev_priv->fmax = fmax; /* IPS callback will increase this */
5644         dev_priv->fstart = fstart;
5645
5646         dev_priv->max_delay = fstart;
5647         dev_priv->min_delay = fmin;
5648         dev_priv->cur_delay = fstart;
5649
5650         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5651                          fmax, fmin, fstart);
5652
5653         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5654
5655         /*
5656          * Interrupts will be enabled in ironlake_irq_postinstall
5657          */
5658
5659         I915_WRITE(VIDSTART, vstart);
5660         POSTING_READ(VIDSTART);
5661
5662         rgvmodectl |= MEMMODE_SWMODE_EN;
5663         I915_WRITE(MEMMODECTL, rgvmodectl);
5664
5665         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5666                 DRM_ERROR("stuck trying to change perf mode\n");
5667         msleep(1);
5668
5669         ironlake_set_drps(dev, fstart);
5670
5671         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5672                 I915_READ(0x112e0);
5673         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5674         dev_priv->last_count2 = I915_READ(0x112f4);
5675         getrawmonotonic(&dev_priv->last_time2);
5676 }
5677
5678 void ironlake_disable_drps(struct drm_device *dev)
5679 {
5680         struct drm_i915_private *dev_priv = dev->dev_private;
5681         u16 rgvswctl = I915_READ16(MEMSWCTL);
5682
5683         /* Ack interrupts, disable EFC interrupt */
5684         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5685         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5686         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5687         I915_WRITE(DEIIR, DE_PCU_EVENT);
5688         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5689
5690         /* Go back to the starting frequency */
5691         ironlake_set_drps(dev, dev_priv->fstart);
5692         msleep(1);
5693         rgvswctl |= MEMCTL_CMD_STS;
5694         I915_WRITE(MEMSWCTL, rgvswctl);
5695         msleep(1);
5696
5697 }
5698
5699 static unsigned long intel_pxfreq(u32 vidfreq)
5700 {
5701         unsigned long freq;
5702         int div = (vidfreq & 0x3f0000) >> 16;
5703         int post = (vidfreq & 0x3000) >> 12;
5704         int pre = (vidfreq & 0x7);
5705
5706         if (!pre)
5707                 return 0;
5708
5709         freq = ((div * 133333) / ((1<<post) * pre));
5710
5711         return freq;
5712 }
5713
5714 void intel_init_emon(struct drm_device *dev)
5715 {
5716         struct drm_i915_private *dev_priv = dev->dev_private;
5717         u32 lcfuse;
5718         u8 pxw[16];
5719         int i;
5720
5721         /* Disable to program */
5722         I915_WRITE(ECR, 0);
5723         POSTING_READ(ECR);
5724
5725         /* Program energy weights for various events */
5726         I915_WRITE(SDEW, 0x15040d00);
5727         I915_WRITE(CSIEW0, 0x007f0000);
5728         I915_WRITE(CSIEW1, 0x1e220004);
5729         I915_WRITE(CSIEW2, 0x04000004);
5730
5731         for (i = 0; i < 5; i++)
5732                 I915_WRITE(PEW + (i * 4), 0);
5733         for (i = 0; i < 3; i++)
5734                 I915_WRITE(DEW + (i * 4), 0);
5735
5736         /* Program P-state weights to account for frequency power adjustment */
5737         for (i = 0; i < 16; i++) {
5738                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5739                 unsigned long freq = intel_pxfreq(pxvidfreq);
5740                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5741                         PXVFREQ_PX_SHIFT;
5742                 unsigned long val;
5743
5744                 val = vid * vid;
5745                 val *= (freq / 1000);
5746                 val *= 255;
5747                 val /= (127*127*900);
5748                 if (val > 0xff)
5749                         DRM_ERROR("bad pxval: %ld\n", val);
5750                 pxw[i] = val;
5751         }
5752         /* Render standby states get 0 weight */
5753         pxw[14] = 0;
5754         pxw[15] = 0;
5755
5756         for (i = 0; i < 4; i++) {
5757                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5758                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5759                 I915_WRITE(PXW + (i * 4), val);
5760         }
5761
5762         /* Adjust magic regs to magic values (more experimental results) */
5763         I915_WRITE(OGW0, 0);
5764         I915_WRITE(OGW1, 0);
5765         I915_WRITE(EG0, 0x00007f00);
5766         I915_WRITE(EG1, 0x0000000e);
5767         I915_WRITE(EG2, 0x000e0000);
5768         I915_WRITE(EG3, 0x68000300);
5769         I915_WRITE(EG4, 0x42000000);
5770         I915_WRITE(EG5, 0x00140031);
5771         I915_WRITE(EG6, 0);
5772         I915_WRITE(EG7, 0);
5773
5774         for (i = 0; i < 8; i++)
5775                 I915_WRITE(PXWL + (i * 4), 0);
5776
5777         /* Enable PMON + select events */
5778         I915_WRITE(ECR, 0x80000019);
5779
5780         lcfuse = I915_READ(LCFUSE02);
5781
5782         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5783 }
5784
5785 void intel_init_clock_gating(struct drm_device *dev)
5786 {
5787         struct drm_i915_private *dev_priv = dev->dev_private;
5788
5789         /*
5790          * Disable clock gating reported to work incorrectly according to the
5791          * specs, but enable as much else as we can.
5792          */
5793         if (HAS_PCH_SPLIT(dev)) {
5794                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5795
5796                 if (IS_GEN5(dev)) {
5797                         /* Required for FBC */
5798                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5799                         /* Required for CxSR */
5800                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5801
5802                         I915_WRITE(PCH_3DCGDIS0,
5803                                    MARIUNIT_CLOCK_GATE_DISABLE |
5804                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5805                 }
5806
5807                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5808
5809                 /*
5810                  * On Ibex Peak and Cougar Point, we need to disable clock
5811                  * gating for the panel power sequencer or it will fail to
5812                  * start up when no ports are active.
5813                  */
5814                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5815
5816                 /*
5817                  * According to the spec the following bits should be set in
5818                  * order to enable memory self-refresh
5819                  * The bit 22/21 of 0x42004
5820                  * The bit 5 of 0x42020
5821                  * The bit 15 of 0x45000
5822                  */
5823                 if (IS_GEN5(dev)) {
5824                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5825                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5826                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5827                         I915_WRITE(ILK_DSPCLK_GATE,
5828                                         (I915_READ(ILK_DSPCLK_GATE) |
5829                                                 ILK_DPARB_CLK_GATE));
5830                         I915_WRITE(DISP_ARB_CTL,
5831                                         (I915_READ(DISP_ARB_CTL) |
5832                                                 DISP_FBC_WM_DIS));
5833                 I915_WRITE(WM3_LP_ILK, 0);
5834                 I915_WRITE(WM2_LP_ILK, 0);
5835                 I915_WRITE(WM1_LP_ILK, 0);
5836                 }
5837                 /*
5838                  * Based on the document from hardware guys the following bits
5839                  * should be set unconditionally in order to enable FBC.
5840                  * The bit 22 of 0x42000
5841                  * The bit 22 of 0x42004
5842                  * The bit 7,8,9 of 0x42020.
5843                  */
5844                 if (IS_IRONLAKE_M(dev)) {
5845                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5846                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5847                                    ILK_FBCQ_DIS);
5848                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5849                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5850                                    ILK_DPARB_GATE);
5851                         I915_WRITE(ILK_DSPCLK_GATE,
5852                                    I915_READ(ILK_DSPCLK_GATE) |
5853                                    ILK_DPFC_DIS1 |
5854                                    ILK_DPFC_DIS2 |
5855                                    ILK_CLK_FBC);
5856                 }
5857
5858                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5859                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5860                            ILK_ELPIN_409_SELECT);
5861
5862                 if (IS_GEN5(dev)) {
5863                         I915_WRITE(_3D_CHICKEN2,
5864                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5865                                    _3D_CHICKEN2_WM_READ_PIPELINED);
5866                 }
5867         } else if (IS_G4X(dev)) {
5868                 uint32_t dspclk_gate;
5869                 I915_WRITE(RENCLK_GATE_D1, 0);
5870                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5871                        GS_UNIT_CLOCK_GATE_DISABLE |
5872                        CL_UNIT_CLOCK_GATE_DISABLE);
5873                 I915_WRITE(RAMCLK_GATE_D, 0);
5874                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5875                         OVRUNIT_CLOCK_GATE_DISABLE |
5876                         OVCUNIT_CLOCK_GATE_DISABLE;
5877                 if (IS_GM45(dev))
5878                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5879                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5880         } else if (IS_CRESTLINE(dev)) {
5881                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5882                 I915_WRITE(RENCLK_GATE_D2, 0);
5883                 I915_WRITE(DSPCLK_GATE_D, 0);
5884                 I915_WRITE(RAMCLK_GATE_D, 0);
5885                 I915_WRITE16(DEUC, 0);
5886         } else if (IS_BROADWATER(dev)) {
5887                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5888                        I965_RCC_CLOCK_GATE_DISABLE |
5889                        I965_RCPB_CLOCK_GATE_DISABLE |
5890                        I965_ISC_CLOCK_GATE_DISABLE |
5891                        I965_FBC_CLOCK_GATE_DISABLE);
5892                 I915_WRITE(RENCLK_GATE_D2, 0);
5893         } else if (IS_GEN3(dev)) {
5894                 u32 dstate = I915_READ(D_STATE);
5895
5896                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5897                         DSTATE_DOT_CLOCK_GATING;
5898                 I915_WRITE(D_STATE, dstate);
5899         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5900                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5901         } else if (IS_I830(dev)) {
5902                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5903         }
5904
5905         /*
5906          * GPU can automatically power down the render unit if given a page
5907          * to save state.
5908          */
5909         if (IS_IRONLAKE_M(dev)) {
5910                 if (dev_priv->renderctx == NULL)
5911                         dev_priv->renderctx = intel_alloc_context_page(dev);
5912                 if (dev_priv->renderctx) {
5913                         struct drm_i915_gem_object *obj = dev_priv->renderctx;
5914                         if (BEGIN_LP_RING(4) == 0) {
5915                                 OUT_RING(MI_SET_CONTEXT);
5916                                 OUT_RING(obj->gtt_offset |
5917                                          MI_MM_SPACE_GTT |
5918                                          MI_SAVE_EXT_STATE_EN |
5919                                          MI_RESTORE_EXT_STATE_EN |
5920                                          MI_RESTORE_INHIBIT);
5921                                 OUT_RING(MI_NOOP);
5922                                 OUT_RING(MI_FLUSH);
5923                                 ADVANCE_LP_RING();
5924                         }
5925                 } else
5926                         DRM_DEBUG_KMS("Failed to allocate render context."
5927                                        "Disable RC6\n");
5928         }
5929
5930         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5931                 if (dev_priv->pwrctx == NULL)
5932                         dev_priv->pwrctx = intel_alloc_context_page(dev);
5933                 if (dev_priv->pwrctx) {
5934                         struct drm_i915_gem_object *obj = dev_priv->pwrctx;
5935                         I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
5936                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5937                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5938                 }
5939         }
5940 }
5941
5942 /* Set up chip specific display functions */
5943 static void intel_init_display(struct drm_device *dev)
5944 {
5945         struct drm_i915_private *dev_priv = dev->dev_private;
5946
5947         /* We always want a DPMS function */
5948         if (HAS_PCH_SPLIT(dev))
5949                 dev_priv->display.dpms = ironlake_crtc_dpms;
5950         else
5951                 dev_priv->display.dpms = i9xx_crtc_dpms;
5952
5953         if (I915_HAS_FBC(dev)) {
5954                 if (IS_IRONLAKE_M(dev)) {
5955                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5956                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5957                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5958                 } else if (IS_GM45(dev)) {
5959                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5960                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5961                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5962                 } else if (IS_CRESTLINE(dev)) {
5963                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5964                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5965                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5966                 }
5967                 /* 855GM needs testing */
5968         }
5969
5970         /* Returns the core display clock speed */
5971         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5972                 dev_priv->display.get_display_clock_speed =
5973                         i945_get_display_clock_speed;
5974         else if (IS_I915G(dev))
5975                 dev_priv->display.get_display_clock_speed =
5976                         i915_get_display_clock_speed;
5977         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5978                 dev_priv->display.get_display_clock_speed =
5979                         i9xx_misc_get_display_clock_speed;
5980         else if (IS_I915GM(dev))
5981                 dev_priv->display.get_display_clock_speed =
5982                         i915gm_get_display_clock_speed;
5983         else if (IS_I865G(dev))
5984                 dev_priv->display.get_display_clock_speed =
5985                         i865_get_display_clock_speed;
5986         else if (IS_I85X(dev))
5987                 dev_priv->display.get_display_clock_speed =
5988                         i855_get_display_clock_speed;
5989         else /* 852, 830 */
5990                 dev_priv->display.get_display_clock_speed =
5991                         i830_get_display_clock_speed;
5992
5993         /* For FIFO watermark updates */
5994         if (HAS_PCH_SPLIT(dev)) {
5995                 if (IS_GEN5(dev)) {
5996                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5997                                 dev_priv->display.update_wm = ironlake_update_wm;
5998                         else {
5999                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6000                                               "Disable CxSR\n");
6001                                 dev_priv->display.update_wm = NULL;
6002                         }
6003                 } else
6004                         dev_priv->display.update_wm = NULL;
6005         } else if (IS_PINEVIEW(dev)) {
6006                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6007                                             dev_priv->is_ddr3,
6008                                             dev_priv->fsb_freq,
6009                                             dev_priv->mem_freq)) {
6010                         DRM_INFO("failed to find known CxSR latency "
6011                                  "(found ddr%s fsb freq %d, mem freq %d), "
6012                                  "disabling CxSR\n",
6013                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6014                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6015                         /* Disable CxSR and never update its watermark again */
6016                         pineview_disable_cxsr(dev);
6017                         dev_priv->display.update_wm = NULL;
6018                 } else
6019                         dev_priv->display.update_wm = pineview_update_wm;
6020         } else if (IS_G4X(dev))
6021                 dev_priv->display.update_wm = g4x_update_wm;
6022         else if (IS_GEN4(dev))
6023                 dev_priv->display.update_wm = i965_update_wm;
6024         else if (IS_GEN3(dev)) {
6025                 dev_priv->display.update_wm = i9xx_update_wm;
6026                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6027         } else if (IS_I85X(dev)) {
6028                 dev_priv->display.update_wm = i9xx_update_wm;
6029                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6030         } else {
6031                 dev_priv->display.update_wm = i830_update_wm;
6032                 if (IS_845G(dev))
6033                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6034                 else
6035                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6036         }
6037 }
6038
6039 /*
6040  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6041  * resume, or other times.  This quirk makes sure that's the case for
6042  * affected systems.
6043  */
6044 static void quirk_pipea_force (struct drm_device *dev)
6045 {
6046         struct drm_i915_private *dev_priv = dev->dev_private;
6047
6048         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6049         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6050 }
6051
6052 struct intel_quirk {
6053         int device;
6054         int subsystem_vendor;
6055         int subsystem_device;
6056         void (*hook)(struct drm_device *dev);
6057 };
6058
6059 struct intel_quirk intel_quirks[] = {
6060         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6061         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6062         /* HP Mini needs pipe A force quirk (LP: #322104) */
6063         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6064
6065         /* Thinkpad R31 needs pipe A force quirk */
6066         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6067         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6068         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6069
6070         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6071         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6072         /* ThinkPad X40 needs pipe A force quirk */
6073
6074         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6075         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6076
6077         /* 855 & before need to leave pipe A & dpll A up */
6078         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6079         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6080 };
6081
6082 static void intel_init_quirks(struct drm_device *dev)
6083 {
6084         struct pci_dev *d = dev->pdev;
6085         int i;
6086
6087         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6088                 struct intel_quirk *q = &intel_quirks[i];
6089
6090                 if (d->device == q->device &&
6091                     (d->subsystem_vendor == q->subsystem_vendor ||
6092                      q->subsystem_vendor == PCI_ANY_ID) &&
6093                     (d->subsystem_device == q->subsystem_device ||
6094                      q->subsystem_device == PCI_ANY_ID))
6095                         q->hook(dev);
6096         }
6097 }
6098
6099 /* Disable the VGA plane that we never use */
6100 static void i915_disable_vga(struct drm_device *dev)
6101 {
6102         struct drm_i915_private *dev_priv = dev->dev_private;
6103         u8 sr1;
6104         u32 vga_reg;
6105
6106         if (HAS_PCH_SPLIT(dev))
6107                 vga_reg = CPU_VGACNTRL;
6108         else
6109                 vga_reg = VGACNTRL;
6110
6111         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6112         outb(1, VGA_SR_INDEX);
6113         sr1 = inb(VGA_SR_DATA);
6114         outb(sr1 | 1<<5, VGA_SR_DATA);
6115         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6116         udelay(300);
6117
6118         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6119         POSTING_READ(vga_reg);
6120 }
6121
6122 void intel_modeset_init(struct drm_device *dev)
6123 {
6124         struct drm_i915_private *dev_priv = dev->dev_private;
6125         int i;
6126
6127         drm_mode_config_init(dev);
6128
6129         dev->mode_config.min_width = 0;
6130         dev->mode_config.min_height = 0;
6131
6132         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6133
6134         intel_init_quirks(dev);
6135
6136         intel_init_display(dev);
6137
6138         if (IS_GEN2(dev)) {
6139                 dev->mode_config.max_width = 2048;
6140                 dev->mode_config.max_height = 2048;
6141         } else if (IS_GEN3(dev)) {
6142                 dev->mode_config.max_width = 4096;
6143                 dev->mode_config.max_height = 4096;
6144         } else {
6145                 dev->mode_config.max_width = 8192;
6146                 dev->mode_config.max_height = 8192;
6147         }
6148
6149         /* set memory base */
6150         if (IS_GEN2(dev))
6151                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6152         else
6153                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6154
6155         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6156                 dev_priv->num_pipe = 2;
6157         else
6158                 dev_priv->num_pipe = 1;
6159         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6160                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6161
6162         for (i = 0; i < dev_priv->num_pipe; i++) {
6163                 intel_crtc_init(dev, i);
6164         }
6165
6166         intel_setup_outputs(dev);
6167
6168         intel_init_clock_gating(dev);
6169
6170         /* Just disable it once at startup */
6171         i915_disable_vga(dev);
6172
6173         if (IS_IRONLAKE_M(dev)) {
6174                 ironlake_enable_drps(dev);
6175                 intel_init_emon(dev);
6176         }
6177
6178         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6179         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6180                     (unsigned long)dev);
6181
6182         intel_setup_overlay(dev);
6183 }
6184
6185 void intel_modeset_cleanup(struct drm_device *dev)
6186 {
6187         struct drm_i915_private *dev_priv = dev->dev_private;
6188         struct drm_crtc *crtc;
6189         struct intel_crtc *intel_crtc;
6190
6191         drm_kms_helper_poll_fini(dev);
6192         mutex_lock(&dev->struct_mutex);
6193
6194         intel_unregister_dsm_handler();
6195
6196
6197         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6198                 /* Skip inactive CRTCs */
6199                 if (!crtc->fb)
6200                         continue;
6201
6202                 intel_crtc = to_intel_crtc(crtc);
6203                 intel_increase_pllclock(crtc);
6204         }
6205
6206         if (dev_priv->display.disable_fbc)
6207                 dev_priv->display.disable_fbc(dev);
6208
6209         if (dev_priv->renderctx) {
6210                 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6211
6212                 I915_WRITE(CCID, obj->gtt_offset &~ CCID_EN);
6213                 POSTING_READ(CCID);
6214
6215                 i915_gem_object_unpin(obj);
6216                 drm_gem_object_unreference(&obj->base);
6217                 dev_priv->renderctx = NULL;
6218         }
6219
6220         if (dev_priv->pwrctx) {
6221                 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6222
6223                 I915_WRITE(PWRCTXA, obj->gtt_offset &~ PWRCTX_EN);
6224                 POSTING_READ(PWRCTXA);
6225
6226                 i915_gem_object_unpin(obj);
6227                 drm_gem_object_unreference(&obj->base);
6228                 dev_priv->pwrctx = NULL;
6229         }
6230
6231         if (IS_IRONLAKE_M(dev))
6232                 ironlake_disable_drps(dev);
6233
6234         mutex_unlock(&dev->struct_mutex);
6235
6236         /* Disable the irq before mode object teardown, for the irq might
6237          * enqueue unpin/hotplug work. */
6238         drm_irq_uninstall(dev);
6239         cancel_work_sync(&dev_priv->hotplug_work);
6240
6241         /* Shut off idle work before the crtcs get freed. */
6242         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6243                 intel_crtc = to_intel_crtc(crtc);
6244                 del_timer_sync(&intel_crtc->idle_timer);
6245         }
6246         del_timer_sync(&dev_priv->idle_timer);
6247         cancel_work_sync(&dev_priv->idle_work);
6248
6249         drm_mode_config_cleanup(dev);
6250 }
6251
6252 /*
6253  * Return which encoder is currently attached for connector.
6254  */
6255 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6256 {
6257         return &intel_attached_encoder(connector)->base;
6258 }
6259
6260 void intel_connector_attach_encoder(struct intel_connector *connector,
6261                                     struct intel_encoder *encoder)
6262 {
6263         connector->encoder = encoder;
6264         drm_mode_connector_attach_encoder(&connector->base,
6265                                           &encoder->base);
6266 }
6267
6268 /*
6269  * set vga decode state - true == enable VGA decode
6270  */
6271 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6272 {
6273         struct drm_i915_private *dev_priv = dev->dev_private;
6274         u16 gmch_ctrl;
6275
6276         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6277         if (state)
6278                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6279         else
6280                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6281         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6282         return 0;
6283 }
6284
6285 #ifdef CONFIG_DEBUG_FS
6286 #include <linux/seq_file.h>
6287
6288 struct intel_display_error_state {
6289         struct intel_cursor_error_state {
6290                 u32 control;
6291                 u32 position;
6292                 u32 base;
6293                 u32 size;
6294         } cursor[2];
6295
6296         struct intel_pipe_error_state {
6297                 u32 conf;
6298                 u32 source;
6299
6300                 u32 htotal;
6301                 u32 hblank;
6302                 u32 hsync;
6303                 u32 vtotal;
6304                 u32 vblank;
6305                 u32 vsync;
6306         } pipe[2];
6307
6308         struct intel_plane_error_state {
6309                 u32 control;
6310                 u32 stride;
6311                 u32 size;
6312                 u32 pos;
6313                 u32 addr;
6314                 u32 surface;
6315                 u32 tile_offset;
6316         } plane[2];
6317 };
6318
6319 struct intel_display_error_state *
6320 intel_display_capture_error_state(struct drm_device *dev)
6321 {
6322         drm_i915_private_t *dev_priv = dev->dev_private;
6323         struct intel_display_error_state *error;
6324         int i;
6325
6326         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6327         if (error == NULL)
6328                 return NULL;
6329
6330         for (i = 0; i < 2; i++) {
6331                 error->cursor[i].control = I915_READ(CURCNTR(i));
6332                 error->cursor[i].position = I915_READ(CURPOS(i));
6333                 error->cursor[i].base = I915_READ(CURBASE(i));
6334
6335                 error->plane[i].control = I915_READ(DSPCNTR(i));
6336                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6337                 error->plane[i].size = I915_READ(DSPSIZE(i));
6338                 error->plane[i].pos= I915_READ(DSPPOS(i));
6339                 error->plane[i].addr = I915_READ(DSPADDR(i));
6340                 if (INTEL_INFO(dev)->gen >= 4) {
6341                         error->plane[i].surface = I915_READ(DSPSURF(i));
6342                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6343                 }
6344
6345                 error->pipe[i].conf = I915_READ(PIPECONF(i));
6346                 error->pipe[i].source = I915_READ(PIPESRC(i));
6347                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6348                 error->pipe[i].hblank = I915_READ(HBLANK(i));
6349                 error->pipe[i].hsync = I915_READ(HSYNC(i));
6350                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6351                 error->pipe[i].vblank = I915_READ(VBLANK(i));
6352                 error->pipe[i].vsync = I915_READ(VSYNC(i));
6353         }
6354
6355         return error;
6356 }
6357
6358 void
6359 intel_display_print_error_state(struct seq_file *m,
6360                                 struct drm_device *dev,
6361                                 struct intel_display_error_state *error)
6362 {
6363         int i;
6364
6365         for (i = 0; i < 2; i++) {
6366                 seq_printf(m, "Pipe [%d]:\n", i);
6367                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
6368                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
6369                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
6370                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
6371                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
6372                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
6373                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
6374                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
6375
6376                 seq_printf(m, "Plane [%d]:\n", i);
6377                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
6378                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
6379                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
6380                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
6381                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
6382                 if (INTEL_INFO(dev)->gen >= 4) {
6383                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
6384                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
6385                 }
6386
6387                 seq_printf(m, "Cursor [%d]:\n", i);
6388                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
6389                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
6390                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
6391         }
6392 }
6393 #endif