drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/scatterlist.h>
  21
  22 #include <linux/leds.h>
  23
  24 #include <linux/mmc/host.h>
  25
  26 #include "sdhci.h"
  27
  28 #define DRIVER_NAME "sdhci"
  29
  30 #define DBG(f, x...) \
  31         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  32
  33 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  34         defined(CONFIG_MMC_SDHCI_MODULE))
  35 #define SDHCI_USE_LEDS_CLASS
  36 #endif
  37
  38 static unsigned int debug_quirks = 0;
  39
  40 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  41 static void sdhci_finish_data(struct sdhci_host *);
  42
  43 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  44 static void sdhci_finish_command(struct sdhci_host *);
  45
  46 static void sdhci_dumpregs(struct sdhci_host *host)
  47 {
  48         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  49
  50         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  51                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  52                 sdhci_readw(host, SDHCI_HOST_VERSION));
  53         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  54                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  55                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  56         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  57                 sdhci_readl(host, SDHCI_ARGUMENT),
  58                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  59         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  60                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  61                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  62         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  63                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  64                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  65         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  66                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  67                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  68         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  69                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  70                 sdhci_readl(host, SDHCI_INT_STATUS));
  71         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  72                 sdhci_readl(host, SDHCI_INT_ENABLE),
  73                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  74         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  75                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  76                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  77         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
  78                 sdhci_readl(host, SDHCI_CAPABILITIES),
  79                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  80
  81         if (host->flags & SDHCI_USE_ADMA)
  82                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  83                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  84                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  85
  86         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  87 }
  88
  89 /*****************************************************************************\
  90  *                                                                           *
  91  * Low level functions                                                       *
  92  *                                                                           *
  93 \*****************************************************************************/
  94
  95 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
  96 {
  97         u32 ier;
  98
  99         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 100         ier &= ~clear;
 101         ier |= set;
 102         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 103         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 104 }
 105
 106 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 107 {
 108         sdhci_clear_set_irqs(host, 0, irqs);
 109 }
 110
 111 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 112 {
 113         sdhci_clear_set_irqs(host, irqs, 0);
 114 }
 115
 116 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 117 {
 118         u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
 119
 120         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 121                 return;
 122
 123         if (enable)
 124                 sdhci_unmask_irqs(host, irqs);
 125         else
 126                 sdhci_mask_irqs(host, irqs);
 127 }
 128
 129 static void sdhci_enable_card_detection(struct sdhci_host *host)
 130 {
 131         sdhci_set_card_detection(host, true);
 132 }
 133
 134 static void sdhci_disable_card_detection(struct sdhci_host *host)
 135 {
 136         sdhci_set_card_detection(host, false);
 137 }
 138
 139 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 140 {
 141         unsigned long timeout;
 142         u32 uninitialized_var(ier);
 143
 144         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 145                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 146                         SDHCI_CARD_PRESENT))
 147                         return;
 148         }
 149
 150         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 151                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 152
 153         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 154
 155         if (mask & SDHCI_RESET_ALL)
 156                 host->clock = 0;
 157
 158         /* Wait max 100 ms */
 159         timeout = 100;
 160
 161         /* hw clears the bit when it's done */
 162         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 163                 if (timeout == 0) {
 164                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 165                                 mmc_hostname(host->mmc), (int)mask);
 166                         sdhci_dumpregs(host);
 167                         return;
 168                 }
 169                 timeout--;
 170                 mdelay(1);
 171         }
 172
 173         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 174                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 175 }
 176
 177 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 178
 179 static void sdhci_init(struct sdhci_host *host, int soft)
 180 {
 181         if (soft)
 182                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 183         else
 184                 sdhci_reset(host, SDHCI_RESET_ALL);
 185
 186         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 187                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 188                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 189                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 190                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 191
 192         if (soft) {
 193                 /* force clock reconfiguration */
 194                 host->clock = 0;
 195                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 196         }
 197 }
 198
 199 static void sdhci_reinit(struct sdhci_host *host)
 200 {
 201         sdhci_init(host, 0);
 202         sdhci_enable_card_detection(host);
 203 }
 204
 205 static void sdhci_activate_led(struct sdhci_host *host)
 206 {
 207         u8 ctrl;
 208
 209         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 210         ctrl |= SDHCI_CTRL_LED;
 211         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 212 }
 213
 214 static void sdhci_deactivate_led(struct sdhci_host *host)
 215 {
 216         u8 ctrl;
 217
 218         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 219         ctrl &= ~SDHCI_CTRL_LED;
 220         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 221 }
 222
 223 #ifdef SDHCI_USE_LEDS_CLASS
 224 static void sdhci_led_control(struct led_classdev *led,
 225         enum led_brightness brightness)
 226 {
 227         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 228         unsigned long flags;
 229
 230         spin_lock_irqsave(&host->lock, flags);
 231
 232         if (brightness == LED_OFF)
 233                 sdhci_deactivate_led(host);
 234         else
 235                 sdhci_activate_led(host);
 236
 237         spin_unlock_irqrestore(&host->lock, flags);
 238 }
 239 #endif
 240
 241 /*****************************************************************************\
 242  *                                                                           *
 243  * Core functions                                                            *
 244  *                                                                           *
 245 \*****************************************************************************/
 246
 247 static void sdhci_read_block_pio(struct sdhci_host *host)
 248 {
 249         unsigned long flags;
 250         size_t blksize, len, chunk;
 251         u32 uninitialized_var(scratch);
 252         u8 *buf;
 253
 254         DBG("PIO reading\n");
 255
 256         blksize = host->data->blksz;
 257         chunk = 0;
 258
 259         local_irq_save(flags);
 260
 261         while (blksize) {
 262                 if (!sg_miter_next(&host->sg_miter))
 263                         BUG();
 264
 265                 len = min(host->sg_miter.length, blksize);
 266
 267                 blksize -= len;
 268                 host->sg_miter.consumed = len;
 269
 270                 buf = host->sg_miter.addr;
 271
 272                 while (len) {
 273                         if (chunk == 0) {
 274                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 275                                 chunk = 4;
 276                         }
 277
 278                         *buf = scratch & 0xFF;
 279
 280                         buf++;
 281                         scratch >>= 8;
 282                         chunk--;
 283                         len--;
 284                 }
 285         }
 286
 287         sg_miter_stop(&host->sg_miter);
 288
 289         local_irq_restore(flags);
 290 }
 291
 292 static void sdhci_write_block_pio(struct sdhci_host *host)
 293 {
 294         unsigned long flags;
 295         size_t blksize, len, chunk;
 296         u32 scratch;
 297         u8 *buf;
 298
 299         DBG("PIO writing\n");
 300
 301         blksize = host->data->blksz;
 302         chunk = 0;
 303         scratch = 0;
 304
 305         local_irq_save(flags);
 306
 307         while (blksize) {
 308                 if (!sg_miter_next(&host->sg_miter))
 309                         BUG();
 310
 311                 len = min(host->sg_miter.length, blksize);
 312
 313                 blksize -= len;
 314                 host->sg_miter.consumed = len;
 315
 316                 buf = host->sg_miter.addr;
 317
 318                 while (len) {
 319                         scratch |= (u32)*buf << (chunk * 8);
 320
 321                         buf++;
 322                         chunk++;
 323                         len--;
 324
 325                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 326                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 327                                 chunk = 0;
 328                                 scratch = 0;
 329                         }
 330                 }
 331         }
 332
 333         sg_miter_stop(&host->sg_miter);
 334
 335         local_irq_restore(flags);
 336 }
 337
 338 static void sdhci_transfer_pio(struct sdhci_host *host)
 339 {
 340         u32 mask;
 341
 342         BUG_ON(!host->data);
 343
 344         if (host->blocks == 0)
 345                 return;
 346
 347         if (host->data->flags & MMC_DATA_READ)
 348                 mask = SDHCI_DATA_AVAILABLE;
 349         else
 350                 mask = SDHCI_SPACE_AVAILABLE;
 351
 352         /*
 353          * Some controllers (JMicron JMB38x) mess up the buffer bits
 354          * for transfers < 4 bytes. As long as it is just one block,
 355          * we can ignore the bits.
 356          */
 357         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 358                 (host->data->blocks == 1))
 359                 mask = ~0;
 360
 361         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 362                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 363                         udelay(100);
 364
 365                 if (host->data->flags & MMC_DATA_READ)
 366                         sdhci_read_block_pio(host);
 367                 else
 368                         sdhci_write_block_pio(host);
 369
 370                 host->blocks--;
 371                 if (host->blocks == 0)
 372                         break;
 373         }
 374
 375         DBG("PIO transfer complete.\n");
 376 }
 377
 378 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 379 {
 380         local_irq_save(*flags);
 381         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 382 }
 383
 384 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 385 {
 386         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 387         local_irq_restore(*flags);
 388 }
 389
 390 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 391 {
 392         __le32 *dataddr = (__le32 __force *)(desc + 4);
 393         __le16 *cmdlen = (__le16 __force *)desc;
 394
 395         /* SDHCI specification says ADMA descriptors should be 4 byte
 396          * aligned, so using 16 or 32bit operations should be safe. */
 397
 398         cmdlen[0] = cpu_to_le16(cmd);
 399         cmdlen[1] = cpu_to_le16(len);
 400
 401         dataddr[0] = cpu_to_le32(addr);
 402 }
 403
 404 static int sdhci_adma_table_pre(struct sdhci_host *host,
 405         struct mmc_data *data)
 406 {
 407         int direction;
 408
 409         u8 *desc;
 410         u8 *align;
 411         dma_addr_t addr;
 412         dma_addr_t align_addr;
 413         int len, offset;
 414
 415         struct scatterlist *sg;
 416         int i;
 417         char *buffer;
 418         unsigned long flags;
 419
 420         /*
 421          * The spec does not specify endianness of descriptor table.
 422          * We currently guess that it is LE.
 423          */
 424
 425         if (data->flags & MMC_DATA_READ)
 426                 direction = DMA_FROM_DEVICE;
 427         else
 428                 direction = DMA_TO_DEVICE;
 429
 430         /*
 431          * The ADMA descriptor table is mapped further down as we
 432          * need to fill it with data first.
 433          */
 434
 435         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 436                 host->align_buffer, 128 * 4, direction);
 437         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 438                 goto fail;
 439         BUG_ON(host->align_addr & 0x3);
 440
 441         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 442                 data->sg, data->sg_len, direction);
 443         if (host->sg_count == 0)
 444                 goto unmap_align;
 445
 446         desc = host->adma_desc;
 447         align = host->align_buffer;
 448
 449         align_addr = host->align_addr;
 450
 451         for_each_sg(data->sg, sg, host->sg_count, i) {
 452                 addr = sg_dma_address(sg);
 453                 len = sg_dma_len(sg);
 454
 455                 /*
 456                  * The SDHCI specification states that ADMA
 457                  * addresses must be 32-bit aligned. If they
 458                  * aren't, then we use a bounce buffer for
 459                  * the (up to three) bytes that screw up the
 460                  * alignment.
 461                  */
 462                 offset = (4 - (addr & 0x3)) & 0x3;
 463                 if (offset) {
 464                         if (data->flags & MMC_DATA_WRITE) {
 465                                 buffer = sdhci_kmap_atomic(sg, &flags);
 466                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 467                                 memcpy(align, buffer, offset);
 468                                 sdhci_kunmap_atomic(buffer, &flags);
 469                         }
 470
 471                         /* tran, valid */
 472                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 473
 474                         BUG_ON(offset > 65536);
 475
 476                         align += 4;
 477                         align_addr += 4;
 478
 479                         desc += 8;
 480
 481                         addr += offset;
 482                         len -= offset;
 483                 }
 484
 485                 BUG_ON(len > 65536);
 486
 487                 /* tran, valid */
 488                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 489                 desc += 8;
 490
 491                 /*
 492                  * If this triggers then we have a calculation bug
 493                  * somewhere. :/
 494                  */
 495                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 496         }
 497
 498         /*
 499          * Add a terminating entry.
 500          */
 501
 502         /* nop, end, valid */
 503         sdhci_set_adma_desc(desc, 0, 0, 0x3);
 504
 505         /*
 506          * Resync align buffer as we might have changed it.
 507          */
 508         if (data->flags & MMC_DATA_WRITE) {
 509                 dma_sync_single_for_device(mmc_dev(host->mmc),
 510                         host->align_addr, 128 * 4, direction);
 511         }
 512
 513         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 514                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 515         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 516                 goto unmap_entries;
 517         BUG_ON(host->adma_addr & 0x3);
 518
 519         return 0;
 520
 521 unmap_entries:
 522         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 523                 data->sg_len, direction);
 524 unmap_align:
 525         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 526                 128 * 4, direction);
 527 fail:
 528         return -EINVAL;
 529 }
 530
 531 static void sdhci_adma_table_post(struct sdhci_host *host,
 532         struct mmc_data *data)
 533 {
 534         int direction;
 535
 536         struct scatterlist *sg;
 537         int i, size;
 538         u8 *align;
 539         char *buffer;
 540         unsigned long flags;
 541
 542         if (data->flags & MMC_DATA_READ)
 543                 direction = DMA_FROM_DEVICE;
 544         else
 545                 direction = DMA_TO_DEVICE;
 546
 547         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 548                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 549
 550         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 551                 128 * 4, direction);
 552
 553         if (data->flags & MMC_DATA_READ) {
 554                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 555                         data->sg_len, direction);
 556
 557                 align = host->align_buffer;
 558
 559                 for_each_sg(data->sg, sg, host->sg_count, i) {
 560                         if (sg_dma_address(sg) & 0x3) {
 561                                 size = 4 - (sg_dma_address(sg) & 0x3);
 562
 563                                 buffer = sdhci_kmap_atomic(sg, &flags);
 564                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 565                                 memcpy(buffer, align, size);
 566                                 sdhci_kunmap_atomic(buffer, &flags);
 567
 568                                 align += 4;
 569                         }
 570                 }
 571         }
 572
 573         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 574                 data->sg_len, direction);
 575 }
 576
 577 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
 578 {
 579         u8 count;
 580         unsigned target_timeout, current_timeout;
 581
 582         /*
 583          * If the host controller provides us with an incorrect timeout
 584          * value, just skip the check and use 0xE.  The hardware may take
 585          * longer to time out, but that's much better than having a too-short
 586          * timeout value.
 587          */
 588         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 589                 return 0xE;
 590
 591         /* timeout in us */
 592         target_timeout = data->timeout_ns / 1000 +
 593                 data->timeout_clks / host->clock;
 594
 595         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
 596                 host->timeout_clk = host->clock / 1000;
 597
 598         /*
 599          * Figure out needed cycles.
 600          * We do this in steps in order to fit inside a 32 bit int.
 601          * The first step is the minimum timeout, which will have a
 602          * minimum resolution of 6 bits:
 603          * (1) 2^13*1000 > 2^22,
 604          * (2) host->timeout_clk < 2^16
 605          *     =>
 606          *     (1) / (2) > 2^6
 607          */
 608         count = 0;
 609         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 610         while (current_timeout < target_timeout) {
 611                 count++;
 612                 current_timeout <<= 1;
 613                 if (count >= 0xF)
 614                         break;
 615         }
 616
 617         if (count >= 0xF) {
 618                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 619                         mmc_hostname(host->mmc));
 620                 count = 0xE;
 621         }
 622
 623         return count;
 624 }
 625
 626 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 627 {
 628         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 629         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 630
 631         if (host->flags & SDHCI_REQ_USE_DMA)
 632                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 633         else
 634                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 635 }
 636
 637 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 638 {
 639         u8 count;
 640         u8 ctrl;
 641         int ret;
 642
 643         WARN_ON(host->data);
 644
 645         if (data == NULL)
 646                 return;
 647
 648         /* Sanity checks */
 649         BUG_ON(data->blksz * data->blocks > 524288);
 650         BUG_ON(data->blksz > host->mmc->max_blk_size);
 651         BUG_ON(data->blocks > 65535);
 652
 653         host->data = data;
 654         host->data_early = 0;
 655
 656         count = sdhci_calc_timeout(host, data);
 657         sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 658
 659         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 660                 host->flags |= SDHCI_REQ_USE_DMA;
 661
 662         /*
 663          * FIXME: This doesn't account for merging when mapping the
 664          * scatterlist.
 665          */
 666         if (host->flags & SDHCI_REQ_USE_DMA) {
 667                 int broken, i;
 668                 struct scatterlist *sg;
 669
 670                 broken = 0;
 671                 if (host->flags & SDHCI_USE_ADMA) {
 672                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 673                                 broken = 1;
 674                 } else {
 675                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 676                                 broken = 1;
 677                 }
 678
 679                 if (unlikely(broken)) {
 680                         for_each_sg(data->sg, sg, data->sg_len, i) {
 681                                 if (sg->length & 0x3) {
 682                                         DBG("Reverting to PIO because of "
 683                                                 "transfer size (%d)\n",
 684                                                 sg->length);
 685                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 686                                         break;
 687                                 }
 688                         }
 689                 }
 690         }
 691
 692         /*
 693          * The assumption here being that alignment is the same after
 694          * translation to device address space.
 695          */
 696         if (host->flags & SDHCI_REQ_USE_DMA) {
 697                 int broken, i;
 698                 struct scatterlist *sg;
 699
 700                 broken = 0;
 701                 if (host->flags & SDHCI_USE_ADMA) {
 702                         /*
 703                          * As we use 3 byte chunks to work around
 704                          * alignment problems, we need to check this
 705                          * quirk.
 706                          */
 707                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 708                                 broken = 1;
 709                 } else {
 710                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 711                                 broken = 1;
 712                 }
 713
 714                 if (unlikely(broken)) {
 715                         for_each_sg(data->sg, sg, data->sg_len, i) {
 716                                 if (sg->offset & 0x3) {
 717                                         DBG("Reverting to PIO because of "
 718                                                 "bad alignment\n");
 719                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 720                                         break;
 721                                 }
 722                         }
 723                 }
 724         }
 725
 726         if (host->flags & SDHCI_REQ_USE_DMA) {
 727                 if (host->flags & SDHCI_USE_ADMA) {
 728                         ret = sdhci_adma_table_pre(host, data);
 729                         if (ret) {
 730                                 /*
 731                                  * This only happens when someone fed
 732                                  * us an invalid request.
 733                                  */
 734                                 WARN_ON(1);
 735                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 736                         } else {
 737                                 sdhci_writel(host, host->adma_addr,
 738                                         SDHCI_ADMA_ADDRESS);
 739                         }
 740                 } else {
 741                         int sg_cnt;
 742
 743                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 744                                         data->sg, data->sg_len,
 745                                         (data->flags & MMC_DATA_READ) ?
 746                                                 DMA_FROM_DEVICE :
 747                                                 DMA_TO_DEVICE);
 748                         if (sg_cnt == 0) {
 749                                 /*
 750                                  * This only happens when someone fed
 751                                  * us an invalid request.
 752                                  */
 753                                 WARN_ON(1);
 754                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 755                         } else {
 756                                 WARN_ON(sg_cnt != 1);
 757                                 sdhci_writel(host, sg_dma_address(data->sg),
 758                                         SDHCI_DMA_ADDRESS);
 759                         }
 760                 }
 761         }
 762
 763         /*
 764          * Always adjust the DMA selection as some controllers
 765          * (e.g. JMicron) can't do PIO properly when the selection
 766          * is ADMA.
 767          */
 768         if (host->version >= SDHCI_SPEC_200) {
 769                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 770                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 771                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 772                         (host->flags & SDHCI_USE_ADMA))
 773                         ctrl |= SDHCI_CTRL_ADMA32;
 774                 else
 775                         ctrl |= SDHCI_CTRL_SDMA;
 776                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 777         }
 778
 779         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 780                 int flags;
 781
 782                 flags = SG_MITER_ATOMIC;
 783                 if (host->data->flags & MMC_DATA_READ)
 784                         flags |= SG_MITER_TO_SG;
 785                 else
 786                         flags |= SG_MITER_FROM_SG;
 787                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 788                 host->blocks = data->blocks;
 789         }
 790
 791         sdhci_set_transfer_irqs(host);
 792
 793         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 794         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
 795         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 796 }
 797
 798 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 799         struct mmc_data *data)
 800 {
 801         u16 mode;
 802
 803         if (data == NULL)
 804                 return;
 805
 806         WARN_ON(!host->data);
 807
 808         mode = SDHCI_TRNS_BLK_CNT_EN;
 809         if (data->blocks > 1)
 810                 mode |= SDHCI_TRNS_MULTI;
 811         if (data->flags & MMC_DATA_READ)
 812                 mode |= SDHCI_TRNS_READ;
 813         if (host->flags & SDHCI_REQ_USE_DMA)
 814                 mode |= SDHCI_TRNS_DMA;
 815
 816         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 817 }
 818
 819 static void sdhci_finish_data(struct sdhci_host *host)
 820 {
 821         struct mmc_data *data;
 822
 823         BUG_ON(!host->data);
 824
 825         data = host->data;
 826         host->data = NULL;
 827
 828         if (host->flags & SDHCI_REQ_USE_DMA) {
 829                 if (host->flags & SDHCI_USE_ADMA)
 830                         sdhci_adma_table_post(host, data);
 831                 else {
 832                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 833                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 834                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 835                 }
 836         }
 837
 838         /*
 839          * The specification states that the block count register must
 840          * be updated, but it does not specify at what point in the
 841          * data flow. That makes the register entirely useless to read
 842          * back so we have to assume that nothing made it to the card
 843          * in the event of an error.
 844          */
 845         if (data->error)
 846                 data->bytes_xfered = 0;
 847         else
 848                 data->bytes_xfered = data->blksz * data->blocks;
 849
 850         if (data->stop) {
 851                 /*
 852                  * The controller needs a reset of internal state machines
 853                  * upon error conditions.
 854                  */
 855                 if (data->error) {
 856                         sdhci_reset(host, SDHCI_RESET_CMD);
 857                         sdhci_reset(host, SDHCI_RESET_DATA);
 858                 }
 859
 860                 sdhci_send_command(host, data->stop);
 861         } else
 862                 tasklet_schedule(&host->finish_tasklet);
 863 }
 864
 865 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 866 {
 867         int flags;
 868         u32 mask;
 869         unsigned long timeout;
 870
 871         WARN_ON(host->cmd);
 872
 873         /* Wait max 10 ms */
 874         timeout = 10;
 875
 876         mask = SDHCI_CMD_INHIBIT;
 877         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 878                 mask |= SDHCI_DATA_INHIBIT;
 879
 880         /* We shouldn't wait for data inihibit for stop commands, even
 881            though they might use busy signaling */
 882         if (host->mrq->data && (cmd == host->mrq->data->stop))
 883                 mask &= ~SDHCI_DATA_INHIBIT;
 884
 885         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 886                 if (timeout == 0) {
 887                         printk(KERN_ERR "%s: Controller never released "
 888                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 889                         sdhci_dumpregs(host);
 890                         cmd->error = -EIO;
 891                         tasklet_schedule(&host->finish_tasklet);
 892                         return;
 893                 }
 894                 timeout--;
 895                 mdelay(1);
 896         }
 897
 898         mod_timer(&host->timer, jiffies + 10 * HZ);
 899
 900         host->cmd = cmd;
 901
 902         sdhci_prepare_data(host, cmd->data);
 903
 904         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 905
 906         sdhci_set_transfer_mode(host, cmd->data);
 907
 908         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 909                 printk(KERN_ERR "%s: Unsupported response type!\n",
 910                         mmc_hostname(host->mmc));
 911                 cmd->error = -EINVAL;
 912                 tasklet_schedule(&host->finish_tasklet);
 913                 return;
 914         }
 915
 916         if (!(cmd->flags & MMC_RSP_PRESENT))
 917                 flags = SDHCI_CMD_RESP_NONE;
 918         else if (cmd->flags & MMC_RSP_136)
 919                 flags = SDHCI_CMD_RESP_LONG;
 920         else if (cmd->flags & MMC_RSP_BUSY)
 921                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 922         else
 923                 flags = SDHCI_CMD_RESP_SHORT;
 924
 925         if (cmd->flags & MMC_RSP_CRC)
 926                 flags |= SDHCI_CMD_CRC;
 927         if (cmd->flags & MMC_RSP_OPCODE)
 928                 flags |= SDHCI_CMD_INDEX;
 929         if (cmd->data)
 930                 flags |= SDHCI_CMD_DATA;
 931
 932         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
 933 }
 934
 935 static void sdhci_finish_command(struct sdhci_host *host)
 936 {
 937         int i;
 938
 939         BUG_ON(host->cmd == NULL);
 940
 941         if (host->cmd->flags & MMC_RSP_PRESENT) {
 942                 if (host->cmd->flags & MMC_RSP_136) {
 943                         /* CRC is stripped so we need to do some shifting. */
 944                         for (i = 0;i < 4;i++) {
 945                                 host->cmd->resp[i] = sdhci_readl(host,
 946                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 947                                 if (i != 3)
 948                                         host->cmd->resp[i] |=
 949                                                 sdhci_readb(host,
 950                                                 SDHCI_RESPONSE + (3-i)*4-1);
 951                         }
 952                 } else {
 953                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
 954                 }
 955         }
 956
 957         host->cmd->error = 0;
 958
 959         if (host->data && host->data_early)
 960                 sdhci_finish_data(host);
 961
 962         if (!host->cmd->data)
 963                 tasklet_schedule(&host->finish_tasklet);
 964
 965         host->cmd = NULL;
 966 }
 967
 968 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 969 {
 970         int div;
 971         u16 clk;
 972         unsigned long timeout;
 973
 974         if (clock == host->clock)
 975                 return;
 976
 977         if (host->ops->set_clock) {
 978                 host->ops->set_clock(host, clock);
 979                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
 980                         return;
 981         }
 982
 983         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 984
 985         if (clock == 0)
 986                 goto out;
 987
 988         for (div = 1;div < 256;div *= 2) {
 989                 if ((host->max_clk / div) <= clock)
 990                         break;
 991         }
 992         div >>= 1;
 993
 994         clk = div << SDHCI_DIVIDER_SHIFT;
 995         clk |= SDHCI_CLOCK_INT_EN;
 996         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 997
 998         /* Wait max 20 ms */
 999         timeout = 20;
1000         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1001                 & SDHCI_CLOCK_INT_STABLE)) {
1002                 if (timeout == 0) {
1003                         printk(KERN_ERR "%s: Internal clock never "
1004                                 "stabilised.\n", mmc_hostname(host->mmc));
1005                         sdhci_dumpregs(host);
1006                         return;
1007                 }
1008                 timeout--;
1009                 mdelay(1);
1010         }
1011
1012         clk |= SDHCI_CLOCK_CARD_EN;
1013         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1014
1015 out:
1016         host->clock = clock;
1017 }
1018
1019 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1020 {
1021         u8 pwr;
1022
1023         if (power == (unsigned short)-1)
1024                 pwr = 0;
1025         else {
1026                 switch (1 << power) {
1027                 case MMC_VDD_165_195:
1028                         pwr = SDHCI_POWER_180;
1029                         break;
1030                 case MMC_VDD_29_30:
1031                 case MMC_VDD_30_31:
1032                         pwr = SDHCI_POWER_300;
1033                         break;
1034                 case MMC_VDD_32_33:
1035                 case MMC_VDD_33_34:
1036                         pwr = SDHCI_POWER_330;
1037                         break;
1038                 default:
1039                         BUG();
1040                 }
1041         }
1042
1043         if (host->pwr == pwr)
1044                 return;
1045
1046         host->pwr = pwr;
1047
1048         if (pwr == 0) {
1049                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1050                 return;
1051         }
1052
1053         /*
1054          * Spec says that we should clear the power reg before setting
1055          * a new value. Some controllers don't seem to like this though.
1056          */
1057         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1058                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1059
1060         /*
1061          * At least the Marvell CaFe chip gets confused if we set the voltage
1062          * and set turn on power at the same time, so set the voltage first.
1063          */
1064         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1065                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1066
1067         pwr |= SDHCI_POWER_ON;
1068
1069         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1070
1071         /*
1072          * Some controllers need an extra 10ms delay of 10ms before they
1073          * can apply clock after applying power
1074          */
1075         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1076                 mdelay(10);
1077 }
1078
1079 /*****************************************************************************\
1080  *                                                                           *
1081  * MMC callbacks                                                             *
1082  *                                                                           *
1083 \*****************************************************************************/
1084
1085 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1086 {
1087         struct sdhci_host *host;
1088         bool present;
1089         unsigned long flags;
1090
1091         host = mmc_priv(mmc);
1092
1093         spin_lock_irqsave(&host->lock, flags);
1094
1095         WARN_ON(host->mrq != NULL);
1096
1097 #ifndef SDHCI_USE_LEDS_CLASS
1098         sdhci_activate_led(host);
1099 #endif
1100
1101         host->mrq = mrq;
1102
1103         /* If polling, assume that the card is always present. */
1104         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1105                 present = true;
1106         else
1107                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1108                                 SDHCI_CARD_PRESENT;
1109
1110         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1111                 host->mrq->cmd->error = -ENOMEDIUM;
1112                 tasklet_schedule(&host->finish_tasklet);
1113         } else
1114                 sdhci_send_command(host, mrq->cmd);
1115
1116         mmiowb();
1117         spin_unlock_irqrestore(&host->lock, flags);
1118 }
1119
1120 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1121 {
1122         struct sdhci_host *host;
1123         unsigned long flags;
1124         u8 ctrl;
1125
1126         host = mmc_priv(mmc);
1127
1128         spin_lock_irqsave(&host->lock, flags);
1129
1130         if (host->flags & SDHCI_DEVICE_DEAD)
1131                 goto out;
1132
1133         /*
1134          * Reset the chip on each power off.
1135          * Should clear out any weird states.
1136          */
1137         if (ios->power_mode == MMC_POWER_OFF) {
1138                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1139                 sdhci_reinit(host);
1140         }
1141
1142         sdhci_set_clock(host, ios->clock);
1143
1144         if (ios->power_mode == MMC_POWER_OFF)
1145                 sdhci_set_power(host, -1);
1146         else
1147                 sdhci_set_power(host, ios->vdd);
1148
1149         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1150
1151         if (ios->bus_width == MMC_BUS_WIDTH_4)
1152                 ctrl |= SDHCI_CTRL_4BITBUS;
1153         else
1154                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1155
1156         if (ios->timing == MMC_TIMING_SD_HS)
1157                 ctrl |= SDHCI_CTRL_HISPD;
1158         else
1159                 ctrl &= ~SDHCI_CTRL_HISPD;
1160
1161         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1162
1163         /*
1164          * Some (ENE) controllers go apeshit on some ios operation,
1165          * signalling timeout and CRC errors even on CMD0. Resetting
1166          * it on each ios seems to solve the problem.
1167          */
1168         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1169                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1170
1171 out:
1172         mmiowb();
1173         spin_unlock_irqrestore(&host->lock, flags);
1174 }
1175
1176 static int sdhci_get_ro(struct mmc_host *mmc)
1177 {
1178         struct sdhci_host *host;
1179         unsigned long flags;
1180         int present;
1181
1182         host = mmc_priv(mmc);
1183
1184         spin_lock_irqsave(&host->lock, flags);
1185
1186         if (host->flags & SDHCI_DEVICE_DEAD)
1187                 present = 0;
1188         else
1189                 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1190
1191         spin_unlock_irqrestore(&host->lock, flags);
1192
1193         if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1194                 return !!(present & SDHCI_WRITE_PROTECT);
1195         return !(present & SDHCI_WRITE_PROTECT);
1196 }
1197
1198 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1199 {
1200         struct sdhci_host *host;
1201         unsigned long flags;
1202
1203         host = mmc_priv(mmc);
1204
1205         spin_lock_irqsave(&host->lock, flags);
1206
1207         if (host->flags & SDHCI_DEVICE_DEAD)
1208                 goto out;
1209
1210         if (enable)
1211                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1212         else
1213                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1214 out:
1215         mmiowb();
1216
1217         spin_unlock_irqrestore(&host->lock, flags);
1218 }
1219
1220 static const struct mmc_host_ops sdhci_ops = {
1221         .request        = sdhci_request,
1222         .set_ios        = sdhci_set_ios,
1223         .get_ro         = sdhci_get_ro,
1224         .enable_sdio_irq = sdhci_enable_sdio_irq,
1225 };
1226
1227 /*****************************************************************************\
1228  *                                                                           *
1229  * Tasklets                                                                  *
1230  *                                                                           *
1231 \*****************************************************************************/
1232
1233 static void sdhci_tasklet_card(unsigned long param)
1234 {
1235         struct sdhci_host *host;
1236         unsigned long flags;
1237
1238         host = (struct sdhci_host*)param;
1239
1240         spin_lock_irqsave(&host->lock, flags);
1241
1242         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1243                 if (host->mrq) {
1244                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1245                                 mmc_hostname(host->mmc));
1246                         printk(KERN_ERR "%s: Resetting controller.\n",
1247                                 mmc_hostname(host->mmc));
1248
1249                         sdhci_reset(host, SDHCI_RESET_CMD);
1250                         sdhci_reset(host, SDHCI_RESET_DATA);
1251
1252                         host->mrq->cmd->error = -ENOMEDIUM;
1253                         tasklet_schedule(&host->finish_tasklet);
1254                 }
1255         }
1256
1257         spin_unlock_irqrestore(&host->lock, flags);
1258
1259         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1260 }
1261
1262 static void sdhci_tasklet_finish(unsigned long param)
1263 {
1264         struct sdhci_host *host;
1265         unsigned long flags;
1266         struct mmc_request *mrq;
1267
1268         host = (struct sdhci_host*)param;
1269
1270         spin_lock_irqsave(&host->lock, flags);
1271
1272         del_timer(&host->timer);
1273
1274         mrq = host->mrq;
1275
1276         /*
1277          * The controller needs a reset of internal state machines
1278          * upon error conditions.
1279          */
1280         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1281                 (mrq->cmd->error ||
1282                  (mrq->data && (mrq->data->error ||
1283                   (mrq->data->stop && mrq->data->stop->error))) ||
1284                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1285
1286                 /* Some controllers need this kick or reset won't work here */
1287                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1288                         unsigned int clock;
1289
1290                         /* This is to force an update */
1291                         clock = host->clock;
1292                         host->clock = 0;
1293                         sdhci_set_clock(host, clock);
1294                 }
1295
1296                 /* Spec says we should do both at the same time, but Ricoh
1297                    controllers do not like that. */
1298                 sdhci_reset(host, SDHCI_RESET_CMD);
1299                 sdhci_reset(host, SDHCI_RESET_DATA);
1300         }
1301
1302         host->mrq = NULL;
1303         host->cmd = NULL;
1304         host->data = NULL;
1305
1306 #ifndef SDHCI_USE_LEDS_CLASS
1307         sdhci_deactivate_led(host);
1308 #endif
1309
1310         mmiowb();
1311         spin_unlock_irqrestore(&host->lock, flags);
1312
1313         mmc_request_done(host->mmc, mrq);
1314 }
1315
1316 static void sdhci_timeout_timer(unsigned long data)
1317 {
1318         struct sdhci_host *host;
1319         unsigned long flags;
1320
1321         host = (struct sdhci_host*)data;
1322
1323         spin_lock_irqsave(&host->lock, flags);
1324
1325         if (host->mrq) {
1326                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1327                         "interrupt.\n", mmc_hostname(host->mmc));
1328                 sdhci_dumpregs(host);
1329
1330                 if (host->data) {
1331                         host->data->error = -ETIMEDOUT;
1332                         sdhci_finish_data(host);
1333                 } else {
1334                         if (host->cmd)
1335                                 host->cmd->error = -ETIMEDOUT;
1336                         else
1337                                 host->mrq->cmd->error = -ETIMEDOUT;
1338
1339                         tasklet_schedule(&host->finish_tasklet);
1340                 }
1341         }
1342
1343         mmiowb();
1344         spin_unlock_irqrestore(&host->lock, flags);
1345 }
1346
1347 /*****************************************************************************\
1348  *                                                                           *
1349  * Interrupt handling                                                        *
1350  *                                                                           *
1351 \*****************************************************************************/
1352
1353 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1354 {
1355         BUG_ON(intmask == 0);
1356
1357         if (!host->cmd) {
1358                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1359                         "though no command operation was in progress.\n",
1360                         mmc_hostname(host->mmc), (unsigned)intmask);
1361                 sdhci_dumpregs(host);
1362                 return;
1363         }
1364
1365         if (intmask & SDHCI_INT_TIMEOUT)
1366                 host->cmd->error = -ETIMEDOUT;
1367         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1368                         SDHCI_INT_INDEX))
1369                 host->cmd->error = -EILSEQ;
1370
1371         if (host->cmd->error) {
1372                 tasklet_schedule(&host->finish_tasklet);
1373                 return;
1374         }
1375
1376         /*
1377          * The host can send and interrupt when the busy state has
1378          * ended, allowing us to wait without wasting CPU cycles.
1379          * Unfortunately this is overloaded on the "data complete"
1380          * interrupt, so we need to take some care when handling
1381          * it.
1382          *
1383          * Note: The 1.0 specification is a bit ambiguous about this
1384          *       feature so there might be some problems with older
1385          *       controllers.
1386          */
1387         if (host->cmd->flags & MMC_RSP_BUSY) {
1388                 if (host->cmd->data)
1389                         DBG("Cannot wait for busy signal when also "
1390                                 "doing a data transfer");
1391                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1392                         return;
1393
1394                 /* The controller does not support the end-of-busy IRQ,
1395                  * fall through and take the SDHCI_INT_RESPONSE */
1396         }
1397
1398         if (intmask & SDHCI_INT_RESPONSE)
1399                 sdhci_finish_command(host);
1400 }
1401
1402 #ifdef DEBUG
1403 static void sdhci_show_adma_error(struct sdhci_host *host)
1404 {
1405         const char *name = mmc_hostname(host->mmc);
1406         u8 *desc = host->adma_desc;
1407         __le32 *dma;
1408         __le16 *len;
1409         u8 attr;
1410
1411         sdhci_dumpregs(host);
1412
1413         while (true) {
1414                 dma = (__le32 *)(desc + 4);
1415                 len = (__le16 *)(desc + 2);
1416                 attr = *desc;
1417
1418                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1419                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1420
1421                 desc += 8;
1422
1423                 if (attr & 2)
1424                         break;
1425         }
1426 }
1427 #else
1428 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1429 #endif
1430
1431 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1432 {
1433         BUG_ON(intmask == 0);
1434
1435         if (!host->data) {
1436                 /*
1437                  * The "data complete" interrupt is also used to
1438                  * indicate that a busy state has ended. See comment
1439                  * above in sdhci_cmd_irq().
1440                  */
1441                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1442                         if (intmask & SDHCI_INT_DATA_END) {
1443                                 sdhci_finish_command(host);
1444                                 return;
1445                         }
1446                 }
1447
1448                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1449                         "though no data operation was in progress.\n",
1450                         mmc_hostname(host->mmc), (unsigned)intmask);
1451                 sdhci_dumpregs(host);
1452
1453                 return;
1454         }
1455
1456         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1457                 host->data->error = -ETIMEDOUT;
1458         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1459                 host->data->error = -EILSEQ;
1460         else if (intmask & SDHCI_INT_ADMA_ERROR) {
1461                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1462                 sdhci_show_adma_error(host);
1463                 host->data->error = -EIO;
1464         }
1465
1466         if (host->data->error)
1467                 sdhci_finish_data(host);
1468         else {
1469                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1470                         sdhci_transfer_pio(host);
1471
1472                 /*
1473                  * We currently don't do anything fancy with DMA
1474                  * boundaries, but as we can't disable the feature
1475                  * we need to at least restart the transfer.
1476                  */
1477                 if (intmask & SDHCI_INT_DMA_END)
1478                         sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1479                                 SDHCI_DMA_ADDRESS);
1480
1481                 if (intmask & SDHCI_INT_DATA_END) {
1482                         if (host->cmd) {
1483                                 /*
1484                                  * Data managed to finish before the
1485                                  * command completed. Make sure we do
1486                                  * things in the proper order.
1487                                  */
1488                                 host->data_early = 1;
1489                         } else {
1490                                 sdhci_finish_data(host);
1491                         }
1492                 }
1493         }
1494 }
1495
1496 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1497 {
1498         irqreturn_t result;
1499         struct sdhci_host* host = dev_id;
1500         u32 intmask;
1501         int cardint = 0;
1502
1503         spin_lock(&host->lock);
1504
1505         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1506
1507         if (!intmask || intmask == 0xffffffff) {
1508                 result = IRQ_NONE;
1509                 goto out;
1510         }
1511
1512         DBG("*** %s got interrupt: 0x%08x\n",
1513                 mmc_hostname(host->mmc), intmask);
1514
1515         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1516                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1517                         SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1518                 tasklet_schedule(&host->card_tasklet);
1519         }
1520
1521         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1522
1523         if (intmask & SDHCI_INT_CMD_MASK) {
1524                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1525                         SDHCI_INT_STATUS);
1526                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1527         }
1528
1529         if (intmask & SDHCI_INT_DATA_MASK) {
1530                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1531                         SDHCI_INT_STATUS);
1532                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1533         }
1534
1535         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1536
1537         intmask &= ~SDHCI_INT_ERROR;
1538
1539         if (intmask & SDHCI_INT_BUS_POWER) {
1540                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1541                         mmc_hostname(host->mmc));
1542                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1543         }
1544
1545         intmask &= ~SDHCI_INT_BUS_POWER;
1546
1547         if (intmask & SDHCI_INT_CARD_INT)
1548                 cardint = 1;
1549
1550         intmask &= ~SDHCI_INT_CARD_INT;
1551
1552         if (intmask) {
1553                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1554                         mmc_hostname(host->mmc), intmask);
1555                 sdhci_dumpregs(host);
1556
1557                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1558         }
1559
1560         result = IRQ_HANDLED;
1561
1562         mmiowb();
1563 out:
1564         spin_unlock(&host->lock);
1565
1566         /*
1567          * We have to delay this as it calls back into the driver.
1568          */
1569         if (cardint)
1570                 mmc_signal_sdio_irq(host->mmc);
1571
1572         return result;
1573 }
1574
1575 /*****************************************************************************\
1576  *                                                                           *
1577  * Suspend/resume                                                            *
1578  *                                                                           *
1579 \*****************************************************************************/
1580
1581 #ifdef CONFIG_PM
1582
1583 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1584 {
1585         int ret;
1586
1587         sdhci_disable_card_detection(host);
1588
1589         ret = mmc_suspend_host(host->mmc, state);
1590         if (ret)
1591                 return ret;
1592
1593         free_irq(host->irq, host);
1594
1595         return 0;
1596 }
1597
1598 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1599
1600 int sdhci_resume_host(struct sdhci_host *host)
1601 {
1602         int ret;
1603
1604         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1605                 if (host->ops->enable_dma)
1606                         host->ops->enable_dma(host);
1607         }
1608
1609         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1610                           mmc_hostname(host->mmc), host);
1611         if (ret)
1612                 return ret;
1613
1614         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1615         mmiowb();
1616
1617         ret = mmc_resume_host(host->mmc);
1618         sdhci_enable_card_detection(host);
1619
1620         return ret;
1621 }
1622
1623 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1624
1625 #endif /* CONFIG_PM */
1626
1627 /*****************************************************************************\
1628  *                                                                           *
1629  * Device allocation/registration                                            *
1630  *                                                                           *
1631 \*****************************************************************************/
1632
1633 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1634         size_t priv_size)
1635 {
1636         struct mmc_host *mmc;
1637         struct sdhci_host *host;
1638
1639         WARN_ON(dev == NULL);
1640
1641         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1642         if (!mmc)
1643                 return ERR_PTR(-ENOMEM);
1644
1645         host = mmc_priv(mmc);
1646         host->mmc = mmc;
1647
1648         return host;
1649 }
1650
1651 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1652
1653 int sdhci_add_host(struct sdhci_host *host)
1654 {
1655         struct mmc_host *mmc;
1656         unsigned int caps;
1657         int ret;
1658
1659         WARN_ON(host == NULL);
1660         if (host == NULL)
1661                 return -EINVAL;
1662
1663         mmc = host->mmc;
1664
1665         if (debug_quirks)
1666                 host->quirks = debug_quirks;
1667
1668         sdhci_reset(host, SDHCI_RESET_ALL);
1669
1670         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1671         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1672                                 >> SDHCI_SPEC_VER_SHIFT;
1673         if (host->version > SDHCI_SPEC_200) {
1674                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1675                         "You may experience problems.\n", mmc_hostname(mmc),
1676                         host->version);
1677         }
1678
1679         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1680
1681         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1682                 host->flags |= SDHCI_USE_SDMA;
1683         else if (!(caps & SDHCI_CAN_DO_SDMA))
1684                 DBG("Controller doesn't have SDMA capability\n");
1685         else
1686                 host->flags |= SDHCI_USE_SDMA;
1687
1688         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1689                 (host->flags & SDHCI_USE_SDMA)) {
1690                 DBG("Disabling DMA as it is marked broken\n");
1691                 host->flags &= ~SDHCI_USE_SDMA;
1692         }
1693
1694         if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1695                 host->flags |= SDHCI_USE_ADMA;
1696
1697         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1698                 (host->flags & SDHCI_USE_ADMA)) {
1699                 DBG("Disabling ADMA as it is marked broken\n");
1700                 host->flags &= ~SDHCI_USE_ADMA;
1701         }
1702
1703         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1704                 if (host->ops->enable_dma) {
1705                         if (host->ops->enable_dma(host)) {
1706                                 printk(KERN_WARNING "%s: No suitable DMA "
1707                                         "available. Falling back to PIO.\n",
1708                                         mmc_hostname(mmc));
1709                                 host->flags &=
1710                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1711                         }
1712                 }
1713         }
1714
1715         if (host->flags & SDHCI_USE_ADMA) {
1716                 /*
1717                  * We need to allocate descriptors for all sg entries
1718                  * (128) and potentially one alignment transfer for
1719                  * each of those entries.
1720                  */
1721                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1722                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1723                 if (!host->adma_desc || !host->align_buffer) {
1724                         kfree(host->adma_desc);
1725                         kfree(host->align_buffer);
1726                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1727                                 "buffers. Falling back to standard DMA.\n",
1728                                 mmc_hostname(mmc));
1729                         host->flags &= ~SDHCI_USE_ADMA;
1730                 }
1731         }
1732
1733         /*
1734          * If we use DMA, then it's up to the caller to set the DMA
1735          * mask, but PIO does not need the hw shim so we set a new
1736          * mask here in that case.
1737          */
1738         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1739                 host->dma_mask = DMA_BIT_MASK(64);
1740                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1741         }
1742
1743         host->max_clk =
1744                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1745         host->max_clk *= 1000000;
1746         if (host->max_clk == 0) {
1747                 if (!host->ops->get_max_clock) {
1748                         printk(KERN_ERR
1749                                "%s: Hardware doesn't specify base clock "
1750                                "frequency.\n", mmc_hostname(mmc));
1751                         return -ENODEV;
1752                 }
1753                 host->max_clk = host->ops->get_max_clock(host);
1754         }
1755
1756         host->timeout_clk =
1757                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1758         if (host->timeout_clk == 0) {
1759                 if (host->ops->get_timeout_clock) {
1760                         host->timeout_clk = host->ops->get_timeout_clock(host);
1761                 } else if (!(host->quirks &
1762                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1763                         printk(KERN_ERR
1764                                "%s: Hardware doesn't specify timeout clock "
1765                                "frequency.\n", mmc_hostname(mmc));
1766                         return -ENODEV;
1767                 }
1768         }
1769         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1770                 host->timeout_clk *= 1000;
1771
1772         /*
1773          * Set host parameters.
1774          */
1775         mmc->ops = &sdhci_ops;
1776         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1777                         host->ops->set_clock && host->ops->get_min_clock)
1778                 mmc->f_min = host->ops->get_min_clock(host);
1779         else
1780                 mmc->f_min = host->max_clk / 256;
1781         mmc->f_max = host->max_clk;
1782         mmc->caps = MMC_CAP_SDIO_IRQ;
1783
1784         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1785                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1786
1787         if (caps & SDHCI_CAN_DO_HISPD)
1788                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1789
1790         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1791                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1792
1793         mmc->ocr_avail = 0;
1794         if (caps & SDHCI_CAN_VDD_330)
1795                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1796         if (caps & SDHCI_CAN_VDD_300)
1797                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1798         if (caps & SDHCI_CAN_VDD_180)
1799                 mmc->ocr_avail |= MMC_VDD_165_195;
1800
1801         if (mmc->ocr_avail == 0) {
1802                 printk(KERN_ERR "%s: Hardware doesn't report any "
1803                         "support voltages.\n", mmc_hostname(mmc));
1804                 return -ENODEV;
1805         }
1806
1807         spin_lock_init(&host->lock);
1808
1809         /*
1810          * Maximum number of segments. Depends on if the hardware
1811          * can do scatter/gather or not.
1812          */
1813         if (host->flags & SDHCI_USE_ADMA)
1814                 mmc->max_hw_segs = 128;
1815         else if (host->flags & SDHCI_USE_SDMA)
1816                 mmc->max_hw_segs = 1;
1817         else /* PIO */
1818                 mmc->max_hw_segs = 128;
1819         mmc->max_phys_segs = 128;
1820
1821         /*
1822          * Maximum number of sectors in one transfer. Limited by DMA boundary
1823          * size (512KiB).
1824          */
1825         mmc->max_req_size = 524288;
1826
1827         /*
1828          * Maximum segment size. Could be one segment with the maximum number
1829          * of bytes. When doing hardware scatter/gather, each entry cannot
1830          * be larger than 64 KiB though.
1831          */
1832         if (host->flags & SDHCI_USE_ADMA)
1833                 mmc->max_seg_size = 65536;
1834         else
1835                 mmc->max_seg_size = mmc->max_req_size;
1836
1837         /*
1838          * Maximum block size. This varies from controller to controller and
1839          * is specified in the capabilities register.
1840          */
1841         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1842                 mmc->max_blk_size = 2;
1843         } else {
1844                 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1845                                 SDHCI_MAX_BLOCK_SHIFT;
1846                 if (mmc->max_blk_size >= 3) {
1847                         printk(KERN_WARNING "%s: Invalid maximum block size, "
1848                                 "assuming 512 bytes\n", mmc_hostname(mmc));
1849                         mmc->max_blk_size = 0;
1850                 }
1851         }
1852
1853         mmc->max_blk_size = 512 << mmc->max_blk_size;
1854
1855         /*
1856          * Maximum block count.
1857          */
1858         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1859
1860         /*
1861          * Init tasklets.
1862          */
1863         tasklet_init(&host->card_tasklet,
1864                 sdhci_tasklet_card, (unsigned long)host);
1865         tasklet_init(&host->finish_tasklet,
1866                 sdhci_tasklet_finish, (unsigned long)host);
1867
1868         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1869
1870         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1871                 mmc_hostname(mmc), host);
1872         if (ret)
1873                 goto untasklet;
1874
1875         sdhci_init(host, 0);
1876
1877 #ifdef CONFIG_MMC_DEBUG
1878         sdhci_dumpregs(host);
1879 #endif
1880
1881 #ifdef SDHCI_USE_LEDS_CLASS
1882         snprintf(host->led_name, sizeof(host->led_name),
1883                 "%s::", mmc_hostname(mmc));
1884         host->led.name = host->led_name;
1885         host->led.brightness = LED_OFF;
1886         host->led.default_trigger = mmc_hostname(mmc);
1887         host->led.brightness_set = sdhci_led_control;
1888
1889         ret = led_classdev_register(mmc_dev(mmc), &host->led);
1890         if (ret)
1891                 goto reset;
1892 #endif
1893
1894         mmiowb();
1895
1896         mmc_add_host(mmc);
1897
1898         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1899                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1900                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1901                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1902
1903         sdhci_enable_card_detection(host);
1904
1905         return 0;
1906
1907 #ifdef SDHCI_USE_LEDS_CLASS
1908 reset:
1909         sdhci_reset(host, SDHCI_RESET_ALL);
1910         free_irq(host->irq, host);
1911 #endif
1912 untasklet:
1913         tasklet_kill(&host->card_tasklet);
1914         tasklet_kill(&host->finish_tasklet);
1915
1916         return ret;
1917 }
1918
1919 EXPORT_SYMBOL_GPL(sdhci_add_host);
1920
1921 void sdhci_remove_host(struct sdhci_host *host, int dead)
1922 {
1923         unsigned long flags;
1924
1925         if (dead) {
1926                 spin_lock_irqsave(&host->lock, flags);
1927
1928                 host->flags |= SDHCI_DEVICE_DEAD;
1929
1930                 if (host->mrq) {
1931                         printk(KERN_ERR "%s: Controller removed during "
1932                                 " transfer!\n", mmc_hostname(host->mmc));
1933
1934                         host->mrq->cmd->error = -ENOMEDIUM;
1935                         tasklet_schedule(&host->finish_tasklet);
1936                 }
1937
1938                 spin_unlock_irqrestore(&host->lock, flags);
1939         }
1940
1941         sdhci_disable_card_detection(host);
1942
1943         mmc_remove_host(host->mmc);
1944
1945 #ifdef SDHCI_USE_LEDS_CLASS
1946         led_classdev_unregister(&host->led);
1947 #endif
1948
1949         if (!dead)
1950                 sdhci_reset(host, SDHCI_RESET_ALL);
1951
1952         free_irq(host->irq, host);
1953
1954         del_timer_sync(&host->timer);
1955
1956         tasklet_kill(&host->card_tasklet);
1957         tasklet_kill(&host->finish_tasklet);
1958
1959         kfree(host->adma_desc);
1960         kfree(host->align_buffer);
1961
1962         host->adma_desc = NULL;
1963         host->align_buffer = NULL;
1964 }
1965
1966 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1967
1968 void sdhci_free_host(struct sdhci_host *host)
1969 {
1970         mmc_free_host(host->mmc);
1971 }
1972
1973 EXPORT_SYMBOL_GPL(sdhci_free_host);
1974
1975 /*****************************************************************************\
1976  *                                                                           *
1977  * Driver init/exit                                                          *
1978  *                                                                           *
1979 \*****************************************************************************/
1980
1981 static int __init sdhci_drv_init(void)
1982 {
1983         printk(KERN_INFO DRIVER_NAME
1984                 ": Secure Digital Host Controller Interface driver\n");
1985         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1986
1987         return 0;
1988 }
1989
1990 static void __exit sdhci_drv_exit(void)
1991 {
1992 }
1993
1994 module_init(sdhci_drv_init);
1995 module_exit(sdhci_drv_exit);
1996
1997 module_param(debug_quirks, uint, 0444);
1998
1999 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2000 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2001 MODULE_LICENSE("GPL");
2002
2003 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");