2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
428 .find_pll = intel_g4x_find_best_PLL,
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
444 .find_pll = intel_g4x_find_best_PLL,
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
468 .find_pll = intel_g4x_find_best_PLL,
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
492 .find_pll = intel_g4x_find_best_PLL,
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 const intel_limit_t *limit;
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100000)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
659 limit = &intel_limits_ironlake_dual_lvds;
661 if (refclk == 100000)
662 limit = &intel_limits_ironlake_single_lvds_100m;
664 limit = &intel_limits_ironlake_single_lvds;
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
668 limit = &intel_limits_ironlake_display_port;
670 limit = &intel_limits_ironlake_dac;
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc, refclk);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
720 limit = &intel_limits_i9xx_sdvo;
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
725 limit = &intel_limits_i8xx_dvo;
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
752 * Returns whether any output on the specified pipe is of the specified type
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
773 static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813 (I915_READ(LVDS)) != 0) {
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
822 clock.p2 = limit->p2.p2_fast;
824 clock.p2 = limit->p2.p2_slow;
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
829 clock.p2 = limit->p2.p2_fast;
832 memset (best_clock, 0, sizeof (*best_clock));
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
847 intel_clock(dev, refclk, &clock);
848 if (!intel_PLL_is_valid(dev, limit,
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
862 return (err != target);
866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
881 if (HAS_PCH_SPLIT(dev))
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
887 clock.p2 = limit->p2.p2_fast;
889 clock.p2 = limit->p2.p2_slow;
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
894 clock.p2 = limit->p2.p2_fast;
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
910 intel_clock(dev, refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit,
915 this_err = abs(clock.dot - target);
916 if (this_err < err_most) {
930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
933 struct drm_device *dev = crtc->dev;
936 if (target < 200000) {
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
960 if (target < 200000) {
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
982 * intel_wait_for_vblank - wait for vblank on a given pipe
984 * @pipe: pipe to wait for
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1020 * @pipe: pipe to wait for
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1038 if (INTEL_INFO(dev)->gen >= 4) {
1039 int reg = PIPECONF(pipe);
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 int reg = PIPEDSL(pipe);
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1050 /* Wait for the display line to settle */
1052 last_line = I915_READ(reg) & DSL_LINEMASK;
1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1061 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1063 struct drm_device *dev = crtc->dev;
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 struct drm_framebuffer *fb = crtc->fb;
1066 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1067 struct drm_i915_gem_object *obj = intel_fb->obj;
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070 u32 fbc_ctl, fbc_ctl2;
1072 if (fb->pitch == dev_priv->cfb_pitch &&
1073 obj->fence_reg == dev_priv->cfb_fence &&
1074 intel_crtc->plane == dev_priv->cfb_plane &&
1075 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078 i8xx_disable_fbc(dev);
1080 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1082 if (fb->pitch < dev_priv->cfb_pitch)
1083 dev_priv->cfb_pitch = fb->pitch;
1085 /* FBC_CTL wants 64B units */
1086 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1087 dev_priv->cfb_fence = obj->fence_reg;
1088 dev_priv->cfb_plane = intel_crtc->plane;
1089 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1091 /* Clear old tags */
1092 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1093 I915_WRITE(FBC_TAG + (i * 4), 0);
1096 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1097 if (obj->tiling_mode != I915_TILING_NONE)
1098 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1099 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1100 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1105 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1106 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1107 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1108 if (obj->tiling_mode != I915_TILING_NONE)
1109 fbc_ctl |= dev_priv->cfb_fence;
1110 I915_WRITE(FBC_CONTROL, fbc_ctl);
1112 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1113 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 void i8xx_disable_fbc(struct drm_device *dev)
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1121 /* Disable compression */
1122 fbc_ctl = I915_READ(FBC_CONTROL);
1123 if ((fbc_ctl & FBC_CTL_EN) == 0)
1126 fbc_ctl &= ~FBC_CTL_EN;
1127 I915_WRITE(FBC_CONTROL, fbc_ctl);
1129 /* Wait for compressing bit to clear */
1130 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1131 DRM_DEBUG_KMS("FBC idle timed out\n");
1135 DRM_DEBUG_KMS("disabled FBC\n");
1138 static bool i8xx_fbc_enabled(struct drm_device *dev)
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1142 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1147 struct drm_device *dev = crtc->dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 struct drm_framebuffer *fb = crtc->fb;
1150 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1151 struct drm_i915_gem_object *obj = intel_fb->obj;
1152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1153 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1154 unsigned long stall_watermark = 200;
1157 dpfc_ctl = I915_READ(DPFC_CONTROL);
1158 if (dpfc_ctl & DPFC_CTL_EN) {
1159 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1160 dev_priv->cfb_fence == obj->fence_reg &&
1161 dev_priv->cfb_plane == intel_crtc->plane &&
1162 dev_priv->cfb_y == crtc->y)
1165 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1166 POSTING_READ(DPFC_CONTROL);
1167 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1171 dev_priv->cfb_fence = obj->fence_reg;
1172 dev_priv->cfb_plane = intel_crtc->plane;
1173 dev_priv->cfb_y = crtc->y;
1175 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1176 if (obj->tiling_mode != I915_TILING_NONE) {
1177 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1178 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1180 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1184 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1185 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1186 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1191 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 void g4x_disable_fbc(struct drm_device *dev)
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1199 /* Disable compression */
1200 dpfc_ctl = I915_READ(DPFC_CONTROL);
1201 if (dpfc_ctl & DPFC_CTL_EN) {
1202 dpfc_ctl &= ~DPFC_CTL_EN;
1203 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1205 DRM_DEBUG_KMS("disabled FBC\n");
1209 static bool g4x_fbc_enabled(struct drm_device *dev)
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1213 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 struct drm_framebuffer *fb = crtc->fb;
1221 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1222 struct drm_i915_gem_object *obj = intel_fb->obj;
1223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1224 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1225 unsigned long stall_watermark = 200;
1228 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1229 if (dpfc_ctl & DPFC_CTL_EN) {
1230 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1231 dev_priv->cfb_fence == obj->fence_reg &&
1232 dev_priv->cfb_plane == intel_crtc->plane &&
1233 dev_priv->cfb_offset == obj->gtt_offset &&
1234 dev_priv->cfb_y == crtc->y)
1237 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1238 POSTING_READ(ILK_DPFC_CONTROL);
1239 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1243 dev_priv->cfb_fence = obj->fence_reg;
1244 dev_priv->cfb_plane = intel_crtc->plane;
1245 dev_priv->cfb_offset = obj->gtt_offset;
1246 dev_priv->cfb_y = crtc->y;
1248 dpfc_ctl &= DPFC_RESERVED;
1249 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1250 if (obj->tiling_mode != I915_TILING_NONE) {
1251 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1252 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1254 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1258 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1259 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1260 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1261 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266 I915_WRITE(SNB_DPFC_CTL_SA,
1267 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1268 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1271 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1274 void ironlake_disable_fbc(struct drm_device *dev)
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1279 /* Disable compression */
1280 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1281 if (dpfc_ctl & DPFC_CTL_EN) {
1282 dpfc_ctl &= ~DPFC_CTL_EN;
1283 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1285 DRM_DEBUG_KMS("disabled FBC\n");
1289 static bool ironlake_fbc_enabled(struct drm_device *dev)
1291 struct drm_i915_private *dev_priv = dev->dev_private;
1293 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1296 bool intel_fbc_enabled(struct drm_device *dev)
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1300 if (!dev_priv->display.fbc_enabled)
1303 return dev_priv->display.fbc_enabled(dev);
1306 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1308 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1310 if (!dev_priv->display.enable_fbc)
1313 dev_priv->display.enable_fbc(crtc, interval);
1316 void intel_disable_fbc(struct drm_device *dev)
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1320 if (!dev_priv->display.disable_fbc)
1323 dev_priv->display.disable_fbc(dev);
1327 * intel_update_fbc - enable/disable FBC as needed
1328 * @dev: the drm_device
1330 * Set up the framebuffer compression hardware at mode set time. We
1331 * enable it if possible:
1332 * - plane A only (on pre-965)
1333 * - no pixel mulitply/line duplication
1334 * - no alpha buffer discard
1336 * - framebuffer <= 2048 in width, 1536 in height
1338 * We can't assume that any compression will take place (worst case),
1339 * so the compressed buffer has to be the same size as the uncompressed
1340 * one. It also must reside (along with the line length buffer) in
1343 * We need to enable/disable FBC on a global basis.
1345 static void intel_update_fbc(struct drm_device *dev)
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 struct drm_crtc *crtc = NULL, *tmp_crtc;
1349 struct intel_crtc *intel_crtc;
1350 struct drm_framebuffer *fb;
1351 struct intel_framebuffer *intel_fb;
1352 struct drm_i915_gem_object *obj;
1354 DRM_DEBUG_KMS("\n");
1356 if (!i915_powersave)
1359 if (!I915_HAS_FBC(dev))
1363 * If FBC is already on, we just have to verify that we can
1364 * keep it that way...
1365 * Need to disable if:
1366 * - more than one pipe is active
1367 * - changing FBC params (stride, fence, mode)
1368 * - new fb is too large to fit in compressed buffer
1369 * - going to an unsupported config (interlace, pixel multiply, etc.)
1371 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1372 if (tmp_crtc->enabled) {
1374 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1375 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1382 if (!crtc || crtc->fb == NULL) {
1383 DRM_DEBUG_KMS("no output, disabling\n");
1384 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1388 intel_crtc = to_intel_crtc(crtc);
1390 intel_fb = to_intel_framebuffer(fb);
1391 obj = intel_fb->obj;
1393 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1394 DRM_DEBUG_KMS("framebuffer too large, disabling "
1396 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1399 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1400 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1401 DRM_DEBUG_KMS("mode incompatible with compression, "
1403 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1406 if ((crtc->mode.hdisplay > 2048) ||
1407 (crtc->mode.vdisplay > 1536)) {
1408 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1409 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1412 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1413 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1414 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1417 if (obj->tiling_mode != I915_TILING_X) {
1418 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1419 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1423 /* If the kernel debugger is active, always disable compression */
1424 if (in_dbg_master())
1427 intel_enable_fbc(crtc, 500);
1431 /* Multiple disables should be harmless */
1432 if (intel_fbc_enabled(dev)) {
1433 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1434 intel_disable_fbc(dev);
1439 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1440 struct drm_i915_gem_object *obj,
1441 struct intel_ring_buffer *pipelined)
1446 switch (obj->tiling_mode) {
1447 case I915_TILING_NONE:
1448 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1449 alignment = 128 * 1024;
1450 else if (INTEL_INFO(dev)->gen >= 4)
1451 alignment = 4 * 1024;
1453 alignment = 64 * 1024;
1456 /* pin() will align the object as required by fence */
1460 /* FIXME: Is this true? */
1461 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1467 ret = i915_gem_object_pin(obj, alignment, true);
1471 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1475 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1476 * fence, whereas 965+ only requires a fence if using
1477 * framebuffer compression. For simplicity, we always install
1478 * a fence as the cost is not that onerous.
1480 if (obj->tiling_mode != I915_TILING_NONE) {
1481 ret = i915_gem_object_get_fence(obj, pipelined, false);
1489 i915_gem_object_unpin(obj);
1493 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1495 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1496 int x, int y, enum mode_set_atomic state)
1498 struct drm_device *dev = crtc->dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1501 struct intel_framebuffer *intel_fb;
1502 struct drm_i915_gem_object *obj;
1503 int plane = intel_crtc->plane;
1504 unsigned long Start, Offset;
1513 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1517 intel_fb = to_intel_framebuffer(fb);
1518 obj = intel_fb->obj;
1520 reg = DSPCNTR(plane);
1521 dspcntr = I915_READ(reg);
1522 /* Mask out pixel format bits in case we change it */
1523 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524 switch (fb->bits_per_pixel) {
1526 dspcntr |= DISPPLANE_8BPP;
1529 if (fb->depth == 15)
1530 dspcntr |= DISPPLANE_15_16BPP;
1532 dspcntr |= DISPPLANE_16BPP;
1536 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1539 DRM_ERROR("Unknown color depth\n");
1542 if (INTEL_INFO(dev)->gen >= 4) {
1543 if (obj->tiling_mode != I915_TILING_NONE)
1544 dspcntr |= DISPPLANE_TILED;
1546 dspcntr &= ~DISPPLANE_TILED;
1549 if (HAS_PCH_SPLIT(dev))
1551 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1553 I915_WRITE(reg, dspcntr);
1555 Start = obj->gtt_offset;
1556 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1558 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559 Start, Offset, x, y, fb->pitch);
1560 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561 if (INTEL_INFO(dev)->gen >= 4) {
1562 I915_WRITE(DSPSURF(plane), Start);
1563 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564 I915_WRITE(DSPADDR(plane), Offset);
1566 I915_WRITE(DSPADDR(plane), Start + Offset);
1569 intel_update_fbc(dev);
1570 intel_increase_pllclock(crtc);
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577 struct drm_framebuffer *old_fb)
1579 struct drm_device *dev = crtc->dev;
1580 struct drm_i915_master_private *master_priv;
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586 DRM_DEBUG_KMS("No FB bound\n");
1590 switch (intel_crtc->plane) {
1598 mutex_lock(&dev->struct_mutex);
1599 ret = intel_pin_and_fence_fb_obj(dev,
1600 to_intel_framebuffer(crtc->fb)->obj,
1603 mutex_unlock(&dev->struct_mutex);
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1611 wait_event(dev_priv->pending_flip_queue,
1612 atomic_read(&obj->pending_flip) == 0);
1614 /* Big Hammer, we also need to ensure that any pending
1615 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1616 * current scanout is retired before unpinning the old
1619 ret = i915_gem_object_flush_gpu(obj, false);
1621 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1622 mutex_unlock(&dev->struct_mutex);
1627 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1628 LEAVE_ATOMIC_MODE_SET);
1630 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1631 mutex_unlock(&dev->struct_mutex);
1636 intel_wait_for_vblank(dev, intel_crtc->pipe);
1637 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1640 mutex_unlock(&dev->struct_mutex);
1642 if (!dev->primary->master)
1645 master_priv = dev->primary->master->driver_priv;
1646 if (!master_priv->sarea_priv)
1649 if (intel_crtc->pipe) {
1650 master_priv->sarea_priv->pipeB_x = x;
1651 master_priv->sarea_priv->pipeB_y = y;
1653 master_priv->sarea_priv->pipeA_x = x;
1654 master_priv->sarea_priv->pipeA_y = y;
1660 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1662 struct drm_device *dev = crtc->dev;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1666 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1667 dpa_ctl = I915_READ(DP_A);
1668 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1670 if (clock < 200000) {
1672 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1673 /* workaround for 160Mhz:
1674 1) program 0x4600c bits 15:0 = 0x8124
1675 2) program 0x46010 bit 0 = 1
1676 3) program 0x46034 bit 24 = 1
1677 4) program 0x64000 bit 14 = 1
1679 temp = I915_READ(0x4600c);
1681 I915_WRITE(0x4600c, temp | 0x8124);
1683 temp = I915_READ(0x46010);
1684 I915_WRITE(0x46010, temp | 1);
1686 temp = I915_READ(0x46034);
1687 I915_WRITE(0x46034, temp | (1 << 24));
1689 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1691 I915_WRITE(DP_A, dpa_ctl);
1697 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1699 struct drm_device *dev = crtc->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1702 int pipe = intel_crtc->pipe;
1705 /* enable normal train */
1706 reg = FDI_TX_CTL(pipe);
1707 temp = I915_READ(reg);
1708 temp &= ~FDI_LINK_TRAIN_NONE;
1709 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1710 I915_WRITE(reg, temp);
1712 reg = FDI_RX_CTL(pipe);
1713 temp = I915_READ(reg);
1714 if (HAS_PCH_CPT(dev)) {
1715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1716 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1718 temp &= ~FDI_LINK_TRAIN_NONE;
1719 temp |= FDI_LINK_TRAIN_NONE;
1721 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1723 /* wait one idle pattern time */
1728 /* The FDI link training functions for ILK/Ibexpeak. */
1729 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1731 struct drm_device *dev = crtc->dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1734 int pipe = intel_crtc->pipe;
1735 u32 reg, temp, tries;
1737 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1739 reg = FDI_RX_IMR(pipe);
1740 temp = I915_READ(reg);
1741 temp &= ~FDI_RX_SYMBOL_LOCK;
1742 temp &= ~FDI_RX_BIT_LOCK;
1743 I915_WRITE(reg, temp);
1747 /* enable CPU FDI TX and PCH FDI RX */
1748 reg = FDI_TX_CTL(pipe);
1749 temp = I915_READ(reg);
1751 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1752 temp &= ~FDI_LINK_TRAIN_NONE;
1753 temp |= FDI_LINK_TRAIN_PATTERN_1;
1754 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1756 reg = FDI_RX_CTL(pipe);
1757 temp = I915_READ(reg);
1758 temp &= ~FDI_LINK_TRAIN_NONE;
1759 temp |= FDI_LINK_TRAIN_PATTERN_1;
1760 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1765 /* Ironlake workaround, enable clock pointer after FDI enable*/
1766 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1768 reg = FDI_RX_IIR(pipe);
1769 for (tries = 0; tries < 5; tries++) {
1770 temp = I915_READ(reg);
1771 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1773 if ((temp & FDI_RX_BIT_LOCK)) {
1774 DRM_DEBUG_KMS("FDI train 1 done.\n");
1775 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1780 DRM_ERROR("FDI train 1 fail!\n");
1783 reg = FDI_TX_CTL(pipe);
1784 temp = I915_READ(reg);
1785 temp &= ~FDI_LINK_TRAIN_NONE;
1786 temp |= FDI_LINK_TRAIN_PATTERN_2;
1787 I915_WRITE(reg, temp);
1789 reg = FDI_RX_CTL(pipe);
1790 temp = I915_READ(reg);
1791 temp &= ~FDI_LINK_TRAIN_NONE;
1792 temp |= FDI_LINK_TRAIN_PATTERN_2;
1793 I915_WRITE(reg, temp);
1798 reg = FDI_RX_IIR(pipe);
1799 for (tries = 0; tries < 5; tries++) {
1800 temp = I915_READ(reg);
1801 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1803 if (temp & FDI_RX_SYMBOL_LOCK) {
1804 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1805 DRM_DEBUG_KMS("FDI train 2 done.\n");
1810 DRM_ERROR("FDI train 2 fail!\n");
1812 DRM_DEBUG_KMS("FDI train done\n");
1816 static const int const snb_b_fdi_train_param [] = {
1817 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1818 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1819 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1820 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1823 /* The FDI link training functions for SNB/Cougarpoint. */
1824 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1826 struct drm_device *dev = crtc->dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1829 int pipe = intel_crtc->pipe;
1832 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1834 reg = FDI_RX_IMR(pipe);
1835 temp = I915_READ(reg);
1836 temp &= ~FDI_RX_SYMBOL_LOCK;
1837 temp &= ~FDI_RX_BIT_LOCK;
1838 I915_WRITE(reg, temp);
1843 /* enable CPU FDI TX and PCH FDI RX */
1844 reg = FDI_TX_CTL(pipe);
1845 temp = I915_READ(reg);
1847 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1848 temp &= ~FDI_LINK_TRAIN_NONE;
1849 temp |= FDI_LINK_TRAIN_PATTERN_1;
1850 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1852 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1853 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1855 reg = FDI_RX_CTL(pipe);
1856 temp = I915_READ(reg);
1857 if (HAS_PCH_CPT(dev)) {
1858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1861 temp &= ~FDI_LINK_TRAIN_NONE;
1862 temp |= FDI_LINK_TRAIN_PATTERN_1;
1864 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1869 for (i = 0; i < 4; i++ ) {
1870 reg = FDI_TX_CTL(pipe);
1871 temp = I915_READ(reg);
1872 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1873 temp |= snb_b_fdi_train_param[i];
1874 I915_WRITE(reg, temp);
1879 reg = FDI_RX_IIR(pipe);
1880 temp = I915_READ(reg);
1881 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1883 if (temp & FDI_RX_BIT_LOCK) {
1884 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1885 DRM_DEBUG_KMS("FDI train 1 done.\n");
1890 DRM_ERROR("FDI train 1 fail!\n");
1893 reg = FDI_TX_CTL(pipe);
1894 temp = I915_READ(reg);
1895 temp &= ~FDI_LINK_TRAIN_NONE;
1896 temp |= FDI_LINK_TRAIN_PATTERN_2;
1898 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1900 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1902 I915_WRITE(reg, temp);
1904 reg = FDI_RX_CTL(pipe);
1905 temp = I915_READ(reg);
1906 if (HAS_PCH_CPT(dev)) {
1907 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1908 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1910 temp &= ~FDI_LINK_TRAIN_NONE;
1911 temp |= FDI_LINK_TRAIN_PATTERN_2;
1913 I915_WRITE(reg, temp);
1918 for (i = 0; i < 4; i++ ) {
1919 reg = FDI_TX_CTL(pipe);
1920 temp = I915_READ(reg);
1921 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1922 temp |= snb_b_fdi_train_param[i];
1923 I915_WRITE(reg, temp);
1928 reg = FDI_RX_IIR(pipe);
1929 temp = I915_READ(reg);
1930 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1932 if (temp & FDI_RX_SYMBOL_LOCK) {
1933 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1934 DRM_DEBUG_KMS("FDI train 2 done.\n");
1939 DRM_ERROR("FDI train 2 fail!\n");
1941 DRM_DEBUG_KMS("FDI train done.\n");
1944 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 int pipe = intel_crtc->pipe;
1952 /* Write the TU size bits so error detection works */
1953 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1954 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1956 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1957 reg = FDI_RX_CTL(pipe);
1958 temp = I915_READ(reg);
1959 temp &= ~((0x7 << 19) | (0x7 << 16));
1960 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1961 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1962 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1967 /* Switch from Rawclk to PCDclk */
1968 temp = I915_READ(reg);
1969 I915_WRITE(reg, temp | FDI_PCDCLK);
1974 /* Enable CPU FDI TX PLL, always on for Ironlake */
1975 reg = FDI_TX_CTL(pipe);
1976 temp = I915_READ(reg);
1977 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1978 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1985 static void intel_flush_display_plane(struct drm_device *dev,
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1989 u32 reg = DSPADDR(plane);
1990 I915_WRITE(reg, I915_READ(reg));
1994 * When we disable a pipe, we need to clear any pending scanline wait events
1995 * to avoid hanging the ring, which we assume we are waiting on.
1997 static void intel_clear_scanline_wait(struct drm_device *dev)
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 struct intel_ring_buffer *ring;
2004 /* Can't break the hang on i8xx */
2007 ring = LP_RING(dev_priv);
2008 tmp = I915_READ_CTL(ring);
2009 if (tmp & RING_WAIT)
2010 I915_WRITE_CTL(ring, tmp);
2013 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2015 struct drm_i915_gem_object *obj;
2016 struct drm_i915_private *dev_priv;
2018 if (crtc->fb == NULL)
2021 obj = to_intel_framebuffer(crtc->fb)->obj;
2022 dev_priv = crtc->dev->dev_private;
2023 wait_event(dev_priv->pending_flip_queue,
2024 atomic_read(&obj->pending_flip) == 0);
2027 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 int pipe = intel_crtc->pipe;
2033 int plane = intel_crtc->plane;
2036 if (intel_crtc->active)
2039 intel_crtc->active = true;
2040 intel_update_watermarks(dev);
2042 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2043 temp = I915_READ(PCH_LVDS);
2044 if ((temp & LVDS_PORT_EN) == 0)
2045 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2048 ironlake_fdi_enable(crtc);
2050 /* Enable panel fitting for LVDS */
2051 if (dev_priv->pch_pf_size &&
2052 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2053 /* Force use of hard-coded filter coefficients
2054 * as some pre-programmed values are broken,
2057 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2058 PF_ENABLE | PF_FILTER_MED_3x3);
2059 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2060 dev_priv->pch_pf_pos);
2061 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2062 dev_priv->pch_pf_size);
2065 /* Enable CPU pipe */
2066 reg = PIPECONF(pipe);
2067 temp = I915_READ(reg);
2068 if ((temp & PIPECONF_ENABLE) == 0) {
2069 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2071 intel_wait_for_vblank(dev, intel_crtc->pipe);
2074 /* configure and enable CPU plane */
2075 reg = DSPCNTR(plane);
2076 temp = I915_READ(reg);
2077 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2078 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2079 intel_flush_display_plane(dev, plane);
2082 /* For PCH output, training FDI link */
2084 gen6_fdi_link_train(crtc);
2086 ironlake_fdi_link_train(crtc);
2088 /* enable PCH DPLL */
2089 reg = PCH_DPLL(pipe);
2090 temp = I915_READ(reg);
2091 if ((temp & DPLL_VCO_ENABLE) == 0) {
2092 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2097 if (HAS_PCH_CPT(dev)) {
2098 /* Be sure PCH DPLL SEL is set */
2099 temp = I915_READ(PCH_DPLL_SEL);
2100 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2101 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2102 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2103 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2104 I915_WRITE(PCH_DPLL_SEL, temp);
2107 /* set transcoder timing */
2108 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2109 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2110 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2112 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2113 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2114 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2116 intel_fdi_normal_train(crtc);
2118 /* For PCH DP, enable TRANS_DP_CTL */
2119 if (HAS_PCH_CPT(dev) &&
2120 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2121 reg = TRANS_DP_CTL(pipe);
2122 temp = I915_READ(reg);
2123 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2124 TRANS_DP_SYNC_MASK |
2126 temp |= (TRANS_DP_OUTPUT_ENABLE |
2127 TRANS_DP_ENH_FRAMING);
2128 temp |= TRANS_DP_8BPC;
2130 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2131 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2132 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2133 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2135 switch (intel_trans_dp_port_sel(crtc)) {
2137 temp |= TRANS_DP_PORT_SEL_B;
2140 temp |= TRANS_DP_PORT_SEL_C;
2143 temp |= TRANS_DP_PORT_SEL_D;
2146 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2147 temp |= TRANS_DP_PORT_SEL_B;
2151 I915_WRITE(reg, temp);
2154 /* enable PCH transcoder */
2155 reg = TRANSCONF(pipe);
2156 temp = I915_READ(reg);
2158 * make the BPC in transcoder be consistent with
2159 * that in pipeconf reg.
2161 temp &= ~PIPE_BPC_MASK;
2162 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2163 I915_WRITE(reg, temp | TRANS_ENABLE);
2164 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2165 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2167 intel_crtc_load_lut(crtc);
2168 intel_update_fbc(dev);
2169 intel_crtc_update_cursor(crtc, true);
2172 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
2176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177 int pipe = intel_crtc->pipe;
2178 int plane = intel_crtc->plane;
2181 if (!intel_crtc->active)
2184 intel_crtc_wait_for_pending_flips(crtc);
2185 drm_vblank_off(dev, pipe);
2186 intel_crtc_update_cursor(crtc, false);
2188 /* Disable display plane */
2189 reg = DSPCNTR(plane);
2190 temp = I915_READ(reg);
2191 if (temp & DISPLAY_PLANE_ENABLE) {
2192 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2193 intel_flush_display_plane(dev, plane);
2196 if (dev_priv->cfb_plane == plane &&
2197 dev_priv->display.disable_fbc)
2198 dev_priv->display.disable_fbc(dev);
2200 /* disable cpu pipe, disable after all planes disabled */
2201 reg = PIPECONF(pipe);
2202 temp = I915_READ(reg);
2203 if (temp & PIPECONF_ENABLE) {
2204 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2206 /* wait for cpu pipe off, pipe state */
2207 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2211 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2212 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2214 /* disable CPU FDI tx and PCH FDI rx */
2215 reg = FDI_TX_CTL(pipe);
2216 temp = I915_READ(reg);
2217 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2220 reg = FDI_RX_CTL(pipe);
2221 temp = I915_READ(reg);
2222 temp &= ~(0x7 << 16);
2223 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2224 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2229 /* Ironlake workaround, disable clock pointer after downing FDI */
2230 if (HAS_PCH_IBX(dev))
2231 I915_WRITE(FDI_RX_CHICKEN(pipe),
2232 I915_READ(FDI_RX_CHICKEN(pipe) &
2233 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2235 /* still set train pattern 1 */
2236 reg = FDI_TX_CTL(pipe);
2237 temp = I915_READ(reg);
2238 temp &= ~FDI_LINK_TRAIN_NONE;
2239 temp |= FDI_LINK_TRAIN_PATTERN_1;
2240 I915_WRITE(reg, temp);
2242 reg = FDI_RX_CTL(pipe);
2243 temp = I915_READ(reg);
2244 if (HAS_PCH_CPT(dev)) {
2245 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2246 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2248 temp &= ~FDI_LINK_TRAIN_NONE;
2249 temp |= FDI_LINK_TRAIN_PATTERN_1;
2251 /* BPC in FDI rx is consistent with that in PIPECONF */
2252 temp &= ~(0x07 << 16);
2253 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2254 I915_WRITE(reg, temp);
2259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2260 temp = I915_READ(PCH_LVDS);
2261 if (temp & LVDS_PORT_EN) {
2262 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2263 POSTING_READ(PCH_LVDS);
2268 /* disable PCH transcoder */
2269 reg = TRANSCONF(plane);
2270 temp = I915_READ(reg);
2271 if (temp & TRANS_ENABLE) {
2272 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2273 /* wait for PCH transcoder off, transcoder state */
2274 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2275 DRM_ERROR("failed to disable transcoder\n");
2278 if (HAS_PCH_CPT(dev)) {
2279 /* disable TRANS_DP_CTL */
2280 reg = TRANS_DP_CTL(pipe);
2281 temp = I915_READ(reg);
2282 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2283 I915_WRITE(reg, temp);
2285 /* disable DPLL_SEL */
2286 temp = I915_READ(PCH_DPLL_SEL);
2288 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2290 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2291 I915_WRITE(PCH_DPLL_SEL, temp);
2294 /* disable PCH DPLL */
2295 reg = PCH_DPLL(pipe);
2296 temp = I915_READ(reg);
2297 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2299 /* Switch from PCDclk to Rawclk */
2300 reg = FDI_RX_CTL(pipe);
2301 temp = I915_READ(reg);
2302 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2304 /* Disable CPU FDI TX PLL */
2305 reg = FDI_TX_CTL(pipe);
2306 temp = I915_READ(reg);
2307 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2316 /* Wait for the clocks to turn off. */
2320 intel_crtc->active = false;
2321 intel_update_watermarks(dev);
2322 intel_update_fbc(dev);
2323 intel_clear_scanline_wait(dev);
2326 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329 int pipe = intel_crtc->pipe;
2330 int plane = intel_crtc->plane;
2332 /* XXX: When our outputs are all unaware of DPMS modes other than off
2333 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2336 case DRM_MODE_DPMS_ON:
2337 case DRM_MODE_DPMS_STANDBY:
2338 case DRM_MODE_DPMS_SUSPEND:
2339 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2340 ironlake_crtc_enable(crtc);
2343 case DRM_MODE_DPMS_OFF:
2344 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2345 ironlake_crtc_disable(crtc);
2350 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2352 if (!enable && intel_crtc->overlay) {
2353 struct drm_device *dev = intel_crtc->base.dev;
2355 mutex_lock(&dev->struct_mutex);
2356 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2357 mutex_unlock(&dev->struct_mutex);
2360 /* Let userspace switch the overlay on again. In most cases userspace
2361 * has to recompute where to put it anyway.
2365 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2367 struct drm_device *dev = crtc->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2370 int pipe = intel_crtc->pipe;
2371 int plane = intel_crtc->plane;
2374 if (intel_crtc->active)
2377 intel_crtc->active = true;
2378 intel_update_watermarks(dev);
2380 /* Enable the DPLL */
2382 temp = I915_READ(reg);
2383 if ((temp & DPLL_VCO_ENABLE) == 0) {
2384 I915_WRITE(reg, temp);
2386 /* Wait for the clocks to stabilize. */
2390 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2392 /* Wait for the clocks to stabilize. */
2396 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2398 /* Wait for the clocks to stabilize. */
2403 /* Enable the pipe */
2404 reg = PIPECONF(pipe);
2405 temp = I915_READ(reg);
2406 if ((temp & PIPECONF_ENABLE) == 0)
2407 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2409 /* Enable the plane */
2410 reg = DSPCNTR(plane);
2411 temp = I915_READ(reg);
2412 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2413 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2414 intel_flush_display_plane(dev, plane);
2417 intel_crtc_load_lut(crtc);
2418 intel_update_fbc(dev);
2420 /* Give the overlay scaler a chance to enable if it's on this pipe */
2421 intel_crtc_dpms_overlay(intel_crtc, true);
2422 intel_crtc_update_cursor(crtc, true);
2425 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 int pipe = intel_crtc->pipe;
2431 int plane = intel_crtc->plane;
2434 if (!intel_crtc->active)
2437 /* Give the overlay scaler a chance to disable if it's on this pipe */
2438 intel_crtc_wait_for_pending_flips(crtc);
2439 drm_vblank_off(dev, pipe);
2440 intel_crtc_dpms_overlay(intel_crtc, false);
2441 intel_crtc_update_cursor(crtc, false);
2443 if (dev_priv->cfb_plane == plane &&
2444 dev_priv->display.disable_fbc)
2445 dev_priv->display.disable_fbc(dev);
2447 /* Disable display plane */
2448 reg = DSPCNTR(plane);
2449 temp = I915_READ(reg);
2450 if (temp & DISPLAY_PLANE_ENABLE) {
2451 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2452 /* Flush the plane changes */
2453 intel_flush_display_plane(dev, plane);
2455 /* Wait for vblank for the disable to take effect */
2457 intel_wait_for_vblank(dev, pipe);
2460 /* Don't disable pipe A or pipe A PLLs if needed */
2461 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2464 /* Next, disable display pipes */
2465 reg = PIPECONF(pipe);
2466 temp = I915_READ(reg);
2467 if (temp & PIPECONF_ENABLE) {
2468 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2470 /* Wait for the pipe to turn off */
2472 intel_wait_for_pipe_off(dev, pipe);
2476 temp = I915_READ(reg);
2477 if (temp & DPLL_VCO_ENABLE) {
2478 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2480 /* Wait for the clocks to turn off. */
2486 intel_crtc->active = false;
2487 intel_update_fbc(dev);
2488 intel_update_watermarks(dev);
2489 intel_clear_scanline_wait(dev);
2492 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2494 /* XXX: When our outputs are all unaware of DPMS modes other than off
2495 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2498 case DRM_MODE_DPMS_ON:
2499 case DRM_MODE_DPMS_STANDBY:
2500 case DRM_MODE_DPMS_SUSPEND:
2501 i9xx_crtc_enable(crtc);
2503 case DRM_MODE_DPMS_OFF:
2504 i9xx_crtc_disable(crtc);
2510 * Sets the power management mode of the pipe and plane.
2512 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct drm_i915_master_private *master_priv;
2517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2518 int pipe = intel_crtc->pipe;
2521 if (intel_crtc->dpms_mode == mode)
2524 intel_crtc->dpms_mode = mode;
2526 dev_priv->display.dpms(crtc, mode);
2528 if (!dev->primary->master)
2531 master_priv = dev->primary->master->driver_priv;
2532 if (!master_priv->sarea_priv)
2535 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2539 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2540 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2543 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2544 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2547 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2552 static void intel_crtc_disable(struct drm_crtc *crtc)
2554 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2555 struct drm_device *dev = crtc->dev;
2557 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2560 mutex_lock(&dev->struct_mutex);
2561 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2562 mutex_unlock(&dev->struct_mutex);
2566 /* Prepare for a mode set.
2568 * Note we could be a lot smarter here. We need to figure out which outputs
2569 * will be enabled, which disabled (in short, how the config will changes)
2570 * and perform the minimum necessary steps to accomplish that, e.g. updating
2571 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2572 * panel fitting is in the proper state, etc.
2574 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2576 i9xx_crtc_disable(crtc);
2579 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2581 i9xx_crtc_enable(crtc);
2584 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2586 ironlake_crtc_disable(crtc);
2589 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2591 ironlake_crtc_enable(crtc);
2594 void intel_encoder_prepare (struct drm_encoder *encoder)
2596 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2597 /* lvds has its own version of prepare see intel_lvds_prepare */
2598 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2601 void intel_encoder_commit (struct drm_encoder *encoder)
2603 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2604 /* lvds has its own version of commit see intel_lvds_commit */
2605 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2608 void intel_encoder_destroy(struct drm_encoder *encoder)
2610 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2612 drm_encoder_cleanup(encoder);
2613 kfree(intel_encoder);
2616 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2617 struct drm_display_mode *mode,
2618 struct drm_display_mode *adjusted_mode)
2620 struct drm_device *dev = crtc->dev;
2622 if (HAS_PCH_SPLIT(dev)) {
2623 /* FDI link clock is fixed at 2.7G */
2624 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2628 /* XXX some encoders set the crtcinfo, others don't.
2629 * Obviously we need some form of conflict resolution here...
2631 if (adjusted_mode->crtc_htotal == 0)
2632 drm_mode_set_crtcinfo(adjusted_mode, 0);
2637 static int i945_get_display_clock_speed(struct drm_device *dev)
2642 static int i915_get_display_clock_speed(struct drm_device *dev)
2647 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2652 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2656 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2658 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2661 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2662 case GC_DISPLAY_CLOCK_333_MHZ:
2665 case GC_DISPLAY_CLOCK_190_200_MHZ:
2671 static int i865_get_display_clock_speed(struct drm_device *dev)
2676 static int i855_get_display_clock_speed(struct drm_device *dev)
2679 /* Assume that the hardware is in the high speed state. This
2680 * should be the default.
2682 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2683 case GC_CLOCK_133_200:
2684 case GC_CLOCK_100_200:
2686 case GC_CLOCK_166_250:
2688 case GC_CLOCK_100_133:
2692 /* Shouldn't happen */
2696 static int i830_get_display_clock_speed(struct drm_device *dev)
2710 fdi_reduce_ratio(u32 *num, u32 *den)
2712 while (*num > 0xffffff || *den > 0xffffff) {
2719 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2720 int link_clock, struct fdi_m_n *m_n)
2722 m_n->tu = 64; /* default size */
2724 /* BUG_ON(pixel_clock > INT_MAX / 36); */
2725 m_n->gmch_m = bits_per_pixel * pixel_clock;
2726 m_n->gmch_n = link_clock * nlanes * 8;
2727 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2729 m_n->link_m = pixel_clock;
2730 m_n->link_n = link_clock;
2731 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2735 struct intel_watermark_params {
2736 unsigned long fifo_size;
2737 unsigned long max_wm;
2738 unsigned long default_wm;
2739 unsigned long guard_size;
2740 unsigned long cacheline_size;
2743 /* Pineview has different values for various configs */
2744 static struct intel_watermark_params pineview_display_wm = {
2745 PINEVIEW_DISPLAY_FIFO,
2749 PINEVIEW_FIFO_LINE_SIZE
2751 static struct intel_watermark_params pineview_display_hplloff_wm = {
2752 PINEVIEW_DISPLAY_FIFO,
2754 PINEVIEW_DFT_HPLLOFF_WM,
2756 PINEVIEW_FIFO_LINE_SIZE
2758 static struct intel_watermark_params pineview_cursor_wm = {
2759 PINEVIEW_CURSOR_FIFO,
2760 PINEVIEW_CURSOR_MAX_WM,
2761 PINEVIEW_CURSOR_DFT_WM,
2762 PINEVIEW_CURSOR_GUARD_WM,
2763 PINEVIEW_FIFO_LINE_SIZE,
2765 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2766 PINEVIEW_CURSOR_FIFO,
2767 PINEVIEW_CURSOR_MAX_WM,
2768 PINEVIEW_CURSOR_DFT_WM,
2769 PINEVIEW_CURSOR_GUARD_WM,
2770 PINEVIEW_FIFO_LINE_SIZE
2772 static struct intel_watermark_params g4x_wm_info = {
2779 static struct intel_watermark_params g4x_cursor_wm_info = {
2786 static struct intel_watermark_params i965_cursor_wm_info = {
2791 I915_FIFO_LINE_SIZE,
2793 static struct intel_watermark_params i945_wm_info = {
2800 static struct intel_watermark_params i915_wm_info = {
2807 static struct intel_watermark_params i855_wm_info = {
2814 static struct intel_watermark_params i830_wm_info = {
2822 static struct intel_watermark_params ironlake_display_wm_info = {
2830 static struct intel_watermark_params ironlake_cursor_wm_info = {
2838 static struct intel_watermark_params ironlake_display_srwm_info = {
2839 ILK_DISPLAY_SR_FIFO,
2840 ILK_DISPLAY_MAX_SRWM,
2841 ILK_DISPLAY_DFT_SRWM,
2846 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2848 ILK_CURSOR_MAX_SRWM,
2849 ILK_CURSOR_DFT_SRWM,
2854 static struct intel_watermark_params sandybridge_display_wm_info = {
2862 static struct intel_watermark_params sandybridge_cursor_wm_info = {
2870 static struct intel_watermark_params sandybridge_display_srwm_info = {
2871 SNB_DISPLAY_SR_FIFO,
2872 SNB_DISPLAY_MAX_SRWM,
2873 SNB_DISPLAY_DFT_SRWM,
2878 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2880 SNB_CURSOR_MAX_SRWM,
2881 SNB_CURSOR_DFT_SRWM,
2888 * intel_calculate_wm - calculate watermark level
2889 * @clock_in_khz: pixel clock
2890 * @wm: chip FIFO params
2891 * @pixel_size: display pixel size
2892 * @latency_ns: memory latency for the platform
2894 * Calculate the watermark level (the level at which the display plane will
2895 * start fetching from memory again). Each chip has a different display
2896 * FIFO size and allocation, so the caller needs to figure that out and pass
2897 * in the correct intel_watermark_params structure.
2899 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2900 * on the pixel size. When it reaches the watermark level, it'll start
2901 * fetching FIFO line sized based chunks from memory until the FIFO fills
2902 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2903 * will occur, and a display engine hang could result.
2905 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2906 struct intel_watermark_params *wm,
2908 unsigned long latency_ns)
2910 long entries_required, wm_size;
2913 * Note: we need to make sure we don't overflow for various clock &
2915 * clocks go from a few thousand to several hundred thousand.
2916 * latency is usually a few thousand
2918 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2920 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2922 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2924 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2926 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2928 /* Don't promote wm_size to unsigned... */
2929 if (wm_size > (long)wm->max_wm)
2930 wm_size = wm->max_wm;
2932 wm_size = wm->default_wm;
2936 struct cxsr_latency {
2939 unsigned long fsb_freq;
2940 unsigned long mem_freq;
2941 unsigned long display_sr;
2942 unsigned long display_hpll_disable;
2943 unsigned long cursor_sr;
2944 unsigned long cursor_hpll_disable;
2947 static const struct cxsr_latency cxsr_latency_table[] = {
2948 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2949 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2950 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2951 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2952 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2954 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2955 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2956 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2957 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2958 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2960 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2961 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2962 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2963 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2964 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2966 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2967 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2968 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2969 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2970 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2972 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2973 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2974 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2975 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2976 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2978 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2979 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2980 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2981 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2982 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2985 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2990 const struct cxsr_latency *latency;
2993 if (fsb == 0 || mem == 0)
2996 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2997 latency = &cxsr_latency_table[i];
2998 if (is_desktop == latency->is_desktop &&
2999 is_ddr3 == latency->is_ddr3 &&
3000 fsb == latency->fsb_freq && mem == latency->mem_freq)
3004 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3009 static void pineview_disable_cxsr(struct drm_device *dev)
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3013 /* deactivate cxsr */
3014 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3018 * Latency for FIFO fetches is dependent on several factors:
3019 * - memory configuration (speed, channels)
3021 * - current MCH state
3022 * It can be fairly high in some situations, so here we assume a fairly
3023 * pessimal value. It's a tradeoff between extra memory fetches (if we
3024 * set this value too high, the FIFO will fetch frequently to stay full)
3025 * and power consumption (set it too low to save power and we might see
3026 * FIFO underruns and display "flicker").
3028 * A value of 5us seems to be a good balance; safe for very low end
3029 * platforms but not overly aggressive on lower latency configs.
3031 static const int latency_ns = 5000;
3033 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 uint32_t dsparb = I915_READ(DSPARB);
3039 size = dsparb & 0x7f;
3041 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3043 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3044 plane ? "B" : "A", size);
3049 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 uint32_t dsparb = I915_READ(DSPARB);
3055 size = dsparb & 0x1ff;
3057 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3058 size >>= 1; /* Convert to cachelines */
3060 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3061 plane ? "B" : "A", size);
3066 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3068 struct drm_i915_private *dev_priv = dev->dev_private;
3069 uint32_t dsparb = I915_READ(DSPARB);
3072 size = dsparb & 0x7f;
3073 size >>= 2; /* Convert to cachelines */
3075 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3082 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 uint32_t dsparb = I915_READ(DSPARB);
3088 size = dsparb & 0x7f;
3089 size >>= 1; /* Convert to cachelines */
3091 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3092 plane ? "B" : "A", size);
3097 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3098 int planeb_clock, int sr_hdisplay, int unused,
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 const struct cxsr_latency *latency;
3107 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3108 dev_priv->fsb_freq, dev_priv->mem_freq);
3110 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3111 pineview_disable_cxsr(dev);
3115 if (!planea_clock || !planeb_clock) {
3116 sr_clock = planea_clock ? planea_clock : planeb_clock;
3119 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3120 pixel_size, latency->display_sr);
3121 reg = I915_READ(DSPFW1);
3122 reg &= ~DSPFW_SR_MASK;
3123 reg |= wm << DSPFW_SR_SHIFT;
3124 I915_WRITE(DSPFW1, reg);
3125 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3128 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3129 pixel_size, latency->cursor_sr);
3130 reg = I915_READ(DSPFW3);
3131 reg &= ~DSPFW_CURSOR_SR_MASK;
3132 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3133 I915_WRITE(DSPFW3, reg);
3135 /* Display HPLL off SR */
3136 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3137 pixel_size, latency->display_hpll_disable);
3138 reg = I915_READ(DSPFW3);
3139 reg &= ~DSPFW_HPLL_SR_MASK;
3140 reg |= wm & DSPFW_HPLL_SR_MASK;
3141 I915_WRITE(DSPFW3, reg);
3143 /* cursor HPLL off SR */
3144 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3145 pixel_size, latency->cursor_hpll_disable);
3146 reg = I915_READ(DSPFW3);
3147 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3148 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3149 I915_WRITE(DSPFW3, reg);
3150 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3154 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3155 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3157 pineview_disable_cxsr(dev);
3158 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3162 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3163 int planeb_clock, int sr_hdisplay, int sr_htotal,
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 int total_size, cacheline_size;
3168 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3169 struct intel_watermark_params planea_params, planeb_params;
3170 unsigned long line_time_us;
3171 int sr_clock, sr_entries = 0, entries_required;
3173 /* Create copies of the base settings for each pipe */
3174 planea_params = planeb_params = g4x_wm_info;
3176 /* Grab a couple of global values before we overwrite them */
3177 total_size = planea_params.fifo_size;
3178 cacheline_size = planea_params.cacheline_size;
3181 * Note: we need to make sure we don't overflow for various clock &
3183 * clocks go from a few thousand to several hundred thousand.
3184 * latency is usually a few thousand
3186 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3188 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3189 planea_wm = entries_required + planea_params.guard_size;
3191 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3193 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3194 planeb_wm = entries_required + planeb_params.guard_size;
3196 cursora_wm = cursorb_wm = 16;
3199 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3201 /* Calc sr entries for one plane configs */
3202 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3203 /* self-refresh has much higher latency */
3204 static const int sr_latency_ns = 12000;
3206 sr_clock = planea_clock ? planea_clock : planeb_clock;
3207 line_time_us = ((sr_htotal * 1000) / sr_clock);
3209 /* Use ns/us then divide to preserve precision */
3210 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3211 pixel_size * sr_hdisplay;
3212 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3214 entries_required = (((sr_latency_ns / line_time_us) +
3215 1000) / 1000) * pixel_size * 64;
3216 entries_required = DIV_ROUND_UP(entries_required,
3217 g4x_cursor_wm_info.cacheline_size);
3218 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3220 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3221 cursor_sr = g4x_cursor_wm_info.max_wm;
3222 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3223 "cursor %d\n", sr_entries, cursor_sr);
3225 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3227 /* Turn off self refresh if both pipes are enabled */
3228 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3232 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3233 planea_wm, planeb_wm, sr_entries);
3238 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3239 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3240 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3241 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3242 (cursora_wm << DSPFW_CURSORA_SHIFT));
3243 /* HPLL off in SR has some issues on G4x... disable it */
3244 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3245 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3248 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3249 int planeb_clock, int sr_hdisplay, int sr_htotal,
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 unsigned long line_time_us;
3254 int sr_clock, sr_entries, srwm = 1;
3257 /* Calc sr entries for one plane configs */
3258 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3259 /* self-refresh has much higher latency */
3260 static const int sr_latency_ns = 12000;
3262 sr_clock = planea_clock ? planea_clock : planeb_clock;
3263 line_time_us = ((sr_htotal * 1000) / sr_clock);
3265 /* Use ns/us then divide to preserve precision */
3266 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3267 pixel_size * sr_hdisplay;
3268 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3269 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3270 srwm = I965_FIFO_SIZE - sr_entries;
3275 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3277 sr_entries = DIV_ROUND_UP(sr_entries,
3278 i965_cursor_wm_info.cacheline_size);
3279 cursor_sr = i965_cursor_wm_info.fifo_size -
3280 (sr_entries + i965_cursor_wm_info.guard_size);
3282 if (cursor_sr > i965_cursor_wm_info.max_wm)
3283 cursor_sr = i965_cursor_wm_info.max_wm;
3285 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3286 "cursor %d\n", srwm, cursor_sr);
3288 if (IS_CRESTLINE(dev))
3289 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3291 /* Turn off self refresh if both pipes are enabled */
3292 if (IS_CRESTLINE(dev))
3293 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3297 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3300 /* 965 has limitations... */
3301 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3303 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3304 /* update cursor SR watermark */
3305 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3308 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3309 int planeb_clock, int sr_hdisplay, int sr_htotal,
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3315 int total_size, cacheline_size, cwm, srwm = 1;
3316 int planea_wm, planeb_wm;
3317 struct intel_watermark_params planea_params, planeb_params;
3318 unsigned long line_time_us;
3319 int sr_clock, sr_entries = 0;
3321 /* Create copies of the base settings for each pipe */
3322 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3323 planea_params = planeb_params = i945_wm_info;
3324 else if (!IS_GEN2(dev))
3325 planea_params = planeb_params = i915_wm_info;
3327 planea_params = planeb_params = i855_wm_info;
3329 /* Grab a couple of global values before we overwrite them */
3330 total_size = planea_params.fifo_size;
3331 cacheline_size = planea_params.cacheline_size;
3333 /* Update per-plane FIFO sizes */
3334 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3335 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3337 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3338 pixel_size, latency_ns);
3339 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3340 pixel_size, latency_ns);
3341 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3344 * Overlay gets an aggressive default since video jitter is bad.
3348 /* Calc sr entries for one plane configs */
3349 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3350 (!planea_clock || !planeb_clock)) {
3351 /* self-refresh has much higher latency */
3352 static const int sr_latency_ns = 6000;
3354 sr_clock = planea_clock ? planea_clock : planeb_clock;
3355 line_time_us = ((sr_htotal * 1000) / sr_clock);
3357 /* Use ns/us then divide to preserve precision */
3358 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3359 pixel_size * sr_hdisplay;
3360 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3361 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3362 srwm = total_size - sr_entries;
3366 if (IS_I945G(dev) || IS_I945GM(dev))
3367 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3368 else if (IS_I915GM(dev)) {
3369 /* 915M has a smaller SRWM field */
3370 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3371 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3374 /* Turn off self refresh if both pipes are enabled */
3375 if (IS_I945G(dev) || IS_I945GM(dev)) {
3376 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3378 } else if (IS_I915GM(dev)) {
3379 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3383 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3384 planea_wm, planeb_wm, cwm, srwm);
3386 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3387 fwater_hi = (cwm & 0x1f);
3389 /* Set request length to 8 cachelines per fetch */
3390 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3391 fwater_hi = fwater_hi | (1 << 8);
3393 I915_WRITE(FW_BLC, fwater_lo);
3394 I915_WRITE(FW_BLC2, fwater_hi);
3397 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3398 int unused2, int unused3, int pixel_size)
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3404 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3406 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3407 pixel_size, latency_ns);
3408 fwater_lo |= (3<<8) | planea_wm;
3410 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3412 I915_WRITE(FW_BLC, fwater_lo);
3415 #define ILK_LP0_PLANE_LATENCY 700
3416 #define ILK_LP0_CURSOR_LATENCY 1300
3418 static bool ironlake_compute_wm0(struct drm_device *dev,
3420 const struct intel_watermark_params *display,
3421 int display_latency_ns,
3422 const struct intel_watermark_params *cursor,
3423 int cursor_latency_ns,
3427 struct drm_crtc *crtc;
3428 int htotal, hdisplay, clock, pixel_size = 0;
3429 int line_time_us, line_count, entries;
3431 crtc = intel_get_crtc_for_pipe(dev, pipe);
3432 if (crtc->fb == NULL || !crtc->enabled)
3435 htotal = crtc->mode.htotal;
3436 hdisplay = crtc->mode.hdisplay;
3437 clock = crtc->mode.clock;
3438 pixel_size = crtc->fb->bits_per_pixel / 8;
3440 /* Use the small buffer method to calculate plane watermark */
3441 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3442 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3443 *plane_wm = entries + display->guard_size;
3444 if (*plane_wm > (int)display->max_wm)
3445 *plane_wm = display->max_wm;
3447 /* Use the large buffer method to calculate cursor watermark */
3448 line_time_us = ((htotal * 1000) / clock);
3449 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3450 entries = line_count * 64 * pixel_size;
3451 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3452 *cursor_wm = entries + cursor->guard_size;
3453 if (*cursor_wm > (int)cursor->max_wm)
3454 *cursor_wm = (int)cursor->max_wm;
3460 * Check the wm result.
3462 * If any calculated watermark values is larger than the maximum value that
3463 * can be programmed into the associated watermark register, that watermark
3466 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3467 int fbc_wm, int display_wm, int cursor_wm,
3468 const struct intel_watermark_params *display,
3469 const struct intel_watermark_params *cursor)
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3473 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3474 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3476 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3477 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3478 fbc_wm, SNB_FBC_MAX_SRWM, level);
3480 /* fbc has it's own way to disable FBC WM */
3481 I915_WRITE(DISP_ARB_CTL,
3482 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3486 if (display_wm > display->max_wm) {
3487 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3488 display_wm, SNB_DISPLAY_MAX_SRWM, level);
3492 if (cursor_wm > cursor->max_wm) {
3493 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3494 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3498 if (!(fbc_wm || display_wm || cursor_wm)) {
3499 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3507 * Compute watermark values of WM[1-3],
3509 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3510 int hdisplay, int htotal,
3511 int pixel_size, int clock, int latency_ns,
3512 const struct intel_watermark_params *display,
3513 const struct intel_watermark_params *cursor,
3514 int *fbc_wm, int *display_wm, int *cursor_wm)
3517 unsigned long line_time_us;
3518 int line_count, line_size;
3523 *fbc_wm = *display_wm = *cursor_wm = 0;
3527 line_time_us = (htotal * 1000) / clock;
3528 line_count = (latency_ns / line_time_us + 1000) / 1000;
3529 line_size = hdisplay * pixel_size;
3531 /* Use the minimum of the small and large buffer method for primary */
3532 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3533 large = line_count * line_size;
3535 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3536 *display_wm = entries + display->guard_size;
3540 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3542 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3544 /* calculate the self-refresh watermark for display cursor */
3545 entries = line_count * pixel_size * 64;
3546 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3547 *cursor_wm = entries + cursor->guard_size;
3549 return ironlake_check_srwm(dev, level,
3550 *fbc_wm, *display_wm, *cursor_wm,
3554 static void ironlake_update_wm(struct drm_device *dev,
3555 int planea_clock, int planeb_clock,
3556 int hdisplay, int htotal,
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 int fbc_wm, plane_wm, cursor_wm, enabled;
3564 if (ironlake_compute_wm0(dev, 0,
3565 &ironlake_display_wm_info,
3566 ILK_LP0_PLANE_LATENCY,
3567 &ironlake_cursor_wm_info,
3568 ILK_LP0_CURSOR_LATENCY,
3569 &plane_wm, &cursor_wm)) {
3570 I915_WRITE(WM0_PIPEA_ILK,
3571 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3572 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3573 " plane %d, " "cursor: %d\n",
3574 plane_wm, cursor_wm);
3578 if (ironlake_compute_wm0(dev, 1,
3579 &ironlake_display_wm_info,
3580 ILK_LP0_PLANE_LATENCY,
3581 &ironlake_cursor_wm_info,
3582 ILK_LP0_CURSOR_LATENCY,
3583 &plane_wm, &cursor_wm)) {
3584 I915_WRITE(WM0_PIPEB_ILK,
3585 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3586 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3587 " plane %d, cursor: %d\n",
3588 plane_wm, cursor_wm);
3593 * Calculate and update the self-refresh watermark only when one
3594 * display plane is used.
3596 I915_WRITE(WM3_LP_ILK, 0);
3597 I915_WRITE(WM2_LP_ILK, 0);
3598 I915_WRITE(WM1_LP_ILK, 0);
3603 clock = planea_clock ? planea_clock : planeb_clock;
3606 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3607 clock, ILK_READ_WM1_LATENCY() * 500,
3608 &ironlake_display_srwm_info,
3609 &ironlake_cursor_srwm_info,
3610 &fbc_wm, &plane_wm, &cursor_wm))
3613 I915_WRITE(WM1_LP_ILK,
3615 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3616 (fbc_wm << WM1_LP_FBC_SHIFT) |
3617 (plane_wm << WM1_LP_SR_SHIFT) |
3621 if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
3622 clock, ILK_READ_WM2_LATENCY() * 500,
3623 &ironlake_display_srwm_info,
3624 &ironlake_cursor_srwm_info,
3625 &fbc_wm, &plane_wm, &cursor_wm))
3628 I915_WRITE(WM2_LP_ILK,
3630 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3631 (fbc_wm << WM1_LP_FBC_SHIFT) |
3632 (plane_wm << WM1_LP_SR_SHIFT) |
3636 * WM3 is unsupported on ILK, probably because we don't have latency
3637 * data for that power state
3641 static void sandybridge_update_wm(struct drm_device *dev,
3642 int planea_clock, int planeb_clock,
3643 int hdisplay, int htotal,
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
3648 int fbc_wm, plane_wm, cursor_wm, enabled;
3652 if (ironlake_compute_wm0(dev, 0,
3653 &sandybridge_display_wm_info, latency,
3654 &sandybridge_cursor_wm_info, latency,
3655 &plane_wm, &cursor_wm)) {
3656 I915_WRITE(WM0_PIPEA_ILK,
3657 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3658 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3659 " plane %d, " "cursor: %d\n",
3660 plane_wm, cursor_wm);
3664 if (ironlake_compute_wm0(dev, 1,
3665 &sandybridge_display_wm_info, latency,
3666 &sandybridge_cursor_wm_info, latency,
3667 &plane_wm, &cursor_wm)) {
3668 I915_WRITE(WM0_PIPEB_ILK,
3669 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3670 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3671 " plane %d, cursor: %d\n",
3672 plane_wm, cursor_wm);
3677 * Calculate and update the self-refresh watermark only when one
3678 * display plane is used.
3680 * SNB support 3 levels of watermark.
3682 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3683 * and disabled in the descending order
3686 I915_WRITE(WM3_LP_ILK, 0);
3687 I915_WRITE(WM2_LP_ILK, 0);
3688 I915_WRITE(WM1_LP_ILK, 0);
3693 clock = planea_clock ? planea_clock : planeb_clock;
3696 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3697 clock, SNB_READ_WM1_LATENCY() * 500,
3698 &sandybridge_display_srwm_info,
3699 &sandybridge_cursor_srwm_info,
3700 &fbc_wm, &plane_wm, &cursor_wm))
3703 I915_WRITE(WM1_LP_ILK,
3705 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3706 (fbc_wm << WM1_LP_FBC_SHIFT) |
3707 (plane_wm << WM1_LP_SR_SHIFT) |
3711 if (!ironlake_compute_srwm(dev, 2,
3712 hdisplay, htotal, pixel_size,
3713 clock, SNB_READ_WM2_LATENCY() * 500,
3714 &sandybridge_display_srwm_info,
3715 &sandybridge_cursor_srwm_info,
3716 &fbc_wm, &plane_wm, &cursor_wm))
3719 I915_WRITE(WM2_LP_ILK,
3721 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3722 (fbc_wm << WM1_LP_FBC_SHIFT) |
3723 (plane_wm << WM1_LP_SR_SHIFT) |
3727 if (!ironlake_compute_srwm(dev, 3,
3728 hdisplay, htotal, pixel_size,
3729 clock, SNB_READ_WM3_LATENCY() * 500,
3730 &sandybridge_display_srwm_info,
3731 &sandybridge_cursor_srwm_info,
3732 &fbc_wm, &plane_wm, &cursor_wm))
3735 I915_WRITE(WM3_LP_ILK,
3737 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3738 (fbc_wm << WM1_LP_FBC_SHIFT) |
3739 (plane_wm << WM1_LP_SR_SHIFT) |
3744 * intel_update_watermarks - update FIFO watermark values based on current modes
3746 * Calculate watermark values for the various WM regs based on current mode
3747 * and plane configuration.
3749 * There are several cases to deal with here:
3750 * - normal (i.e. non-self-refresh)
3751 * - self-refresh (SR) mode
3752 * - lines are large relative to FIFO size (buffer can hold up to 2)
3753 * - lines are small relative to FIFO size (buffer can hold more than 2
3754 * lines), so need to account for TLB latency
3756 * The normal calculation is:
3757 * watermark = dotclock * bytes per pixel * latency
3758 * where latency is platform & configuration dependent (we assume pessimal
3761 * The SR calculation is:
3762 * watermark = (trunc(latency/line time)+1) * surface width *
3765 * line time = htotal / dotclock
3766 * surface width = hdisplay for normal plane and 64 for cursor
3767 * and latency is assumed to be high, as above.
3769 * The final value programmed to the register should always be rounded up,
3770 * and include an extra 2 entries to account for clock crossings.
3772 * We don't use the sprite, so we can ignore that. And on Crestline we have
3773 * to set the non-SR watermarks to 8.
3775 static void intel_update_watermarks(struct drm_device *dev)
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778 struct drm_crtc *crtc;
3779 int sr_hdisplay = 0;
3780 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3781 int enabled = 0, pixel_size = 0;
3784 if (!dev_priv->display.update_wm)
3787 /* Get the clock config from both planes */
3788 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 if (intel_crtc->active) {
3792 if (intel_crtc->plane == 0) {
3793 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3794 intel_crtc->pipe, crtc->mode.clock);
3795 planea_clock = crtc->mode.clock;
3797 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3798 intel_crtc->pipe, crtc->mode.clock);
3799 planeb_clock = crtc->mode.clock;
3801 sr_hdisplay = crtc->mode.hdisplay;
3802 sr_clock = crtc->mode.clock;
3803 sr_htotal = crtc->mode.htotal;
3805 pixel_size = crtc->fb->bits_per_pixel / 8;
3807 pixel_size = 4; /* by default */
3814 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3815 sr_hdisplay, sr_htotal, pixel_size);
3818 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3819 struct drm_display_mode *mode,
3820 struct drm_display_mode *adjusted_mode,
3822 struct drm_framebuffer *old_fb)
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 int plane = intel_crtc->plane;
3829 u32 fp_reg, dpll_reg;
3830 int refclk, num_connectors = 0;
3831 intel_clock_t clock, reduced_clock;
3832 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3833 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3834 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3835 struct intel_encoder *has_edp_encoder = NULL;
3836 struct drm_mode_config *mode_config = &dev->mode_config;
3837 struct intel_encoder *encoder;
3838 const intel_limit_t *limit;
3840 struct fdi_m_n m_n = {0};
3844 drm_vblank_pre_modeset(dev, pipe);
3846 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3847 if (encoder->base.crtc != crtc)
3850 switch (encoder->type) {
3851 case INTEL_OUTPUT_LVDS:
3854 case INTEL_OUTPUT_SDVO:
3855 case INTEL_OUTPUT_HDMI:
3857 if (encoder->needs_tv_clock)
3860 case INTEL_OUTPUT_DVO:
3863 case INTEL_OUTPUT_TVOUT:
3866 case INTEL_OUTPUT_ANALOG:
3869 case INTEL_OUTPUT_DISPLAYPORT:
3872 case INTEL_OUTPUT_EDP:
3873 has_edp_encoder = encoder;
3880 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3881 refclk = dev_priv->lvds_ssc_freq * 1000;
3882 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3884 } else if (!IS_GEN2(dev)) {
3886 if (HAS_PCH_SPLIT(dev) &&
3887 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3888 refclk = 120000; /* 120Mhz refclk */
3894 * Returns a set of divisors for the desired target clock with the given
3895 * refclk, or FALSE. The returned values represent the clock equation:
3896 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3898 limit = intel_limit(crtc, refclk);
3899 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3901 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3902 drm_vblank_post_modeset(dev, pipe);
3906 /* Ensure that the cursor is valid for the new mode before changing... */
3907 intel_crtc_update_cursor(crtc, true);
3909 if (is_lvds && dev_priv->lvds_downclock_avail) {
3910 has_reduced_clock = limit->find_pll(limit, crtc,
3911 dev_priv->lvds_downclock,
3914 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3916 * If the different P is found, it means that we can't
3917 * switch the display clock by using the FP0/FP1.
3918 * In such case we will disable the LVDS downclock
3921 DRM_DEBUG_KMS("Different P is found for "
3922 "LVDS clock/downclock\n");
3923 has_reduced_clock = 0;
3926 /* SDVO TV has fixed PLL values depend on its clock range,
3927 this mirrors vbios setting. */
3928 if (is_sdvo && is_tv) {
3929 if (adjusted_mode->clock >= 100000
3930 && adjusted_mode->clock < 140500) {
3936 } else if (adjusted_mode->clock >= 140500
3937 && adjusted_mode->clock <= 200000) {
3947 if (HAS_PCH_SPLIT(dev)) {
3948 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3949 int lane = 0, link_bw, bpp;
3950 /* CPU eDP doesn't require FDI link, so just set DP M/N
3951 according to current link config */
3952 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3953 target_clock = mode->clock;
3954 intel_edp_link_config(has_edp_encoder,
3957 /* [e]DP over FDI requires target mode clock
3958 instead of link clock */
3959 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3960 target_clock = mode->clock;
3962 target_clock = adjusted_mode->clock;
3964 /* FDI is a binary signal running at ~2.7GHz, encoding
3965 * each output octet as 10 bits. The actual frequency
3966 * is stored as a divider into a 100MHz clock, and the
3967 * mode pixel clock is stored in units of 1KHz.
3968 * Hence the bw of each lane in terms of the mode signal
3971 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3974 /* determine panel color depth */
3975 temp = I915_READ(PIPECONF(pipe));
3976 temp &= ~PIPE_BPC_MASK;
3978 /* the BPC will be 6 if it is 18-bit LVDS panel */
3979 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3983 } else if (has_edp_encoder) {
3984 switch (dev_priv->edp.bpp/3) {
4000 I915_WRITE(PIPECONF(pipe), temp);
4002 switch (temp & PIPE_BPC_MASK) {
4016 DRM_ERROR("unknown pipe bpc value\n");
4022 * Account for spread spectrum to avoid
4023 * oversubscribing the link. Max center spread
4024 * is 2.5%; use 5% for safety's sake.
4026 u32 bps = target_clock * bpp * 21 / 20;
4027 lane = bps / (link_bw * 8) + 1;
4030 intel_crtc->fdi_lanes = lane;
4032 if (pixel_multiplier > 1)
4033 link_bw *= pixel_multiplier;
4034 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4037 /* Ironlake: try to setup display ref clock before DPLL
4038 * enabling. This is only under driver's control after
4039 * PCH B stepping, previous chipset stepping should be
4040 * ignoring this setting.
4042 if (HAS_PCH_SPLIT(dev)) {
4043 temp = I915_READ(PCH_DREF_CONTROL);
4044 /* Always enable nonspread source */
4045 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4046 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4047 temp &= ~DREF_SSC_SOURCE_MASK;
4048 temp |= DREF_SSC_SOURCE_ENABLE;
4049 I915_WRITE(PCH_DREF_CONTROL, temp);
4051 POSTING_READ(PCH_DREF_CONTROL);
4054 if (has_edp_encoder) {
4055 if (dev_priv->lvds_use_ssc) {
4056 temp |= DREF_SSC1_ENABLE;
4057 I915_WRITE(PCH_DREF_CONTROL, temp);
4059 POSTING_READ(PCH_DREF_CONTROL);
4062 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4064 /* Enable CPU source on CPU attached eDP */
4065 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4066 if (dev_priv->lvds_use_ssc)
4067 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4069 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4071 /* Enable SSC on PCH eDP if needed */
4072 if (dev_priv->lvds_use_ssc) {
4073 DRM_ERROR("enabling SSC on PCH\n");
4074 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4077 I915_WRITE(PCH_DREF_CONTROL, temp);
4078 POSTING_READ(PCH_DREF_CONTROL);
4083 if (IS_PINEVIEW(dev)) {
4084 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4085 if (has_reduced_clock)
4086 fp2 = (1 << reduced_clock.n) << 16 |
4087 reduced_clock.m1 << 8 | reduced_clock.m2;
4089 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4090 if (has_reduced_clock)
4091 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4095 /* Enable autotuning of the PLL clock (if permissible) */
4096 if (HAS_PCH_SPLIT(dev)) {
4100 if ((dev_priv->lvds_use_ssc &&
4101 dev_priv->lvds_ssc_freq == 100) ||
4102 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4104 } else if (is_sdvo && is_tv)
4107 if (clock.m1 < factor * clock.n)
4112 if (!HAS_PCH_SPLIT(dev))
4113 dpll = DPLL_VGA_MODE_DIS;
4115 if (!IS_GEN2(dev)) {
4117 dpll |= DPLLB_MODE_LVDS;
4119 dpll |= DPLLB_MODE_DAC_SERIAL;
4121 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4122 if (pixel_multiplier > 1) {
4123 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4124 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4125 else if (HAS_PCH_SPLIT(dev))
4126 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4128 dpll |= DPLL_DVO_HIGH_SPEED;
4130 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4131 dpll |= DPLL_DVO_HIGH_SPEED;
4133 /* compute bitmask from p1 value */
4134 if (IS_PINEVIEW(dev))
4135 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4137 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4139 if (HAS_PCH_SPLIT(dev))
4140 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4141 if (IS_G4X(dev) && has_reduced_clock)
4142 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4146 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4149 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4152 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4155 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4158 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4159 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4162 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4165 dpll |= PLL_P1_DIVIDE_BY_TWO;
4167 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4169 dpll |= PLL_P2_DIVIDE_BY_4;
4173 if (is_sdvo && is_tv)
4174 dpll |= PLL_REF_INPUT_TVCLKINBC;
4176 /* XXX: just matching BIOS for now */
4177 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4179 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
4180 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4182 dpll |= PLL_REF_INPUT_DREFCLK;
4184 /* setup pipeconf */
4185 pipeconf = I915_READ(PIPECONF(pipe));
4187 /* Set up the display plane register */
4188 dspcntr = DISPPLANE_GAMMA_ENABLE;
4190 /* Ironlake's plane is forced to pipe, bit 24 is to
4191 enable color space conversion */
4192 if (!HAS_PCH_SPLIT(dev)) {
4194 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4196 dspcntr |= DISPPLANE_SEL_PIPE_B;
4199 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4200 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4203 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4207 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4208 pipeconf |= PIPECONF_DOUBLE_WIDE;
4210 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4213 dspcntr |= DISPLAY_PLANE_ENABLE;
4214 pipeconf |= PIPECONF_ENABLE;
4215 dpll |= DPLL_VCO_ENABLE;
4217 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4218 drm_mode_debug_printmodeline(mode);
4220 /* assign to Ironlake registers */
4221 if (HAS_PCH_SPLIT(dev)) {
4222 fp_reg = PCH_FP0(pipe);
4223 dpll_reg = PCH_DPLL(pipe);
4226 dpll_reg = DPLL(pipe);
4229 /* PCH eDP needs FDI, but CPU eDP does not */
4230 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4231 I915_WRITE(fp_reg, fp);
4232 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4234 POSTING_READ(dpll_reg);
4238 /* enable transcoder DPLL */
4239 if (HAS_PCH_CPT(dev)) {
4240 temp = I915_READ(PCH_DPLL_SEL);
4242 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4244 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4245 I915_WRITE(PCH_DPLL_SEL, temp);
4247 POSTING_READ(PCH_DPLL_SEL);
4251 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4252 * This is an exception to the general rule that mode_set doesn't turn
4257 if (HAS_PCH_SPLIT(dev))
4260 temp = I915_READ(reg);
4261 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4263 if (HAS_PCH_CPT(dev))
4264 temp |= PORT_TRANS_B_SEL_CPT;
4266 temp |= LVDS_PIPEB_SELECT;
4268 if (HAS_PCH_CPT(dev))
4269 temp &= ~PORT_TRANS_SEL_MASK;
4271 temp &= ~LVDS_PIPEB_SELECT;
4273 /* set the corresponsding LVDS_BORDER bit */
4274 temp |= dev_priv->lvds_border_bits;
4275 /* Set the B0-B3 data pairs corresponding to whether we're going to
4276 * set the DPLLs for dual-channel mode or not.
4279 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4281 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4283 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4284 * appropriately here, but we need to look more thoroughly into how
4285 * panels behave in the two modes.
4287 /* set the dithering flag on non-PCH LVDS as needed */
4288 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4289 if (dev_priv->lvds_dither)
4290 temp |= LVDS_ENABLE_DITHER;
4292 temp &= ~LVDS_ENABLE_DITHER;
4294 I915_WRITE(reg, temp);
4297 /* set the dithering flag and clear for anything other than a panel. */
4298 if (HAS_PCH_SPLIT(dev)) {
4299 pipeconf &= ~PIPECONF_DITHER_EN;
4300 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4301 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4302 pipeconf |= PIPECONF_DITHER_EN;
4303 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4307 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4308 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4309 } else if (HAS_PCH_SPLIT(dev)) {
4310 /* For non-DP output, clear any trans DP clock recovery setting.*/
4312 I915_WRITE(TRANSA_DATA_M1, 0);
4313 I915_WRITE(TRANSA_DATA_N1, 0);
4314 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4315 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4317 I915_WRITE(TRANSB_DATA_M1, 0);
4318 I915_WRITE(TRANSB_DATA_N1, 0);
4319 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4320 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4324 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4325 I915_WRITE(dpll_reg, dpll);
4327 /* Wait for the clocks to stabilize. */
4328 POSTING_READ(dpll_reg);
4331 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4334 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4336 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4340 I915_WRITE(DPLL_MD(pipe), temp);
4342 /* The pixel multiplier can only be updated once the
4343 * DPLL is enabled and the clocks are stable.
4345 * So write it again.
4347 I915_WRITE(dpll_reg, dpll);
4351 intel_crtc->lowfreq_avail = false;
4352 if (is_lvds && has_reduced_clock && i915_powersave) {
4353 I915_WRITE(fp_reg + 4, fp2);
4354 intel_crtc->lowfreq_avail = true;
4355 if (HAS_PIPE_CXSR(dev)) {
4356 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4357 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4360 I915_WRITE(fp_reg + 4, fp);
4361 if (HAS_PIPE_CXSR(dev)) {
4362 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4363 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4367 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4368 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4369 /* the chip adds 2 halflines automatically */
4370 adjusted_mode->crtc_vdisplay -= 1;
4371 adjusted_mode->crtc_vtotal -= 1;
4372 adjusted_mode->crtc_vblank_start -= 1;
4373 adjusted_mode->crtc_vblank_end -= 1;
4374 adjusted_mode->crtc_vsync_end -= 1;
4375 adjusted_mode->crtc_vsync_start -= 1;
4377 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4379 I915_WRITE(HTOTAL(pipe),
4380 (adjusted_mode->crtc_hdisplay - 1) |
4381 ((adjusted_mode->crtc_htotal - 1) << 16));
4382 I915_WRITE(HBLANK(pipe),
4383 (adjusted_mode->crtc_hblank_start - 1) |
4384 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4385 I915_WRITE(HSYNC(pipe),
4386 (adjusted_mode->crtc_hsync_start - 1) |
4387 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4389 I915_WRITE(VTOTAL(pipe),
4390 (adjusted_mode->crtc_vdisplay - 1) |
4391 ((adjusted_mode->crtc_vtotal - 1) << 16));
4392 I915_WRITE(VBLANK(pipe),
4393 (adjusted_mode->crtc_vblank_start - 1) |
4394 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4395 I915_WRITE(VSYNC(pipe),
4396 (adjusted_mode->crtc_vsync_start - 1) |
4397 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4399 /* pipesrc and dspsize control the size that is scaled from,
4400 * which should always be the user's requested size.
4402 if (!HAS_PCH_SPLIT(dev)) {
4403 I915_WRITE(DSPSIZE(plane),
4404 ((mode->vdisplay - 1) << 16) |
4405 (mode->hdisplay - 1));
4406 I915_WRITE(DSPPOS(plane), 0);
4408 I915_WRITE(PIPESRC(pipe),
4409 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4411 if (HAS_PCH_SPLIT(dev)) {
4412 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4413 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4414 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4415 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4417 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4418 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4422 I915_WRITE(PIPECONF(pipe), pipeconf);
4423 POSTING_READ(PIPECONF(pipe));
4425 intel_wait_for_vblank(dev, pipe);
4428 /* enable address swizzle for tiling buffer */
4429 temp = I915_READ(DISP_ARB_CTL);
4430 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4433 I915_WRITE(DSPCNTR(plane), dspcntr);
4435 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4437 intel_update_watermarks(dev);
4439 drm_vblank_post_modeset(dev, pipe);
4444 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4445 void intel_crtc_load_lut(struct drm_crtc *crtc)
4447 struct drm_device *dev = crtc->dev;
4448 struct drm_i915_private *dev_priv = dev->dev_private;
4449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4450 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4453 /* The clocks have to be on to load the palette. */
4457 /* use legacy palette for Ironlake */
4458 if (HAS_PCH_SPLIT(dev))
4459 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4462 for (i = 0; i < 256; i++) {
4463 I915_WRITE(palreg + 4 * i,
4464 (intel_crtc->lut_r[i] << 16) |
4465 (intel_crtc->lut_g[i] << 8) |
4466 intel_crtc->lut_b[i]);
4470 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4472 struct drm_device *dev = crtc->dev;
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475 bool visible = base != 0;
4478 if (intel_crtc->cursor_visible == visible)
4481 cntl = I915_READ(CURACNTR);
4483 /* On these chipsets we can only modify the base whilst
4484 * the cursor is disabled.
4486 I915_WRITE(CURABASE, base);
4488 cntl &= ~(CURSOR_FORMAT_MASK);
4489 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4490 cntl |= CURSOR_ENABLE |
4491 CURSOR_GAMMA_ENABLE |
4494 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4495 I915_WRITE(CURACNTR, cntl);
4497 intel_crtc->cursor_visible = visible;
4500 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4502 struct drm_device *dev = crtc->dev;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4505 int pipe = intel_crtc->pipe;
4506 bool visible = base != 0;
4508 if (intel_crtc->cursor_visible != visible) {
4509 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4511 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4512 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4513 cntl |= pipe << 28; /* Connect to correct pipe */
4515 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4516 cntl |= CURSOR_MODE_DISABLE;
4518 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4520 intel_crtc->cursor_visible = visible;
4522 /* and commit changes on next vblank */
4523 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4526 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4527 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4530 struct drm_device *dev = crtc->dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4533 int pipe = intel_crtc->pipe;
4534 int x = intel_crtc->cursor_x;
4535 int y = intel_crtc->cursor_y;
4541 if (on && crtc->enabled && crtc->fb) {
4542 base = intel_crtc->cursor_addr;
4543 if (x > (int) crtc->fb->width)
4546 if (y > (int) crtc->fb->height)
4552 if (x + intel_crtc->cursor_width < 0)
4555 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4558 pos |= x << CURSOR_X_SHIFT;
4561 if (y + intel_crtc->cursor_height < 0)
4564 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4567 pos |= y << CURSOR_Y_SHIFT;
4569 visible = base != 0;
4570 if (!visible && !intel_crtc->cursor_visible)
4573 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4574 if (IS_845G(dev) || IS_I865G(dev))
4575 i845_update_cursor(crtc, base);
4577 i9xx_update_cursor(crtc, base);
4580 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4583 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4584 struct drm_file *file,
4586 uint32_t width, uint32_t height)
4588 struct drm_device *dev = crtc->dev;
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4591 struct drm_i915_gem_object *obj;
4595 DRM_DEBUG_KMS("\n");
4597 /* if we want to turn off the cursor ignore width and height */
4599 DRM_DEBUG_KMS("cursor off\n");
4602 mutex_lock(&dev->struct_mutex);
4606 /* Currently we only support 64x64 cursors */
4607 if (width != 64 || height != 64) {
4608 DRM_ERROR("we currently only support 64x64 cursors\n");
4612 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4616 if (obj->base.size < width * height * 4) {
4617 DRM_ERROR("buffer is to small\n");
4622 /* we only need to pin inside GTT if cursor is non-phy */
4623 mutex_lock(&dev->struct_mutex);
4624 if (!dev_priv->info->cursor_needs_physical) {
4625 if (obj->tiling_mode) {
4626 DRM_ERROR("cursor cannot be tiled\n");
4631 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4633 DRM_ERROR("failed to pin cursor bo\n");
4637 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4639 DRM_ERROR("failed to move cursor bo into the GTT\n");
4643 ret = i915_gem_object_put_fence(obj);
4645 DRM_ERROR("failed to move cursor bo into the GTT\n");
4649 addr = obj->gtt_offset;
4651 int align = IS_I830(dev) ? 16 * 1024 : 256;
4652 ret = i915_gem_attach_phys_object(dev, obj,
4653 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4656 DRM_ERROR("failed to attach phys object\n");
4659 addr = obj->phys_obj->handle->busaddr;
4663 I915_WRITE(CURSIZE, (height << 12) | width);
4666 if (intel_crtc->cursor_bo) {
4667 if (dev_priv->info->cursor_needs_physical) {
4668 if (intel_crtc->cursor_bo != obj)
4669 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4671 i915_gem_object_unpin(intel_crtc->cursor_bo);
4672 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4675 mutex_unlock(&dev->struct_mutex);
4677 intel_crtc->cursor_addr = addr;
4678 intel_crtc->cursor_bo = obj;
4679 intel_crtc->cursor_width = width;
4680 intel_crtc->cursor_height = height;
4682 intel_crtc_update_cursor(crtc, true);
4686 i915_gem_object_unpin(obj);
4688 mutex_unlock(&dev->struct_mutex);
4690 drm_gem_object_unreference_unlocked(&obj->base);
4694 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 intel_crtc->cursor_x = x;
4699 intel_crtc->cursor_y = y;
4701 intel_crtc_update_cursor(crtc, true);
4706 /** Sets the color ramps on behalf of RandR */
4707 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4708 u16 blue, int regno)
4710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 intel_crtc->lut_r[regno] = red >> 8;
4713 intel_crtc->lut_g[regno] = green >> 8;
4714 intel_crtc->lut_b[regno] = blue >> 8;
4717 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4718 u16 *blue, int regno)
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4722 *red = intel_crtc->lut_r[regno] << 8;
4723 *green = intel_crtc->lut_g[regno] << 8;
4724 *blue = intel_crtc->lut_b[regno] << 8;
4727 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4728 u16 *blue, uint32_t start, uint32_t size)
4730 int end = (start + size > 256) ? 256 : start + size, i;
4731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733 for (i = start; i < end; i++) {
4734 intel_crtc->lut_r[i] = red[i] >> 8;
4735 intel_crtc->lut_g[i] = green[i] >> 8;
4736 intel_crtc->lut_b[i] = blue[i] >> 8;
4739 intel_crtc_load_lut(crtc);
4743 * Get a pipe with a simple mode set on it for doing load-based monitor
4746 * It will be up to the load-detect code to adjust the pipe as appropriate for
4747 * its requirements. The pipe will be connected to no other encoders.
4749 * Currently this code will only succeed if there is a pipe with no encoders
4750 * configured for it. In the future, it could choose to temporarily disable
4751 * some outputs to free up a pipe for its use.
4753 * \return crtc, or NULL if no pipes are available.
4756 /* VESA 640x480x72Hz mode to set on the pipe */
4757 static struct drm_display_mode load_detect_mode = {
4758 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4759 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4762 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4763 struct drm_connector *connector,
4764 struct drm_display_mode *mode,
4767 struct intel_crtc *intel_crtc;
4768 struct drm_crtc *possible_crtc;
4769 struct drm_crtc *supported_crtc =NULL;
4770 struct drm_encoder *encoder = &intel_encoder->base;
4771 struct drm_crtc *crtc = NULL;
4772 struct drm_device *dev = encoder->dev;
4773 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4774 struct drm_crtc_helper_funcs *crtc_funcs;
4778 * Algorithm gets a little messy:
4779 * - if the connector already has an assigned crtc, use it (but make
4780 * sure it's on first)
4781 * - try to find the first unused crtc that can drive this connector,
4782 * and use that if we find one
4783 * - if there are no unused crtcs available, try to use the first
4784 * one we found that supports the connector
4787 /* See if we already have a CRTC for this connector */
4788 if (encoder->crtc) {
4789 crtc = encoder->crtc;
4790 /* Make sure the crtc and connector are running */
4791 intel_crtc = to_intel_crtc(crtc);
4792 *dpms_mode = intel_crtc->dpms_mode;
4793 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4794 crtc_funcs = crtc->helper_private;
4795 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4796 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4801 /* Find an unused one (if possible) */
4802 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4804 if (!(encoder->possible_crtcs & (1 << i)))
4806 if (!possible_crtc->enabled) {
4807 crtc = possible_crtc;
4810 if (!supported_crtc)
4811 supported_crtc = possible_crtc;
4815 * If we didn't find an unused CRTC, don't use any.
4821 encoder->crtc = crtc;
4822 connector->encoder = encoder;
4823 intel_encoder->load_detect_temp = true;
4825 intel_crtc = to_intel_crtc(crtc);
4826 *dpms_mode = intel_crtc->dpms_mode;
4828 if (!crtc->enabled) {
4830 mode = &load_detect_mode;
4831 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4833 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4834 crtc_funcs = crtc->helper_private;
4835 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4838 /* Add this connector to the crtc */
4839 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4840 encoder_funcs->commit(encoder);
4842 /* let the connector get through one full cycle before testing */
4843 intel_wait_for_vblank(dev, intel_crtc->pipe);
4848 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4849 struct drm_connector *connector, int dpms_mode)
4851 struct drm_encoder *encoder = &intel_encoder->base;
4852 struct drm_device *dev = encoder->dev;
4853 struct drm_crtc *crtc = encoder->crtc;
4854 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4855 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4857 if (intel_encoder->load_detect_temp) {
4858 encoder->crtc = NULL;
4859 connector->encoder = NULL;
4860 intel_encoder->load_detect_temp = false;
4861 crtc->enabled = drm_helper_crtc_in_use(crtc);
4862 drm_helper_disable_unused_functions(dev);
4865 /* Switch crtc and encoder back off if necessary */
4866 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4867 if (encoder->crtc == crtc)
4868 encoder_funcs->dpms(encoder, dpms_mode);
4869 crtc_funcs->dpms(crtc, dpms_mode);
4873 /* Returns the clock of the currently programmed mode of the given pipe. */
4874 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878 int pipe = intel_crtc->pipe;
4879 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4881 intel_clock_t clock;
4883 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4884 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4886 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4888 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4889 if (IS_PINEVIEW(dev)) {
4890 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4891 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4893 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4894 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4897 if (!IS_GEN2(dev)) {
4898 if (IS_PINEVIEW(dev))
4899 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4900 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4902 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4903 DPLL_FPA01_P1_POST_DIV_SHIFT);
4905 switch (dpll & DPLL_MODE_MASK) {
4906 case DPLLB_MODE_DAC_SERIAL:
4907 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4910 case DPLLB_MODE_LVDS:
4911 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4915 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4916 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4920 /* XXX: Handle the 100Mhz refclk */
4921 intel_clock(dev, 96000, &clock);
4923 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4926 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4927 DPLL_FPA01_P1_POST_DIV_SHIFT);
4930 if ((dpll & PLL_REF_INPUT_MASK) ==
4931 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4932 /* XXX: might not be 66MHz */
4933 intel_clock(dev, 66000, &clock);
4935 intel_clock(dev, 48000, &clock);
4937 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4940 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4941 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4943 if (dpll & PLL_P2_DIVIDE_BY_4)
4948 intel_clock(dev, 48000, &clock);
4952 /* XXX: It would be nice to validate the clocks, but we can't reuse
4953 * i830PllIsValid() because it relies on the xf86_config connector
4954 * configuration being accurate, which it isn't necessarily.
4960 /** Returns the currently programmed mode of the given pipe. */
4961 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4962 struct drm_crtc *crtc)
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966 int pipe = intel_crtc->pipe;
4967 struct drm_display_mode *mode;
4968 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4969 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4970 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4971 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4973 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4977 mode->clock = intel_crtc_clock_get(dev, crtc);
4978 mode->hdisplay = (htot & 0xffff) + 1;
4979 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4980 mode->hsync_start = (hsync & 0xffff) + 1;
4981 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4982 mode->vdisplay = (vtot & 0xffff) + 1;
4983 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4984 mode->vsync_start = (vsync & 0xffff) + 1;
4985 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4987 drm_mode_set_name(mode);
4988 drm_mode_set_crtcinfo(mode, 0);
4993 #define GPU_IDLE_TIMEOUT 500 /* ms */
4995 /* When this timer fires, we've been idle for awhile */
4996 static void intel_gpu_idle_timer(unsigned long arg)
4998 struct drm_device *dev = (struct drm_device *)arg;
4999 drm_i915_private_t *dev_priv = dev->dev_private;
5001 if (!list_empty(&dev_priv->mm.active_list)) {
5002 /* Still processing requests, so just re-arm the timer. */
5003 mod_timer(&dev_priv->idle_timer, jiffies +
5004 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5008 dev_priv->busy = false;
5009 queue_work(dev_priv->wq, &dev_priv->idle_work);
5012 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5014 static void intel_crtc_idle_timer(unsigned long arg)
5016 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5017 struct drm_crtc *crtc = &intel_crtc->base;
5018 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5019 struct intel_framebuffer *intel_fb;
5021 intel_fb = to_intel_framebuffer(crtc->fb);
5022 if (intel_fb && intel_fb->obj->active) {
5023 /* The framebuffer is still being accessed by the GPU. */
5024 mod_timer(&intel_crtc->idle_timer, jiffies +
5025 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5029 intel_crtc->busy = false;
5030 queue_work(dev_priv->wq, &dev_priv->idle_work);
5033 static void intel_increase_pllclock(struct drm_crtc *crtc)
5035 struct drm_device *dev = crtc->dev;
5036 drm_i915_private_t *dev_priv = dev->dev_private;
5037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038 int pipe = intel_crtc->pipe;
5039 int dpll_reg = DPLL(pipe);
5042 if (HAS_PCH_SPLIT(dev))
5045 if (!dev_priv->lvds_downclock_avail)
5048 dpll = I915_READ(dpll_reg);
5049 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5050 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5052 /* Unlock panel regs */
5053 I915_WRITE(PP_CONTROL,
5054 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5056 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5057 I915_WRITE(dpll_reg, dpll);
5058 POSTING_READ(dpll_reg);
5059 intel_wait_for_vblank(dev, pipe);
5061 dpll = I915_READ(dpll_reg);
5062 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5063 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5065 /* ...and lock them again */
5066 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5069 /* Schedule downclock */
5070 mod_timer(&intel_crtc->idle_timer, jiffies +
5071 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5074 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5076 struct drm_device *dev = crtc->dev;
5077 drm_i915_private_t *dev_priv = dev->dev_private;
5078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5079 int pipe = intel_crtc->pipe;
5080 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5081 int dpll = I915_READ(dpll_reg);
5083 if (HAS_PCH_SPLIT(dev))
5086 if (!dev_priv->lvds_downclock_avail)
5090 * Since this is called by a timer, we should never get here in
5093 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5094 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5096 /* Unlock panel regs */
5097 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5100 dpll |= DISPLAY_RATE_SELECT_FPA1;
5101 I915_WRITE(dpll_reg, dpll);
5102 dpll = I915_READ(dpll_reg);
5103 intel_wait_for_vblank(dev, pipe);
5104 dpll = I915_READ(dpll_reg);
5105 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5106 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5108 /* ...and lock them again */
5109 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5115 * intel_idle_update - adjust clocks for idleness
5116 * @work: work struct
5118 * Either the GPU or display (or both) went idle. Check the busy status
5119 * here and adjust the CRTC and GPU clocks as necessary.
5121 static void intel_idle_update(struct work_struct *work)
5123 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5125 struct drm_device *dev = dev_priv->dev;
5126 struct drm_crtc *crtc;
5127 struct intel_crtc *intel_crtc;
5130 if (!i915_powersave)
5133 mutex_lock(&dev->struct_mutex);
5135 i915_update_gfx_val(dev_priv);
5137 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5138 /* Skip inactive CRTCs */
5143 intel_crtc = to_intel_crtc(crtc);
5144 if (!intel_crtc->busy)
5145 intel_decrease_pllclock(crtc);
5148 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5149 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5150 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5153 mutex_unlock(&dev->struct_mutex);
5157 * intel_mark_busy - mark the GPU and possibly the display busy
5159 * @obj: object we're operating on
5161 * Callers can use this function to indicate that the GPU is busy processing
5162 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5163 * buffer), we'll also mark the display as busy, so we know to increase its
5166 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5168 drm_i915_private_t *dev_priv = dev->dev_private;
5169 struct drm_crtc *crtc = NULL;
5170 struct intel_framebuffer *intel_fb;
5171 struct intel_crtc *intel_crtc;
5173 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5176 if (!dev_priv->busy) {
5177 if (IS_I945G(dev) || IS_I945GM(dev)) {
5180 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5181 fw_blc_self = I915_READ(FW_BLC_SELF);
5182 fw_blc_self &= ~FW_BLC_SELF_EN;
5183 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5185 dev_priv->busy = true;
5187 mod_timer(&dev_priv->idle_timer, jiffies +
5188 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5194 intel_crtc = to_intel_crtc(crtc);
5195 intel_fb = to_intel_framebuffer(crtc->fb);
5196 if (intel_fb->obj == obj) {
5197 if (!intel_crtc->busy) {
5198 if (IS_I945G(dev) || IS_I945GM(dev)) {
5201 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5202 fw_blc_self = I915_READ(FW_BLC_SELF);
5203 fw_blc_self &= ~FW_BLC_SELF_EN;
5204 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5206 /* Non-busy -> busy, upclock */
5207 intel_increase_pllclock(crtc);
5208 intel_crtc->busy = true;
5210 /* Busy -> busy, put off timer */
5211 mod_timer(&intel_crtc->idle_timer, jiffies +
5212 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5218 static void intel_crtc_destroy(struct drm_crtc *crtc)
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221 struct drm_device *dev = crtc->dev;
5222 struct intel_unpin_work *work;
5223 unsigned long flags;
5225 spin_lock_irqsave(&dev->event_lock, flags);
5226 work = intel_crtc->unpin_work;
5227 intel_crtc->unpin_work = NULL;
5228 spin_unlock_irqrestore(&dev->event_lock, flags);
5231 cancel_work_sync(&work->work);
5235 drm_crtc_cleanup(crtc);
5240 static void intel_unpin_work_fn(struct work_struct *__work)
5242 struct intel_unpin_work *work =
5243 container_of(__work, struct intel_unpin_work, work);
5245 mutex_lock(&work->dev->struct_mutex);
5246 i915_gem_object_unpin(work->old_fb_obj);
5247 drm_gem_object_unreference(&work->pending_flip_obj->base);
5248 drm_gem_object_unreference(&work->old_fb_obj->base);
5250 mutex_unlock(&work->dev->struct_mutex);
5254 static void do_intel_finish_page_flip(struct drm_device *dev,
5255 struct drm_crtc *crtc)
5257 drm_i915_private_t *dev_priv = dev->dev_private;
5258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5259 struct intel_unpin_work *work;
5260 struct drm_i915_gem_object *obj;
5261 struct drm_pending_vblank_event *e;
5262 struct timeval tnow, tvbl;
5263 unsigned long flags;
5265 /* Ignore early vblank irqs */
5266 if (intel_crtc == NULL)
5269 do_gettimeofday(&tnow);
5271 spin_lock_irqsave(&dev->event_lock, flags);
5272 work = intel_crtc->unpin_work;
5273 if (work == NULL || !work->pending) {
5274 spin_unlock_irqrestore(&dev->event_lock, flags);
5278 intel_crtc->unpin_work = NULL;
5282 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5284 /* Called before vblank count and timestamps have
5285 * been updated for the vblank interval of flip
5286 * completion? Need to increment vblank count and
5287 * add one videorefresh duration to returned timestamp
5288 * to account for this. We assume this happened if we
5289 * get called over 0.9 frame durations after the last
5290 * timestamped vblank.
5292 * This calculation can not be used with vrefresh rates
5293 * below 5Hz (10Hz to be on the safe side) without
5294 * promoting to 64 integers.
5296 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5297 9 * crtc->framedur_ns) {
5298 e->event.sequence++;
5299 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5303 e->event.tv_sec = tvbl.tv_sec;
5304 e->event.tv_usec = tvbl.tv_usec;
5306 list_add_tail(&e->base.link,
5307 &e->base.file_priv->event_list);
5308 wake_up_interruptible(&e->base.file_priv->event_wait);
5311 drm_vblank_put(dev, intel_crtc->pipe);
5313 spin_unlock_irqrestore(&dev->event_lock, flags);
5315 obj = work->old_fb_obj;
5317 atomic_clear_mask(1 << intel_crtc->plane,
5318 &obj->pending_flip.counter);
5319 if (atomic_read(&obj->pending_flip) == 0)
5320 wake_up(&dev_priv->pending_flip_queue);
5322 schedule_work(&work->work);
5324 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5327 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5329 drm_i915_private_t *dev_priv = dev->dev_private;
5330 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5332 do_intel_finish_page_flip(dev, crtc);
5335 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5337 drm_i915_private_t *dev_priv = dev->dev_private;
5338 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5340 do_intel_finish_page_flip(dev, crtc);
5343 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5345 drm_i915_private_t *dev_priv = dev->dev_private;
5346 struct intel_crtc *intel_crtc =
5347 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5348 unsigned long flags;
5350 spin_lock_irqsave(&dev->event_lock, flags);
5351 if (intel_crtc->unpin_work) {
5352 if ((++intel_crtc->unpin_work->pending) > 1)
5353 DRM_ERROR("Prepared flip multiple times\n");
5355 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5357 spin_unlock_irqrestore(&dev->event_lock, flags);
5360 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5361 struct drm_framebuffer *fb,
5362 struct drm_pending_vblank_event *event)
5364 struct drm_device *dev = crtc->dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 struct intel_framebuffer *intel_fb;
5367 struct drm_i915_gem_object *obj;
5368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5369 struct intel_unpin_work *work;
5370 unsigned long flags, offset;
5371 int pipe = intel_crtc->pipe;
5375 work = kzalloc(sizeof *work, GFP_KERNEL);
5379 work->event = event;
5380 work->dev = crtc->dev;
5381 intel_fb = to_intel_framebuffer(crtc->fb);
5382 work->old_fb_obj = intel_fb->obj;
5383 INIT_WORK(&work->work, intel_unpin_work_fn);
5385 /* We borrow the event spin lock for protecting unpin_work */
5386 spin_lock_irqsave(&dev->event_lock, flags);
5387 if (intel_crtc->unpin_work) {
5388 spin_unlock_irqrestore(&dev->event_lock, flags);
5391 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5394 intel_crtc->unpin_work = work;
5395 spin_unlock_irqrestore(&dev->event_lock, flags);
5397 intel_fb = to_intel_framebuffer(fb);
5398 obj = intel_fb->obj;
5400 mutex_lock(&dev->struct_mutex);
5401 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5405 /* Reference the objects for the scheduled work. */
5406 drm_gem_object_reference(&work->old_fb_obj->base);
5407 drm_gem_object_reference(&obj->base);
5411 ret = drm_vblank_get(dev, intel_crtc->pipe);
5415 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5418 /* Can't queue multiple flips, so wait for the previous
5419 * one to finish before executing the next.
5421 ret = BEGIN_LP_RING(2);
5425 if (intel_crtc->plane)
5426 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5428 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5429 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5434 work->pending_flip_obj = obj;
5436 work->enable_stall_check = true;
5438 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5439 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5441 ret = BEGIN_LP_RING(4);
5445 /* Block clients from rendering to the new back buffer until
5446 * the flip occurs and the object is no longer visible.
5448 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5450 switch (INTEL_INFO(dev)->gen) {
5452 OUT_RING(MI_DISPLAY_FLIP |
5453 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5454 OUT_RING(fb->pitch);
5455 OUT_RING(obj->gtt_offset + offset);
5460 OUT_RING(MI_DISPLAY_FLIP_I915 |
5461 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5462 OUT_RING(fb->pitch);
5463 OUT_RING(obj->gtt_offset + offset);
5469 /* i965+ uses the linear or tiled offsets from the
5470 * Display Registers (which do not change across a page-flip)
5471 * so we need only reprogram the base address.
5473 OUT_RING(MI_DISPLAY_FLIP |
5474 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5475 OUT_RING(fb->pitch);
5476 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5478 /* XXX Enabling the panel-fitter across page-flip is so far
5479 * untested on non-native modes, so ignore it for now.
5480 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5483 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5484 OUT_RING(pf | pipesrc);
5488 OUT_RING(MI_DISPLAY_FLIP |
5489 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5490 OUT_RING(fb->pitch | obj->tiling_mode);
5491 OUT_RING(obj->gtt_offset);
5493 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5494 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5495 OUT_RING(pf | pipesrc);
5500 mutex_unlock(&dev->struct_mutex);
5502 trace_i915_flip_request(intel_crtc->plane, obj);
5507 drm_gem_object_unreference(&work->old_fb_obj->base);
5508 drm_gem_object_unreference(&obj->base);
5510 mutex_unlock(&dev->struct_mutex);
5512 spin_lock_irqsave(&dev->event_lock, flags);
5513 intel_crtc->unpin_work = NULL;
5514 spin_unlock_irqrestore(&dev->event_lock, flags);
5521 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5522 .dpms = intel_crtc_dpms,
5523 .mode_fixup = intel_crtc_mode_fixup,
5524 .mode_set = intel_crtc_mode_set,
5525 .mode_set_base = intel_pipe_set_base,
5526 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5527 .load_lut = intel_crtc_load_lut,
5528 .disable = intel_crtc_disable,
5531 static const struct drm_crtc_funcs intel_crtc_funcs = {
5532 .cursor_set = intel_crtc_cursor_set,
5533 .cursor_move = intel_crtc_cursor_move,
5534 .gamma_set = intel_crtc_gamma_set,
5535 .set_config = drm_crtc_helper_set_config,
5536 .destroy = intel_crtc_destroy,
5537 .page_flip = intel_crtc_page_flip,
5540 static void intel_sanitize_modesetting(struct drm_device *dev,
5541 int pipe, int plane)
5543 struct drm_i915_private *dev_priv = dev->dev_private;
5546 if (HAS_PCH_SPLIT(dev))
5549 /* Who knows what state these registers were left in by the BIOS or
5552 * If we leave the registers in a conflicting state (e.g. with the
5553 * display plane reading from the other pipe than the one we intend
5554 * to use) then when we attempt to teardown the active mode, we will
5555 * not disable the pipes and planes in the correct order -- leaving
5556 * a plane reading from a disabled pipe and possibly leading to
5557 * undefined behaviour.
5560 reg = DSPCNTR(plane);
5561 val = I915_READ(reg);
5563 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5565 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5568 /* This display plane is active and attached to the other CPU pipe. */
5571 /* Disable the plane and wait for it to stop reading from the pipe. */
5572 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5573 intel_flush_display_plane(dev, plane);
5576 intel_wait_for_vblank(dev, pipe);
5578 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5581 /* Switch off the pipe. */
5582 reg = PIPECONF(pipe);
5583 val = I915_READ(reg);
5584 if (val & PIPECONF_ENABLE) {
5585 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5586 intel_wait_for_pipe_off(dev, pipe);
5590 static void intel_crtc_init(struct drm_device *dev, int pipe)
5592 drm_i915_private_t *dev_priv = dev->dev_private;
5593 struct intel_crtc *intel_crtc;
5596 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5597 if (intel_crtc == NULL)
5600 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5602 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5603 for (i = 0; i < 256; i++) {
5604 intel_crtc->lut_r[i] = i;
5605 intel_crtc->lut_g[i] = i;
5606 intel_crtc->lut_b[i] = i;
5609 /* Swap pipes & planes for FBC on pre-965 */
5610 intel_crtc->pipe = pipe;
5611 intel_crtc->plane = pipe;
5612 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5613 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5614 intel_crtc->plane = !pipe;
5617 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5618 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5619 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5620 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5622 intel_crtc->cursor_addr = 0;
5623 intel_crtc->dpms_mode = -1;
5624 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5626 if (HAS_PCH_SPLIT(dev)) {
5627 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5628 intel_helper_funcs.commit = ironlake_crtc_commit;
5630 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5631 intel_helper_funcs.commit = i9xx_crtc_commit;
5634 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5636 intel_crtc->busy = false;
5638 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5639 (unsigned long)intel_crtc);
5641 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5644 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5645 struct drm_file *file)
5647 drm_i915_private_t *dev_priv = dev->dev_private;
5648 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5649 struct drm_mode_object *drmmode_obj;
5650 struct intel_crtc *crtc;
5653 DRM_ERROR("called with no initialization\n");
5657 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5658 DRM_MODE_OBJECT_CRTC);
5661 DRM_ERROR("no such CRTC id\n");
5665 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5666 pipe_from_crtc_id->pipe = crtc->pipe;
5671 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5673 struct intel_encoder *encoder;
5677 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5678 if (type_mask & encoder->clone_mask)
5679 index_mask |= (1 << entry);
5686 static bool has_edp_a(struct drm_device *dev)
5688 struct drm_i915_private *dev_priv = dev->dev_private;
5690 if (!IS_MOBILE(dev))
5693 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5697 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5703 static void intel_setup_outputs(struct drm_device *dev)
5705 struct drm_i915_private *dev_priv = dev->dev_private;
5706 struct intel_encoder *encoder;
5707 bool dpd_is_edp = false;
5708 bool has_lvds = false;
5710 if (IS_MOBILE(dev) && !IS_I830(dev))
5711 has_lvds = intel_lvds_init(dev);
5712 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5713 /* disable the panel fitter on everything but LVDS */
5714 I915_WRITE(PFIT_CONTROL, 0);
5717 if (HAS_PCH_SPLIT(dev)) {
5718 dpd_is_edp = intel_dpd_is_edp(dev);
5721 intel_dp_init(dev, DP_A);
5723 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5724 intel_dp_init(dev, PCH_DP_D);
5727 intel_crt_init(dev);
5729 if (HAS_PCH_SPLIT(dev)) {
5732 if (I915_READ(HDMIB) & PORT_DETECTED) {
5733 /* PCH SDVOB multiplex with HDMIB */
5734 found = intel_sdvo_init(dev, PCH_SDVOB);
5736 intel_hdmi_init(dev, HDMIB);
5737 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5738 intel_dp_init(dev, PCH_DP_B);
5741 if (I915_READ(HDMIC) & PORT_DETECTED)
5742 intel_hdmi_init(dev, HDMIC);
5744 if (I915_READ(HDMID) & PORT_DETECTED)
5745 intel_hdmi_init(dev, HDMID);
5747 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5748 intel_dp_init(dev, PCH_DP_C);
5750 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5751 intel_dp_init(dev, PCH_DP_D);
5753 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5756 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5757 DRM_DEBUG_KMS("probing SDVOB\n");
5758 found = intel_sdvo_init(dev, SDVOB);
5759 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5760 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5761 intel_hdmi_init(dev, SDVOB);
5764 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5765 DRM_DEBUG_KMS("probing DP_B\n");
5766 intel_dp_init(dev, DP_B);
5770 /* Before G4X SDVOC doesn't have its own detect register */
5772 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5773 DRM_DEBUG_KMS("probing SDVOC\n");
5774 found = intel_sdvo_init(dev, SDVOC);
5777 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5779 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5780 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5781 intel_hdmi_init(dev, SDVOC);
5783 if (SUPPORTS_INTEGRATED_DP(dev)) {
5784 DRM_DEBUG_KMS("probing DP_C\n");
5785 intel_dp_init(dev, DP_C);
5789 if (SUPPORTS_INTEGRATED_DP(dev) &&
5790 (I915_READ(DP_D) & DP_DETECTED)) {
5791 DRM_DEBUG_KMS("probing DP_D\n");
5792 intel_dp_init(dev, DP_D);
5794 } else if (IS_GEN2(dev))
5795 intel_dvo_init(dev);
5797 if (SUPPORTS_TV(dev))
5800 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5801 encoder->base.possible_crtcs = encoder->crtc_mask;
5802 encoder->base.possible_clones =
5803 intel_encoder_clones(dev, encoder->clone_mask);
5806 intel_panel_setup_backlight(dev);
5809 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5811 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5813 drm_framebuffer_cleanup(fb);
5814 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5819 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5820 struct drm_file *file,
5821 unsigned int *handle)
5823 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5824 struct drm_i915_gem_object *obj = intel_fb->obj;
5826 return drm_gem_handle_create(file, &obj->base, handle);
5829 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5830 .destroy = intel_user_framebuffer_destroy,
5831 .create_handle = intel_user_framebuffer_create_handle,
5834 int intel_framebuffer_init(struct drm_device *dev,
5835 struct intel_framebuffer *intel_fb,
5836 struct drm_mode_fb_cmd *mode_cmd,
5837 struct drm_i915_gem_object *obj)
5841 if (obj->tiling_mode == I915_TILING_Y)
5844 if (mode_cmd->pitch & 63)
5847 switch (mode_cmd->bpp) {
5857 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5859 DRM_ERROR("framebuffer init failed %d\n", ret);
5863 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5864 intel_fb->obj = obj;
5868 static struct drm_framebuffer *
5869 intel_user_framebuffer_create(struct drm_device *dev,
5870 struct drm_file *filp,
5871 struct drm_mode_fb_cmd *mode_cmd)
5873 struct drm_i915_gem_object *obj;
5874 struct intel_framebuffer *intel_fb;
5877 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
5879 return ERR_PTR(-ENOENT);
5881 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5883 return ERR_PTR(-ENOMEM);
5885 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5887 drm_gem_object_unreference_unlocked(&obj->base);
5889 return ERR_PTR(ret);
5892 return &intel_fb->base;
5895 static const struct drm_mode_config_funcs intel_mode_funcs = {
5896 .fb_create = intel_user_framebuffer_create,
5897 .output_poll_changed = intel_fb_output_poll_changed,
5900 static struct drm_i915_gem_object *
5901 intel_alloc_context_page(struct drm_device *dev)
5903 struct drm_i915_gem_object *ctx;
5906 ctx = i915_gem_alloc_object(dev, 4096);
5908 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5912 mutex_lock(&dev->struct_mutex);
5913 ret = i915_gem_object_pin(ctx, 4096, true);
5915 DRM_ERROR("failed to pin power context: %d\n", ret);
5919 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5921 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5924 mutex_unlock(&dev->struct_mutex);
5929 i915_gem_object_unpin(ctx);
5931 drm_gem_object_unreference(&ctx->base);
5932 mutex_unlock(&dev->struct_mutex);
5936 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5941 rgvswctl = I915_READ16(MEMSWCTL);
5942 if (rgvswctl & MEMCTL_CMD_STS) {
5943 DRM_DEBUG("gpu busy, RCS change rejected\n");
5944 return false; /* still busy with another command */
5947 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5948 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5949 I915_WRITE16(MEMSWCTL, rgvswctl);
5950 POSTING_READ16(MEMSWCTL);
5952 rgvswctl |= MEMCTL_CMD_STS;
5953 I915_WRITE16(MEMSWCTL, rgvswctl);
5958 void ironlake_enable_drps(struct drm_device *dev)
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961 u32 rgvmodectl = I915_READ(MEMMODECTL);
5962 u8 fmax, fmin, fstart, vstart;
5964 /* Enable temp reporting */
5965 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5966 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5968 /* 100ms RC evaluation intervals */
5969 I915_WRITE(RCUPEI, 100000);
5970 I915_WRITE(RCDNEI, 100000);
5972 /* Set max/min thresholds to 90ms and 80ms respectively */
5973 I915_WRITE(RCBMAXAVG, 90000);
5974 I915_WRITE(RCBMINAVG, 80000);
5976 I915_WRITE(MEMIHYST, 1);
5978 /* Set up min, max, and cur for interrupt handling */
5979 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5980 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5981 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5982 MEMMODE_FSTART_SHIFT;
5984 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5987 dev_priv->fmax = fmax; /* IPS callback will increase this */
5988 dev_priv->fstart = fstart;
5990 dev_priv->max_delay = fstart;
5991 dev_priv->min_delay = fmin;
5992 dev_priv->cur_delay = fstart;
5994 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5995 fmax, fmin, fstart);
5997 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6000 * Interrupts will be enabled in ironlake_irq_postinstall
6003 I915_WRITE(VIDSTART, vstart);
6004 POSTING_READ(VIDSTART);
6006 rgvmodectl |= MEMMODE_SWMODE_EN;
6007 I915_WRITE(MEMMODECTL, rgvmodectl);
6009 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6010 DRM_ERROR("stuck trying to change perf mode\n");
6013 ironlake_set_drps(dev, fstart);
6015 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6017 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6018 dev_priv->last_count2 = I915_READ(0x112f4);
6019 getrawmonotonic(&dev_priv->last_time2);
6022 void ironlake_disable_drps(struct drm_device *dev)
6024 struct drm_i915_private *dev_priv = dev->dev_private;
6025 u16 rgvswctl = I915_READ16(MEMSWCTL);
6027 /* Ack interrupts, disable EFC interrupt */
6028 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6029 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6030 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6031 I915_WRITE(DEIIR, DE_PCU_EVENT);
6032 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6034 /* Go back to the starting frequency */
6035 ironlake_set_drps(dev, dev_priv->fstart);
6037 rgvswctl |= MEMCTL_CMD_STS;
6038 I915_WRITE(MEMSWCTL, rgvswctl);
6043 void gen6_set_rps(struct drm_device *dev, u8 val)
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6048 swreq = (val & 0x3ff) << 25;
6049 I915_WRITE(GEN6_RPNSWREQ, swreq);
6052 void gen6_disable_rps(struct drm_device *dev)
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6056 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6057 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6058 I915_WRITE(GEN6_PMIER, 0);
6059 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6062 static unsigned long intel_pxfreq(u32 vidfreq)
6065 int div = (vidfreq & 0x3f0000) >> 16;
6066 int post = (vidfreq & 0x3000) >> 12;
6067 int pre = (vidfreq & 0x7);
6072 freq = ((div * 133333) / ((1<<post) * pre));
6077 void intel_init_emon(struct drm_device *dev)
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6084 /* Disable to program */
6088 /* Program energy weights for various events */
6089 I915_WRITE(SDEW, 0x15040d00);
6090 I915_WRITE(CSIEW0, 0x007f0000);
6091 I915_WRITE(CSIEW1, 0x1e220004);
6092 I915_WRITE(CSIEW2, 0x04000004);
6094 for (i = 0; i < 5; i++)
6095 I915_WRITE(PEW + (i * 4), 0);
6096 for (i = 0; i < 3; i++)
6097 I915_WRITE(DEW + (i * 4), 0);
6099 /* Program P-state weights to account for frequency power adjustment */
6100 for (i = 0; i < 16; i++) {
6101 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6102 unsigned long freq = intel_pxfreq(pxvidfreq);
6103 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6108 val *= (freq / 1000);
6110 val /= (127*127*900);
6112 DRM_ERROR("bad pxval: %ld\n", val);
6115 /* Render standby states get 0 weight */
6119 for (i = 0; i < 4; i++) {
6120 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6121 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6122 I915_WRITE(PXW + (i * 4), val);
6125 /* Adjust magic regs to magic values (more experimental results) */
6126 I915_WRITE(OGW0, 0);
6127 I915_WRITE(OGW1, 0);
6128 I915_WRITE(EG0, 0x00007f00);
6129 I915_WRITE(EG1, 0x0000000e);
6130 I915_WRITE(EG2, 0x000e0000);
6131 I915_WRITE(EG3, 0x68000300);
6132 I915_WRITE(EG4, 0x42000000);
6133 I915_WRITE(EG5, 0x00140031);
6137 for (i = 0; i < 8; i++)
6138 I915_WRITE(PXWL + (i * 4), 0);
6140 /* Enable PMON + select events */
6141 I915_WRITE(ECR, 0x80000019);
6143 lcfuse = I915_READ(LCFUSE02);
6145 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6148 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6150 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6151 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6153 int cur_freq, min_freq, max_freq;
6156 /* Here begins a magic sequence of register writes to enable
6157 * auto-downclocking.
6159 * Perhaps there might be some value in exposing these to
6162 I915_WRITE(GEN6_RC_STATE, 0);
6163 __gen6_force_wake_get(dev_priv);
6165 /* disable the counters and set deterministic thresholds */
6166 I915_WRITE(GEN6_RC_CONTROL, 0);
6168 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6169 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6170 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6171 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6172 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6174 for (i = 0; i < I915_NUM_RINGS; i++)
6175 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6177 I915_WRITE(GEN6_RC_SLEEP, 0);
6178 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6179 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6180 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6181 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6183 I915_WRITE(GEN6_RC_CONTROL,
6184 GEN6_RC_CTL_RC6p_ENABLE |
6185 GEN6_RC_CTL_RC6_ENABLE |
6186 GEN6_RC_CTL_EI_MODE(1) |
6187 GEN6_RC_CTL_HW_ENABLE);
6189 I915_WRITE(GEN6_RPNSWREQ,
6190 GEN6_FREQUENCY(10) |
6192 GEN6_AGGRESSIVE_TURBO);
6193 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6194 GEN6_FREQUENCY(12));
6196 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6197 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6200 I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6201 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6202 I915_WRITE(GEN6_RP_UP_EI, 100000);
6203 I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6204 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6205 I915_WRITE(GEN6_RP_CONTROL,
6206 GEN6_RP_MEDIA_TURBO |
6207 GEN6_RP_USE_NORMAL_FREQ |
6208 GEN6_RP_MEDIA_IS_GFX |
6210 GEN6_RP_UP_BUSY_MAX |
6211 GEN6_RP_DOWN_BUSY_MIN);
6213 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6215 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6217 I915_WRITE(GEN6_PCODE_DATA, 0);
6218 I915_WRITE(GEN6_PCODE_MAILBOX,
6220 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6221 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6223 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6225 min_freq = (rp_state_cap & 0xff0000) >> 16;
6226 max_freq = rp_state_cap & 0xff;
6227 cur_freq = (gt_perf_status & 0xff00) >> 8;
6229 /* Check for overclock support */
6230 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6232 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6233 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6234 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6235 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6237 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6238 if (pcu_mbox & (1<<31)) { /* OC supported */
6239 max_freq = pcu_mbox & 0xff;
6240 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6243 /* In units of 100MHz */
6244 dev_priv->max_delay = max_freq;
6245 dev_priv->min_delay = min_freq;
6246 dev_priv->cur_delay = cur_freq;
6248 /* requires MSI enabled */
6249 I915_WRITE(GEN6_PMIER,
6250 GEN6_PM_MBOX_EVENT |
6251 GEN6_PM_THERMAL_EVENT |
6252 GEN6_PM_RP_DOWN_TIMEOUT |
6253 GEN6_PM_RP_UP_THRESHOLD |
6254 GEN6_PM_RP_DOWN_THRESHOLD |
6255 GEN6_PM_RP_UP_EI_EXPIRED |
6256 GEN6_PM_RP_DOWN_EI_EXPIRED);
6257 I915_WRITE(GEN6_PMIMR, 0);
6258 /* enable all PM interrupts */
6259 I915_WRITE(GEN6_PMINTRMSK, 0);
6261 __gen6_force_wake_put(dev_priv);
6264 void intel_enable_clock_gating(struct drm_device *dev)
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6269 * Disable clock gating reported to work incorrectly according to the
6270 * specs, but enable as much else as we can.
6272 if (HAS_PCH_SPLIT(dev)) {
6273 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6276 /* Required for FBC */
6277 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
6278 /* Required for CxSR */
6279 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6281 I915_WRITE(PCH_3DCGDIS0,
6282 MARIUNIT_CLOCK_GATE_DISABLE |
6283 SVSMUNIT_CLOCK_GATE_DISABLE);
6284 I915_WRITE(PCH_3DCGDIS1,
6285 VFMUNIT_CLOCK_GATE_DISABLE);
6288 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6291 * On Ibex Peak and Cougar Point, we need to disable clock
6292 * gating for the panel power sequencer or it will fail to
6293 * start up when no ports are active.
6295 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6298 * According to the spec the following bits should be set in
6299 * order to enable memory self-refresh
6300 * The bit 22/21 of 0x42004
6301 * The bit 5 of 0x42020
6302 * The bit 15 of 0x45000
6305 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6306 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6307 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6308 I915_WRITE(ILK_DSPCLK_GATE,
6309 (I915_READ(ILK_DSPCLK_GATE) |
6310 ILK_DPARB_CLK_GATE));
6311 I915_WRITE(DISP_ARB_CTL,
6312 (I915_READ(DISP_ARB_CTL) |
6314 I915_WRITE(WM3_LP_ILK, 0);
6315 I915_WRITE(WM2_LP_ILK, 0);
6316 I915_WRITE(WM1_LP_ILK, 0);
6319 * Based on the document from hardware guys the following bits
6320 * should be set unconditionally in order to enable FBC.
6321 * The bit 22 of 0x42000
6322 * The bit 22 of 0x42004
6323 * The bit 7,8,9 of 0x42020.
6325 if (IS_IRONLAKE_M(dev)) {
6326 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6327 I915_READ(ILK_DISPLAY_CHICKEN1) |
6329 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6330 I915_READ(ILK_DISPLAY_CHICKEN2) |
6332 I915_WRITE(ILK_DSPCLK_GATE,
6333 I915_READ(ILK_DSPCLK_GATE) |
6339 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6340 I915_READ(ILK_DISPLAY_CHICKEN2) |
6341 ILK_ELPIN_409_SELECT);
6344 I915_WRITE(_3D_CHICKEN2,
6345 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6346 _3D_CHICKEN2_WM_READ_PIPELINED);
6350 I915_WRITE(WM3_LP_ILK, 0);
6351 I915_WRITE(WM2_LP_ILK, 0);
6352 I915_WRITE(WM1_LP_ILK, 0);
6355 * According to the spec the following bits should be
6356 * set in order to enable memory self-refresh and fbc:
6357 * The bit21 and bit22 of 0x42000
6358 * The bit21 and bit22 of 0x42004
6359 * The bit5 and bit7 of 0x42020
6360 * The bit14 of 0x70180
6361 * The bit14 of 0x71180
6363 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6364 I915_READ(ILK_DISPLAY_CHICKEN1) |
6365 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6366 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6367 I915_READ(ILK_DISPLAY_CHICKEN2) |
6368 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6369 I915_WRITE(ILK_DSPCLK_GATE,
6370 I915_READ(ILK_DSPCLK_GATE) |
6371 ILK_DPARB_CLK_GATE |
6374 I915_WRITE(DSPACNTR,
6375 I915_READ(DSPACNTR) |
6376 DISPPLANE_TRICKLE_FEED_DISABLE);
6377 I915_WRITE(DSPBCNTR,
6378 I915_READ(DSPBCNTR) |
6379 DISPPLANE_TRICKLE_FEED_DISABLE);
6381 } else if (IS_G4X(dev)) {
6382 uint32_t dspclk_gate;
6383 I915_WRITE(RENCLK_GATE_D1, 0);
6384 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6385 GS_UNIT_CLOCK_GATE_DISABLE |
6386 CL_UNIT_CLOCK_GATE_DISABLE);
6387 I915_WRITE(RAMCLK_GATE_D, 0);
6388 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6389 OVRUNIT_CLOCK_GATE_DISABLE |
6390 OVCUNIT_CLOCK_GATE_DISABLE;
6392 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6393 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6394 } else if (IS_CRESTLINE(dev)) {
6395 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6396 I915_WRITE(RENCLK_GATE_D2, 0);
6397 I915_WRITE(DSPCLK_GATE_D, 0);
6398 I915_WRITE(RAMCLK_GATE_D, 0);
6399 I915_WRITE16(DEUC, 0);
6400 } else if (IS_BROADWATER(dev)) {
6401 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6402 I965_RCC_CLOCK_GATE_DISABLE |
6403 I965_RCPB_CLOCK_GATE_DISABLE |
6404 I965_ISC_CLOCK_GATE_DISABLE |
6405 I965_FBC_CLOCK_GATE_DISABLE);
6406 I915_WRITE(RENCLK_GATE_D2, 0);
6407 } else if (IS_GEN3(dev)) {
6408 u32 dstate = I915_READ(D_STATE);
6410 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6411 DSTATE_DOT_CLOCK_GATING;
6412 I915_WRITE(D_STATE, dstate);
6413 } else if (IS_I85X(dev) || IS_I865G(dev)) {
6414 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6415 } else if (IS_I830(dev)) {
6416 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6420 void intel_disable_clock_gating(struct drm_device *dev)
6422 struct drm_i915_private *dev_priv = dev->dev_private;
6424 if (dev_priv->renderctx) {
6425 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6427 I915_WRITE(CCID, 0);
6430 i915_gem_object_unpin(obj);
6431 drm_gem_object_unreference(&obj->base);
6432 dev_priv->renderctx = NULL;
6435 if (dev_priv->pwrctx) {
6436 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6438 I915_WRITE(PWRCTXA, 0);
6439 POSTING_READ(PWRCTXA);
6441 i915_gem_object_unpin(obj);
6442 drm_gem_object_unreference(&obj->base);
6443 dev_priv->pwrctx = NULL;
6447 static void ironlake_disable_rc6(struct drm_device *dev)
6449 struct drm_i915_private *dev_priv = dev->dev_private;
6451 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6452 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6453 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6456 I915_WRITE(PWRCTXA, 0);
6457 POSTING_READ(PWRCTXA);
6458 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6459 POSTING_READ(RSTDBYCTL);
6460 i915_gem_object_unpin(dev_priv->renderctx);
6461 drm_gem_object_unreference(&dev_priv->renderctx->base);
6462 dev_priv->renderctx = NULL;
6463 i915_gem_object_unpin(dev_priv->pwrctx);
6464 drm_gem_object_unreference(&dev_priv->pwrctx->base);
6465 dev_priv->pwrctx = NULL;
6468 void ironlake_enable_rc6(struct drm_device *dev)
6470 struct drm_i915_private *dev_priv = dev->dev_private;
6474 * GPU can automatically power down the render unit if given a page
6477 ret = BEGIN_LP_RING(6);
6479 ironlake_disable_rc6(dev);
6482 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6483 OUT_RING(MI_SET_CONTEXT);
6484 OUT_RING(dev_priv->renderctx->gtt_offset |
6486 MI_SAVE_EXT_STATE_EN |
6487 MI_RESTORE_EXT_STATE_EN |
6488 MI_RESTORE_INHIBIT);
6489 OUT_RING(MI_SUSPEND_FLUSH);
6494 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6495 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6498 /* Set up chip specific display functions */
6499 static void intel_init_display(struct drm_device *dev)
6501 struct drm_i915_private *dev_priv = dev->dev_private;
6503 /* We always want a DPMS function */
6504 if (HAS_PCH_SPLIT(dev))
6505 dev_priv->display.dpms = ironlake_crtc_dpms;
6507 dev_priv->display.dpms = i9xx_crtc_dpms;
6509 if (I915_HAS_FBC(dev)) {
6510 if (HAS_PCH_SPLIT(dev)) {
6511 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6512 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6513 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6514 } else if (IS_GM45(dev)) {
6515 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6516 dev_priv->display.enable_fbc = g4x_enable_fbc;
6517 dev_priv->display.disable_fbc = g4x_disable_fbc;
6518 } else if (IS_CRESTLINE(dev)) {
6519 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6520 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6521 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6523 /* 855GM needs testing */
6526 /* Returns the core display clock speed */
6527 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6528 dev_priv->display.get_display_clock_speed =
6529 i945_get_display_clock_speed;
6530 else if (IS_I915G(dev))
6531 dev_priv->display.get_display_clock_speed =
6532 i915_get_display_clock_speed;
6533 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6534 dev_priv->display.get_display_clock_speed =
6535 i9xx_misc_get_display_clock_speed;
6536 else if (IS_I915GM(dev))
6537 dev_priv->display.get_display_clock_speed =
6538 i915gm_get_display_clock_speed;
6539 else if (IS_I865G(dev))
6540 dev_priv->display.get_display_clock_speed =
6541 i865_get_display_clock_speed;
6542 else if (IS_I85X(dev))
6543 dev_priv->display.get_display_clock_speed =
6544 i855_get_display_clock_speed;
6546 dev_priv->display.get_display_clock_speed =
6547 i830_get_display_clock_speed;
6549 /* For FIFO watermark updates */
6550 if (HAS_PCH_SPLIT(dev)) {
6552 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6553 dev_priv->display.update_wm = ironlake_update_wm;
6555 DRM_DEBUG_KMS("Failed to get proper latency. "
6557 dev_priv->display.update_wm = NULL;
6559 } else if (IS_GEN6(dev)) {
6560 if (SNB_READ_WM0_LATENCY()) {
6561 dev_priv->display.update_wm = sandybridge_update_wm;
6563 DRM_DEBUG_KMS("Failed to read display plane latency. "
6565 dev_priv->display.update_wm = NULL;
6568 dev_priv->display.update_wm = NULL;
6569 } else if (IS_PINEVIEW(dev)) {
6570 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6573 dev_priv->mem_freq)) {
6574 DRM_INFO("failed to find known CxSR latency "
6575 "(found ddr%s fsb freq %d, mem freq %d), "
6577 (dev_priv->is_ddr3 == 1) ? "3": "2",
6578 dev_priv->fsb_freq, dev_priv->mem_freq);
6579 /* Disable CxSR and never update its watermark again */
6580 pineview_disable_cxsr(dev);
6581 dev_priv->display.update_wm = NULL;
6583 dev_priv->display.update_wm = pineview_update_wm;
6584 } else if (IS_G4X(dev))
6585 dev_priv->display.update_wm = g4x_update_wm;
6586 else if (IS_GEN4(dev))
6587 dev_priv->display.update_wm = i965_update_wm;
6588 else if (IS_GEN3(dev)) {
6589 dev_priv->display.update_wm = i9xx_update_wm;
6590 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6591 } else if (IS_I85X(dev)) {
6592 dev_priv->display.update_wm = i9xx_update_wm;
6593 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6595 dev_priv->display.update_wm = i830_update_wm;
6597 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6599 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6604 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6605 * resume, or other times. This quirk makes sure that's the case for
6608 static void quirk_pipea_force (struct drm_device *dev)
6610 struct drm_i915_private *dev_priv = dev->dev_private;
6612 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6613 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6616 struct intel_quirk {
6618 int subsystem_vendor;
6619 int subsystem_device;
6620 void (*hook)(struct drm_device *dev);
6623 struct intel_quirk intel_quirks[] = {
6624 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6625 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6626 /* HP Mini needs pipe A force quirk (LP: #322104) */
6627 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6629 /* Thinkpad R31 needs pipe A force quirk */
6630 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6631 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6632 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6634 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6635 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6636 /* ThinkPad X40 needs pipe A force quirk */
6638 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6639 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6641 /* 855 & before need to leave pipe A & dpll A up */
6642 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6643 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6646 static void intel_init_quirks(struct drm_device *dev)
6648 struct pci_dev *d = dev->pdev;
6651 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6652 struct intel_quirk *q = &intel_quirks[i];
6654 if (d->device == q->device &&
6655 (d->subsystem_vendor == q->subsystem_vendor ||
6656 q->subsystem_vendor == PCI_ANY_ID) &&
6657 (d->subsystem_device == q->subsystem_device ||
6658 q->subsystem_device == PCI_ANY_ID))
6663 /* Disable the VGA plane that we never use */
6664 static void i915_disable_vga(struct drm_device *dev)
6666 struct drm_i915_private *dev_priv = dev->dev_private;
6670 if (HAS_PCH_SPLIT(dev))
6671 vga_reg = CPU_VGACNTRL;
6675 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6676 outb(1, VGA_SR_INDEX);
6677 sr1 = inb(VGA_SR_DATA);
6678 outb(sr1 | 1<<5, VGA_SR_DATA);
6679 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6682 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6683 POSTING_READ(vga_reg);
6686 void intel_modeset_init(struct drm_device *dev)
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6691 drm_mode_config_init(dev);
6693 dev->mode_config.min_width = 0;
6694 dev->mode_config.min_height = 0;
6696 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6698 intel_init_quirks(dev);
6700 intel_init_display(dev);
6703 dev->mode_config.max_width = 2048;
6704 dev->mode_config.max_height = 2048;
6705 } else if (IS_GEN3(dev)) {
6706 dev->mode_config.max_width = 4096;
6707 dev->mode_config.max_height = 4096;
6709 dev->mode_config.max_width = 8192;
6710 dev->mode_config.max_height = 8192;
6712 dev->mode_config.fb_base = dev->agp->base;
6714 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6715 dev_priv->num_pipe = 2;
6717 dev_priv->num_pipe = 1;
6718 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6719 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6721 for (i = 0; i < dev_priv->num_pipe; i++) {
6722 intel_crtc_init(dev, i);
6725 intel_setup_outputs(dev);
6727 intel_enable_clock_gating(dev);
6729 /* Just disable it once at startup */
6730 i915_disable_vga(dev);
6732 if (IS_IRONLAKE_M(dev)) {
6733 ironlake_enable_drps(dev);
6734 intel_init_emon(dev);
6738 gen6_enable_rps(dev_priv);
6740 if (IS_IRONLAKE_M(dev)) {
6741 dev_priv->renderctx = intel_alloc_context_page(dev);
6742 if (!dev_priv->renderctx)
6744 dev_priv->pwrctx = intel_alloc_context_page(dev);
6745 if (!dev_priv->pwrctx) {
6746 i915_gem_object_unpin(dev_priv->renderctx);
6747 drm_gem_object_unreference(&dev_priv->renderctx->base);
6748 dev_priv->renderctx = NULL;
6751 ironlake_enable_rc6(dev);
6755 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6756 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6757 (unsigned long)dev);
6759 intel_setup_overlay(dev);
6762 void intel_modeset_cleanup(struct drm_device *dev)
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 struct drm_crtc *crtc;
6766 struct intel_crtc *intel_crtc;
6768 drm_kms_helper_poll_fini(dev);
6769 mutex_lock(&dev->struct_mutex);
6771 intel_unregister_dsm_handler();
6774 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6775 /* Skip inactive CRTCs */
6779 intel_crtc = to_intel_crtc(crtc);
6780 intel_increase_pllclock(crtc);
6783 if (dev_priv->display.disable_fbc)
6784 dev_priv->display.disable_fbc(dev);
6786 if (IS_IRONLAKE_M(dev))
6787 ironlake_disable_drps(dev);
6789 gen6_disable_rps(dev);
6791 if (IS_IRONLAKE_M(dev))
6792 ironlake_disable_rc6(dev);
6794 mutex_unlock(&dev->struct_mutex);
6796 /* Disable the irq before mode object teardown, for the irq might
6797 * enqueue unpin/hotplug work. */
6798 drm_irq_uninstall(dev);
6799 cancel_work_sync(&dev_priv->hotplug_work);
6801 /* Shut off idle work before the crtcs get freed. */
6802 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6803 intel_crtc = to_intel_crtc(crtc);
6804 del_timer_sync(&intel_crtc->idle_timer);
6806 del_timer_sync(&dev_priv->idle_timer);
6807 cancel_work_sync(&dev_priv->idle_work);
6809 drm_mode_config_cleanup(dev);
6813 * Return which encoder is currently attached for connector.
6815 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6817 return &intel_attached_encoder(connector)->base;
6820 void intel_connector_attach_encoder(struct intel_connector *connector,
6821 struct intel_encoder *encoder)
6823 connector->encoder = encoder;
6824 drm_mode_connector_attach_encoder(&connector->base,
6829 * set vga decode state - true == enable VGA decode
6831 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6836 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6838 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6840 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6841 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6845 #ifdef CONFIG_DEBUG_FS
6846 #include <linux/seq_file.h>
6848 struct intel_display_error_state {
6849 struct intel_cursor_error_state {
6856 struct intel_pipe_error_state {
6868 struct intel_plane_error_state {
6879 struct intel_display_error_state *
6880 intel_display_capture_error_state(struct drm_device *dev)
6882 drm_i915_private_t *dev_priv = dev->dev_private;
6883 struct intel_display_error_state *error;
6886 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6890 for (i = 0; i < 2; i++) {
6891 error->cursor[i].control = I915_READ(CURCNTR(i));
6892 error->cursor[i].position = I915_READ(CURPOS(i));
6893 error->cursor[i].base = I915_READ(CURBASE(i));
6895 error->plane[i].control = I915_READ(DSPCNTR(i));
6896 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6897 error->plane[i].size = I915_READ(DSPSIZE(i));
6898 error->plane[i].pos= I915_READ(DSPPOS(i));
6899 error->plane[i].addr = I915_READ(DSPADDR(i));
6900 if (INTEL_INFO(dev)->gen >= 4) {
6901 error->plane[i].surface = I915_READ(DSPSURF(i));
6902 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6905 error->pipe[i].conf = I915_READ(PIPECONF(i));
6906 error->pipe[i].source = I915_READ(PIPESRC(i));
6907 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6908 error->pipe[i].hblank = I915_READ(HBLANK(i));
6909 error->pipe[i].hsync = I915_READ(HSYNC(i));
6910 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6911 error->pipe[i].vblank = I915_READ(VBLANK(i));
6912 error->pipe[i].vsync = I915_READ(VSYNC(i));
6919 intel_display_print_error_state(struct seq_file *m,
6920 struct drm_device *dev,
6921 struct intel_display_error_state *error)
6925 for (i = 0; i < 2; i++) {
6926 seq_printf(m, "Pipe [%d]:\n", i);
6927 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6928 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6929 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6930 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6931 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6932 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6933 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6934 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6936 seq_printf(m, "Plane [%d]:\n", i);
6937 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6938 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6939 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6940 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6941 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6942 if (INTEL_INFO(dev)->gen >= 4) {
6943 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6944 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6947 seq_printf(m, "Cursor [%d]:\n", i);
6948 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6949 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6950 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);