arch/x86/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/genapic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 static int __init parse_noapic(char *str)
 102 {
 103         /* disable IO-APIC */
 104         disable_ioapic_setup();
 105         return 0;
 106 }
 107 early_param("noapic", parse_noapic);
 108
 109 struct irq_pin_list;
 110
 111 /*
 112  * This is performance-critical, we want to do it O(1)
 113  *
 114  * the indexing order of this array favors 1:1 mappings
 115  * between pins and IRQs.
 116  */
 117
 118 struct irq_pin_list {
 119         int apic, pin;
 120         struct irq_pin_list *next;
 121 };
 122
 123 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 124 {
 125         struct irq_pin_list *pin;
 126         int node;
 127
 128         node = cpu_to_node(cpu);
 129
 130         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 131
 132         return pin;
 133 }
 134
 135 struct irq_cfg {
 136         struct irq_pin_list *irq_2_pin;
 137         cpumask_var_t domain;
 138         cpumask_var_t old_domain;
 139         unsigned move_cleanup_count;
 140         u8 vector;
 141         u8 move_in_progress : 1;
 142 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 143         u8 move_desc_pending : 1;
 144 #endif
 145 };
 146
 147 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 148 #ifdef CONFIG_SPARSE_IRQ
 149 static struct irq_cfg irq_cfgx[] = {
 150 #else
 151 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 152 #endif
 153         [0]  = { .vector = IRQ0_VECTOR,  },
 154         [1]  = { .vector = IRQ1_VECTOR,  },
 155         [2]  = { .vector = IRQ2_VECTOR,  },
 156         [3]  = { .vector = IRQ3_VECTOR,  },
 157         [4]  = { .vector = IRQ4_VECTOR,  },
 158         [5]  = { .vector = IRQ5_VECTOR,  },
 159         [6]  = { .vector = IRQ6_VECTOR,  },
 160         [7]  = { .vector = IRQ7_VECTOR,  },
 161         [8]  = { .vector = IRQ8_VECTOR,  },
 162         [9]  = { .vector = IRQ9_VECTOR,  },
 163         [10] = { .vector = IRQ10_VECTOR, },
 164         [11] = { .vector = IRQ11_VECTOR, },
 165         [12] = { .vector = IRQ12_VECTOR, },
 166         [13] = { .vector = IRQ13_VECTOR, },
 167         [14] = { .vector = IRQ14_VECTOR, },
 168         [15] = { .vector = IRQ15_VECTOR, },
 169 };
 170
 171 int __init arch_early_irq_init(void)
 172 {
 173         struct irq_cfg *cfg;
 174         struct irq_desc *desc;
 175         int count;
 176         int i;
 177
 178         cfg = irq_cfgx;
 179         count = ARRAY_SIZE(irq_cfgx);
 180
 181         for (i = 0; i < count; i++) {
 182                 desc = irq_to_desc(i);
 183                 desc->chip_data = &cfg[i];
 184                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 185                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 186                 if (i < NR_IRQS_LEGACY)
 187                         cpumask_setall(cfg[i].domain);
 188         }
 189
 190         return 0;
 191 }
 192
 193 #ifdef CONFIG_SPARSE_IRQ
 194 static struct irq_cfg *irq_cfg(unsigned int irq)
 195 {
 196         struct irq_cfg *cfg = NULL;
 197         struct irq_desc *desc;
 198
 199         desc = irq_to_desc(irq);
 200         if (desc)
 201                 cfg = desc->chip_data;
 202
 203         return cfg;
 204 }
 205
 206 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 207 {
 208         struct irq_cfg *cfg;
 209         int node;
 210
 211         node = cpu_to_node(cpu);
 212
 213         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 214         if (cfg) {
 215                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 216                         kfree(cfg);
 217                         cfg = NULL;
 218                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 219                                                           GFP_ATOMIC, node)) {
 220                         free_cpumask_var(cfg->domain);
 221                         kfree(cfg);
 222                         cfg = NULL;
 223                 } else {
 224                         cpumask_clear(cfg->domain);
 225                         cpumask_clear(cfg->old_domain);
 226                 }
 227         }
 228
 229         return cfg;
 230 }
 231
 232 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 233 {
 234         struct irq_cfg *cfg;
 235
 236         cfg = desc->chip_data;
 237         if (!cfg) {
 238                 desc->chip_data = get_one_free_irq_cfg(cpu);
 239                 if (!desc->chip_data) {
 240                         printk(KERN_ERR "can not alloc irq_cfg\n");
 241                         BUG_ON(1);
 242                 }
 243         }
 244
 245         return 0;
 246 }
 247
 248 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 249
 250 static void
 251 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 252 {
 253         struct irq_pin_list *old_entry, *head, *tail, *entry;
 254
 255         cfg->irq_2_pin = NULL;
 256         old_entry = old_cfg->irq_2_pin;
 257         if (!old_entry)
 258                 return;
 259
 260         entry = get_one_free_irq_2_pin(cpu);
 261         if (!entry)
 262                 return;
 263
 264         entry->apic     = old_entry->apic;
 265         entry->pin      = old_entry->pin;
 266         head            = entry;
 267         tail            = entry;
 268         old_entry       = old_entry->next;
 269         while (old_entry) {
 270                 entry = get_one_free_irq_2_pin(cpu);
 271                 if (!entry) {
 272                         entry = head;
 273                         while (entry) {
 274                                 head = entry->next;
 275                                 kfree(entry);
 276                                 entry = head;
 277                         }
 278                         /* still use the old one */
 279                         return;
 280                 }
 281                 entry->apic     = old_entry->apic;
 282                 entry->pin      = old_entry->pin;
 283                 tail->next      = entry;
 284                 tail            = entry;
 285                 old_entry       = old_entry->next;
 286         }
 287
 288         tail->next = NULL;
 289         cfg->irq_2_pin = head;
 290 }
 291
 292 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 293 {
 294         struct irq_pin_list *entry, *next;
 295
 296         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 297                 return;
 298
 299         entry = old_cfg->irq_2_pin;
 300
 301         while (entry) {
 302                 next = entry->next;
 303                 kfree(entry);
 304                 entry = next;
 305         }
 306         old_cfg->irq_2_pin = NULL;
 307 }
 308
 309 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 310                                  struct irq_desc *desc, int cpu)
 311 {
 312         struct irq_cfg *cfg;
 313         struct irq_cfg *old_cfg;
 314
 315         cfg = get_one_free_irq_cfg(cpu);
 316
 317         if (!cfg)
 318                 return;
 319
 320         desc->chip_data = cfg;
 321
 322         old_cfg = old_desc->chip_data;
 323
 324         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 325
 326         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 327 }
 328
 329 static void free_irq_cfg(struct irq_cfg *old_cfg)
 330 {
 331         kfree(old_cfg);
 332 }
 333
 334 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 335 {
 336         struct irq_cfg *old_cfg, *cfg;
 337
 338         old_cfg = old_desc->chip_data;
 339         cfg = desc->chip_data;
 340
 341         if (old_cfg == cfg)
 342                 return;
 343
 344         if (old_cfg) {
 345                 free_irq_2_pin(old_cfg, cfg);
 346                 free_irq_cfg(old_cfg);
 347                 old_desc->chip_data = NULL;
 348         }
 349 }
 350
 351 static void
 352 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 353 {
 354         struct irq_cfg *cfg = desc->chip_data;
 355
 356         if (!cfg->move_in_progress) {
 357                 /* it means that domain is not changed */
 358                 if (!cpumask_intersects(desc->affinity, mask))
 359                         cfg->move_desc_pending = 1;
 360         }
 361 }
 362 #endif
 363
 364 #else
 365 static struct irq_cfg *irq_cfg(unsigned int irq)
 366 {
 367         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 368 }
 369
 370 #endif
 371
 372 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 373 static inline void
 374 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 375 {
 376 }
 377 #endif
 378
 379 struct io_apic {
 380         unsigned int index;
 381         unsigned int unused[3];
 382         unsigned int data;
 383 };
 384
 385 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 386 {
 387         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 388                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 389 }
 390
 391 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 392 {
 393         struct io_apic __iomem *io_apic = io_apic_base(apic);
 394         writel(reg, &io_apic->index);
 395         return readl(&io_apic->data);
 396 }
 397
 398 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 399 {
 400         struct io_apic __iomem *io_apic = io_apic_base(apic);
 401         writel(reg, &io_apic->index);
 402         writel(value, &io_apic->data);
 403 }
 404
 405 /*
 406  * Re-write a value: to be used for read-modify-write
 407  * cycles where the read already set up the index register.
 408  *
 409  * Older SiS APIC requires we rewrite the index register
 410  */
 411 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 412 {
 413         struct io_apic __iomem *io_apic = io_apic_base(apic);
 414
 415         if (sis_apic_bug)
 416                 writel(reg, &io_apic->index);
 417         writel(value, &io_apic->data);
 418 }
 419
 420 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 421 {
 422         struct irq_pin_list *entry;
 423         unsigned long flags;
 424
 425         spin_lock_irqsave(&ioapic_lock, flags);
 426         entry = cfg->irq_2_pin;
 427         for (;;) {
 428                 unsigned int reg;
 429                 int pin;
 430
 431                 if (!entry)
 432                         break;
 433                 pin = entry->pin;
 434                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 435                 /* Is the remote IRR bit set? */
 436                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 437                         spin_unlock_irqrestore(&ioapic_lock, flags);
 438                         return true;
 439                 }
 440                 if (!entry->next)
 441                         break;
 442                 entry = entry->next;
 443         }
 444         spin_unlock_irqrestore(&ioapic_lock, flags);
 445
 446         return false;
 447 }
 448
 449 union entry_union {
 450         struct { u32 w1, w2; };
 451         struct IO_APIC_route_entry entry;
 452 };
 453
 454 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 455 {
 456         union entry_union eu;
 457         unsigned long flags;
 458         spin_lock_irqsave(&ioapic_lock, flags);
 459         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 460         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462         return eu.entry;
 463 }
 464
 465 /*
 466  * When we write a new IO APIC routing entry, we need to write the high
 467  * word first! If the mask bit in the low word is clear, we will enable
 468  * the interrupt, and we need to make sure the entry is fully populated
 469  * before that happens.
 470  */
 471 static void
 472 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 473 {
 474         union entry_union eu;
 475         eu.entry = e;
 476         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 477         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 478 }
 479
 480 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 481 {
 482         unsigned long flags;
 483         spin_lock_irqsave(&ioapic_lock, flags);
 484         __ioapic_write_entry(apic, pin, e);
 485         spin_unlock_irqrestore(&ioapic_lock, flags);
 486 }
 487
 488 /*
 489  * When we mask an IO APIC routing entry, we need to write the low
 490  * word first, in order to set the mask bit before we change the
 491  * high bits!
 492  */
 493 static void ioapic_mask_entry(int apic, int pin)
 494 {
 495         unsigned long flags;
 496         union entry_union eu = { .entry.mask = 1 };
 497
 498         spin_lock_irqsave(&ioapic_lock, flags);
 499         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 500         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 501         spin_unlock_irqrestore(&ioapic_lock, flags);
 502 }
 503
 504 #ifdef CONFIG_SMP
 505 static void send_cleanup_vector(struct irq_cfg *cfg)
 506 {
 507         cpumask_var_t cleanup_mask;
 508
 509         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 510                 unsigned int i;
 511                 cfg->move_cleanup_count = 0;
 512                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 513                         cfg->move_cleanup_count++;
 514                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 515                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 516         } else {
 517                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 518                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 519                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 520                 free_cpumask_var(cleanup_mask);
 521         }
 522         cfg->move_in_progress = 0;
 523 }
 524
 525 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 526 {
 527         int apic, pin;
 528         struct irq_pin_list *entry;
 529         u8 vector = cfg->vector;
 530
 531         entry = cfg->irq_2_pin;
 532         for (;;) {
 533                 unsigned int reg;
 534
 535                 if (!entry)
 536                         break;
 537
 538                 apic = entry->apic;
 539                 pin = entry->pin;
 540 #ifdef CONFIG_INTR_REMAP
 541                 /*
 542                  * With interrupt-remapping, destination information comes
 543                  * from interrupt-remapping table entry.
 544                  */
 545                 if (!irq_remapped(irq))
 546                         io_apic_write(apic, 0x11 + pin*2, dest);
 547 #else
 548                 io_apic_write(apic, 0x11 + pin*2, dest);
 549 #endif
 550                 reg = io_apic_read(apic, 0x10 + pin*2);
 551                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 552                 reg |= vector;
 553                 io_apic_modify(apic, 0x10 + pin*2, reg);
 554                 if (!entry->next)
 555                         break;
 556                 entry = entry->next;
 557         }
 558 }
 559
 560 static int
 561 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 562
 563 /*
 564  * Either sets desc->affinity to a valid value, and returns
 565  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 566  * leaves desc->affinity untouched.
 567  */
 568 static unsigned int
 569 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 570 {
 571         struct irq_cfg *cfg;
 572         unsigned int irq;
 573
 574         if (!cpumask_intersects(mask, cpu_online_mask))
 575                 return BAD_APICID;
 576
 577         irq = desc->irq;
 578         cfg = desc->chip_data;
 579         if (assign_irq_vector(irq, cfg, mask))
 580                 return BAD_APICID;
 581
 582         cpumask_and(desc->affinity, cfg->domain, mask);
 583         set_extra_move_desc(desc, mask);
 584
 585         return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
 586 }
 587
 588 static void
 589 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 590 {
 591         struct irq_cfg *cfg;
 592         unsigned long flags;
 593         unsigned int dest;
 594         unsigned int irq;
 595
 596         irq = desc->irq;
 597         cfg = desc->chip_data;
 598
 599         spin_lock_irqsave(&ioapic_lock, flags);
 600         dest = set_desc_affinity(desc, mask);
 601         if (dest != BAD_APICID) {
 602                 /* Only the high 8 bits are valid. */
 603                 dest = SET_APIC_LOGICAL_ID(dest);
 604                 __target_IO_APIC_irq(irq, dest, cfg);
 605         }
 606         spin_unlock_irqrestore(&ioapic_lock, flags);
 607 }
 608
 609 static void
 610 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 611 {
 612         struct irq_desc *desc;
 613
 614         desc = irq_to_desc(irq);
 615
 616         set_ioapic_affinity_irq_desc(desc, mask);
 617 }
 618 #endif /* CONFIG_SMP */
 619
 620 /*
 621  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 622  * shared ISA-space IRQs, so we have to support them. We are super
 623  * fast in the common case, and fast for shared ISA-space IRQs.
 624  */
 625 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 626 {
 627         struct irq_pin_list *entry;
 628
 629         entry = cfg->irq_2_pin;
 630         if (!entry) {
 631                 entry = get_one_free_irq_2_pin(cpu);
 632                 if (!entry) {
 633                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 634                                         apic, pin);
 635                         return;
 636                 }
 637                 cfg->irq_2_pin = entry;
 638                 entry->apic = apic;
 639                 entry->pin = pin;
 640                 return;
 641         }
 642
 643         while (entry->next) {
 644                 /* not again, please */
 645                 if (entry->apic == apic && entry->pin == pin)
 646                         return;
 647
 648                 entry = entry->next;
 649         }
 650
 651         entry->next = get_one_free_irq_2_pin(cpu);
 652         entry = entry->next;
 653         entry->apic = apic;
 654         entry->pin = pin;
 655 }
 656
 657 /*
 658  * Reroute an IRQ to a different pin.
 659  */
 660 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 661                                       int oldapic, int oldpin,
 662                                       int newapic, int newpin)
 663 {
 664         struct irq_pin_list *entry = cfg->irq_2_pin;
 665         int replaced = 0;
 666
 667         while (entry) {
 668                 if (entry->apic == oldapic && entry->pin == oldpin) {
 669                         entry->apic = newapic;
 670                         entry->pin = newpin;
 671                         replaced = 1;
 672                         /* every one is different, right? */
 673                         break;
 674                 }
 675                 entry = entry->next;
 676         }
 677
 678         /* why? call replace before add? */
 679         if (!replaced)
 680                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 681 }
 682
 683 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 684                                 int mask_and, int mask_or,
 685                                 void (*final)(struct irq_pin_list *entry))
 686 {
 687         int pin;
 688         struct irq_pin_list *entry;
 689
 690         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 691                 unsigned int reg;
 692                 pin = entry->pin;
 693                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 694                 reg &= mask_and;
 695                 reg |= mask_or;
 696                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 697                 if (final)
 698                         final(entry);
 699         }
 700 }
 701
 702 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 703 {
 704         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 705 }
 706
 707 #ifdef CONFIG_X86_64
 708 static void io_apic_sync(struct irq_pin_list *entry)
 709 {
 710         /*
 711          * Synchronize the IO-APIC and the CPU by doing
 712          * a dummy read from the IO-APIC
 713          */
 714         struct io_apic __iomem *io_apic;
 715         io_apic = io_apic_base(entry->apic);
 716         readl(&io_apic->data);
 717 }
 718
 719 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 720 {
 721         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 722 }
 723 #else /* CONFIG_X86_32 */
 724 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 725 {
 726         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 727 }
 728
 729 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 730 {
 731         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 732                         IO_APIC_REDIR_MASKED, NULL);
 733 }
 734
 735 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 736 {
 737         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 738                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 739 }
 740 #endif /* CONFIG_X86_32 */
 741
 742 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 743 {
 744         struct irq_cfg *cfg = desc->chip_data;
 745         unsigned long flags;
 746
 747         BUG_ON(!cfg);
 748
 749         spin_lock_irqsave(&ioapic_lock, flags);
 750         __mask_IO_APIC_irq(cfg);
 751         spin_unlock_irqrestore(&ioapic_lock, flags);
 752 }
 753
 754 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 755 {
 756         struct irq_cfg *cfg = desc->chip_data;
 757         unsigned long flags;
 758
 759         spin_lock_irqsave(&ioapic_lock, flags);
 760         __unmask_IO_APIC_irq(cfg);
 761         spin_unlock_irqrestore(&ioapic_lock, flags);
 762 }
 763
 764 static void mask_IO_APIC_irq(unsigned int irq)
 765 {
 766         struct irq_desc *desc = irq_to_desc(irq);
 767
 768         mask_IO_APIC_irq_desc(desc);
 769 }
 770 static void unmask_IO_APIC_irq(unsigned int irq)
 771 {
 772         struct irq_desc *desc = irq_to_desc(irq);
 773
 774         unmask_IO_APIC_irq_desc(desc);
 775 }
 776
 777 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 778 {
 779         struct IO_APIC_route_entry entry;
 780
 781         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 782         entry = ioapic_read_entry(apic, pin);
 783         if (entry.delivery_mode == dest_SMI)
 784                 return;
 785         /*
 786          * Disable it in the IO-APIC irq-routing table:
 787          */
 788         ioapic_mask_entry(apic, pin);
 789 }
 790
 791 static void clear_IO_APIC (void)
 792 {
 793         int apic, pin;
 794
 795         for (apic = 0; apic < nr_ioapics; apic++)
 796                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 797                         clear_IO_APIC_pin(apic, pin);
 798 }
 799
 800 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
 801 void default_send_IPI_self(int vector)
 802 {
 803         unsigned int cfg;
 804
 805         /*
 806          * Wait for idle.
 807          */
 808         apic_wait_icr_idle();
 809         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | apic->dest_logical;
 810         /*
 811          * Send the IPI. The write to APIC_ICR fires this off.
 812          */
 813         apic_write(APIC_ICR, cfg);
 814 }
 815 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
 816
 817 #ifdef CONFIG_X86_32
 818 /*
 819  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 820  * specific CPU-side IRQs.
 821  */
 822
 823 #define MAX_PIRQS 8
 824 static int pirq_entries [MAX_PIRQS];
 825 static int pirqs_enabled;
 826
 827 static int __init ioapic_pirq_setup(char *str)
 828 {
 829         int i, max;
 830         int ints[MAX_PIRQS+1];
 831
 832         get_options(str, ARRAY_SIZE(ints), ints);
 833
 834         for (i = 0; i < MAX_PIRQS; i++)
 835                 pirq_entries[i] = -1;
 836
 837         pirqs_enabled = 1;
 838         apic_printk(APIC_VERBOSE, KERN_INFO
 839                         "PIRQ redirection, working around broken MP-BIOS.\n");
 840         max = MAX_PIRQS;
 841         if (ints[0] < MAX_PIRQS)
 842                 max = ints[0];
 843
 844         for (i = 0; i < max; i++) {
 845                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 846                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 847                 /*
 848                  * PIRQs are mapped upside down, usually.
 849                  */
 850                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 851         }
 852         return 1;
 853 }
 854
 855 __setup("pirq=", ioapic_pirq_setup);
 856 #endif /* CONFIG_X86_32 */
 857
 858 #ifdef CONFIG_INTR_REMAP
 859 /* I/O APIC RTE contents at the OS boot up */
 860 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 861
 862 /*
 863  * Saves and masks all the unmasked IO-APIC RTE's
 864  */
 865 int save_mask_IO_APIC_setup(void)
 866 {
 867         union IO_APIC_reg_01 reg_01;
 868         unsigned long flags;
 869         int apic, pin;
 870
 871         /*
 872          * The number of IO-APIC IRQ registers (== #pins):
 873          */
 874         for (apic = 0; apic < nr_ioapics; apic++) {
 875                 spin_lock_irqsave(&ioapic_lock, flags);
 876                 reg_01.raw = io_apic_read(apic, 1);
 877                 spin_unlock_irqrestore(&ioapic_lock, flags);
 878                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 879         }
 880
 881         for (apic = 0; apic < nr_ioapics; apic++) {
 882                 early_ioapic_entries[apic] =
 883                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 884                                 nr_ioapic_registers[apic], GFP_KERNEL);
 885                 if (!early_ioapic_entries[apic])
 886                         goto nomem;
 887         }
 888
 889         for (apic = 0; apic < nr_ioapics; apic++)
 890                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 891                         struct IO_APIC_route_entry entry;
 892
 893                         entry = early_ioapic_entries[apic][pin] =
 894                                 ioapic_read_entry(apic, pin);
 895                         if (!entry.mask) {
 896                                 entry.mask = 1;
 897                                 ioapic_write_entry(apic, pin, entry);
 898                         }
 899                 }
 900
 901         return 0;
 902
 903 nomem:
 904         while (apic >= 0)
 905                 kfree(early_ioapic_entries[apic--]);
 906         memset(early_ioapic_entries, 0,
 907                 ARRAY_SIZE(early_ioapic_entries));
 908
 909         return -ENOMEM;
 910 }
 911
 912 void restore_IO_APIC_setup(void)
 913 {
 914         int apic, pin;
 915
 916         for (apic = 0; apic < nr_ioapics; apic++) {
 917                 if (!early_ioapic_entries[apic])
 918                         break;
 919                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 920                         ioapic_write_entry(apic, pin,
 921                                            early_ioapic_entries[apic][pin]);
 922                 kfree(early_ioapic_entries[apic]);
 923                 early_ioapic_entries[apic] = NULL;
 924         }
 925 }
 926
 927 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 928 {
 929         /*
 930          * for now plain restore of previous settings.
 931          * TBD: In the case of OS enabling interrupt-remapping,
 932          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 933          * table entries. for now, do a plain restore, and wait for
 934          * the setup_IO_APIC_irqs() to do proper initialization.
 935          */
 936         restore_IO_APIC_setup();
 937 }
 938 #endif
 939
 940 /*
 941  * Find the IRQ entry number of a certain pin.
 942  */
 943 static int find_irq_entry(int apic, int pin, int type)
 944 {
 945         int i;
 946
 947         for (i = 0; i < mp_irq_entries; i++)
 948                 if (mp_irqs[i].irqtype == type &&
 949                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 950                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 951                     mp_irqs[i].dstirq == pin)
 952                         return i;
 953
 954         return -1;
 955 }
 956
 957 /*
 958  * Find the pin to which IRQ[irq] (ISA) is connected
 959  */
 960 static int __init find_isa_irq_pin(int irq, int type)
 961 {
 962         int i;
 963
 964         for (i = 0; i < mp_irq_entries; i++) {
 965                 int lbus = mp_irqs[i].srcbus;
 966
 967                 if (test_bit(lbus, mp_bus_not_pci) &&
 968                     (mp_irqs[i].irqtype == type) &&
 969                     (mp_irqs[i].srcbusirq == irq))
 970
 971                         return mp_irqs[i].dstirq;
 972         }
 973         return -1;
 974 }
 975
 976 static int __init find_isa_irq_apic(int irq, int type)
 977 {
 978         int i;
 979
 980         for (i = 0; i < mp_irq_entries; i++) {
 981                 int lbus = mp_irqs[i].srcbus;
 982
 983                 if (test_bit(lbus, mp_bus_not_pci) &&
 984                     (mp_irqs[i].irqtype == type) &&
 985                     (mp_irqs[i].srcbusirq == irq))
 986                         break;
 987         }
 988         if (i < mp_irq_entries) {
 989                 int apic;
 990                 for(apic = 0; apic < nr_ioapics; apic++) {
 991                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 992                                 return apic;
 993                 }
 994         }
 995
 996         return -1;
 997 }
 998
 999 /*
1000  * Find a specific PCI IRQ entry.
1001  * Not an __init, possibly needed by modules
1002  */
1003 static int pin_2_irq(int idx, int apic, int pin);
1004
1005 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1006 {
1007         int apic, i, best_guess = -1;
1008
1009         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1010                 bus, slot, pin);
1011         if (test_bit(bus, mp_bus_not_pci)) {
1012                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1013                 return -1;
1014         }
1015         for (i = 0; i < mp_irq_entries; i++) {
1016                 int lbus = mp_irqs[i].srcbus;
1017
1018                 for (apic = 0; apic < nr_ioapics; apic++)
1019                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1020                             mp_irqs[i].dstapic == MP_APIC_ALL)
1021                                 break;
1022
1023                 if (!test_bit(lbus, mp_bus_not_pci) &&
1024                     !mp_irqs[i].irqtype &&
1025                     (bus == lbus) &&
1026                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1027                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1028
1029                         if (!(apic || IO_APIC_IRQ(irq)))
1030                                 continue;
1031
1032                         if (pin == (mp_irqs[i].srcbusirq & 3))
1033                                 return irq;
1034                         /*
1035                          * Use the first all-but-pin matching entry as a
1036                          * best-guess fuzzy result for broken mptables.
1037                          */
1038                         if (best_guess < 0)
1039                                 best_guess = irq;
1040                 }
1041         }
1042         return best_guess;
1043 }
1044
1045 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1046
1047 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1048 /*
1049  * EISA Edge/Level control register, ELCR
1050  */
1051 static int EISA_ELCR(unsigned int irq)
1052 {
1053         if (irq < NR_IRQS_LEGACY) {
1054                 unsigned int port = 0x4d0 + (irq >> 3);
1055                 return (inb(port) >> (irq & 7)) & 1;
1056         }
1057         apic_printk(APIC_VERBOSE, KERN_INFO
1058                         "Broken MPtable reports ISA irq %d\n", irq);
1059         return 0;
1060 }
1061
1062 #endif
1063
1064 /* ISA interrupts are always polarity zero edge triggered,
1065  * when listed as conforming in the MP table. */
1066
1067 #define default_ISA_trigger(idx)        (0)
1068 #define default_ISA_polarity(idx)       (0)
1069
1070 /* EISA interrupts are always polarity zero and can be edge or level
1071  * trigger depending on the ELCR value.  If an interrupt is listed as
1072  * EISA conforming in the MP table, that means its trigger type must
1073  * be read in from the ELCR */
1074
1075 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1076 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1077
1078 /* PCI interrupts are always polarity one level triggered,
1079  * when listed as conforming in the MP table. */
1080
1081 #define default_PCI_trigger(idx)        (1)
1082 #define default_PCI_polarity(idx)       (1)
1083
1084 /* MCA interrupts are always polarity zero level triggered,
1085  * when listed as conforming in the MP table. */
1086
1087 #define default_MCA_trigger(idx)        (1)
1088 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1089
1090 static int MPBIOS_polarity(int idx)
1091 {
1092         int bus = mp_irqs[idx].srcbus;
1093         int polarity;
1094
1095         /*
1096          * Determine IRQ line polarity (high active or low active):
1097          */
1098         switch (mp_irqs[idx].irqflag & 3)
1099         {
1100                 case 0: /* conforms, ie. bus-type dependent polarity */
1101                         if (test_bit(bus, mp_bus_not_pci))
1102                                 polarity = default_ISA_polarity(idx);
1103                         else
1104                                 polarity = default_PCI_polarity(idx);
1105                         break;
1106                 case 1: /* high active */
1107                 {
1108                         polarity = 0;
1109                         break;
1110                 }
1111                 case 2: /* reserved */
1112                 {
1113                         printk(KERN_WARNING "broken BIOS!!\n");
1114                         polarity = 1;
1115                         break;
1116                 }
1117                 case 3: /* low active */
1118                 {
1119                         polarity = 1;
1120                         break;
1121                 }
1122                 default: /* invalid */
1123                 {
1124                         printk(KERN_WARNING "broken BIOS!!\n");
1125                         polarity = 1;
1126                         break;
1127                 }
1128         }
1129         return polarity;
1130 }
1131
1132 static int MPBIOS_trigger(int idx)
1133 {
1134         int bus = mp_irqs[idx].srcbus;
1135         int trigger;
1136
1137         /*
1138          * Determine IRQ trigger mode (edge or level sensitive):
1139          */
1140         switch ((mp_irqs[idx].irqflag>>2) & 3)
1141         {
1142                 case 0: /* conforms, ie. bus-type dependent */
1143                         if (test_bit(bus, mp_bus_not_pci))
1144                                 trigger = default_ISA_trigger(idx);
1145                         else
1146                                 trigger = default_PCI_trigger(idx);
1147 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1148                         switch (mp_bus_id_to_type[bus]) {
1149                                 case MP_BUS_ISA: /* ISA pin */
1150                                 {
1151                                         /* set before the switch */
1152                                         break;
1153                                 }
1154                                 case MP_BUS_EISA: /* EISA pin */
1155                                 {
1156                                         trigger = default_EISA_trigger(idx);
1157                                         break;
1158                                 }
1159                                 case MP_BUS_PCI: /* PCI pin */
1160                                 {
1161                                         /* set before the switch */
1162                                         break;
1163                                 }
1164                                 case MP_BUS_MCA: /* MCA pin */
1165                                 {
1166                                         trigger = default_MCA_trigger(idx);
1167                                         break;
1168                                 }
1169                                 default:
1170                                 {
1171                                         printk(KERN_WARNING "broken BIOS!!\n");
1172                                         trigger = 1;
1173                                         break;
1174                                 }
1175                         }
1176 #endif
1177                         break;
1178                 case 1: /* edge */
1179                 {
1180                         trigger = 0;
1181                         break;
1182                 }
1183                 case 2: /* reserved */
1184                 {
1185                         printk(KERN_WARNING "broken BIOS!!\n");
1186                         trigger = 1;
1187                         break;
1188                 }
1189                 case 3: /* level */
1190                 {
1191                         trigger = 1;
1192                         break;
1193                 }
1194                 default: /* invalid */
1195                 {
1196                         printk(KERN_WARNING "broken BIOS!!\n");
1197                         trigger = 0;
1198                         break;
1199                 }
1200         }
1201         return trigger;
1202 }
1203
1204 static inline int irq_polarity(int idx)
1205 {
1206         return MPBIOS_polarity(idx);
1207 }
1208
1209 static inline int irq_trigger(int idx)
1210 {
1211         return MPBIOS_trigger(idx);
1212 }
1213
1214 int (*ioapic_renumber_irq)(int ioapic, int irq);
1215 static int pin_2_irq(int idx, int apic, int pin)
1216 {
1217         int irq, i;
1218         int bus = mp_irqs[idx].srcbus;
1219
1220         /*
1221          * Debugging check, we are in big trouble if this message pops up!
1222          */
1223         if (mp_irqs[idx].dstirq != pin)
1224                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1225
1226         if (test_bit(bus, mp_bus_not_pci)) {
1227                 irq = mp_irqs[idx].srcbusirq;
1228         } else {
1229                 /*
1230                  * PCI IRQs are mapped in order
1231                  */
1232                 i = irq = 0;
1233                 while (i < apic)
1234                         irq += nr_ioapic_registers[i++];
1235                 irq += pin;
1236                 /*
1237                  * For MPS mode, so far only needed by ES7000 platform
1238                  */
1239                 if (ioapic_renumber_irq)
1240                         irq = ioapic_renumber_irq(apic, irq);
1241         }
1242
1243 #ifdef CONFIG_X86_32
1244         /*
1245          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1246          */
1247         if ((pin >= 16) && (pin <= 23)) {
1248                 if (pirq_entries[pin-16] != -1) {
1249                         if (!pirq_entries[pin-16]) {
1250                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1251                                                 "disabling PIRQ%d\n", pin-16);
1252                         } else {
1253                                 irq = pirq_entries[pin-16];
1254                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1255                                                 "using PIRQ%d -> IRQ %d\n",
1256                                                 pin-16, irq);
1257                         }
1258                 }
1259         }
1260 #endif
1261
1262         return irq;
1263 }
1264
1265 void lock_vector_lock(void)
1266 {
1267         /* Used to the online set of cpus does not change
1268          * during assign_irq_vector.
1269          */
1270         spin_lock(&vector_lock);
1271 }
1272
1273 void unlock_vector_lock(void)
1274 {
1275         spin_unlock(&vector_lock);
1276 }
1277
1278 static int
1279 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1280 {
1281         /*
1282          * NOTE! The local APIC isn't very good at handling
1283          * multiple interrupts at the same interrupt level.
1284          * As the interrupt level is determined by taking the
1285          * vector number and shifting that right by 4, we
1286          * want to spread these out a bit so that they don't
1287          * all fall in the same interrupt level.
1288          *
1289          * Also, we've got to be careful not to trash gate
1290          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1291          */
1292         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1293         unsigned int old_vector;
1294         int cpu, err;
1295         cpumask_var_t tmp_mask;
1296
1297         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1298                 return -EBUSY;
1299
1300         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1301                 return -ENOMEM;
1302
1303         old_vector = cfg->vector;
1304         if (old_vector) {
1305                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1306                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1307                 if (!cpumask_empty(tmp_mask)) {
1308                         free_cpumask_var(tmp_mask);
1309                         return 0;
1310                 }
1311         }
1312
1313         /* Only try and allocate irqs on cpus that are present */
1314         err = -ENOSPC;
1315         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1316                 int new_cpu;
1317                 int vector, offset;
1318
1319                 apic->vector_allocation_domain(cpu, tmp_mask);
1320
1321                 vector = current_vector;
1322                 offset = current_offset;
1323 next:
1324                 vector += 8;
1325                 if (vector >= first_system_vector) {
1326                         /* If out of vectors on large boxen, must share them. */
1327                         offset = (offset + 1) % 8;
1328                         vector = FIRST_DEVICE_VECTOR + offset;
1329                 }
1330                 if (unlikely(current_vector == vector))
1331                         continue;
1332
1333                 if (test_bit(vector, used_vectors))
1334                         goto next;
1335
1336                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1337                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1338                                 goto next;
1339                 /* Found one! */
1340                 current_vector = vector;
1341                 current_offset = offset;
1342                 if (old_vector) {
1343                         cfg->move_in_progress = 1;
1344                         cpumask_copy(cfg->old_domain, cfg->domain);
1345                 }
1346                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1347                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1348                 cfg->vector = vector;
1349                 cpumask_copy(cfg->domain, tmp_mask);
1350                 err = 0;
1351                 break;
1352         }
1353         free_cpumask_var(tmp_mask);
1354         return err;
1355 }
1356
1357 static int
1358 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1359 {
1360         int err;
1361         unsigned long flags;
1362
1363         spin_lock_irqsave(&vector_lock, flags);
1364         err = __assign_irq_vector(irq, cfg, mask);
1365         spin_unlock_irqrestore(&vector_lock, flags);
1366         return err;
1367 }
1368
1369 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1370 {
1371         int cpu, vector;
1372
1373         BUG_ON(!cfg->vector);
1374
1375         vector = cfg->vector;
1376         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1377                 per_cpu(vector_irq, cpu)[vector] = -1;
1378
1379         cfg->vector = 0;
1380         cpumask_clear(cfg->domain);
1381
1382         if (likely(!cfg->move_in_progress))
1383                 return;
1384         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1385                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1386                                                                 vector++) {
1387                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1388                                 continue;
1389                         per_cpu(vector_irq, cpu)[vector] = -1;
1390                         break;
1391                 }
1392         }
1393         cfg->move_in_progress = 0;
1394 }
1395
1396 void __setup_vector_irq(int cpu)
1397 {
1398         /* Initialize vector_irq on a new cpu */
1399         /* This function must be called with vector_lock held */
1400         int irq, vector;
1401         struct irq_cfg *cfg;
1402         struct irq_desc *desc;
1403
1404         /* Mark the inuse vectors */
1405         for_each_irq_desc(irq, desc) {
1406                 cfg = desc->chip_data;
1407                 if (!cpumask_test_cpu(cpu, cfg->domain))
1408                         continue;
1409                 vector = cfg->vector;
1410                 per_cpu(vector_irq, cpu)[vector] = irq;
1411         }
1412         /* Mark the free vectors */
1413         for (vector = 0; vector < NR_VECTORS; ++vector) {
1414                 irq = per_cpu(vector_irq, cpu)[vector];
1415                 if (irq < 0)
1416                         continue;
1417
1418                 cfg = irq_cfg(irq);
1419                 if (!cpumask_test_cpu(cpu, cfg->domain))
1420                         per_cpu(vector_irq, cpu)[vector] = -1;
1421         }
1422 }
1423
1424 static struct irq_chip ioapic_chip;
1425 #ifdef CONFIG_INTR_REMAP
1426 static struct irq_chip ir_ioapic_chip;
1427 #endif
1428
1429 #define IOAPIC_AUTO     -1
1430 #define IOAPIC_EDGE     0
1431 #define IOAPIC_LEVEL    1
1432
1433 #ifdef CONFIG_X86_32
1434 static inline int IO_APIC_irq_trigger(int irq)
1435 {
1436         int apic, idx, pin;
1437
1438         for (apic = 0; apic < nr_ioapics; apic++) {
1439                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1440                         idx = find_irq_entry(apic, pin, mp_INT);
1441                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1442                                 return irq_trigger(idx);
1443                 }
1444         }
1445         /*
1446          * nonexistent IRQs are edge default
1447          */
1448         return 0;
1449 }
1450 #else
1451 static inline int IO_APIC_irq_trigger(int irq)
1452 {
1453         return 1;
1454 }
1455 #endif
1456
1457 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1458 {
1459
1460         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1461             trigger == IOAPIC_LEVEL)
1462                 desc->status |= IRQ_LEVEL;
1463         else
1464                 desc->status &= ~IRQ_LEVEL;
1465
1466 #ifdef CONFIG_INTR_REMAP
1467         if (irq_remapped(irq)) {
1468                 desc->status |= IRQ_MOVE_PCNTXT;
1469                 if (trigger)
1470                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1471                                                       handle_fasteoi_irq,
1472                                                      "fasteoi");
1473                 else
1474                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1475                                                       handle_edge_irq, "edge");
1476                 return;
1477         }
1478 #endif
1479         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1480             trigger == IOAPIC_LEVEL)
1481                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1482                                               handle_fasteoi_irq,
1483                                               "fasteoi");
1484         else
1485                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1486                                               handle_edge_irq, "edge");
1487 }
1488
1489 static int setup_ioapic_entry(int apic_id, int irq,
1490                               struct IO_APIC_route_entry *entry,
1491                               unsigned int destination, int trigger,
1492                               int polarity, int vector)
1493 {
1494         /*
1495          * add it to the IO-APIC irq-routing table:
1496          */
1497         memset(entry,0,sizeof(*entry));
1498
1499 #ifdef CONFIG_INTR_REMAP
1500         if (intr_remapping_enabled) {
1501                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1502                 struct irte irte;
1503                 struct IR_IO_APIC_route_entry *ir_entry =
1504                         (struct IR_IO_APIC_route_entry *) entry;
1505                 int index;
1506
1507                 if (!iommu)
1508                         panic("No mapping iommu for ioapic %d\n", apic_id);
1509
1510                 index = alloc_irte(iommu, irq, 1);
1511                 if (index < 0)
1512                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1513
1514                 memset(&irte, 0, sizeof(irte));
1515
1516                 irte.present = 1;
1517                 irte.dst_mode = apic->irq_dest_mode;
1518                 irte.trigger_mode = trigger;
1519                 irte.dlvry_mode = apic->irq_delivery_mode;
1520                 irte.vector = vector;
1521                 irte.dest_id = IRTE_DEST(destination);
1522
1523                 modify_irte(irq, &irte);
1524
1525                 ir_entry->index2 = (index >> 15) & 0x1;
1526                 ir_entry->zero = 0;
1527                 ir_entry->format = 1;
1528                 ir_entry->index = (index & 0x7fff);
1529         } else
1530 #endif
1531         {
1532                 entry->delivery_mode = apic->irq_delivery_mode;
1533                 entry->dest_mode = apic->irq_dest_mode;
1534                 entry->dest = destination;
1535         }
1536
1537         entry->mask = 0;                                /* enable IRQ */
1538         entry->trigger = trigger;
1539         entry->polarity = polarity;
1540         entry->vector = vector;
1541
1542         /* Mask level triggered irqs.
1543          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1544          */
1545         if (trigger)
1546                 entry->mask = 1;
1547         return 0;
1548 }
1549
1550 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1551                               int trigger, int polarity)
1552 {
1553         struct irq_cfg *cfg;
1554         struct IO_APIC_route_entry entry;
1555         unsigned int dest;
1556
1557         if (!IO_APIC_IRQ(irq))
1558                 return;
1559
1560         cfg = desc->chip_data;
1561
1562         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1563                 return;
1564
1565         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1566
1567         apic_printk(APIC_VERBOSE,KERN_DEBUG
1568                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1569                     "IRQ %d Mode:%i Active:%i)\n",
1570                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1571                     irq, trigger, polarity);
1572
1573
1574         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1575                                dest, trigger, polarity, cfg->vector)) {
1576                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1577                        mp_ioapics[apic_id].apicid, pin);
1578                 __clear_irq_vector(irq, cfg);
1579                 return;
1580         }
1581
1582         ioapic_register_intr(irq, desc, trigger);
1583         if (irq < NR_IRQS_LEGACY)
1584                 disable_8259A_irq(irq);
1585
1586         ioapic_write_entry(apic_id, pin, entry);
1587 }
1588
1589 static void __init setup_IO_APIC_irqs(void)
1590 {
1591         int apic_id, pin, idx, irq;
1592         int notcon = 0;
1593         struct irq_desc *desc;
1594         struct irq_cfg *cfg;
1595         int cpu = boot_cpu_id;
1596
1597         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1598
1599         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1600                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1601
1602                         idx = find_irq_entry(apic_id, pin, mp_INT);
1603                         if (idx == -1) {
1604                                 if (!notcon) {
1605                                         notcon = 1;
1606                                         apic_printk(APIC_VERBOSE,
1607                                                 KERN_DEBUG " %d-%d",
1608                                                 mp_ioapics[apic_id].apicid, pin);
1609                                 } else
1610                                         apic_printk(APIC_VERBOSE, " %d-%d",
1611                                                 mp_ioapics[apic_id].apicid, pin);
1612                                 continue;
1613                         }
1614                         if (notcon) {
1615                                 apic_printk(APIC_VERBOSE,
1616                                         " (apicid-pin) not connected\n");
1617                                 notcon = 0;
1618                         }
1619
1620                         irq = pin_2_irq(idx, apic_id, pin);
1621
1622                         /*
1623                          * Skip the timer IRQ if there's a quirk handler
1624                          * installed and if it returns 1:
1625                          */
1626                         if (apic->multi_timer_check &&
1627                                         apic->multi_timer_check(apic_id, irq))
1628                                 continue;
1629
1630                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1631                         if (!desc) {
1632                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1633                                 continue;
1634                         }
1635                         cfg = desc->chip_data;
1636                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1637
1638                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1639                                         irq_trigger(idx), irq_polarity(idx));
1640                 }
1641         }
1642
1643         if (notcon)
1644                 apic_printk(APIC_VERBOSE,
1645                         " (apicid-pin) not connected\n");
1646 }
1647
1648 /*
1649  * Set up the timer pin, possibly with the 8259A-master behind.
1650  */
1651 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1652                                         int vector)
1653 {
1654         struct IO_APIC_route_entry entry;
1655
1656 #ifdef CONFIG_INTR_REMAP
1657         if (intr_remapping_enabled)
1658                 return;
1659 #endif
1660
1661         memset(&entry, 0, sizeof(entry));
1662
1663         /*
1664          * We use logical delivery to get the timer IRQ
1665          * to the first CPU.
1666          */
1667         entry.dest_mode = apic->irq_dest_mode;
1668         entry.mask = 1;                                 /* mask IRQ now */
1669         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1670         entry.delivery_mode = apic->irq_delivery_mode;
1671         entry.polarity = 0;
1672         entry.trigger = 0;
1673         entry.vector = vector;
1674
1675         /*
1676          * The timer IRQ doesn't have to know that behind the
1677          * scene we may have a 8259A-master in AEOI mode ...
1678          */
1679         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1680
1681         /*
1682          * Add it to the IO-APIC irq-routing table:
1683          */
1684         ioapic_write_entry(apic_id, pin, entry);
1685 }
1686
1687
1688 __apicdebuginit(void) print_IO_APIC(void)
1689 {
1690         int apic, i;
1691         union IO_APIC_reg_00 reg_00;
1692         union IO_APIC_reg_01 reg_01;
1693         union IO_APIC_reg_02 reg_02;
1694         union IO_APIC_reg_03 reg_03;
1695         unsigned long flags;
1696         struct irq_cfg *cfg;
1697         struct irq_desc *desc;
1698         unsigned int irq;
1699
1700         if (apic_verbosity == APIC_QUIET)
1701                 return;
1702
1703         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1704         for (i = 0; i < nr_ioapics; i++)
1705                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1706                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1707
1708         /*
1709          * We are a bit conservative about what we expect.  We have to
1710          * know about every hardware change ASAP.
1711          */
1712         printk(KERN_INFO "testing the IO APIC.......................\n");
1713
1714         for (apic = 0; apic < nr_ioapics; apic++) {
1715
1716         spin_lock_irqsave(&ioapic_lock, flags);
1717         reg_00.raw = io_apic_read(apic, 0);
1718         reg_01.raw = io_apic_read(apic, 1);
1719         if (reg_01.bits.version >= 0x10)
1720                 reg_02.raw = io_apic_read(apic, 2);
1721         if (reg_01.bits.version >= 0x20)
1722                 reg_03.raw = io_apic_read(apic, 3);
1723         spin_unlock_irqrestore(&ioapic_lock, flags);
1724
1725         printk("\n");
1726         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1727         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1728         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1729         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1730         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1731
1732         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1733         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1734
1735         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1736         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1737
1738         /*
1739          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1740          * but the value of reg_02 is read as the previous read register
1741          * value, so ignore it if reg_02 == reg_01.
1742          */
1743         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1744                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1745                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1746         }
1747
1748         /*
1749          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1750          * or reg_03, but the value of reg_0[23] is read as the previous read
1751          * register value, so ignore it if reg_03 == reg_0[12].
1752          */
1753         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1754             reg_03.raw != reg_01.raw) {
1755                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1756                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1757         }
1758
1759         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1760
1761         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1762                           " Stat Dmod Deli Vect:   \n");
1763
1764         for (i = 0; i <= reg_01.bits.entries; i++) {
1765                 struct IO_APIC_route_entry entry;
1766
1767                 entry = ioapic_read_entry(apic, i);
1768
1769                 printk(KERN_DEBUG " %02x %03X ",
1770                         i,
1771                         entry.dest
1772                 );
1773
1774                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1775                         entry.mask,
1776                         entry.trigger,
1777                         entry.irr,
1778                         entry.polarity,
1779                         entry.delivery_status,
1780                         entry.dest_mode,
1781                         entry.delivery_mode,
1782                         entry.vector
1783                 );
1784         }
1785         }
1786         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1787         for_each_irq_desc(irq, desc) {
1788                 struct irq_pin_list *entry;
1789
1790                 cfg = desc->chip_data;
1791                 entry = cfg->irq_2_pin;
1792                 if (!entry)
1793                         continue;
1794                 printk(KERN_DEBUG "IRQ%d ", irq);
1795                 for (;;) {
1796                         printk("-> %d:%d", entry->apic, entry->pin);
1797                         if (!entry->next)
1798                                 break;
1799                         entry = entry->next;
1800                 }
1801                 printk("\n");
1802         }
1803
1804         printk(KERN_INFO ".................................... done.\n");
1805
1806         return;
1807 }
1808
1809 __apicdebuginit(void) print_APIC_bitfield(int base)
1810 {
1811         unsigned int v;
1812         int i, j;
1813
1814         if (apic_verbosity == APIC_QUIET)
1815                 return;
1816
1817         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1818         for (i = 0; i < 8; i++) {
1819                 v = apic_read(base + i*0x10);
1820                 for (j = 0; j < 32; j++) {
1821                         if (v & (1<<j))
1822                                 printk("1");
1823                         else
1824                                 printk("0");
1825                 }
1826                 printk("\n");
1827         }
1828 }
1829
1830 __apicdebuginit(void) print_local_APIC(void *dummy)
1831 {
1832         unsigned int v, ver, maxlvt;
1833         u64 icr;
1834
1835         if (apic_verbosity == APIC_QUIET)
1836                 return;
1837
1838         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1839                 smp_processor_id(), hard_smp_processor_id());
1840         v = apic_read(APIC_ID);
1841         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1842         v = apic_read(APIC_LVR);
1843         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1844         ver = GET_APIC_VERSION(v);
1845         maxlvt = lapic_get_maxlvt();
1846
1847         v = apic_read(APIC_TASKPRI);
1848         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1849
1850         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1851                 if (!APIC_XAPIC(ver)) {
1852                         v = apic_read(APIC_ARBPRI);
1853                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1854                                v & APIC_ARBPRI_MASK);
1855                 }
1856                 v = apic_read(APIC_PROCPRI);
1857                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1858         }
1859
1860         /*
1861          * Remote read supported only in the 82489DX and local APIC for
1862          * Pentium processors.
1863          */
1864         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1865                 v = apic_read(APIC_RRR);
1866                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1867         }
1868
1869         v = apic_read(APIC_LDR);
1870         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1871         if (!x2apic_enabled()) {
1872                 v = apic_read(APIC_DFR);
1873                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1874         }
1875         v = apic_read(APIC_SPIV);
1876         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1877
1878         printk(KERN_DEBUG "... APIC ISR field:\n");
1879         print_APIC_bitfield(APIC_ISR);
1880         printk(KERN_DEBUG "... APIC TMR field:\n");
1881         print_APIC_bitfield(APIC_TMR);
1882         printk(KERN_DEBUG "... APIC IRR field:\n");
1883         print_APIC_bitfield(APIC_IRR);
1884
1885         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1886                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1887                         apic_write(APIC_ESR, 0);
1888
1889                 v = apic_read(APIC_ESR);
1890                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1891         }
1892
1893         icr = apic_icr_read();
1894         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1895         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1896
1897         v = apic_read(APIC_LVTT);
1898         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1899
1900         if (maxlvt > 3) {                       /* PC is LVT#4. */
1901                 v = apic_read(APIC_LVTPC);
1902                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1903         }
1904         v = apic_read(APIC_LVT0);
1905         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1906         v = apic_read(APIC_LVT1);
1907         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1908
1909         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1910                 v = apic_read(APIC_LVTERR);
1911                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1912         }
1913
1914         v = apic_read(APIC_TMICT);
1915         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1916         v = apic_read(APIC_TMCCT);
1917         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1918         v = apic_read(APIC_TDCR);
1919         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1920         printk("\n");
1921 }
1922
1923 __apicdebuginit(void) print_all_local_APICs(void)
1924 {
1925         int cpu;
1926
1927         preempt_disable();
1928         for_each_online_cpu(cpu)
1929                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1930         preempt_enable();
1931 }
1932
1933 __apicdebuginit(void) print_PIC(void)
1934 {
1935         unsigned int v;
1936         unsigned long flags;
1937
1938         if (apic_verbosity == APIC_QUIET)
1939                 return;
1940
1941         printk(KERN_DEBUG "\nprinting PIC contents\n");
1942
1943         spin_lock_irqsave(&i8259A_lock, flags);
1944
1945         v = inb(0xa1) << 8 | inb(0x21);
1946         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1947
1948         v = inb(0xa0) << 8 | inb(0x20);
1949         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1950
1951         outb(0x0b,0xa0);
1952         outb(0x0b,0x20);
1953         v = inb(0xa0) << 8 | inb(0x20);
1954         outb(0x0a,0xa0);
1955         outb(0x0a,0x20);
1956
1957         spin_unlock_irqrestore(&i8259A_lock, flags);
1958
1959         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1960
1961         v = inb(0x4d1) << 8 | inb(0x4d0);
1962         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1963 }
1964
1965 __apicdebuginit(int) print_all_ICs(void)
1966 {
1967         print_PIC();
1968         print_all_local_APICs();
1969         print_IO_APIC();
1970
1971         return 0;
1972 }
1973
1974 fs_initcall(print_all_ICs);
1975
1976
1977 /* Where if anywhere is the i8259 connect in external int mode */
1978 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1979
1980 void __init enable_IO_APIC(void)
1981 {
1982         union IO_APIC_reg_01 reg_01;
1983         int i8259_apic, i8259_pin;
1984         int apic;
1985         unsigned long flags;
1986
1987 #ifdef CONFIG_X86_32
1988         int i;
1989         if (!pirqs_enabled)
1990                 for (i = 0; i < MAX_PIRQS; i++)
1991                         pirq_entries[i] = -1;
1992 #endif
1993
1994         /*
1995          * The number of IO-APIC IRQ registers (== #pins):
1996          */
1997         for (apic = 0; apic < nr_ioapics; apic++) {
1998                 spin_lock_irqsave(&ioapic_lock, flags);
1999                 reg_01.raw = io_apic_read(apic, 1);
2000                 spin_unlock_irqrestore(&ioapic_lock, flags);
2001                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2002         }
2003         for(apic = 0; apic < nr_ioapics; apic++) {
2004                 int pin;
2005                 /* See if any of the pins is in ExtINT mode */
2006                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2007                         struct IO_APIC_route_entry entry;
2008                         entry = ioapic_read_entry(apic, pin);
2009
2010                         /* If the interrupt line is enabled and in ExtInt mode
2011                          * I have found the pin where the i8259 is connected.
2012                          */
2013                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2014                                 ioapic_i8259.apic = apic;
2015                                 ioapic_i8259.pin  = pin;
2016                                 goto found_i8259;
2017                         }
2018                 }
2019         }
2020  found_i8259:
2021         /* Look to see what if the MP table has reported the ExtINT */
2022         /* If we could not find the appropriate pin by looking at the ioapic
2023          * the i8259 probably is not connected the ioapic but give the
2024          * mptable a chance anyway.
2025          */
2026         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2027         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2028         /* Trust the MP table if nothing is setup in the hardware */
2029         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2030                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2031                 ioapic_i8259.pin  = i8259_pin;
2032                 ioapic_i8259.apic = i8259_apic;
2033         }
2034         /* Complain if the MP table and the hardware disagree */
2035         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2036                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2037         {
2038                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2039         }
2040
2041         /*
2042          * Do not trust the IO-APIC being empty at bootup
2043          */
2044         clear_IO_APIC();
2045 }
2046
2047 /*
2048  * Not an __init, needed by the reboot code
2049  */
2050 void disable_IO_APIC(void)
2051 {
2052         /*
2053          * Clear the IO-APIC before rebooting:
2054          */
2055         clear_IO_APIC();
2056
2057         /*
2058          * If the i8259 is routed through an IOAPIC
2059          * Put that IOAPIC in virtual wire mode
2060          * so legacy interrupts can be delivered.
2061          */
2062         if (ioapic_i8259.pin != -1) {
2063                 struct IO_APIC_route_entry entry;
2064
2065                 memset(&entry, 0, sizeof(entry));
2066                 entry.mask            = 0; /* Enabled */
2067                 entry.trigger         = 0; /* Edge */
2068                 entry.irr             = 0;
2069                 entry.polarity        = 0; /* High */
2070                 entry.delivery_status = 0;
2071                 entry.dest_mode       = 0; /* Physical */
2072                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2073                 entry.vector          = 0;
2074                 entry.dest            = read_apic_id();
2075
2076                 /*
2077                  * Add it to the IO-APIC irq-routing table:
2078                  */
2079                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2080         }
2081
2082         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2083 }
2084
2085 #ifdef CONFIG_X86_32
2086 /*
2087  * function to set the IO-APIC physical IDs based on the
2088  * values stored in the MPC table.
2089  *
2090  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2091  */
2092
2093 static void __init setup_ioapic_ids_from_mpc(void)
2094 {
2095         union IO_APIC_reg_00 reg_00;
2096         physid_mask_t phys_id_present_map;
2097         int apic_id;
2098         int i;
2099         unsigned char old_id;
2100         unsigned long flags;
2101
2102         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2103                 return;
2104
2105         /*
2106          * Don't check I/O APIC IDs for xAPIC systems.  They have
2107          * no meaning without the serial APIC bus.
2108          */
2109         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2110                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2111                 return;
2112         /*
2113          * This is broken; anything with a real cpu count has to
2114          * circumvent this idiocy regardless.
2115          */
2116         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2117
2118         /*
2119          * Set the IOAPIC ID to the value stored in the MPC table.
2120          */
2121         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2122
2123                 /* Read the register 0 value */
2124                 spin_lock_irqsave(&ioapic_lock, flags);
2125                 reg_00.raw = io_apic_read(apic_id, 0);
2126                 spin_unlock_irqrestore(&ioapic_lock, flags);
2127
2128                 old_id = mp_ioapics[apic_id].apicid;
2129
2130                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2131                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2132                                 apic_id, mp_ioapics[apic_id].apicid);
2133                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2134                                 reg_00.bits.ID);
2135                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2136                 }
2137
2138                 /*
2139                  * Sanity check, is the ID really free? Every APIC in a
2140                  * system must have a unique ID or we get lots of nice
2141                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2142                  */
2143                 if (apic->check_apicid_used(phys_id_present_map,
2144                                         mp_ioapics[apic_id].apicid)) {
2145                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2146                                 apic_id, mp_ioapics[apic_id].apicid);
2147                         for (i = 0; i < get_physical_broadcast(); i++)
2148                                 if (!physid_isset(i, phys_id_present_map))
2149                                         break;
2150                         if (i >= get_physical_broadcast())
2151                                 panic("Max APIC ID exceeded!\n");
2152                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2153                                 i);
2154                         physid_set(i, phys_id_present_map);
2155                         mp_ioapics[apic_id].apicid = i;
2156                 } else {
2157                         physid_mask_t tmp;
2158                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2159                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2160                                         "phys_id_present_map\n",
2161                                         mp_ioapics[apic_id].apicid);
2162                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2163                 }
2164
2165
2166                 /*
2167                  * We need to adjust the IRQ routing table
2168                  * if the ID changed.
2169                  */
2170                 if (old_id != mp_ioapics[apic_id].apicid)
2171                         for (i = 0; i < mp_irq_entries; i++)
2172                                 if (mp_irqs[i].dstapic == old_id)
2173                                         mp_irqs[i].dstapic
2174                                                 = mp_ioapics[apic_id].apicid;
2175
2176                 /*
2177                  * Read the right value from the MPC table and
2178                  * write it into the ID register.
2179                  */
2180                 apic_printk(APIC_VERBOSE, KERN_INFO
2181                         "...changing IO-APIC physical APIC ID to %d ...",
2182                         mp_ioapics[apic_id].apicid);
2183
2184                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2185                 spin_lock_irqsave(&ioapic_lock, flags);
2186                 io_apic_write(apic_id, 0, reg_00.raw);
2187                 spin_unlock_irqrestore(&ioapic_lock, flags);
2188
2189                 /*
2190                  * Sanity check
2191                  */
2192                 spin_lock_irqsave(&ioapic_lock, flags);
2193                 reg_00.raw = io_apic_read(apic_id, 0);
2194                 spin_unlock_irqrestore(&ioapic_lock, flags);
2195                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2196                         printk("could not set ID!\n");
2197                 else
2198                         apic_printk(APIC_VERBOSE, " ok.\n");
2199         }
2200 }
2201 #endif
2202
2203 int no_timer_check __initdata;
2204
2205 static int __init notimercheck(char *s)
2206 {
2207         no_timer_check = 1;
2208         return 1;
2209 }
2210 __setup("no_timer_check", notimercheck);
2211
2212 /*
2213  * There is a nasty bug in some older SMP boards, their mptable lies
2214  * about the timer IRQ. We do the following to work around the situation:
2215  *
2216  *      - timer IRQ defaults to IO-APIC IRQ
2217  *      - if this function detects that timer IRQs are defunct, then we fall
2218  *        back to ISA timer IRQs
2219  */
2220 static int __init timer_irq_works(void)
2221 {
2222         unsigned long t1 = jiffies;
2223         unsigned long flags;
2224
2225         if (no_timer_check)
2226                 return 1;
2227
2228         local_save_flags(flags);
2229         local_irq_enable();
2230         /* Let ten ticks pass... */
2231         mdelay((10 * 1000) / HZ);
2232         local_irq_restore(flags);
2233
2234         /*
2235          * Expect a few ticks at least, to be sure some possible
2236          * glue logic does not lock up after one or two first
2237          * ticks in a non-ExtINT mode.  Also the local APIC
2238          * might have cached one ExtINT interrupt.  Finally, at
2239          * least one tick may be lost due to delays.
2240          */
2241
2242         /* jiffies wrap? */
2243         if (time_after(jiffies, t1 + 4))
2244                 return 1;
2245         return 0;
2246 }
2247
2248 /*
2249  * In the SMP+IOAPIC case it might happen that there are an unspecified
2250  * number of pending IRQ events unhandled. These cases are very rare,
2251  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2252  * better to do it this way as thus we do not have to be aware of
2253  * 'pending' interrupts in the IRQ path, except at this point.
2254  */
2255 /*
2256  * Edge triggered needs to resend any interrupt
2257  * that was delayed but this is now handled in the device
2258  * independent code.
2259  */
2260
2261 /*
2262  * Starting up a edge-triggered IO-APIC interrupt is
2263  * nasty - we need to make sure that we get the edge.
2264  * If it is already asserted for some reason, we need
2265  * return 1 to indicate that is was pending.
2266  *
2267  * This is not complete - we should be able to fake
2268  * an edge even if it isn't on the 8259A...
2269  */
2270
2271 static unsigned int startup_ioapic_irq(unsigned int irq)
2272 {
2273         int was_pending = 0;
2274         unsigned long flags;
2275         struct irq_cfg *cfg;
2276
2277         spin_lock_irqsave(&ioapic_lock, flags);
2278         if (irq < NR_IRQS_LEGACY) {
2279                 disable_8259A_irq(irq);
2280                 if (i8259A_irq_pending(irq))
2281                         was_pending = 1;
2282         }
2283         cfg = irq_cfg(irq);
2284         __unmask_IO_APIC_irq(cfg);
2285         spin_unlock_irqrestore(&ioapic_lock, flags);
2286
2287         return was_pending;
2288 }
2289
2290 #ifdef CONFIG_X86_64
2291 static int ioapic_retrigger_irq(unsigned int irq)
2292 {
2293
2294         struct irq_cfg *cfg = irq_cfg(irq);
2295         unsigned long flags;
2296
2297         spin_lock_irqsave(&vector_lock, flags);
2298         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2299         spin_unlock_irqrestore(&vector_lock, flags);
2300
2301         return 1;
2302 }
2303 #else
2304 static int ioapic_retrigger_irq(unsigned int irq)
2305 {
2306         apic->send_IPI_self(irq_cfg(irq)->vector);
2307
2308         return 1;
2309 }
2310 #endif
2311
2312 /*
2313  * Level and edge triggered IO-APIC interrupts need different handling,
2314  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2315  * handled with the level-triggered descriptor, but that one has slightly
2316  * more overhead. Level-triggered interrupts cannot be handled with the
2317  * edge-triggered handler, without risking IRQ storms and other ugly
2318  * races.
2319  */
2320
2321 #ifdef CONFIG_SMP
2322
2323 #ifdef CONFIG_INTR_REMAP
2324 static void ir_irq_migration(struct work_struct *work);
2325
2326 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2327
2328 /*
2329  * Migrate the IO-APIC irq in the presence of intr-remapping.
2330  *
2331  * For edge triggered, irq migration is a simple atomic update(of vector
2332  * and cpu destination) of IRTE and flush the hardware cache.
2333  *
2334  * For level triggered, we need to modify the io-apic RTE aswell with the update
2335  * vector information, along with modifying IRTE with vector and destination.
2336  * So irq migration for level triggered is little  bit more complex compared to
2337  * edge triggered migration. But the good news is, we use the same algorithm
2338  * for level triggered migration as we have today, only difference being,
2339  * we now initiate the irq migration from process context instead of the
2340  * interrupt context.
2341  *
2342  * In future, when we do a directed EOI (combined with cpu EOI broadcast
2343  * suppression) to the IO-APIC, level triggered irq migration will also be
2344  * as simple as edge triggered migration and we can do the irq migration
2345  * with a simple atomic update to IO-APIC RTE.
2346  */
2347 static void
2348 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2349 {
2350         struct irq_cfg *cfg;
2351         struct irte irte;
2352         int modify_ioapic_rte;
2353         unsigned int dest;
2354         unsigned long flags;
2355         unsigned int irq;
2356
2357         if (!cpumask_intersects(mask, cpu_online_mask))
2358                 return;
2359
2360         irq = desc->irq;
2361         if (get_irte(irq, &irte))
2362                 return;
2363
2364         cfg = desc->chip_data;
2365         if (assign_irq_vector(irq, cfg, mask))
2366                 return;
2367
2368         set_extra_move_desc(desc, mask);
2369
2370         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2371
2372         modify_ioapic_rte = desc->status & IRQ_LEVEL;
2373         if (modify_ioapic_rte) {
2374                 spin_lock_irqsave(&ioapic_lock, flags);
2375                 __target_IO_APIC_irq(irq, dest, cfg);
2376                 spin_unlock_irqrestore(&ioapic_lock, flags);
2377         }
2378
2379         irte.vector = cfg->vector;
2380         irte.dest_id = IRTE_DEST(dest);
2381
2382         /*
2383          * Modified the IRTE and flushes the Interrupt entry cache.
2384          */
2385         modify_irte(irq, &irte);
2386
2387         if (cfg->move_in_progress)
2388                 send_cleanup_vector(cfg);
2389
2390         cpumask_copy(desc->affinity, mask);
2391 }
2392
2393 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2394 {
2395         int ret = -1;
2396         struct irq_cfg *cfg = desc->chip_data;
2397
2398         mask_IO_APIC_irq_desc(desc);
2399
2400         if (io_apic_level_ack_pending(cfg)) {
2401                 /*
2402                  * Interrupt in progress. Migrating irq now will change the
2403                  * vector information in the IO-APIC RTE and that will confuse
2404                  * the EOI broadcast performed by cpu.
2405                  * So, delay the irq migration to the next instance.
2406                  */
2407                 schedule_delayed_work(&ir_migration_work, 1);
2408                 goto unmask;
2409         }
2410
2411         /* everthing is clear. we have right of way */
2412         migrate_ioapic_irq_desc(desc, desc->pending_mask);
2413
2414         ret = 0;
2415         desc->status &= ~IRQ_MOVE_PENDING;
2416         cpumask_clear(desc->pending_mask);
2417
2418 unmask:
2419         unmask_IO_APIC_irq_desc(desc);
2420
2421         return ret;
2422 }
2423
2424 static void ir_irq_migration(struct work_struct *work)
2425 {
2426         unsigned int irq;
2427         struct irq_desc *desc;
2428
2429         for_each_irq_desc(irq, desc) {
2430                 if (desc->status & IRQ_MOVE_PENDING) {
2431                         unsigned long flags;
2432
2433                         spin_lock_irqsave(&desc->lock, flags);
2434                         if (!desc->chip->set_affinity ||
2435                             !(desc->status & IRQ_MOVE_PENDING)) {
2436                                 desc->status &= ~IRQ_MOVE_PENDING;
2437                                 spin_unlock_irqrestore(&desc->lock, flags);
2438                                 continue;
2439                         }
2440
2441                         desc->chip->set_affinity(irq, desc->pending_mask);
2442                         spin_unlock_irqrestore(&desc->lock, flags);
2443                 }
2444         }
2445 }
2446
2447 /*
2448  * Migrates the IRQ destination in the process context.
2449  */
2450 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2451                                             const struct cpumask *mask)
2452 {
2453         if (desc->status & IRQ_LEVEL) {
2454                 desc->status |= IRQ_MOVE_PENDING;
2455                 cpumask_copy(desc->pending_mask, mask);
2456                 migrate_irq_remapped_level_desc(desc);
2457                 return;
2458         }
2459
2460         migrate_ioapic_irq_desc(desc, mask);
2461 }
2462 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2463                                        const struct cpumask *mask)
2464 {
2465         struct irq_desc *desc = irq_to_desc(irq);
2466
2467         set_ir_ioapic_affinity_irq_desc(desc, mask);
2468 }
2469 #endif
2470
2471 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2472 {
2473         unsigned vector, me;
2474
2475         ack_APIC_irq();
2476         exit_idle();
2477         irq_enter();
2478
2479         me = smp_processor_id();
2480         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2481                 unsigned int irq;
2482                 struct irq_desc *desc;
2483                 struct irq_cfg *cfg;
2484                 irq = __get_cpu_var(vector_irq)[vector];
2485
2486                 if (irq == -1)
2487                         continue;
2488
2489                 desc = irq_to_desc(irq);
2490                 if (!desc)
2491                         continue;
2492
2493                 cfg = irq_cfg(irq);
2494                 spin_lock(&desc->lock);
2495                 if (!cfg->move_cleanup_count)
2496                         goto unlock;
2497
2498                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2499                         goto unlock;
2500
2501                 __get_cpu_var(vector_irq)[vector] = -1;
2502                 cfg->move_cleanup_count--;
2503 unlock:
2504                 spin_unlock(&desc->lock);
2505         }
2506
2507         irq_exit();
2508 }
2509
2510 static void irq_complete_move(struct irq_desc **descp)
2511 {
2512         struct irq_desc *desc = *descp;
2513         struct irq_cfg *cfg = desc->chip_data;
2514         unsigned vector, me;
2515
2516         if (likely(!cfg->move_in_progress)) {
2517 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2518                 if (likely(!cfg->move_desc_pending))
2519                         return;
2520
2521                 /* domain has not changed, but affinity did */
2522                 me = smp_processor_id();
2523                 if (cpumask_test_cpu(me, desc->affinity)) {
2524                         *descp = desc = move_irq_desc(desc, me);
2525                         /* get the new one */
2526                         cfg = desc->chip_data;
2527                         cfg->move_desc_pending = 0;
2528                 }
2529 #endif
2530                 return;
2531         }
2532
2533         vector = ~get_irq_regs()->orig_ax;
2534         me = smp_processor_id();
2535 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2536                 *descp = desc = move_irq_desc(desc, me);
2537                 /* get the new one */
2538                 cfg = desc->chip_data;
2539 #endif
2540
2541         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2542                 send_cleanup_vector(cfg);
2543 }
2544 #else
2545 static inline void irq_complete_move(struct irq_desc **descp) {}
2546 #endif
2547
2548 #ifdef CONFIG_INTR_REMAP
2549 static void ack_x2apic_level(unsigned int irq)
2550 {
2551         ack_x2APIC_irq();
2552 }
2553
2554 static void ack_x2apic_edge(unsigned int irq)
2555 {
2556         ack_x2APIC_irq();
2557 }
2558
2559 #endif
2560
2561 static void ack_apic_edge(unsigned int irq)
2562 {
2563         struct irq_desc *desc = irq_to_desc(irq);
2564
2565         irq_complete_move(&desc);
2566         move_native_irq(irq);
2567         ack_APIC_irq();
2568 }
2569
2570 atomic_t irq_mis_count;
2571
2572 static void ack_apic_level(unsigned int irq)
2573 {
2574         struct irq_desc *desc = irq_to_desc(irq);
2575
2576 #ifdef CONFIG_X86_32
2577         unsigned long v;
2578         int i;
2579 #endif
2580         struct irq_cfg *cfg;
2581         int do_unmask_irq = 0;
2582
2583         irq_complete_move(&desc);
2584 #ifdef CONFIG_GENERIC_PENDING_IRQ
2585         /* If we are moving the irq we need to mask it */
2586         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2587                 do_unmask_irq = 1;
2588                 mask_IO_APIC_irq_desc(desc);
2589         }
2590 #endif
2591
2592 #ifdef CONFIG_X86_32
2593         /*
2594         * It appears there is an erratum which affects at least version 0x11
2595         * of I/O APIC (that's the 82093AA and cores integrated into various
2596         * chipsets).  Under certain conditions a level-triggered interrupt is
2597         * erroneously delivered as edge-triggered one but the respective IRR
2598         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2599         * message but it will never arrive and further interrupts are blocked
2600         * from the source.  The exact reason is so far unknown, but the
2601         * phenomenon was observed when two consecutive interrupt requests
2602         * from a given source get delivered to the same CPU and the source is
2603         * temporarily disabled in between.
2604         *
2605         * A workaround is to simulate an EOI message manually.  We achieve it
2606         * by setting the trigger mode to edge and then to level when the edge
2607         * trigger mode gets detected in the TMR of a local APIC for a
2608         * level-triggered interrupt.  We mask the source for the time of the
2609         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2610         * The idea is from Manfred Spraul.  --macro
2611         */
2612         cfg = desc->chip_data;
2613         i = cfg->vector;
2614
2615         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2616 #endif
2617
2618         /*
2619          * We must acknowledge the irq before we move it or the acknowledge will
2620          * not propagate properly.
2621          */
2622         ack_APIC_irq();
2623
2624         /* Now we can move and renable the irq */
2625         if (unlikely(do_unmask_irq)) {
2626                 /* Only migrate the irq if the ack has been received.
2627                  *
2628                  * On rare occasions the broadcast level triggered ack gets
2629                  * delayed going to ioapics, and if we reprogram the
2630                  * vector while Remote IRR is still set the irq will never
2631                  * fire again.
2632                  *
2633                  * To prevent this scenario we read the Remote IRR bit
2634                  * of the ioapic.  This has two effects.
2635                  * - On any sane system the read of the ioapic will
2636                  *   flush writes (and acks) going to the ioapic from
2637                  *   this cpu.
2638                  * - We get to see if the ACK has actually been delivered.
2639                  *
2640                  * Based on failed experiments of reprogramming the
2641                  * ioapic entry from outside of irq context starting
2642                  * with masking the ioapic entry and then polling until
2643                  * Remote IRR was clear before reprogramming the
2644                  * ioapic I don't trust the Remote IRR bit to be
2645                  * completey accurate.
2646                  *
2647                  * However there appears to be no other way to plug
2648                  * this race, so if the Remote IRR bit is not
2649                  * accurate and is causing problems then it is a hardware bug
2650                  * and you can go talk to the chipset vendor about it.
2651                  */
2652                 cfg = desc->chip_data;
2653                 if (!io_apic_level_ack_pending(cfg))
2654                         move_masked_irq(irq);
2655                 unmask_IO_APIC_irq_desc(desc);
2656         }
2657
2658 #ifdef CONFIG_X86_32
2659         if (!(v & (1 << (i & 0x1f)))) {
2660                 atomic_inc(&irq_mis_count);
2661                 spin_lock(&ioapic_lock);
2662                 __mask_and_edge_IO_APIC_irq(cfg);
2663                 __unmask_and_level_IO_APIC_irq(cfg);
2664                 spin_unlock(&ioapic_lock);
2665         }
2666 #endif
2667 }
2668
2669 static struct irq_chip ioapic_chip __read_mostly = {
2670         .name           = "IO-APIC",
2671         .startup        = startup_ioapic_irq,
2672         .mask           = mask_IO_APIC_irq,
2673         .unmask         = unmask_IO_APIC_irq,
2674         .ack            = ack_apic_edge,
2675         .eoi            = ack_apic_level,
2676 #ifdef CONFIG_SMP
2677         .set_affinity   = set_ioapic_affinity_irq,
2678 #endif
2679         .retrigger      = ioapic_retrigger_irq,
2680 };
2681
2682 #ifdef CONFIG_INTR_REMAP
2683 static struct irq_chip ir_ioapic_chip __read_mostly = {
2684         .name           = "IR-IO-APIC",
2685         .startup        = startup_ioapic_irq,
2686         .mask           = mask_IO_APIC_irq,
2687         .unmask         = unmask_IO_APIC_irq,
2688         .ack            = ack_x2apic_edge,
2689         .eoi            = ack_x2apic_level,
2690 #ifdef CONFIG_SMP
2691         .set_affinity   = set_ir_ioapic_affinity_irq,
2692 #endif
2693         .retrigger      = ioapic_retrigger_irq,
2694 };
2695 #endif
2696
2697 static inline void init_IO_APIC_traps(void)
2698 {
2699         int irq;
2700         struct irq_desc *desc;
2701         struct irq_cfg *cfg;
2702
2703         /*
2704          * NOTE! The local APIC isn't very good at handling
2705          * multiple interrupts at the same interrupt level.
2706          * As the interrupt level is determined by taking the
2707          * vector number and shifting that right by 4, we
2708          * want to spread these out a bit so that they don't
2709          * all fall in the same interrupt level.
2710          *
2711          * Also, we've got to be careful not to trash gate
2712          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2713          */
2714         for_each_irq_desc(irq, desc) {
2715                 cfg = desc->chip_data;
2716                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2717                         /*
2718                          * Hmm.. We don't have an entry for this,
2719                          * so default to an old-fashioned 8259
2720                          * interrupt if we can..
2721                          */
2722                         if (irq < NR_IRQS_LEGACY)
2723                                 make_8259A_irq(irq);
2724                         else
2725                                 /* Strange. Oh, well.. */
2726                                 desc->chip = &no_irq_chip;
2727                 }
2728         }
2729 }
2730
2731 /*
2732  * The local APIC irq-chip implementation:
2733  */
2734
2735 static void mask_lapic_irq(unsigned int irq)
2736 {
2737         unsigned long v;
2738
2739         v = apic_read(APIC_LVT0);
2740         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2741 }
2742
2743 static void unmask_lapic_irq(unsigned int irq)
2744 {
2745         unsigned long v;
2746
2747         v = apic_read(APIC_LVT0);
2748         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2749 }
2750
2751 static void ack_lapic_irq(unsigned int irq)
2752 {
2753         ack_APIC_irq();
2754 }
2755
2756 static struct irq_chip lapic_chip __read_mostly = {
2757         .name           = "local-APIC",
2758         .mask           = mask_lapic_irq,
2759         .unmask         = unmask_lapic_irq,
2760         .ack            = ack_lapic_irq,
2761 };
2762
2763 static void lapic_register_intr(int irq, struct irq_desc *desc)
2764 {
2765         desc->status &= ~IRQ_LEVEL;
2766         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2767                                       "edge");
2768 }
2769
2770 static void __init setup_nmi(void)
2771 {
2772         /*
2773          * Dirty trick to enable the NMI watchdog ...
2774          * We put the 8259A master into AEOI mode and
2775          * unmask on all local APICs LVT0 as NMI.
2776          *
2777          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2778          * is from Maciej W. Rozycki - so we do not have to EOI from
2779          * the NMI handler or the timer interrupt.
2780          */
2781         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2782
2783         enable_NMI_through_LVT0();
2784
2785         apic_printk(APIC_VERBOSE, " done.\n");
2786 }
2787
2788 /*
2789  * This looks a bit hackish but it's about the only one way of sending
2790  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2791  * not support the ExtINT mode, unfortunately.  We need to send these
2792  * cycles as some i82489DX-based boards have glue logic that keeps the
2793  * 8259A interrupt line asserted until INTA.  --macro
2794  */
2795 static inline void __init unlock_ExtINT_logic(void)
2796 {
2797         int apic, pin, i;
2798         struct IO_APIC_route_entry entry0, entry1;
2799         unsigned char save_control, save_freq_select;
2800
2801         pin  = find_isa_irq_pin(8, mp_INT);
2802         if (pin == -1) {
2803                 WARN_ON_ONCE(1);
2804                 return;
2805         }
2806         apic = find_isa_irq_apic(8, mp_INT);
2807         if (apic == -1) {
2808                 WARN_ON_ONCE(1);
2809                 return;
2810         }
2811
2812         entry0 = ioapic_read_entry(apic, pin);
2813         clear_IO_APIC_pin(apic, pin);
2814
2815         memset(&entry1, 0, sizeof(entry1));
2816
2817         entry1.dest_mode = 0;                   /* physical delivery */
2818         entry1.mask = 0;                        /* unmask IRQ now */
2819         entry1.dest = hard_smp_processor_id();
2820         entry1.delivery_mode = dest_ExtINT;
2821         entry1.polarity = entry0.polarity;
2822         entry1.trigger = 0;
2823         entry1.vector = 0;
2824
2825         ioapic_write_entry(apic, pin, entry1);
2826
2827         save_control = CMOS_READ(RTC_CONTROL);
2828         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2829         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2830                    RTC_FREQ_SELECT);
2831         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2832
2833         i = 100;
2834         while (i-- > 0) {
2835                 mdelay(10);
2836                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2837                         i -= 10;
2838         }
2839
2840         CMOS_WRITE(save_control, RTC_CONTROL);
2841         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2842         clear_IO_APIC_pin(apic, pin);
2843
2844         ioapic_write_entry(apic, pin, entry0);
2845 }
2846
2847 static int disable_timer_pin_1 __initdata;
2848 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2849 static int __init disable_timer_pin_setup(char *arg)
2850 {
2851         disable_timer_pin_1 = 1;
2852         return 0;
2853 }
2854 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2855
2856 int timer_through_8259 __initdata;
2857
2858 /*
2859  * This code may look a bit paranoid, but it's supposed to cooperate with
2860  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2861  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2862  * fanatically on his truly buggy board.
2863  *
2864  * FIXME: really need to revamp this for all platforms.
2865  */
2866 static inline void __init check_timer(void)
2867 {
2868         struct irq_desc *desc = irq_to_desc(0);
2869         struct irq_cfg *cfg = desc->chip_data;
2870         int cpu = boot_cpu_id;
2871         int apic1, pin1, apic2, pin2;
2872         unsigned long flags;
2873         unsigned int ver;
2874         int no_pin1 = 0;
2875
2876         local_irq_save(flags);
2877
2878         ver = apic_read(APIC_LVR);
2879         ver = GET_APIC_VERSION(ver);
2880
2881         /*
2882          * get/set the timer IRQ vector:
2883          */
2884         disable_8259A_irq(0);
2885         assign_irq_vector(0, cfg, apic->target_cpus());
2886
2887         /*
2888          * As IRQ0 is to be enabled in the 8259A, the virtual
2889          * wire has to be disabled in the local APIC.  Also
2890          * timer interrupts need to be acknowledged manually in
2891          * the 8259A for the i82489DX when using the NMI
2892          * watchdog as that APIC treats NMIs as level-triggered.
2893          * The AEOI mode will finish them in the 8259A
2894          * automatically.
2895          */
2896         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2897         init_8259A(1);
2898 #ifdef CONFIG_X86_32
2899         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2900 #endif
2901
2902         pin1  = find_isa_irq_pin(0, mp_INT);
2903         apic1 = find_isa_irq_apic(0, mp_INT);
2904         pin2  = ioapic_i8259.pin;
2905         apic2 = ioapic_i8259.apic;
2906
2907         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2908                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2909                     cfg->vector, apic1, pin1, apic2, pin2);
2910
2911         /*
2912          * Some BIOS writers are clueless and report the ExtINTA
2913          * I/O APIC input from the cascaded 8259A as the timer
2914          * interrupt input.  So just in case, if only one pin
2915          * was found above, try it both directly and through the
2916          * 8259A.
2917          */
2918         if (pin1 == -1) {
2919 #ifdef CONFIG_INTR_REMAP
2920                 if (intr_remapping_enabled)
2921                         panic("BIOS bug: timer not connected to IO-APIC");
2922 #endif
2923                 pin1 = pin2;
2924                 apic1 = apic2;
2925                 no_pin1 = 1;
2926         } else if (pin2 == -1) {
2927                 pin2 = pin1;
2928                 apic2 = apic1;
2929         }
2930
2931         if (pin1 != -1) {
2932                 /*
2933                  * Ok, does IRQ0 through the IOAPIC work?
2934                  */
2935                 if (no_pin1) {
2936                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2937                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2938                 }
2939                 unmask_IO_APIC_irq_desc(desc);
2940                 if (timer_irq_works()) {
2941                         if (nmi_watchdog == NMI_IO_APIC) {
2942                                 setup_nmi();
2943                                 enable_8259A_irq(0);
2944                         }
2945                         if (disable_timer_pin_1 > 0)
2946                                 clear_IO_APIC_pin(0, pin1);
2947                         goto out;
2948                 }
2949 #ifdef CONFIG_INTR_REMAP
2950                 if (intr_remapping_enabled)
2951                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2952 #endif
2953                 clear_IO_APIC_pin(apic1, pin1);
2954                 if (!no_pin1)
2955                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2956                                     "8254 timer not connected to IO-APIC\n");
2957
2958                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2959                             "(IRQ0) through the 8259A ...\n");
2960                 apic_printk(APIC_QUIET, KERN_INFO
2961                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2962                 /*
2963                  * legacy devices should be connected to IO APIC #0
2964                  */
2965                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2966                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2967                 unmask_IO_APIC_irq_desc(desc);
2968                 enable_8259A_irq(0);
2969                 if (timer_irq_works()) {
2970                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2971                         timer_through_8259 = 1;
2972                         if (nmi_watchdog == NMI_IO_APIC) {
2973                                 disable_8259A_irq(0);
2974                                 setup_nmi();
2975                                 enable_8259A_irq(0);
2976                         }
2977                         goto out;
2978                 }
2979                 /*
2980                  * Cleanup, just in case ...
2981                  */
2982                 disable_8259A_irq(0);
2983                 clear_IO_APIC_pin(apic2, pin2);
2984                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2985         }
2986
2987         if (nmi_watchdog == NMI_IO_APIC) {
2988                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2989                             "through the IO-APIC - disabling NMI Watchdog!\n");
2990                 nmi_watchdog = NMI_NONE;
2991         }
2992 #ifdef CONFIG_X86_32
2993         timer_ack = 0;
2994 #endif
2995
2996         apic_printk(APIC_QUIET, KERN_INFO
2997                     "...trying to set up timer as Virtual Wire IRQ...\n");
2998
2999         lapic_register_intr(0, desc);
3000         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
3001         enable_8259A_irq(0);
3002
3003         if (timer_irq_works()) {
3004                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3005                 goto out;
3006         }
3007         disable_8259A_irq(0);
3008         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3009         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3010
3011         apic_printk(APIC_QUIET, KERN_INFO
3012                     "...trying to set up timer as ExtINT IRQ...\n");
3013
3014         init_8259A(0);
3015         make_8259A_irq(0);
3016         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3017
3018         unlock_ExtINT_logic();
3019
3020         if (timer_irq_works()) {
3021                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3022                 goto out;
3023         }
3024         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3025         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3026                 "report.  Then try booting with the 'noapic' option.\n");
3027 out:
3028         local_irq_restore(flags);
3029 }
3030
3031 /*
3032  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3033  * to devices.  However there may be an I/O APIC pin available for
3034  * this interrupt regardless.  The pin may be left unconnected, but
3035  * typically it will be reused as an ExtINT cascade interrupt for
3036  * the master 8259A.  In the MPS case such a pin will normally be
3037  * reported as an ExtINT interrupt in the MP table.  With ACPI
3038  * there is no provision for ExtINT interrupts, and in the absence
3039  * of an override it would be treated as an ordinary ISA I/O APIC
3040  * interrupt, that is edge-triggered and unmasked by default.  We
3041  * used to do this, but it caused problems on some systems because
3042  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3043  * the same ExtINT cascade interrupt to drive the local APIC of the
3044  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3045  * the I/O APIC in all cases now.  No actual device should request
3046  * it anyway.  --macro
3047  */
3048 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3049
3050 void __init setup_IO_APIC(void)
3051 {
3052
3053 #ifdef CONFIG_X86_32
3054         enable_IO_APIC();
3055 #else
3056         /*
3057          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3058          */
3059 #endif
3060
3061         io_apic_irqs = ~PIC_IRQS;
3062
3063         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3064         /*
3065          * Set up IO-APIC IRQ routing.
3066          */
3067 #ifdef CONFIG_X86_32
3068         if (!acpi_ioapic)
3069                 setup_ioapic_ids_from_mpc();
3070 #endif
3071         sync_Arb_IDs();
3072         setup_IO_APIC_irqs();
3073         init_IO_APIC_traps();
3074         check_timer();
3075 }
3076
3077 /*
3078  *      Called after all the initialization is done. If we didnt find any
3079  *      APIC bugs then we can allow the modify fast path
3080  */
3081
3082 static int __init io_apic_bug_finalize(void)
3083 {
3084         if (sis_apic_bug == -1)
3085                 sis_apic_bug = 0;
3086         return 0;
3087 }
3088
3089 late_initcall(io_apic_bug_finalize);
3090
3091 struct sysfs_ioapic_data {
3092         struct sys_device dev;
3093         struct IO_APIC_route_entry entry[0];
3094 };
3095 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3096
3097 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3098 {
3099         struct IO_APIC_route_entry *entry;
3100         struct sysfs_ioapic_data *data;
3101         int i;
3102
3103         data = container_of(dev, struct sysfs_ioapic_data, dev);
3104         entry = data->entry;
3105         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3106                 *entry = ioapic_read_entry(dev->id, i);
3107
3108         return 0;
3109 }
3110
3111 static int ioapic_resume(struct sys_device *dev)
3112 {
3113         struct IO_APIC_route_entry *entry;
3114         struct sysfs_ioapic_data *data;
3115         unsigned long flags;
3116         union IO_APIC_reg_00 reg_00;
3117         int i;
3118
3119         data = container_of(dev, struct sysfs_ioapic_data, dev);
3120         entry = data->entry;
3121
3122         spin_lock_irqsave(&ioapic_lock, flags);
3123         reg_00.raw = io_apic_read(dev->id, 0);
3124         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3125                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3126                 io_apic_write(dev->id, 0, reg_00.raw);
3127         }
3128         spin_unlock_irqrestore(&ioapic_lock, flags);
3129         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3130                 ioapic_write_entry(dev->id, i, entry[i]);
3131
3132         return 0;
3133 }
3134
3135 static struct sysdev_class ioapic_sysdev_class = {
3136         .name = "ioapic",
3137         .suspend = ioapic_suspend,
3138         .resume = ioapic_resume,
3139 };
3140
3141 static int __init ioapic_init_sysfs(void)
3142 {
3143         struct sys_device * dev;
3144         int i, size, error;
3145
3146         error = sysdev_class_register(&ioapic_sysdev_class);
3147         if (error)
3148                 return error;
3149
3150         for (i = 0; i < nr_ioapics; i++ ) {
3151                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3152                         * sizeof(struct IO_APIC_route_entry);
3153                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3154                 if (!mp_ioapic_data[i]) {
3155                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3156                         continue;
3157                 }
3158                 dev = &mp_ioapic_data[i]->dev;
3159                 dev->id = i;
3160                 dev->cls = &ioapic_sysdev_class;
3161                 error = sysdev_register(dev);
3162                 if (error) {
3163                         kfree(mp_ioapic_data[i]);
3164                         mp_ioapic_data[i] = NULL;
3165                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3166                         continue;
3167                 }
3168         }
3169
3170         return 0;
3171 }
3172
3173 device_initcall(ioapic_init_sysfs);
3174
3175 /*
3176  * Dynamic irq allocate and deallocation
3177  */
3178 unsigned int create_irq_nr(unsigned int irq_want)
3179 {
3180         /* Allocate an unused irq */
3181         unsigned int irq;
3182         unsigned int new;
3183         unsigned long flags;
3184         struct irq_cfg *cfg_new = NULL;
3185         int cpu = boot_cpu_id;
3186         struct irq_desc *desc_new = NULL;
3187
3188         irq = 0;
3189         spin_lock_irqsave(&vector_lock, flags);
3190         for (new = irq_want; new < nr_irqs; new++) {
3191                 if (platform_legacy_irq(new))
3192                         continue;
3193
3194                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3195                 if (!desc_new) {
3196                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3197                         continue;
3198                 }
3199                 cfg_new = desc_new->chip_data;
3200
3201                 if (cfg_new->vector != 0)
3202                         continue;
3203                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3204                         irq = new;
3205                 break;
3206         }
3207         spin_unlock_irqrestore(&vector_lock, flags);
3208
3209         if (irq > 0) {
3210                 dynamic_irq_init(irq);
3211                 /* restore it, in case dynamic_irq_init clear it */
3212                 if (desc_new)
3213                         desc_new->chip_data = cfg_new;
3214         }
3215         return irq;
3216 }
3217
3218 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3219 int create_irq(void)
3220 {
3221         unsigned int irq_want;
3222         int irq;
3223
3224         irq_want = nr_irqs_gsi;
3225         irq = create_irq_nr(irq_want);
3226
3227         if (irq == 0)
3228                 irq = -1;
3229
3230         return irq;
3231 }
3232
3233 void destroy_irq(unsigned int irq)
3234 {
3235         unsigned long flags;
3236         struct irq_cfg *cfg;
3237         struct irq_desc *desc;
3238
3239         /* store it, in case dynamic_irq_cleanup clear it */
3240         desc = irq_to_desc(irq);
3241         cfg = desc->chip_data;
3242         dynamic_irq_cleanup(irq);
3243         /* connect back irq_cfg */
3244         if (desc)
3245                 desc->chip_data = cfg;
3246
3247 #ifdef CONFIG_INTR_REMAP
3248         free_irte(irq);
3249 #endif
3250         spin_lock_irqsave(&vector_lock, flags);
3251         __clear_irq_vector(irq, cfg);
3252         spin_unlock_irqrestore(&vector_lock, flags);
3253 }
3254
3255 /*
3256  * MSI message composition
3257  */
3258 #ifdef CONFIG_PCI_MSI
3259 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3260 {
3261         struct irq_cfg *cfg;
3262         int err;
3263         unsigned dest;
3264
3265         if (disable_apic)
3266                 return -ENXIO;
3267
3268         cfg = irq_cfg(irq);
3269         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3270         if (err)
3271                 return err;
3272
3273         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3274
3275 #ifdef CONFIG_INTR_REMAP
3276         if (irq_remapped(irq)) {
3277                 struct irte irte;
3278                 int ir_index;
3279                 u16 sub_handle;
3280
3281                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3282                 BUG_ON(ir_index == -1);
3283
3284                 memset (&irte, 0, sizeof(irte));
3285
3286                 irte.present = 1;
3287                 irte.dst_mode = apic->irq_dest_mode;
3288                 irte.trigger_mode = 0; /* edge */
3289                 irte.dlvry_mode = apic->irq_delivery_mode;
3290                 irte.vector = cfg->vector;
3291                 irte.dest_id = IRTE_DEST(dest);
3292
3293                 modify_irte(irq, &irte);
3294
3295                 msg->address_hi = MSI_ADDR_BASE_HI;
3296                 msg->data = sub_handle;
3297                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3298                                   MSI_ADDR_IR_SHV |
3299                                   MSI_ADDR_IR_INDEX1(ir_index) |
3300                                   MSI_ADDR_IR_INDEX2(ir_index);
3301         } else
3302 #endif
3303         {
3304                 msg->address_hi = MSI_ADDR_BASE_HI;
3305                 msg->address_lo =
3306                         MSI_ADDR_BASE_LO |
3307                         ((apic->irq_dest_mode == 0) ?
3308                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3309                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3310                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3311                                 MSI_ADDR_REDIRECTION_CPU:
3312                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3313                         MSI_ADDR_DEST_ID(dest);
3314
3315                 msg->data =
3316                         MSI_DATA_TRIGGER_EDGE |
3317                         MSI_DATA_LEVEL_ASSERT |
3318                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3319                                 MSI_DATA_DELIVERY_FIXED:
3320                                 MSI_DATA_DELIVERY_LOWPRI) |
3321                         MSI_DATA_VECTOR(cfg->vector);
3322         }
3323         return err;
3324 }
3325
3326 #ifdef CONFIG_SMP
3327 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3328 {
3329         struct irq_desc *desc = irq_to_desc(irq);
3330         struct irq_cfg *cfg;
3331         struct msi_msg msg;
3332         unsigned int dest;
3333
3334         dest = set_desc_affinity(desc, mask);
3335         if (dest == BAD_APICID)
3336                 return;
3337
3338         cfg = desc->chip_data;
3339
3340         read_msi_msg_desc(desc, &msg);
3341
3342         msg.data &= ~MSI_DATA_VECTOR_MASK;
3343         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3344         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3345         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3346
3347         write_msi_msg_desc(desc, &msg);
3348 }
3349 #ifdef CONFIG_INTR_REMAP
3350 /*
3351  * Migrate the MSI irq to another cpumask. This migration is
3352  * done in the process context using interrupt-remapping hardware.
3353  */
3354 static void
3355 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3356 {
3357         struct irq_desc *desc = irq_to_desc(irq);
3358         struct irq_cfg *cfg = desc->chip_data;
3359         unsigned int dest;
3360         struct irte irte;
3361
3362         if (get_irte(irq, &irte))
3363                 return;
3364
3365         dest = set_desc_affinity(desc, mask);
3366         if (dest == BAD_APICID)
3367                 return;
3368
3369         irte.vector = cfg->vector;
3370         irte.dest_id = IRTE_DEST(dest);
3371
3372         /*
3373          * atomically update the IRTE with the new destination and vector.
3374          */
3375         modify_irte(irq, &irte);
3376
3377         /*
3378          * After this point, all the interrupts will start arriving
3379          * at the new destination. So, time to cleanup the previous
3380          * vector allocation.
3381          */
3382         if (cfg->move_in_progress)
3383                 send_cleanup_vector(cfg);
3384 }
3385
3386 #endif
3387 #endif /* CONFIG_SMP */
3388
3389 /*
3390  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3391  * which implement the MSI or MSI-X Capability Structure.
3392  */
3393 static struct irq_chip msi_chip = {
3394         .name           = "PCI-MSI",
3395         .unmask         = unmask_msi_irq,
3396         .mask           = mask_msi_irq,
3397         .ack            = ack_apic_edge,
3398 #ifdef CONFIG_SMP
3399         .set_affinity   = set_msi_irq_affinity,
3400 #endif
3401         .retrigger      = ioapic_retrigger_irq,
3402 };
3403
3404 #ifdef CONFIG_INTR_REMAP
3405 static struct irq_chip msi_ir_chip = {
3406         .name           = "IR-PCI-MSI",
3407         .unmask         = unmask_msi_irq,
3408         .mask           = mask_msi_irq,
3409         .ack            = ack_x2apic_edge,
3410 #ifdef CONFIG_SMP
3411         .set_affinity   = ir_set_msi_irq_affinity,
3412 #endif
3413         .retrigger      = ioapic_retrigger_irq,
3414 };
3415
3416 /*
3417  * Map the PCI dev to the corresponding remapping hardware unit
3418  * and allocate 'nvec' consecutive interrupt-remapping table entries
3419  * in it.
3420  */
3421 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3422 {
3423         struct intel_iommu *iommu;
3424         int index;
3425
3426         iommu = map_dev_to_ir(dev);
3427         if (!iommu) {
3428                 printk(KERN_ERR
3429                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3430                 return -ENOENT;
3431         }
3432
3433         index = alloc_irte(iommu, irq, nvec);
3434         if (index < 0) {
3435                 printk(KERN_ERR
3436                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3437                        pci_name(dev));
3438                 return -ENOSPC;
3439         }
3440         return index;
3441 }
3442 #endif
3443
3444 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3445 {
3446         int ret;
3447         struct msi_msg msg;
3448
3449         ret = msi_compose_msg(dev, irq, &msg);
3450         if (ret < 0)
3451                 return ret;
3452
3453         set_irq_msi(irq, msidesc);
3454         write_msi_msg(irq, &msg);
3455
3456 #ifdef CONFIG_INTR_REMAP
3457         if (irq_remapped(irq)) {
3458                 struct irq_desc *desc = irq_to_desc(irq);
3459                 /*
3460                  * irq migration in process context
3461                  */
3462                 desc->status |= IRQ_MOVE_PCNTXT;
3463                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3464         } else
3465 #endif
3466                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3467
3468         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3469
3470         return 0;
3471 }
3472
3473 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3474 {
3475         unsigned int irq;
3476         int ret, sub_handle;
3477         struct msi_desc *msidesc;
3478         unsigned int irq_want;
3479
3480 #ifdef CONFIG_INTR_REMAP
3481         struct intel_iommu *iommu = 0;
3482         int index = 0;
3483 #endif
3484
3485         irq_want = nr_irqs_gsi;
3486         sub_handle = 0;
3487         list_for_each_entry(msidesc, &dev->msi_list, list) {
3488                 irq = create_irq_nr(irq_want);
3489                 irq_want++;
3490                 if (irq == 0)
3491                         return -1;
3492 #ifdef CONFIG_INTR_REMAP
3493                 if (!intr_remapping_enabled)
3494                         goto no_ir;
3495
3496                 if (!sub_handle) {
3497                         /*
3498                          * allocate the consecutive block of IRTE's
3499                          * for 'nvec'
3500                          */
3501                         index = msi_alloc_irte(dev, irq, nvec);
3502                         if (index < 0) {
3503                                 ret = index;
3504                                 goto error;
3505                         }
3506                 } else {
3507                         iommu = map_dev_to_ir(dev);
3508                         if (!iommu) {
3509                                 ret = -ENOENT;
3510                                 goto error;
3511                         }
3512                         /*
3513                          * setup the mapping between the irq and the IRTE
3514                          * base index, the sub_handle pointing to the
3515                          * appropriate interrupt remap table entry.
3516                          */
3517                         set_irte_irq(irq, iommu, index, sub_handle);
3518                 }
3519 no_ir:
3520 #endif
3521                 ret = setup_msi_irq(dev, msidesc, irq);
3522                 if (ret < 0)
3523                         goto error;
3524                 sub_handle++;
3525         }
3526         return 0;
3527
3528 error:
3529         destroy_irq(irq);
3530         return ret;
3531 }
3532
3533 void arch_teardown_msi_irq(unsigned int irq)
3534 {
3535         destroy_irq(irq);
3536 }
3537
3538 #ifdef CONFIG_DMAR
3539 #ifdef CONFIG_SMP
3540 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3541 {
3542         struct irq_desc *desc = irq_to_desc(irq);
3543         struct irq_cfg *cfg;
3544         struct msi_msg msg;
3545         unsigned int dest;
3546
3547         dest = set_desc_affinity(desc, mask);
3548         if (dest == BAD_APICID)
3549                 return;
3550
3551         cfg = desc->chip_data;
3552
3553         dmar_msi_read(irq, &msg);
3554
3555         msg.data &= ~MSI_DATA_VECTOR_MASK;
3556         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3557         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3558         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3559
3560         dmar_msi_write(irq, &msg);
3561 }
3562
3563 #endif /* CONFIG_SMP */
3564
3565 struct irq_chip dmar_msi_type = {
3566         .name = "DMAR_MSI",
3567         .unmask = dmar_msi_unmask,
3568         .mask = dmar_msi_mask,
3569         .ack = ack_apic_edge,
3570 #ifdef CONFIG_SMP
3571         .set_affinity = dmar_msi_set_affinity,
3572 #endif
3573         .retrigger = ioapic_retrigger_irq,
3574 };
3575
3576 int arch_setup_dmar_msi(unsigned int irq)
3577 {
3578         int ret;
3579         struct msi_msg msg;
3580
3581         ret = msi_compose_msg(NULL, irq, &msg);
3582         if (ret < 0)
3583                 return ret;
3584         dmar_msi_write(irq, &msg);
3585         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3586                 "edge");
3587         return 0;
3588 }
3589 #endif
3590
3591 #ifdef CONFIG_HPET_TIMER
3592
3593 #ifdef CONFIG_SMP
3594 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3595 {
3596         struct irq_desc *desc = irq_to_desc(irq);
3597         struct irq_cfg *cfg;
3598         struct msi_msg msg;
3599         unsigned int dest;
3600
3601         dest = set_desc_affinity(desc, mask);
3602         if (dest == BAD_APICID)
3603                 return;
3604
3605         cfg = desc->chip_data;
3606
3607         hpet_msi_read(irq, &msg);
3608
3609         msg.data &= ~MSI_DATA_VECTOR_MASK;
3610         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3611         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3612         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3613
3614         hpet_msi_write(irq, &msg);
3615 }
3616
3617 #endif /* CONFIG_SMP */
3618
3619 struct irq_chip hpet_msi_type = {
3620         .name = "HPET_MSI",
3621         .unmask = hpet_msi_unmask,
3622         .mask = hpet_msi_mask,
3623         .ack = ack_apic_edge,
3624 #ifdef CONFIG_SMP
3625         .set_affinity = hpet_msi_set_affinity,
3626 #endif
3627         .retrigger = ioapic_retrigger_irq,
3628 };
3629
3630 int arch_setup_hpet_msi(unsigned int irq)
3631 {
3632         int ret;
3633         struct msi_msg msg;
3634
3635         ret = msi_compose_msg(NULL, irq, &msg);
3636         if (ret < 0)
3637                 return ret;
3638
3639         hpet_msi_write(irq, &msg);
3640         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3641                 "edge");
3642
3643         return 0;
3644 }
3645 #endif
3646
3647 #endif /* CONFIG_PCI_MSI */
3648 /*
3649  * Hypertransport interrupt support
3650  */
3651 #ifdef CONFIG_HT_IRQ
3652
3653 #ifdef CONFIG_SMP
3654
3655 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3656 {
3657         struct ht_irq_msg msg;
3658         fetch_ht_irq_msg(irq, &msg);
3659
3660         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3661         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3662
3663         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3664         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3665
3666         write_ht_irq_msg(irq, &msg);
3667 }
3668
3669 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3670 {
3671         struct irq_desc *desc = irq_to_desc(irq);
3672         struct irq_cfg *cfg;
3673         unsigned int dest;
3674
3675         dest = set_desc_affinity(desc, mask);
3676         if (dest == BAD_APICID)
3677                 return;
3678
3679         cfg = desc->chip_data;
3680
3681         target_ht_irq(irq, dest, cfg->vector);
3682 }
3683
3684 #endif
3685
3686 static struct irq_chip ht_irq_chip = {
3687         .name           = "PCI-HT",
3688         .mask           = mask_ht_irq,
3689         .unmask         = unmask_ht_irq,
3690         .ack            = ack_apic_edge,
3691 #ifdef CONFIG_SMP
3692         .set_affinity   = set_ht_irq_affinity,
3693 #endif
3694         .retrigger      = ioapic_retrigger_irq,
3695 };
3696
3697 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3698 {
3699         struct irq_cfg *cfg;
3700         int err;
3701
3702         if (disable_apic)
3703                 return -ENXIO;
3704
3705         cfg = irq_cfg(irq);
3706         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3707         if (!err) {
3708                 struct ht_irq_msg msg;
3709                 unsigned dest;
3710
3711                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3712                                                     apic->target_cpus());
3713
3714                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3715
3716                 msg.address_lo =
3717                         HT_IRQ_LOW_BASE |
3718                         HT_IRQ_LOW_DEST_ID(dest) |
3719                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3720                         ((apic->irq_dest_mode == 0) ?
3721                                 HT_IRQ_LOW_DM_PHYSICAL :
3722                                 HT_IRQ_LOW_DM_LOGICAL) |
3723                         HT_IRQ_LOW_RQEOI_EDGE |
3724                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3725                                 HT_IRQ_LOW_MT_FIXED :
3726                                 HT_IRQ_LOW_MT_ARBITRATED) |
3727                         HT_IRQ_LOW_IRQ_MASKED;
3728
3729                 write_ht_irq_msg(irq, &msg);
3730
3731                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3732                                               handle_edge_irq, "edge");
3733
3734                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3735         }
3736         return err;
3737 }
3738 #endif /* CONFIG_HT_IRQ */
3739
3740 #ifdef CONFIG_X86_UV
3741 /*
3742  * Re-target the irq to the specified CPU and enable the specified MMR located
3743  * on the specified blade to allow the sending of MSIs to the specified CPU.
3744  */
3745 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3746                        unsigned long mmr_offset)
3747 {
3748         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3749         struct irq_cfg *cfg;
3750         int mmr_pnode;
3751         unsigned long mmr_value;
3752         struct uv_IO_APIC_route_entry *entry;
3753         unsigned long flags;
3754         int err;
3755
3756         cfg = irq_cfg(irq);
3757
3758         err = assign_irq_vector(irq, cfg, eligible_cpu);
3759         if (err != 0)
3760                 return err;
3761
3762         spin_lock_irqsave(&vector_lock, flags);
3763         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3764                                       irq_name);
3765         spin_unlock_irqrestore(&vector_lock, flags);
3766
3767         mmr_value = 0;
3768         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3769         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3770
3771         entry->vector = cfg->vector;
3772         entry->delivery_mode = apic->irq_delivery_mode;
3773         entry->dest_mode = apic->irq_dest_mode;
3774         entry->polarity = 0;
3775         entry->trigger = 0;
3776         entry->mask = 0;
3777         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3778
3779         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3780         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3781
3782         return irq;
3783 }
3784
3785 /*
3786  * Disable the specified MMR located on the specified blade so that MSIs are
3787  * longer allowed to be sent.
3788  */
3789 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3790 {
3791         unsigned long mmr_value;
3792         struct uv_IO_APIC_route_entry *entry;
3793         int mmr_pnode;
3794
3795         mmr_value = 0;
3796         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3797         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3798
3799         entry->mask = 1;
3800
3801         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3802         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3803 }
3804 #endif /* CONFIG_X86_64 */
3805
3806 int __init io_apic_get_redir_entries (int ioapic)
3807 {
3808         union IO_APIC_reg_01    reg_01;
3809         unsigned long flags;
3810
3811         spin_lock_irqsave(&ioapic_lock, flags);
3812         reg_01.raw = io_apic_read(ioapic, 1);
3813         spin_unlock_irqrestore(&ioapic_lock, flags);
3814
3815         return reg_01.bits.entries;
3816 }
3817
3818 void __init probe_nr_irqs_gsi(void)
3819 {
3820         int idx;
3821         int nr = 0;
3822
3823         for (idx = 0; idx < nr_ioapics; idx++)
3824                 nr += io_apic_get_redir_entries(idx) + 1;
3825
3826         if (nr > nr_irqs_gsi)
3827                 nr_irqs_gsi = nr;
3828 }
3829
3830 #ifdef CONFIG_SPARSE_IRQ
3831 int __init arch_probe_nr_irqs(void)
3832 {
3833         int nr;
3834
3835         nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ?
3836                 (NR_VECTORS + (8 * nr_cpu_ids)) :
3837                 (NR_VECTORS + (32 * nr_ioapics)));
3838
3839         if (nr < nr_irqs && nr > nr_irqs_gsi)
3840                 nr_irqs = nr;
3841
3842         return 0;
3843 }
3844 #endif
3845
3846 /* --------------------------------------------------------------------------
3847                           ACPI-based IOAPIC Configuration
3848    -------------------------------------------------------------------------- */
3849
3850 #ifdef CONFIG_ACPI
3851
3852 #ifdef CONFIG_X86_32
3853 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3854 {
3855         union IO_APIC_reg_00 reg_00;
3856         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3857         physid_mask_t tmp;
3858         unsigned long flags;
3859         int i = 0;
3860
3861         /*
3862          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3863          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3864          * supports up to 16 on one shared APIC bus.
3865          *
3866          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3867          *      advantage of new APIC bus architecture.
3868          */
3869
3870         if (physids_empty(apic_id_map))
3871                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3872
3873         spin_lock_irqsave(&ioapic_lock, flags);
3874         reg_00.raw = io_apic_read(ioapic, 0);
3875         spin_unlock_irqrestore(&ioapic_lock, flags);
3876
3877         if (apic_id >= get_physical_broadcast()) {
3878                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3879                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3880                 apic_id = reg_00.bits.ID;
3881         }
3882
3883         /*
3884          * Every APIC in a system must have a unique ID or we get lots of nice
3885          * 'stuck on smp_invalidate_needed IPI wait' messages.
3886          */
3887         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3888
3889                 for (i = 0; i < get_physical_broadcast(); i++) {
3890                         if (!apic->check_apicid_used(apic_id_map, i))
3891                                 break;
3892                 }
3893
3894                 if (i == get_physical_broadcast())
3895                         panic("Max apic_id exceeded!\n");
3896
3897                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3898                         "trying %d\n", ioapic, apic_id, i);
3899
3900                 apic_id = i;
3901         }
3902
3903         tmp = apic->apicid_to_cpu_present(apic_id);
3904         physids_or(apic_id_map, apic_id_map, tmp);
3905
3906         if (reg_00.bits.ID != apic_id) {
3907                 reg_00.bits.ID = apic_id;
3908
3909                 spin_lock_irqsave(&ioapic_lock, flags);
3910                 io_apic_write(ioapic, 0, reg_00.raw);
3911                 reg_00.raw = io_apic_read(ioapic, 0);
3912                 spin_unlock_irqrestore(&ioapic_lock, flags);
3913
3914                 /* Sanity check */
3915                 if (reg_00.bits.ID != apic_id) {
3916                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3917                         return -1;
3918                 }
3919         }
3920
3921         apic_printk(APIC_VERBOSE, KERN_INFO
3922                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3923
3924         return apic_id;
3925 }
3926
3927 int __init io_apic_get_version(int ioapic)
3928 {
3929         union IO_APIC_reg_01    reg_01;
3930         unsigned long flags;
3931
3932         spin_lock_irqsave(&ioapic_lock, flags);
3933         reg_01.raw = io_apic_read(ioapic, 1);
3934         spin_unlock_irqrestore(&ioapic_lock, flags);
3935
3936         return reg_01.bits.version;
3937 }
3938 #endif
3939
3940 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3941 {
3942         struct irq_desc *desc;
3943         struct irq_cfg *cfg;
3944         int cpu = boot_cpu_id;
3945
3946         if (!IO_APIC_IRQ(irq)) {
3947                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3948                         ioapic);
3949                 return -EINVAL;
3950         }
3951
3952         desc = irq_to_desc_alloc_cpu(irq, cpu);
3953         if (!desc) {
3954                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3955                 return 0;
3956         }
3957
3958         /*
3959          * IRQs < 16 are already in the irq_2_pin[] map
3960          */
3961         if (irq >= NR_IRQS_LEGACY) {
3962                 cfg = desc->chip_data;
3963                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3964         }
3965
3966         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3967
3968         return 0;
3969 }
3970
3971
3972 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3973 {
3974         int i;
3975
3976         if (skip_ioapic_setup)
3977                 return -1;
3978
3979         for (i = 0; i < mp_irq_entries; i++)
3980                 if (mp_irqs[i].irqtype == mp_INT &&
3981                     mp_irqs[i].srcbusirq == bus_irq)
3982                         break;
3983         if (i >= mp_irq_entries)
3984                 return -1;
3985
3986         *trigger = irq_trigger(i);
3987         *polarity = irq_polarity(i);
3988         return 0;
3989 }
3990
3991 #endif /* CONFIG_ACPI */
3992
3993 /*
3994  * This function currently is only a helper for the i386 smp boot process where
3995  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3996  * so mask in all cases should simply be apic->target_cpus()
3997  */
3998 #ifdef CONFIG_SMP
3999 void __init setup_ioapic_dest(void)
4000 {
4001         int pin, ioapic, irq, irq_entry;
4002         struct irq_desc *desc;
4003         struct irq_cfg *cfg;
4004         const struct cpumask *mask;
4005
4006         if (skip_ioapic_setup == 1)
4007                 return;
4008
4009         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4010                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4011                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4012                         if (irq_entry == -1)
4013                                 continue;
4014                         irq = pin_2_irq(irq_entry, ioapic, pin);
4015
4016                         /* setup_IO_APIC_irqs could fail to get vector for some device
4017                          * when you have too many devices, because at that time only boot
4018                          * cpu is online.
4019                          */
4020                         desc = irq_to_desc(irq);
4021                         cfg = desc->chip_data;
4022                         if (!cfg->vector) {
4023                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4024                                                   irq_trigger(irq_entry),
4025                                                   irq_polarity(irq_entry));
4026                                 continue;
4027
4028                         }
4029
4030                         /*
4031                          * Honour affinities which have been set in early boot
4032                          */
4033                         if (desc->status &
4034                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4035                                 mask = desc->affinity;
4036                         else
4037                                 mask = apic->target_cpus();
4038
4039 #ifdef CONFIG_INTR_REMAP
4040                         if (intr_remapping_enabled)
4041                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4042                         else
4043 #endif
4044                                 set_ioapic_affinity_irq_desc(desc, mask);
4045                 }
4046
4047         }
4048 }
4049 #endif
4050
4051 #define IOAPIC_RESOURCE_NAME_SIZE 11
4052
4053 static struct resource *ioapic_resources;
4054
4055 static struct resource * __init ioapic_setup_resources(void)
4056 {
4057         unsigned long n;
4058         struct resource *res;
4059         char *mem;
4060         int i;
4061
4062         if (nr_ioapics <= 0)
4063                 return NULL;
4064
4065         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4066         n *= nr_ioapics;
4067
4068         mem = alloc_bootmem(n);
4069         res = (void *)mem;
4070
4071         if (mem != NULL) {
4072                 mem += sizeof(struct resource) * nr_ioapics;
4073
4074                 for (i = 0; i < nr_ioapics; i++) {
4075                         res[i].name = mem;
4076                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4077                         sprintf(mem,  "IOAPIC %u", i);
4078                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4079                 }
4080         }
4081
4082         ioapic_resources = res;
4083
4084         return res;
4085 }
4086
4087 void __init ioapic_init_mappings(void)
4088 {
4089         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4090         struct resource *ioapic_res;
4091         int i;
4092
4093         ioapic_res = ioapic_setup_resources();
4094         for (i = 0; i < nr_ioapics; i++) {
4095                 if (smp_found_config) {
4096                         ioapic_phys = mp_ioapics[i].apicaddr;
4097 #ifdef CONFIG_X86_32
4098                         if (!ioapic_phys) {
4099                                 printk(KERN_ERR
4100                                        "WARNING: bogus zero IO-APIC "
4101                                        "address found in MPTABLE, "
4102                                        "disabling IO/APIC support!\n");
4103                                 smp_found_config = 0;
4104                                 skip_ioapic_setup = 1;
4105                                 goto fake_ioapic_page;
4106                         }
4107 #endif
4108                 } else {
4109 #ifdef CONFIG_X86_32
4110 fake_ioapic_page:
4111 #endif
4112                         ioapic_phys = (unsigned long)
4113                                 alloc_bootmem_pages(PAGE_SIZE);
4114                         ioapic_phys = __pa(ioapic_phys);
4115                 }
4116                 set_fixmap_nocache(idx, ioapic_phys);
4117                 apic_printk(APIC_VERBOSE,
4118                             "mapped IOAPIC to %08lx (%08lx)\n",
4119                             __fix_to_virt(idx), ioapic_phys);
4120                 idx++;
4121
4122                 if (ioapic_res != NULL) {
4123                         ioapic_res->start = ioapic_phys;
4124                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4125                         ioapic_res++;
4126                 }
4127         }
4128 }
4129
4130 static int __init ioapic_insert_resources(void)
4131 {
4132         int i;
4133         struct resource *r = ioapic_resources;
4134
4135         if (!r) {
4136                 printk(KERN_ERR
4137                        "IO APIC resources could be not be allocated.\n");
4138                 return -1;
4139         }
4140
4141         for (i = 0; i < nr_ioapics; i++) {
4142                 insert_resource(&iomem_resource, r);
4143                 r++;
4144         }
4145
4146         return 0;
4147 }
4148
4149 /* Insert the IO APIC resources after PCI initialization has occured to handle
4150  * IO APICS that are mapped in on a BAR in PCI space. */
4151 late_initcall(ioapic_insert_resources);