drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj_priv->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj_priv->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj_priv->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj_priv->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj_priv->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj_priv->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj_priv;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj_priv = to_intel_bo(intel_fb->obj);
1388
1389         if (intel_fb->obj->size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj_priv->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_gem_object *obj,
1437                            bool pipelined)
1438 {
1439         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440         u32 alignment;
1441         int ret;
1442
1443         switch (obj_priv->tiling_mode) {
1444         case I915_TILING_NONE:
1445                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446                         alignment = 128 * 1024;
1447                 else if (INTEL_INFO(dev)->gen >= 4)
1448                         alignment = 4 * 1024;
1449                 else
1450                         alignment = 64 * 1024;
1451                 break;
1452         case I915_TILING_X:
1453                 /* pin() will align the object as required by fence */
1454                 alignment = 0;
1455                 break;
1456         case I915_TILING_Y:
1457                 /* FIXME: Is this true? */
1458                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459                 return -EINVAL;
1460         default:
1461                 BUG();
1462         }
1463
1464         ret = i915_gem_object_pin(obj, alignment, true);
1465         if (ret)
1466                 return ret;
1467
1468         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469         if (ret)
1470                 goto err_unpin;
1471
1472         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473          * fence, whereas 965+ only requires a fence if using
1474          * framebuffer compression.  For simplicity, we always install
1475          * a fence as the cost is not that onerous.
1476          */
1477         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1478                 ret = i915_gem_object_get_fence_reg(obj, false);
1479                 if (ret)
1480                         goto err_unpin;
1481         }
1482
1483         return 0;
1484
1485 err_unpin:
1486         i915_gem_object_unpin(obj);
1487         return ret;
1488 }
1489
1490 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1491 static int
1492 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1493                            int x, int y, enum mode_set_atomic state)
1494 {
1495         struct drm_device *dev = crtc->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1498         struct intel_framebuffer *intel_fb;
1499         struct drm_i915_gem_object *obj_priv;
1500         struct drm_gem_object *obj;
1501         int plane = intel_crtc->plane;
1502         unsigned long Start, Offset;
1503         u32 dspcntr;
1504         u32 reg;
1505
1506         switch (plane) {
1507         case 0:
1508         case 1:
1509                 break;
1510         default:
1511                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1512                 return -EINVAL;
1513         }
1514
1515         intel_fb = to_intel_framebuffer(fb);
1516         obj = intel_fb->obj;
1517         obj_priv = to_intel_bo(obj);
1518
1519         reg = DSPCNTR(plane);
1520         dspcntr = I915_READ(reg);
1521         /* Mask out pixel format bits in case we change it */
1522         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1523         switch (fb->bits_per_pixel) {
1524         case 8:
1525                 dspcntr |= DISPPLANE_8BPP;
1526                 break;
1527         case 16:
1528                 if (fb->depth == 15)
1529                         dspcntr |= DISPPLANE_15_16BPP;
1530                 else
1531                         dspcntr |= DISPPLANE_16BPP;
1532                 break;
1533         case 24:
1534         case 32:
1535                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1536                 break;
1537         default:
1538                 DRM_ERROR("Unknown color depth\n");
1539                 return -EINVAL;
1540         }
1541         if (INTEL_INFO(dev)->gen >= 4) {
1542                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1543                         dspcntr |= DISPPLANE_TILED;
1544                 else
1545                         dspcntr &= ~DISPPLANE_TILED;
1546         }
1547
1548         if (HAS_PCH_SPLIT(dev))
1549                 /* must disable */
1550                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1551
1552         I915_WRITE(reg, dspcntr);
1553
1554         Start = obj_priv->gtt_offset;
1555         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1556
1557         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1558                       Start, Offset, x, y, fb->pitch);
1559         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1560         if (INTEL_INFO(dev)->gen >= 4) {
1561                 I915_WRITE(DSPSURF(plane), Start);
1562                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1563                 I915_WRITE(DSPADDR(plane), Offset);
1564         } else
1565                 I915_WRITE(DSPADDR(plane), Start + Offset);
1566         POSTING_READ(reg);
1567
1568         intel_update_fbc(dev);
1569         intel_increase_pllclock(crtc);
1570
1571         return 0;
1572 }
1573
1574 static int
1575 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1576                     struct drm_framebuffer *old_fb)
1577 {
1578         struct drm_device *dev = crtc->dev;
1579         struct drm_i915_master_private *master_priv;
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         int ret;
1582
1583         /* no fb bound */
1584         if (!crtc->fb) {
1585                 DRM_DEBUG_KMS("No FB bound\n");
1586                 return 0;
1587         }
1588
1589         switch (intel_crtc->plane) {
1590         case 0:
1591         case 1:
1592                 break;
1593         default:
1594                 return -EINVAL;
1595         }
1596
1597         mutex_lock(&dev->struct_mutex);
1598         ret = intel_pin_and_fence_fb_obj(dev,
1599                                          to_intel_framebuffer(crtc->fb)->obj,
1600                                          false);
1601         if (ret != 0) {
1602                 mutex_unlock(&dev->struct_mutex);
1603                 return ret;
1604         }
1605
1606         if (old_fb) {
1607                 struct drm_i915_private *dev_priv = dev->dev_private;
1608                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1609                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1610
1611                 wait_event(dev_priv->pending_flip_queue,
1612                            atomic_read(&obj_priv->pending_flip) == 0);
1613
1614                 /* Big Hammer, we also need to ensure that any pending
1615                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1616                  * current scanout is retired before unpinning the old
1617                  * framebuffer.
1618                  */
1619                 ret = i915_gem_object_flush_gpu(obj_priv, false);
1620                 if (ret) {
1621                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1622                         mutex_unlock(&dev->struct_mutex);
1623                         return ret;
1624                 }
1625         }
1626
1627         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1628                                          LEAVE_ATOMIC_MODE_SET);
1629         if (ret) {
1630                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1631                 mutex_unlock(&dev->struct_mutex);
1632                 return ret;
1633         }
1634
1635         if (old_fb)
1636                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1637
1638         mutex_unlock(&dev->struct_mutex);
1639
1640         if (!dev->primary->master)
1641                 return 0;
1642
1643         master_priv = dev->primary->master->driver_priv;
1644         if (!master_priv->sarea_priv)
1645                 return 0;
1646
1647         if (intel_crtc->pipe) {
1648                 master_priv->sarea_priv->pipeB_x = x;
1649                 master_priv->sarea_priv->pipeB_y = y;
1650         } else {
1651                 master_priv->sarea_priv->pipeA_x = x;
1652                 master_priv->sarea_priv->pipeA_y = y;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1659 {
1660         struct drm_device *dev = crtc->dev;
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         u32 dpa_ctl;
1663
1664         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1665         dpa_ctl = I915_READ(DP_A);
1666         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1667
1668         if (clock < 200000) {
1669                 u32 temp;
1670                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1671                 /* workaround for 160Mhz:
1672                    1) program 0x4600c bits 15:0 = 0x8124
1673                    2) program 0x46010 bit 0 = 1
1674                    3) program 0x46034 bit 24 = 1
1675                    4) program 0x64000 bit 14 = 1
1676                    */
1677                 temp = I915_READ(0x4600c);
1678                 temp &= 0xffff0000;
1679                 I915_WRITE(0x4600c, temp | 0x8124);
1680
1681                 temp = I915_READ(0x46010);
1682                 I915_WRITE(0x46010, temp | 1);
1683
1684                 temp = I915_READ(0x46034);
1685                 I915_WRITE(0x46034, temp | (1 << 24));
1686         } else {
1687                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1688         }
1689         I915_WRITE(DP_A, dpa_ctl);
1690
1691         POSTING_READ(DP_A);
1692         udelay(500);
1693 }
1694
1695 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1696 {
1697         struct drm_device *dev = crtc->dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700         int pipe = intel_crtc->pipe;
1701         u32 reg, temp;
1702
1703         /* enable normal train */
1704         reg = FDI_TX_CTL(pipe);
1705         temp = I915_READ(reg);
1706         temp &= ~FDI_LINK_TRAIN_NONE;
1707         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1708         I915_WRITE(reg, temp);
1709
1710         reg = FDI_RX_CTL(pipe);
1711         temp = I915_READ(reg);
1712         if (HAS_PCH_CPT(dev)) {
1713                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1714                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1715         } else {
1716                 temp &= ~FDI_LINK_TRAIN_NONE;
1717                 temp |= FDI_LINK_TRAIN_NONE;
1718         }
1719         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1720
1721         /* wait one idle pattern time */
1722         POSTING_READ(reg);
1723         udelay(1000);
1724 }
1725
1726 /* The FDI link training functions for ILK/Ibexpeak. */
1727 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1728 {
1729         struct drm_device *dev = crtc->dev;
1730         struct drm_i915_private *dev_priv = dev->dev_private;
1731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1732         int pipe = intel_crtc->pipe;
1733         u32 reg, temp, tries;
1734
1735         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1736            for train result */
1737         reg = FDI_RX_IMR(pipe);
1738         temp = I915_READ(reg);
1739         temp &= ~FDI_RX_SYMBOL_LOCK;
1740         temp &= ~FDI_RX_BIT_LOCK;
1741         I915_WRITE(reg, temp);
1742         I915_READ(reg);
1743         udelay(150);
1744
1745         /* enable CPU FDI TX and PCH FDI RX */
1746         reg = FDI_TX_CTL(pipe);
1747         temp = I915_READ(reg);
1748         temp &= ~(7 << 19);
1749         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1750         temp &= ~FDI_LINK_TRAIN_NONE;
1751         temp |= FDI_LINK_TRAIN_PATTERN_1;
1752         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1753
1754         reg = FDI_RX_CTL(pipe);
1755         temp = I915_READ(reg);
1756         temp &= ~FDI_LINK_TRAIN_NONE;
1757         temp |= FDI_LINK_TRAIN_PATTERN_1;
1758         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1759
1760         POSTING_READ(reg);
1761         udelay(150);
1762
1763         /* Ironlake workaround, enable clock pointer after FDI enable*/
1764         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1765
1766         reg = FDI_RX_IIR(pipe);
1767         for (tries = 0; tries < 5; tries++) {
1768                 temp = I915_READ(reg);
1769                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1770
1771                 if ((temp & FDI_RX_BIT_LOCK)) {
1772                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1773                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1774                         break;
1775                 }
1776         }
1777         if (tries == 5)
1778                 DRM_ERROR("FDI train 1 fail!\n");
1779
1780         /* Train 2 */
1781         reg = FDI_TX_CTL(pipe);
1782         temp = I915_READ(reg);
1783         temp &= ~FDI_LINK_TRAIN_NONE;
1784         temp |= FDI_LINK_TRAIN_PATTERN_2;
1785         I915_WRITE(reg, temp);
1786
1787         reg = FDI_RX_CTL(pipe);
1788         temp = I915_READ(reg);
1789         temp &= ~FDI_LINK_TRAIN_NONE;
1790         temp |= FDI_LINK_TRAIN_PATTERN_2;
1791         I915_WRITE(reg, temp);
1792
1793         POSTING_READ(reg);
1794         udelay(150);
1795
1796         reg = FDI_RX_IIR(pipe);
1797         for (tries = 0; tries < 5; tries++) {
1798                 temp = I915_READ(reg);
1799                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1800
1801                 if (temp & FDI_RX_SYMBOL_LOCK) {
1802                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1803                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1804                         break;
1805                 }
1806         }
1807         if (tries == 5)
1808                 DRM_ERROR("FDI train 2 fail!\n");
1809
1810         DRM_DEBUG_KMS("FDI train done\n");
1811
1812 }
1813
1814 static const int const snb_b_fdi_train_param [] = {
1815         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1816         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1817         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1818         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1819 };
1820
1821 /* The FDI link training functions for SNB/Cougarpoint. */
1822 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1823 {
1824         struct drm_device *dev = crtc->dev;
1825         struct drm_i915_private *dev_priv = dev->dev_private;
1826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827         int pipe = intel_crtc->pipe;
1828         u32 reg, temp, i;
1829
1830         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1831            for train result */
1832         reg = FDI_RX_IMR(pipe);
1833         temp = I915_READ(reg);
1834         temp &= ~FDI_RX_SYMBOL_LOCK;
1835         temp &= ~FDI_RX_BIT_LOCK;
1836         I915_WRITE(reg, temp);
1837
1838         POSTING_READ(reg);
1839         udelay(150);
1840
1841         /* enable CPU FDI TX and PCH FDI RX */
1842         reg = FDI_TX_CTL(pipe);
1843         temp = I915_READ(reg);
1844         temp &= ~(7 << 19);
1845         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1846         temp &= ~FDI_LINK_TRAIN_NONE;
1847         temp |= FDI_LINK_TRAIN_PATTERN_1;
1848         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1849         /* SNB-B */
1850         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1851         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1852
1853         reg = FDI_RX_CTL(pipe);
1854         temp = I915_READ(reg);
1855         if (HAS_PCH_CPT(dev)) {
1856                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1857                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1858         } else {
1859                 temp &= ~FDI_LINK_TRAIN_NONE;
1860                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1861         }
1862         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1863
1864         POSTING_READ(reg);
1865         udelay(150);
1866
1867         for (i = 0; i < 4; i++ ) {
1868                 reg = FDI_TX_CTL(pipe);
1869                 temp = I915_READ(reg);
1870                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1871                 temp |= snb_b_fdi_train_param[i];
1872                 I915_WRITE(reg, temp);
1873
1874                 POSTING_READ(reg);
1875                 udelay(500);
1876
1877                 reg = FDI_RX_IIR(pipe);
1878                 temp = I915_READ(reg);
1879                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1880
1881                 if (temp & FDI_RX_BIT_LOCK) {
1882                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1883                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1884                         break;
1885                 }
1886         }
1887         if (i == 4)
1888                 DRM_ERROR("FDI train 1 fail!\n");
1889
1890         /* Train 2 */
1891         reg = FDI_TX_CTL(pipe);
1892         temp = I915_READ(reg);
1893         temp &= ~FDI_LINK_TRAIN_NONE;
1894         temp |= FDI_LINK_TRAIN_PATTERN_2;
1895         if (IS_GEN6(dev)) {
1896                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1897                 /* SNB-B */
1898                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1899         }
1900         I915_WRITE(reg, temp);
1901
1902         reg = FDI_RX_CTL(pipe);
1903         temp = I915_READ(reg);
1904         if (HAS_PCH_CPT(dev)) {
1905                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1906                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1907         } else {
1908                 temp &= ~FDI_LINK_TRAIN_NONE;
1909                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1910         }
1911         I915_WRITE(reg, temp);
1912
1913         POSTING_READ(reg);
1914         udelay(150);
1915
1916         for (i = 0; i < 4; i++ ) {
1917                 reg = FDI_TX_CTL(pipe);
1918                 temp = I915_READ(reg);
1919                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1920                 temp |= snb_b_fdi_train_param[i];
1921                 I915_WRITE(reg, temp);
1922
1923                 POSTING_READ(reg);
1924                 udelay(500);
1925
1926                 reg = FDI_RX_IIR(pipe);
1927                 temp = I915_READ(reg);
1928                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1929
1930                 if (temp & FDI_RX_SYMBOL_LOCK) {
1931                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1932                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1933                         break;
1934                 }
1935         }
1936         if (i == 4)
1937                 DRM_ERROR("FDI train 2 fail!\n");
1938
1939         DRM_DEBUG_KMS("FDI train done.\n");
1940 }
1941
1942 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1943 {
1944         struct drm_device *dev = crtc->dev;
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947         int pipe = intel_crtc->pipe;
1948         u32 reg, temp;
1949
1950         /* Write the TU size bits so error detection works */
1951         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1952                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1953
1954         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1955         reg = FDI_RX_CTL(pipe);
1956         temp = I915_READ(reg);
1957         temp &= ~((0x7 << 19) | (0x7 << 16));
1958         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1959         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1960         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1961
1962         POSTING_READ(reg);
1963         udelay(200);
1964
1965         /* Switch from Rawclk to PCDclk */
1966         temp = I915_READ(reg);
1967         I915_WRITE(reg, temp | FDI_PCDCLK);
1968
1969         POSTING_READ(reg);
1970         udelay(200);
1971
1972         /* Enable CPU FDI TX PLL, always on for Ironlake */
1973         reg = FDI_TX_CTL(pipe);
1974         temp = I915_READ(reg);
1975         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1976                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1977
1978                 POSTING_READ(reg);
1979                 udelay(100);
1980         }
1981 }
1982
1983 static void intel_flush_display_plane(struct drm_device *dev,
1984                                       int plane)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         u32 reg = DSPADDR(plane);
1988         I915_WRITE(reg, I915_READ(reg));
1989 }
1990
1991 /*
1992  * When we disable a pipe, we need to clear any pending scanline wait events
1993  * to avoid hanging the ring, which we assume we are waiting on.
1994  */
1995 static void intel_clear_scanline_wait(struct drm_device *dev)
1996 {
1997         struct drm_i915_private *dev_priv = dev->dev_private;
1998         struct intel_ring_buffer *ring;
1999         u32 tmp;
2000
2001         if (IS_GEN2(dev))
2002                 /* Can't break the hang on i8xx */
2003                 return;
2004
2005         ring = &dev_priv->render_ring;
2006         tmp = I915_READ_CTL(ring);
2007         if (tmp & RING_WAIT)
2008                 I915_WRITE_CTL(ring, tmp);
2009 }
2010
2011 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2012 {
2013         struct drm_i915_gem_object *obj_priv;
2014         struct drm_i915_private *dev_priv;
2015
2016         if (crtc->fb == NULL)
2017                 return;
2018
2019         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2020         dev_priv = crtc->dev->dev_private;
2021         wait_event(dev_priv->pending_flip_queue,
2022                    atomic_read(&obj_priv->pending_flip) == 0);
2023 }
2024
2025 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2026 {
2027         struct drm_device *dev = crtc->dev;
2028         struct drm_i915_private *dev_priv = dev->dev_private;
2029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030         int pipe = intel_crtc->pipe;
2031         int plane = intel_crtc->plane;
2032         u32 reg, temp;
2033
2034         if (intel_crtc->active)
2035                 return;
2036
2037         intel_crtc->active = true;
2038         intel_update_watermarks(dev);
2039
2040         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2041                 temp = I915_READ(PCH_LVDS);
2042                 if ((temp & LVDS_PORT_EN) == 0)
2043                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2044         }
2045
2046         ironlake_fdi_enable(crtc);
2047
2048         /* Enable panel fitting for LVDS */
2049         if (dev_priv->pch_pf_size &&
2050             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2051                 /* Force use of hard-coded filter coefficients
2052                  * as some pre-programmed values are broken,
2053                  * e.g. x201.
2054                  */
2055                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2056                            PF_ENABLE | PF_FILTER_MED_3x3);
2057                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2058                            dev_priv->pch_pf_pos);
2059                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2060                            dev_priv->pch_pf_size);
2061         }
2062
2063         /* Enable CPU pipe */
2064         reg = PIPECONF(pipe);
2065         temp = I915_READ(reg);
2066         if ((temp & PIPECONF_ENABLE) == 0) {
2067                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2068                 POSTING_READ(reg);
2069                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2070         }
2071
2072         /* configure and enable CPU plane */
2073         reg = DSPCNTR(plane);
2074         temp = I915_READ(reg);
2075         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2076                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2077                 intel_flush_display_plane(dev, plane);
2078         }
2079
2080         /* For PCH output, training FDI link */
2081         if (IS_GEN6(dev))
2082                 gen6_fdi_link_train(crtc);
2083         else
2084                 ironlake_fdi_link_train(crtc);
2085
2086         /* enable PCH DPLL */
2087         reg = PCH_DPLL(pipe);
2088         temp = I915_READ(reg);
2089         if ((temp & DPLL_VCO_ENABLE) == 0) {
2090                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2091                 POSTING_READ(reg);
2092                 udelay(200);
2093         }
2094
2095         if (HAS_PCH_CPT(dev)) {
2096                 /* Be sure PCH DPLL SEL is set */
2097                 temp = I915_READ(PCH_DPLL_SEL);
2098                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2099                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2100                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2101                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2102                 I915_WRITE(PCH_DPLL_SEL, temp);
2103         }
2104
2105         /* set transcoder timing */
2106         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2107         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2108         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2109
2110         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2111         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2112         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2113
2114         intel_fdi_normal_train(crtc);
2115
2116         /* For PCH DP, enable TRANS_DP_CTL */
2117         if (HAS_PCH_CPT(dev) &&
2118             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2119                 reg = TRANS_DP_CTL(pipe);
2120                 temp = I915_READ(reg);
2121                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2122                           TRANS_DP_SYNC_MASK);
2123                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2124                          TRANS_DP_ENH_FRAMING);
2125
2126                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2127                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2128                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2129                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2130
2131                 switch (intel_trans_dp_port_sel(crtc)) {
2132                 case PCH_DP_B:
2133                         temp |= TRANS_DP_PORT_SEL_B;
2134                         break;
2135                 case PCH_DP_C:
2136                         temp |= TRANS_DP_PORT_SEL_C;
2137                         break;
2138                 case PCH_DP_D:
2139                         temp |= TRANS_DP_PORT_SEL_D;
2140                         break;
2141                 default:
2142                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2143                         temp |= TRANS_DP_PORT_SEL_B;
2144                         break;
2145                 }
2146
2147                 I915_WRITE(reg, temp);
2148         }
2149
2150         /* enable PCH transcoder */
2151         reg = TRANSCONF(pipe);
2152         temp = I915_READ(reg);
2153         /*
2154          * make the BPC in transcoder be consistent with
2155          * that in pipeconf reg.
2156          */
2157         temp &= ~PIPE_BPC_MASK;
2158         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2159         I915_WRITE(reg, temp | TRANS_ENABLE);
2160         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2161                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2162
2163         intel_crtc_load_lut(crtc);
2164         intel_update_fbc(dev);
2165         intel_crtc_update_cursor(crtc, true);
2166 }
2167
2168 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2169 {
2170         struct drm_device *dev = crtc->dev;
2171         struct drm_i915_private *dev_priv = dev->dev_private;
2172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2173         int pipe = intel_crtc->pipe;
2174         int plane = intel_crtc->plane;
2175         u32 reg, temp;
2176
2177         if (!intel_crtc->active)
2178                 return;
2179
2180         intel_crtc_wait_for_pending_flips(crtc);
2181         drm_vblank_off(dev, pipe);
2182         intel_crtc_update_cursor(crtc, false);
2183
2184         /* Disable display plane */
2185         reg = DSPCNTR(plane);
2186         temp = I915_READ(reg);
2187         if (temp & DISPLAY_PLANE_ENABLE) {
2188                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2189                 intel_flush_display_plane(dev, plane);
2190         }
2191
2192         if (dev_priv->cfb_plane == plane &&
2193             dev_priv->display.disable_fbc)
2194                 dev_priv->display.disable_fbc(dev);
2195
2196         /* disable cpu pipe, disable after all planes disabled */
2197         reg = PIPECONF(pipe);
2198         temp = I915_READ(reg);
2199         if (temp & PIPECONF_ENABLE) {
2200                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2201                 POSTING_READ(reg);
2202                 /* wait for cpu pipe off, pipe state */
2203                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2204         }
2205
2206         /* Disable PF */
2207         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2208         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2209
2210         /* disable CPU FDI tx and PCH FDI rx */
2211         reg = FDI_TX_CTL(pipe);
2212         temp = I915_READ(reg);
2213         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2214         POSTING_READ(reg);
2215
2216         reg = FDI_RX_CTL(pipe);
2217         temp = I915_READ(reg);
2218         temp &= ~(0x7 << 16);
2219         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2220         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2221
2222         POSTING_READ(reg);
2223         udelay(100);
2224
2225         /* Ironlake workaround, disable clock pointer after downing FDI */
2226         if (HAS_PCH_IBX(dev))
2227                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2228                            I915_READ(FDI_RX_CHICKEN(pipe) &
2229                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2230
2231         /* still set train pattern 1 */
2232         reg = FDI_TX_CTL(pipe);
2233         temp = I915_READ(reg);
2234         temp &= ~FDI_LINK_TRAIN_NONE;
2235         temp |= FDI_LINK_TRAIN_PATTERN_1;
2236         I915_WRITE(reg, temp);
2237
2238         reg = FDI_RX_CTL(pipe);
2239         temp = I915_READ(reg);
2240         if (HAS_PCH_CPT(dev)) {
2241                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2242                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2243         } else {
2244                 temp &= ~FDI_LINK_TRAIN_NONE;
2245                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2246         }
2247         /* BPC in FDI rx is consistent with that in PIPECONF */
2248         temp &= ~(0x07 << 16);
2249         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2250         I915_WRITE(reg, temp);
2251
2252         POSTING_READ(reg);
2253         udelay(100);
2254
2255         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2256                 temp = I915_READ(PCH_LVDS);
2257                 if (temp & LVDS_PORT_EN) {
2258                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2259                         POSTING_READ(PCH_LVDS);
2260                         udelay(100);
2261                 }
2262         }
2263
2264         /* disable PCH transcoder */
2265         reg = TRANSCONF(plane);
2266         temp = I915_READ(reg);
2267         if (temp & TRANS_ENABLE) {
2268                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2269                 /* wait for PCH transcoder off, transcoder state */
2270                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2271                         DRM_ERROR("failed to disable transcoder\n");
2272         }
2273
2274         if (HAS_PCH_CPT(dev)) {
2275                 /* disable TRANS_DP_CTL */
2276                 reg = TRANS_DP_CTL(pipe);
2277                 temp = I915_READ(reg);
2278                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2279                 I915_WRITE(reg, temp);
2280
2281                 /* disable DPLL_SEL */
2282                 temp = I915_READ(PCH_DPLL_SEL);
2283                 if (pipe == 0)
2284                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2285                 else
2286                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2287                 I915_WRITE(PCH_DPLL_SEL, temp);
2288         }
2289
2290         /* disable PCH DPLL */
2291         reg = PCH_DPLL(pipe);
2292         temp = I915_READ(reg);
2293         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2294
2295         /* Switch from PCDclk to Rawclk */
2296         reg = FDI_RX_CTL(pipe);
2297         temp = I915_READ(reg);
2298         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2299
2300         /* Disable CPU FDI TX PLL */
2301         reg = FDI_TX_CTL(pipe);
2302         temp = I915_READ(reg);
2303         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2304
2305         POSTING_READ(reg);
2306         udelay(100);
2307
2308         reg = FDI_RX_CTL(pipe);
2309         temp = I915_READ(reg);
2310         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2311
2312         /* Wait for the clocks to turn off. */
2313         POSTING_READ(reg);
2314         udelay(100);
2315
2316         intel_crtc->active = false;
2317         intel_update_watermarks(dev);
2318         intel_update_fbc(dev);
2319         intel_clear_scanline_wait(dev);
2320 }
2321
2322 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2323 {
2324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2325         int pipe = intel_crtc->pipe;
2326         int plane = intel_crtc->plane;
2327
2328         /* XXX: When our outputs are all unaware of DPMS modes other than off
2329          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2330          */
2331         switch (mode) {
2332         case DRM_MODE_DPMS_ON:
2333         case DRM_MODE_DPMS_STANDBY:
2334         case DRM_MODE_DPMS_SUSPEND:
2335                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2336                 ironlake_crtc_enable(crtc);
2337                 break;
2338
2339         case DRM_MODE_DPMS_OFF:
2340                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2341                 ironlake_crtc_disable(crtc);
2342                 break;
2343         }
2344 }
2345
2346 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2347 {
2348         if (!enable && intel_crtc->overlay) {
2349                 struct drm_device *dev = intel_crtc->base.dev;
2350
2351                 mutex_lock(&dev->struct_mutex);
2352                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2353                 mutex_unlock(&dev->struct_mutex);
2354         }
2355
2356         /* Let userspace switch the overlay on again. In most cases userspace
2357          * has to recompute where to put it anyway.
2358          */
2359 }
2360
2361 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366         int pipe = intel_crtc->pipe;
2367         int plane = intel_crtc->plane;
2368         u32 reg, temp;
2369
2370         if (intel_crtc->active)
2371                 return;
2372
2373         intel_crtc->active = true;
2374         intel_update_watermarks(dev);
2375
2376         /* Enable the DPLL */
2377         reg = DPLL(pipe);
2378         temp = I915_READ(reg);
2379         if ((temp & DPLL_VCO_ENABLE) == 0) {
2380                 I915_WRITE(reg, temp);
2381
2382                 /* Wait for the clocks to stabilize. */
2383                 POSTING_READ(reg);
2384                 udelay(150);
2385
2386                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2387
2388                 /* Wait for the clocks to stabilize. */
2389                 POSTING_READ(reg);
2390                 udelay(150);
2391
2392                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2393
2394                 /* Wait for the clocks to stabilize. */
2395                 POSTING_READ(reg);
2396                 udelay(150);
2397         }
2398
2399         /* Enable the pipe */
2400         reg = PIPECONF(pipe);
2401         temp = I915_READ(reg);
2402         if ((temp & PIPECONF_ENABLE) == 0)
2403                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2404
2405         /* Enable the plane */
2406         reg = DSPCNTR(plane);
2407         temp = I915_READ(reg);
2408         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2409                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2410                 intel_flush_display_plane(dev, plane);
2411         }
2412
2413         intel_crtc_load_lut(crtc);
2414         intel_update_fbc(dev);
2415
2416         /* Give the overlay scaler a chance to enable if it's on this pipe */
2417         intel_crtc_dpms_overlay(intel_crtc, true);
2418         intel_crtc_update_cursor(crtc, true);
2419 }
2420
2421 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         int plane = intel_crtc->plane;
2428         u32 reg, temp;
2429
2430         if (!intel_crtc->active)
2431                 return;
2432
2433         /* Give the overlay scaler a chance to disable if it's on this pipe */
2434         intel_crtc_wait_for_pending_flips(crtc);
2435         drm_vblank_off(dev, pipe);
2436         intel_crtc_dpms_overlay(intel_crtc, false);
2437         intel_crtc_update_cursor(crtc, false);
2438
2439         if (dev_priv->cfb_plane == plane &&
2440             dev_priv->display.disable_fbc)
2441                 dev_priv->display.disable_fbc(dev);
2442
2443         /* Disable display plane */
2444         reg = DSPCNTR(plane);
2445         temp = I915_READ(reg);
2446         if (temp & DISPLAY_PLANE_ENABLE) {
2447                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2448                 /* Flush the plane changes */
2449                 intel_flush_display_plane(dev, plane);
2450
2451                 /* Wait for vblank for the disable to take effect */
2452                 if (IS_GEN2(dev))
2453                         intel_wait_for_vblank(dev, pipe);
2454         }
2455
2456         /* Don't disable pipe A or pipe A PLLs if needed */
2457         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2458                 goto done;
2459
2460         /* Next, disable display pipes */
2461         reg = PIPECONF(pipe);
2462         temp = I915_READ(reg);
2463         if (temp & PIPECONF_ENABLE) {
2464                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2465
2466                 /* Wait for the pipe to turn off */
2467                 POSTING_READ(reg);
2468                 intel_wait_for_pipe_off(dev, pipe);
2469         }
2470
2471         reg = DPLL(pipe);
2472         temp = I915_READ(reg);
2473         if (temp & DPLL_VCO_ENABLE) {
2474                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2475
2476                 /* Wait for the clocks to turn off. */
2477                 POSTING_READ(reg);
2478                 udelay(150);
2479         }
2480
2481 done:
2482         intel_crtc->active = false;
2483         intel_update_fbc(dev);
2484         intel_update_watermarks(dev);
2485         intel_clear_scanline_wait(dev);
2486 }
2487
2488 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2489 {
2490         /* XXX: When our outputs are all unaware of DPMS modes other than off
2491          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2492          */
2493         switch (mode) {
2494         case DRM_MODE_DPMS_ON:
2495         case DRM_MODE_DPMS_STANDBY:
2496         case DRM_MODE_DPMS_SUSPEND:
2497                 i9xx_crtc_enable(crtc);
2498                 break;
2499         case DRM_MODE_DPMS_OFF:
2500                 i9xx_crtc_disable(crtc);
2501                 break;
2502         }
2503 }
2504
2505 /**
2506  * Sets the power management mode of the pipe and plane.
2507  */
2508 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2509 {
2510         struct drm_device *dev = crtc->dev;
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512         struct drm_i915_master_private *master_priv;
2513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2514         int pipe = intel_crtc->pipe;
2515         bool enabled;
2516
2517         if (intel_crtc->dpms_mode == mode)
2518                 return;
2519
2520         intel_crtc->dpms_mode = mode;
2521
2522         dev_priv->display.dpms(crtc, mode);
2523
2524         if (!dev->primary->master)
2525                 return;
2526
2527         master_priv = dev->primary->master->driver_priv;
2528         if (!master_priv->sarea_priv)
2529                 return;
2530
2531         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2532
2533         switch (pipe) {
2534         case 0:
2535                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2536                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2537                 break;
2538         case 1:
2539                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2540                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2541                 break;
2542         default:
2543                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2544                 break;
2545         }
2546 }
2547
2548 static void intel_crtc_disable(struct drm_crtc *crtc)
2549 {
2550         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2551         struct drm_device *dev = crtc->dev;
2552
2553         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2554
2555         if (crtc->fb) {
2556                 mutex_lock(&dev->struct_mutex);
2557                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2558                 mutex_unlock(&dev->struct_mutex);
2559         }
2560 }
2561
2562 /* Prepare for a mode set.
2563  *
2564  * Note we could be a lot smarter here.  We need to figure out which outputs
2565  * will be enabled, which disabled (in short, how the config will changes)
2566  * and perform the minimum necessary steps to accomplish that, e.g. updating
2567  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2568  * panel fitting is in the proper state, etc.
2569  */
2570 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2571 {
2572         i9xx_crtc_disable(crtc);
2573 }
2574
2575 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2576 {
2577         i9xx_crtc_enable(crtc);
2578 }
2579
2580 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2581 {
2582         ironlake_crtc_disable(crtc);
2583 }
2584
2585 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2586 {
2587         ironlake_crtc_enable(crtc);
2588 }
2589
2590 void intel_encoder_prepare (struct drm_encoder *encoder)
2591 {
2592         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2593         /* lvds has its own version of prepare see intel_lvds_prepare */
2594         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2595 }
2596
2597 void intel_encoder_commit (struct drm_encoder *encoder)
2598 {
2599         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2600         /* lvds has its own version of commit see intel_lvds_commit */
2601         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2602 }
2603
2604 void intel_encoder_destroy(struct drm_encoder *encoder)
2605 {
2606         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2607
2608         drm_encoder_cleanup(encoder);
2609         kfree(intel_encoder);
2610 }
2611
2612 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2613                                   struct drm_display_mode *mode,
2614                                   struct drm_display_mode *adjusted_mode)
2615 {
2616         struct drm_device *dev = crtc->dev;
2617
2618         if (HAS_PCH_SPLIT(dev)) {
2619                 /* FDI link clock is fixed at 2.7G */
2620                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2621                         return false;
2622         }
2623
2624         /* XXX some encoders set the crtcinfo, others don't.
2625          * Obviously we need some form of conflict resolution here...
2626          */
2627         if (adjusted_mode->crtc_htotal == 0)
2628                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2629
2630         return true;
2631 }
2632
2633 static int i945_get_display_clock_speed(struct drm_device *dev)
2634 {
2635         return 400000;
2636 }
2637
2638 static int i915_get_display_clock_speed(struct drm_device *dev)
2639 {
2640         return 333000;
2641 }
2642
2643 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2644 {
2645         return 200000;
2646 }
2647
2648 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2649 {
2650         u16 gcfgc = 0;
2651
2652         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2653
2654         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2655                 return 133000;
2656         else {
2657                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2658                 case GC_DISPLAY_CLOCK_333_MHZ:
2659                         return 333000;
2660                 default:
2661                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2662                         return 190000;
2663                 }
2664         }
2665 }
2666
2667 static int i865_get_display_clock_speed(struct drm_device *dev)
2668 {
2669         return 266000;
2670 }
2671
2672 static int i855_get_display_clock_speed(struct drm_device *dev)
2673 {
2674         u16 hpllcc = 0;
2675         /* Assume that the hardware is in the high speed state.  This
2676          * should be the default.
2677          */
2678         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2679         case GC_CLOCK_133_200:
2680         case GC_CLOCK_100_200:
2681                 return 200000;
2682         case GC_CLOCK_166_250:
2683                 return 250000;
2684         case GC_CLOCK_100_133:
2685                 return 133000;
2686         }
2687
2688         /* Shouldn't happen */
2689         return 0;
2690 }
2691
2692 static int i830_get_display_clock_speed(struct drm_device *dev)
2693 {
2694         return 133000;
2695 }
2696
2697 struct fdi_m_n {
2698         u32        tu;
2699         u32        gmch_m;
2700         u32        gmch_n;
2701         u32        link_m;
2702         u32        link_n;
2703 };
2704
2705 static void
2706 fdi_reduce_ratio(u32 *num, u32 *den)
2707 {
2708         while (*num > 0xffffff || *den > 0xffffff) {
2709                 *num >>= 1;
2710                 *den >>= 1;
2711         }
2712 }
2713
2714 #define DATA_N 0x800000
2715 #define LINK_N 0x80000
2716
2717 static void
2718 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2719                      int link_clock, struct fdi_m_n *m_n)
2720 {
2721         u64 temp;
2722
2723         m_n->tu = 64; /* default size */
2724
2725         temp = (u64) DATA_N * pixel_clock;
2726         temp = div_u64(temp, link_clock);
2727         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2728         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2729         m_n->gmch_n = DATA_N;
2730         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2731
2732         temp = (u64) LINK_N * pixel_clock;
2733         m_n->link_m = div_u64(temp, link_clock);
2734         m_n->link_n = LINK_N;
2735         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2736 }
2737
2738
2739 struct intel_watermark_params {
2740         unsigned long fifo_size;
2741         unsigned long max_wm;
2742         unsigned long default_wm;
2743         unsigned long guard_size;
2744         unsigned long cacheline_size;
2745 };
2746
2747 /* Pineview has different values for various configs */
2748 static struct intel_watermark_params pineview_display_wm = {
2749         PINEVIEW_DISPLAY_FIFO,
2750         PINEVIEW_MAX_WM,
2751         PINEVIEW_DFT_WM,
2752         PINEVIEW_GUARD_WM,
2753         PINEVIEW_FIFO_LINE_SIZE
2754 };
2755 static struct intel_watermark_params pineview_display_hplloff_wm = {
2756         PINEVIEW_DISPLAY_FIFO,
2757         PINEVIEW_MAX_WM,
2758         PINEVIEW_DFT_HPLLOFF_WM,
2759         PINEVIEW_GUARD_WM,
2760         PINEVIEW_FIFO_LINE_SIZE
2761 };
2762 static struct intel_watermark_params pineview_cursor_wm = {
2763         PINEVIEW_CURSOR_FIFO,
2764         PINEVIEW_CURSOR_MAX_WM,
2765         PINEVIEW_CURSOR_DFT_WM,
2766         PINEVIEW_CURSOR_GUARD_WM,
2767         PINEVIEW_FIFO_LINE_SIZE,
2768 };
2769 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2770         PINEVIEW_CURSOR_FIFO,
2771         PINEVIEW_CURSOR_MAX_WM,
2772         PINEVIEW_CURSOR_DFT_WM,
2773         PINEVIEW_CURSOR_GUARD_WM,
2774         PINEVIEW_FIFO_LINE_SIZE
2775 };
2776 static struct intel_watermark_params g4x_wm_info = {
2777         G4X_FIFO_SIZE,
2778         G4X_MAX_WM,
2779         G4X_MAX_WM,
2780         2,
2781         G4X_FIFO_LINE_SIZE,
2782 };
2783 static struct intel_watermark_params g4x_cursor_wm_info = {
2784         I965_CURSOR_FIFO,
2785         I965_CURSOR_MAX_WM,
2786         I965_CURSOR_DFT_WM,
2787         2,
2788         G4X_FIFO_LINE_SIZE,
2789 };
2790 static struct intel_watermark_params i965_cursor_wm_info = {
2791         I965_CURSOR_FIFO,
2792         I965_CURSOR_MAX_WM,
2793         I965_CURSOR_DFT_WM,
2794         2,
2795         I915_FIFO_LINE_SIZE,
2796 };
2797 static struct intel_watermark_params i945_wm_info = {
2798         I945_FIFO_SIZE,
2799         I915_MAX_WM,
2800         1,
2801         2,
2802         I915_FIFO_LINE_SIZE
2803 };
2804 static struct intel_watermark_params i915_wm_info = {
2805         I915_FIFO_SIZE,
2806         I915_MAX_WM,
2807         1,
2808         2,
2809         I915_FIFO_LINE_SIZE
2810 };
2811 static struct intel_watermark_params i855_wm_info = {
2812         I855GM_FIFO_SIZE,
2813         I915_MAX_WM,
2814         1,
2815         2,
2816         I830_FIFO_LINE_SIZE
2817 };
2818 static struct intel_watermark_params i830_wm_info = {
2819         I830_FIFO_SIZE,
2820         I915_MAX_WM,
2821         1,
2822         2,
2823         I830_FIFO_LINE_SIZE
2824 };
2825
2826 static struct intel_watermark_params ironlake_display_wm_info = {
2827         ILK_DISPLAY_FIFO,
2828         ILK_DISPLAY_MAXWM,
2829         ILK_DISPLAY_DFTWM,
2830         2,
2831         ILK_FIFO_LINE_SIZE
2832 };
2833
2834 static struct intel_watermark_params ironlake_cursor_wm_info = {
2835         ILK_CURSOR_FIFO,
2836         ILK_CURSOR_MAXWM,
2837         ILK_CURSOR_DFTWM,
2838         2,
2839         ILK_FIFO_LINE_SIZE
2840 };
2841
2842 static struct intel_watermark_params ironlake_display_srwm_info = {
2843         ILK_DISPLAY_SR_FIFO,
2844         ILK_DISPLAY_MAX_SRWM,
2845         ILK_DISPLAY_DFT_SRWM,
2846         2,
2847         ILK_FIFO_LINE_SIZE
2848 };
2849
2850 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2851         ILK_CURSOR_SR_FIFO,
2852         ILK_CURSOR_MAX_SRWM,
2853         ILK_CURSOR_DFT_SRWM,
2854         2,
2855         ILK_FIFO_LINE_SIZE
2856 };
2857
2858 /**
2859  * intel_calculate_wm - calculate watermark level
2860  * @clock_in_khz: pixel clock
2861  * @wm: chip FIFO params
2862  * @pixel_size: display pixel size
2863  * @latency_ns: memory latency for the platform
2864  *
2865  * Calculate the watermark level (the level at which the display plane will
2866  * start fetching from memory again).  Each chip has a different display
2867  * FIFO size and allocation, so the caller needs to figure that out and pass
2868  * in the correct intel_watermark_params structure.
2869  *
2870  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2871  * on the pixel size.  When it reaches the watermark level, it'll start
2872  * fetching FIFO line sized based chunks from memory until the FIFO fills
2873  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2874  * will occur, and a display engine hang could result.
2875  */
2876 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2877                                         struct intel_watermark_params *wm,
2878                                         int pixel_size,
2879                                         unsigned long latency_ns)
2880 {
2881         long entries_required, wm_size;
2882
2883         /*
2884          * Note: we need to make sure we don't overflow for various clock &
2885          * latency values.
2886          * clocks go from a few thousand to several hundred thousand.
2887          * latency is usually a few thousand
2888          */
2889         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2890                 1000;
2891         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2892
2893         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2894
2895         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2896
2897         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2898
2899         /* Don't promote wm_size to unsigned... */
2900         if (wm_size > (long)wm->max_wm)
2901                 wm_size = wm->max_wm;
2902         if (wm_size <= 0)
2903                 wm_size = wm->default_wm;
2904         return wm_size;
2905 }
2906
2907 struct cxsr_latency {
2908         int is_desktop;
2909         int is_ddr3;
2910         unsigned long fsb_freq;
2911         unsigned long mem_freq;
2912         unsigned long display_sr;
2913         unsigned long display_hpll_disable;
2914         unsigned long cursor_sr;
2915         unsigned long cursor_hpll_disable;
2916 };
2917
2918 static const struct cxsr_latency cxsr_latency_table[] = {
2919         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2920         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2921         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2922         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2923         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2924
2925         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2926         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2927         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2928         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2929         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2930
2931         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2932         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2933         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2934         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2935         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2936
2937         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2938         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2939         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2940         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2941         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2942
2943         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2944         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2945         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2946         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2947         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2948
2949         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2950         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2951         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2952         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2953         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2954 };
2955
2956 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2957                                                          int is_ddr3,
2958                                                          int fsb,
2959                                                          int mem)
2960 {
2961         const struct cxsr_latency *latency;
2962         int i;
2963
2964         if (fsb == 0 || mem == 0)
2965                 return NULL;
2966
2967         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2968                 latency = &cxsr_latency_table[i];
2969                 if (is_desktop == latency->is_desktop &&
2970                     is_ddr3 == latency->is_ddr3 &&
2971                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2972                         return latency;
2973         }
2974
2975         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2976
2977         return NULL;
2978 }
2979
2980 static void pineview_disable_cxsr(struct drm_device *dev)
2981 {
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983
2984         /* deactivate cxsr */
2985         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2986 }
2987
2988 /*
2989  * Latency for FIFO fetches is dependent on several factors:
2990  *   - memory configuration (speed, channels)
2991  *   - chipset
2992  *   - current MCH state
2993  * It can be fairly high in some situations, so here we assume a fairly
2994  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2995  * set this value too high, the FIFO will fetch frequently to stay full)
2996  * and power consumption (set it too low to save power and we might see
2997  * FIFO underruns and display "flicker").
2998  *
2999  * A value of 5us seems to be a good balance; safe for very low end
3000  * platforms but not overly aggressive on lower latency configs.
3001  */
3002 static const int latency_ns = 5000;
3003
3004 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3005 {
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         uint32_t dsparb = I915_READ(DSPARB);
3008         int size;
3009
3010         size = dsparb & 0x7f;
3011         if (plane)
3012                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3013
3014         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3015                       plane ? "B" : "A", size);
3016
3017         return size;
3018 }
3019
3020 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3021 {
3022         struct drm_i915_private *dev_priv = dev->dev_private;
3023         uint32_t dsparb = I915_READ(DSPARB);
3024         int size;
3025
3026         size = dsparb & 0x1ff;
3027         if (plane)
3028                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3029         size >>= 1; /* Convert to cachelines */
3030
3031         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3032                       plane ? "B" : "A", size);
3033
3034         return size;
3035 }
3036
3037 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3038 {
3039         struct drm_i915_private *dev_priv = dev->dev_private;
3040         uint32_t dsparb = I915_READ(DSPARB);
3041         int size;
3042
3043         size = dsparb & 0x7f;
3044         size >>= 2; /* Convert to cachelines */
3045
3046         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3047                       plane ? "B" : "A",
3048                       size);
3049
3050         return size;
3051 }
3052
3053 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3054 {
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         uint32_t dsparb = I915_READ(DSPARB);
3057         int size;
3058
3059         size = dsparb & 0x7f;
3060         size >>= 1; /* Convert to cachelines */
3061
3062         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3063                       plane ? "B" : "A", size);
3064
3065         return size;
3066 }
3067
3068 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3069                                int planeb_clock, int sr_hdisplay, int unused,
3070                                int pixel_size)
3071 {
3072         struct drm_i915_private *dev_priv = dev->dev_private;
3073         const struct cxsr_latency *latency;
3074         u32 reg;
3075         unsigned long wm;
3076         int sr_clock;
3077
3078         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3079                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3080         if (!latency) {
3081                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3082                 pineview_disable_cxsr(dev);
3083                 return;
3084         }
3085
3086         if (!planea_clock || !planeb_clock) {
3087                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3088
3089                 /* Display SR */
3090                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3091                                         pixel_size, latency->display_sr);
3092                 reg = I915_READ(DSPFW1);
3093                 reg &= ~DSPFW_SR_MASK;
3094                 reg |= wm << DSPFW_SR_SHIFT;
3095                 I915_WRITE(DSPFW1, reg);
3096                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3097
3098                 /* cursor SR */
3099                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3100                                         pixel_size, latency->cursor_sr);
3101                 reg = I915_READ(DSPFW3);
3102                 reg &= ~DSPFW_CURSOR_SR_MASK;
3103                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3104                 I915_WRITE(DSPFW3, reg);
3105
3106                 /* Display HPLL off SR */
3107                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3108                                         pixel_size, latency->display_hpll_disable);
3109                 reg = I915_READ(DSPFW3);
3110                 reg &= ~DSPFW_HPLL_SR_MASK;
3111                 reg |= wm & DSPFW_HPLL_SR_MASK;
3112                 I915_WRITE(DSPFW3, reg);
3113
3114                 /* cursor HPLL off SR */
3115                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3116                                         pixel_size, latency->cursor_hpll_disable);
3117                 reg = I915_READ(DSPFW3);
3118                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3119                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3120                 I915_WRITE(DSPFW3, reg);
3121                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3122
3123                 /* activate cxsr */
3124                 I915_WRITE(DSPFW3,
3125                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3126                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3127         } else {
3128                 pineview_disable_cxsr(dev);
3129                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3130         }
3131 }
3132
3133 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3134                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3135                           int pixel_size)
3136 {
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         int total_size, cacheline_size;
3139         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3140         struct intel_watermark_params planea_params, planeb_params;
3141         unsigned long line_time_us;
3142         int sr_clock, sr_entries = 0, entries_required;
3143
3144         /* Create copies of the base settings for each pipe */
3145         planea_params = planeb_params = g4x_wm_info;
3146
3147         /* Grab a couple of global values before we overwrite them */
3148         total_size = planea_params.fifo_size;
3149         cacheline_size = planea_params.cacheline_size;
3150
3151         /*
3152          * Note: we need to make sure we don't overflow for various clock &
3153          * latency values.
3154          * clocks go from a few thousand to several hundred thousand.
3155          * latency is usually a few thousand
3156          */
3157         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3158                 1000;
3159         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3160         planea_wm = entries_required + planea_params.guard_size;
3161
3162         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3163                 1000;
3164         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3165         planeb_wm = entries_required + planeb_params.guard_size;
3166
3167         cursora_wm = cursorb_wm = 16;
3168         cursor_sr = 32;
3169
3170         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3171
3172         /* Calc sr entries for one plane configs */
3173         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3174                 /* self-refresh has much higher latency */
3175                 static const int sr_latency_ns = 12000;
3176
3177                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3178                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3179
3180                 /* Use ns/us then divide to preserve precision */
3181                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3182                         pixel_size * sr_hdisplay;
3183                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3184
3185                 entries_required = (((sr_latency_ns / line_time_us) +
3186                                      1000) / 1000) * pixel_size * 64;
3187                 entries_required = DIV_ROUND_UP(entries_required,
3188                                                 g4x_cursor_wm_info.cacheline_size);
3189                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3190
3191                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3192                         cursor_sr = g4x_cursor_wm_info.max_wm;
3193                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3194                               "cursor %d\n", sr_entries, cursor_sr);
3195
3196                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3197         } else {
3198                 /* Turn off self refresh if both pipes are enabled */
3199                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3200                            & ~FW_BLC_SELF_EN);
3201         }
3202
3203         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3204                   planea_wm, planeb_wm, sr_entries);
3205
3206         planea_wm &= 0x3f;
3207         planeb_wm &= 0x3f;
3208
3209         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3210                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3211                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3212         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3213                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3214         /* HPLL off in SR has some issues on G4x... disable it */
3215         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3216                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3217 }
3218
3219 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3220                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3221                            int pixel_size)
3222 {
3223         struct drm_i915_private *dev_priv = dev->dev_private;
3224         unsigned long line_time_us;
3225         int sr_clock, sr_entries, srwm = 1;
3226         int cursor_sr = 16;
3227
3228         /* Calc sr entries for one plane configs */
3229         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3230                 /* self-refresh has much higher latency */
3231                 static const int sr_latency_ns = 12000;
3232
3233                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3234                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3235
3236                 /* Use ns/us then divide to preserve precision */
3237                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3238                         pixel_size * sr_hdisplay;
3239                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3240                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3241                 srwm = I965_FIFO_SIZE - sr_entries;
3242                 if (srwm < 0)
3243                         srwm = 1;
3244                 srwm &= 0x1ff;
3245
3246                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3247                         pixel_size * 64;
3248                 sr_entries = DIV_ROUND_UP(sr_entries,
3249                                           i965_cursor_wm_info.cacheline_size);
3250                 cursor_sr = i965_cursor_wm_info.fifo_size -
3251                         (sr_entries + i965_cursor_wm_info.guard_size);
3252
3253                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3254                         cursor_sr = i965_cursor_wm_info.max_wm;
3255
3256                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3257                               "cursor %d\n", srwm, cursor_sr);
3258
3259                 if (IS_CRESTLINE(dev))
3260                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3261         } else {
3262                 /* Turn off self refresh if both pipes are enabled */
3263                 if (IS_CRESTLINE(dev))
3264                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3265                                    & ~FW_BLC_SELF_EN);
3266         }
3267
3268         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3269                       srwm);
3270
3271         /* 965 has limitations... */
3272         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3273                    (8 << 0));
3274         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3275         /* update cursor SR watermark */
3276         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3277 }
3278
3279 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3280                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3281                            int pixel_size)
3282 {
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         uint32_t fwater_lo;
3285         uint32_t fwater_hi;
3286         int total_size, cacheline_size, cwm, srwm = 1;
3287         int planea_wm, planeb_wm;
3288         struct intel_watermark_params planea_params, planeb_params;
3289         unsigned long line_time_us;
3290         int sr_clock, sr_entries = 0;
3291
3292         /* Create copies of the base settings for each pipe */
3293         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3294                 planea_params = planeb_params = i945_wm_info;
3295         else if (!IS_GEN2(dev))
3296                 planea_params = planeb_params = i915_wm_info;
3297         else
3298                 planea_params = planeb_params = i855_wm_info;
3299
3300         /* Grab a couple of global values before we overwrite them */
3301         total_size = planea_params.fifo_size;
3302         cacheline_size = planea_params.cacheline_size;
3303
3304         /* Update per-plane FIFO sizes */
3305         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3306         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3307
3308         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3309                                        pixel_size, latency_ns);
3310         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3311                                        pixel_size, latency_ns);
3312         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3313
3314         /*
3315          * Overlay gets an aggressive default since video jitter is bad.
3316          */
3317         cwm = 2;
3318
3319         /* Calc sr entries for one plane configs */
3320         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3321             (!planea_clock || !planeb_clock)) {
3322                 /* self-refresh has much higher latency */
3323                 static const int sr_latency_ns = 6000;
3324
3325                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3326                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3327
3328                 /* Use ns/us then divide to preserve precision */
3329                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3330                         pixel_size * sr_hdisplay;
3331                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3332                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3333                 srwm = total_size - sr_entries;
3334                 if (srwm < 0)
3335                         srwm = 1;
3336
3337                 if (IS_I945G(dev) || IS_I945GM(dev))
3338                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3339                 else if (IS_I915GM(dev)) {
3340                         /* 915M has a smaller SRWM field */
3341                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3342                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3343                 }
3344         } else {
3345                 /* Turn off self refresh if both pipes are enabled */
3346                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3347                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3348                                    & ~FW_BLC_SELF_EN);
3349                 } else if (IS_I915GM(dev)) {
3350                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3351                 }
3352         }
3353
3354         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3355                       planea_wm, planeb_wm, cwm, srwm);
3356
3357         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3358         fwater_hi = (cwm & 0x1f);
3359
3360         /* Set request length to 8 cachelines per fetch */
3361         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3362         fwater_hi = fwater_hi | (1 << 8);
3363
3364         I915_WRITE(FW_BLC, fwater_lo);
3365         I915_WRITE(FW_BLC2, fwater_hi);
3366 }
3367
3368 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3369                            int unused2, int unused3, int pixel_size)
3370 {
3371         struct drm_i915_private *dev_priv = dev->dev_private;
3372         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3373         int planea_wm;
3374
3375         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3376
3377         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3378                                        pixel_size, latency_ns);
3379         fwater_lo |= (3<<8) | planea_wm;
3380
3381         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3382
3383         I915_WRITE(FW_BLC, fwater_lo);
3384 }
3385
3386 #define ILK_LP0_PLANE_LATENCY           700
3387 #define ILK_LP0_CURSOR_LATENCY          1300
3388
3389 static bool ironlake_compute_wm0(struct drm_device *dev,
3390                                  int pipe,
3391                                  int *plane_wm,
3392                                  int *cursor_wm)
3393 {
3394         struct drm_crtc *crtc;
3395         int htotal, hdisplay, clock, pixel_size = 0;
3396         int line_time_us, line_count, entries;
3397
3398         crtc = intel_get_crtc_for_pipe(dev, pipe);
3399         if (crtc->fb == NULL || !crtc->enabled)
3400                 return false;
3401
3402         htotal = crtc->mode.htotal;
3403         hdisplay = crtc->mode.hdisplay;
3404         clock = crtc->mode.clock;
3405         pixel_size = crtc->fb->bits_per_pixel / 8;
3406
3407         /* Use the small buffer method to calculate plane watermark */
3408         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3409         entries = DIV_ROUND_UP(entries,
3410                                ironlake_display_wm_info.cacheline_size);
3411         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3412         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3413                 *plane_wm = ironlake_display_wm_info.max_wm;
3414
3415         /* Use the large buffer method to calculate cursor watermark */
3416         line_time_us = ((htotal * 1000) / clock);
3417         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3418         entries = line_count * 64 * pixel_size;
3419         entries = DIV_ROUND_UP(entries,
3420                                ironlake_cursor_wm_info.cacheline_size);
3421         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3422         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3423                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3424
3425         return true;
3426 }
3427
3428 static void ironlake_update_wm(struct drm_device *dev,
3429                                int planea_clock, int planeb_clock,
3430                                int sr_hdisplay, int sr_htotal,
3431                                int pixel_size)
3432 {
3433         struct drm_i915_private *dev_priv = dev->dev_private;
3434         int plane_wm, cursor_wm, enabled;
3435         int tmp;
3436
3437         enabled = 0;
3438         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3439                 I915_WRITE(WM0_PIPEA_ILK,
3440                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3441                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3442                               " plane %d, " "cursor: %d\n",
3443                               plane_wm, cursor_wm);
3444                 enabled++;
3445         }
3446
3447         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3448                 I915_WRITE(WM0_PIPEB_ILK,
3449                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3450                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3451                               " plane %d, cursor: %d\n",
3452                               plane_wm, cursor_wm);
3453                 enabled++;
3454         }
3455
3456         /*
3457          * Calculate and update the self-refresh watermark only when one
3458          * display plane is used.
3459          */
3460         tmp = 0;
3461         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3462                 unsigned long line_time_us;
3463                 int small, large, plane_fbc;
3464                 int sr_clock, entries;
3465                 int line_count, line_size;
3466                 /* Read the self-refresh latency. The unit is 0.5us */
3467                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3468
3469                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3470                 line_time_us = (sr_htotal * 1000) / sr_clock;
3471
3472                 /* Use ns/us then divide to preserve precision */
3473                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3474                         / 1000;
3475                 line_size = sr_hdisplay * pixel_size;
3476
3477                 /* Use the minimum of the small and large buffer method for primary */
3478                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3479                 large = line_count * line_size;
3480
3481                 entries = DIV_ROUND_UP(min(small, large),
3482                                        ironlake_display_srwm_info.cacheline_size);
3483
3484                 plane_fbc = entries * 64;
3485                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3486
3487                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3488                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3489                         plane_wm = ironlake_display_srwm_info.max_wm;
3490
3491                 /* calculate the self-refresh watermark for display cursor */
3492                 entries = line_count * pixel_size * 64;
3493                 entries = DIV_ROUND_UP(entries,
3494                                        ironlake_cursor_srwm_info.cacheline_size);
3495
3496                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3497                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3498                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3499
3500                 /* configure watermark and enable self-refresh */
3501                 tmp = (WM1_LP_SR_EN |
3502                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3503                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3504                        (plane_wm << WM1_LP_SR_SHIFT) |
3505                        cursor_wm);
3506                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3507                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3508         }
3509         I915_WRITE(WM1_LP_ILK, tmp);
3510         /* XXX setup WM2 and WM3 */
3511 }
3512
3513 /**
3514  * intel_update_watermarks - update FIFO watermark values based on current modes
3515  *
3516  * Calculate watermark values for the various WM regs based on current mode
3517  * and plane configuration.
3518  *
3519  * There are several cases to deal with here:
3520  *   - normal (i.e. non-self-refresh)
3521  *   - self-refresh (SR) mode
3522  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3523  *   - lines are small relative to FIFO size (buffer can hold more than 2
3524  *     lines), so need to account for TLB latency
3525  *
3526  *   The normal calculation is:
3527  *     watermark = dotclock * bytes per pixel * latency
3528  *   where latency is platform & configuration dependent (we assume pessimal
3529  *   values here).
3530  *
3531  *   The SR calculation is:
3532  *     watermark = (trunc(latency/line time)+1) * surface width *
3533  *       bytes per pixel
3534  *   where
3535  *     line time = htotal / dotclock
3536  *     surface width = hdisplay for normal plane and 64 for cursor
3537  *   and latency is assumed to be high, as above.
3538  *
3539  * The final value programmed to the register should always be rounded up,
3540  * and include an extra 2 entries to account for clock crossings.
3541  *
3542  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3543  * to set the non-SR watermarks to 8.
3544  */
3545 static void intel_update_watermarks(struct drm_device *dev)
3546 {
3547         struct drm_i915_private *dev_priv = dev->dev_private;
3548         struct drm_crtc *crtc;
3549         int sr_hdisplay = 0;
3550         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3551         int enabled = 0, pixel_size = 0;
3552         int sr_htotal = 0;
3553
3554         if (!dev_priv->display.update_wm)
3555                 return;
3556
3557         /* Get the clock config from both planes */
3558         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3559                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3560                 if (intel_crtc->active) {
3561                         enabled++;
3562                         if (intel_crtc->plane == 0) {
3563                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3564                                               intel_crtc->pipe, crtc->mode.clock);
3565                                 planea_clock = crtc->mode.clock;
3566                         } else {
3567                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3568                                               intel_crtc->pipe, crtc->mode.clock);
3569                                 planeb_clock = crtc->mode.clock;
3570                         }
3571                         sr_hdisplay = crtc->mode.hdisplay;
3572                         sr_clock = crtc->mode.clock;
3573                         sr_htotal = crtc->mode.htotal;
3574                         if (crtc->fb)
3575                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3576                         else
3577                                 pixel_size = 4; /* by default */
3578                 }
3579         }
3580
3581         if (enabled <= 0)
3582                 return;
3583
3584         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3585                                     sr_hdisplay, sr_htotal, pixel_size);
3586 }
3587
3588 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3589                                struct drm_display_mode *mode,
3590                                struct drm_display_mode *adjusted_mode,
3591                                int x, int y,
3592                                struct drm_framebuffer *old_fb)
3593 {
3594         struct drm_device *dev = crtc->dev;
3595         struct drm_i915_private *dev_priv = dev->dev_private;
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         int pipe = intel_crtc->pipe;
3598         int plane = intel_crtc->plane;
3599         u32 fp_reg, dpll_reg;
3600         int refclk, num_connectors = 0;
3601         intel_clock_t clock, reduced_clock;
3602         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3603         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3604         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3605         struct intel_encoder *has_edp_encoder = NULL;
3606         struct drm_mode_config *mode_config = &dev->mode_config;
3607         struct intel_encoder *encoder;
3608         const intel_limit_t *limit;
3609         int ret;
3610         struct fdi_m_n m_n = {0};
3611         u32 reg, temp;
3612         int target_clock;
3613
3614         drm_vblank_pre_modeset(dev, pipe);
3615
3616         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3617                 if (encoder->base.crtc != crtc)
3618                         continue;
3619
3620                 switch (encoder->type) {
3621                 case INTEL_OUTPUT_LVDS:
3622                         is_lvds = true;
3623                         break;
3624                 case INTEL_OUTPUT_SDVO:
3625                 case INTEL_OUTPUT_HDMI:
3626                         is_sdvo = true;
3627                         if (encoder->needs_tv_clock)
3628                                 is_tv = true;
3629                         break;
3630                 case INTEL_OUTPUT_DVO:
3631                         is_dvo = true;
3632                         break;
3633                 case INTEL_OUTPUT_TVOUT:
3634                         is_tv = true;
3635                         break;
3636                 case INTEL_OUTPUT_ANALOG:
3637                         is_crt = true;
3638                         break;
3639                 case INTEL_OUTPUT_DISPLAYPORT:
3640                         is_dp = true;
3641                         break;
3642                 case INTEL_OUTPUT_EDP:
3643                         has_edp_encoder = encoder;
3644                         break;
3645                 }
3646
3647                 num_connectors++;
3648         }
3649
3650         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3651                 refclk = dev_priv->lvds_ssc_freq * 1000;
3652                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3653                               refclk / 1000);
3654         } else if (!IS_GEN2(dev)) {
3655                 refclk = 96000;
3656                 if (HAS_PCH_SPLIT(dev) &&
3657                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3658                         refclk = 120000; /* 120Mhz refclk */
3659         } else {
3660                 refclk = 48000;
3661         }
3662
3663         /*
3664          * Returns a set of divisors for the desired target clock with the given
3665          * refclk, or FALSE.  The returned values represent the clock equation:
3666          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3667          */
3668         limit = intel_limit(crtc);
3669         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3670         if (!ok) {
3671                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3672                 drm_vblank_post_modeset(dev, pipe);
3673                 return -EINVAL;
3674         }
3675
3676         /* Ensure that the cursor is valid for the new mode before changing... */
3677         intel_crtc_update_cursor(crtc, true);
3678
3679         if (is_lvds && dev_priv->lvds_downclock_avail) {
3680                 has_reduced_clock = limit->find_pll(limit, crtc,
3681                                                     dev_priv->lvds_downclock,
3682                                                     refclk,
3683                                                     &reduced_clock);
3684                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3685                         /*
3686                          * If the different P is found, it means that we can't
3687                          * switch the display clock by using the FP0/FP1.
3688                          * In such case we will disable the LVDS downclock
3689                          * feature.
3690                          */
3691                         DRM_DEBUG_KMS("Different P is found for "
3692                                       "LVDS clock/downclock\n");
3693                         has_reduced_clock = 0;
3694                 }
3695         }
3696         /* SDVO TV has fixed PLL values depend on its clock range,
3697            this mirrors vbios setting. */
3698         if (is_sdvo && is_tv) {
3699                 if (adjusted_mode->clock >= 100000
3700                     && adjusted_mode->clock < 140500) {
3701                         clock.p1 = 2;
3702                         clock.p2 = 10;
3703                         clock.n = 3;
3704                         clock.m1 = 16;
3705                         clock.m2 = 8;
3706                 } else if (adjusted_mode->clock >= 140500
3707                            && adjusted_mode->clock <= 200000) {
3708                         clock.p1 = 1;
3709                         clock.p2 = 10;
3710                         clock.n = 6;
3711                         clock.m1 = 12;
3712                         clock.m2 = 8;
3713                 }
3714         }
3715
3716         /* FDI link */
3717         if (HAS_PCH_SPLIT(dev)) {
3718                 int lane = 0, link_bw, bpp;
3719                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3720                    according to current link config */
3721                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3722                         target_clock = mode->clock;
3723                         intel_edp_link_config(has_edp_encoder,
3724                                               &lane, &link_bw);
3725                 } else {
3726                         /* [e]DP over FDI requires target mode clock
3727                            instead of link clock */
3728                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3729                                 target_clock = mode->clock;
3730                         else
3731                                 target_clock = adjusted_mode->clock;
3732
3733                         /* FDI is a binary signal running at ~2.7GHz, encoding
3734                          * each output octet as 10 bits. The actual frequency
3735                          * is stored as a divider into a 100MHz clock, and the
3736                          * mode pixel clock is stored in units of 1KHz.
3737                          * Hence the bw of each lane in terms of the mode signal
3738                          * is:
3739                          */
3740                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3741                 }
3742
3743                 /* determine panel color depth */
3744                 temp = I915_READ(PIPECONF(pipe));
3745                 temp &= ~PIPE_BPC_MASK;
3746                 if (is_lvds) {
3747                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3748                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3749                                 temp |= PIPE_8BPC;
3750                         else
3751                                 temp |= PIPE_6BPC;
3752                 } else if (has_edp_encoder) {
3753                         switch (dev_priv->edp.bpp/3) {
3754                         case 8:
3755                                 temp |= PIPE_8BPC;
3756                                 break;
3757                         case 10:
3758                                 temp |= PIPE_10BPC;
3759                                 break;
3760                         case 6:
3761                                 temp |= PIPE_6BPC;
3762                                 break;
3763                         case 12:
3764                                 temp |= PIPE_12BPC;
3765                                 break;
3766                         }
3767                 } else
3768                         temp |= PIPE_8BPC;
3769                 I915_WRITE(PIPECONF(pipe), temp);
3770
3771                 switch (temp & PIPE_BPC_MASK) {
3772                 case PIPE_8BPC:
3773                         bpp = 24;
3774                         break;
3775                 case PIPE_10BPC:
3776                         bpp = 30;
3777                         break;
3778                 case PIPE_6BPC:
3779                         bpp = 18;
3780                         break;
3781                 case PIPE_12BPC:
3782                         bpp = 36;
3783                         break;
3784                 default:
3785                         DRM_ERROR("unknown pipe bpc value\n");
3786                         bpp = 24;
3787                 }
3788
3789                 if (!lane) {
3790                         /*
3791                          * Account for spread spectrum to avoid
3792                          * oversubscribing the link. Max center spread
3793                          * is 2.5%; use 5% for safety's sake.
3794                          */
3795                         u32 bps = target_clock * bpp * 21 / 20;
3796                         lane = bps / (link_bw * 8) + 1;
3797                 }
3798
3799                 intel_crtc->fdi_lanes = lane;
3800
3801                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3802         }
3803
3804         /* Ironlake: try to setup display ref clock before DPLL
3805          * enabling. This is only under driver's control after
3806          * PCH B stepping, previous chipset stepping should be
3807          * ignoring this setting.
3808          */
3809         if (HAS_PCH_SPLIT(dev)) {
3810                 temp = I915_READ(PCH_DREF_CONTROL);
3811                 /* Always enable nonspread source */
3812                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3813                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3814                 temp &= ~DREF_SSC_SOURCE_MASK;
3815                 temp |= DREF_SSC_SOURCE_ENABLE;
3816                 I915_WRITE(PCH_DREF_CONTROL, temp);
3817
3818                 POSTING_READ(PCH_DREF_CONTROL);
3819                 udelay(200);
3820
3821                 if (has_edp_encoder) {
3822                         if (dev_priv->lvds_use_ssc) {
3823                                 temp |= DREF_SSC1_ENABLE;
3824                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3825
3826                                 POSTING_READ(PCH_DREF_CONTROL);
3827                                 udelay(200);
3828                         }
3829                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3830
3831                         /* Enable CPU source on CPU attached eDP */
3832                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3833                                 if (dev_priv->lvds_use_ssc)
3834                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3835                                 else
3836                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3837                         } else {
3838                                 /* Enable SSC on PCH eDP if needed */
3839                                 if (dev_priv->lvds_use_ssc) {
3840                                         DRM_ERROR("enabling SSC on PCH\n");
3841                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3842                                 }
3843                         }
3844                         I915_WRITE(PCH_DREF_CONTROL, temp);
3845                         POSTING_READ(PCH_DREF_CONTROL);
3846                         udelay(200);
3847                 }
3848         }
3849
3850         if (IS_PINEVIEW(dev)) {
3851                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3852                 if (has_reduced_clock)
3853                         fp2 = (1 << reduced_clock.n) << 16 |
3854                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3855         } else {
3856                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3857                 if (has_reduced_clock)
3858                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3859                                 reduced_clock.m2;
3860         }
3861
3862         dpll = 0;
3863         if (!HAS_PCH_SPLIT(dev))
3864                 dpll = DPLL_VGA_MODE_DIS;
3865
3866         if (!IS_GEN2(dev)) {
3867                 if (is_lvds)
3868                         dpll |= DPLLB_MODE_LVDS;
3869                 else
3870                         dpll |= DPLLB_MODE_DAC_SERIAL;
3871                 if (is_sdvo) {
3872                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3873                         if (pixel_multiplier > 1) {
3874                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3875                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3876                                 else if (HAS_PCH_SPLIT(dev))
3877                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3878                         }
3879                         dpll |= DPLL_DVO_HIGH_SPEED;
3880                 }
3881                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3882                         dpll |= DPLL_DVO_HIGH_SPEED;
3883
3884                 /* compute bitmask from p1 value */
3885                 if (IS_PINEVIEW(dev))
3886                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3887                 else {
3888                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3889                         /* also FPA1 */
3890                         if (HAS_PCH_SPLIT(dev))
3891                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3892                         if (IS_G4X(dev) && has_reduced_clock)
3893                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3894                 }
3895                 switch (clock.p2) {
3896                 case 5:
3897                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3898                         break;
3899                 case 7:
3900                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3901                         break;
3902                 case 10:
3903                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3904                         break;
3905                 case 14:
3906                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3907                         break;
3908                 }
3909                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3910                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3911         } else {
3912                 if (is_lvds) {
3913                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3914                 } else {
3915                         if (clock.p1 == 2)
3916                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3917                         else
3918                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3919                         if (clock.p2 == 4)
3920                                 dpll |= PLL_P2_DIVIDE_BY_4;
3921                 }
3922         }
3923
3924         if (is_sdvo && is_tv)
3925                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3926         else if (is_tv)
3927                 /* XXX: just matching BIOS for now */
3928                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3929                 dpll |= 3;
3930         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3931                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3932         else
3933                 dpll |= PLL_REF_INPUT_DREFCLK;
3934
3935         /* setup pipeconf */
3936         pipeconf = I915_READ(PIPECONF(pipe));
3937
3938         /* Set up the display plane register */
3939         dspcntr = DISPPLANE_GAMMA_ENABLE;
3940
3941         /* Ironlake's plane is forced to pipe, bit 24 is to
3942            enable color space conversion */
3943         if (!HAS_PCH_SPLIT(dev)) {
3944                 if (pipe == 0)
3945                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3946                 else
3947                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3948         }
3949
3950         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3951                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3952                  * core speed.
3953                  *
3954                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3955                  * pipe == 0 check?
3956                  */
3957                 if (mode->clock >
3958                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3959                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3960                 else
3961                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3962         }
3963
3964         dspcntr |= DISPLAY_PLANE_ENABLE;
3965         pipeconf |= PIPECONF_ENABLE;
3966         dpll |= DPLL_VCO_ENABLE;
3967
3968         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3969         drm_mode_debug_printmodeline(mode);
3970
3971         /* assign to Ironlake registers */
3972         if (HAS_PCH_SPLIT(dev)) {
3973                 fp_reg = PCH_FP0(pipe);
3974                 dpll_reg = PCH_DPLL(pipe);
3975         } else {
3976                 fp_reg = FP0(pipe);
3977                 dpll_reg = DPLL(pipe);
3978         }
3979
3980         /* PCH eDP needs FDI, but CPU eDP does not */
3981         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3982                 I915_WRITE(fp_reg, fp);
3983                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3984
3985                 POSTING_READ(dpll_reg);
3986                 udelay(150);
3987         }
3988
3989         /* enable transcoder DPLL */
3990         if (HAS_PCH_CPT(dev)) {
3991                 temp = I915_READ(PCH_DPLL_SEL);
3992                 if (pipe == 0)
3993                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3994                 else
3995                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3996                 I915_WRITE(PCH_DPLL_SEL, temp);
3997
3998                 POSTING_READ(PCH_DPLL_SEL);
3999                 udelay(150);
4000         }
4001
4002         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4003          * This is an exception to the general rule that mode_set doesn't turn
4004          * things on.
4005          */
4006         if (is_lvds) {
4007                 reg = LVDS;
4008                 if (HAS_PCH_SPLIT(dev))
4009                         reg = PCH_LVDS;
4010
4011                 temp = I915_READ(reg);
4012                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4013                 if (pipe == 1) {
4014                         if (HAS_PCH_CPT(dev))
4015                                 temp |= PORT_TRANS_B_SEL_CPT;
4016                         else
4017                                 temp |= LVDS_PIPEB_SELECT;
4018                 } else {
4019                         if (HAS_PCH_CPT(dev))
4020                                 temp &= ~PORT_TRANS_SEL_MASK;
4021                         else
4022                                 temp &= ~LVDS_PIPEB_SELECT;
4023                 }
4024                 /* set the corresponsding LVDS_BORDER bit */
4025                 temp |= dev_priv->lvds_border_bits;
4026                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4027                  * set the DPLLs for dual-channel mode or not.
4028                  */
4029                 if (clock.p2 == 7)
4030                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4031                 else
4032                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4033
4034                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4035                  * appropriately here, but we need to look more thoroughly into how
4036                  * panels behave in the two modes.
4037                  */
4038                 /* set the dithering flag on non-PCH LVDS as needed */
4039                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4040                         if (dev_priv->lvds_dither)
4041                                 temp |= LVDS_ENABLE_DITHER;
4042                         else
4043                                 temp &= ~LVDS_ENABLE_DITHER;
4044                 }
4045                 I915_WRITE(reg, temp);
4046         }
4047
4048         /* set the dithering flag and clear for anything other than a panel. */
4049         if (HAS_PCH_SPLIT(dev)) {
4050                 pipeconf &= ~PIPECONF_DITHER_EN;
4051                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4052                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4053                         pipeconf |= PIPECONF_DITHER_EN;
4054                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4055                 }
4056         }
4057
4058         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4059                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4060         } else if (HAS_PCH_SPLIT(dev)) {
4061                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4062                 if (pipe == 0) {
4063                         I915_WRITE(TRANSA_DATA_M1, 0);
4064                         I915_WRITE(TRANSA_DATA_N1, 0);
4065                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4066                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4067                 } else {
4068                         I915_WRITE(TRANSB_DATA_M1, 0);
4069                         I915_WRITE(TRANSB_DATA_N1, 0);
4070                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4071                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4072                 }
4073         }
4074
4075         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4076                 I915_WRITE(fp_reg, fp);
4077                 I915_WRITE(dpll_reg, dpll);
4078
4079                 /* Wait for the clocks to stabilize. */
4080                 POSTING_READ(dpll_reg);
4081                 udelay(150);
4082
4083                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4084                         temp = 0;
4085                         if (is_sdvo) {
4086                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4087                                 if (temp > 1)
4088                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4089                                 else
4090                                         temp = 0;
4091                         }
4092                         I915_WRITE(DPLL_MD(pipe), temp);
4093                 } else {
4094                         /* write it again -- the BIOS does, after all */
4095                         I915_WRITE(dpll_reg, dpll);
4096                 }
4097
4098                 /* Wait for the clocks to stabilize. */
4099                 POSTING_READ(dpll_reg);
4100                 udelay(150);
4101         }
4102
4103         intel_crtc->lowfreq_avail = false;
4104         if (is_lvds && has_reduced_clock && i915_powersave) {
4105                 I915_WRITE(fp_reg + 4, fp2);
4106                 intel_crtc->lowfreq_avail = true;
4107                 if (HAS_PIPE_CXSR(dev)) {
4108                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4109                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4110                 }
4111         } else {
4112                 I915_WRITE(fp_reg + 4, fp);
4113                 if (HAS_PIPE_CXSR(dev)) {
4114                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4115                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4116                 }
4117         }
4118
4119         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4120                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4121                 /* the chip adds 2 halflines automatically */
4122                 adjusted_mode->crtc_vdisplay -= 1;
4123                 adjusted_mode->crtc_vtotal -= 1;
4124                 adjusted_mode->crtc_vblank_start -= 1;
4125                 adjusted_mode->crtc_vblank_end -= 1;
4126                 adjusted_mode->crtc_vsync_end -= 1;
4127                 adjusted_mode->crtc_vsync_start -= 1;
4128         } else
4129                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4130
4131         I915_WRITE(HTOTAL(pipe),
4132                    (adjusted_mode->crtc_hdisplay - 1) |
4133                    ((adjusted_mode->crtc_htotal - 1) << 16));
4134         I915_WRITE(HBLANK(pipe),
4135                    (adjusted_mode->crtc_hblank_start - 1) |
4136                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4137         I915_WRITE(HSYNC(pipe),
4138                    (adjusted_mode->crtc_hsync_start - 1) |
4139                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4140
4141         I915_WRITE(VTOTAL(pipe),
4142                    (adjusted_mode->crtc_vdisplay - 1) |
4143                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4144         I915_WRITE(VBLANK(pipe),
4145                    (adjusted_mode->crtc_vblank_start - 1) |
4146                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4147         I915_WRITE(VSYNC(pipe),
4148                    (adjusted_mode->crtc_vsync_start - 1) |
4149                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4150
4151         /* pipesrc and dspsize control the size that is scaled from,
4152          * which should always be the user's requested size.
4153          */
4154         if (!HAS_PCH_SPLIT(dev)) {
4155                 I915_WRITE(DSPSIZE(plane),
4156                            ((mode->vdisplay - 1) << 16) |
4157                            (mode->hdisplay - 1));
4158                 I915_WRITE(DSPPOS(plane), 0);
4159         }
4160         I915_WRITE(PIPESRC(pipe),
4161                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4162
4163         if (HAS_PCH_SPLIT(dev)) {
4164                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4165                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4166                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4167                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4168
4169                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4170                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4171                 }
4172         }
4173
4174         I915_WRITE(PIPECONF(pipe), pipeconf);
4175         POSTING_READ(PIPECONF(pipe));
4176
4177         intel_wait_for_vblank(dev, pipe);
4178
4179         if (IS_GEN5(dev)) {
4180                 /* enable address swizzle for tiling buffer */
4181                 temp = I915_READ(DISP_ARB_CTL);
4182                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4183         }
4184
4185         I915_WRITE(DSPCNTR(plane), dspcntr);
4186
4187         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4188
4189         intel_update_watermarks(dev);
4190
4191         drm_vblank_post_modeset(dev, pipe);
4192
4193         return ret;
4194 }
4195
4196 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4197 void intel_crtc_load_lut(struct drm_crtc *crtc)
4198 {
4199         struct drm_device *dev = crtc->dev;
4200         struct drm_i915_private *dev_priv = dev->dev_private;
4201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4202         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4203         int i;
4204
4205         /* The clocks have to be on to load the palette. */
4206         if (!crtc->enabled)
4207                 return;
4208
4209         /* use legacy palette for Ironlake */
4210         if (HAS_PCH_SPLIT(dev))
4211                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4212                                                    LGC_PALETTE_B;
4213
4214         for (i = 0; i < 256; i++) {
4215                 I915_WRITE(palreg + 4 * i,
4216                            (intel_crtc->lut_r[i] << 16) |
4217                            (intel_crtc->lut_g[i] << 8) |
4218                            intel_crtc->lut_b[i]);
4219         }
4220 }
4221
4222 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4223 {
4224         struct drm_device *dev = crtc->dev;
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4227         bool visible = base != 0;
4228         u32 cntl;
4229
4230         if (intel_crtc->cursor_visible == visible)
4231                 return;
4232
4233         cntl = I915_READ(CURACNTR);
4234         if (visible) {
4235                 /* On these chipsets we can only modify the base whilst
4236                  * the cursor is disabled.
4237                  */
4238                 I915_WRITE(CURABASE, base);
4239
4240                 cntl &= ~(CURSOR_FORMAT_MASK);
4241                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4242                 cntl |= CURSOR_ENABLE |
4243                         CURSOR_GAMMA_ENABLE |
4244                         CURSOR_FORMAT_ARGB;
4245         } else
4246                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4247         I915_WRITE(CURACNTR, cntl);
4248
4249         intel_crtc->cursor_visible = visible;
4250 }
4251
4252 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4253 {
4254         struct drm_device *dev = crtc->dev;
4255         struct drm_i915_private *dev_priv = dev->dev_private;
4256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4257         int pipe = intel_crtc->pipe;
4258         bool visible = base != 0;
4259
4260         if (intel_crtc->cursor_visible != visible) {
4261                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4262                 if (base) {
4263                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4264                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4265                         cntl |= pipe << 28; /* Connect to correct pipe */
4266                 } else {
4267                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4268                         cntl |= CURSOR_MODE_DISABLE;
4269                 }
4270                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4271
4272                 intel_crtc->cursor_visible = visible;
4273         }
4274         /* and commit changes on next vblank */
4275         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4276 }
4277
4278 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4279 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4280                                      bool on)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285         int pipe = intel_crtc->pipe;
4286         int x = intel_crtc->cursor_x;
4287         int y = intel_crtc->cursor_y;
4288         u32 base, pos;
4289         bool visible;
4290
4291         pos = 0;
4292
4293         if (on && crtc->enabled && crtc->fb) {
4294                 base = intel_crtc->cursor_addr;
4295                 if (x > (int) crtc->fb->width)
4296                         base = 0;
4297
4298                 if (y > (int) crtc->fb->height)
4299                         base = 0;
4300         } else
4301                 base = 0;
4302
4303         if (x < 0) {
4304                 if (x + intel_crtc->cursor_width < 0)
4305                         base = 0;
4306
4307                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4308                 x = -x;
4309         }
4310         pos |= x << CURSOR_X_SHIFT;
4311
4312         if (y < 0) {
4313                 if (y + intel_crtc->cursor_height < 0)
4314                         base = 0;
4315
4316                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4317                 y = -y;
4318         }
4319         pos |= y << CURSOR_Y_SHIFT;
4320
4321         visible = base != 0;
4322         if (!visible && !intel_crtc->cursor_visible)
4323                 return;
4324
4325         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4326         if (IS_845G(dev) || IS_I865G(dev))
4327                 i845_update_cursor(crtc, base);
4328         else
4329                 i9xx_update_cursor(crtc, base);
4330
4331         if (visible)
4332                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4333 }
4334
4335 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4336                                  struct drm_file *file_priv,
4337                                  uint32_t handle,
4338                                  uint32_t width, uint32_t height)
4339 {
4340         struct drm_device *dev = crtc->dev;
4341         struct drm_i915_private *dev_priv = dev->dev_private;
4342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4343         struct drm_gem_object *bo;
4344         struct drm_i915_gem_object *obj_priv;
4345         uint32_t addr;
4346         int ret;
4347
4348         DRM_DEBUG_KMS("\n");
4349
4350         /* if we want to turn off the cursor ignore width and height */
4351         if (!handle) {
4352                 DRM_DEBUG_KMS("cursor off\n");
4353                 addr = 0;
4354                 bo = NULL;
4355                 mutex_lock(&dev->struct_mutex);
4356                 goto finish;
4357         }
4358
4359         /* Currently we only support 64x64 cursors */
4360         if (width != 64 || height != 64) {
4361                 DRM_ERROR("we currently only support 64x64 cursors\n");
4362                 return -EINVAL;
4363         }
4364
4365         bo = drm_gem_object_lookup(dev, file_priv, handle);
4366         if (!bo)
4367                 return -ENOENT;
4368
4369         obj_priv = to_intel_bo(bo);
4370
4371         if (bo->size < width * height * 4) {
4372                 DRM_ERROR("buffer is to small\n");
4373                 ret = -ENOMEM;
4374                 goto fail;
4375         }
4376
4377         /* we only need to pin inside GTT if cursor is non-phy */
4378         mutex_lock(&dev->struct_mutex);
4379         if (!dev_priv->info->cursor_needs_physical) {
4380                 ret = i915_gem_object_pin(bo, PAGE_SIZE, true);
4381                 if (ret) {
4382                         DRM_ERROR("failed to pin cursor bo\n");
4383                         goto fail_locked;
4384                 }
4385
4386                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4387                 if (ret) {
4388                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4389                         goto fail_unpin;
4390                 }
4391
4392                 addr = obj_priv->gtt_offset;
4393         } else {
4394                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4395                 ret = i915_gem_attach_phys_object(dev, bo,
4396                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4397                                                   align);
4398                 if (ret) {
4399                         DRM_ERROR("failed to attach phys object\n");
4400                         goto fail_locked;
4401                 }
4402                 addr = obj_priv->phys_obj->handle->busaddr;
4403         }
4404
4405         if (IS_GEN2(dev))
4406                 I915_WRITE(CURSIZE, (height << 12) | width);
4407
4408  finish:
4409         if (intel_crtc->cursor_bo) {
4410                 if (dev_priv->info->cursor_needs_physical) {
4411                         if (intel_crtc->cursor_bo != bo)
4412                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4413                 } else
4414                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4415                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4416         }
4417
4418         mutex_unlock(&dev->struct_mutex);
4419
4420         intel_crtc->cursor_addr = addr;
4421         intel_crtc->cursor_bo = bo;
4422         intel_crtc->cursor_width = width;
4423         intel_crtc->cursor_height = height;
4424
4425         intel_crtc_update_cursor(crtc, true);
4426
4427         return 0;
4428 fail_unpin:
4429         i915_gem_object_unpin(bo);
4430 fail_locked:
4431         mutex_unlock(&dev->struct_mutex);
4432 fail:
4433         drm_gem_object_unreference_unlocked(bo);
4434         return ret;
4435 }
4436
4437 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4438 {
4439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4440
4441         intel_crtc->cursor_x = x;
4442         intel_crtc->cursor_y = y;
4443
4444         intel_crtc_update_cursor(crtc, true);
4445
4446         return 0;
4447 }
4448
4449 /** Sets the color ramps on behalf of RandR */
4450 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4451                                  u16 blue, int regno)
4452 {
4453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4454
4455         intel_crtc->lut_r[regno] = red >> 8;
4456         intel_crtc->lut_g[regno] = green >> 8;
4457         intel_crtc->lut_b[regno] = blue >> 8;
4458 }
4459
4460 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4461                              u16 *blue, int regno)
4462 {
4463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4464
4465         *red = intel_crtc->lut_r[regno] << 8;
4466         *green = intel_crtc->lut_g[regno] << 8;
4467         *blue = intel_crtc->lut_b[regno] << 8;
4468 }
4469
4470 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4471                                  u16 *blue, uint32_t start, uint32_t size)
4472 {
4473         int end = (start + size > 256) ? 256 : start + size, i;
4474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475
4476         for (i = start; i < end; i++) {
4477                 intel_crtc->lut_r[i] = red[i] >> 8;
4478                 intel_crtc->lut_g[i] = green[i] >> 8;
4479                 intel_crtc->lut_b[i] = blue[i] >> 8;
4480         }
4481
4482         intel_crtc_load_lut(crtc);
4483 }
4484
4485 /**
4486  * Get a pipe with a simple mode set on it for doing load-based monitor
4487  * detection.
4488  *
4489  * It will be up to the load-detect code to adjust the pipe as appropriate for
4490  * its requirements.  The pipe will be connected to no other encoders.
4491  *
4492  * Currently this code will only succeed if there is a pipe with no encoders
4493  * configured for it.  In the future, it could choose to temporarily disable
4494  * some outputs to free up a pipe for its use.
4495  *
4496  * \return crtc, or NULL if no pipes are available.
4497  */
4498
4499 /* VESA 640x480x72Hz mode to set on the pipe */
4500 static struct drm_display_mode load_detect_mode = {
4501         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4502                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4503 };
4504
4505 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4506                                             struct drm_connector *connector,
4507                                             struct drm_display_mode *mode,
4508                                             int *dpms_mode)
4509 {
4510         struct intel_crtc *intel_crtc;
4511         struct drm_crtc *possible_crtc;
4512         struct drm_crtc *supported_crtc =NULL;
4513         struct drm_encoder *encoder = &intel_encoder->base;
4514         struct drm_crtc *crtc = NULL;
4515         struct drm_device *dev = encoder->dev;
4516         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4517         struct drm_crtc_helper_funcs *crtc_funcs;
4518         int i = -1;
4519
4520         /*
4521          * Algorithm gets a little messy:
4522          *   - if the connector already has an assigned crtc, use it (but make
4523          *     sure it's on first)
4524          *   - try to find the first unused crtc that can drive this connector,
4525          *     and use that if we find one
4526          *   - if there are no unused crtcs available, try to use the first
4527          *     one we found that supports the connector
4528          */
4529
4530         /* See if we already have a CRTC for this connector */
4531         if (encoder->crtc) {
4532                 crtc = encoder->crtc;
4533                 /* Make sure the crtc and connector are running */
4534                 intel_crtc = to_intel_crtc(crtc);
4535                 *dpms_mode = intel_crtc->dpms_mode;
4536                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4537                         crtc_funcs = crtc->helper_private;
4538                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4539                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4540                 }
4541                 return crtc;
4542         }
4543
4544         /* Find an unused one (if possible) */
4545         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4546                 i++;
4547                 if (!(encoder->possible_crtcs & (1 << i)))
4548                         continue;
4549                 if (!possible_crtc->enabled) {
4550                         crtc = possible_crtc;
4551                         break;
4552                 }
4553                 if (!supported_crtc)
4554                         supported_crtc = possible_crtc;
4555         }
4556
4557         /*
4558          * If we didn't find an unused CRTC, don't use any.
4559          */
4560         if (!crtc) {
4561                 return NULL;
4562         }
4563
4564         encoder->crtc = crtc;
4565         connector->encoder = encoder;
4566         intel_encoder->load_detect_temp = true;
4567
4568         intel_crtc = to_intel_crtc(crtc);
4569         *dpms_mode = intel_crtc->dpms_mode;
4570
4571         if (!crtc->enabled) {
4572                 if (!mode)
4573                         mode = &load_detect_mode;
4574                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4575         } else {
4576                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4577                         crtc_funcs = crtc->helper_private;
4578                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4579                 }
4580
4581                 /* Add this connector to the crtc */
4582                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4583                 encoder_funcs->commit(encoder);
4584         }
4585         /* let the connector get through one full cycle before testing */
4586         intel_wait_for_vblank(dev, intel_crtc->pipe);
4587
4588         return crtc;
4589 }
4590
4591 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4592                                     struct drm_connector *connector, int dpms_mode)
4593 {
4594         struct drm_encoder *encoder = &intel_encoder->base;
4595         struct drm_device *dev = encoder->dev;
4596         struct drm_crtc *crtc = encoder->crtc;
4597         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4598         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4599
4600         if (intel_encoder->load_detect_temp) {
4601                 encoder->crtc = NULL;
4602                 connector->encoder = NULL;
4603                 intel_encoder->load_detect_temp = false;
4604                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4605                 drm_helper_disable_unused_functions(dev);
4606         }
4607
4608         /* Switch crtc and encoder back off if necessary */
4609         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4610                 if (encoder->crtc == crtc)
4611                         encoder_funcs->dpms(encoder, dpms_mode);
4612                 crtc_funcs->dpms(crtc, dpms_mode);
4613         }
4614 }
4615
4616 /* Returns the clock of the currently programmed mode of the given pipe. */
4617 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4618 {
4619         struct drm_i915_private *dev_priv = dev->dev_private;
4620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4621         int pipe = intel_crtc->pipe;
4622         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4623         u32 fp;
4624         intel_clock_t clock;
4625
4626         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4627                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4628         else
4629                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4630
4631         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4632         if (IS_PINEVIEW(dev)) {
4633                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4634                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4635         } else {
4636                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4637                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4638         }
4639
4640         if (!IS_GEN2(dev)) {
4641                 if (IS_PINEVIEW(dev))
4642                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4643                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4644                 else
4645                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4646                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4647
4648                 switch (dpll & DPLL_MODE_MASK) {
4649                 case DPLLB_MODE_DAC_SERIAL:
4650                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4651                                 5 : 10;
4652                         break;
4653                 case DPLLB_MODE_LVDS:
4654                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4655                                 7 : 14;
4656                         break;
4657                 default:
4658                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4659                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4660                         return 0;
4661                 }
4662
4663                 /* XXX: Handle the 100Mhz refclk */
4664                 intel_clock(dev, 96000, &clock);
4665         } else {
4666                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4667
4668                 if (is_lvds) {
4669                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4670                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4671                         clock.p2 = 14;
4672
4673                         if ((dpll & PLL_REF_INPUT_MASK) ==
4674                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4675                                 /* XXX: might not be 66MHz */
4676                                 intel_clock(dev, 66000, &clock);
4677                         } else
4678                                 intel_clock(dev, 48000, &clock);
4679                 } else {
4680                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4681                                 clock.p1 = 2;
4682                         else {
4683                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4684                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4685                         }
4686                         if (dpll & PLL_P2_DIVIDE_BY_4)
4687                                 clock.p2 = 4;
4688                         else
4689                                 clock.p2 = 2;
4690
4691                         intel_clock(dev, 48000, &clock);
4692                 }
4693         }
4694
4695         /* XXX: It would be nice to validate the clocks, but we can't reuse
4696          * i830PllIsValid() because it relies on the xf86_config connector
4697          * configuration being accurate, which it isn't necessarily.
4698          */
4699
4700         return clock.dot;
4701 }
4702
4703 /** Returns the currently programmed mode of the given pipe. */
4704 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4705                                              struct drm_crtc *crtc)
4706 {
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         int pipe = intel_crtc->pipe;
4710         struct drm_display_mode *mode;
4711         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4712         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4713         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4714         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4715
4716         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4717         if (!mode)
4718                 return NULL;
4719
4720         mode->clock = intel_crtc_clock_get(dev, crtc);
4721         mode->hdisplay = (htot & 0xffff) + 1;
4722         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4723         mode->hsync_start = (hsync & 0xffff) + 1;
4724         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4725         mode->vdisplay = (vtot & 0xffff) + 1;
4726         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4727         mode->vsync_start = (vsync & 0xffff) + 1;
4728         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4729
4730         drm_mode_set_name(mode);
4731         drm_mode_set_crtcinfo(mode, 0);
4732
4733         return mode;
4734 }
4735
4736 #define GPU_IDLE_TIMEOUT 500 /* ms */
4737
4738 /* When this timer fires, we've been idle for awhile */
4739 static void intel_gpu_idle_timer(unsigned long arg)
4740 {
4741         struct drm_device *dev = (struct drm_device *)arg;
4742         drm_i915_private_t *dev_priv = dev->dev_private;
4743
4744         dev_priv->busy = false;
4745
4746         queue_work(dev_priv->wq, &dev_priv->idle_work);
4747 }
4748
4749 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4750
4751 static void intel_crtc_idle_timer(unsigned long arg)
4752 {
4753         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4754         struct drm_crtc *crtc = &intel_crtc->base;
4755         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4756
4757         intel_crtc->busy = false;
4758
4759         queue_work(dev_priv->wq, &dev_priv->idle_work);
4760 }
4761
4762 static void intel_increase_pllclock(struct drm_crtc *crtc)
4763 {
4764         struct drm_device *dev = crtc->dev;
4765         drm_i915_private_t *dev_priv = dev->dev_private;
4766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767         int pipe = intel_crtc->pipe;
4768         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4769         int dpll = I915_READ(dpll_reg);
4770
4771         if (HAS_PCH_SPLIT(dev))
4772                 return;
4773
4774         if (!dev_priv->lvds_downclock_avail)
4775                 return;
4776
4777         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4778                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4779
4780                 /* Unlock panel regs */
4781                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4782                            PANEL_UNLOCK_REGS);
4783
4784                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4785                 I915_WRITE(dpll_reg, dpll);
4786                 dpll = I915_READ(dpll_reg);
4787                 intel_wait_for_vblank(dev, pipe);
4788                 dpll = I915_READ(dpll_reg);
4789                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4790                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4791
4792                 /* ...and lock them again */
4793                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4794         }
4795
4796         /* Schedule downclock */
4797         mod_timer(&intel_crtc->idle_timer, jiffies +
4798                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4799 }
4800
4801 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4802 {
4803         struct drm_device *dev = crtc->dev;
4804         drm_i915_private_t *dev_priv = dev->dev_private;
4805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806         int pipe = intel_crtc->pipe;
4807         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4808         int dpll = I915_READ(dpll_reg);
4809
4810         if (HAS_PCH_SPLIT(dev))
4811                 return;
4812
4813         if (!dev_priv->lvds_downclock_avail)
4814                 return;
4815
4816         /*
4817          * Since this is called by a timer, we should never get here in
4818          * the manual case.
4819          */
4820         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4821                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4822
4823                 /* Unlock panel regs */
4824                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4825                            PANEL_UNLOCK_REGS);
4826
4827                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4828                 I915_WRITE(dpll_reg, dpll);
4829                 dpll = I915_READ(dpll_reg);
4830                 intel_wait_for_vblank(dev, pipe);
4831                 dpll = I915_READ(dpll_reg);
4832                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4833                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4834
4835                 /* ...and lock them again */
4836                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4837         }
4838
4839 }
4840
4841 /**
4842  * intel_idle_update - adjust clocks for idleness
4843  * @work: work struct
4844  *
4845  * Either the GPU or display (or both) went idle.  Check the busy status
4846  * here and adjust the CRTC and GPU clocks as necessary.
4847  */
4848 static void intel_idle_update(struct work_struct *work)
4849 {
4850         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4851                                                     idle_work);
4852         struct drm_device *dev = dev_priv->dev;
4853         struct drm_crtc *crtc;
4854         struct intel_crtc *intel_crtc;
4855         int enabled = 0;
4856
4857         if (!i915_powersave)
4858                 return;
4859
4860         mutex_lock(&dev->struct_mutex);
4861
4862         i915_update_gfx_val(dev_priv);
4863
4864         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4865                 /* Skip inactive CRTCs */
4866                 if (!crtc->fb)
4867                         continue;
4868
4869                 enabled++;
4870                 intel_crtc = to_intel_crtc(crtc);
4871                 if (!intel_crtc->busy)
4872                         intel_decrease_pllclock(crtc);
4873         }
4874
4875         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4876                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4877                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4878         }
4879
4880         mutex_unlock(&dev->struct_mutex);
4881 }
4882
4883 /**
4884  * intel_mark_busy - mark the GPU and possibly the display busy
4885  * @dev: drm device
4886  * @obj: object we're operating on
4887  *
4888  * Callers can use this function to indicate that the GPU is busy processing
4889  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4890  * buffer), we'll also mark the display as busy, so we know to increase its
4891  * clock frequency.
4892  */
4893 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4894 {
4895         drm_i915_private_t *dev_priv = dev->dev_private;
4896         struct drm_crtc *crtc = NULL;
4897         struct intel_framebuffer *intel_fb;
4898         struct intel_crtc *intel_crtc;
4899
4900         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4901                 return;
4902
4903         if (!dev_priv->busy) {
4904                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4905                         u32 fw_blc_self;
4906
4907                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4908                         fw_blc_self = I915_READ(FW_BLC_SELF);
4909                         fw_blc_self &= ~FW_BLC_SELF_EN;
4910                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4911                 }
4912                 dev_priv->busy = true;
4913         } else
4914                 mod_timer(&dev_priv->idle_timer, jiffies +
4915                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4916
4917         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4918                 if (!crtc->fb)
4919                         continue;
4920
4921                 intel_crtc = to_intel_crtc(crtc);
4922                 intel_fb = to_intel_framebuffer(crtc->fb);
4923                 if (intel_fb->obj == obj) {
4924                         if (!intel_crtc->busy) {
4925                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4926                                         u32 fw_blc_self;
4927
4928                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4929                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4930                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4931                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4932                                 }
4933                                 /* Non-busy -> busy, upclock */
4934                                 intel_increase_pllclock(crtc);
4935                                 intel_crtc->busy = true;
4936                         } else {
4937                                 /* Busy -> busy, put off timer */
4938                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4939                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4940                         }
4941                 }
4942         }
4943 }
4944
4945 static void intel_crtc_destroy(struct drm_crtc *crtc)
4946 {
4947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948         struct drm_device *dev = crtc->dev;
4949         struct intel_unpin_work *work;
4950         unsigned long flags;
4951
4952         spin_lock_irqsave(&dev->event_lock, flags);
4953         work = intel_crtc->unpin_work;
4954         intel_crtc->unpin_work = NULL;
4955         spin_unlock_irqrestore(&dev->event_lock, flags);
4956
4957         if (work) {
4958                 cancel_work_sync(&work->work);
4959                 kfree(work);
4960         }
4961
4962         drm_crtc_cleanup(crtc);
4963
4964         kfree(intel_crtc);
4965 }
4966
4967 static void intel_unpin_work_fn(struct work_struct *__work)
4968 {
4969         struct intel_unpin_work *work =
4970                 container_of(__work, struct intel_unpin_work, work);
4971
4972         mutex_lock(&work->dev->struct_mutex);
4973         i915_gem_object_unpin(work->old_fb_obj);
4974         drm_gem_object_unreference(work->pending_flip_obj);
4975         drm_gem_object_unreference(work->old_fb_obj);
4976         mutex_unlock(&work->dev->struct_mutex);
4977         kfree(work);
4978 }
4979
4980 static void do_intel_finish_page_flip(struct drm_device *dev,
4981                                       struct drm_crtc *crtc)
4982 {
4983         drm_i915_private_t *dev_priv = dev->dev_private;
4984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4985         struct intel_unpin_work *work;
4986         struct drm_i915_gem_object *obj_priv;
4987         struct drm_pending_vblank_event *e;
4988         struct timeval now;
4989         unsigned long flags;
4990
4991         /* Ignore early vblank irqs */
4992         if (intel_crtc == NULL)
4993                 return;
4994
4995         spin_lock_irqsave(&dev->event_lock, flags);
4996         work = intel_crtc->unpin_work;
4997         if (work == NULL || !work->pending) {
4998                 spin_unlock_irqrestore(&dev->event_lock, flags);
4999                 return;
5000         }
5001
5002         intel_crtc->unpin_work = NULL;
5003         drm_vblank_put(dev, intel_crtc->pipe);
5004
5005         if (work->event) {
5006                 e = work->event;
5007                 do_gettimeofday(&now);
5008                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5009                 e->event.tv_sec = now.tv_sec;
5010                 e->event.tv_usec = now.tv_usec;
5011                 list_add_tail(&e->base.link,
5012                               &e->base.file_priv->event_list);
5013                 wake_up_interruptible(&e->base.file_priv->event_wait);
5014         }
5015
5016         spin_unlock_irqrestore(&dev->event_lock, flags);
5017
5018         obj_priv = to_intel_bo(work->old_fb_obj);
5019         atomic_clear_mask(1 << intel_crtc->plane,
5020                           &obj_priv->pending_flip.counter);
5021         if (atomic_read(&obj_priv->pending_flip) == 0)
5022                 wake_up(&dev_priv->pending_flip_queue);
5023         schedule_work(&work->work);
5024
5025         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5026 }
5027
5028 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5029 {
5030         drm_i915_private_t *dev_priv = dev->dev_private;
5031         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5032
5033         do_intel_finish_page_flip(dev, crtc);
5034 }
5035
5036 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5037 {
5038         drm_i915_private_t *dev_priv = dev->dev_private;
5039         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5040
5041         do_intel_finish_page_flip(dev, crtc);
5042 }
5043
5044 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5045 {
5046         drm_i915_private_t *dev_priv = dev->dev_private;
5047         struct intel_crtc *intel_crtc =
5048                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5049         unsigned long flags;
5050
5051         spin_lock_irqsave(&dev->event_lock, flags);
5052         if (intel_crtc->unpin_work) {
5053                 if ((++intel_crtc->unpin_work->pending) > 1)
5054                         DRM_ERROR("Prepared flip multiple times\n");
5055         } else {
5056                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5057         }
5058         spin_unlock_irqrestore(&dev->event_lock, flags);
5059 }
5060
5061 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5062                                 struct drm_framebuffer *fb,
5063                                 struct drm_pending_vblank_event *event)
5064 {
5065         struct drm_device *dev = crtc->dev;
5066         struct drm_i915_private *dev_priv = dev->dev_private;
5067         struct intel_framebuffer *intel_fb;
5068         struct drm_i915_gem_object *obj_priv;
5069         struct drm_gem_object *obj;
5070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071         struct intel_unpin_work *work;
5072         unsigned long flags, offset;
5073         int pipe = intel_crtc->pipe;
5074         u32 pf, pipesrc;
5075         int ret;
5076
5077         work = kzalloc(sizeof *work, GFP_KERNEL);
5078         if (work == NULL)
5079                 return -ENOMEM;
5080
5081         work->event = event;
5082         work->dev = crtc->dev;
5083         intel_fb = to_intel_framebuffer(crtc->fb);
5084         work->old_fb_obj = intel_fb->obj;
5085         INIT_WORK(&work->work, intel_unpin_work_fn);
5086
5087         /* We borrow the event spin lock for protecting unpin_work */
5088         spin_lock_irqsave(&dev->event_lock, flags);
5089         if (intel_crtc->unpin_work) {
5090                 spin_unlock_irqrestore(&dev->event_lock, flags);
5091                 kfree(work);
5092
5093                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5094                 return -EBUSY;
5095         }
5096         intel_crtc->unpin_work = work;
5097         spin_unlock_irqrestore(&dev->event_lock, flags);
5098
5099         intel_fb = to_intel_framebuffer(fb);
5100         obj = intel_fb->obj;
5101
5102         mutex_lock(&dev->struct_mutex);
5103         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5104         if (ret)
5105                 goto cleanup_work;
5106
5107         /* Reference the objects for the scheduled work. */
5108         drm_gem_object_reference(work->old_fb_obj);
5109         drm_gem_object_reference(obj);
5110
5111         crtc->fb = fb;
5112
5113         ret = drm_vblank_get(dev, intel_crtc->pipe);
5114         if (ret)
5115                 goto cleanup_objs;
5116
5117         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5118                 u32 flip_mask;
5119
5120                 /* Can't queue multiple flips, so wait for the previous
5121                  * one to finish before executing the next.
5122                  */
5123                 ret = BEGIN_LP_RING(2);
5124                 if (ret)
5125                         goto cleanup_objs;
5126
5127                 if (intel_crtc->plane)
5128                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5129                 else
5130                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5131                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5132                 OUT_RING(MI_NOOP);
5133                 ADVANCE_LP_RING();
5134         }
5135
5136         work->pending_flip_obj = obj;
5137         obj_priv = to_intel_bo(obj);
5138
5139         work->enable_stall_check = true;
5140
5141         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5142         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5143
5144         ret = BEGIN_LP_RING(4);
5145         if (ret)
5146                 goto cleanup_objs;
5147
5148         /* Block clients from rendering to the new back buffer until
5149          * the flip occurs and the object is no longer visible.
5150          */
5151         atomic_add(1 << intel_crtc->plane,
5152                    &to_intel_bo(work->old_fb_obj)->pending_flip);
5153
5154         switch (INTEL_INFO(dev)->gen) {
5155         case 2:
5156                 OUT_RING(MI_DISPLAY_FLIP |
5157                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5158                 OUT_RING(fb->pitch);
5159                 OUT_RING(obj_priv->gtt_offset + offset);
5160                 OUT_RING(MI_NOOP);
5161                 break;
5162
5163         case 3:
5164                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5165                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5166                 OUT_RING(fb->pitch);
5167                 OUT_RING(obj_priv->gtt_offset + offset);
5168                 OUT_RING(MI_NOOP);
5169                 break;
5170
5171         case 4:
5172         case 5:
5173                 /* i965+ uses the linear or tiled offsets from the
5174                  * Display Registers (which do not change across a page-flip)
5175                  * so we need only reprogram the base address.
5176                  */
5177                 OUT_RING(MI_DISPLAY_FLIP |
5178                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5179                 OUT_RING(fb->pitch);
5180                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5181
5182                 /* XXX Enabling the panel-fitter across page-flip is so far
5183                  * untested on non-native modes, so ignore it for now.
5184                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5185                  */
5186                 pf = 0;
5187                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5188                 OUT_RING(pf | pipesrc);
5189                 break;
5190
5191         case 6:
5192                 OUT_RING(MI_DISPLAY_FLIP |
5193                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5194                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5195                 OUT_RING(obj_priv->gtt_offset);
5196
5197                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5198                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5199                 OUT_RING(pf | pipesrc);
5200                 break;
5201         }
5202         ADVANCE_LP_RING();
5203
5204         mutex_unlock(&dev->struct_mutex);
5205
5206         trace_i915_flip_request(intel_crtc->plane, obj);
5207
5208         return 0;
5209
5210 cleanup_objs:
5211         drm_gem_object_unreference(work->old_fb_obj);
5212         drm_gem_object_unreference(obj);
5213 cleanup_work:
5214         mutex_unlock(&dev->struct_mutex);
5215
5216         spin_lock_irqsave(&dev->event_lock, flags);
5217         intel_crtc->unpin_work = NULL;
5218         spin_unlock_irqrestore(&dev->event_lock, flags);
5219
5220         kfree(work);
5221
5222         return ret;
5223 }
5224
5225 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5226         .dpms = intel_crtc_dpms,
5227         .mode_fixup = intel_crtc_mode_fixup,
5228         .mode_set = intel_crtc_mode_set,
5229         .mode_set_base = intel_pipe_set_base,
5230         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5231         .load_lut = intel_crtc_load_lut,
5232         .disable = intel_crtc_disable,
5233 };
5234
5235 static const struct drm_crtc_funcs intel_crtc_funcs = {
5236         .cursor_set = intel_crtc_cursor_set,
5237         .cursor_move = intel_crtc_cursor_move,
5238         .gamma_set = intel_crtc_gamma_set,
5239         .set_config = drm_crtc_helper_set_config,
5240         .destroy = intel_crtc_destroy,
5241         .page_flip = intel_crtc_page_flip,
5242 };
5243
5244
5245 static void intel_crtc_init(struct drm_device *dev, int pipe)
5246 {
5247         drm_i915_private_t *dev_priv = dev->dev_private;
5248         struct intel_crtc *intel_crtc;
5249         int i;
5250
5251         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5252         if (intel_crtc == NULL)
5253                 return;
5254
5255         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5256
5257         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5258         for (i = 0; i < 256; i++) {
5259                 intel_crtc->lut_r[i] = i;
5260                 intel_crtc->lut_g[i] = i;
5261                 intel_crtc->lut_b[i] = i;
5262         }
5263
5264         /* Swap pipes & planes for FBC on pre-965 */
5265         intel_crtc->pipe = pipe;
5266         intel_crtc->plane = pipe;
5267         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5268                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5269                 intel_crtc->plane = !pipe;
5270         }
5271
5272         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5273                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5274         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5275         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5276
5277         intel_crtc->cursor_addr = 0;
5278         intel_crtc->dpms_mode = -1;
5279         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5280
5281         if (HAS_PCH_SPLIT(dev)) {
5282                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5283                 intel_helper_funcs.commit = ironlake_crtc_commit;
5284         } else {
5285                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5286                 intel_helper_funcs.commit = i9xx_crtc_commit;
5287         }
5288
5289         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5290
5291         intel_crtc->busy = false;
5292
5293         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5294                     (unsigned long)intel_crtc);
5295 }
5296
5297 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5298                                 struct drm_file *file_priv)
5299 {
5300         drm_i915_private_t *dev_priv = dev->dev_private;
5301         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5302         struct drm_mode_object *drmmode_obj;
5303         struct intel_crtc *crtc;
5304
5305         if (!dev_priv) {
5306                 DRM_ERROR("called with no initialization\n");
5307                 return -EINVAL;
5308         }
5309
5310         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5311                         DRM_MODE_OBJECT_CRTC);
5312
5313         if (!drmmode_obj) {
5314                 DRM_ERROR("no such CRTC id\n");
5315                 return -EINVAL;
5316         }
5317
5318         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5319         pipe_from_crtc_id->pipe = crtc->pipe;
5320
5321         return 0;
5322 }
5323
5324 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5325 {
5326         struct intel_encoder *encoder;
5327         int index_mask = 0;
5328         int entry = 0;
5329
5330         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5331                 if (type_mask & encoder->clone_mask)
5332                         index_mask |= (1 << entry);
5333                 entry++;
5334         }
5335
5336         return index_mask;
5337 }
5338
5339 static void intel_setup_outputs(struct drm_device *dev)
5340 {
5341         struct drm_i915_private *dev_priv = dev->dev_private;
5342         struct intel_encoder *encoder;
5343         bool dpd_is_edp = false;
5344
5345         if (IS_MOBILE(dev) && !IS_I830(dev))
5346                 intel_lvds_init(dev);
5347
5348         if (HAS_PCH_SPLIT(dev)) {
5349                 dpd_is_edp = intel_dpd_is_edp(dev);
5350
5351                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5352                         intel_dp_init(dev, DP_A);
5353
5354                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5355                         intel_dp_init(dev, PCH_DP_D);
5356         }
5357
5358         intel_crt_init(dev);
5359
5360         if (HAS_PCH_SPLIT(dev)) {
5361                 int found;
5362
5363                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5364                         /* PCH SDVOB multiplex with HDMIB */
5365                         found = intel_sdvo_init(dev, PCH_SDVOB);
5366                         if (!found)
5367                                 intel_hdmi_init(dev, HDMIB);
5368                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5369                                 intel_dp_init(dev, PCH_DP_B);
5370                 }
5371
5372                 if (I915_READ(HDMIC) & PORT_DETECTED)
5373                         intel_hdmi_init(dev, HDMIC);
5374
5375                 if (I915_READ(HDMID) & PORT_DETECTED)
5376                         intel_hdmi_init(dev, HDMID);
5377
5378                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5379                         intel_dp_init(dev, PCH_DP_C);
5380
5381                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5382                         intel_dp_init(dev, PCH_DP_D);
5383
5384         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5385                 bool found = false;
5386
5387                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5388                         DRM_DEBUG_KMS("probing SDVOB\n");
5389                         found = intel_sdvo_init(dev, SDVOB);
5390                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5391                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5392                                 intel_hdmi_init(dev, SDVOB);
5393                         }
5394
5395                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5396                                 DRM_DEBUG_KMS("probing DP_B\n");
5397                                 intel_dp_init(dev, DP_B);
5398                         }
5399                 }
5400
5401                 /* Before G4X SDVOC doesn't have its own detect register */
5402
5403                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5404                         DRM_DEBUG_KMS("probing SDVOC\n");
5405                         found = intel_sdvo_init(dev, SDVOC);
5406                 }
5407
5408                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5409
5410                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5411                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5412                                 intel_hdmi_init(dev, SDVOC);
5413                         }
5414                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5415                                 DRM_DEBUG_KMS("probing DP_C\n");
5416                                 intel_dp_init(dev, DP_C);
5417                         }
5418                 }
5419
5420                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5421                     (I915_READ(DP_D) & DP_DETECTED)) {
5422                         DRM_DEBUG_KMS("probing DP_D\n");
5423                         intel_dp_init(dev, DP_D);
5424                 }
5425         } else if (IS_GEN2(dev))
5426                 intel_dvo_init(dev);
5427
5428         if (SUPPORTS_TV(dev))
5429                 intel_tv_init(dev);
5430
5431         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5432                 encoder->base.possible_crtcs = encoder->crtc_mask;
5433                 encoder->base.possible_clones =
5434                         intel_encoder_clones(dev, encoder->clone_mask);
5435         }
5436 }
5437
5438 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5439 {
5440         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5441
5442         drm_framebuffer_cleanup(fb);
5443         drm_gem_object_unreference_unlocked(intel_fb->obj);
5444
5445         kfree(intel_fb);
5446 }
5447
5448 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5449                                                 struct drm_file *file_priv,
5450                                                 unsigned int *handle)
5451 {
5452         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5453         struct drm_gem_object *object = intel_fb->obj;
5454
5455         return drm_gem_handle_create(file_priv, object, handle);
5456 }
5457
5458 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5459         .destroy = intel_user_framebuffer_destroy,
5460         .create_handle = intel_user_framebuffer_create_handle,
5461 };
5462
5463 int intel_framebuffer_init(struct drm_device *dev,
5464                            struct intel_framebuffer *intel_fb,
5465                            struct drm_mode_fb_cmd *mode_cmd,
5466                            struct drm_gem_object *obj)
5467 {
5468         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5469         int ret;
5470
5471         if (obj_priv->tiling_mode == I915_TILING_Y)
5472                 return -EINVAL;
5473
5474         if (mode_cmd->pitch & 63)
5475                 return -EINVAL;
5476
5477         switch (mode_cmd->bpp) {
5478         case 8:
5479         case 16:
5480         case 24:
5481         case 32:
5482                 break;
5483         default:
5484                 return -EINVAL;
5485         }
5486
5487         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5488         if (ret) {
5489                 DRM_ERROR("framebuffer init failed %d\n", ret);
5490                 return ret;
5491         }
5492
5493         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5494         intel_fb->obj = obj;
5495         return 0;
5496 }
5497
5498 static struct drm_framebuffer *
5499 intel_user_framebuffer_create(struct drm_device *dev,
5500                               struct drm_file *filp,
5501                               struct drm_mode_fb_cmd *mode_cmd)
5502 {
5503         struct drm_gem_object *obj;
5504         struct intel_framebuffer *intel_fb;
5505         int ret;
5506
5507         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5508         if (!obj)
5509                 return ERR_PTR(-ENOENT);
5510
5511         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5512         if (!intel_fb)
5513                 return ERR_PTR(-ENOMEM);
5514
5515         ret = intel_framebuffer_init(dev, intel_fb,
5516                                      mode_cmd, obj);
5517         if (ret) {
5518                 drm_gem_object_unreference_unlocked(obj);
5519                 kfree(intel_fb);
5520                 return ERR_PTR(ret);
5521         }
5522
5523         return &intel_fb->base;
5524 }
5525
5526 static const struct drm_mode_config_funcs intel_mode_funcs = {
5527         .fb_create = intel_user_framebuffer_create,
5528         .output_poll_changed = intel_fb_output_poll_changed,
5529 };
5530
5531 static struct drm_gem_object *
5532 intel_alloc_context_page(struct drm_device *dev)
5533 {
5534         struct drm_gem_object *ctx;
5535         int ret;
5536
5537         ctx = i915_gem_alloc_object(dev, 4096);
5538         if (!ctx) {
5539                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5540                 return NULL;
5541         }
5542
5543         mutex_lock(&dev->struct_mutex);
5544         ret = i915_gem_object_pin(ctx, 4096, true);
5545         if (ret) {
5546                 DRM_ERROR("failed to pin power context: %d\n", ret);
5547                 goto err_unref;
5548         }
5549
5550         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5551         if (ret) {
5552                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5553                 goto err_unpin;
5554         }
5555         mutex_unlock(&dev->struct_mutex);
5556
5557         return ctx;
5558
5559 err_unpin:
5560         i915_gem_object_unpin(ctx);
5561 err_unref:
5562         drm_gem_object_unreference(ctx);
5563         mutex_unlock(&dev->struct_mutex);
5564         return NULL;
5565 }
5566
5567 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5568 {
5569         struct drm_i915_private *dev_priv = dev->dev_private;
5570         u16 rgvswctl;
5571
5572         rgvswctl = I915_READ16(MEMSWCTL);
5573         if (rgvswctl & MEMCTL_CMD_STS) {
5574                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5575                 return false; /* still busy with another command */
5576         }
5577
5578         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5579                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5580         I915_WRITE16(MEMSWCTL, rgvswctl);
5581         POSTING_READ16(MEMSWCTL);
5582
5583         rgvswctl |= MEMCTL_CMD_STS;
5584         I915_WRITE16(MEMSWCTL, rgvswctl);
5585
5586         return true;
5587 }
5588
5589 void ironlake_enable_drps(struct drm_device *dev)
5590 {
5591         struct drm_i915_private *dev_priv = dev->dev_private;
5592         u32 rgvmodectl = I915_READ(MEMMODECTL);
5593         u8 fmax, fmin, fstart, vstart;
5594
5595         /* Enable temp reporting */
5596         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5597         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5598
5599         /* 100ms RC evaluation intervals */
5600         I915_WRITE(RCUPEI, 100000);
5601         I915_WRITE(RCDNEI, 100000);
5602
5603         /* Set max/min thresholds to 90ms and 80ms respectively */
5604         I915_WRITE(RCBMAXAVG, 90000);
5605         I915_WRITE(RCBMINAVG, 80000);
5606
5607         I915_WRITE(MEMIHYST, 1);
5608
5609         /* Set up min, max, and cur for interrupt handling */
5610         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5611         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5612         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5613                 MEMMODE_FSTART_SHIFT;
5614
5615         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5616                 PXVFREQ_PX_SHIFT;
5617
5618         dev_priv->fmax = fmax; /* IPS callback will increase this */
5619         dev_priv->fstart = fstart;
5620
5621         dev_priv->max_delay = fstart;
5622         dev_priv->min_delay = fmin;
5623         dev_priv->cur_delay = fstart;
5624
5625         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5626                          fmax, fmin, fstart);
5627
5628         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5629
5630         /*
5631          * Interrupts will be enabled in ironlake_irq_postinstall
5632          */
5633
5634         I915_WRITE(VIDSTART, vstart);
5635         POSTING_READ(VIDSTART);
5636
5637         rgvmodectl |= MEMMODE_SWMODE_EN;
5638         I915_WRITE(MEMMODECTL, rgvmodectl);
5639
5640         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5641                 DRM_ERROR("stuck trying to change perf mode\n");
5642         msleep(1);
5643
5644         ironlake_set_drps(dev, fstart);
5645
5646         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5647                 I915_READ(0x112e0);
5648         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5649         dev_priv->last_count2 = I915_READ(0x112f4);
5650         getrawmonotonic(&dev_priv->last_time2);
5651 }
5652
5653 void ironlake_disable_drps(struct drm_device *dev)
5654 {
5655         struct drm_i915_private *dev_priv = dev->dev_private;
5656         u16 rgvswctl = I915_READ16(MEMSWCTL);
5657
5658         /* Ack interrupts, disable EFC interrupt */
5659         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5660         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5661         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5662         I915_WRITE(DEIIR, DE_PCU_EVENT);
5663         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5664
5665         /* Go back to the starting frequency */
5666         ironlake_set_drps(dev, dev_priv->fstart);
5667         msleep(1);
5668         rgvswctl |= MEMCTL_CMD_STS;
5669         I915_WRITE(MEMSWCTL, rgvswctl);
5670         msleep(1);
5671
5672 }
5673
5674 static unsigned long intel_pxfreq(u32 vidfreq)
5675 {
5676         unsigned long freq;
5677         int div = (vidfreq & 0x3f0000) >> 16;
5678         int post = (vidfreq & 0x3000) >> 12;
5679         int pre = (vidfreq & 0x7);
5680
5681         if (!pre)
5682                 return 0;
5683
5684         freq = ((div * 133333) / ((1<<post) * pre));
5685
5686         return freq;
5687 }
5688
5689 void intel_init_emon(struct drm_device *dev)
5690 {
5691         struct drm_i915_private *dev_priv = dev->dev_private;
5692         u32 lcfuse;
5693         u8 pxw[16];
5694         int i;
5695
5696         /* Disable to program */
5697         I915_WRITE(ECR, 0);
5698         POSTING_READ(ECR);
5699
5700         /* Program energy weights for various events */
5701         I915_WRITE(SDEW, 0x15040d00);
5702         I915_WRITE(CSIEW0, 0x007f0000);
5703         I915_WRITE(CSIEW1, 0x1e220004);
5704         I915_WRITE(CSIEW2, 0x04000004);
5705
5706         for (i = 0; i < 5; i++)
5707                 I915_WRITE(PEW + (i * 4), 0);
5708         for (i = 0; i < 3; i++)
5709                 I915_WRITE(DEW + (i * 4), 0);
5710
5711         /* Program P-state weights to account for frequency power adjustment */
5712         for (i = 0; i < 16; i++) {
5713                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5714                 unsigned long freq = intel_pxfreq(pxvidfreq);
5715                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5716                         PXVFREQ_PX_SHIFT;
5717                 unsigned long val;
5718
5719                 val = vid * vid;
5720                 val *= (freq / 1000);
5721                 val *= 255;
5722                 val /= (127*127*900);
5723                 if (val > 0xff)
5724                         DRM_ERROR("bad pxval: %ld\n", val);
5725                 pxw[i] = val;
5726         }
5727         /* Render standby states get 0 weight */
5728         pxw[14] = 0;
5729         pxw[15] = 0;
5730
5731         for (i = 0; i < 4; i++) {
5732                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5733                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5734                 I915_WRITE(PXW + (i * 4), val);
5735         }
5736
5737         /* Adjust magic regs to magic values (more experimental results) */
5738         I915_WRITE(OGW0, 0);
5739         I915_WRITE(OGW1, 0);
5740         I915_WRITE(EG0, 0x00007f00);
5741         I915_WRITE(EG1, 0x0000000e);
5742         I915_WRITE(EG2, 0x000e0000);
5743         I915_WRITE(EG3, 0x68000300);
5744         I915_WRITE(EG4, 0x42000000);
5745         I915_WRITE(EG5, 0x00140031);
5746         I915_WRITE(EG6, 0);
5747         I915_WRITE(EG7, 0);
5748
5749         for (i = 0; i < 8; i++)
5750                 I915_WRITE(PXWL + (i * 4), 0);
5751
5752         /* Enable PMON + select events */
5753         I915_WRITE(ECR, 0x80000019);
5754
5755         lcfuse = I915_READ(LCFUSE02);
5756
5757         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5758 }
5759
5760 void intel_init_clock_gating(struct drm_device *dev)
5761 {
5762         struct drm_i915_private *dev_priv = dev->dev_private;
5763
5764         /*
5765          * Disable clock gating reported to work incorrectly according to the
5766          * specs, but enable as much else as we can.
5767          */
5768         if (HAS_PCH_SPLIT(dev)) {
5769                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5770
5771                 if (IS_GEN5(dev)) {
5772                         /* Required for FBC */
5773                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5774                         /* Required for CxSR */
5775                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5776
5777                         I915_WRITE(PCH_3DCGDIS0,
5778                                    MARIUNIT_CLOCK_GATE_DISABLE |
5779                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5780                 }
5781
5782                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5783
5784                 /*
5785                  * On Ibex Peak and Cougar Point, we need to disable clock
5786                  * gating for the panel power sequencer or it will fail to
5787                  * start up when no ports are active.
5788                  */
5789                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5790
5791                 /*
5792                  * According to the spec the following bits should be set in
5793                  * order to enable memory self-refresh
5794                  * The bit 22/21 of 0x42004
5795                  * The bit 5 of 0x42020
5796                  * The bit 15 of 0x45000
5797                  */
5798                 if (IS_GEN5(dev)) {
5799                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5800                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5801                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5802                         I915_WRITE(ILK_DSPCLK_GATE,
5803                                         (I915_READ(ILK_DSPCLK_GATE) |
5804                                                 ILK_DPARB_CLK_GATE));
5805                         I915_WRITE(DISP_ARB_CTL,
5806                                         (I915_READ(DISP_ARB_CTL) |
5807                                                 DISP_FBC_WM_DIS));
5808                 I915_WRITE(WM3_LP_ILK, 0);
5809                 I915_WRITE(WM2_LP_ILK, 0);
5810                 I915_WRITE(WM1_LP_ILK, 0);
5811                 }
5812                 /*
5813                  * Based on the document from hardware guys the following bits
5814                  * should be set unconditionally in order to enable FBC.
5815                  * The bit 22 of 0x42000
5816                  * The bit 22 of 0x42004
5817                  * The bit 7,8,9 of 0x42020.
5818                  */
5819                 if (IS_IRONLAKE_M(dev)) {
5820                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5821                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5822                                    ILK_FBCQ_DIS);
5823                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5824                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5825                                    ILK_DPARB_GATE);
5826                         I915_WRITE(ILK_DSPCLK_GATE,
5827                                    I915_READ(ILK_DSPCLK_GATE) |
5828                                    ILK_DPFC_DIS1 |
5829                                    ILK_DPFC_DIS2 |
5830                                    ILK_CLK_FBC);
5831                 }
5832
5833                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5834                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5835                            ILK_ELPIN_409_SELECT);
5836
5837                 if (IS_GEN5(dev)) {
5838                         I915_WRITE(_3D_CHICKEN2,
5839                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5840                                    _3D_CHICKEN2_WM_READ_PIPELINED);
5841                 }
5842                 return;
5843         } else if (IS_G4X(dev)) {
5844                 uint32_t dspclk_gate;
5845                 I915_WRITE(RENCLK_GATE_D1, 0);
5846                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5847                        GS_UNIT_CLOCK_GATE_DISABLE |
5848                        CL_UNIT_CLOCK_GATE_DISABLE);
5849                 I915_WRITE(RAMCLK_GATE_D, 0);
5850                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5851                         OVRUNIT_CLOCK_GATE_DISABLE |
5852                         OVCUNIT_CLOCK_GATE_DISABLE;
5853                 if (IS_GM45(dev))
5854                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5855                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5856         } else if (IS_CRESTLINE(dev)) {
5857                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5858                 I915_WRITE(RENCLK_GATE_D2, 0);
5859                 I915_WRITE(DSPCLK_GATE_D, 0);
5860                 I915_WRITE(RAMCLK_GATE_D, 0);
5861                 I915_WRITE16(DEUC, 0);
5862         } else if (IS_BROADWATER(dev)) {
5863                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5864                        I965_RCC_CLOCK_GATE_DISABLE |
5865                        I965_RCPB_CLOCK_GATE_DISABLE |
5866                        I965_ISC_CLOCK_GATE_DISABLE |
5867                        I965_FBC_CLOCK_GATE_DISABLE);
5868                 I915_WRITE(RENCLK_GATE_D2, 0);
5869         } else if (IS_GEN3(dev)) {
5870                 u32 dstate = I915_READ(D_STATE);
5871
5872                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5873                         DSTATE_DOT_CLOCK_GATING;
5874                 I915_WRITE(D_STATE, dstate);
5875         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5876                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5877         } else if (IS_I830(dev)) {
5878                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5879         }
5880
5881         /*
5882          * GPU can automatically power down the render unit if given a page
5883          * to save state.
5884          */
5885         if (IS_IRONLAKE_M(dev)) {
5886                 if (dev_priv->renderctx == NULL)
5887                         dev_priv->renderctx = intel_alloc_context_page(dev);
5888                 if (dev_priv->renderctx) {
5889                         struct drm_i915_gem_object *obj_priv;
5890                         obj_priv = to_intel_bo(dev_priv->renderctx);
5891                         if (obj_priv) {
5892                                 if (BEGIN_LP_RING(4) == 0) {
5893                                         OUT_RING(MI_SET_CONTEXT);
5894                                         OUT_RING(obj_priv->gtt_offset |
5895                                                  MI_MM_SPACE_GTT |
5896                                                  MI_SAVE_EXT_STATE_EN |
5897                                                  MI_RESTORE_EXT_STATE_EN |
5898                                                  MI_RESTORE_INHIBIT);
5899                                         OUT_RING(MI_NOOP);
5900                                         OUT_RING(MI_FLUSH);
5901                                         ADVANCE_LP_RING();
5902                                 }
5903                         }
5904                 } else
5905                         DRM_DEBUG_KMS("Failed to allocate render context."
5906                                        "Disable RC6\n");
5907         }
5908
5909         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5910                 struct drm_i915_gem_object *obj_priv = NULL;
5911
5912                 if (dev_priv->pwrctx) {
5913                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5914                 } else {
5915                         struct drm_gem_object *pwrctx;
5916
5917                         pwrctx = intel_alloc_context_page(dev);
5918                         if (pwrctx) {
5919                                 dev_priv->pwrctx = pwrctx;
5920                                 obj_priv = to_intel_bo(pwrctx);
5921                         }
5922                 }
5923
5924                 if (obj_priv) {
5925                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5926                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5927                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5928                 }
5929         }
5930 }
5931
5932 /* Set up chip specific display functions */
5933 static void intel_init_display(struct drm_device *dev)
5934 {
5935         struct drm_i915_private *dev_priv = dev->dev_private;
5936
5937         /* We always want a DPMS function */
5938         if (HAS_PCH_SPLIT(dev))
5939                 dev_priv->display.dpms = ironlake_crtc_dpms;
5940         else
5941                 dev_priv->display.dpms = i9xx_crtc_dpms;
5942
5943         if (I915_HAS_FBC(dev)) {
5944                 if (IS_IRONLAKE_M(dev)) {
5945                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5946                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5947                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5948                 } else if (IS_GM45(dev)) {
5949                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5950                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5951                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5952                 } else if (IS_CRESTLINE(dev)) {
5953                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5954                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5955                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5956                 }
5957                 /* 855GM needs testing */
5958         }
5959
5960         /* Returns the core display clock speed */
5961         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5962                 dev_priv->display.get_display_clock_speed =
5963                         i945_get_display_clock_speed;
5964         else if (IS_I915G(dev))
5965                 dev_priv->display.get_display_clock_speed =
5966                         i915_get_display_clock_speed;
5967         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5968                 dev_priv->display.get_display_clock_speed =
5969                         i9xx_misc_get_display_clock_speed;
5970         else if (IS_I915GM(dev))
5971                 dev_priv->display.get_display_clock_speed =
5972                         i915gm_get_display_clock_speed;
5973         else if (IS_I865G(dev))
5974                 dev_priv->display.get_display_clock_speed =
5975                         i865_get_display_clock_speed;
5976         else if (IS_I85X(dev))
5977                 dev_priv->display.get_display_clock_speed =
5978                         i855_get_display_clock_speed;
5979         else /* 852, 830 */
5980                 dev_priv->display.get_display_clock_speed =
5981                         i830_get_display_clock_speed;
5982
5983         /* For FIFO watermark updates */
5984         if (HAS_PCH_SPLIT(dev)) {
5985                 if (IS_GEN5(dev)) {
5986                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5987                                 dev_priv->display.update_wm = ironlake_update_wm;
5988                         else {
5989                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5990                                               "Disable CxSR\n");
5991                                 dev_priv->display.update_wm = NULL;
5992                         }
5993                 } else
5994                         dev_priv->display.update_wm = NULL;
5995         } else if (IS_PINEVIEW(dev)) {
5996                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5997                                             dev_priv->is_ddr3,
5998                                             dev_priv->fsb_freq,
5999                                             dev_priv->mem_freq)) {
6000                         DRM_INFO("failed to find known CxSR latency "
6001                                  "(found ddr%s fsb freq %d, mem freq %d), "
6002                                  "disabling CxSR\n",
6003                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6004                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6005                         /* Disable CxSR and never update its watermark again */
6006                         pineview_disable_cxsr(dev);
6007                         dev_priv->display.update_wm = NULL;
6008                 } else
6009                         dev_priv->display.update_wm = pineview_update_wm;
6010         } else if (IS_G4X(dev))
6011                 dev_priv->display.update_wm = g4x_update_wm;
6012         else if (IS_GEN4(dev))
6013                 dev_priv->display.update_wm = i965_update_wm;
6014         else if (IS_GEN3(dev)) {
6015                 dev_priv->display.update_wm = i9xx_update_wm;
6016                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6017         } else if (IS_I85X(dev)) {
6018                 dev_priv->display.update_wm = i9xx_update_wm;
6019                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6020         } else {
6021                 dev_priv->display.update_wm = i830_update_wm;
6022                 if (IS_845G(dev))
6023                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6024                 else
6025                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6026         }
6027 }
6028
6029 /*
6030  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6031  * resume, or other times.  This quirk makes sure that's the case for
6032  * affected systems.
6033  */
6034 static void quirk_pipea_force (struct drm_device *dev)
6035 {
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037
6038         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6039         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6040 }
6041
6042 struct intel_quirk {
6043         int device;
6044         int subsystem_vendor;
6045         int subsystem_device;
6046         void (*hook)(struct drm_device *dev);
6047 };
6048
6049 struct intel_quirk intel_quirks[] = {
6050         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6051         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6052         /* HP Mini needs pipe A force quirk (LP: #322104) */
6053         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6054
6055         /* Thinkpad R31 needs pipe A force quirk */
6056         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6057         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6058         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6059
6060         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6061         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6062         /* ThinkPad X40 needs pipe A force quirk */
6063
6064         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6065         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6066
6067         /* 855 & before need to leave pipe A & dpll A up */
6068         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6069         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6070 };
6071
6072 static void intel_init_quirks(struct drm_device *dev)
6073 {
6074         struct pci_dev *d = dev->pdev;
6075         int i;
6076
6077         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6078                 struct intel_quirk *q = &intel_quirks[i];
6079
6080                 if (d->device == q->device &&
6081                     (d->subsystem_vendor == q->subsystem_vendor ||
6082                      q->subsystem_vendor == PCI_ANY_ID) &&
6083                     (d->subsystem_device == q->subsystem_device ||
6084                      q->subsystem_device == PCI_ANY_ID))
6085                         q->hook(dev);
6086         }
6087 }
6088
6089 /* Disable the VGA plane that we never use */
6090 static void i915_disable_vga(struct drm_device *dev)
6091 {
6092         struct drm_i915_private *dev_priv = dev->dev_private;
6093         u8 sr1;
6094         u32 vga_reg;
6095
6096         if (HAS_PCH_SPLIT(dev))
6097                 vga_reg = CPU_VGACNTRL;
6098         else
6099                 vga_reg = VGACNTRL;
6100
6101         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6102         outb(1, VGA_SR_INDEX);
6103         sr1 = inb(VGA_SR_DATA);
6104         outb(sr1 | 1<<5, VGA_SR_DATA);
6105         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6106         udelay(300);
6107
6108         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6109         POSTING_READ(vga_reg);
6110 }
6111
6112 void intel_modeset_init(struct drm_device *dev)
6113 {
6114         struct drm_i915_private *dev_priv = dev->dev_private;
6115         int i;
6116
6117         drm_mode_config_init(dev);
6118
6119         dev->mode_config.min_width = 0;
6120         dev->mode_config.min_height = 0;
6121
6122         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6123
6124         intel_init_quirks(dev);
6125
6126         intel_init_display(dev);
6127
6128         if (IS_GEN2(dev)) {
6129                 dev->mode_config.max_width = 2048;
6130                 dev->mode_config.max_height = 2048;
6131         } else if (IS_GEN3(dev)) {
6132                 dev->mode_config.max_width = 4096;
6133                 dev->mode_config.max_height = 4096;
6134         } else {
6135                 dev->mode_config.max_width = 8192;
6136                 dev->mode_config.max_height = 8192;
6137         }
6138
6139         /* set memory base */
6140         if (IS_GEN2(dev))
6141                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6142         else
6143                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6144
6145         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6146                 dev_priv->num_pipe = 2;
6147         else
6148                 dev_priv->num_pipe = 1;
6149         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6150                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6151
6152         for (i = 0; i < dev_priv->num_pipe; i++) {
6153                 intel_crtc_init(dev, i);
6154         }
6155
6156         intel_setup_outputs(dev);
6157
6158         intel_init_clock_gating(dev);
6159
6160         /* Just disable it once at startup */
6161         i915_disable_vga(dev);
6162
6163         if (IS_IRONLAKE_M(dev)) {
6164                 ironlake_enable_drps(dev);
6165                 intel_init_emon(dev);
6166         }
6167
6168         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6169         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6170                     (unsigned long)dev);
6171
6172         intel_setup_overlay(dev);
6173 }
6174
6175 void intel_modeset_cleanup(struct drm_device *dev)
6176 {
6177         struct drm_i915_private *dev_priv = dev->dev_private;
6178         struct drm_crtc *crtc;
6179         struct intel_crtc *intel_crtc;
6180
6181         drm_kms_helper_poll_fini(dev);
6182         mutex_lock(&dev->struct_mutex);
6183
6184         intel_unregister_dsm_handler();
6185
6186
6187         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6188                 /* Skip inactive CRTCs */
6189                 if (!crtc->fb)
6190                         continue;
6191
6192                 intel_crtc = to_intel_crtc(crtc);
6193                 intel_increase_pllclock(crtc);
6194         }
6195
6196         if (dev_priv->display.disable_fbc)
6197                 dev_priv->display.disable_fbc(dev);
6198
6199         if (dev_priv->renderctx) {
6200                 struct drm_i915_gem_object *obj_priv;
6201
6202                 obj_priv = to_intel_bo(dev_priv->renderctx);
6203                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6204                 I915_READ(CCID);
6205                 i915_gem_object_unpin(dev_priv->renderctx);
6206                 drm_gem_object_unreference(dev_priv->renderctx);
6207         }
6208
6209         if (dev_priv->pwrctx) {
6210                 struct drm_i915_gem_object *obj_priv;
6211
6212                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6213                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6214                 I915_READ(PWRCTXA);
6215                 i915_gem_object_unpin(dev_priv->pwrctx);
6216                 drm_gem_object_unreference(dev_priv->pwrctx);
6217         }
6218
6219         if (IS_IRONLAKE_M(dev))
6220                 ironlake_disable_drps(dev);
6221
6222         mutex_unlock(&dev->struct_mutex);
6223
6224         /* Disable the irq before mode object teardown, for the irq might
6225          * enqueue unpin/hotplug work. */
6226         drm_irq_uninstall(dev);
6227         cancel_work_sync(&dev_priv->hotplug_work);
6228
6229         /* Shut off idle work before the crtcs get freed. */
6230         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6231                 intel_crtc = to_intel_crtc(crtc);
6232                 del_timer_sync(&intel_crtc->idle_timer);
6233         }
6234         del_timer_sync(&dev_priv->idle_timer);
6235         cancel_work_sync(&dev_priv->idle_work);
6236
6237         drm_mode_config_cleanup(dev);
6238 }
6239
6240 /*
6241  * Return which encoder is currently attached for connector.
6242  */
6243 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6244 {
6245         return &intel_attached_encoder(connector)->base;
6246 }
6247
6248 void intel_connector_attach_encoder(struct intel_connector *connector,
6249                                     struct intel_encoder *encoder)
6250 {
6251         connector->encoder = encoder;
6252         drm_mode_connector_attach_encoder(&connector->base,
6253                                           &encoder->base);
6254 }
6255
6256 /*
6257  * set vga decode state - true == enable VGA decode
6258  */
6259 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6260 {
6261         struct drm_i915_private *dev_priv = dev->dev_private;
6262         u16 gmch_ctrl;
6263
6264         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6265         if (state)
6266                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6267         else
6268                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6269         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6270         return 0;
6271 }