drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45
  46 #include <asm/byteorder.h>
  47 #include <asm/page.h>
  48 #include <asm/system.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define DESCRIPTOR_OUTPUT_MORE          0
  58 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  59 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  60 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  61 #define DESCRIPTOR_STATUS               (1 << 11)
  62 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  63 #define DESCRIPTOR_PING                 (1 << 7)
  64 #define DESCRIPTOR_YY                   (1 << 6)
  65 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  66 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  67 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  68 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  69 #define DESCRIPTOR_WAIT                 (3 << 0)
  70
  71 struct descriptor {
  72         __le16 req_count;
  73         __le16 control;
  74         __le32 data_address;
  75         __le32 branch_address;
  76         __le16 res_count;
  77         __le16 transfer_status;
  78 } __attribute__((aligned(16)));
  79
  80 #define CONTROL_SET(regs)       (regs)
  81 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  82 #define COMMAND_PTR(regs)       ((regs) + 12)
  83 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  84
  85 #define AR_BUFFER_SIZE  (32*1024)
  86 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  87 /* we need at least two pages for proper list management */
  88 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  89
  90 #define MAX_ASYNC_PAYLOAD       4096
  91 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  92 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  93
  94 struct ar_context {
  95         struct fw_ohci *ohci;
  96         struct page *pages[AR_BUFFERS];
  97         void *buffer;
  98         struct descriptor *descriptors;
  99         dma_addr_t descriptors_bus;
 100         void *pointer;
 101         unsigned int last_buffer_index;
 102         u32 regs;
 103         struct tasklet_struct tasklet;
 104 };
 105
 106 struct context;
 107
 108 typedef int (*descriptor_callback_t)(struct context *ctx,
 109                                      struct descriptor *d,
 110                                      struct descriptor *last);
 111
 112 /*
 113  * A buffer that contains a block of DMA-able coherent memory used for
 114  * storing a portion of a DMA descriptor program.
 115  */
 116 struct descriptor_buffer {
 117         struct list_head list;
 118         dma_addr_t buffer_bus;
 119         size_t buffer_size;
 120         size_t used;
 121         struct descriptor buffer[0];
 122 };
 123
 124 struct context {
 125         struct fw_ohci *ohci;
 126         u32 regs;
 127         int total_allocation;
 128         bool running;
 129         bool flushing;
 130
 131         /*
 132          * List of page-sized buffers for storing DMA descriptors.
 133          * Head of list contains buffers in use and tail of list contains
 134          * free buffers.
 135          */
 136         struct list_head buffer_list;
 137
 138         /*
 139          * Pointer to a buffer inside buffer_list that contains the tail
 140          * end of the current DMA program.
 141          */
 142         struct descriptor_buffer *buffer_tail;
 143
 144         /*
 145          * The descriptor containing the branch address of the first
 146          * descriptor that has not yet been filled by the device.
 147          */
 148         struct descriptor *last;
 149
 150         /*
 151          * The last descriptor in the DMA program.  It contains the branch
 152          * address that must be updated upon appending a new descriptor.
 153          */
 154         struct descriptor *prev;
 155
 156         descriptor_callback_t callback;
 157
 158         struct tasklet_struct tasklet;
 159 };
 160
 161 #define IT_HEADER_SY(v)          ((v) <<  0)
 162 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 163 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 164 #define IT_HEADER_TAG(v)         ((v) << 14)
 165 #define IT_HEADER_SPEED(v)       ((v) << 16)
 166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 167
 168 struct iso_context {
 169         struct fw_iso_context base;
 170         struct context context;
 171         int excess_bytes;
 172         void *header;
 173         size_t header_length;
 174
 175         u8 sync;
 176         u8 tags;
 177 };
 178
 179 #define CONFIG_ROM_SIZE 1024
 180
 181 struct fw_ohci {
 182         struct fw_card card;
 183
 184         __iomem char *registers;
 185         int node_id;
 186         int generation;
 187         int request_generation; /* for timestamping incoming requests */
 188         unsigned quirks;
 189         unsigned int pri_req_max;
 190         u32 bus_time;
 191         bool is_root;
 192         bool csr_state_setclear_abdicate;
 193         int n_ir;
 194         int n_it;
 195         /*
 196          * Spinlock for accessing fw_ohci data.  Never call out of
 197          * this driver with this lock held.
 198          */
 199         spinlock_t lock;
 200
 201         struct mutex phy_reg_mutex;
 202
 203         void *misc_buffer;
 204         dma_addr_t misc_buffer_bus;
 205
 206         struct ar_context ar_request_ctx;
 207         struct ar_context ar_response_ctx;
 208         struct context at_request_ctx;
 209         struct context at_response_ctx;
 210
 211         u32 it_context_mask;     /* unoccupied IT contexts */
 212         struct iso_context *it_context_list;
 213         u64 ir_context_channels; /* unoccupied channels */
 214         u32 ir_context_mask;     /* unoccupied IR contexts */
 215         struct iso_context *ir_context_list;
 216         u64 mc_channels; /* channels in use by the multichannel IR context */
 217         bool mc_allocated;
 218
 219         __be32    *config_rom;
 220         dma_addr_t config_rom_bus;
 221         __be32    *next_config_rom;
 222         dma_addr_t next_config_rom_bus;
 223         __be32     next_header;
 224
 225         __le32    *self_id_cpu;
 226         dma_addr_t self_id_bus;
 227         struct tasklet_struct bus_reset_tasklet;
 228
 229         u32 self_id_buffer[512];
 230 };
 231
 232 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 233 {
 234         return container_of(card, struct fw_ohci, card);
 235 }
 236
 237 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 238 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 239 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 240 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 241 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 242 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 243
 244 #define CONTEXT_RUN     0x8000
 245 #define CONTEXT_WAKE    0x1000
 246 #define CONTEXT_DEAD    0x0800
 247 #define CONTEXT_ACTIVE  0x0400
 248
 249 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 250 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 251 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 252
 253 #define OHCI1394_REGISTER_SIZE          0x800
 254 #define OHCI_LOOP_COUNT                 500
 255 #define OHCI1394_PCI_HCI_Control        0x40
 256 #define SELF_ID_BUF_SIZE                0x800
 257 #define OHCI_TCODE_PHY_PACKET           0x0e
 258 #define OHCI_VERSION_1_1                0x010010
 259
 260 static char ohci_driver_name[] = KBUILD_MODNAME;
 261
 262 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 263 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 264 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 265
 266 #define QUIRK_CYCLE_TIMER               1
 267 #define QUIRK_RESET_PACKET              2
 268 #define QUIRK_BE_HEADERS                4
 269 #define QUIRK_NO_1394A                  8
 270 #define QUIRK_NO_MSI                    16
 271
 272 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 273 static const struct {
 274         unsigned short vendor, device, revision, flags;
 275 } ohci_quirks[] = {
 276         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 277                 QUIRK_CYCLE_TIMER},
 278
 279         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 280                 QUIRK_BE_HEADERS},
 281
 282         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 283                 QUIRK_NO_MSI},
 284
 285         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 286                 QUIRK_NO_MSI},
 287
 288         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 289                 QUIRK_CYCLE_TIMER},
 290
 291         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 292                 QUIRK_CYCLE_TIMER},
 293
 294         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 295                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 296
 297         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 298                 QUIRK_RESET_PACKET},
 299
 300         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 301                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 302         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 303                 QUIRK_NO_MSI},
 304 };
 305
 306 /* This overrides anything that was found in ohci_quirks[]. */
 307 static int param_quirks;
 308 module_param_named(quirks, param_quirks, int, 0644);
 309 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 310         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 311         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 312         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 313         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 314         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 315         ")");
 316
 317 #define OHCI_PARAM_DEBUG_AT_AR          1
 318 #define OHCI_PARAM_DEBUG_SELFIDS        2
 319 #define OHCI_PARAM_DEBUG_IRQS           4
 320 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 321
 322 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 323
 324 static int param_debug;
 325 module_param_named(debug, param_debug, int, 0644);
 326 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 327         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 328         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 329         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 330         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 331         ", or a combination, or all = -1)");
 332
 333 static void log_irqs(u32 evt)
 334 {
 335         if (likely(!(param_debug &
 336                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 337                 return;
 338
 339         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 340             !(evt & OHCI1394_busReset))
 341                 return;
 342
 343         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 344             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 345             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 346             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 347             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 348             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 349             evt & OHCI1394_isochRx              ? " IR"                 : "",
 350             evt & OHCI1394_isochTx              ? " IT"                 : "",
 351             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 352             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 353             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 354             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 355             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 356             evt & OHCI1394_busReset             ? " busReset"           : "",
 357             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 358                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 359                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 360                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 361                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 362                     OHCI1394_cycleInconsistent |
 363                     OHCI1394_regAccessFail | OHCI1394_busReset)
 364                                                 ? " ?"                  : "");
 365 }
 366
 367 static const char *speed[] = {
 368         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 369 };
 370 static const char *power[] = {
 371         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 372         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 373 };
 374 static const char port[] = { '.', '-', 'p', 'c', };
 375
 376 static char _p(u32 *s, int shift)
 377 {
 378         return port[*s >> shift & 3];
 379 }
 380
 381 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 382 {
 383         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 384                 return;
 385
 386         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 387                   self_id_count, generation, node_id);
 388
 389         for (; self_id_count--; ++s)
 390                 if ((*s & 1 << 23) == 0)
 391                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 392                             "%s gc=%d %s %s%s%s\n",
 393                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 394                             speed[*s >> 14 & 3], *s >> 16 & 63,
 395                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 396                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 397                 else
 398                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 399                             *s, *s >> 24 & 63,
 400                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 401                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 402 }
 403
 404 static const char *evts[] = {
 405         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 406         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 407         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 408         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 409         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 410         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 411         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 412         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 413         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 414         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 415         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 416         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 417         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 418         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 419         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 420         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 421         [0x20] = "pending/cancelled",
 422 };
 423 static const char *tcodes[] = {
 424         [0x0] = "QW req",               [0x1] = "BW req",
 425         [0x2] = "W resp",               [0x3] = "-reserved-",
 426         [0x4] = "QR req",               [0x5] = "BR req",
 427         [0x6] = "QR resp",              [0x7] = "BR resp",
 428         [0x8] = "cycle start",          [0x9] = "Lk req",
 429         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 430         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 431         [0xe] = "link internal",        [0xf] = "-reserved-",
 432 };
 433
 434 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 435 {
 436         int tcode = header[0] >> 4 & 0xf;
 437         char specific[12];
 438
 439         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 440                 return;
 441
 442         if (unlikely(evt >= ARRAY_SIZE(evts)))
 443                         evt = 0x1f;
 444
 445         if (evt == OHCI1394_evt_bus_reset) {
 446                 fw_notify("A%c evt_bus_reset, generation %d\n",
 447                     dir, (header[2] >> 16) & 0xff);
 448                 return;
 449         }
 450
 451         switch (tcode) {
 452         case 0x0: case 0x6: case 0x8:
 453                 snprintf(specific, sizeof(specific), " = %08x",
 454                          be32_to_cpu((__force __be32)header[3]));
 455                 break;
 456         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 457                 snprintf(specific, sizeof(specific), " %x,%x",
 458                          header[3] >> 16, header[3] & 0xffff);
 459                 break;
 460         default:
 461                 specific[0] = '\0';
 462         }
 463
 464         switch (tcode) {
 465         case 0xa:
 466                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 467                 break;
 468         case 0xe:
 469                 fw_notify("A%c %s, PHY %08x %08x\n",
 470                           dir, evts[evt], header[1], header[2]);
 471                 break;
 472         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 473                 fw_notify("A%c spd %x tl %02x, "
 474                     "%04x -> %04x, %s, "
 475                     "%s, %04x%08x%s\n",
 476                     dir, speed, header[0] >> 10 & 0x3f,
 477                     header[1] >> 16, header[0] >> 16, evts[evt],
 478                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 479                 break;
 480         default:
 481                 fw_notify("A%c spd %x tl %02x, "
 482                     "%04x -> %04x, %s, "
 483                     "%s%s\n",
 484                     dir, speed, header[0] >> 10 & 0x3f,
 485                     header[1] >> 16, header[0] >> 16, evts[evt],
 486                     tcodes[tcode], specific);
 487         }
 488 }
 489
 490 #else
 491
 492 #define param_debug 0
 493 static inline void log_irqs(u32 evt) {}
 494 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 495 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 496
 497 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 498
 499 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 500 {
 501         writel(data, ohci->registers + offset);
 502 }
 503
 504 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 505 {
 506         return readl(ohci->registers + offset);
 507 }
 508
 509 static inline void flush_writes(const struct fw_ohci *ohci)
 510 {
 511         /* Do a dummy read to flush writes. */
 512         reg_read(ohci, OHCI1394_Version);
 513 }
 514
 515 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 516 {
 517         u32 val;
 518         int i;
 519
 520         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 521         for (i = 0; i < 3 + 100; i++) {
 522                 val = reg_read(ohci, OHCI1394_PhyControl);
 523                 if (val & OHCI1394_PhyControl_ReadDone)
 524                         return OHCI1394_PhyControl_ReadData(val);
 525
 526                 /*
 527                  * Try a few times without waiting.  Sleeping is necessary
 528                  * only when the link/PHY interface is busy.
 529                  */
 530                 if (i >= 3)
 531                         msleep(1);
 532         }
 533         fw_error("failed to read phy reg\n");
 534
 535         return -EBUSY;
 536 }
 537
 538 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 539 {
 540         int i;
 541
 542         reg_write(ohci, OHCI1394_PhyControl,
 543                   OHCI1394_PhyControl_Write(addr, val));
 544         for (i = 0; i < 3 + 100; i++) {
 545                 val = reg_read(ohci, OHCI1394_PhyControl);
 546                 if (!(val & OHCI1394_PhyControl_WritePending))
 547                         return 0;
 548
 549                 if (i >= 3)
 550                         msleep(1);
 551         }
 552         fw_error("failed to write phy reg\n");
 553
 554         return -EBUSY;
 555 }
 556
 557 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 558                           int clear_bits, int set_bits)
 559 {
 560         int ret = read_phy_reg(ohci, addr);
 561         if (ret < 0)
 562                 return ret;
 563
 564         /*
 565          * The interrupt status bits are cleared by writing a one bit.
 566          * Avoid clearing them unless explicitly requested in set_bits.
 567          */
 568         if (addr == 5)
 569                 clear_bits |= PHY_INT_STATUS_BITS;
 570
 571         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 572 }
 573
 574 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 575 {
 576         int ret;
 577
 578         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 579         if (ret < 0)
 580                 return ret;
 581
 582         return read_phy_reg(ohci, addr);
 583 }
 584
 585 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 586 {
 587         struct fw_ohci *ohci = fw_ohci(card);
 588         int ret;
 589
 590         mutex_lock(&ohci->phy_reg_mutex);
 591         ret = read_phy_reg(ohci, addr);
 592         mutex_unlock(&ohci->phy_reg_mutex);
 593
 594         return ret;
 595 }
 596
 597 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 598                                int clear_bits, int set_bits)
 599 {
 600         struct fw_ohci *ohci = fw_ohci(card);
 601         int ret;
 602
 603         mutex_lock(&ohci->phy_reg_mutex);
 604         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 605         mutex_unlock(&ohci->phy_reg_mutex);
 606
 607         return ret;
 608 }
 609
 610 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 611 {
 612         return page_private(ctx->pages[i]);
 613 }
 614
 615 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 616 {
 617         struct descriptor *d;
 618
 619         d = &ctx->descriptors[index];
 620         d->branch_address  &= cpu_to_le32(~0xf);
 621         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 622         d->transfer_status =  0;
 623
 624         wmb(); /* finish init of new descriptors before branch_address update */
 625         d = &ctx->descriptors[ctx->last_buffer_index];
 626         d->branch_address  |= cpu_to_le32(1);
 627
 628         ctx->last_buffer_index = index;
 629
 630         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 631         flush_writes(ctx->ohci);
 632 }
 633
 634 static void ar_context_release(struct ar_context *ctx)
 635 {
 636         unsigned int i;
 637
 638         if (ctx->buffer)
 639                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 640
 641         for (i = 0; i < AR_BUFFERS; i++)
 642                 if (ctx->pages[i]) {
 643                         dma_unmap_page(ctx->ohci->card.device,
 644                                        ar_buffer_bus(ctx, i),
 645                                        PAGE_SIZE, DMA_FROM_DEVICE);
 646                         __free_page(ctx->pages[i]);
 647                 }
 648 }
 649
 650 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 651 {
 652         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 653                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 654                 flush_writes(ctx->ohci);
 655
 656                 fw_error("AR error: %s; DMA stopped\n", error_msg);
 657         }
 658         /* FIXME: restart? */
 659 }
 660
 661 static inline unsigned int ar_next_buffer_index(unsigned int index)
 662 {
 663         return (index + 1) % AR_BUFFERS;
 664 }
 665
 666 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 667 {
 668         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 669 }
 670
 671 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 672 {
 673         return ar_next_buffer_index(ctx->last_buffer_index);
 674 }
 675
 676 /*
 677  * We search for the buffer that contains the last AR packet DMA data written
 678  * by the controller.
 679  */
 680 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 681                                                  unsigned int *buffer_offset)
 682 {
 683         unsigned int i, next_i, last = ctx->last_buffer_index;
 684         __le16 res_count, next_res_count;
 685
 686         i = ar_first_buffer_index(ctx);
 687         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 688
 689         /* A buffer that is not yet completely filled must be the last one. */
 690         while (i != last && res_count == 0) {
 691
 692                 /* Peek at the next descriptor. */
 693                 next_i = ar_next_buffer_index(i);
 694                 rmb(); /* read descriptors in order */
 695                 next_res_count = ACCESS_ONCE(
 696                                 ctx->descriptors[next_i].res_count);
 697                 /*
 698                  * If the next descriptor is still empty, we must stop at this
 699                  * descriptor.
 700                  */
 701                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 702                         /*
 703                          * The exception is when the DMA data for one packet is
 704                          * split over three buffers; in this case, the middle
 705                          * buffer's descriptor might be never updated by the
 706                          * controller and look still empty, and we have to peek
 707                          * at the third one.
 708                          */
 709                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 710                                 next_i = ar_next_buffer_index(next_i);
 711                                 rmb();
 712                                 next_res_count = ACCESS_ONCE(
 713                                         ctx->descriptors[next_i].res_count);
 714                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 715                                         goto next_buffer_is_active;
 716                         }
 717
 718                         break;
 719                 }
 720
 721 next_buffer_is_active:
 722                 i = next_i;
 723                 res_count = next_res_count;
 724         }
 725
 726         rmb(); /* read res_count before the DMA data */
 727
 728         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 729         if (*buffer_offset > PAGE_SIZE) {
 730                 *buffer_offset = 0;
 731                 ar_context_abort(ctx, "corrupted descriptor");
 732         }
 733
 734         return i;
 735 }
 736
 737 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 738                                     unsigned int end_buffer_index,
 739                                     unsigned int end_buffer_offset)
 740 {
 741         unsigned int i;
 742
 743         i = ar_first_buffer_index(ctx);
 744         while (i != end_buffer_index) {
 745                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 746                                         ar_buffer_bus(ctx, i),
 747                                         PAGE_SIZE, DMA_FROM_DEVICE);
 748                 i = ar_next_buffer_index(i);
 749         }
 750         if (end_buffer_offset > 0)
 751                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 752                                         ar_buffer_bus(ctx, i),
 753                                         end_buffer_offset, DMA_FROM_DEVICE);
 754 }
 755
 756 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 757 #define cond_le32_to_cpu(v) \
 758         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 759 #else
 760 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 761 #endif
 762
 763 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 764 {
 765         struct fw_ohci *ohci = ctx->ohci;
 766         struct fw_packet p;
 767         u32 status, length, tcode;
 768         int evt;
 769
 770         p.header[0] = cond_le32_to_cpu(buffer[0]);
 771         p.header[1] = cond_le32_to_cpu(buffer[1]);
 772         p.header[2] = cond_le32_to_cpu(buffer[2]);
 773
 774         tcode = (p.header[0] >> 4) & 0x0f;
 775         switch (tcode) {
 776         case TCODE_WRITE_QUADLET_REQUEST:
 777         case TCODE_READ_QUADLET_RESPONSE:
 778                 p.header[3] = (__force __u32) buffer[3];
 779                 p.header_length = 16;
 780                 p.payload_length = 0;
 781                 break;
 782
 783         case TCODE_READ_BLOCK_REQUEST :
 784                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 785                 p.header_length = 16;
 786                 p.payload_length = 0;
 787                 break;
 788
 789         case TCODE_WRITE_BLOCK_REQUEST:
 790         case TCODE_READ_BLOCK_RESPONSE:
 791         case TCODE_LOCK_REQUEST:
 792         case TCODE_LOCK_RESPONSE:
 793                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 794                 p.header_length = 16;
 795                 p.payload_length = p.header[3] >> 16;
 796                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 797                         ar_context_abort(ctx, "invalid packet length");
 798                         return NULL;
 799                 }
 800                 break;
 801
 802         case TCODE_WRITE_RESPONSE:
 803         case TCODE_READ_QUADLET_REQUEST:
 804         case OHCI_TCODE_PHY_PACKET:
 805                 p.header_length = 12;
 806                 p.payload_length = 0;
 807                 break;
 808
 809         default:
 810                 ar_context_abort(ctx, "invalid tcode");
 811                 return NULL;
 812         }
 813
 814         p.payload = (void *) buffer + p.header_length;
 815
 816         /* FIXME: What to do about evt_* errors? */
 817         length = (p.header_length + p.payload_length + 3) / 4;
 818         status = cond_le32_to_cpu(buffer[length]);
 819         evt    = (status >> 16) & 0x1f;
 820
 821         p.ack        = evt - 16;
 822         p.speed      = (status >> 21) & 0x7;
 823         p.timestamp  = status & 0xffff;
 824         p.generation = ohci->request_generation;
 825
 826         log_ar_at_event('R', p.speed, p.header, evt);
 827
 828         /*
 829          * Several controllers, notably from NEC and VIA, forget to
 830          * write ack_complete status at PHY packet reception.
 831          */
 832         if (evt == OHCI1394_evt_no_status &&
 833             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 834                 p.ack = ACK_COMPLETE;
 835
 836         /*
 837          * The OHCI bus reset handler synthesizes a PHY packet with
 838          * the new generation number when a bus reset happens (see
 839          * section 8.4.2.3).  This helps us determine when a request
 840          * was received and make sure we send the response in the same
 841          * generation.  We only need this for requests; for responses
 842          * we use the unique tlabel for finding the matching
 843          * request.
 844          *
 845          * Alas some chips sometimes emit bus reset packets with a
 846          * wrong generation.  We set the correct generation for these
 847          * at a slightly incorrect time (in bus_reset_tasklet).
 848          */
 849         if (evt == OHCI1394_evt_bus_reset) {
 850                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 851                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 852         } else if (ctx == &ohci->ar_request_ctx) {
 853                 fw_core_handle_request(&ohci->card, &p);
 854         } else {
 855                 fw_core_handle_response(&ohci->card, &p);
 856         }
 857
 858         return buffer + length + 1;
 859 }
 860
 861 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 862 {
 863         void *next;
 864
 865         while (p < end) {
 866                 next = handle_ar_packet(ctx, p);
 867                 if (!next)
 868                         return p;
 869                 p = next;
 870         }
 871
 872         return p;
 873 }
 874
 875 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 876 {
 877         unsigned int i;
 878
 879         i = ar_first_buffer_index(ctx);
 880         while (i != end_buffer) {
 881                 dma_sync_single_for_device(ctx->ohci->card.device,
 882                                            ar_buffer_bus(ctx, i),
 883                                            PAGE_SIZE, DMA_FROM_DEVICE);
 884                 ar_context_link_page(ctx, i);
 885                 i = ar_next_buffer_index(i);
 886         }
 887 }
 888
 889 static void ar_context_tasklet(unsigned long data)
 890 {
 891         struct ar_context *ctx = (struct ar_context *)data;
 892         unsigned int end_buffer_index, end_buffer_offset;
 893         void *p, *end;
 894
 895         p = ctx->pointer;
 896         if (!p)
 897                 return;
 898
 899         end_buffer_index = ar_search_last_active_buffer(ctx,
 900                                                         &end_buffer_offset);
 901         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 902         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 903
 904         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 905                 /*
 906                  * The filled part of the overall buffer wraps around; handle
 907                  * all packets up to the buffer end here.  If the last packet
 908                  * wraps around, its tail will be visible after the buffer end
 909                  * because the buffer start pages are mapped there again.
 910                  */
 911                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 912                 p = handle_ar_packets(ctx, p, buffer_end);
 913                 if (p < buffer_end)
 914                         goto error;
 915                 /* adjust p to point back into the actual buffer */
 916                 p -= AR_BUFFERS * PAGE_SIZE;
 917         }
 918
 919         p = handle_ar_packets(ctx, p, end);
 920         if (p != end) {
 921                 if (p > end)
 922                         ar_context_abort(ctx, "inconsistent descriptor");
 923                 goto error;
 924         }
 925
 926         ctx->pointer = p;
 927         ar_recycle_buffers(ctx, end_buffer_index);
 928
 929         return;
 930
 931 error:
 932         ctx->pointer = NULL;
 933 }
 934
 935 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 936                            unsigned int descriptors_offset, u32 regs)
 937 {
 938         unsigned int i;
 939         dma_addr_t dma_addr;
 940         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 941         struct descriptor *d;
 942
 943         ctx->regs        = regs;
 944         ctx->ohci        = ohci;
 945         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 946
 947         for (i = 0; i < AR_BUFFERS; i++) {
 948                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 949                 if (!ctx->pages[i])
 950                         goto out_of_memory;
 951                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 952                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 953                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 954                         __free_page(ctx->pages[i]);
 955                         ctx->pages[i] = NULL;
 956                         goto out_of_memory;
 957                 }
 958                 set_page_private(ctx->pages[i], dma_addr);
 959         }
 960
 961         for (i = 0; i < AR_BUFFERS; i++)
 962                 pages[i]              = ctx->pages[i];
 963         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 964                 pages[AR_BUFFERS + i] = ctx->pages[i];
 965         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 966                                  -1, PAGE_KERNEL);
 967         if (!ctx->buffer)
 968                 goto out_of_memory;
 969
 970         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
 971         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
 972
 973         for (i = 0; i < AR_BUFFERS; i++) {
 974                 d = &ctx->descriptors[i];
 975                 d->req_count      = cpu_to_le16(PAGE_SIZE);
 976                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 977                                                 DESCRIPTOR_STATUS |
 978                                                 DESCRIPTOR_BRANCH_ALWAYS);
 979                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
 980                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
 981                         ar_next_buffer_index(i) * sizeof(struct descriptor));
 982         }
 983
 984         return 0;
 985
 986 out_of_memory:
 987         ar_context_release(ctx);
 988
 989         return -ENOMEM;
 990 }
 991
 992 static void ar_context_run(struct ar_context *ctx)
 993 {
 994         unsigned int i;
 995
 996         for (i = 0; i < AR_BUFFERS; i++)
 997                 ar_context_link_page(ctx, i);
 998
 999         ctx->pointer = ctx->buffer;
1000
1001         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1002         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1003         flush_writes(ctx->ohci);
1004 }
1005
1006 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1007 {
1008         int b, key;
1009
1010         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1011         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1012
1013         /* figure out which descriptor the branch address goes in */
1014         if (z == 2 && (b == 3 || key == 2))
1015                 return d;
1016         else
1017                 return d + z - 1;
1018 }
1019
1020 static void context_tasklet(unsigned long data)
1021 {
1022         struct context *ctx = (struct context *) data;
1023         struct descriptor *d, *last;
1024         u32 address;
1025         int z;
1026         struct descriptor_buffer *desc;
1027
1028         desc = list_entry(ctx->buffer_list.next,
1029                         struct descriptor_buffer, list);
1030         last = ctx->last;
1031         while (last->branch_address != 0) {
1032                 struct descriptor_buffer *old_desc = desc;
1033                 address = le32_to_cpu(last->branch_address);
1034                 z = address & 0xf;
1035                 address &= ~0xf;
1036
1037                 /* If the branch address points to a buffer outside of the
1038                  * current buffer, advance to the next buffer. */
1039                 if (address < desc->buffer_bus ||
1040                                 address >= desc->buffer_bus + desc->used)
1041                         desc = list_entry(desc->list.next,
1042                                         struct descriptor_buffer, list);
1043                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1044                 last = find_branch_descriptor(d, z);
1045
1046                 if (!ctx->callback(ctx, d, last))
1047                         break;
1048
1049                 if (old_desc != desc) {
1050                         /* If we've advanced to the next buffer, move the
1051                          * previous buffer to the free list. */
1052                         unsigned long flags;
1053                         old_desc->used = 0;
1054                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1055                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1056                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1057                 }
1058                 ctx->last = last;
1059         }
1060 }
1061
1062 /*
1063  * Allocate a new buffer and add it to the list of free buffers for this
1064  * context.  Must be called with ohci->lock held.
1065  */
1066 static int context_add_buffer(struct context *ctx)
1067 {
1068         struct descriptor_buffer *desc;
1069         dma_addr_t uninitialized_var(bus_addr);
1070         int offset;
1071
1072         /*
1073          * 16MB of descriptors should be far more than enough for any DMA
1074          * program.  This will catch run-away userspace or DoS attacks.
1075          */
1076         if (ctx->total_allocation >= 16*1024*1024)
1077                 return -ENOMEM;
1078
1079         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1080                         &bus_addr, GFP_ATOMIC);
1081         if (!desc)
1082                 return -ENOMEM;
1083
1084         offset = (void *)&desc->buffer - (void *)desc;
1085         desc->buffer_size = PAGE_SIZE - offset;
1086         desc->buffer_bus = bus_addr + offset;
1087         desc->used = 0;
1088
1089         list_add_tail(&desc->list, &ctx->buffer_list);
1090         ctx->total_allocation += PAGE_SIZE;
1091
1092         return 0;
1093 }
1094
1095 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1096                         u32 regs, descriptor_callback_t callback)
1097 {
1098         ctx->ohci = ohci;
1099         ctx->regs = regs;
1100         ctx->total_allocation = 0;
1101
1102         INIT_LIST_HEAD(&ctx->buffer_list);
1103         if (context_add_buffer(ctx) < 0)
1104                 return -ENOMEM;
1105
1106         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1107                         struct descriptor_buffer, list);
1108
1109         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1110         ctx->callback = callback;
1111
1112         /*
1113          * We put a dummy descriptor in the buffer that has a NULL
1114          * branch address and looks like it's been sent.  That way we
1115          * have a descriptor to append DMA programs to.
1116          */
1117         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1118         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1119         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1120         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1121         ctx->last = ctx->buffer_tail->buffer;
1122         ctx->prev = ctx->buffer_tail->buffer;
1123
1124         return 0;
1125 }
1126
1127 static void context_release(struct context *ctx)
1128 {
1129         struct fw_card *card = &ctx->ohci->card;
1130         struct descriptor_buffer *desc, *tmp;
1131
1132         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1133                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1134                         desc->buffer_bus -
1135                         ((void *)&desc->buffer - (void *)desc));
1136 }
1137
1138 /* Must be called with ohci->lock held */
1139 static struct descriptor *context_get_descriptors(struct context *ctx,
1140                                                   int z, dma_addr_t *d_bus)
1141 {
1142         struct descriptor *d = NULL;
1143         struct descriptor_buffer *desc = ctx->buffer_tail;
1144
1145         if (z * sizeof(*d) > desc->buffer_size)
1146                 return NULL;
1147
1148         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1149                 /* No room for the descriptor in this buffer, so advance to the
1150                  * next one. */
1151
1152                 if (desc->list.next == &ctx->buffer_list) {
1153                         /* If there is no free buffer next in the list,
1154                          * allocate one. */
1155                         if (context_add_buffer(ctx) < 0)
1156                                 return NULL;
1157                 }
1158                 desc = list_entry(desc->list.next,
1159                                 struct descriptor_buffer, list);
1160                 ctx->buffer_tail = desc;
1161         }
1162
1163         d = desc->buffer + desc->used / sizeof(*d);
1164         memset(d, 0, z * sizeof(*d));
1165         *d_bus = desc->buffer_bus + desc->used;
1166
1167         return d;
1168 }
1169
1170 static void context_run(struct context *ctx, u32 extra)
1171 {
1172         struct fw_ohci *ohci = ctx->ohci;
1173
1174         reg_write(ohci, COMMAND_PTR(ctx->regs),
1175                   le32_to_cpu(ctx->last->branch_address));
1176         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1177         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1178         ctx->running = true;
1179         flush_writes(ohci);
1180 }
1181
1182 static void context_append(struct context *ctx,
1183                            struct descriptor *d, int z, int extra)
1184 {
1185         dma_addr_t d_bus;
1186         struct descriptor_buffer *desc = ctx->buffer_tail;
1187
1188         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1189
1190         desc->used += (z + extra) * sizeof(*d);
1191
1192         wmb(); /* finish init of new descriptors before branch_address update */
1193         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1194         ctx->prev = find_branch_descriptor(d, z);
1195
1196         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1197         flush_writes(ctx->ohci);
1198 }
1199
1200 static void context_stop(struct context *ctx)
1201 {
1202         u32 reg;
1203         int i;
1204
1205         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1206         ctx->running = false;
1207         flush_writes(ctx->ohci);
1208
1209         for (i = 0; i < 10; i++) {
1210                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1211                 if ((reg & CONTEXT_ACTIVE) == 0)
1212                         return;
1213
1214                 mdelay(1);
1215         }
1216         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1217 }
1218
1219 struct driver_data {
1220         struct fw_packet *packet;
1221 };
1222
1223 /*
1224  * This function apppends a packet to the DMA queue for transmission.
1225  * Must always be called with the ochi->lock held to ensure proper
1226  * generation handling and locking around packet queue manipulation.
1227  */
1228 static int at_context_queue_packet(struct context *ctx,
1229                                    struct fw_packet *packet)
1230 {
1231         struct fw_ohci *ohci = ctx->ohci;
1232         dma_addr_t d_bus, uninitialized_var(payload_bus);
1233         struct driver_data *driver_data;
1234         struct descriptor *d, *last;
1235         __le32 *header;
1236         int z, tcode;
1237
1238         d = context_get_descriptors(ctx, 4, &d_bus);
1239         if (d == NULL) {
1240                 packet->ack = RCODE_SEND_ERROR;
1241                 return -1;
1242         }
1243
1244         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1245         d[0].res_count = cpu_to_le16(packet->timestamp);
1246
1247         /*
1248          * The DMA format for asyncronous link packets is different
1249          * from the IEEE1394 layout, so shift the fields around
1250          * accordingly.
1251          */
1252
1253         tcode = (packet->header[0] >> 4) & 0x0f;
1254         header = (__le32 *) &d[1];
1255         switch (tcode) {
1256         case TCODE_WRITE_QUADLET_REQUEST:
1257         case TCODE_WRITE_BLOCK_REQUEST:
1258         case TCODE_WRITE_RESPONSE:
1259         case TCODE_READ_QUADLET_REQUEST:
1260         case TCODE_READ_BLOCK_REQUEST:
1261         case TCODE_READ_QUADLET_RESPONSE:
1262         case TCODE_READ_BLOCK_RESPONSE:
1263         case TCODE_LOCK_REQUEST:
1264         case TCODE_LOCK_RESPONSE:
1265                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1266                                         (packet->speed << 16));
1267                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1268                                         (packet->header[0] & 0xffff0000));
1269                 header[2] = cpu_to_le32(packet->header[2]);
1270
1271                 if (TCODE_IS_BLOCK_PACKET(tcode))
1272                         header[3] = cpu_to_le32(packet->header[3]);
1273                 else
1274                         header[3] = (__force __le32) packet->header[3];
1275
1276                 d[0].req_count = cpu_to_le16(packet->header_length);
1277                 break;
1278
1279         case TCODE_LINK_INTERNAL:
1280                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1281                                         (packet->speed << 16));
1282                 header[1] = cpu_to_le32(packet->header[1]);
1283                 header[2] = cpu_to_le32(packet->header[2]);
1284                 d[0].req_count = cpu_to_le16(12);
1285
1286                 if (is_ping_packet(&packet->header[1]))
1287                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1288                 break;
1289
1290         case TCODE_STREAM_DATA:
1291                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1292                                         (packet->speed << 16));
1293                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1294                 d[0].req_count = cpu_to_le16(8);
1295                 break;
1296
1297         default:
1298                 /* BUG(); */
1299                 packet->ack = RCODE_SEND_ERROR;
1300                 return -1;
1301         }
1302
1303         driver_data = (struct driver_data *) &d[3];
1304         driver_data->packet = packet;
1305         packet->driver_data = driver_data;
1306
1307         if (packet->payload_length > 0) {
1308                 payload_bus =
1309                         dma_map_single(ohci->card.device, packet->payload,
1310                                        packet->payload_length, DMA_TO_DEVICE);
1311                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1312                         packet->ack = RCODE_SEND_ERROR;
1313                         return -1;
1314                 }
1315                 packet->payload_bus     = payload_bus;
1316                 packet->payload_mapped  = true;
1317
1318                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1319                 d[2].data_address = cpu_to_le32(payload_bus);
1320                 last = &d[2];
1321                 z = 3;
1322         } else {
1323                 last = &d[0];
1324                 z = 2;
1325         }
1326
1327         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1328                                      DESCRIPTOR_IRQ_ALWAYS |
1329                                      DESCRIPTOR_BRANCH_ALWAYS);
1330
1331         /*
1332          * If the controller and packet generations don't match, we need to
1333          * bail out and try again.  If IntEvent.busReset is set, the AT context
1334          * is halted, so appending to the context and trying to run it is
1335          * futile.  Most controllers do the right thing and just flush the AT
1336          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1337          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1338          * up stalling out.  So we just bail out in software and try again
1339          * later, and everyone is happy.
1340          * FIXME: Test of IntEvent.busReset may no longer be necessary since we
1341          *        flush AT queues in bus_reset_tasklet.
1342          * FIXME: Document how the locking works.
1343          */
1344         if (ohci->generation != packet->generation ||
1345             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1346                 if (packet->payload_mapped)
1347                         dma_unmap_single(ohci->card.device, payload_bus,
1348                                          packet->payload_length, DMA_TO_DEVICE);
1349                 packet->ack = RCODE_GENERATION;
1350                 return -1;
1351         }
1352
1353         context_append(ctx, d, z, 4 - z);
1354
1355         if (!ctx->running)
1356                 context_run(ctx, 0);
1357
1358         return 0;
1359 }
1360
1361 static void at_context_flush(struct context *ctx)
1362 {
1363         tasklet_disable(&ctx->tasklet);
1364
1365         ctx->flushing = true;
1366         context_tasklet((unsigned long)ctx);
1367         ctx->flushing = false;
1368
1369         tasklet_enable(&ctx->tasklet);
1370 }
1371
1372 static int handle_at_packet(struct context *context,
1373                             struct descriptor *d,
1374                             struct descriptor *last)
1375 {
1376         struct driver_data *driver_data;
1377         struct fw_packet *packet;
1378         struct fw_ohci *ohci = context->ohci;
1379         int evt;
1380
1381         if (last->transfer_status == 0 && !context->flushing)
1382                 /* This descriptor isn't done yet, stop iteration. */
1383                 return 0;
1384
1385         driver_data = (struct driver_data *) &d[3];
1386         packet = driver_data->packet;
1387         if (packet == NULL)
1388                 /* This packet was cancelled, just continue. */
1389                 return 1;
1390
1391         if (packet->payload_mapped)
1392                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1393                                  packet->payload_length, DMA_TO_DEVICE);
1394
1395         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1396         packet->timestamp = le16_to_cpu(last->res_count);
1397
1398         log_ar_at_event('T', packet->speed, packet->header, evt);
1399
1400         switch (evt) {
1401         case OHCI1394_evt_timeout:
1402                 /* Async response transmit timed out. */
1403                 packet->ack = RCODE_CANCELLED;
1404                 break;
1405
1406         case OHCI1394_evt_flushed:
1407                 /*
1408                  * The packet was flushed should give same error as
1409                  * when we try to use a stale generation count.
1410                  */
1411                 packet->ack = RCODE_GENERATION;
1412                 break;
1413
1414         case OHCI1394_evt_missing_ack:
1415                 if (context->flushing)
1416                         packet->ack = RCODE_GENERATION;
1417                 else {
1418                         /*
1419                          * Using a valid (current) generation count, but the
1420                          * node is not on the bus or not sending acks.
1421                          */
1422                         packet->ack = RCODE_NO_ACK;
1423                 }
1424                 break;
1425
1426         case ACK_COMPLETE + 0x10:
1427         case ACK_PENDING + 0x10:
1428         case ACK_BUSY_X + 0x10:
1429         case ACK_BUSY_A + 0x10:
1430         case ACK_BUSY_B + 0x10:
1431         case ACK_DATA_ERROR + 0x10:
1432         case ACK_TYPE_ERROR + 0x10:
1433                 packet->ack = evt - 0x10;
1434                 break;
1435
1436         case OHCI1394_evt_no_status:
1437                 if (context->flushing) {
1438                         packet->ack = RCODE_GENERATION;
1439                         break;
1440                 }
1441                 /* fall through */
1442
1443         default:
1444                 packet->ack = RCODE_SEND_ERROR;
1445                 break;
1446         }
1447
1448         packet->callback(packet, &ohci->card, packet->ack);
1449
1450         return 1;
1451 }
1452
1453 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1454 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1455 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1456 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1457 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1458
1459 static void handle_local_rom(struct fw_ohci *ohci,
1460                              struct fw_packet *packet, u32 csr)
1461 {
1462         struct fw_packet response;
1463         int tcode, length, i;
1464
1465         tcode = HEADER_GET_TCODE(packet->header[0]);
1466         if (TCODE_IS_BLOCK_PACKET(tcode))
1467                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1468         else
1469                 length = 4;
1470
1471         i = csr - CSR_CONFIG_ROM;
1472         if (i + length > CONFIG_ROM_SIZE) {
1473                 fw_fill_response(&response, packet->header,
1474                                  RCODE_ADDRESS_ERROR, NULL, 0);
1475         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1476                 fw_fill_response(&response, packet->header,
1477                                  RCODE_TYPE_ERROR, NULL, 0);
1478         } else {
1479                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1480                                  (void *) ohci->config_rom + i, length);
1481         }
1482
1483         fw_core_handle_response(&ohci->card, &response);
1484 }
1485
1486 static void handle_local_lock(struct fw_ohci *ohci,
1487                               struct fw_packet *packet, u32 csr)
1488 {
1489         struct fw_packet response;
1490         int tcode, length, ext_tcode, sel, try;
1491         __be32 *payload, lock_old;
1492         u32 lock_arg, lock_data;
1493
1494         tcode = HEADER_GET_TCODE(packet->header[0]);
1495         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1496         payload = packet->payload;
1497         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1498
1499         if (tcode == TCODE_LOCK_REQUEST &&
1500             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1501                 lock_arg = be32_to_cpu(payload[0]);
1502                 lock_data = be32_to_cpu(payload[1]);
1503         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1504                 lock_arg = 0;
1505                 lock_data = 0;
1506         } else {
1507                 fw_fill_response(&response, packet->header,
1508                                  RCODE_TYPE_ERROR, NULL, 0);
1509                 goto out;
1510         }
1511
1512         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1513         reg_write(ohci, OHCI1394_CSRData, lock_data);
1514         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1515         reg_write(ohci, OHCI1394_CSRControl, sel);
1516
1517         for (try = 0; try < 20; try++)
1518                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1519                         lock_old = cpu_to_be32(reg_read(ohci,
1520                                                         OHCI1394_CSRData));
1521                         fw_fill_response(&response, packet->header,
1522                                          RCODE_COMPLETE,
1523                                          &lock_old, sizeof(lock_old));
1524                         goto out;
1525                 }
1526
1527         fw_error("swap not done (CSR lock timeout)\n");
1528         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1529
1530  out:
1531         fw_core_handle_response(&ohci->card, &response);
1532 }
1533
1534 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1535 {
1536         u64 offset, csr;
1537
1538         if (ctx == &ctx->ohci->at_request_ctx) {
1539                 packet->ack = ACK_PENDING;
1540                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1541         }
1542
1543         offset =
1544                 ((unsigned long long)
1545                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1546                 packet->header[2];
1547         csr = offset - CSR_REGISTER_BASE;
1548
1549         /* Handle config rom reads. */
1550         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1551                 handle_local_rom(ctx->ohci, packet, csr);
1552         else switch (csr) {
1553         case CSR_BUS_MANAGER_ID:
1554         case CSR_BANDWIDTH_AVAILABLE:
1555         case CSR_CHANNELS_AVAILABLE_HI:
1556         case CSR_CHANNELS_AVAILABLE_LO:
1557                 handle_local_lock(ctx->ohci, packet, csr);
1558                 break;
1559         default:
1560                 if (ctx == &ctx->ohci->at_request_ctx)
1561                         fw_core_handle_request(&ctx->ohci->card, packet);
1562                 else
1563                         fw_core_handle_response(&ctx->ohci->card, packet);
1564                 break;
1565         }
1566
1567         if (ctx == &ctx->ohci->at_response_ctx) {
1568                 packet->ack = ACK_COMPLETE;
1569                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1570         }
1571 }
1572
1573 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1574 {
1575         unsigned long flags;
1576         int ret;
1577
1578         spin_lock_irqsave(&ctx->ohci->lock, flags);
1579
1580         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1581             ctx->ohci->generation == packet->generation) {
1582                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1583                 handle_local_request(ctx, packet);
1584                 return;
1585         }
1586
1587         ret = at_context_queue_packet(ctx, packet);
1588         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1589
1590         if (ret < 0)
1591                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1592
1593 }
1594
1595 static u32 cycle_timer_ticks(u32 cycle_timer)
1596 {
1597         u32 ticks;
1598
1599         ticks = cycle_timer & 0xfff;
1600         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1601         ticks += (3072 * 8000) * (cycle_timer >> 25);
1602
1603         return ticks;
1604 }
1605
1606 /*
1607  * Some controllers exhibit one or more of the following bugs when updating the
1608  * iso cycle timer register:
1609  *  - When the lowest six bits are wrapping around to zero, a read that happens
1610  *    at the same time will return garbage in the lowest ten bits.
1611  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1612  *    not incremented for about 60 ns.
1613  *  - Occasionally, the entire register reads zero.
1614  *
1615  * To catch these, we read the register three times and ensure that the
1616  * difference between each two consecutive reads is approximately the same, i.e.
1617  * less than twice the other.  Furthermore, any negative difference indicates an
1618  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1619  * execute, so we have enough precision to compute the ratio of the differences.)
1620  */
1621 static u32 get_cycle_time(struct fw_ohci *ohci)
1622 {
1623         u32 c0, c1, c2;
1624         u32 t0, t1, t2;
1625         s32 diff01, diff12;
1626         int i;
1627
1628         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1629
1630         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1631                 i = 0;
1632                 c1 = c2;
1633                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1634                 do {
1635                         c0 = c1;
1636                         c1 = c2;
1637                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1638                         t0 = cycle_timer_ticks(c0);
1639                         t1 = cycle_timer_ticks(c1);
1640                         t2 = cycle_timer_ticks(c2);
1641                         diff01 = t1 - t0;
1642                         diff12 = t2 - t1;
1643                 } while ((diff01 <= 0 || diff12 <= 0 ||
1644                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1645                          && i++ < 20);
1646         }
1647
1648         return c2;
1649 }
1650
1651 /*
1652  * This function has to be called at least every 64 seconds.  The bus_time
1653  * field stores not only the upper 25 bits of the BUS_TIME register but also
1654  * the most significant bit of the cycle timer in bit 6 so that we can detect
1655  * changes in this bit.
1656  */
1657 static u32 update_bus_time(struct fw_ohci *ohci)
1658 {
1659         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1660
1661         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1662                 ohci->bus_time += 0x40;
1663
1664         return ohci->bus_time | cycle_time_seconds;
1665 }
1666
1667 static void bus_reset_tasklet(unsigned long data)
1668 {
1669         struct fw_ohci *ohci = (struct fw_ohci *)data;
1670         int self_id_count, i, j, reg;
1671         int generation, new_generation;
1672         unsigned long flags;
1673         void *free_rom = NULL;
1674         dma_addr_t free_rom_bus = 0;
1675         bool is_new_root;
1676
1677         reg = reg_read(ohci, OHCI1394_NodeID);
1678         if (!(reg & OHCI1394_NodeID_idValid)) {
1679                 fw_notify("node ID not valid, new bus reset in progress\n");
1680                 return;
1681         }
1682         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1683                 fw_notify("malconfigured bus\n");
1684                 return;
1685         }
1686         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1687                                OHCI1394_NodeID_nodeNumber);
1688
1689         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1690         if (!(ohci->is_root && is_new_root))
1691                 reg_write(ohci, OHCI1394_LinkControlSet,
1692                           OHCI1394_LinkControl_cycleMaster);
1693         ohci->is_root = is_new_root;
1694
1695         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1696         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1697                 fw_notify("inconsistent self IDs\n");
1698                 return;
1699         }
1700         /*
1701          * The count in the SelfIDCount register is the number of
1702          * bytes in the self ID receive buffer.  Since we also receive
1703          * the inverted quadlets and a header quadlet, we shift one
1704          * bit extra to get the actual number of self IDs.
1705          */
1706         self_id_count = (reg >> 3) & 0xff;
1707         if (self_id_count == 0 || self_id_count > 252) {
1708                 fw_notify("inconsistent self IDs\n");
1709                 return;
1710         }
1711         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1712         rmb();
1713
1714         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1715                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1716                         fw_notify("inconsistent self IDs\n");
1717                         return;
1718                 }
1719                 ohci->self_id_buffer[j] =
1720                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1721         }
1722         rmb();
1723
1724         /*
1725          * Check the consistency of the self IDs we just read.  The
1726          * problem we face is that a new bus reset can start while we
1727          * read out the self IDs from the DMA buffer. If this happens,
1728          * the DMA buffer will be overwritten with new self IDs and we
1729          * will read out inconsistent data.  The OHCI specification
1730          * (section 11.2) recommends a technique similar to
1731          * linux/seqlock.h, where we remember the generation of the
1732          * self IDs in the buffer before reading them out and compare
1733          * it to the current generation after reading them out.  If
1734          * the two generations match we know we have a consistent set
1735          * of self IDs.
1736          */
1737
1738         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1739         if (new_generation != generation) {
1740                 fw_notify("recursive bus reset detected, "
1741                           "discarding self ids\n");
1742                 return;
1743         }
1744
1745         /* FIXME: Document how the locking works. */
1746         spin_lock_irqsave(&ohci->lock, flags);
1747
1748         ohci->generation = -1; /* prevent AT packet queueing */
1749         context_stop(&ohci->at_request_ctx);
1750         context_stop(&ohci->at_response_ctx);
1751
1752         spin_unlock_irqrestore(&ohci->lock, flags);
1753
1754         /*
1755          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1756          * packets in the AT queues and software needs to drain them.
1757          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1758          */
1759         at_context_flush(&ohci->at_request_ctx);
1760         at_context_flush(&ohci->at_response_ctx);
1761
1762         spin_lock_irqsave(&ohci->lock, flags);
1763
1764         ohci->generation = generation;
1765         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1766
1767         if (ohci->quirks & QUIRK_RESET_PACKET)
1768                 ohci->request_generation = generation;
1769
1770         /*
1771          * This next bit is unrelated to the AT context stuff but we
1772          * have to do it under the spinlock also.  If a new config rom
1773          * was set up before this reset, the old one is now no longer
1774          * in use and we can free it. Update the config rom pointers
1775          * to point to the current config rom and clear the
1776          * next_config_rom pointer so a new update can take place.
1777          */
1778
1779         if (ohci->next_config_rom != NULL) {
1780                 if (ohci->next_config_rom != ohci->config_rom) {
1781                         free_rom      = ohci->config_rom;
1782                         free_rom_bus  = ohci->config_rom_bus;
1783                 }
1784                 ohci->config_rom      = ohci->next_config_rom;
1785                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1786                 ohci->next_config_rom = NULL;
1787
1788                 /*
1789                  * Restore config_rom image and manually update
1790                  * config_rom registers.  Writing the header quadlet
1791                  * will indicate that the config rom is ready, so we
1792                  * do that last.
1793                  */
1794                 reg_write(ohci, OHCI1394_BusOptions,
1795                           be32_to_cpu(ohci->config_rom[2]));
1796                 ohci->config_rom[0] = ohci->next_header;
1797                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1798                           be32_to_cpu(ohci->next_header));
1799         }
1800
1801 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1802         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1803         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1804 #endif
1805
1806         spin_unlock_irqrestore(&ohci->lock, flags);
1807
1808         if (free_rom)
1809                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1810                                   free_rom, free_rom_bus);
1811
1812         log_selfids(ohci->node_id, generation,
1813                     self_id_count, ohci->self_id_buffer);
1814
1815         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1816                                  self_id_count, ohci->self_id_buffer,
1817                                  ohci->csr_state_setclear_abdicate);
1818         ohci->csr_state_setclear_abdicate = false;
1819 }
1820
1821 static irqreturn_t irq_handler(int irq, void *data)
1822 {
1823         struct fw_ohci *ohci = data;
1824         u32 event, iso_event;
1825         int i;
1826
1827         event = reg_read(ohci, OHCI1394_IntEventClear);
1828
1829         if (!event || !~event)
1830                 return IRQ_NONE;
1831
1832         /*
1833          * busReset and postedWriteErr must not be cleared yet
1834          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1835          */
1836         reg_write(ohci, OHCI1394_IntEventClear,
1837                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1838         log_irqs(event);
1839
1840         if (event & OHCI1394_selfIDComplete)
1841                 tasklet_schedule(&ohci->bus_reset_tasklet);
1842
1843         if (event & OHCI1394_RQPkt)
1844                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1845
1846         if (event & OHCI1394_RSPkt)
1847                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1848
1849         if (event & OHCI1394_reqTxComplete)
1850                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1851
1852         if (event & OHCI1394_respTxComplete)
1853                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1854
1855         if (event & OHCI1394_isochRx) {
1856                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1857                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1858
1859                 while (iso_event) {
1860                         i = ffs(iso_event) - 1;
1861                         tasklet_schedule(
1862                                 &ohci->ir_context_list[i].context.tasklet);
1863                         iso_event &= ~(1 << i);
1864                 }
1865         }
1866
1867         if (event & OHCI1394_isochTx) {
1868                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1869                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1870
1871                 while (iso_event) {
1872                         i = ffs(iso_event) - 1;
1873                         tasklet_schedule(
1874                                 &ohci->it_context_list[i].context.tasklet);
1875                         iso_event &= ~(1 << i);
1876                 }
1877         }
1878
1879         if (unlikely(event & OHCI1394_regAccessFail))
1880                 fw_error("Register access failure - "
1881                          "please notify linux1394-devel@lists.sf.net\n");
1882
1883         if (unlikely(event & OHCI1394_postedWriteErr)) {
1884                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1885                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1886                 reg_write(ohci, OHCI1394_IntEventClear,
1887                           OHCI1394_postedWriteErr);
1888                 fw_error("PCI posted write error\n");
1889         }
1890
1891         if (unlikely(event & OHCI1394_cycleTooLong)) {
1892                 if (printk_ratelimit())
1893                         fw_notify("isochronous cycle too long\n");
1894                 reg_write(ohci, OHCI1394_LinkControlSet,
1895                           OHCI1394_LinkControl_cycleMaster);
1896         }
1897
1898         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1899                 /*
1900                  * We need to clear this event bit in order to make
1901                  * cycleMatch isochronous I/O work.  In theory we should
1902                  * stop active cycleMatch iso contexts now and restart
1903                  * them at least two cycles later.  (FIXME?)
1904                  */
1905                 if (printk_ratelimit())
1906                         fw_notify("isochronous cycle inconsistent\n");
1907         }
1908
1909         if (event & OHCI1394_cycle64Seconds) {
1910                 spin_lock(&ohci->lock);
1911                 update_bus_time(ohci);
1912                 spin_unlock(&ohci->lock);
1913         } else
1914                 flush_writes(ohci);
1915
1916         return IRQ_HANDLED;
1917 }
1918
1919 static int software_reset(struct fw_ohci *ohci)
1920 {
1921         int i;
1922
1923         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1924
1925         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1926                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1927                      OHCI1394_HCControl_softReset) == 0)
1928                         return 0;
1929                 msleep(1);
1930         }
1931
1932         return -EBUSY;
1933 }
1934
1935 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1936 {
1937         size_t size = length * 4;
1938
1939         memcpy(dest, src, size);
1940         if (size < CONFIG_ROM_SIZE)
1941                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1942 }
1943
1944 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1945 {
1946         bool enable_1394a;
1947         int ret, clear, set, offset;
1948
1949         /* Check if the driver should configure link and PHY. */
1950         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1951               OHCI1394_HCControl_programPhyEnable))
1952                 return 0;
1953
1954         /* Paranoia: check whether the PHY supports 1394a, too. */
1955         enable_1394a = false;
1956         ret = read_phy_reg(ohci, 2);
1957         if (ret < 0)
1958                 return ret;
1959         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1960                 ret = read_paged_phy_reg(ohci, 1, 8);
1961                 if (ret < 0)
1962                         return ret;
1963                 if (ret >= 1)
1964                         enable_1394a = true;
1965         }
1966
1967         if (ohci->quirks & QUIRK_NO_1394A)
1968                 enable_1394a = false;
1969
1970         /* Configure PHY and link consistently. */
1971         if (enable_1394a) {
1972                 clear = 0;
1973                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1974         } else {
1975                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1976                 set = 0;
1977         }
1978         ret = update_phy_reg(ohci, 5, clear, set);
1979         if (ret < 0)
1980                 return ret;
1981
1982         if (enable_1394a)
1983                 offset = OHCI1394_HCControlSet;
1984         else
1985                 offset = OHCI1394_HCControlClear;
1986         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1987
1988         /* Clean up: configuration has been taken care of. */
1989         reg_write(ohci, OHCI1394_HCControlClear,
1990                   OHCI1394_HCControl_programPhyEnable);
1991
1992         return 0;
1993 }
1994
1995 static int ohci_enable(struct fw_card *card,
1996                        const __be32 *config_rom, size_t length)
1997 {
1998         struct fw_ohci *ohci = fw_ohci(card);
1999         struct pci_dev *dev = to_pci_dev(card->device);
2000         u32 lps, seconds, version, irqs;
2001         int i, ret;
2002
2003         if (software_reset(ohci)) {
2004                 fw_error("Failed to reset ohci card.\n");
2005                 return -EBUSY;
2006         }
2007
2008         /*
2009          * Now enable LPS, which we need in order to start accessing
2010          * most of the registers.  In fact, on some cards (ALI M5251),
2011          * accessing registers in the SClk domain without LPS enabled
2012          * will lock up the machine.  Wait 50msec to make sure we have
2013          * full link enabled.  However, with some cards (well, at least
2014          * a JMicron PCIe card), we have to try again sometimes.
2015          */
2016         reg_write(ohci, OHCI1394_HCControlSet,
2017                   OHCI1394_HCControl_LPS |
2018                   OHCI1394_HCControl_postedWriteEnable);
2019         flush_writes(ohci);
2020
2021         for (lps = 0, i = 0; !lps && i < 3; i++) {
2022                 msleep(50);
2023                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2024                       OHCI1394_HCControl_LPS;
2025         }
2026
2027         if (!lps) {
2028                 fw_error("Failed to set Link Power Status\n");
2029                 return -EIO;
2030         }
2031
2032         reg_write(ohci, OHCI1394_HCControlClear,
2033                   OHCI1394_HCControl_noByteSwapData);
2034
2035         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2036         reg_write(ohci, OHCI1394_LinkControlSet,
2037                   OHCI1394_LinkControl_rcvSelfID |
2038                   OHCI1394_LinkControl_rcvPhyPkt |
2039                   OHCI1394_LinkControl_cycleTimerEnable |
2040                   OHCI1394_LinkControl_cycleMaster);
2041
2042         reg_write(ohci, OHCI1394_ATRetries,
2043                   OHCI1394_MAX_AT_REQ_RETRIES |
2044                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2045                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2046                   (200 << 16));
2047
2048         seconds = lower_32_bits(get_seconds());
2049         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2050         ohci->bus_time = seconds & ~0x3f;
2051
2052         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2053         if (version >= OHCI_VERSION_1_1) {
2054                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2055                           0xfffffffe);
2056                 card->broadcast_channel_auto_allocated = true;
2057         }
2058
2059         /* Get implemented bits of the priority arbitration request counter. */
2060         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2061         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2062         reg_write(ohci, OHCI1394_FairnessControl, 0);
2063         card->priority_budget_implemented = ohci->pri_req_max != 0;
2064
2065         ar_context_run(&ohci->ar_request_ctx);
2066         ar_context_run(&ohci->ar_response_ctx);
2067
2068         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2069         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2070         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2071
2072         ret = configure_1394a_enhancements(ohci);
2073         if (ret < 0)
2074                 return ret;
2075
2076         /* Activate link_on bit and contender bit in our self ID packets.*/
2077         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2078         if (ret < 0)
2079                 return ret;
2080
2081         /*
2082          * When the link is not yet enabled, the atomic config rom
2083          * update mechanism described below in ohci_set_config_rom()
2084          * is not active.  We have to update ConfigRomHeader and
2085          * BusOptions manually, and the write to ConfigROMmap takes
2086          * effect immediately.  We tie this to the enabling of the
2087          * link, so we have a valid config rom before enabling - the
2088          * OHCI requires that ConfigROMhdr and BusOptions have valid
2089          * values before enabling.
2090          *
2091          * However, when the ConfigROMmap is written, some controllers
2092          * always read back quadlets 0 and 2 from the config rom to
2093          * the ConfigRomHeader and BusOptions registers on bus reset.
2094          * They shouldn't do that in this initial case where the link
2095          * isn't enabled.  This means we have to use the same
2096          * workaround here, setting the bus header to 0 and then write
2097          * the right values in the bus reset tasklet.
2098          */
2099
2100         if (config_rom) {
2101                 ohci->next_config_rom =
2102                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2103                                            &ohci->next_config_rom_bus,
2104                                            GFP_KERNEL);
2105                 if (ohci->next_config_rom == NULL)
2106                         return -ENOMEM;
2107
2108                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2109         } else {
2110                 /*
2111                  * In the suspend case, config_rom is NULL, which
2112                  * means that we just reuse the old config rom.
2113                  */
2114                 ohci->next_config_rom = ohci->config_rom;
2115                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2116         }
2117
2118         ohci->next_header = ohci->next_config_rom[0];
2119         ohci->next_config_rom[0] = 0;
2120         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2121         reg_write(ohci, OHCI1394_BusOptions,
2122                   be32_to_cpu(ohci->next_config_rom[2]));
2123         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2124
2125         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2126
2127         if (!(ohci->quirks & QUIRK_NO_MSI))
2128                 pci_enable_msi(dev);
2129         if (request_irq(dev->irq, irq_handler,
2130                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2131                         ohci_driver_name, ohci)) {
2132                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2133                 pci_disable_msi(dev);
2134                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2135                                   ohci->config_rom, ohci->config_rom_bus);
2136                 return -EIO;
2137         }
2138
2139         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2140                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2141                 OHCI1394_isochTx | OHCI1394_isochRx |
2142                 OHCI1394_postedWriteErr |
2143                 OHCI1394_selfIDComplete |
2144                 OHCI1394_regAccessFail |
2145                 OHCI1394_cycle64Seconds |
2146                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2147                 OHCI1394_masterIntEnable;
2148         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2149                 irqs |= OHCI1394_busReset;
2150         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2151
2152         reg_write(ohci, OHCI1394_HCControlSet,
2153                   OHCI1394_HCControl_linkEnable |
2154                   OHCI1394_HCControl_BIBimageValid);
2155         flush_writes(ohci);
2156
2157         /* We are ready to go, reset bus to finish initialization. */
2158         fw_schedule_bus_reset(&ohci->card, false, true);
2159
2160         return 0;
2161 }
2162
2163 static int ohci_set_config_rom(struct fw_card *card,
2164                                const __be32 *config_rom, size_t length)
2165 {
2166         struct fw_ohci *ohci;
2167         unsigned long flags;
2168         __be32 *next_config_rom;
2169         dma_addr_t uninitialized_var(next_config_rom_bus);
2170
2171         ohci = fw_ohci(card);
2172
2173         /*
2174          * When the OHCI controller is enabled, the config rom update
2175          * mechanism is a bit tricky, but easy enough to use.  See
2176          * section 5.5.6 in the OHCI specification.
2177          *
2178          * The OHCI controller caches the new config rom address in a
2179          * shadow register (ConfigROMmapNext) and needs a bus reset
2180          * for the changes to take place.  When the bus reset is
2181          * detected, the controller loads the new values for the
2182          * ConfigRomHeader and BusOptions registers from the specified
2183          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2184          * shadow register. All automatically and atomically.
2185          *
2186          * Now, there's a twist to this story.  The automatic load of
2187          * ConfigRomHeader and BusOptions doesn't honor the
2188          * noByteSwapData bit, so with a be32 config rom, the
2189          * controller will load be32 values in to these registers
2190          * during the atomic update, even on litte endian
2191          * architectures.  The workaround we use is to put a 0 in the
2192          * header quadlet; 0 is endian agnostic and means that the
2193          * config rom isn't ready yet.  In the bus reset tasklet we
2194          * then set up the real values for the two registers.
2195          *
2196          * We use ohci->lock to avoid racing with the code that sets
2197          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2198          */
2199
2200         next_config_rom =
2201                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2202                                    &next_config_rom_bus, GFP_KERNEL);
2203         if (next_config_rom == NULL)
2204                 return -ENOMEM;
2205
2206         spin_lock_irqsave(&ohci->lock, flags);
2207
2208         /*
2209          * If there is not an already pending config_rom update,
2210          * push our new allocation into the ohci->next_config_rom
2211          * and then mark the local variable as null so that we
2212          * won't deallocate the new buffer.
2213          *
2214          * OTOH, if there is a pending config_rom update, just
2215          * use that buffer with the new config_rom data, and
2216          * let this routine free the unused DMA allocation.
2217          */
2218
2219         if (ohci->next_config_rom == NULL) {
2220                 ohci->next_config_rom = next_config_rom;
2221                 ohci->next_config_rom_bus = next_config_rom_bus;
2222                 next_config_rom = NULL;
2223         }
2224
2225         copy_config_rom(ohci->next_config_rom, config_rom, length);
2226
2227         ohci->next_header = config_rom[0];
2228         ohci->next_config_rom[0] = 0;
2229
2230         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2231
2232         spin_unlock_irqrestore(&ohci->lock, flags);
2233
2234         /* If we didn't use the DMA allocation, delete it. */
2235         if (next_config_rom != NULL)
2236                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2237                                   next_config_rom, next_config_rom_bus);
2238
2239         /*
2240          * Now initiate a bus reset to have the changes take
2241          * effect. We clean up the old config rom memory and DMA
2242          * mappings in the bus reset tasklet, since the OHCI
2243          * controller could need to access it before the bus reset
2244          * takes effect.
2245          */
2246
2247         fw_schedule_bus_reset(&ohci->card, true, true);
2248
2249         return 0;
2250 }
2251
2252 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2253 {
2254         struct fw_ohci *ohci = fw_ohci(card);
2255
2256         at_context_transmit(&ohci->at_request_ctx, packet);
2257 }
2258
2259 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2260 {
2261         struct fw_ohci *ohci = fw_ohci(card);
2262
2263         at_context_transmit(&ohci->at_response_ctx, packet);
2264 }
2265
2266 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2267 {
2268         struct fw_ohci *ohci = fw_ohci(card);
2269         struct context *ctx = &ohci->at_request_ctx;
2270         struct driver_data *driver_data = packet->driver_data;
2271         int ret = -ENOENT;
2272
2273         tasklet_disable(&ctx->tasklet);
2274
2275         if (packet->ack != 0)
2276                 goto out;
2277
2278         if (packet->payload_mapped)
2279                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2280                                  packet->payload_length, DMA_TO_DEVICE);
2281
2282         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2283         driver_data->packet = NULL;
2284         packet->ack = RCODE_CANCELLED;
2285         packet->callback(packet, &ohci->card, packet->ack);
2286         ret = 0;
2287  out:
2288         tasklet_enable(&ctx->tasklet);
2289
2290         return ret;
2291 }
2292
2293 static int ohci_enable_phys_dma(struct fw_card *card,
2294                                 int node_id, int generation)
2295 {
2296 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2297         return 0;
2298 #else
2299         struct fw_ohci *ohci = fw_ohci(card);
2300         unsigned long flags;
2301         int n, ret = 0;
2302
2303         /*
2304          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2305          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2306          */
2307
2308         spin_lock_irqsave(&ohci->lock, flags);
2309
2310         if (ohci->generation != generation) {
2311                 ret = -ESTALE;
2312                 goto out;
2313         }
2314
2315         /*
2316          * Note, if the node ID contains a non-local bus ID, physical DMA is
2317          * enabled for _all_ nodes on remote buses.
2318          */
2319
2320         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2321         if (n < 32)
2322                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2323         else
2324                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2325
2326         flush_writes(ohci);
2327  out:
2328         spin_unlock_irqrestore(&ohci->lock, flags);
2329
2330         return ret;
2331 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2332 }
2333
2334 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2335 {
2336         struct fw_ohci *ohci = fw_ohci(card);
2337         unsigned long flags;
2338         u32 value;
2339
2340         switch (csr_offset) {
2341         case CSR_STATE_CLEAR:
2342         case CSR_STATE_SET:
2343                 if (ohci->is_root &&
2344                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2345                      OHCI1394_LinkControl_cycleMaster))
2346                         value = CSR_STATE_BIT_CMSTR;
2347                 else
2348                         value = 0;
2349                 if (ohci->csr_state_setclear_abdicate)
2350                         value |= CSR_STATE_BIT_ABDICATE;
2351
2352                 return value;
2353
2354         case CSR_NODE_IDS:
2355                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2356
2357         case CSR_CYCLE_TIME:
2358                 return get_cycle_time(ohci);
2359
2360         case CSR_BUS_TIME:
2361                 /*
2362                  * We might be called just after the cycle timer has wrapped
2363                  * around but just before the cycle64Seconds handler, so we
2364                  * better check here, too, if the bus time needs to be updated.
2365                  */
2366                 spin_lock_irqsave(&ohci->lock, flags);
2367                 value = update_bus_time(ohci);
2368                 spin_unlock_irqrestore(&ohci->lock, flags);
2369                 return value;
2370
2371         case CSR_BUSY_TIMEOUT:
2372                 value = reg_read(ohci, OHCI1394_ATRetries);
2373                 return (value >> 4) & 0x0ffff00f;
2374
2375         case CSR_PRIORITY_BUDGET:
2376                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2377                         (ohci->pri_req_max << 8);
2378
2379         default:
2380                 WARN_ON(1);
2381                 return 0;
2382         }
2383 }
2384
2385 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2386 {
2387         struct fw_ohci *ohci = fw_ohci(card);
2388         unsigned long flags;
2389
2390         switch (csr_offset) {
2391         case CSR_STATE_CLEAR:
2392                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2393                         reg_write(ohci, OHCI1394_LinkControlClear,
2394                                   OHCI1394_LinkControl_cycleMaster);
2395                         flush_writes(ohci);
2396                 }
2397                 if (value & CSR_STATE_BIT_ABDICATE)
2398                         ohci->csr_state_setclear_abdicate = false;
2399                 break;
2400
2401         case CSR_STATE_SET:
2402                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2403                         reg_write(ohci, OHCI1394_LinkControlSet,
2404                                   OHCI1394_LinkControl_cycleMaster);
2405                         flush_writes(ohci);
2406                 }
2407                 if (value & CSR_STATE_BIT_ABDICATE)
2408                         ohci->csr_state_setclear_abdicate = true;
2409                 break;
2410
2411         case CSR_NODE_IDS:
2412                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2413                 flush_writes(ohci);
2414                 break;
2415
2416         case CSR_CYCLE_TIME:
2417                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2418                 reg_write(ohci, OHCI1394_IntEventSet,
2419                           OHCI1394_cycleInconsistent);
2420                 flush_writes(ohci);
2421                 break;
2422
2423         case CSR_BUS_TIME:
2424                 spin_lock_irqsave(&ohci->lock, flags);
2425                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2426                 spin_unlock_irqrestore(&ohci->lock, flags);
2427                 break;
2428
2429         case CSR_BUSY_TIMEOUT:
2430                 value = (value & 0xf) | ((value & 0xf) << 4) |
2431                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2432                 reg_write(ohci, OHCI1394_ATRetries, value);
2433                 flush_writes(ohci);
2434                 break;
2435
2436         case CSR_PRIORITY_BUDGET:
2437                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2438                 flush_writes(ohci);
2439                 break;
2440
2441         default:
2442                 WARN_ON(1);
2443                 break;
2444         }
2445 }
2446
2447 static void copy_iso_headers(struct iso_context *ctx, void *p)
2448 {
2449         int i = ctx->header_length;
2450
2451         if (i + ctx->base.header_size > PAGE_SIZE)
2452                 return;
2453
2454         /*
2455          * The iso header is byteswapped to little endian by
2456          * the controller, but the remaining header quadlets
2457          * are big endian.  We want to present all the headers
2458          * as big endian, so we have to swap the first quadlet.
2459          */
2460         if (ctx->base.header_size > 0)
2461                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2462         if (ctx->base.header_size > 4)
2463                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2464         if (ctx->base.header_size > 8)
2465                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2466         ctx->header_length += ctx->base.header_size;
2467 }
2468
2469 static int handle_ir_packet_per_buffer(struct context *context,
2470                                        struct descriptor *d,
2471                                        struct descriptor *last)
2472 {
2473         struct iso_context *ctx =
2474                 container_of(context, struct iso_context, context);
2475         struct descriptor *pd;
2476         __le32 *ir_header;
2477         void *p;
2478
2479         for (pd = d; pd <= last; pd++)
2480                 if (pd->transfer_status)
2481                         break;
2482         if (pd > last)
2483                 /* Descriptor(s) not done yet, stop iteration */
2484                 return 0;
2485
2486         p = last + 1;
2487         copy_iso_headers(ctx, p);
2488
2489         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2490                 ir_header = (__le32 *) p;
2491                 ctx->base.callback.sc(&ctx->base,
2492                                       le32_to_cpu(ir_header[0]) & 0xffff,
2493                                       ctx->header_length, ctx->header,
2494                                       ctx->base.callback_data);
2495                 ctx->header_length = 0;
2496         }
2497
2498         return 1;
2499 }
2500
2501 /* d == last because each descriptor block is only a single descriptor. */
2502 static int handle_ir_buffer_fill(struct context *context,
2503                                  struct descriptor *d,
2504                                  struct descriptor *last)
2505 {
2506         struct iso_context *ctx =
2507                 container_of(context, struct iso_context, context);
2508
2509         if (!last->transfer_status)
2510                 /* Descriptor(s) not done yet, stop iteration */
2511                 return 0;
2512
2513         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2514                 ctx->base.callback.mc(&ctx->base,
2515                                       le32_to_cpu(last->data_address) +
2516                                       le16_to_cpu(last->req_count) -
2517                                       le16_to_cpu(last->res_count),
2518                                       ctx->base.callback_data);
2519
2520         return 1;
2521 }
2522
2523 static int handle_it_packet(struct context *context,
2524                             struct descriptor *d,
2525                             struct descriptor *last)
2526 {
2527         struct iso_context *ctx =
2528                 container_of(context, struct iso_context, context);
2529         int i;
2530         struct descriptor *pd;
2531
2532         for (pd = d; pd <= last; pd++)
2533                 if (pd->transfer_status)
2534                         break;
2535         if (pd > last)
2536                 /* Descriptor(s) not done yet, stop iteration */
2537                 return 0;
2538
2539         i = ctx->header_length;
2540         if (i + 4 < PAGE_SIZE) {
2541                 /* Present this value as big-endian to match the receive code */
2542                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2543                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2544                                 le16_to_cpu(pd->res_count));
2545                 ctx->header_length += 4;
2546         }
2547         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2548                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2549                                       ctx->header_length, ctx->header,
2550                                       ctx->base.callback_data);
2551                 ctx->header_length = 0;
2552         }
2553         return 1;
2554 }
2555
2556 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2557 {
2558         u32 hi = channels >> 32, lo = channels;
2559
2560         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2561         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2562         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2563         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2564         mmiowb();
2565         ohci->mc_channels = channels;
2566 }
2567
2568 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2569                                 int type, int channel, size_t header_size)
2570 {
2571         struct fw_ohci *ohci = fw_ohci(card);
2572         struct iso_context *uninitialized_var(ctx);
2573         descriptor_callback_t uninitialized_var(callback);
2574         u64 *uninitialized_var(channels);
2575         u32 *uninitialized_var(mask), uninitialized_var(regs);
2576         unsigned long flags;
2577         int index, ret = -EBUSY;
2578
2579         spin_lock_irqsave(&ohci->lock, flags);
2580
2581         switch (type) {
2582         case FW_ISO_CONTEXT_TRANSMIT:
2583                 mask     = &ohci->it_context_mask;
2584                 callback = handle_it_packet;
2585                 index    = ffs(*mask) - 1;
2586                 if (index >= 0) {
2587                         *mask &= ~(1 << index);
2588                         regs = OHCI1394_IsoXmitContextBase(index);
2589                         ctx  = &ohci->it_context_list[index];
2590                 }
2591                 break;
2592
2593         case FW_ISO_CONTEXT_RECEIVE:
2594                 channels = &ohci->ir_context_channels;
2595                 mask     = &ohci->ir_context_mask;
2596                 callback = handle_ir_packet_per_buffer;
2597                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2598                 if (index >= 0) {
2599                         *channels &= ~(1ULL << channel);
2600                         *mask     &= ~(1 << index);
2601                         regs = OHCI1394_IsoRcvContextBase(index);
2602                         ctx  = &ohci->ir_context_list[index];
2603                 }
2604                 break;
2605
2606         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2607                 mask     = &ohci->ir_context_mask;
2608                 callback = handle_ir_buffer_fill;
2609                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2610                 if (index >= 0) {
2611                         ohci->mc_allocated = true;
2612                         *mask &= ~(1 << index);
2613                         regs = OHCI1394_IsoRcvContextBase(index);
2614                         ctx  = &ohci->ir_context_list[index];
2615                 }
2616                 break;
2617
2618         default:
2619                 index = -1;
2620                 ret = -ENOSYS;
2621         }
2622
2623         spin_unlock_irqrestore(&ohci->lock, flags);
2624
2625         if (index < 0)
2626                 return ERR_PTR(ret);
2627
2628         memset(ctx, 0, sizeof(*ctx));
2629         ctx->header_length = 0;
2630         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2631         if (ctx->header == NULL) {
2632                 ret = -ENOMEM;
2633                 goto out;
2634         }
2635         ret = context_init(&ctx->context, ohci, regs, callback);
2636         if (ret < 0)
2637                 goto out_with_header;
2638
2639         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2640                 set_multichannel_mask(ohci, 0);
2641
2642         return &ctx->base;
2643
2644  out_with_header:
2645         free_page((unsigned long)ctx->header);
2646  out:
2647         spin_lock_irqsave(&ohci->lock, flags);
2648
2649         switch (type) {
2650         case FW_ISO_CONTEXT_RECEIVE:
2651                 *channels |= 1ULL << channel;
2652                 break;
2653
2654         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2655                 ohci->mc_allocated = false;
2656                 break;
2657         }
2658         *mask |= 1 << index;
2659
2660         spin_unlock_irqrestore(&ohci->lock, flags);
2661
2662         return ERR_PTR(ret);
2663 }
2664
2665 static int ohci_start_iso(struct fw_iso_context *base,
2666                           s32 cycle, u32 sync, u32 tags)
2667 {
2668         struct iso_context *ctx = container_of(base, struct iso_context, base);
2669         struct fw_ohci *ohci = ctx->context.ohci;
2670         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2671         int index;
2672
2673         switch (ctx->base.type) {
2674         case FW_ISO_CONTEXT_TRANSMIT:
2675                 index = ctx - ohci->it_context_list;
2676                 match = 0;
2677                 if (cycle >= 0)
2678                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2679                                 (cycle & 0x7fff) << 16;
2680
2681                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2682                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2683                 context_run(&ctx->context, match);
2684                 break;
2685
2686         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2687                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2688                 /* fall through */
2689         case FW_ISO_CONTEXT_RECEIVE:
2690                 index = ctx - ohci->ir_context_list;
2691                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2692                 if (cycle >= 0) {
2693                         match |= (cycle & 0x07fff) << 12;
2694                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2695                 }
2696
2697                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2698                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2699                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2700                 context_run(&ctx->context, control);
2701
2702                 ctx->sync = sync;
2703                 ctx->tags = tags;
2704
2705                 break;
2706         }
2707
2708         return 0;
2709 }
2710
2711 static int ohci_stop_iso(struct fw_iso_context *base)
2712 {
2713         struct fw_ohci *ohci = fw_ohci(base->card);
2714         struct iso_context *ctx = container_of(base, struct iso_context, base);
2715         int index;
2716
2717         switch (ctx->base.type) {
2718         case FW_ISO_CONTEXT_TRANSMIT:
2719                 index = ctx - ohci->it_context_list;
2720                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2721                 break;
2722
2723         case FW_ISO_CONTEXT_RECEIVE:
2724         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2725                 index = ctx - ohci->ir_context_list;
2726                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2727                 break;
2728         }
2729         flush_writes(ohci);
2730         context_stop(&ctx->context);
2731
2732         return 0;
2733 }
2734
2735 static void ohci_free_iso_context(struct fw_iso_context *base)
2736 {
2737         struct fw_ohci *ohci = fw_ohci(base->card);
2738         struct iso_context *ctx = container_of(base, struct iso_context, base);
2739         unsigned long flags;
2740         int index;
2741
2742         ohci_stop_iso(base);
2743         context_release(&ctx->context);
2744         free_page((unsigned long)ctx->header);
2745
2746         spin_lock_irqsave(&ohci->lock, flags);
2747
2748         switch (base->type) {
2749         case FW_ISO_CONTEXT_TRANSMIT:
2750                 index = ctx - ohci->it_context_list;
2751                 ohci->it_context_mask |= 1 << index;
2752                 break;
2753
2754         case FW_ISO_CONTEXT_RECEIVE:
2755                 index = ctx - ohci->ir_context_list;
2756                 ohci->ir_context_mask |= 1 << index;
2757                 ohci->ir_context_channels |= 1ULL << base->channel;
2758                 break;
2759
2760         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2761                 index = ctx - ohci->ir_context_list;
2762                 ohci->ir_context_mask |= 1 << index;
2763                 ohci->ir_context_channels |= ohci->mc_channels;
2764                 ohci->mc_channels = 0;
2765                 ohci->mc_allocated = false;
2766                 break;
2767         }
2768
2769         spin_unlock_irqrestore(&ohci->lock, flags);
2770 }
2771
2772 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2773 {
2774         struct fw_ohci *ohci = fw_ohci(base->card);
2775         unsigned long flags;
2776         int ret;
2777
2778         switch (base->type) {
2779         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2780
2781                 spin_lock_irqsave(&ohci->lock, flags);
2782
2783                 /* Don't allow multichannel to grab other contexts' channels. */
2784                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2785                         *channels = ohci->ir_context_channels;
2786                         ret = -EBUSY;
2787                 } else {
2788                         set_multichannel_mask(ohci, *channels);
2789                         ret = 0;
2790                 }
2791
2792                 spin_unlock_irqrestore(&ohci->lock, flags);
2793
2794                 break;
2795         default:
2796                 ret = -EINVAL;
2797         }
2798
2799         return ret;
2800 }
2801
2802 #ifdef CONFIG_PM
2803 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2804 {
2805         int i;
2806         struct iso_context *ctx;
2807
2808         for (i = 0 ; i < ohci->n_ir ; i++) {
2809                 ctx = &ohci->ir_context_list[i];
2810                 if (ctx->context.running)
2811                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2812         }
2813
2814         for (i = 0 ; i < ohci->n_it ; i++) {
2815                 ctx = &ohci->it_context_list[i];
2816                 if (ctx->context.running)
2817                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2818         }
2819 }
2820 #endif
2821
2822 static int queue_iso_transmit(struct iso_context *ctx,
2823                               struct fw_iso_packet *packet,
2824                               struct fw_iso_buffer *buffer,
2825                               unsigned long payload)
2826 {
2827         struct descriptor *d, *last, *pd;
2828         struct fw_iso_packet *p;
2829         __le32 *header;
2830         dma_addr_t d_bus, page_bus;
2831         u32 z, header_z, payload_z, irq;
2832         u32 payload_index, payload_end_index, next_page_index;
2833         int page, end_page, i, length, offset;
2834
2835         p = packet;
2836         payload_index = payload;
2837
2838         if (p->skip)
2839                 z = 1;
2840         else
2841                 z = 2;
2842         if (p->header_length > 0)
2843                 z++;
2844
2845         /* Determine the first page the payload isn't contained in. */
2846         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2847         if (p->payload_length > 0)
2848                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2849         else
2850                 payload_z = 0;
2851
2852         z += payload_z;
2853
2854         /* Get header size in number of descriptors. */
2855         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2856
2857         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2858         if (d == NULL)
2859                 return -ENOMEM;
2860
2861         if (!p->skip) {
2862                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2863                 d[0].req_count = cpu_to_le16(8);
2864                 /*
2865                  * Link the skip address to this descriptor itself.  This causes
2866                  * a context to skip a cycle whenever lost cycles or FIFO
2867                  * overruns occur, without dropping the data.  The application
2868                  * should then decide whether this is an error condition or not.
2869                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2870                  */
2871                 d[0].branch_address = cpu_to_le32(d_bus | z);
2872
2873                 header = (__le32 *) &d[1];
2874                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2875                                         IT_HEADER_TAG(p->tag) |
2876                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2877                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2878                                         IT_HEADER_SPEED(ctx->base.speed));
2879                 header[1] =
2880                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2881                                                           p->payload_length));
2882         }
2883
2884         if (p->header_length > 0) {
2885                 d[2].req_count    = cpu_to_le16(p->header_length);
2886                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2887                 memcpy(&d[z], p->header, p->header_length);
2888         }
2889
2890         pd = d + z - payload_z;
2891         payload_end_index = payload_index + p->payload_length;
2892         for (i = 0; i < payload_z; i++) {
2893                 page               = payload_index >> PAGE_SHIFT;
2894                 offset             = payload_index & ~PAGE_MASK;
2895                 next_page_index    = (page + 1) << PAGE_SHIFT;
2896                 length             =
2897                         min(next_page_index, payload_end_index) - payload_index;
2898                 pd[i].req_count    = cpu_to_le16(length);
2899
2900                 page_bus = page_private(buffer->pages[page]);
2901                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2902
2903                 payload_index += length;
2904         }
2905
2906         if (p->interrupt)
2907                 irq = DESCRIPTOR_IRQ_ALWAYS;
2908         else
2909                 irq = DESCRIPTOR_NO_IRQ;
2910
2911         last = z == 2 ? d : d + z - 1;
2912         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2913                                      DESCRIPTOR_STATUS |
2914                                      DESCRIPTOR_BRANCH_ALWAYS |
2915                                      irq);
2916
2917         context_append(&ctx->context, d, z, header_z);
2918
2919         return 0;
2920 }
2921
2922 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2923                                        struct fw_iso_packet *packet,
2924                                        struct fw_iso_buffer *buffer,
2925                                        unsigned long payload)
2926 {
2927         struct descriptor *d, *pd;
2928         dma_addr_t d_bus, page_bus;
2929         u32 z, header_z, rest;
2930         int i, j, length;
2931         int page, offset, packet_count, header_size, payload_per_buffer;
2932
2933         /*
2934          * The OHCI controller puts the isochronous header and trailer in the
2935          * buffer, so we need at least 8 bytes.
2936          */
2937         packet_count = packet->header_length / ctx->base.header_size;
2938         header_size  = max(ctx->base.header_size, (size_t)8);
2939
2940         /* Get header size in number of descriptors. */
2941         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2942         page     = payload >> PAGE_SHIFT;
2943         offset   = payload & ~PAGE_MASK;
2944         payload_per_buffer = packet->payload_length / packet_count;
2945
2946         for (i = 0; i < packet_count; i++) {
2947                 /* d points to the header descriptor */
2948                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2949                 d = context_get_descriptors(&ctx->context,
2950                                 z + header_z, &d_bus);
2951                 if (d == NULL)
2952                         return -ENOMEM;
2953
2954                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2955                                               DESCRIPTOR_INPUT_MORE);
2956                 if (packet->skip && i == 0)
2957                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2958                 d->req_count    = cpu_to_le16(header_size);
2959                 d->res_count    = d->req_count;
2960                 d->transfer_status = 0;
2961                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2962
2963                 rest = payload_per_buffer;
2964                 pd = d;
2965                 for (j = 1; j < z; j++) {
2966                         pd++;
2967                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2968                                                   DESCRIPTOR_INPUT_MORE);
2969
2970                         if (offset + rest < PAGE_SIZE)
2971                                 length = rest;
2972                         else
2973                                 length = PAGE_SIZE - offset;
2974                         pd->req_count = cpu_to_le16(length);
2975                         pd->res_count = pd->req_count;
2976                         pd->transfer_status = 0;
2977
2978                         page_bus = page_private(buffer->pages[page]);
2979                         pd->data_address = cpu_to_le32(page_bus + offset);
2980
2981                         offset = (offset + length) & ~PAGE_MASK;
2982                         rest -= length;
2983                         if (offset == 0)
2984                                 page++;
2985                 }
2986                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2987                                           DESCRIPTOR_INPUT_LAST |
2988                                           DESCRIPTOR_BRANCH_ALWAYS);
2989                 if (packet->interrupt && i == packet_count - 1)
2990                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2991
2992                 context_append(&ctx->context, d, z, header_z);
2993         }
2994
2995         return 0;
2996 }
2997
2998 static int queue_iso_buffer_fill(struct iso_context *ctx,
2999                                  struct fw_iso_packet *packet,
3000                                  struct fw_iso_buffer *buffer,
3001                                  unsigned long payload)
3002 {
3003         struct descriptor *d;
3004         dma_addr_t d_bus, page_bus;
3005         int page, offset, rest, z, i, length;
3006
3007         page   = payload >> PAGE_SHIFT;
3008         offset = payload & ~PAGE_MASK;
3009         rest   = packet->payload_length;
3010
3011         /* We need one descriptor for each page in the buffer. */
3012         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3013
3014         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3015                 return -EFAULT;
3016
3017         for (i = 0; i < z; i++) {
3018                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3019                 if (d == NULL)
3020                         return -ENOMEM;
3021
3022                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3023                                          DESCRIPTOR_BRANCH_ALWAYS);
3024                 if (packet->skip && i == 0)
3025                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3026                 if (packet->interrupt && i == z - 1)
3027                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3028
3029                 if (offset + rest < PAGE_SIZE)
3030                         length = rest;
3031                 else
3032                         length = PAGE_SIZE - offset;
3033                 d->req_count = cpu_to_le16(length);
3034                 d->res_count = d->req_count;
3035                 d->transfer_status = 0;
3036
3037                 page_bus = page_private(buffer->pages[page]);
3038                 d->data_address = cpu_to_le32(page_bus + offset);
3039
3040                 rest -= length;
3041                 offset = 0;
3042                 page++;
3043
3044                 context_append(&ctx->context, d, 1, 0);
3045         }
3046
3047         return 0;
3048 }
3049
3050 static int ohci_queue_iso(struct fw_iso_context *base,
3051                           struct fw_iso_packet *packet,
3052                           struct fw_iso_buffer *buffer,
3053                           unsigned long payload)
3054 {
3055         struct iso_context *ctx = container_of(base, struct iso_context, base);
3056         unsigned long flags;
3057         int ret = -ENOSYS;
3058
3059         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3060         switch (base->type) {
3061         case FW_ISO_CONTEXT_TRANSMIT:
3062                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3063                 break;
3064         case FW_ISO_CONTEXT_RECEIVE:
3065                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3066                 break;
3067         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3068                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3069                 break;
3070         }
3071         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3072
3073         return ret;
3074 }
3075
3076 static const struct fw_card_driver ohci_driver = {
3077         .enable                 = ohci_enable,
3078         .read_phy_reg           = ohci_read_phy_reg,
3079         .update_phy_reg         = ohci_update_phy_reg,
3080         .set_config_rom         = ohci_set_config_rom,
3081         .send_request           = ohci_send_request,
3082         .send_response          = ohci_send_response,
3083         .cancel_packet          = ohci_cancel_packet,
3084         .enable_phys_dma        = ohci_enable_phys_dma,
3085         .read_csr               = ohci_read_csr,
3086         .write_csr              = ohci_write_csr,
3087
3088         .allocate_iso_context   = ohci_allocate_iso_context,
3089         .free_iso_context       = ohci_free_iso_context,
3090         .set_iso_channels       = ohci_set_iso_channels,
3091         .queue_iso              = ohci_queue_iso,
3092         .start_iso              = ohci_start_iso,
3093         .stop_iso               = ohci_stop_iso,
3094 };
3095
3096 #ifdef CONFIG_PPC_PMAC
3097 static void pmac_ohci_on(struct pci_dev *dev)
3098 {
3099         if (machine_is(powermac)) {
3100                 struct device_node *ofn = pci_device_to_OF_node(dev);
3101
3102                 if (ofn) {
3103                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3104                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3105                 }
3106         }
3107 }
3108
3109 static void pmac_ohci_off(struct pci_dev *dev)
3110 {
3111         if (machine_is(powermac)) {
3112                 struct device_node *ofn = pci_device_to_OF_node(dev);
3113
3114                 if (ofn) {
3115                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3116                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3117                 }
3118         }
3119 }
3120 #else
3121 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3122 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3123 #endif /* CONFIG_PPC_PMAC */
3124
3125 static int __devinit pci_probe(struct pci_dev *dev,
3126                                const struct pci_device_id *ent)
3127 {
3128         struct fw_ohci *ohci;
3129         u32 bus_options, max_receive, link_speed, version;
3130         u64 guid;
3131         int i, err;
3132         size_t size;
3133
3134         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3135         if (ohci == NULL) {
3136                 err = -ENOMEM;
3137                 goto fail;
3138         }
3139
3140         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3141
3142         pmac_ohci_on(dev);
3143
3144         err = pci_enable_device(dev);
3145         if (err) {
3146                 fw_error("Failed to enable OHCI hardware\n");
3147                 goto fail_free;
3148         }
3149
3150         pci_set_master(dev);
3151         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3152         pci_set_drvdata(dev, ohci);
3153
3154         spin_lock_init(&ohci->lock);
3155         mutex_init(&ohci->phy_reg_mutex);
3156
3157         tasklet_init(&ohci->bus_reset_tasklet,
3158                      bus_reset_tasklet, (unsigned long)ohci);
3159
3160         err = pci_request_region(dev, 0, ohci_driver_name);
3161         if (err) {
3162                 fw_error("MMIO resource unavailable\n");
3163                 goto fail_disable;
3164         }
3165
3166         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3167         if (ohci->registers == NULL) {
3168                 fw_error("Failed to remap registers\n");
3169                 err = -ENXIO;
3170                 goto fail_iomem;
3171         }
3172
3173         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3174                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3175                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3176                      ohci_quirks[i].device == dev->device) &&
3177                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3178                      ohci_quirks[i].revision >= dev->revision)) {
3179                         ohci->quirks = ohci_quirks[i].flags;
3180                         break;
3181                 }
3182         if (param_quirks)
3183                 ohci->quirks = param_quirks;
3184
3185         /*
3186          * Because dma_alloc_coherent() allocates at least one page,
3187          * we save space by using a common buffer for the AR request/
3188          * response descriptors and the self IDs buffer.
3189          */
3190         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3191         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3192         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3193                                                PAGE_SIZE,
3194                                                &ohci->misc_buffer_bus,
3195                                                GFP_KERNEL);
3196         if (!ohci->misc_buffer) {
3197                 err = -ENOMEM;
3198                 goto fail_iounmap;
3199         }
3200
3201         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3202                               OHCI1394_AsReqRcvContextControlSet);
3203         if (err < 0)
3204                 goto fail_misc_buf;
3205
3206         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3207                               OHCI1394_AsRspRcvContextControlSet);
3208         if (err < 0)
3209                 goto fail_arreq_ctx;
3210
3211         err = context_init(&ohci->at_request_ctx, ohci,
3212                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3213         if (err < 0)
3214                 goto fail_arrsp_ctx;
3215
3216         err = context_init(&ohci->at_response_ctx, ohci,
3217                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3218         if (err < 0)
3219                 goto fail_atreq_ctx;
3220
3221         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3222         ohci->ir_context_channels = ~0ULL;
3223         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3224         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3225         ohci->n_ir = hweight32(ohci->ir_context_mask);
3226         size = sizeof(struct iso_context) * ohci->n_ir;
3227         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3228
3229         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3230         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3231         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3232         ohci->n_it = hweight32(ohci->it_context_mask);
3233         size = sizeof(struct iso_context) * ohci->n_it;
3234         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3235
3236         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3237                 err = -ENOMEM;
3238                 goto fail_contexts;
3239         }
3240
3241         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3242         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3243
3244         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3245         max_receive = (bus_options >> 12) & 0xf;
3246         link_speed = bus_options & 0x7;
3247         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3248                 reg_read(ohci, OHCI1394_GUIDLo);
3249
3250         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3251         if (err)
3252                 goto fail_contexts;
3253
3254         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3255         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3256                   "%d IR + %d IT contexts, quirks 0x%x\n",
3257                   dev_name(&dev->dev), version >> 16, version & 0xff,
3258                   ohci->n_ir, ohci->n_it, ohci->quirks);
3259
3260         return 0;
3261
3262  fail_contexts:
3263         kfree(ohci->ir_context_list);
3264         kfree(ohci->it_context_list);
3265         context_release(&ohci->at_response_ctx);
3266  fail_atreq_ctx:
3267         context_release(&ohci->at_request_ctx);
3268  fail_arrsp_ctx:
3269         ar_context_release(&ohci->ar_response_ctx);
3270  fail_arreq_ctx:
3271         ar_context_release(&ohci->ar_request_ctx);
3272  fail_misc_buf:
3273         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3274                           ohci->misc_buffer, ohci->misc_buffer_bus);
3275  fail_iounmap:
3276         pci_iounmap(dev, ohci->registers);
3277  fail_iomem:
3278         pci_release_region(dev, 0);
3279  fail_disable:
3280         pci_disable_device(dev);
3281  fail_free:
3282         kfree(&ohci->card);
3283         pmac_ohci_off(dev);
3284  fail:
3285         if (err == -ENOMEM)
3286                 fw_error("Out of memory\n");
3287
3288         return err;
3289 }
3290
3291 static void pci_remove(struct pci_dev *dev)
3292 {
3293         struct fw_ohci *ohci;
3294
3295         ohci = pci_get_drvdata(dev);
3296         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3297         flush_writes(ohci);
3298         fw_core_remove_card(&ohci->card);
3299
3300         /*
3301          * FIXME: Fail all pending packets here, now that the upper
3302          * layers can't queue any more.
3303          */
3304
3305         software_reset(ohci);
3306         free_irq(dev->irq, ohci);
3307
3308         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3309                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3310                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3311         if (ohci->config_rom)
3312                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3313                                   ohci->config_rom, ohci->config_rom_bus);
3314         ar_context_release(&ohci->ar_request_ctx);
3315         ar_context_release(&ohci->ar_response_ctx);
3316         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3317                           ohci->misc_buffer, ohci->misc_buffer_bus);
3318         context_release(&ohci->at_request_ctx);
3319         context_release(&ohci->at_response_ctx);
3320         kfree(ohci->it_context_list);
3321         kfree(ohci->ir_context_list);
3322         pci_disable_msi(dev);
3323         pci_iounmap(dev, ohci->registers);
3324         pci_release_region(dev, 0);
3325         pci_disable_device(dev);
3326         kfree(&ohci->card);
3327         pmac_ohci_off(dev);
3328
3329         fw_notify("Removed fw-ohci device.\n");
3330 }
3331
3332 #ifdef CONFIG_PM
3333 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3334 {
3335         struct fw_ohci *ohci = pci_get_drvdata(dev);
3336         int err;
3337
3338         software_reset(ohci);
3339         free_irq(dev->irq, ohci);
3340         pci_disable_msi(dev);
3341         err = pci_save_state(dev);
3342         if (err) {
3343                 fw_error("pci_save_state failed\n");
3344                 return err;
3345         }
3346         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3347         if (err)
3348                 fw_error("pci_set_power_state failed with %d\n", err);
3349         pmac_ohci_off(dev);
3350
3351         return 0;
3352 }
3353
3354 static int pci_resume(struct pci_dev *dev)
3355 {
3356         struct fw_ohci *ohci = pci_get_drvdata(dev);
3357         int err;
3358
3359         pmac_ohci_on(dev);
3360         pci_set_power_state(dev, PCI_D0);
3361         pci_restore_state(dev);
3362         err = pci_enable_device(dev);
3363         if (err) {
3364                 fw_error("pci_enable_device failed\n");
3365                 return err;
3366         }
3367
3368         /* Some systems don't setup GUID register on resume from ram  */
3369         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3370                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3371                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3372                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3373         }
3374
3375         err = ohci_enable(&ohci->card, NULL, 0);
3376         if (err)
3377                 return err;
3378
3379         ohci_resume_iso_dma(ohci);
3380
3381         return 0;
3382 }
3383 #endif
3384
3385 static const struct pci_device_id pci_table[] = {
3386         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3387         { }
3388 };
3389
3390 MODULE_DEVICE_TABLE(pci, pci_table);
3391
3392 static struct pci_driver fw_ohci_pci_driver = {
3393         .name           = ohci_driver_name,
3394         .id_table       = pci_table,
3395         .probe          = pci_probe,
3396         .remove         = pci_remove,
3397 #ifdef CONFIG_PM
3398         .resume         = pci_resume,
3399         .suspend        = pci_suspend,
3400 #endif
3401 };
3402
3403 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3404 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3405 MODULE_LICENSE("GPL");
3406
3407 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3408 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3409 MODULE_ALIAS("ohci1394");
3410 #endif
3411
3412 static int __init fw_ohci_init(void)
3413 {
3414         return pci_register_driver(&fw_ohci_pci_driver);
3415 }
3416
3417 static void __exit fw_ohci_cleanup(void)
3418 {
3419         pci_unregister_driver(&fw_ohci_pci_driver);
3420 }
3421
3422 module_init(fw_ohci_init);
3423 module_exit(fw_ohci_cleanup);