arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/thread_info.h>
   8 #include <linux/module.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/pgtable.h>
  12 #include <asm/msr.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/ds.h>
  15 #include <asm/bugs.h>
  16
  17 #ifdef CONFIG_X86_64
  18 #include <asm/topology.h>
  19 #include <asm/numa_64.h>
  20 #endif
  21
  22 #include "cpu.h"
  23
  24 #ifdef CONFIG_X86_LOCAL_APIC
  25 #include <asm/mpspec.h>
  26 #include <asm/apic.h>
  27 #include <mach_apic.h>
  28 #endif
  29
  30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  31 {
  32         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  33                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  34                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  35
  36 #ifdef CONFIG_X86_64
  37         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  38 #else
  39         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  40         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  41                 c->x86_cache_alignment = 128;
  42 #endif
  43 }
  44
  45 #ifdef CONFIG_X86_32
  46 /*
  47  *      Early probe support logic for ppro memory erratum #50
  48  *
  49  *      This is called before we do cpu ident work
  50  */
  51
  52 int __cpuinit ppro_with_ram_bug(void)
  53 {
  54         /* Uses data from early_cpu_detect now */
  55         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  56             boot_cpu_data.x86 == 6 &&
  57             boot_cpu_data.x86_model == 1 &&
  58             boot_cpu_data.x86_mask < 8) {
  59                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  60                 return 1;
  61         }
  62         return 0;
  63 }
  64
  65 #ifdef CONFIG_X86_F00F_BUG
  66 static void __cpuinit trap_init_f00f_bug(void)
  67 {
  68         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
  69
  70         /*
  71          * Update the IDT descriptor and reload the IDT so that
  72          * it uses the read-only mapped virtual address.
  73          */
  74         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
  75         load_idt(&idt_descr);
  76 }
  77 #endif
  78
  79 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
  80 {
  81         unsigned long lo, hi;
  82
  83 #ifdef CONFIG_X86_F00F_BUG
  84         /*
  85          * All current models of Pentium and Pentium with MMX technology CPUs
  86          * have the F0 0F bug, which lets nonprivileged users lock up the system.
  87          * Note that the workaround only should be initialized once...
  88          */
  89         c->f00f_bug = 0;
  90         if (!paravirt_enabled() && c->x86 == 5) {
  91                 static int f00f_workaround_enabled;
  92
  93                 c->f00f_bug = 1;
  94                 if (!f00f_workaround_enabled) {
  95                         trap_init_f00f_bug();
  96                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
  97                         f00f_workaround_enabled = 1;
  98                 }
  99         }
 100 #endif
 101
 102         /*
 103          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 104          * model 3 mask 3
 105          */
 106         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 107                 clear_cpu_cap(c, X86_FEATURE_SEP);
 108
 109         /*
 110          * P4 Xeon errata 037 workaround.
 111          * Hardware prefetcher may cause stale data to be loaded into the cache.
 112          */
 113         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 114                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 115                 if ((lo & (1<<9)) == 0) {
 116                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 117                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 118                         lo |= (1<<9);   /* Disable hw prefetching */
 119                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 120                 }
 121         }
 122
 123         /*
 124          * See if we have a good local APIC by checking for buggy Pentia,
 125          * i.e. all B steppings and the C2 stepping of P54C when using their
 126          * integrated APIC (see 11AP erratum in "Pentium Processor
 127          * Specification Update").
 128          */
 129         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 130             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 131                 set_cpu_cap(c, X86_FEATURE_11AP);
 132
 133
 134 #ifdef CONFIG_X86_INTEL_USERCOPY
 135         /*
 136          * Set up the preferred alignment for movsl bulk memory moves
 137          */
 138         switch (c->x86) {
 139         case 4:         /* 486: untested */
 140                 break;
 141         case 5:         /* Old Pentia: untested */
 142                 break;
 143         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 144                 movsl_mask.mask = 7;
 145                 break;
 146         case 15:        /* P4 is OK down to 8-byte alignment */
 147                 movsl_mask.mask = 7;
 148                 break;
 149         }
 150 #endif
 151
 152 #ifdef CONFIG_X86_NUMAQ
 153         numaq_tsc_disable();
 154 #endif
 155 }
 156 #else
 157 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 158 {
 159 }
 160 #endif
 161
 162 static void __cpuinit srat_detect_node(void)
 163 {
 164 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 165         unsigned node;
 166         int cpu = smp_processor_id();
 167         int apicid = hard_smp_processor_id();
 168
 169         /* Don't do the funky fallback heuristics the AMD version employs
 170            for now. */
 171         node = apicid_to_node[apicid];
 172         if (node == NUMA_NO_NODE || !node_online(node))
 173                 node = first_node(node_online_map);
 174         numa_set_node(cpu, node);
 175
 176         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
 177 #endif
 178 }
 179
 180 /*
 181  * find out the number of processor cores on the die
 182  */
 183 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 184 {
 185         unsigned int eax, ebx, ecx, edx;
 186
 187         if (c->cpuid_level < 4)
 188                 return 1;
 189
 190         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 191         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 192         if (eax & 0x1f)
 193                 return ((eax >> 26) + 1);
 194         else
 195                 return 1;
 196 }
 197
 198 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 199 {
 200         /* Intel VMX MSR indicated features */
 201 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 202 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 203 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 204 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 205 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 206 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 207
 208         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 209
 210         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 211         clear_cpu_cap(c, X86_FEATURE_VNMI);
 212         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 213         clear_cpu_cap(c, X86_FEATURE_EPT);
 214         clear_cpu_cap(c, X86_FEATURE_VPID);
 215
 216         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 217         msr_ctl = vmx_msr_high | vmx_msr_low;
 218         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 219                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 220         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 221                 set_cpu_cap(c, X86_FEATURE_VNMI);
 222         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 223                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 224                       vmx_msr_low, vmx_msr_high);
 225                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 226                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 227                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 228                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 229                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 230                         set_cpu_cap(c, X86_FEATURE_EPT);
 231                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 232                         set_cpu_cap(c, X86_FEATURE_VPID);
 233         }
 234 }
 235
 236 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 237 {
 238         unsigned int l2 = 0;
 239
 240         early_init_intel(c);
 241
 242         intel_workarounds(c);
 243
 244         l2 = init_intel_cacheinfo(c);
 245         if (c->cpuid_level > 9) {
 246                 unsigned eax = cpuid_eax(10);
 247                 /* Check for version and the number of counters */
 248                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 249                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 250         }
 251
 252         if (cpu_has_xmm2)
 253                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 254         if (cpu_has_ds) {
 255                 unsigned int l1;
 256                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 257                 if (!(l1 & (1<<11)))
 258                         set_cpu_cap(c, X86_FEATURE_BTS);
 259                 if (!(l1 & (1<<12)))
 260                         set_cpu_cap(c, X86_FEATURE_PEBS);
 261                 ds_init_intel(c);
 262         }
 263
 264 #ifdef CONFIG_X86_64
 265         if (c->x86 == 15)
 266                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 267         if (c->x86 == 6)
 268                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 269 #else
 270         /*
 271          * Names for the Pentium II/Celeron processors
 272          * detectable only by also checking the cache size.
 273          * Dixon is NOT a Celeron.
 274          */
 275         if (c->x86 == 6) {
 276                 char *p = NULL;
 277
 278                 switch (c->x86_model) {
 279                 case 5:
 280                         if (c->x86_mask == 0) {
 281                                 if (l2 == 0)
 282                                         p = "Celeron (Covington)";
 283                                 else if (l2 == 256)
 284                                         p = "Mobile Pentium II (Dixon)";
 285                         }
 286                         break;
 287
 288                 case 6:
 289                         if (l2 == 128)
 290                                 p = "Celeron (Mendocino)";
 291                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 292                                 p = "Celeron-A";
 293                         break;
 294
 295                 case 8:
 296                         if (l2 == 128)
 297                                 p = "Celeron (Coppermine)";
 298                         break;
 299                 }
 300
 301                 if (p)
 302                         strcpy(c->x86_model_id, p);
 303         }
 304
 305         if (c->x86 == 15)
 306                 set_cpu_cap(c, X86_FEATURE_P4);
 307         if (c->x86 == 6)
 308                 set_cpu_cap(c, X86_FEATURE_P3);
 309 #endif
 310
 311         detect_extended_topology(c);
 312         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 313                 /*
 314                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 315                  * detection.
 316                  */
 317                 c->x86_max_cores = intel_num_cpu_cores(c);
 318 #ifdef CONFIG_X86_32
 319                 detect_ht(c);
 320 #endif
 321         }
 322
 323         /* Work around errata */
 324         srat_detect_node();
 325
 326         if (cpu_has(c, X86_FEATURE_VMX))
 327                 detect_vmx_virtcap(c);
 328 }
 329
 330 #ifdef CONFIG_X86_32
 331 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 332 {
 333         /*
 334          * Intel PIII Tualatin. This comes in two flavours.
 335          * One has 256kb of cache, the other 512. We have no way
 336          * to determine which, so we use a boottime override
 337          * for the 512kb model, and assume 256 otherwise.
 338          */
 339         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 340                 size = 256;
 341         return size;
 342 }
 343 #endif
 344
 345 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
 346         .c_vendor       = "Intel",
 347         .c_ident        = { "GenuineIntel" },
 348 #ifdef CONFIG_X86_32
 349         .c_models = {
 350                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 351                   {
 352                           [0] = "486 DX-25/33",
 353                           [1] = "486 DX-50",
 354                           [2] = "486 SX",
 355                           [3] = "486 DX/2",
 356                           [4] = "486 SL",
 357                           [5] = "486 SX/2",
 358                           [7] = "486 DX/2-WB",
 359                           [8] = "486 DX/4",
 360                           [9] = "486 DX/4-WB"
 361                   }
 362                 },
 363                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 364                   {
 365                           [0] = "Pentium 60/66 A-step",
 366                           [1] = "Pentium 60/66",
 367                           [2] = "Pentium 75 - 200",
 368                           [3] = "OverDrive PODP5V83",
 369                           [4] = "Pentium MMX",
 370                           [7] = "Mobile Pentium 75 - 200",
 371                           [8] = "Mobile Pentium MMX"
 372                   }
 373                 },
 374                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 375                   {
 376                           [0] = "Pentium Pro A-step",
 377                           [1] = "Pentium Pro",
 378                           [3] = "Pentium II (Klamath)",
 379                           [4] = "Pentium II (Deschutes)",
 380                           [5] = "Pentium II (Deschutes)",
 381                           [6] = "Mobile Pentium II",
 382                           [7] = "Pentium III (Katmai)",
 383                           [8] = "Pentium III (Coppermine)",
 384                           [10] = "Pentium III (Cascades)",
 385                           [11] = "Pentium III (Tualatin)",
 386                   }
 387                 },
 388                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 389                   {
 390                           [0] = "Pentium 4 (Unknown)",
 391                           [1] = "Pentium 4 (Willamette)",
 392                           [2] = "Pentium 4 (Northwood)",
 393                           [4] = "Pentium 4 (Foster)",
 394                           [5] = "Pentium 4 (Foster)",
 395                   }
 396                 },
 397         },
 398         .c_size_cache   = intel_size_cache,
 399 #endif
 400         .c_early_init   = early_init_intel,
 401         .c_init         = init_intel,
 402         .c_x86_vendor   = X86_VENDOR_INTEL,
 403 };
 404
 405 cpu_dev_register(intel_cpu_dev);
 406