drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static u32 i915_gem_get_seqno(struct drm_device *dev)
  38 {
  39         drm_i915_private_t *dev_priv = dev->dev_private;
  40         u32 seqno;
  41
  42         seqno = dev_priv->next_seqno;
  43
  44         /* reserve 0 for non-seqno */
  45         if (++dev_priv->next_seqno == 0)
  46                 dev_priv->next_seqno = 1;
  47
  48         return seqno;
  49 }
  50
  51 static int
  52 render_ring_flush(struct intel_ring_buffer *ring,
  53                   u32   invalidate_domains,
  54                   u32   flush_domains)
  55 {
  56         struct drm_device *dev = ring->dev;
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 cmd;
  59         int ret;
  60
  61 #if WATCH_EXEC
  62         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
  63                   invalidate_domains, flush_domains);
  64 #endif
  65
  66         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
  67                                      invalidate_domains, flush_domains);
  68
  69         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
  70                 /*
  71                  * read/write caches:
  72                  *
  73                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  74                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  75                  * also flushed at 2d versus 3d pipeline switches.
  76                  *
  77                  * read-only caches:
  78                  *
  79                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  80                  * MI_READ_FLUSH is set, and is always flushed on 965.
  81                  *
  82                  * I915_GEM_DOMAIN_COMMAND may not exist?
  83                  *
  84                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  85                  * invalidated when MI_EXE_FLUSH is set.
  86                  *
  87                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  88                  * invalidated with every MI_FLUSH.
  89                  *
  90                  * TLBs:
  91                  *
  92                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  93                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  94                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  95                  * are flushed at any MI_FLUSH.
  96                  */
  97
  98                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  99                 if ((invalidate_domains|flush_domains) &
 100                     I915_GEM_DOMAIN_RENDER)
 101                         cmd &= ~MI_NO_WRITE_FLUSH;
 102                 if (INTEL_INFO(dev)->gen < 4) {
 103                         /*
 104                          * On the 965, the sampler cache always gets flushed
 105                          * and this bit is reserved.
 106                          */
 107                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 108                                 cmd |= MI_READ_FLUSH;
 109                 }
 110                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 111                         cmd |= MI_EXE_FLUSH;
 112
 113                 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 114                     (IS_G4X(dev) || IS_GEN5(dev)))
 115                         cmd |= MI_INVALIDATE_ISP;
 116
 117 #if WATCH_EXEC
 118                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 119 #endif
 120                 ret = intel_ring_begin(ring, 2);
 121                 if (ret)
 122                         return ret;
 123
 124                 intel_ring_emit(ring, cmd);
 125                 intel_ring_emit(ring, MI_NOOP);
 126                 intel_ring_advance(ring);
 127         }
 128
 129         return 0;
 130 }
 131
 132 static void ring_write_tail(struct intel_ring_buffer *ring,
 133                             u32 value)
 134 {
 135         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 136         I915_WRITE_TAIL(ring, value);
 137 }
 138
 139 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 140 {
 141         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 142         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 143                         RING_ACTHD(ring->mmio_base) : ACTHD;
 144
 145         return I915_READ(acthd_reg);
 146 }
 147
 148 static int init_ring_common(struct intel_ring_buffer *ring)
 149 {
 150         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 151         struct drm_i915_gem_object *obj = ring->obj;
 152         u32 head;
 153
 154         /* Stop the ring if it's running. */
 155         I915_WRITE_CTL(ring, 0);
 156         I915_WRITE_HEAD(ring, 0);
 157         ring->write_tail(ring, 0);
 158
 159         /* Initialize the ring. */
 160         I915_WRITE_START(ring, obj->gtt_offset);
 161         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 162
 163         /* G45 ring initialization fails to reset head to zero */
 164         if (head != 0) {
 165                 DRM_DEBUG_KMS("%s head not reset to zero "
 166                               "ctl %08x head %08x tail %08x start %08x\n",
 167                               ring->name,
 168                               I915_READ_CTL(ring),
 169                               I915_READ_HEAD(ring),
 170                               I915_READ_TAIL(ring),
 171                               I915_READ_START(ring));
 172
 173                 I915_WRITE_HEAD(ring, 0);
 174
 175                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 176                         DRM_ERROR("failed to set %s head to zero "
 177                                   "ctl %08x head %08x tail %08x start %08x\n",
 178                                   ring->name,
 179                                   I915_READ_CTL(ring),
 180                                   I915_READ_HEAD(ring),
 181                                   I915_READ_TAIL(ring),
 182                                   I915_READ_START(ring));
 183                 }
 184         }
 185
 186         I915_WRITE_CTL(ring,
 187                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 188                         | RING_REPORT_64K | RING_VALID);
 189
 190         /* If the head is still not zero, the ring is dead */
 191         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 192             I915_READ_START(ring) != obj->gtt_offset ||
 193             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 194                 DRM_ERROR("%s initialization failed "
 195                                 "ctl %08x head %08x tail %08x start %08x\n",
 196                                 ring->name,
 197                                 I915_READ_CTL(ring),
 198                                 I915_READ_HEAD(ring),
 199                                 I915_READ_TAIL(ring),
 200                                 I915_READ_START(ring));
 201                 return -EIO;
 202         }
 203
 204         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 205                 i915_kernel_lost_context(ring->dev);
 206         else {
 207                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 208                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 209                 ring->space = ring->head - (ring->tail + 8);
 210                 if (ring->space < 0)
 211                         ring->space += ring->size;
 212         }
 213
 214         return 0;
 215 }
 216
 217 /*
 218  * 965+ support PIPE_CONTROL commands, which provide finer grained control
 219  * over cache flushing.
 220  */
 221 struct pipe_control {
 222         struct drm_i915_gem_object *obj;
 223         volatile u32 *cpu_page;
 224         u32 gtt_offset;
 225 };
 226
 227 static int
 228 init_pipe_control(struct intel_ring_buffer *ring)
 229 {
 230         struct pipe_control *pc;
 231         struct drm_i915_gem_object *obj;
 232         int ret;
 233
 234         if (ring->private)
 235                 return 0;
 236
 237         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 238         if (!pc)
 239                 return -ENOMEM;
 240
 241         obj = i915_gem_alloc_object(ring->dev, 4096);
 242         if (obj == NULL) {
 243                 DRM_ERROR("Failed to allocate seqno page\n");
 244                 ret = -ENOMEM;
 245                 goto err;
 246         }
 247         obj->agp_type = AGP_USER_CACHED_MEMORY;
 248
 249         ret = i915_gem_object_pin(obj, 4096, true);
 250         if (ret)
 251                 goto err_unref;
 252
 253         pc->gtt_offset = obj->gtt_offset;
 254         pc->cpu_page =  kmap(obj->pages[0]);
 255         if (pc->cpu_page == NULL)
 256                 goto err_unpin;
 257
 258         pc->obj = obj;
 259         ring->private = pc;
 260         return 0;
 261
 262 err_unpin:
 263         i915_gem_object_unpin(obj);
 264 err_unref:
 265         drm_gem_object_unreference(&obj->base);
 266 err:
 267         kfree(pc);
 268         return ret;
 269 }
 270
 271 static void
 272 cleanup_pipe_control(struct intel_ring_buffer *ring)
 273 {
 274         struct pipe_control *pc = ring->private;
 275         struct drm_i915_gem_object *obj;
 276
 277         if (!ring->private)
 278                 return;
 279
 280         obj = pc->obj;
 281         kunmap(obj->pages[0]);
 282         i915_gem_object_unpin(obj);
 283         drm_gem_object_unreference(&obj->base);
 284
 285         kfree(pc);
 286         ring->private = NULL;
 287 }
 288
 289 static int init_render_ring(struct intel_ring_buffer *ring)
 290 {
 291         struct drm_device *dev = ring->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         int ret = init_ring_common(ring);
 294
 295         if (INTEL_INFO(dev)->gen > 3) {
 296                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 297                 if (IS_GEN6(dev))
 298                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 299                 I915_WRITE(MI_MODE, mode);
 300         }
 301
 302         if (INTEL_INFO(dev)->gen >= 6) {
 303         } else if (IS_GEN5(dev)) {
 304                 ret = init_pipe_control(ring);
 305                 if (ret)
 306                         return ret;
 307         }
 308
 309         return ret;
 310 }
 311
 312 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 313 {
 314         if (!ring->private)
 315                 return;
 316
 317         cleanup_pipe_control(ring);
 318 }
 319
 320 static void
 321 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
 322 {
 323         struct drm_device *dev = ring->dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325         int id;
 326
 327         /*
 328          * cs -> 1 = vcs, 0 = bcs
 329          * vcs -> 1 = bcs, 0 = cs,
 330          * bcs -> 1 = cs, 0 = vcs.
 331          */
 332         id = ring - dev_priv->ring;
 333         id += 2 - i;
 334         id %= 3;
 335
 336         intel_ring_emit(ring,
 337                         MI_SEMAPHORE_MBOX |
 338                         MI_SEMAPHORE_REGISTER |
 339                         MI_SEMAPHORE_UPDATE);
 340         intel_ring_emit(ring, seqno);
 341         intel_ring_emit(ring,
 342                         RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
 343 }
 344
 345 static int
 346 gen6_add_request(struct intel_ring_buffer *ring,
 347                  u32 *result)
 348 {
 349         u32 seqno;
 350         int ret;
 351
 352         ret = intel_ring_begin(ring, 10);
 353         if (ret)
 354                 return ret;
 355
 356         seqno = i915_gem_get_seqno(ring->dev);
 357         update_semaphore(ring, 0, seqno);
 358         update_semaphore(ring, 1, seqno);
 359
 360         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 361         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 362         intel_ring_emit(ring, seqno);
 363         intel_ring_emit(ring, MI_USER_INTERRUPT);
 364         intel_ring_advance(ring);
 365
 366         *result = seqno;
 367         return 0;
 368 }
 369
 370 int
 371 intel_ring_sync(struct intel_ring_buffer *ring,
 372                 struct intel_ring_buffer *to,
 373                 u32 seqno)
 374 {
 375         int ret;
 376
 377         ret = intel_ring_begin(ring, 4);
 378         if (ret)
 379                 return ret;
 380
 381         intel_ring_emit(ring,
 382                         MI_SEMAPHORE_MBOX |
 383                         MI_SEMAPHORE_REGISTER |
 384                         intel_ring_sync_index(ring, to) << 17 |
 385                         MI_SEMAPHORE_COMPARE);
 386         intel_ring_emit(ring, seqno);
 387         intel_ring_emit(ring, 0);
 388         intel_ring_emit(ring, MI_NOOP);
 389         intel_ring_advance(ring);
 390
 391         return 0;
 392 }
 393
 394 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 395 do {                                                                    \
 396         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
 397                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 398         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 399         intel_ring_emit(ring__, 0);                                                     \
 400         intel_ring_emit(ring__, 0);                                                     \
 401 } while (0)
 402
 403 static int
 404 pc_render_add_request(struct intel_ring_buffer *ring,
 405                       u32 *result)
 406 {
 407         struct drm_device *dev = ring->dev;
 408         u32 seqno = i915_gem_get_seqno(dev);
 409         struct pipe_control *pc = ring->private;
 410         u32 scratch_addr = pc->gtt_offset + 128;
 411         int ret;
 412
 413         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 414          * incoherent with writes to memory, i.e. completely fubar,
 415          * so we need to use PIPE_NOTIFY instead.
 416          *
 417          * However, we also need to workaround the qword write
 418          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 419          * memory before requesting an interrupt.
 420          */
 421         ret = intel_ring_begin(ring, 32);
 422         if (ret)
 423                 return ret;
 424
 425         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 426                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 427         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 428         intel_ring_emit(ring, seqno);
 429         intel_ring_emit(ring, 0);
 430         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 431         scratch_addr += 128; /* write to separate cachelines */
 432         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 433         scratch_addr += 128;
 434         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 435         scratch_addr += 128;
 436         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 437         scratch_addr += 128;
 438         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 439         scratch_addr += 128;
 440         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 441         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 442                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 443                         PIPE_CONTROL_NOTIFY);
 444         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 445         intel_ring_emit(ring, seqno);
 446         intel_ring_emit(ring, 0);
 447         intel_ring_advance(ring);
 448
 449         *result = seqno;
 450         return 0;
 451 }
 452
 453 static int
 454 render_ring_add_request(struct intel_ring_buffer *ring,
 455                         u32 *result)
 456 {
 457         struct drm_device *dev = ring->dev;
 458         u32 seqno = i915_gem_get_seqno(dev);
 459         int ret;
 460
 461         ret = intel_ring_begin(ring, 4);
 462         if (ret)
 463                 return ret;
 464
 465         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 466         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 467         intel_ring_emit(ring, seqno);
 468         intel_ring_emit(ring, MI_USER_INTERRUPT);
 469         intel_ring_advance(ring);
 470
 471         *result = seqno;
 472         return 0;
 473 }
 474
 475 static u32
 476 ring_get_seqno(struct intel_ring_buffer *ring)
 477 {
 478         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 479 }
 480
 481 static u32
 482 pc_render_get_seqno(struct intel_ring_buffer *ring)
 483 {
 484         struct pipe_control *pc = ring->private;
 485         return pc->cpu_page[0];
 486 }
 487
 488 static bool
 489 render_ring_get_irq(struct intel_ring_buffer *ring)
 490 {
 491         struct drm_device *dev = ring->dev;
 492
 493         if (!dev->irq_enabled)
 494                 return false;
 495
 496         if (atomic_inc_return(&ring->irq_refcount) == 1) {
 497                 drm_i915_private_t *dev_priv = dev->dev_private;
 498                 unsigned long irqflags;
 499
 500                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 501                 if (HAS_PCH_SPLIT(dev))
 502                         ironlake_enable_graphics_irq(dev_priv,
 503                                                      GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 504                 else
 505                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 506                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 507         }
 508
 509         return true;
 510 }
 511
 512 static void
 513 render_ring_put_irq(struct intel_ring_buffer *ring)
 514 {
 515         struct drm_device *dev = ring->dev;
 516
 517         if (atomic_dec_and_test(&ring->irq_refcount)) {
 518                 drm_i915_private_t *dev_priv = dev->dev_private;
 519                 unsigned long irqflags;
 520
 521                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 522                 if (HAS_PCH_SPLIT(dev))
 523                         ironlake_disable_graphics_irq(dev_priv,
 524                                                       GT_USER_INTERRUPT |
 525                                                       GT_PIPE_NOTIFY);
 526                 else
 527                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 528                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 529         }
 530 }
 531
 532 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 533 {
 534         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 535         u32 mmio = IS_GEN6(ring->dev) ?
 536                 RING_HWS_PGA_GEN6(ring->mmio_base) :
 537                 RING_HWS_PGA(ring->mmio_base);
 538         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 539         POSTING_READ(mmio);
 540 }
 541
 542 static int
 543 bsd_ring_flush(struct intel_ring_buffer *ring,
 544                u32     invalidate_domains,
 545                u32     flush_domains)
 546 {
 547         int ret;
 548
 549         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
 550                 return 0;
 551
 552         ret = intel_ring_begin(ring, 2);
 553         if (ret)
 554                 return ret;
 555
 556         intel_ring_emit(ring, MI_FLUSH);
 557         intel_ring_emit(ring, MI_NOOP);
 558         intel_ring_advance(ring);
 559         return 0;
 560 }
 561
 562 static int
 563 ring_add_request(struct intel_ring_buffer *ring,
 564                  u32 *result)
 565 {
 566         u32 seqno;
 567         int ret;
 568
 569         ret = intel_ring_begin(ring, 4);
 570         if (ret)
 571                 return ret;
 572
 573         seqno = i915_gem_get_seqno(ring->dev);
 574
 575         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 576         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 577         intel_ring_emit(ring, seqno);
 578         intel_ring_emit(ring, MI_USER_INTERRUPT);
 579         intel_ring_advance(ring);
 580
 581         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
 582         *result = seqno;
 583         return 0;
 584 }
 585
 586 static bool
 587 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
 588 {
 589         struct drm_device *dev = ring->dev;
 590
 591         if (!dev->irq_enabled)
 592                return false;
 593
 594         if (atomic_inc_return(&ring->irq_refcount) == 1) {
 595                 drm_i915_private_t *dev_priv = dev->dev_private;
 596                 unsigned long irqflags;
 597
 598                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 599                 ironlake_enable_graphics_irq(dev_priv, flag);
 600                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 601         }
 602
 603         return true;
 604 }
 605
 606 static void
 607 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
 608 {
 609         struct drm_device *dev = ring->dev;
 610
 611         if (atomic_dec_and_test(&ring->irq_refcount)) {
 612                 drm_i915_private_t *dev_priv = dev->dev_private;
 613                 unsigned long irqflags;
 614
 615                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 616                 ironlake_disable_graphics_irq(dev_priv, flag);
 617                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 618         }
 619 }
 620
 621 static bool
 622 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 623 {
 624         return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
 625 }
 626 static void
 627 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 628 {
 629         ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
 630 }
 631
 632 static int
 633 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 634 {
 635         int ret;
 636
 637         ret = intel_ring_begin(ring, 2);
 638         if (ret)
 639                 return ret;
 640
 641         intel_ring_emit(ring,
 642                         MI_BATCH_BUFFER_START | (2 << 6) |
 643                         MI_BATCH_NON_SECURE_I965);
 644         intel_ring_emit(ring, offset);
 645         intel_ring_advance(ring);
 646
 647         return 0;
 648 }
 649
 650 static int
 651 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 652                                 u32 offset, u32 len)
 653 {
 654         struct drm_device *dev = ring->dev;
 655         drm_i915_private_t *dev_priv = dev->dev_private;
 656         int ret;
 657
 658         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
 659
 660         if (IS_I830(dev) || IS_845G(dev)) {
 661                 ret = intel_ring_begin(ring, 4);
 662                 if (ret)
 663                         return ret;
 664
 665                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 666                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 667                 intel_ring_emit(ring, offset + len - 8);
 668                 intel_ring_emit(ring, 0);
 669         } else {
 670                 ret = intel_ring_begin(ring, 2);
 671                 if (ret)
 672                         return ret;
 673
 674                 if (INTEL_INFO(dev)->gen >= 4) {
 675                         intel_ring_emit(ring,
 676                                         MI_BATCH_BUFFER_START | (2 << 6) |
 677                                         MI_BATCH_NON_SECURE_I965);
 678                         intel_ring_emit(ring, offset);
 679                 } else {
 680                         intel_ring_emit(ring,
 681                                         MI_BATCH_BUFFER_START | (2 << 6));
 682                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 683                 }
 684         }
 685         intel_ring_advance(ring);
 686
 687         return 0;
 688 }
 689
 690 static void cleanup_status_page(struct intel_ring_buffer *ring)
 691 {
 692         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 693         struct drm_i915_gem_object *obj;
 694
 695         obj = ring->status_page.obj;
 696         if (obj == NULL)
 697                 return;
 698
 699         kunmap(obj->pages[0]);
 700         i915_gem_object_unpin(obj);
 701         drm_gem_object_unreference(&obj->base);
 702         ring->status_page.obj = NULL;
 703
 704         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 705 }
 706
 707 static int init_status_page(struct intel_ring_buffer *ring)
 708 {
 709         struct drm_device *dev = ring->dev;
 710         drm_i915_private_t *dev_priv = dev->dev_private;
 711         struct drm_i915_gem_object *obj;
 712         int ret;
 713
 714         obj = i915_gem_alloc_object(dev, 4096);
 715         if (obj == NULL) {
 716                 DRM_ERROR("Failed to allocate status page\n");
 717                 ret = -ENOMEM;
 718                 goto err;
 719         }
 720         obj->agp_type = AGP_USER_CACHED_MEMORY;
 721
 722         ret = i915_gem_object_pin(obj, 4096, true);
 723         if (ret != 0) {
 724                 goto err_unref;
 725         }
 726
 727         ring->status_page.gfx_addr = obj->gtt_offset;
 728         ring->status_page.page_addr = kmap(obj->pages[0]);
 729         if (ring->status_page.page_addr == NULL) {
 730                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 731                 goto err_unpin;
 732         }
 733         ring->status_page.obj = obj;
 734         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 735
 736         intel_ring_setup_status_page(ring);
 737         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 738                         ring->name, ring->status_page.gfx_addr);
 739
 740         return 0;
 741
 742 err_unpin:
 743         i915_gem_object_unpin(obj);
 744 err_unref:
 745         drm_gem_object_unreference(&obj->base);
 746 err:
 747         return ret;
 748 }
 749
 750 int intel_init_ring_buffer(struct drm_device *dev,
 751                            struct intel_ring_buffer *ring)
 752 {
 753         struct drm_i915_gem_object *obj;
 754         int ret;
 755
 756         ring->dev = dev;
 757         INIT_LIST_HEAD(&ring->active_list);
 758         INIT_LIST_HEAD(&ring->request_list);
 759         INIT_LIST_HEAD(&ring->gpu_write_list);
 760
 761         if (I915_NEED_GFX_HWS(dev)) {
 762                 ret = init_status_page(ring);
 763                 if (ret)
 764                         return ret;
 765         }
 766
 767         obj = i915_gem_alloc_object(dev, ring->size);
 768         if (obj == NULL) {
 769                 DRM_ERROR("Failed to allocate ringbuffer\n");
 770                 ret = -ENOMEM;
 771                 goto err_hws;
 772         }
 773
 774         ring->obj = obj;
 775
 776         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 777         if (ret)
 778                 goto err_unref;
 779
 780         ring->map.size = ring->size;
 781         ring->map.offset = dev->agp->base + obj->gtt_offset;
 782         ring->map.type = 0;
 783         ring->map.flags = 0;
 784         ring->map.mtrr = 0;
 785
 786         drm_core_ioremap_wc(&ring->map, dev);
 787         if (ring->map.handle == NULL) {
 788                 DRM_ERROR("Failed to map ringbuffer.\n");
 789                 ret = -EINVAL;
 790                 goto err_unpin;
 791         }
 792
 793         ring->virtual_start = ring->map.handle;
 794         ret = ring->init(ring);
 795         if (ret)
 796                 goto err_unmap;
 797
 798         /* Workaround an erratum on the i830 which causes a hang if
 799          * the TAIL pointer points to within the last 2 cachelines
 800          * of the buffer.
 801          */
 802         ring->effective_size = ring->size;
 803         if (IS_I830(ring->dev))
 804                 ring->effective_size -= 128;
 805
 806         return 0;
 807
 808 err_unmap:
 809         drm_core_ioremapfree(&ring->map, dev);
 810 err_unpin:
 811         i915_gem_object_unpin(obj);
 812 err_unref:
 813         drm_gem_object_unreference(&obj->base);
 814         ring->obj = NULL;
 815 err_hws:
 816         cleanup_status_page(ring);
 817         return ret;
 818 }
 819
 820 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
 821 {
 822         struct drm_i915_private *dev_priv;
 823         int ret;
 824
 825         if (ring->obj == NULL)
 826                 return;
 827
 828         /* Disable the ring buffer. The ring must be idle at this point */
 829         dev_priv = ring->dev->dev_private;
 830         ret = intel_wait_ring_buffer(ring, ring->size - 8);
 831         I915_WRITE_CTL(ring, 0);
 832
 833         drm_core_ioremapfree(&ring->map, ring->dev);
 834
 835         i915_gem_object_unpin(ring->obj);
 836         drm_gem_object_unreference(&ring->obj->base);
 837         ring->obj = NULL;
 838
 839         if (ring->cleanup)
 840                 ring->cleanup(ring);
 841
 842         cleanup_status_page(ring);
 843 }
 844
 845 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
 846 {
 847         unsigned int *virt;
 848         int rem = ring->size - ring->tail;
 849
 850         if (ring->space < rem) {
 851                 int ret = intel_wait_ring_buffer(ring, rem);
 852                 if (ret)
 853                         return ret;
 854         }
 855
 856         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 857         rem /= 8;
 858         while (rem--) {
 859                 *virt++ = MI_NOOP;
 860                 *virt++ = MI_NOOP;
 861         }
 862
 863         ring->tail = 0;
 864         ring->space = ring->head - 8;
 865
 866         return 0;
 867 }
 868
 869 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
 870 {
 871         struct drm_device *dev = ring->dev;
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873         unsigned long end;
 874         u32 head;
 875
 876         trace_i915_ring_wait_begin (dev);
 877         end = jiffies + 3 * HZ;
 878         do {
 879                 /* If the reported head position has wrapped or hasn't advanced,
 880                  * fallback to the slow and accurate path.
 881                  */
 882                 head = intel_read_status_page(ring, 4);
 883                 if (head < ring->actual_head)
 884                         head = I915_READ_HEAD(ring);
 885                 ring->actual_head = head;
 886                 ring->head = head & HEAD_ADDR;
 887                 ring->space = ring->head - (ring->tail + 8);
 888                 if (ring->space < 0)
 889                         ring->space += ring->size;
 890                 if (ring->space >= n) {
 891                         trace_i915_ring_wait_end(dev);
 892                         return 0;
 893                 }
 894
 895                 if (dev->primary->master) {
 896                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 897                         if (master_priv->sarea_priv)
 898                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 899                 }
 900
 901                 msleep(1);
 902                 if (atomic_read(&dev_priv->mm.wedged))
 903                         return -EAGAIN;
 904         } while (!time_after(jiffies, end));
 905         trace_i915_ring_wait_end (dev);
 906         return -EBUSY;
 907 }
 908
 909 int intel_ring_begin(struct intel_ring_buffer *ring,
 910                      int num_dwords)
 911 {
 912         int n = 4*num_dwords;
 913         int ret;
 914
 915         if (unlikely(ring->tail + n > ring->effective_size)) {
 916                 ret = intel_wrap_ring_buffer(ring);
 917                 if (unlikely(ret))
 918                         return ret;
 919         }
 920
 921         if (unlikely(ring->space < n)) {
 922                 ret = intel_wait_ring_buffer(ring, n);
 923                 if (unlikely(ret))
 924                         return ret;
 925         }
 926
 927         ring->space -= n;
 928         return 0;
 929 }
 930
 931 void intel_ring_advance(struct intel_ring_buffer *ring)
 932 {
 933         ring->tail &= ring->size - 1;
 934         ring->write_tail(ring, ring->tail);
 935 }
 936
 937 static const struct intel_ring_buffer render_ring = {
 938         .name                   = "render ring",
 939         .id                     = RING_RENDER,
 940         .mmio_base              = RENDER_RING_BASE,
 941         .size                   = 32 * PAGE_SIZE,
 942         .init                   = init_render_ring,
 943         .write_tail             = ring_write_tail,
 944         .flush                  = render_ring_flush,
 945         .add_request            = render_ring_add_request,
 946         .get_seqno              = ring_get_seqno,
 947         .irq_get                = render_ring_get_irq,
 948         .irq_put                = render_ring_put_irq,
 949         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
 950        .cleanup                 = render_ring_cleanup,
 951 };
 952
 953 /* ring buffer for bit-stream decoder */
 954
 955 static const struct intel_ring_buffer bsd_ring = {
 956         .name                   = "bsd ring",
 957         .id                     = RING_BSD,
 958         .mmio_base              = BSD_RING_BASE,
 959         .size                   = 32 * PAGE_SIZE,
 960         .init                   = init_ring_common,
 961         .write_tail             = ring_write_tail,
 962         .flush                  = bsd_ring_flush,
 963         .add_request            = ring_add_request,
 964         .get_seqno              = ring_get_seqno,
 965         .irq_get                = bsd_ring_get_irq,
 966         .irq_put                = bsd_ring_put_irq,
 967         .dispatch_execbuffer    = ring_dispatch_execbuffer,
 968 };
 969
 970
 971 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
 972                                      u32 value)
 973 {
 974        drm_i915_private_t *dev_priv = ring->dev->dev_private;
 975
 976        /* Every tail move must follow the sequence below */
 977        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 978                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 979                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
 980        I915_WRITE(GEN6_BSD_RNCID, 0x0);
 981
 982        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
 983                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
 984                        50))
 985                DRM_ERROR("timed out waiting for IDLE Indicator\n");
 986
 987        I915_WRITE_TAIL(ring, value);
 988        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 989                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 990                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
 991 }
 992
 993 static int gen6_ring_flush(struct intel_ring_buffer *ring,
 994                            u32 invalidate_domains,
 995                            u32 flush_domains)
 996 {
 997         int ret;
 998
 999         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
1000                 return 0;
1001
1002         ret = intel_ring_begin(ring, 4);
1003         if (ret)
1004                 return ret;
1005
1006         intel_ring_emit(ring, MI_FLUSH_DW);
1007         intel_ring_emit(ring, 0);
1008         intel_ring_emit(ring, 0);
1009         intel_ring_emit(ring, 0);
1010         intel_ring_advance(ring);
1011         return 0;
1012 }
1013
1014 static int
1015 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1016                               u32 offset, u32 len)
1017 {
1018        int ret;
1019
1020        ret = intel_ring_begin(ring, 2);
1021        if (ret)
1022                return ret;
1023
1024        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1025        /* bit0-7 is the length on GEN6+ */
1026        intel_ring_emit(ring, offset);
1027        intel_ring_advance(ring);
1028
1029        return 0;
1030 }
1031
1032 static bool
1033 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1034 {
1035         return ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
1036 }
1037
1038 static void
1039 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1040 {
1041         ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
1042 }
1043
1044 /* ring buffer for Video Codec for Gen6+ */
1045 static const struct intel_ring_buffer gen6_bsd_ring = {
1046         .name                   = "gen6 bsd ring",
1047         .id                     = RING_BSD,
1048         .mmio_base              = GEN6_BSD_RING_BASE,
1049         .size                   = 32 * PAGE_SIZE,
1050         .init                   = init_ring_common,
1051         .write_tail             = gen6_bsd_ring_write_tail,
1052         .flush                  = gen6_ring_flush,
1053         .add_request            = gen6_add_request,
1054         .get_seqno              = ring_get_seqno,
1055         .irq_get                = gen6_bsd_ring_get_irq,
1056         .irq_put                = gen6_bsd_ring_put_irq,
1057         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1058 };
1059
1060 /* Blitter support (SandyBridge+) */
1061
1062 static bool
1063 blt_ring_get_irq(struct intel_ring_buffer *ring)
1064 {
1065         return ring_get_irq(ring, GT_BLT_USER_INTERRUPT);
1066 }
1067
1068 static void
1069 blt_ring_put_irq(struct intel_ring_buffer *ring)
1070 {
1071         ring_put_irq(ring, GT_BLT_USER_INTERRUPT);
1072 }
1073
1074
1075 /* Workaround for some stepping of SNB,
1076  * each time when BLT engine ring tail moved,
1077  * the first command in the ring to be parsed
1078  * should be MI_BATCH_BUFFER_START
1079  */
1080 #define NEED_BLT_WORKAROUND(dev) \
1081         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1082
1083 static inline struct drm_i915_gem_object *
1084 to_blt_workaround(struct intel_ring_buffer *ring)
1085 {
1086         return ring->private;
1087 }
1088
1089 static int blt_ring_init(struct intel_ring_buffer *ring)
1090 {
1091         if (NEED_BLT_WORKAROUND(ring->dev)) {
1092                 struct drm_i915_gem_object *obj;
1093                 u32 *ptr;
1094                 int ret;
1095
1096                 obj = i915_gem_alloc_object(ring->dev, 4096);
1097                 if (obj == NULL)
1098                         return -ENOMEM;
1099
1100                 ret = i915_gem_object_pin(obj, 4096, true);
1101                 if (ret) {
1102                         drm_gem_object_unreference(&obj->base);
1103                         return ret;
1104                 }
1105
1106                 ptr = kmap(obj->pages[0]);
1107                 *ptr++ = MI_BATCH_BUFFER_END;
1108                 *ptr++ = MI_NOOP;
1109                 kunmap(obj->pages[0]);
1110
1111                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1112                 if (ret) {
1113                         i915_gem_object_unpin(obj);
1114                         drm_gem_object_unreference(&obj->base);
1115                         return ret;
1116                 }
1117
1118                 ring->private = obj;
1119         }
1120
1121         return init_ring_common(ring);
1122 }
1123
1124 static int blt_ring_begin(struct intel_ring_buffer *ring,
1125                           int num_dwords)
1126 {
1127         if (ring->private) {
1128                 int ret = intel_ring_begin(ring, num_dwords+2);
1129                 if (ret)
1130                         return ret;
1131
1132                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1133                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1134
1135                 return 0;
1136         } else
1137                 return intel_ring_begin(ring, 4);
1138 }
1139
1140 static int blt_ring_flush(struct intel_ring_buffer *ring,
1141                            u32 invalidate_domains,
1142                            u32 flush_domains)
1143 {
1144         int ret;
1145
1146         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
1147                 return 0;
1148
1149         ret = blt_ring_begin(ring, 4);
1150         if (ret)
1151                 return ret;
1152
1153         intel_ring_emit(ring, MI_FLUSH_DW);
1154         intel_ring_emit(ring, 0);
1155         intel_ring_emit(ring, 0);
1156         intel_ring_emit(ring, 0);
1157         intel_ring_advance(ring);
1158         return 0;
1159 }
1160
1161 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1162 {
1163         if (!ring->private)
1164                 return;
1165
1166         i915_gem_object_unpin(ring->private);
1167         drm_gem_object_unreference(ring->private);
1168         ring->private = NULL;
1169 }
1170
1171 static const struct intel_ring_buffer gen6_blt_ring = {
1172        .name                    = "blt ring",
1173        .id                      = RING_BLT,
1174        .mmio_base               = BLT_RING_BASE,
1175        .size                    = 32 * PAGE_SIZE,
1176        .init                    = blt_ring_init,
1177        .write_tail              = ring_write_tail,
1178        .flush                   = blt_ring_flush,
1179        .add_request             = gen6_add_request,
1180        .get_seqno               = ring_get_seqno,
1181        .irq_get                 = blt_ring_get_irq,
1182        .irq_put                 = blt_ring_put_irq,
1183        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
1184        .cleanup                 = blt_ring_cleanup,
1185 };
1186
1187 int intel_init_render_ring_buffer(struct drm_device *dev)
1188 {
1189         drm_i915_private_t *dev_priv = dev->dev_private;
1190         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1191
1192         *ring = render_ring;
1193         if (INTEL_INFO(dev)->gen >= 6) {
1194                 ring->add_request = gen6_add_request;
1195         } else if (IS_GEN5(dev)) {
1196                 ring->add_request = pc_render_add_request;
1197                 ring->get_seqno = pc_render_get_seqno;
1198         }
1199
1200         if (!I915_NEED_GFX_HWS(dev)) {
1201                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1202                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1203         }
1204
1205         return intel_init_ring_buffer(dev, ring);
1206 }
1207
1208 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1209 {
1210         drm_i915_private_t *dev_priv = dev->dev_private;
1211         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1212
1213         if (IS_GEN6(dev))
1214                 *ring = gen6_bsd_ring;
1215         else
1216                 *ring = bsd_ring;
1217
1218         return intel_init_ring_buffer(dev, ring);
1219 }
1220
1221 int intel_init_blt_ring_buffer(struct drm_device *dev)
1222 {
1223         drm_i915_private_t *dev_priv = dev->dev_private;
1224         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1225
1226         *ring = gen6_blt_ring;
1227
1228         return intel_init_ring_buffer(dev, ring);
1229 }