1 #include <linux/init.h>
4 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/module.h>
11 #include <asm/tlbflush.h>
12 #include <asm/mmu_context.h>
13 #include <asm/cache.h>
15 #include <asm/uv/uv.h>
17 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
21 * Smarter SMP flushing macros.
24 * These mean you can really definitely utterly forget about
25 * writing to user space from interrupts. (Its not allowed anyway).
27 * Optimizations Manfred Spraul <manfred@colorfullife.com>
29 * More scalable flush, from Andi Kleen
31 * To avoid global state use 8 different call vectors.
32 * Each CPU uses a specific vector to trigger flushes on other
33 * CPUs. Depending on the received vector the target CPUs look into
34 * the right array slot for the flush data.
36 * With more than 8 CPUs they are hashed to the 8 available
37 * vectors. The limited global vector space forces us to this right now.
38 * In future when interrupts are split into per CPU domains this could be
39 * fixed, at the cost of triggering multiple IPIs in some cases.
42 union smp_flush_state {
44 struct mm_struct *flush_mm;
45 unsigned long flush_va;
46 raw_spinlock_t tlbstate_lock;
47 DECLARE_BITMAP(flush_cpumask, NR_CPUS);
49 char pad[INTERNODE_CACHE_BYTES];
50 } ____cacheline_internodealigned_in_smp;
52 /* State is put into the per CPU data section, but padded
53 to a full cache line because other CPUs can access it and we don't
54 want false sharing in the per cpu data segment. */
55 static union smp_flush_state flush_state[NUM_INVALIDATE_TLB_VECTORS];
57 static DEFINE_PER_CPU_READ_MOSTLY(int, tlb_vector_offset);
60 * We cannot call mmdrop() because we are in interrupt context,
61 * instead update mm->cpu_vm_mask.
63 void leave_mm(int cpu)
65 if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
67 cpumask_clear_cpu(cpu,
68 mm_cpumask(percpu_read(cpu_tlbstate.active_mm)));
69 load_cr3(swapper_pg_dir);
71 EXPORT_SYMBOL_GPL(leave_mm);
75 * The flush IPI assumes that a thread switch happens in this order:
76 * [cpu0: the cpu that switches]
77 * 1) switch_mm() either 1a) or 1b)
78 * 1a) thread switch to a different mm
79 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
80 * Stop ipi delivery for the old mm. This is not synchronized with
81 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
82 * for the wrong mm, and in the worst case we perform a superfluous
84 * 1a2) set cpu mmu_state to TLBSTATE_OK
85 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
86 * was in lazy tlb mode.
87 * 1a3) update cpu active_mm
88 * Now cpu0 accepts tlb flushes for the new mm.
89 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
90 * Now the other cpus will send tlb flush ipis.
92 * 1b) thread switch without mm change
93 * cpu active_mm is correct, cpu0 already handles
95 * 1b1) set cpu mmu_state to TLBSTATE_OK
96 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
97 * Atomically set the bit [other cpus will start sending flush ipis],
99 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
100 * 2) switch %%esp, ie current
102 * The interrupt must handle 2 special cases:
103 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
104 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
105 * runs in kernel space, the cpu could load tlb entries for user space
108 * The good news is that cpu mmu_state is local to each cpu, no
109 * write/read ordering problems.
115 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
116 * 2) Leave the mm if we are in the lazy tlb mode.
118 * Interrupts are disabled.
122 * FIXME: use of asmlinkage is not consistent. On x86_64 it's noop
123 * but still used for documentation purpose but the usage is slightly
124 * inconsistent. On x86_32, asmlinkage is regparm(0) but interrupt
125 * entry calls in with the first parameter in %eax. Maybe define
131 void smp_invalidate_interrupt(struct pt_regs *regs)
135 union smp_flush_state *f;
137 cpu = smp_processor_id();
140 if (current->active_mm)
141 load_user_cs_desc(cpu, current->active_mm);
145 * orig_rax contains the negated interrupt vector.
146 * Use that to determine where the sender put the data.
148 sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
149 f = &flush_state[sender];
151 if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
154 * This was a BUG() but until someone can quote me the
155 * line from the intel manual that guarantees an IPI to
156 * multiple CPUs is retried _only_ on the erroring CPUs
157 * its staying as a return
162 if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
163 if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
164 if (f->flush_va == TLB_FLUSH_ALL)
167 __flush_tlb_one(f->flush_va);
173 smp_mb__before_clear_bit();
174 cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
175 smp_mb__after_clear_bit();
176 inc_irq_stat(irq_tlb_count);
179 static void flush_tlb_others_ipi(const struct cpumask *cpumask,
180 struct mm_struct *mm, unsigned long va)
183 union smp_flush_state *f;
185 /* Caller has disabled preemption */
186 sender = this_cpu_read(tlb_vector_offset);
187 f = &flush_state[sender];
190 * Could avoid this lock when
191 * num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
192 * probably not worth checking this for a cache-hot lock.
194 raw_spin_lock(&f->tlbstate_lock);
198 if (cpumask_andnot(to_cpumask(f->flush_cpumask), cpumask, cpumask_of(smp_processor_id()))) {
200 * We have to send the IPI only to
203 apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
204 INVALIDATE_TLB_VECTOR_START + sender);
206 while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
212 raw_spin_unlock(&f->tlbstate_lock);
215 void native_flush_tlb_others(const struct cpumask *cpumask,
216 struct mm_struct *mm, unsigned long va)
218 if (is_uv_system()) {
222 cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
224 flush_tlb_others_ipi(cpumask, mm, va);
228 flush_tlb_others_ipi(cpumask, mm, va);
231 static void __cpuinit calculate_tlb_offset(void)
233 int cpu, node, nr_node_vecs, idx = 0;
235 * we are changing tlb_vector_offset for each CPU in runtime, but this
236 * will not cause inconsistency, as the write is atomic under X86. we
237 * might see more lock contentions in a short time, but after all CPU's
238 * tlb_vector_offset are changed, everything should go normal
240 * Note: if NUM_INVALIDATE_TLB_VECTORS % nr_online_nodes !=0, we might
241 * waste some vectors.
243 if (nr_online_nodes > NUM_INVALIDATE_TLB_VECTORS)
246 nr_node_vecs = NUM_INVALIDATE_TLB_VECTORS/nr_online_nodes;
248 for_each_online_node(node) {
249 int node_offset = (idx % NUM_INVALIDATE_TLB_VECTORS) *
252 for_each_cpu(cpu, cpumask_of_node(node)) {
253 per_cpu(tlb_vector_offset, cpu) = node_offset +
256 cpu_offset = cpu_offset % nr_node_vecs;
262 static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
263 unsigned long action, void *hcpu)
265 switch (action & 0xf) {
268 calculate_tlb_offset();
273 static int __cpuinit init_smp_flush(void)
277 for (i = 0; i < ARRAY_SIZE(flush_state); i++)
278 raw_spin_lock_init(&flush_state[i].tlbstate_lock);
280 calculate_tlb_offset();
281 hotcpu_notifier(tlb_cpuhp_notify, 0);
284 core_initcall(init_smp_flush);
286 void flush_tlb_current_task(void)
288 struct mm_struct *mm = current->mm;
293 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
294 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
298 void flush_tlb_mm(struct mm_struct *mm)
302 if (current->active_mm == mm) {
306 leave_mm(smp_processor_id());
308 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
309 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
314 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
316 struct mm_struct *mm = vma->vm_mm;
320 if (current->active_mm == mm) {
324 leave_mm(smp_processor_id());
327 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
328 flush_tlb_others(mm_cpumask(mm), mm, va);
333 static void do_flush_tlb_all(void *info)
336 if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
337 leave_mm(smp_processor_id());
340 void flush_tlb_all(void)
342 on_each_cpu(do_flush_tlb_all, NULL, 1);