drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/pci.h>
  38 #include <linux/vgaarb.h>
  39 #include <linux/acpi.h>
  40 #include <linux/pnp.h>
  41 #include <linux/vga_switcheroo.h>
  42 #include <linux/slab.h>
  43 #include <acpi/video.h>
  44
  45 /**
  46  * Sets up the hardware status page for devices that need a physical address
  47  * in the register.
  48  */
  49 static int i915_init_phys_hws(struct drm_device *dev)
  50 {
  51         drm_i915_private_t *dev_priv = dev->dev_private;
  52         /* Program Hardware Status Page */
  53         dev_priv->status_page_dmah =
  54                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  55
  56         if (!dev_priv->status_page_dmah) {
  57                 DRM_ERROR("Can not allocate hardware status page\n");
  58                 return -ENOMEM;
  59         }
  60         dev_priv->render_ring.status_page.page_addr
  61                 = dev_priv->status_page_dmah->vaddr;
  62         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  63
  64         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  65
  66         if (IS_I965G(dev))
  67                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  68                                              0xf0;
  69
  70         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  71         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  72         return 0;
  73 }
  74
  75 /**
  76  * Frees the hardware status page, whether it's a physical address or a virtual
  77  * address set up by the X Server.
  78  */
  79 static void i915_free_hws(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         if (dev_priv->status_page_dmah) {
  83                 drm_pci_free(dev, dev_priv->status_page_dmah);
  84                 dev_priv->status_page_dmah = NULL;
  85         }
  86
  87         if (dev_priv->render_ring.status_page.gfx_addr) {
  88                 dev_priv->render_ring.status_page.gfx_addr = 0;
  89                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  90         }
  91
  92         /* Need to rewrite hardware status page */
  93         I915_WRITE(HWS_PGA, 0x1ffff000);
  94 }
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         drm_i915_private_t *dev_priv = dev->dev_private;
  99         struct drm_i915_master_private *master_priv;
 100         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 101
 102         /*
 103          * We should never lose context on the ring with modesetting
 104          * as we don't expose it to userspace
 105          */
 106         if (drm_core_check_feature(dev, DRIVER_MODESET))
 107                 return;
 108
 109         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 110         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 111         ring->space = ring->head - (ring->tail + 8);
 112         if (ring->space < 0)
 113                 ring->space += ring->size;
 114
 115         if (!dev->primary->master)
 116                 return;
 117
 118         master_priv = dev->primary->master->driver_priv;
 119         if (ring->head == ring->tail && master_priv->sarea_priv)
 120                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 121 }
 122
 123 static int i915_dma_cleanup(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         /* Make sure interrupts are disabled here because the uninstall ioctl
 127          * may not have been called from userspace and after dev_private
 128          * is freed, it's too late.
 129          */
 130         if (dev->irq_enabled)
 131                 drm_irq_uninstall(dev);
 132
 133         mutex_lock(&dev->struct_mutex);
 134         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 135         if (HAS_BSD(dev))
 136                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 137         mutex_unlock(&dev->struct_mutex);
 138
 139         /* Clear the HWS virtual address at teardown */
 140         if (I915_NEED_GFX_HWS(dev))
 141                 i915_free_hws(dev);
 142
 143         return 0;
 144 }
 145
 146 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 147 {
 148         drm_i915_private_t *dev_priv = dev->dev_private;
 149         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 150
 151         master_priv->sarea = drm_getsarea(dev);
 152         if (master_priv->sarea) {
 153                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 154                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 155         } else {
 156                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 157         }
 158
 159         if (init->ring_size != 0) {
 160                 if (dev_priv->render_ring.gem_object != NULL) {
 161                         i915_dma_cleanup(dev);
 162                         DRM_ERROR("Client tried to initialize ringbuffer in "
 163                                   "GEM mode\n");
 164                         return -EINVAL;
 165                 }
 166
 167                 dev_priv->render_ring.size = init->ring_size;
 168
 169                 dev_priv->render_ring.map.offset = init->ring_start;
 170                 dev_priv->render_ring.map.size = init->ring_size;
 171                 dev_priv->render_ring.map.type = 0;
 172                 dev_priv->render_ring.map.flags = 0;
 173                 dev_priv->render_ring.map.mtrr = 0;
 174
 175                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 176
 177                 if (dev_priv->render_ring.map.handle == NULL) {
 178                         i915_dma_cleanup(dev);
 179                         DRM_ERROR("can not ioremap virtual address for"
 180                                   " ring buffer\n");
 181                         return -ENOMEM;
 182                 }
 183         }
 184
 185         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 186
 187         dev_priv->cpp = init->cpp;
 188         dev_priv->back_offset = init->back_offset;
 189         dev_priv->front_offset = init->front_offset;
 190         dev_priv->current_page = 0;
 191         if (master_priv->sarea_priv)
 192                 master_priv->sarea_priv->pf_current_page = 0;
 193
 194         /* Allow hardware batchbuffers unless told otherwise.
 195          */
 196         dev_priv->allow_batchbuffer = 1;
 197
 198         return 0;
 199 }
 200
 201 static int i915_dma_resume(struct drm_device * dev)
 202 {
 203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 204
 205         struct intel_ring_buffer *ring;
 206         DRM_DEBUG_DRIVER("%s\n", __func__);
 207
 208         ring = &dev_priv->render_ring;
 209
 210         if (ring->map.handle == NULL) {
 211                 DRM_ERROR("can not ioremap virtual address for"
 212                           " ring buffer\n");
 213                 return -ENOMEM;
 214         }
 215
 216         /* Program Hardware Status Page */
 217         if (!ring->status_page.page_addr) {
 218                 DRM_ERROR("Can not find hardware status page\n");
 219                 return -EINVAL;
 220         }
 221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 222                                 ring->status_page.page_addr);
 223         if (ring->status_page.gfx_addr != 0)
 224                 ring->setup_status_page(dev, ring);
 225         else
 226                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 227
 228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_init(struct drm_device *dev, void *data,
 234                          struct drm_file *file_priv)
 235 {
 236         drm_i915_init_t *init = data;
 237         int retcode = 0;
 238
 239         switch (init->func) {
 240         case I915_INIT_DMA:
 241                 retcode = i915_initialize(dev, init);
 242                 break;
 243         case I915_CLEANUP_DMA:
 244                 retcode = i915_dma_cleanup(dev);
 245                 break;
 246         case I915_RESUME_DMA:
 247                 retcode = i915_dma_resume(dev);
 248                 break;
 249         default:
 250                 retcode = -EINVAL;
 251                 break;
 252         }
 253
 254         return retcode;
 255 }
 256
 257 /* Implement basically the same security restrictions as hardware does
 258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 259  *
 260  * Most of the calculations below involve calculating the size of a
 261  * particular instruction.  It's important to get the size right as
 262  * that tells us where the next instruction to check is.  Any illegal
 263  * instruction detected will be given a size of zero, which is a
 264  * signal to abort the rest of the buffer.
 265  */
 266 static int do_validate_cmd(int cmd)
 267 {
 268         switch (((cmd >> 29) & 0x7)) {
 269         case 0x0:
 270                 switch ((cmd >> 23) & 0x3f) {
 271                 case 0x0:
 272                         return 1;       /* MI_NOOP */
 273                 case 0x4:
 274                         return 1;       /* MI_FLUSH */
 275                 default:
 276                         return 0;       /* disallow everything else */
 277                 }
 278                 break;
 279         case 0x1:
 280                 return 0;       /* reserved */
 281         case 0x2:
 282                 return (cmd & 0xff) + 2;        /* 2d commands */
 283         case 0x3:
 284                 if (((cmd >> 24) & 0x1f) <= 0x18)
 285                         return 1;
 286
 287                 switch ((cmd >> 24) & 0x1f) {
 288                 case 0x1c:
 289                         return 1;
 290                 case 0x1d:
 291                         switch ((cmd >> 16) & 0xff) {
 292                         case 0x3:
 293                                 return (cmd & 0x1f) + 2;
 294                         case 0x4:
 295                                 return (cmd & 0xf) + 2;
 296                         default:
 297                                 return (cmd & 0xffff) + 2;
 298                         }
 299                 case 0x1e:
 300                         if (cmd & (1 << 23))
 301                                 return (cmd & 0xffff) + 1;
 302                         else
 303                                 return 1;
 304                 case 0x1f:
 305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 306                                 return (cmd & 0x1ffff) + 2;
 307                         else if (cmd & (1 << 17))       /* indirect random */
 308                                 if ((cmd & 0xffff) == 0)
 309                                         return 0;       /* unknown length, too hard */
 310                                 else
 311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 312                         else
 313                                 return 2;       /* indirect sequential */
 314                 default:
 315                         return 0;
 316                 }
 317         default:
 318                 return 0;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int validate_cmd(int cmd)
 325 {
 326         int ret = do_validate_cmd(cmd);
 327
 328 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 329
 330         return ret;
 331 }
 332
 333 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 334 {
 335         drm_i915_private_t *dev_priv = dev->dev_private;
 336         int i;
 337
 338         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 339                 return -EINVAL;
 340
 341         BEGIN_LP_RING((dwords+1)&~1);
 342
 343         for (i = 0; i < dwords;) {
 344                 int cmd, sz;
 345
 346                 cmd = buffer[i];
 347
 348                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 349                         return -EINVAL;
 350
 351                 OUT_RING(cmd);
 352
 353                 while (++i, --sz) {
 354                         OUT_RING(buffer[i]);
 355                 }
 356         }
 357
 358         if (dwords & 1)
 359                 OUT_RING(0);
 360
 361         ADVANCE_LP_RING();
 362
 363         return 0;
 364 }
 365
 366 int
 367 i915_emit_box(struct drm_device *dev,
 368               struct drm_clip_rect *boxes,
 369               int i, int DR1, int DR4)
 370 {
 371         struct drm_clip_rect box = boxes[i];
 372
 373         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 374                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 375                           box.x1, box.y1, box.x2, box.y2);
 376                 return -EINVAL;
 377         }
 378
 379         if (IS_I965G(dev)) {
 380                 BEGIN_LP_RING(4);
 381                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 382                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 383                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 384                 OUT_RING(DR4);
 385                 ADVANCE_LP_RING();
 386         } else {
 387                 BEGIN_LP_RING(6);
 388                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 389                 OUT_RING(DR1);
 390                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 391                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 392                 OUT_RING(DR4);
 393                 OUT_RING(0);
 394                 ADVANCE_LP_RING();
 395         }
 396
 397         return 0;
 398 }
 399
 400 /* XXX: Emitting the counter should really be moved to part of the IRQ
 401  * emit. For now, do it in both places:
 402  */
 403
 404 static void i915_emit_breadcrumb(struct drm_device *dev)
 405 {
 406         drm_i915_private_t *dev_priv = dev->dev_private;
 407         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 408
 409         dev_priv->counter++;
 410         if (dev_priv->counter > 0x7FFFFFFFUL)
 411                 dev_priv->counter = 0;
 412         if (master_priv->sarea_priv)
 413                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 414
 415         BEGIN_LP_RING(4);
 416         OUT_RING(MI_STORE_DWORD_INDEX);
 417         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 418         OUT_RING(dev_priv->counter);
 419         OUT_RING(0);
 420         ADVANCE_LP_RING();
 421 }
 422
 423 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 424                                    drm_i915_cmdbuffer_t *cmd,
 425                                    struct drm_clip_rect *cliprects,
 426                                    void *cmdbuf)
 427 {
 428         int nbox = cmd->num_cliprects;
 429         int i = 0, count, ret;
 430
 431         if (cmd->sz & 0x3) {
 432                 DRM_ERROR("alignment");
 433                 return -EINVAL;
 434         }
 435
 436         i915_kernel_lost_context(dev);
 437
 438         count = nbox ? nbox : 1;
 439
 440         for (i = 0; i < count; i++) {
 441                 if (i < nbox) {
 442                         ret = i915_emit_box(dev, cliprects, i,
 443                                             cmd->DR1, cmd->DR4);
 444                         if (ret)
 445                                 return ret;
 446                 }
 447
 448                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         i915_emit_breadcrumb(dev);
 454         return 0;
 455 }
 456
 457 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 458                                      drm_i915_batchbuffer_t * batch,
 459                                      struct drm_clip_rect *cliprects)
 460 {
 461         int nbox = batch->num_cliprects;
 462         int i = 0, count;
 463
 464         if ((batch->start | batch->used) & 0x7) {
 465                 DRM_ERROR("alignment");
 466                 return -EINVAL;
 467         }
 468
 469         i915_kernel_lost_context(dev);
 470
 471         count = nbox ? nbox : 1;
 472
 473         for (i = 0; i < count; i++) {
 474                 if (i < nbox) {
 475                         int ret = i915_emit_box(dev, cliprects, i,
 476                                                 batch->DR1, batch->DR4);
 477                         if (ret)
 478                                 return ret;
 479                 }
 480
 481                 if (!IS_I830(dev) && !IS_845G(dev)) {
 482                         BEGIN_LP_RING(2);
 483                         if (IS_I965G(dev)) {
 484                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 485                                 OUT_RING(batch->start);
 486                         } else {
 487                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 488                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 489                         }
 490                         ADVANCE_LP_RING();
 491                 } else {
 492                         BEGIN_LP_RING(4);
 493                         OUT_RING(MI_BATCH_BUFFER);
 494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 495                         OUT_RING(batch->start + batch->used - 4);
 496                         OUT_RING(0);
 497                         ADVANCE_LP_RING();
 498                 }
 499         }
 500
 501
 502         if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
 503                 BEGIN_LP_RING(2);
 504                 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 505                 OUT_RING(MI_NOOP);
 506                 ADVANCE_LP_RING();
 507         }
 508         i915_emit_breadcrumb(dev);
 509
 510         return 0;
 511 }
 512
 513 static int i915_dispatch_flip(struct drm_device * dev)
 514 {
 515         drm_i915_private_t *dev_priv = dev->dev_private;
 516         struct drm_i915_master_private *master_priv =
 517                 dev->primary->master->driver_priv;
 518
 519         if (!master_priv->sarea_priv)
 520                 return -EINVAL;
 521
 522         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 523                           __func__,
 524                          dev_priv->current_page,
 525                          master_priv->sarea_priv->pf_current_page);
 526
 527         i915_kernel_lost_context(dev);
 528
 529         BEGIN_LP_RING(2);
 530         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 531         OUT_RING(0);
 532         ADVANCE_LP_RING();
 533
 534         BEGIN_LP_RING(6);
 535         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 536         OUT_RING(0);
 537         if (dev_priv->current_page == 0) {
 538                 OUT_RING(dev_priv->back_offset);
 539                 dev_priv->current_page = 1;
 540         } else {
 541                 OUT_RING(dev_priv->front_offset);
 542                 dev_priv->current_page = 0;
 543         }
 544         OUT_RING(0);
 545         ADVANCE_LP_RING();
 546
 547         BEGIN_LP_RING(2);
 548         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 549         OUT_RING(0);
 550         ADVANCE_LP_RING();
 551
 552         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 553
 554         BEGIN_LP_RING(4);
 555         OUT_RING(MI_STORE_DWORD_INDEX);
 556         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 557         OUT_RING(dev_priv->counter);
 558         OUT_RING(0);
 559         ADVANCE_LP_RING();
 560
 561         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 562         return 0;
 563 }
 564
 565 static int i915_quiescent(struct drm_device * dev)
 566 {
 567         drm_i915_private_t *dev_priv = dev->dev_private;
 568
 569         i915_kernel_lost_context(dev);
 570         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 571                                       dev_priv->render_ring.size - 8);
 572 }
 573
 574 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 575                             struct drm_file *file_priv)
 576 {
 577         int ret;
 578
 579         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 580
 581         mutex_lock(&dev->struct_mutex);
 582         ret = i915_quiescent(dev);
 583         mutex_unlock(&dev->struct_mutex);
 584
 585         return ret;
 586 }
 587
 588 static int i915_batchbuffer(struct drm_device *dev, void *data,
 589                             struct drm_file *file_priv)
 590 {
 591         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 592         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 593         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 594             master_priv->sarea_priv;
 595         drm_i915_batchbuffer_t *batch = data;
 596         int ret;
 597         struct drm_clip_rect *cliprects = NULL;
 598
 599         if (!dev_priv->allow_batchbuffer) {
 600                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 601                 return -EINVAL;
 602         }
 603
 604         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 605                         batch->start, batch->used, batch->num_cliprects);
 606
 607         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 608
 609         if (batch->num_cliprects < 0)
 610                 return -EINVAL;
 611
 612         if (batch->num_cliprects) {
 613                 cliprects = kcalloc(batch->num_cliprects,
 614                                     sizeof(struct drm_clip_rect),
 615                                     GFP_KERNEL);
 616                 if (cliprects == NULL)
 617                         return -ENOMEM;
 618
 619                 ret = copy_from_user(cliprects, batch->cliprects,
 620                                      batch->num_cliprects *
 621                                      sizeof(struct drm_clip_rect));
 622                 if (ret != 0) {
 623                         ret = -EFAULT;
 624                         goto fail_free;
 625                 }
 626         }
 627
 628         mutex_lock(&dev->struct_mutex);
 629         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 630         mutex_unlock(&dev->struct_mutex);
 631
 632         if (sarea_priv)
 633                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 634
 635 fail_free:
 636         kfree(cliprects);
 637
 638         return ret;
 639 }
 640
 641 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 642                           struct drm_file *file_priv)
 643 {
 644         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 645         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 646         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 647             master_priv->sarea_priv;
 648         drm_i915_cmdbuffer_t *cmdbuf = data;
 649         struct drm_clip_rect *cliprects = NULL;
 650         void *batch_data;
 651         int ret;
 652
 653         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 654                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 655
 656         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 657
 658         if (cmdbuf->num_cliprects < 0)
 659                 return -EINVAL;
 660
 661         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 662         if (batch_data == NULL)
 663                 return -ENOMEM;
 664
 665         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 666         if (ret != 0) {
 667                 ret = -EFAULT;
 668                 goto fail_batch_free;
 669         }
 670
 671         if (cmdbuf->num_cliprects) {
 672                 cliprects = kcalloc(cmdbuf->num_cliprects,
 673                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 674                 if (cliprects == NULL) {
 675                         ret = -ENOMEM;
 676                         goto fail_batch_free;
 677                 }
 678
 679                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 680                                      cmdbuf->num_cliprects *
 681                                      sizeof(struct drm_clip_rect));
 682                 if (ret != 0) {
 683                         ret = -EFAULT;
 684                         goto fail_clip_free;
 685                 }
 686         }
 687
 688         mutex_lock(&dev->struct_mutex);
 689         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 690         mutex_unlock(&dev->struct_mutex);
 691         if (ret) {
 692                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 693                 goto fail_clip_free;
 694         }
 695
 696         if (sarea_priv)
 697                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 698
 699 fail_clip_free:
 700         kfree(cliprects);
 701 fail_batch_free:
 702         kfree(batch_data);
 703
 704         return ret;
 705 }
 706
 707 static int i915_flip_bufs(struct drm_device *dev, void *data,
 708                           struct drm_file *file_priv)
 709 {
 710         int ret;
 711
 712         DRM_DEBUG_DRIVER("%s\n", __func__);
 713
 714         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 715
 716         mutex_lock(&dev->struct_mutex);
 717         ret = i915_dispatch_flip(dev);
 718         mutex_unlock(&dev->struct_mutex);
 719
 720         return ret;
 721 }
 722
 723 static int i915_getparam(struct drm_device *dev, void *data,
 724                          struct drm_file *file_priv)
 725 {
 726         drm_i915_private_t *dev_priv = dev->dev_private;
 727         drm_i915_getparam_t *param = data;
 728         int value;
 729
 730         if (!dev_priv) {
 731                 DRM_ERROR("called with no initialization\n");
 732                 return -EINVAL;
 733         }
 734
 735         switch (param->param) {
 736         case I915_PARAM_IRQ_ACTIVE:
 737                 value = dev->pdev->irq ? 1 : 0;
 738                 break;
 739         case I915_PARAM_ALLOW_BATCHBUFFER:
 740                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 741                 break;
 742         case I915_PARAM_LAST_DISPATCH:
 743                 value = READ_BREADCRUMB(dev_priv);
 744                 break;
 745         case I915_PARAM_CHIPSET_ID:
 746                 value = dev->pci_device;
 747                 break;
 748         case I915_PARAM_HAS_GEM:
 749                 value = dev_priv->has_gem;
 750                 break;
 751         case I915_PARAM_NUM_FENCES_AVAIL:
 752                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 753                 break;
 754         case I915_PARAM_HAS_OVERLAY:
 755                 value = dev_priv->overlay ? 1 : 0;
 756                 break;
 757         case I915_PARAM_HAS_PAGEFLIPPING:
 758                 value = 1;
 759                 break;
 760         case I915_PARAM_HAS_EXECBUF2:
 761                 /* depends on GEM */
 762                 value = dev_priv->has_gem;
 763                 break;
 764         case I915_PARAM_HAS_BSD:
 765                 value = HAS_BSD(dev);
 766                 break;
 767         default:
 768                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 769                                  param->param);
 770                 return -EINVAL;
 771         }
 772
 773         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 774                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 775                 return -EFAULT;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int i915_setparam(struct drm_device *dev, void *data,
 782                          struct drm_file *file_priv)
 783 {
 784         drm_i915_private_t *dev_priv = dev->dev_private;
 785         drm_i915_setparam_t *param = data;
 786
 787         if (!dev_priv) {
 788                 DRM_ERROR("called with no initialization\n");
 789                 return -EINVAL;
 790         }
 791
 792         switch (param->param) {
 793         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 794                 break;
 795         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 796                 dev_priv->tex_lru_log_granularity = param->value;
 797                 break;
 798         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 799                 dev_priv->allow_batchbuffer = param->value;
 800                 break;
 801         case I915_SETPARAM_NUM_USED_FENCES:
 802                 if (param->value > dev_priv->num_fence_regs ||
 803                     param->value < 0)
 804                         return -EINVAL;
 805                 /* Userspace can use first N regs */
 806                 dev_priv->fence_reg_start = param->value;
 807                 break;
 808         default:
 809                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 810                                         param->param);
 811                 return -EINVAL;
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int i915_set_status_page(struct drm_device *dev, void *data,
 818                                 struct drm_file *file_priv)
 819 {
 820         drm_i915_private_t *dev_priv = dev->dev_private;
 821         drm_i915_hws_addr_t *hws = data;
 822         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 823
 824         if (!I915_NEED_GFX_HWS(dev))
 825                 return -EINVAL;
 826
 827         if (!dev_priv) {
 828                 DRM_ERROR("called with no initialization\n");
 829                 return -EINVAL;
 830         }
 831
 832         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 833                 WARN(1, "tried to set status page when mode setting active\n");
 834                 return 0;
 835         }
 836
 837         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 838
 839         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 840
 841         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 842         dev_priv->hws_map.size = 4*1024;
 843         dev_priv->hws_map.type = 0;
 844         dev_priv->hws_map.flags = 0;
 845         dev_priv->hws_map.mtrr = 0;
 846
 847         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 848         if (dev_priv->hws_map.handle == NULL) {
 849                 i915_dma_cleanup(dev);
 850                 ring->status_page.gfx_addr = 0;
 851                 DRM_ERROR("can not ioremap virtual address for"
 852                                 " G33 hw status page\n");
 853                 return -ENOMEM;
 854         }
 855         ring->status_page.page_addr = dev_priv->hws_map.handle;
 856         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 857         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 858
 859         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 860                          ring->status_page.gfx_addr);
 861         DRM_DEBUG_DRIVER("load hws at %p\n",
 862                          ring->status_page.page_addr);
 863         return 0;
 864 }
 865
 866 static int i915_get_bridge_dev(struct drm_device *dev)
 867 {
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 871         if (!dev_priv->bridge_dev) {
 872                 DRM_ERROR("bridge device not found\n");
 873                 return -1;
 874         }
 875         return 0;
 876 }
 877
 878 #define MCHBAR_I915 0x44
 879 #define MCHBAR_I965 0x48
 880 #define MCHBAR_SIZE (4*4096)
 881
 882 #define DEVEN_REG 0x54
 883 #define   DEVEN_MCHBAR_EN (1 << 28)
 884
 885 /* Allocate space for the MCH regs if needed, return nonzero on error */
 886 static int
 887 intel_alloc_mchbar_resource(struct drm_device *dev)
 888 {
 889         drm_i915_private_t *dev_priv = dev->dev_private;
 890         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 891         u32 temp_lo, temp_hi = 0;
 892         u64 mchbar_addr;
 893         int ret;
 894
 895         if (IS_I965G(dev))
 896                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 897         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 898         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 899
 900         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 901 #ifdef CONFIG_PNP
 902         if (mchbar_addr &&
 903             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 904                 return 0;
 905 #endif
 906
 907         /* Get some space for it */
 908         dev_priv->mch_res.name = "i915 MCHBAR";
 909         dev_priv->mch_res.flags = IORESOURCE_MEM;
 910         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 911                                      &dev_priv->mch_res,
 912                                      MCHBAR_SIZE, MCHBAR_SIZE,
 913                                      PCIBIOS_MIN_MEM,
 914                                      0, pcibios_align_resource,
 915                                      dev_priv->bridge_dev);
 916         if (ret) {
 917                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 918                 dev_priv->mch_res.start = 0;
 919                 return ret;
 920         }
 921
 922         if (IS_I965G(dev))
 923                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 924                                        upper_32_bits(dev_priv->mch_res.start));
 925
 926         pci_write_config_dword(dev_priv->bridge_dev, reg,
 927                                lower_32_bits(dev_priv->mch_res.start));
 928         return 0;
 929 }
 930
 931 /* Setup MCHBAR if possible, return true if we should disable it again */
 932 static void
 933 intel_setup_mchbar(struct drm_device *dev)
 934 {
 935         drm_i915_private_t *dev_priv = dev->dev_private;
 936         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 937         u32 temp;
 938         bool enabled;
 939
 940         dev_priv->mchbar_need_disable = false;
 941
 942         if (IS_I915G(dev) || IS_I915GM(dev)) {
 943                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 944                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 945         } else {
 946                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 947                 enabled = temp & 1;
 948         }
 949
 950         /* If it's already enabled, don't have to do anything */
 951         if (enabled)
 952                 return;
 953
 954         if (intel_alloc_mchbar_resource(dev))
 955                 return;
 956
 957         dev_priv->mchbar_need_disable = true;
 958
 959         /* Space is allocated or reserved, so enable it. */
 960         if (IS_I915G(dev) || IS_I915GM(dev)) {
 961                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 962                                        temp | DEVEN_MCHBAR_EN);
 963         } else {
 964                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 965                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 966         }
 967 }
 968
 969 static void
 970 intel_teardown_mchbar(struct drm_device *dev)
 971 {
 972         drm_i915_private_t *dev_priv = dev->dev_private;
 973         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 974         u32 temp;
 975
 976         if (dev_priv->mchbar_need_disable) {
 977                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 978                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 979                         temp &= ~DEVEN_MCHBAR_EN;
 980                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 981                 } else {
 982                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 983                         temp &= ~1;
 984                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 985                 }
 986         }
 987
 988         if (dev_priv->mch_res.start)
 989                 release_resource(&dev_priv->mch_res);
 990 }
 991
 992 /**
 993  * i915_probe_agp - get AGP bootup configuration
 994  * @pdev: PCI device
 995  * @aperture_size: returns AGP aperture configured size
 996  * @preallocated_size: returns size of BIOS preallocated AGP space
 997  *
 998  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 999  * some RAM for the framebuffer at early boot.  This code figures out
1000  * how much was set aside so we can use it for our own purposes.
1001  */
1002 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1003                           uint32_t *preallocated_size)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         u16 tmp = 0;
1007         unsigned long overhead;
1008         unsigned long stolen;
1009
1010         /* Get the fb aperture size and "stolen" memory amount. */
1011         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1012
1013         *aperture_size = 1024 * 1024;
1014         *preallocated_size = 1024 * 1024;
1015
1016         switch (dev->pdev->device) {
1017         case PCI_DEVICE_ID_INTEL_82830_CGC:
1018         case PCI_DEVICE_ID_INTEL_82845G_IG:
1019         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1020         case PCI_DEVICE_ID_INTEL_82865_IG:
1021                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1022                         *aperture_size *= 64;
1023                 else
1024                         *aperture_size *= 128;
1025                 break;
1026         default:
1027                 /* 9xx supports large sizes, just look at the length */
1028                 *aperture_size = pci_resource_len(dev->pdev, 2);
1029                 break;
1030         }
1031
1032         /*
1033          * Some of the preallocated space is taken by the GTT
1034          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1035          */
1036         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1037                 overhead = 4096;
1038         else
1039                 overhead = (*aperture_size / 1024) + 4096;
1040
1041         if (IS_GEN6(dev)) {
1042                 /* SNB has memory control reg at 0x50.w */
1043                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1044
1045                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1046                 case INTEL_855_GMCH_GMS_DISABLED:
1047                         DRM_ERROR("video memory is disabled\n");
1048                         return -1;
1049                 case SNB_GMCH_GMS_STOLEN_32M:
1050                         stolen = 32 * 1024 * 1024;
1051                         break;
1052                 case SNB_GMCH_GMS_STOLEN_64M:
1053                         stolen = 64 * 1024 * 1024;
1054                         break;
1055                 case SNB_GMCH_GMS_STOLEN_96M:
1056                         stolen = 96 * 1024 * 1024;
1057                         break;
1058                 case SNB_GMCH_GMS_STOLEN_128M:
1059                         stolen = 128 * 1024 * 1024;
1060                         break;
1061                 case SNB_GMCH_GMS_STOLEN_160M:
1062                         stolen = 160 * 1024 * 1024;
1063                         break;
1064                 case SNB_GMCH_GMS_STOLEN_192M:
1065                         stolen = 192 * 1024 * 1024;
1066                         break;
1067                 case SNB_GMCH_GMS_STOLEN_224M:
1068                         stolen = 224 * 1024 * 1024;
1069                         break;
1070                 case SNB_GMCH_GMS_STOLEN_256M:
1071                         stolen = 256 * 1024 * 1024;
1072                         break;
1073                 case SNB_GMCH_GMS_STOLEN_288M:
1074                         stolen = 288 * 1024 * 1024;
1075                         break;
1076                 case SNB_GMCH_GMS_STOLEN_320M:
1077                         stolen = 320 * 1024 * 1024;
1078                         break;
1079                 case SNB_GMCH_GMS_STOLEN_352M:
1080                         stolen = 352 * 1024 * 1024;
1081                         break;
1082                 case SNB_GMCH_GMS_STOLEN_384M:
1083                         stolen = 384 * 1024 * 1024;
1084                         break;
1085                 case SNB_GMCH_GMS_STOLEN_416M:
1086                         stolen = 416 * 1024 * 1024;
1087                         break;
1088                 case SNB_GMCH_GMS_STOLEN_448M:
1089                         stolen = 448 * 1024 * 1024;
1090                         break;
1091                 case SNB_GMCH_GMS_STOLEN_480M:
1092                         stolen = 480 * 1024 * 1024;
1093                         break;
1094                 case SNB_GMCH_GMS_STOLEN_512M:
1095                         stolen = 512 * 1024 * 1024;
1096                         break;
1097                 default:
1098                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1099                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1100                         return -1;
1101                 }
1102         } else {
1103                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1104                 case INTEL_855_GMCH_GMS_DISABLED:
1105                         DRM_ERROR("video memory is disabled\n");
1106                         return -1;
1107                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1108                         stolen = 1 * 1024 * 1024;
1109                         break;
1110                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1111                         stolen = 4 * 1024 * 1024;
1112                         break;
1113                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1114                         stolen = 8 * 1024 * 1024;
1115                         break;
1116                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1117                         stolen = 16 * 1024 * 1024;
1118                         break;
1119                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1120                         stolen = 32 * 1024 * 1024;
1121                         break;
1122                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1123                         stolen = 48 * 1024 * 1024;
1124                         break;
1125                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1126                         stolen = 64 * 1024 * 1024;
1127                         break;
1128                 case INTEL_GMCH_GMS_STOLEN_128M:
1129                         stolen = 128 * 1024 * 1024;
1130                         break;
1131                 case INTEL_GMCH_GMS_STOLEN_256M:
1132                         stolen = 256 * 1024 * 1024;
1133                         break;
1134                 case INTEL_GMCH_GMS_STOLEN_96M:
1135                         stolen = 96 * 1024 * 1024;
1136                         break;
1137                 case INTEL_GMCH_GMS_STOLEN_160M:
1138                         stolen = 160 * 1024 * 1024;
1139                         break;
1140                 case INTEL_GMCH_GMS_STOLEN_224M:
1141                         stolen = 224 * 1024 * 1024;
1142                         break;
1143                 case INTEL_GMCH_GMS_STOLEN_352M:
1144                         stolen = 352 * 1024 * 1024;
1145                         break;
1146                 default:
1147                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1148                                   tmp & INTEL_GMCH_GMS_MASK);
1149                         return -1;
1150                 }
1151         }
1152
1153         *preallocated_size = stolen - overhead;
1154
1155         return 0;
1156 }
1157
1158 #define PTE_ADDRESS_MASK                0xfffff000
1159 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1160 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1161 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1162 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1163 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1164 #define PTE_VALID                       (1 << 0)
1165
1166 /**
1167  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1168  * @dev: drm device
1169  * @gtt_addr: address to translate
1170  *
1171  * Some chip functions require allocations from stolen space but need the
1172  * physical address of the memory in question.  We use this routine
1173  * to get a physical address suitable for register programming from a given
1174  * GTT address.
1175  */
1176 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1177                                       unsigned long gtt_addr)
1178 {
1179         unsigned long *gtt;
1180         unsigned long entry, phys;
1181         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1182         int gtt_offset, gtt_size;
1183
1184         if (IS_I965G(dev)) {
1185                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1186                         gtt_offset = 2*1024*1024;
1187                         gtt_size = 2*1024*1024;
1188                 } else {
1189                         gtt_offset = 512*1024;
1190                         gtt_size = 512*1024;
1191                 }
1192         } else {
1193                 gtt_bar = 3;
1194                 gtt_offset = 0;
1195                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1196         }
1197
1198         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1199                          gtt_size);
1200         if (!gtt) {
1201                 DRM_ERROR("ioremap of GTT failed\n");
1202                 return 0;
1203         }
1204
1205         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1206
1207         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1208
1209         /* Mask out these reserved bits on this hardware. */
1210         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1211             IS_I945G(dev) || IS_I945GM(dev)) {
1212                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1213         }
1214
1215         /* If it's not a mapping type we know, then bail. */
1216         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1217             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1218                 iounmap(gtt);
1219                 return 0;
1220         }
1221
1222         if (!(entry & PTE_VALID)) {
1223                 DRM_ERROR("bad GTT entry in stolen space\n");
1224                 iounmap(gtt);
1225                 return 0;
1226         }
1227
1228         iounmap(gtt);
1229
1230         phys =(entry & PTE_ADDRESS_MASK) |
1231                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1232
1233         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1234
1235         return phys;
1236 }
1237
1238 static void i915_warn_stolen(struct drm_device *dev)
1239 {
1240         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1241         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1242 }
1243
1244 static void i915_setup_compression(struct drm_device *dev, int size)
1245 {
1246         struct drm_i915_private *dev_priv = dev->dev_private;
1247         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1248         unsigned long cfb_base;
1249         unsigned long ll_base = 0;
1250
1251         /* Leave 1M for line length buffer & misc. */
1252         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1253         if (!compressed_fb) {
1254                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1255                 i915_warn_stolen(dev);
1256                 return;
1257         }
1258
1259         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1260         if (!compressed_fb) {
1261                 i915_warn_stolen(dev);
1262                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1263                 return;
1264         }
1265
1266         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1267         if (!cfb_base) {
1268                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1269                 drm_mm_put_block(compressed_fb);
1270         }
1271
1272         if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1273                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1274                                                     4096, 0);
1275                 if (!compressed_llb) {
1276                         i915_warn_stolen(dev);
1277                         return;
1278                 }
1279
1280                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1281                 if (!compressed_llb) {
1282                         i915_warn_stolen(dev);
1283                         return;
1284                 }
1285
1286                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1287                 if (!ll_base) {
1288                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1289                         drm_mm_put_block(compressed_fb);
1290                         drm_mm_put_block(compressed_llb);
1291                 }
1292         }
1293
1294         dev_priv->cfb_size = size;
1295
1296         intel_disable_fbc(dev);
1297         dev_priv->compressed_fb = compressed_fb;
1298         if (IS_IRONLAKE_M(dev))
1299                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1300         else if (IS_GM45(dev)) {
1301                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1302         } else {
1303                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1304                 I915_WRITE(FBC_LL_BASE, ll_base);
1305                 dev_priv->compressed_llb = compressed_llb;
1306         }
1307
1308         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1309                   ll_base, size >> 20);
1310 }
1311
1312 static void i915_cleanup_compression(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         drm_mm_put_block(dev_priv->compressed_fb);
1317         if (dev_priv->compressed_llb)
1318                 drm_mm_put_block(dev_priv->compressed_llb);
1319 }
1320
1321 /* true = enable decode, false = disable decoder */
1322 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1323 {
1324         struct drm_device *dev = cookie;
1325
1326         intel_modeset_vga_set_state(dev, state);
1327         if (state)
1328                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1329                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1330         else
1331                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1332 }
1333
1334 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1335 {
1336         struct drm_device *dev = pci_get_drvdata(pdev);
1337         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1338         if (state == VGA_SWITCHEROO_ON) {
1339                 printk(KERN_INFO "i915: switched on\n");
1340                 /* i915 resume handler doesn't set to D0 */
1341                 pci_set_power_state(dev->pdev, PCI_D0);
1342                 i915_resume(dev);
1343                 drm_kms_helper_poll_enable(dev);
1344         } else {
1345                 printk(KERN_ERR "i915: switched off\n");
1346                 drm_kms_helper_poll_disable(dev);
1347                 i915_suspend(dev, pmm);
1348         }
1349 }
1350
1351 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1352 {
1353         struct drm_device *dev = pci_get_drvdata(pdev);
1354         bool can_switch;
1355
1356         spin_lock(&dev->count_lock);
1357         can_switch = (dev->open_count == 0);
1358         spin_unlock(&dev->count_lock);
1359         return can_switch;
1360 }
1361
1362 static int i915_load_modeset_init(struct drm_device *dev,
1363                                   unsigned long prealloc_size,
1364                                   unsigned long agp_size)
1365 {
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         int ret = 0;
1368
1369         /* Basic memrange allocator for stolen space (aka vram) */
1370         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1371         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1372
1373         /* We're off and running w/KMS */
1374         dev_priv->mm.suspended = 0;
1375
1376         /* Let GEM Manage from end of prealloc space to end of aperture.
1377          *
1378          * However, leave one page at the end still bound to the scratch page.
1379          * There are a number of places where the hardware apparently
1380          * prefetches past the end of the object, and we've seen multiple
1381          * hangs with the GPU head pointer stuck in a batchbuffer bound
1382          * at the last page of the aperture.  One page should be enough to
1383          * keep any prefetching inside of the aperture.
1384          */
1385         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1386
1387         mutex_lock(&dev->struct_mutex);
1388         ret = i915_gem_init_ringbuffer(dev);
1389         mutex_unlock(&dev->struct_mutex);
1390         if (ret)
1391                 goto out;
1392
1393         /* Try to set up FBC with a reasonable compressed buffer size */
1394         if (I915_HAS_FBC(dev) && i915_powersave) {
1395                 int cfb_size;
1396
1397                 /* Try to get an 8M buffer... */
1398                 if (prealloc_size > (9*1024*1024))
1399                         cfb_size = 8*1024*1024;
1400                 else /* fall back to 7/8 of the stolen space */
1401                         cfb_size = prealloc_size * 7 / 8;
1402                 i915_setup_compression(dev, cfb_size);
1403         }
1404
1405         /* Allow hardware batchbuffers unless told otherwise.
1406          */
1407         dev_priv->allow_batchbuffer = 1;
1408
1409         ret = intel_init_bios(dev);
1410         if (ret)
1411                 DRM_INFO("failed to find VBIOS tables\n");
1412
1413         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1414         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1415         if (ret)
1416                 goto cleanup_ringbuffer;
1417
1418         ret = vga_switcheroo_register_client(dev->pdev,
1419                                              i915_switcheroo_set_state,
1420                                              i915_switcheroo_can_switch);
1421         if (ret)
1422                 goto cleanup_vga_client;
1423
1424         /* IIR "flip pending" bit means done if this bit is set */
1425         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1426                 dev_priv->flip_pending_is_done = true;
1427
1428         intel_modeset_init(dev);
1429
1430         ret = drm_irq_install(dev);
1431         if (ret)
1432                 goto cleanup_vga_switcheroo;
1433
1434         /* Always safe in the mode setting case. */
1435         /* FIXME: do pre/post-mode set stuff in core KMS code */
1436         dev->vblank_disable_allowed = 1;
1437
1438         ret = intel_fbdev_init(dev);
1439         if (ret)
1440                 goto cleanup_irq;
1441
1442         drm_kms_helper_poll_init(dev);
1443         return 0;
1444
1445 cleanup_irq:
1446         drm_irq_uninstall(dev);
1447 cleanup_vga_switcheroo:
1448         vga_switcheroo_unregister_client(dev->pdev);
1449 cleanup_vga_client:
1450         vga_client_register(dev->pdev, NULL, NULL, NULL);
1451 cleanup_ringbuffer:
1452         mutex_lock(&dev->struct_mutex);
1453         i915_gem_cleanup_ringbuffer(dev);
1454         mutex_unlock(&dev->struct_mutex);
1455 out:
1456         return ret;
1457 }
1458
1459 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1460 {
1461         struct drm_i915_master_private *master_priv;
1462
1463         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1464         if (!master_priv)
1465                 return -ENOMEM;
1466
1467         master->driver_priv = master_priv;
1468         return 0;
1469 }
1470
1471 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1472 {
1473         struct drm_i915_master_private *master_priv = master->driver_priv;
1474
1475         if (!master_priv)
1476                 return;
1477
1478         kfree(master_priv);
1479
1480         master->driver_priv = NULL;
1481 }
1482
1483 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1484 {
1485         drm_i915_private_t *dev_priv = dev->dev_private;
1486         u32 tmp;
1487
1488         tmp = I915_READ(CLKCFG);
1489
1490         switch (tmp & CLKCFG_FSB_MASK) {
1491         case CLKCFG_FSB_533:
1492                 dev_priv->fsb_freq = 533; /* 133*4 */
1493                 break;
1494         case CLKCFG_FSB_800:
1495                 dev_priv->fsb_freq = 800; /* 200*4 */
1496                 break;
1497         case CLKCFG_FSB_667:
1498                 dev_priv->fsb_freq =  667; /* 167*4 */
1499                 break;
1500         case CLKCFG_FSB_400:
1501                 dev_priv->fsb_freq = 400; /* 100*4 */
1502                 break;
1503         }
1504
1505         switch (tmp & CLKCFG_MEM_MASK) {
1506         case CLKCFG_MEM_533:
1507                 dev_priv->mem_freq = 533;
1508                 break;
1509         case CLKCFG_MEM_667:
1510                 dev_priv->mem_freq = 667;
1511                 break;
1512         case CLKCFG_MEM_800:
1513                 dev_priv->mem_freq = 800;
1514                 break;
1515         }
1516
1517         /* detect pineview DDR3 setting */
1518         tmp = I915_READ(CSHRDDR3CTL);
1519         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1520 }
1521
1522 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1523 {
1524         drm_i915_private_t *dev_priv = dev->dev_private;
1525         u16 ddrpll, csipll;
1526
1527         ddrpll = I915_READ16(DDRMPLL1);
1528         csipll = I915_READ16(CSIPLL0);
1529
1530         switch (ddrpll & 0xff) {
1531         case 0xc:
1532                 dev_priv->mem_freq = 800;
1533                 break;
1534         case 0x10:
1535                 dev_priv->mem_freq = 1066;
1536                 break;
1537         case 0x14:
1538                 dev_priv->mem_freq = 1333;
1539                 break;
1540         case 0x18:
1541                 dev_priv->mem_freq = 1600;
1542                 break;
1543         default:
1544                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1545                                  ddrpll & 0xff);
1546                 dev_priv->mem_freq = 0;
1547                 break;
1548         }
1549
1550         dev_priv->r_t = dev_priv->mem_freq;
1551
1552         switch (csipll & 0x3ff) {
1553         case 0x00c:
1554                 dev_priv->fsb_freq = 3200;
1555                 break;
1556         case 0x00e:
1557                 dev_priv->fsb_freq = 3733;
1558                 break;
1559         case 0x010:
1560                 dev_priv->fsb_freq = 4266;
1561                 break;
1562         case 0x012:
1563                 dev_priv->fsb_freq = 4800;
1564                 break;
1565         case 0x014:
1566                 dev_priv->fsb_freq = 5333;
1567                 break;
1568         case 0x016:
1569                 dev_priv->fsb_freq = 5866;
1570                 break;
1571         case 0x018:
1572                 dev_priv->fsb_freq = 6400;
1573                 break;
1574         default:
1575                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1576                                  csipll & 0x3ff);
1577                 dev_priv->fsb_freq = 0;
1578                 break;
1579         }
1580
1581         if (dev_priv->fsb_freq == 3200) {
1582                 dev_priv->c_m = 0;
1583         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1584                 dev_priv->c_m = 1;
1585         } else {
1586                 dev_priv->c_m = 2;
1587         }
1588 }
1589
1590 struct v_table {
1591         u8 vid;
1592         unsigned long vd; /* in .1 mil */
1593         unsigned long vm; /* in .1 mil */
1594         u8 pvid;
1595 };
1596
1597 static struct v_table v_table[] = {
1598         { 0, 16125, 15000, 0x7f, },
1599         { 1, 16000, 14875, 0x7e, },
1600         { 2, 15875, 14750, 0x7d, },
1601         { 3, 15750, 14625, 0x7c, },
1602         { 4, 15625, 14500, 0x7b, },
1603         { 5, 15500, 14375, 0x7a, },
1604         { 6, 15375, 14250, 0x79, },
1605         { 7, 15250, 14125, 0x78, },
1606         { 8, 15125, 14000, 0x77, },
1607         { 9, 15000, 13875, 0x76, },
1608         { 10, 14875, 13750, 0x75, },
1609         { 11, 14750, 13625, 0x74, },
1610         { 12, 14625, 13500, 0x73, },
1611         { 13, 14500, 13375, 0x72, },
1612         { 14, 14375, 13250, 0x71, },
1613         { 15, 14250, 13125, 0x70, },
1614         { 16, 14125, 13000, 0x6f, },
1615         { 17, 14000, 12875, 0x6e, },
1616         { 18, 13875, 12750, 0x6d, },
1617         { 19, 13750, 12625, 0x6c, },
1618         { 20, 13625, 12500, 0x6b, },
1619         { 21, 13500, 12375, 0x6a, },
1620         { 22, 13375, 12250, 0x69, },
1621         { 23, 13250, 12125, 0x68, },
1622         { 24, 13125, 12000, 0x67, },
1623         { 25, 13000, 11875, 0x66, },
1624         { 26, 12875, 11750, 0x65, },
1625         { 27, 12750, 11625, 0x64, },
1626         { 28, 12625, 11500, 0x63, },
1627         { 29, 12500, 11375, 0x62, },
1628         { 30, 12375, 11250, 0x61, },
1629         { 31, 12250, 11125, 0x60, },
1630         { 32, 12125, 11000, 0x5f, },
1631         { 33, 12000, 10875, 0x5e, },
1632         { 34, 11875, 10750, 0x5d, },
1633         { 35, 11750, 10625, 0x5c, },
1634         { 36, 11625, 10500, 0x5b, },
1635         { 37, 11500, 10375, 0x5a, },
1636         { 38, 11375, 10250, 0x59, },
1637         { 39, 11250, 10125, 0x58, },
1638         { 40, 11125, 10000, 0x57, },
1639         { 41, 11000, 9875, 0x56, },
1640         { 42, 10875, 9750, 0x55, },
1641         { 43, 10750, 9625, 0x54, },
1642         { 44, 10625, 9500, 0x53, },
1643         { 45, 10500, 9375, 0x52, },
1644         { 46, 10375, 9250, 0x51, },
1645         { 47, 10250, 9125, 0x50, },
1646         { 48, 10125, 9000, 0x4f, },
1647         { 49, 10000, 8875, 0x4e, },
1648         { 50, 9875, 8750, 0x4d, },
1649         { 51, 9750, 8625, 0x4c, },
1650         { 52, 9625, 8500, 0x4b, },
1651         { 53, 9500, 8375, 0x4a, },
1652         { 54, 9375, 8250, 0x49, },
1653         { 55, 9250, 8125, 0x48, },
1654         { 56, 9125, 8000, 0x47, },
1655         { 57, 9000, 7875, 0x46, },
1656         { 58, 8875, 7750, 0x45, },
1657         { 59, 8750, 7625, 0x44, },
1658         { 60, 8625, 7500, 0x43, },
1659         { 61, 8500, 7375, 0x42, },
1660         { 62, 8375, 7250, 0x41, },
1661         { 63, 8250, 7125, 0x40, },
1662         { 64, 8125, 7000, 0x3f, },
1663         { 65, 8000, 6875, 0x3e, },
1664         { 66, 7875, 6750, 0x3d, },
1665         { 67, 7750, 6625, 0x3c, },
1666         { 68, 7625, 6500, 0x3b, },
1667         { 69, 7500, 6375, 0x3a, },
1668         { 70, 7375, 6250, 0x39, },
1669         { 71, 7250, 6125, 0x38, },
1670         { 72, 7125, 6000, 0x37, },
1671         { 73, 7000, 5875, 0x36, },
1672         { 74, 6875, 5750, 0x35, },
1673         { 75, 6750, 5625, 0x34, },
1674         { 76, 6625, 5500, 0x33, },
1675         { 77, 6500, 5375, 0x32, },
1676         { 78, 6375, 5250, 0x31, },
1677         { 79, 6250, 5125, 0x30, },
1678         { 80, 6125, 5000, 0x2f, },
1679         { 81, 6000, 4875, 0x2e, },
1680         { 82, 5875, 4750, 0x2d, },
1681         { 83, 5750, 4625, 0x2c, },
1682         { 84, 5625, 4500, 0x2b, },
1683         { 85, 5500, 4375, 0x2a, },
1684         { 86, 5375, 4250, 0x29, },
1685         { 87, 5250, 4125, 0x28, },
1686         { 88, 5125, 4000, 0x27, },
1687         { 89, 5000, 3875, 0x26, },
1688         { 90, 4875, 3750, 0x25, },
1689         { 91, 4750, 3625, 0x24, },
1690         { 92, 4625, 3500, 0x23, },
1691         { 93, 4500, 3375, 0x22, },
1692         { 94, 4375, 3250, 0x21, },
1693         { 95, 4250, 3125, 0x20, },
1694         { 96, 4125, 3000, 0x1f, },
1695         { 97, 4125, 3000, 0x1e, },
1696         { 98, 4125, 3000, 0x1d, },
1697         { 99, 4125, 3000, 0x1c, },
1698         { 100, 4125, 3000, 0x1b, },
1699         { 101, 4125, 3000, 0x1a, },
1700         { 102, 4125, 3000, 0x19, },
1701         { 103, 4125, 3000, 0x18, },
1702         { 104, 4125, 3000, 0x17, },
1703         { 105, 4125, 3000, 0x16, },
1704         { 106, 4125, 3000, 0x15, },
1705         { 107, 4125, 3000, 0x14, },
1706         { 108, 4125, 3000, 0x13, },
1707         { 109, 4125, 3000, 0x12, },
1708         { 110, 4125, 3000, 0x11, },
1709         { 111, 4125, 3000, 0x10, },
1710         { 112, 4125, 3000, 0x0f, },
1711         { 113, 4125, 3000, 0x0e, },
1712         { 114, 4125, 3000, 0x0d, },
1713         { 115, 4125, 3000, 0x0c, },
1714         { 116, 4125, 3000, 0x0b, },
1715         { 117, 4125, 3000, 0x0a, },
1716         { 118, 4125, 3000, 0x09, },
1717         { 119, 4125, 3000, 0x08, },
1718         { 120, 1125, 0, 0x07, },
1719         { 121, 1000, 0, 0x06, },
1720         { 122, 875, 0, 0x05, },
1721         { 123, 750, 0, 0x04, },
1722         { 124, 625, 0, 0x03, },
1723         { 125, 500, 0, 0x02, },
1724         { 126, 375, 0, 0x01, },
1725         { 127, 0, 0, 0x00, },
1726 };
1727
1728 struct cparams {
1729         int i;
1730         int t;
1731         int m;
1732         int c;
1733 };
1734
1735 static struct cparams cparams[] = {
1736         { 1, 1333, 301, 28664 },
1737         { 1, 1066, 294, 24460 },
1738         { 1, 800, 294, 25192 },
1739         { 0, 1333, 276, 27605 },
1740         { 0, 1066, 276, 27605 },
1741         { 0, 800, 231, 23784 },
1742 };
1743
1744 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1745 {
1746         u64 total_count, diff, ret;
1747         u32 count1, count2, count3, m = 0, c = 0;
1748         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1749         int i;
1750
1751         diff1 = now - dev_priv->last_time1;
1752
1753         count1 = I915_READ(DMIEC);
1754         count2 = I915_READ(DDREC);
1755         count3 = I915_READ(CSIEC);
1756
1757         total_count = count1 + count2 + count3;
1758
1759         /* FIXME: handle per-counter overflow */
1760         if (total_count < dev_priv->last_count1) {
1761                 diff = ~0UL - dev_priv->last_count1;
1762                 diff += total_count;
1763         } else {
1764                 diff = total_count - dev_priv->last_count1;
1765         }
1766
1767         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1768                 if (cparams[i].i == dev_priv->c_m &&
1769                     cparams[i].t == dev_priv->r_t) {
1770                         m = cparams[i].m;
1771                         c = cparams[i].c;
1772                         break;
1773                 }
1774         }
1775
1776         div_u64(diff, diff1);
1777         ret = ((m * diff) + c);
1778         div_u64(ret, 10);
1779
1780         dev_priv->last_count1 = total_count;
1781         dev_priv->last_time1 = now;
1782
1783         return ret;
1784 }
1785
1786 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1787 {
1788         unsigned long m, x, b;
1789         u32 tsfs;
1790
1791         tsfs = I915_READ(TSFS);
1792
1793         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1794         x = I915_READ8(TR1);
1795
1796         b = tsfs & TSFS_INTR_MASK;
1797
1798         return ((m * x) / 127) - b;
1799 }
1800
1801 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1802 {
1803         unsigned long val = 0;
1804         int i;
1805
1806         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1807                 if (v_table[i].pvid == pxvid) {
1808                         if (IS_MOBILE(dev_priv->dev))
1809                                 val = v_table[i].vm;
1810                         else
1811                                 val = v_table[i].vd;
1812                 }
1813         }
1814
1815         return val;
1816 }
1817
1818 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1819 {
1820         struct timespec now, diff1;
1821         u64 diff;
1822         unsigned long diffms;
1823         u32 count;
1824
1825         getrawmonotonic(&now);
1826         diff1 = timespec_sub(now, dev_priv->last_time2);
1827
1828         /* Don't divide by 0 */
1829         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1830         if (!diffms)
1831                 return;
1832
1833         count = I915_READ(GFXEC);
1834
1835         if (count < dev_priv->last_count2) {
1836                 diff = ~0UL - dev_priv->last_count2;
1837                 diff += count;
1838         } else {
1839                 diff = count - dev_priv->last_count2;
1840         }
1841
1842         dev_priv->last_count2 = count;
1843         dev_priv->last_time2 = now;
1844
1845         /* More magic constants... */
1846         diff = diff * 1181;
1847         div_u64(diff, diffms * 10);
1848         dev_priv->gfx_power = diff;
1849 }
1850
1851 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1852 {
1853         unsigned long t, corr, state1, corr2, state2;
1854         u32 pxvid, ext_v;
1855
1856         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1857         pxvid = (pxvid >> 24) & 0x7f;
1858         ext_v = pvid_to_extvid(dev_priv, pxvid);
1859
1860         state1 = ext_v;
1861
1862         t = i915_mch_val(dev_priv);
1863
1864         /* Revel in the empirically derived constants */
1865
1866         /* Correction factor in 1/100000 units */
1867         if (t > 80)
1868                 corr = ((t * 2349) + 135940);
1869         else if (t >= 50)
1870                 corr = ((t * 964) + 29317);
1871         else /* < 50 */
1872                 corr = ((t * 301) + 1004);
1873
1874         corr = corr * ((150142 * state1) / 10000 - 78642);
1875         corr /= 100000;
1876         corr2 = (corr * dev_priv->corr);
1877
1878         state2 = (corr2 * state1) / 10000;
1879         state2 /= 100; /* convert to mW */
1880
1881         i915_update_gfx_val(dev_priv);
1882
1883         return dev_priv->gfx_power + state2;
1884 }
1885
1886 /* Global for IPS driver to get at the current i915 device */
1887 static struct drm_i915_private *i915_mch_dev;
1888 /*
1889  * Lock protecting IPS related data structures
1890  *   - i915_mch_dev
1891  *   - dev_priv->max_delay
1892  *   - dev_priv->min_delay
1893  *   - dev_priv->fmax
1894  *   - dev_priv->gpu_busy
1895  */
1896 static DEFINE_SPINLOCK(mchdev_lock);
1897
1898 /**
1899  * i915_read_mch_val - return value for IPS use
1900  *
1901  * Calculate and return a value for the IPS driver to use when deciding whether
1902  * we have thermal and power headroom to increase CPU or GPU power budget.
1903  */
1904 unsigned long i915_read_mch_val(void)
1905 {
1906         struct drm_i915_private *dev_priv;
1907         unsigned long chipset_val, graphics_val, ret = 0;
1908
1909         spin_lock(&mchdev_lock);
1910         if (!i915_mch_dev)
1911                 goto out_unlock;
1912         dev_priv = i915_mch_dev;
1913
1914         chipset_val = i915_chipset_val(dev_priv);
1915         graphics_val = i915_gfx_val(dev_priv);
1916
1917         ret = chipset_val + graphics_val;
1918
1919 out_unlock:
1920         spin_unlock(&mchdev_lock);
1921
1922         return ret;
1923 }
1924 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1925
1926 /**
1927  * i915_gpu_raise - raise GPU frequency limit
1928  *
1929  * Raise the limit; IPS indicates we have thermal headroom.
1930  */
1931 bool i915_gpu_raise(void)
1932 {
1933         struct drm_i915_private *dev_priv;
1934         bool ret = true;
1935
1936         spin_lock(&mchdev_lock);
1937         if (!i915_mch_dev) {
1938                 ret = false;
1939                 goto out_unlock;
1940         }
1941         dev_priv = i915_mch_dev;
1942
1943         if (dev_priv->max_delay > dev_priv->fmax)
1944                 dev_priv->max_delay--;
1945
1946 out_unlock:
1947         spin_unlock(&mchdev_lock);
1948
1949         return ret;
1950 }
1951 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1952
1953 /**
1954  * i915_gpu_lower - lower GPU frequency limit
1955  *
1956  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1957  * frequency maximum.
1958  */
1959 bool i915_gpu_lower(void)
1960 {
1961         struct drm_i915_private *dev_priv;
1962         bool ret = true;
1963
1964         spin_lock(&mchdev_lock);
1965         if (!i915_mch_dev) {
1966                 ret = false;
1967                 goto out_unlock;
1968         }
1969         dev_priv = i915_mch_dev;
1970
1971         if (dev_priv->max_delay < dev_priv->min_delay)
1972                 dev_priv->max_delay++;
1973
1974 out_unlock:
1975         spin_unlock(&mchdev_lock);
1976
1977         return ret;
1978 }
1979 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1980
1981 /**
1982  * i915_gpu_busy - indicate GPU business to IPS
1983  *
1984  * Tell the IPS driver whether or not the GPU is busy.
1985  */
1986 bool i915_gpu_busy(void)
1987 {
1988         struct drm_i915_private *dev_priv;
1989         bool ret = false;
1990
1991         spin_lock(&mchdev_lock);
1992         if (!i915_mch_dev)
1993                 goto out_unlock;
1994         dev_priv = i915_mch_dev;
1995
1996         ret = dev_priv->busy;
1997
1998 out_unlock:
1999         spin_unlock(&mchdev_lock);
2000
2001         return ret;
2002 }
2003 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2004
2005 /**
2006  * i915_gpu_turbo_disable - disable graphics turbo
2007  *
2008  * Disable graphics turbo by resetting the max frequency and setting the
2009  * current frequency to the default.
2010  */
2011 bool i915_gpu_turbo_disable(void)
2012 {
2013         struct drm_i915_private *dev_priv;
2014         bool ret = true;
2015
2016         spin_lock(&mchdev_lock);
2017         if (!i915_mch_dev) {
2018                 ret = false;
2019                 goto out_unlock;
2020         }
2021         dev_priv = i915_mch_dev;
2022
2023         dev_priv->max_delay = dev_priv->fstart;
2024
2025         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2026                 ret = false;
2027
2028 out_unlock:
2029         spin_unlock(&mchdev_lock);
2030
2031         return ret;
2032 }
2033 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2034
2035 /**
2036  * i915_driver_load - setup chip and create an initial config
2037  * @dev: DRM device
2038  * @flags: startup flags
2039  *
2040  * The driver load routine has to do several things:
2041  *   - drive output discovery via intel_modeset_init()
2042  *   - initialize the memory manager
2043  *   - allocate initial config memory
2044  *   - setup the DRM framebuffer with the allocated memory
2045  */
2046 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2047 {
2048         struct drm_i915_private *dev_priv;
2049         resource_size_t base, size;
2050         int ret = 0, mmio_bar;
2051         uint32_t agp_size, prealloc_size;
2052         /* i915 has 4 more counters */
2053         dev->counters += 4;
2054         dev->types[6] = _DRM_STAT_IRQ;
2055         dev->types[7] = _DRM_STAT_PRIMARY;
2056         dev->types[8] = _DRM_STAT_SECONDARY;
2057         dev->types[9] = _DRM_STAT_DMA;
2058
2059         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2060         if (dev_priv == NULL)
2061                 return -ENOMEM;
2062
2063         dev->dev_private = (void *)dev_priv;
2064         dev_priv->dev = dev;
2065         dev_priv->info = (struct intel_device_info *) flags;
2066
2067         /* Add register map (needed for suspend/resume) */
2068         mmio_bar = IS_I9XX(dev) ? 0 : 1;
2069         base = pci_resource_start(dev->pdev, mmio_bar);
2070         size = pci_resource_len(dev->pdev, mmio_bar);
2071
2072         if (i915_get_bridge_dev(dev)) {
2073                 ret = -EIO;
2074                 goto free_priv;
2075         }
2076
2077         /* overlay on gen2 is broken and can't address above 1G */
2078         if (IS_GEN2(dev))
2079                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2080
2081         dev_priv->regs = ioremap(base, size);
2082         if (!dev_priv->regs) {
2083                 DRM_ERROR("failed to map registers\n");
2084                 ret = -EIO;
2085                 goto put_bridge;
2086         }
2087
2088         dev_priv->mm.gtt_mapping =
2089                 io_mapping_create_wc(dev->agp->base,
2090                                      dev->agp->agp_info.aper_size * 1024*1024);
2091         if (dev_priv->mm.gtt_mapping == NULL) {
2092                 ret = -EIO;
2093                 goto out_rmmap;
2094         }
2095
2096         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2097          * one would think, because the kernel disables PAT on first
2098          * generation Core chips because WC PAT gets overridden by a UC
2099          * MTRR if present.  Even if a UC MTRR isn't present.
2100          */
2101         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2102                                          dev->agp->agp_info.aper_size *
2103                                          1024 * 1024,
2104                                          MTRR_TYPE_WRCOMB, 1);
2105         if (dev_priv->mm.gtt_mtrr < 0) {
2106                 DRM_INFO("MTRR allocation failed.  Graphics "
2107                          "performance may suffer.\n");
2108         }
2109
2110         ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
2111         if (ret)
2112                 goto out_iomapfree;
2113
2114         if (prealloc_size > intel_max_stolen) {
2115                 DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
2116                          prealloc_size >> 20, intel_max_stolen >> 20);
2117                 prealloc_size = intel_max_stolen;
2118         }
2119
2120         dev_priv->wq = create_singlethread_workqueue("i915");
2121         if (dev_priv->wq == NULL) {
2122                 DRM_ERROR("Failed to create our workqueue.\n");
2123                 ret = -ENOMEM;
2124                 goto out_iomapfree;
2125         }
2126
2127         /* enable GEM by default */
2128         dev_priv->has_gem = 1;
2129
2130         if (prealloc_size > agp_size * 3 / 4) {
2131                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2132                           "memory stolen.\n",
2133                           prealloc_size / 1024, agp_size / 1024);
2134                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2135                           "updating the BIOS to fix).\n");
2136                 dev_priv->has_gem = 0;
2137         }
2138
2139         if (dev_priv->has_gem == 0 &&
2140             drm_core_check_feature(dev, DRIVER_MODESET)) {
2141                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2142                 ret = -ENODEV;
2143                 goto out_iomapfree;
2144         }
2145
2146         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2147         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2148         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2149                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2150                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2151         }
2152
2153         /* Try to make sure MCHBAR is enabled before poking at it */
2154         intel_setup_mchbar(dev);
2155         intel_opregion_setup(dev);
2156
2157         i915_gem_load(dev);
2158
2159         /* Init HWS */
2160         if (!I915_NEED_GFX_HWS(dev)) {
2161                 ret = i915_init_phys_hws(dev);
2162                 if (ret != 0)
2163                         goto out_workqueue_free;
2164         }
2165
2166         if (IS_PINEVIEW(dev))
2167                 i915_pineview_get_mem_freq(dev);
2168         else if (IS_IRONLAKE(dev))
2169                 i915_ironlake_get_mem_freq(dev);
2170
2171         /* On the 945G/GM, the chipset reports the MSI capability on the
2172          * integrated graphics even though the support isn't actually there
2173          * according to the published specs.  It doesn't appear to function
2174          * correctly in testing on 945G.
2175          * This may be a side effect of MSI having been made available for PEG
2176          * and the registers being closely associated.
2177          *
2178          * According to chipset errata, on the 965GM, MSI interrupts may
2179          * be lost or delayed, but we use them anyways to avoid
2180          * stuck interrupts on some machines.
2181          */
2182         if (!IS_I945G(dev) && !IS_I945GM(dev))
2183                 pci_enable_msi(dev->pdev);
2184
2185         spin_lock_init(&dev_priv->user_irq_lock);
2186         spin_lock_init(&dev_priv->error_lock);
2187         dev_priv->trace_irq_seqno = 0;
2188
2189         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2190
2191         if (ret) {
2192                 (void) i915_driver_unload(dev);
2193                 return ret;
2194         }
2195
2196         /* Start out suspended */
2197         dev_priv->mm.suspended = 1;
2198
2199         intel_detect_pch(dev);
2200
2201         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2202                 ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
2203                 if (ret < 0) {
2204                         DRM_ERROR("failed to init modeset\n");
2205                         goto out_workqueue_free;
2206                 }
2207         }
2208
2209         /* Must be done after probing outputs */
2210         intel_opregion_init(dev);
2211         acpi_video_register();
2212
2213         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2214                     (unsigned long) dev);
2215
2216         spin_lock(&mchdev_lock);
2217         i915_mch_dev = dev_priv;
2218         dev_priv->mchdev_lock = &mchdev_lock;
2219         spin_unlock(&mchdev_lock);
2220
2221         return 0;
2222
2223 out_workqueue_free:
2224         destroy_workqueue(dev_priv->wq);
2225 out_iomapfree:
2226         io_mapping_free(dev_priv->mm.gtt_mapping);
2227 out_rmmap:
2228         iounmap(dev_priv->regs);
2229 put_bridge:
2230         pci_dev_put(dev_priv->bridge_dev);
2231 free_priv:
2232         kfree(dev_priv);
2233         return ret;
2234 }
2235
2236 int i915_driver_unload(struct drm_device *dev)
2237 {
2238         struct drm_i915_private *dev_priv = dev->dev_private;
2239         int ret;
2240
2241         spin_lock(&mchdev_lock);
2242         i915_mch_dev = NULL;
2243         spin_unlock(&mchdev_lock);
2244
2245         mutex_lock(&dev->struct_mutex);
2246         ret = i915_gpu_idle(dev);
2247         if (ret)
2248                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2249         mutex_unlock(&dev->struct_mutex);
2250
2251         /* Cancel the retire work handler, which should be idle now. */
2252         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2253
2254         io_mapping_free(dev_priv->mm.gtt_mapping);
2255         if (dev_priv->mm.gtt_mtrr >= 0) {
2256                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2257                          dev->agp->agp_info.aper_size * 1024 * 1024);
2258                 dev_priv->mm.gtt_mtrr = -1;
2259         }
2260
2261         acpi_video_unregister();
2262
2263         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2264                 intel_modeset_cleanup(dev);
2265
2266                 /*
2267                  * free the memory space allocated for the child device
2268                  * config parsed from VBT
2269                  */
2270                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2271                         kfree(dev_priv->child_dev);
2272                         dev_priv->child_dev = NULL;
2273                         dev_priv->child_dev_num = 0;
2274                 }
2275
2276                 vga_switcheroo_unregister_client(dev->pdev);
2277                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2278         }
2279
2280         /* Free error state after interrupts are fully disabled. */
2281         del_timer_sync(&dev_priv->hangcheck_timer);
2282         cancel_work_sync(&dev_priv->error_work);
2283         i915_destroy_error_state(dev);
2284
2285         if (dev->pdev->msi_enabled)
2286                 pci_disable_msi(dev->pdev);
2287
2288         if (dev_priv->regs != NULL)
2289                 iounmap(dev_priv->regs);
2290
2291         intel_opregion_fini(dev);
2292
2293         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2294                 /* Flush any outstanding unpin_work. */
2295                 flush_workqueue(dev_priv->wq);
2296
2297                 i915_gem_free_all_phys_object(dev);
2298
2299                 mutex_lock(&dev->struct_mutex);
2300                 i915_gem_cleanup_ringbuffer(dev);
2301                 mutex_unlock(&dev->struct_mutex);
2302                 if (I915_HAS_FBC(dev) && i915_powersave)
2303                         i915_cleanup_compression(dev);
2304                 drm_mm_takedown(&dev_priv->vram);
2305
2306                 intel_cleanup_overlay(dev);
2307         }
2308
2309         intel_teardown_mchbar(dev);
2310
2311         destroy_workqueue(dev_priv->wq);
2312
2313         pci_dev_put(dev_priv->bridge_dev);
2314         kfree(dev->dev_private);
2315
2316         return 0;
2317 }
2318
2319 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2320 {
2321         struct drm_i915_file_private *i915_file_priv;
2322
2323         DRM_DEBUG_DRIVER("\n");
2324         i915_file_priv = (struct drm_i915_file_private *)
2325             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2326
2327         if (!i915_file_priv)
2328                 return -ENOMEM;
2329
2330         file_priv->driver_priv = i915_file_priv;
2331
2332         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2333
2334         return 0;
2335 }
2336
2337 /**
2338  * i915_driver_lastclose - clean up after all DRM clients have exited
2339  * @dev: DRM device
2340  *
2341  * Take care of cleaning up after all DRM clients have exited.  In the
2342  * mode setting case, we want to restore the kernel's initial mode (just
2343  * in case the last client left us in a bad state).
2344  *
2345  * Additionally, in the non-mode setting case, we'll tear down the AGP
2346  * and DMA structures, since the kernel won't be using them, and clea
2347  * up any GEM state.
2348  */
2349 void i915_driver_lastclose(struct drm_device * dev)
2350 {
2351         drm_i915_private_t *dev_priv = dev->dev_private;
2352
2353         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2354                 drm_fb_helper_restore();
2355                 vga_switcheroo_process_delayed_switch();
2356                 return;
2357         }
2358
2359         i915_gem_lastclose(dev);
2360
2361         if (dev_priv->agp_heap)
2362                 i915_mem_takedown(&(dev_priv->agp_heap));
2363
2364         i915_dma_cleanup(dev);
2365 }
2366
2367 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2368 {
2369         drm_i915_private_t *dev_priv = dev->dev_private;
2370         i915_gem_release(dev, file_priv);
2371         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2372                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2373 }
2374
2375 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2376 {
2377         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2378
2379         kfree(i915_file_priv);
2380 }
2381
2382 struct drm_ioctl_desc i915_ioctls[] = {
2383         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2384         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2385         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2386         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2387         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2388         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2389         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2390         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2391         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2392         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2393         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2394         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2395         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2396         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2397         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2398         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2399         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2400         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2401         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2402         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2403         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2404         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2405         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2406         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2407         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2408         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2409         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2410         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2411         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2412         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2413         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2414         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2415         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2416         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2417         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2418         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2419         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2420         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2421         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2422         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2423 };
2424
2425 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2426
2427 /**
2428  * Determine if the device really is AGP or not.
2429  *
2430  * All Intel graphics chipsets are treated as AGP, even if they are really
2431  * PCI-e.
2432  *
2433  * \param dev   The device to be tested.
2434  *
2435  * \returns
2436  * A value of 1 is always retured to indictate every i9x5 is AGP.
2437  */
2438 int i915_driver_device_is_agp(struct drm_device * dev)
2439 {
2440         return 1;
2441 }