drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 {
1063         struct drm_device *dev = crtc->dev;
1064         struct drm_i915_private *dev_priv = dev->dev_private;
1065         struct drm_framebuffer *fb = crtc->fb;
1066         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1067         struct drm_i915_gem_object *obj = intel_fb->obj;
1068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069         int plane, i;
1070         u32 fbc_ctl, fbc_ctl2;
1071
1072         if (fb->pitch == dev_priv->cfb_pitch &&
1073             obj->fence_reg == dev_priv->cfb_fence &&
1074             intel_crtc->plane == dev_priv->cfb_plane &&
1075             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1076                 return;
1077
1078         i8xx_disable_fbc(dev);
1079
1080         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1081
1082         if (fb->pitch < dev_priv->cfb_pitch)
1083                 dev_priv->cfb_pitch = fb->pitch;
1084
1085         /* FBC_CTL wants 64B units */
1086         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1087         dev_priv->cfb_fence = obj->fence_reg;
1088         dev_priv->cfb_plane = intel_crtc->plane;
1089         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1090
1091         /* Clear old tags */
1092         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1093                 I915_WRITE(FBC_TAG + (i * 4), 0);
1094
1095         /* Set it up... */
1096         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1097         if (obj->tiling_mode != I915_TILING_NONE)
1098                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1099         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1100         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1101
1102         /* enable it... */
1103         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1104         if (IS_I945GM(dev))
1105                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1106         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1107         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1108         if (obj->tiling_mode != I915_TILING_NONE)
1109                 fbc_ctl |= dev_priv->cfb_fence;
1110         I915_WRITE(FBC_CONTROL, fbc_ctl);
1111
1112         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1113                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1114 }
1115
1116 void i8xx_disable_fbc(struct drm_device *dev)
1117 {
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119         u32 fbc_ctl;
1120
1121         /* Disable compression */
1122         fbc_ctl = I915_READ(FBC_CONTROL);
1123         if ((fbc_ctl & FBC_CTL_EN) == 0)
1124                 return;
1125
1126         fbc_ctl &= ~FBC_CTL_EN;
1127         I915_WRITE(FBC_CONTROL, fbc_ctl);
1128
1129         /* Wait for compressing bit to clear */
1130         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1131                 DRM_DEBUG_KMS("FBC idle timed out\n");
1132                 return;
1133         }
1134
1135         DRM_DEBUG_KMS("disabled FBC\n");
1136 }
1137
1138 static bool i8xx_fbc_enabled(struct drm_device *dev)
1139 {
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1143 }
1144
1145 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1146 {
1147         struct drm_device *dev = crtc->dev;
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149         struct drm_framebuffer *fb = crtc->fb;
1150         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1151         struct drm_i915_gem_object *obj = intel_fb->obj;
1152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1153         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1154         unsigned long stall_watermark = 200;
1155         u32 dpfc_ctl;
1156
1157         dpfc_ctl = I915_READ(DPFC_CONTROL);
1158         if (dpfc_ctl & DPFC_CTL_EN) {
1159                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1160                     dev_priv->cfb_fence == obj->fence_reg &&
1161                     dev_priv->cfb_plane == intel_crtc->plane &&
1162                     dev_priv->cfb_y == crtc->y)
1163                         return;
1164
1165                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1166                 POSTING_READ(DPFC_CONTROL);
1167                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1168         }
1169
1170         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1171         dev_priv->cfb_fence = obj->fence_reg;
1172         dev_priv->cfb_plane = intel_crtc->plane;
1173         dev_priv->cfb_y = crtc->y;
1174
1175         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1176         if (obj->tiling_mode != I915_TILING_NONE) {
1177                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1178                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1179         } else {
1180                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1181         }
1182
1183         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1184                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1185                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1186         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1187
1188         /* enable it... */
1189         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1190
1191         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1192 }
1193
1194 void g4x_disable_fbc(struct drm_device *dev)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         u32 dpfc_ctl;
1198
1199         /* Disable compression */
1200         dpfc_ctl = I915_READ(DPFC_CONTROL);
1201         if (dpfc_ctl & DPFC_CTL_EN) {
1202                 dpfc_ctl &= ~DPFC_CTL_EN;
1203                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1204
1205                 DRM_DEBUG_KMS("disabled FBC\n");
1206         }
1207 }
1208
1209 static bool g4x_fbc_enabled(struct drm_device *dev)
1210 {
1211         struct drm_i915_private *dev_priv = dev->dev_private;
1212
1213         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1214 }
1215
1216 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1217 {
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         u32 blt_ecoskpd;
1220
1221         /* Make sure blitter notifies FBC of writes */
1222         __gen6_gt_force_wake_get(dev_priv);
1223         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1224         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1225                 GEN6_BLITTER_LOCK_SHIFT;
1226         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1227         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1228         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1229         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1230                          GEN6_BLITTER_LOCK_SHIFT);
1231         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1232         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1233         __gen6_gt_force_wake_put(dev_priv);
1234 }
1235
1236 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1237 {
1238         struct drm_device *dev = crtc->dev;
1239         struct drm_i915_private *dev_priv = dev->dev_private;
1240         struct drm_framebuffer *fb = crtc->fb;
1241         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1242         struct drm_i915_gem_object *obj = intel_fb->obj;
1243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1244         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1245         unsigned long stall_watermark = 200;
1246         u32 dpfc_ctl;
1247
1248         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1249         if (dpfc_ctl & DPFC_CTL_EN) {
1250                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1251                     dev_priv->cfb_fence == obj->fence_reg &&
1252                     dev_priv->cfb_plane == intel_crtc->plane &&
1253                     dev_priv->cfb_offset == obj->gtt_offset &&
1254                     dev_priv->cfb_y == crtc->y)
1255                         return;
1256
1257                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1258                 POSTING_READ(ILK_DPFC_CONTROL);
1259                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1260         }
1261
1262         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1263         dev_priv->cfb_fence = obj->fence_reg;
1264         dev_priv->cfb_plane = intel_crtc->plane;
1265         dev_priv->cfb_offset = obj->gtt_offset;
1266         dev_priv->cfb_y = crtc->y;
1267
1268         dpfc_ctl &= DPFC_RESERVED;
1269         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1270         if (obj->tiling_mode != I915_TILING_NONE) {
1271                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1272                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1273         } else {
1274                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1275         }
1276
1277         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1278                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1279                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1280         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1281         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1282         /* enable it... */
1283         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1284
1285         if (IS_GEN6(dev)) {
1286                 I915_WRITE(SNB_DPFC_CTL_SA,
1287                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1288                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1289                 sandybridge_blit_fbc_update(dev);
1290         }
1291
1292         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1293 }
1294
1295 void ironlake_disable_fbc(struct drm_device *dev)
1296 {
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         u32 dpfc_ctl;
1299
1300         /* Disable compression */
1301         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1302         if (dpfc_ctl & DPFC_CTL_EN) {
1303                 dpfc_ctl &= ~DPFC_CTL_EN;
1304                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1305
1306                 DRM_DEBUG_KMS("disabled FBC\n");
1307         }
1308 }
1309
1310 static bool ironlake_fbc_enabled(struct drm_device *dev)
1311 {
1312         struct drm_i915_private *dev_priv = dev->dev_private;
1313
1314         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1315 }
1316
1317 bool intel_fbc_enabled(struct drm_device *dev)
1318 {
1319         struct drm_i915_private *dev_priv = dev->dev_private;
1320
1321         if (!dev_priv->display.fbc_enabled)
1322                 return false;
1323
1324         return dev_priv->display.fbc_enabled(dev);
1325 }
1326
1327 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1328 {
1329         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1330
1331         if (!dev_priv->display.enable_fbc)
1332                 return;
1333
1334         dev_priv->display.enable_fbc(crtc, interval);
1335 }
1336
1337 void intel_disable_fbc(struct drm_device *dev)
1338 {
1339         struct drm_i915_private *dev_priv = dev->dev_private;
1340
1341         if (!dev_priv->display.disable_fbc)
1342                 return;
1343
1344         dev_priv->display.disable_fbc(dev);
1345 }
1346
1347 /**
1348  * intel_update_fbc - enable/disable FBC as needed
1349  * @dev: the drm_device
1350  *
1351  * Set up the framebuffer compression hardware at mode set time.  We
1352  * enable it if possible:
1353  *   - plane A only (on pre-965)
1354  *   - no pixel mulitply/line duplication
1355  *   - no alpha buffer discard
1356  *   - no dual wide
1357  *   - framebuffer <= 2048 in width, 1536 in height
1358  *
1359  * We can't assume that any compression will take place (worst case),
1360  * so the compressed buffer has to be the same size as the uncompressed
1361  * one.  It also must reside (along with the line length buffer) in
1362  * stolen memory.
1363  *
1364  * We need to enable/disable FBC on a global basis.
1365  */
1366 static void intel_update_fbc(struct drm_device *dev)
1367 {
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         struct drm_crtc *crtc = NULL, *tmp_crtc;
1370         struct intel_crtc *intel_crtc;
1371         struct drm_framebuffer *fb;
1372         struct intel_framebuffer *intel_fb;
1373         struct drm_i915_gem_object *obj;
1374
1375         DRM_DEBUG_KMS("\n");
1376
1377         if (!i915_powersave)
1378                 return;
1379
1380         if (!I915_HAS_FBC(dev))
1381                 return;
1382
1383         /*
1384          * If FBC is already on, we just have to verify that we can
1385          * keep it that way...
1386          * Need to disable if:
1387          *   - more than one pipe is active
1388          *   - changing FBC params (stride, fence, mode)
1389          *   - new fb is too large to fit in compressed buffer
1390          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1391          */
1392         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1393                 if (tmp_crtc->enabled) {
1394                         if (crtc) {
1395                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1396                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1397                                 goto out_disable;
1398                         }
1399                         crtc = tmp_crtc;
1400                 }
1401         }
1402
1403         if (!crtc || crtc->fb == NULL) {
1404                 DRM_DEBUG_KMS("no output, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1406                 goto out_disable;
1407         }
1408
1409         intel_crtc = to_intel_crtc(crtc);
1410         fb = crtc->fb;
1411         intel_fb = to_intel_framebuffer(fb);
1412         obj = intel_fb->obj;
1413
1414         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1415                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1416                               "compression\n");
1417                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1418                 goto out_disable;
1419         }
1420         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1421             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1422                 DRM_DEBUG_KMS("mode incompatible with compression, "
1423                               "disabling\n");
1424                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1425                 goto out_disable;
1426         }
1427         if ((crtc->mode.hdisplay > 2048) ||
1428             (crtc->mode.vdisplay > 1536)) {
1429                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1430                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1431                 goto out_disable;
1432         }
1433         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1434                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1435                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1436                 goto out_disable;
1437         }
1438         if (obj->tiling_mode != I915_TILING_X) {
1439                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1440                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1441                 goto out_disable;
1442         }
1443
1444         /* If the kernel debugger is active, always disable compression */
1445         if (in_dbg_master())
1446                 goto out_disable;
1447
1448         intel_enable_fbc(crtc, 500);
1449         return;
1450
1451 out_disable:
1452         /* Multiple disables should be harmless */
1453         if (intel_fbc_enabled(dev)) {
1454                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1455                 intel_disable_fbc(dev);
1456         }
1457 }
1458
1459 int
1460 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1461                            struct drm_i915_gem_object *obj,
1462                            struct intel_ring_buffer *pipelined)
1463 {
1464         u32 alignment;
1465         int ret;
1466
1467         switch (obj->tiling_mode) {
1468         case I915_TILING_NONE:
1469                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1470                         alignment = 128 * 1024;
1471                 else if (INTEL_INFO(dev)->gen >= 4)
1472                         alignment = 4 * 1024;
1473                 else
1474                         alignment = 64 * 1024;
1475                 break;
1476         case I915_TILING_X:
1477                 /* pin() will align the object as required by fence */
1478                 alignment = 0;
1479                 break;
1480         case I915_TILING_Y:
1481                 /* FIXME: Is this true? */
1482                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1483                 return -EINVAL;
1484         default:
1485                 BUG();
1486         }
1487
1488         ret = i915_gem_object_pin(obj, alignment, true);
1489         if (ret)
1490                 return ret;
1491
1492         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1493         if (ret)
1494                 goto err_unpin;
1495
1496         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1497          * fence, whereas 965+ only requires a fence if using
1498          * framebuffer compression.  For simplicity, we always install
1499          * a fence as the cost is not that onerous.
1500          */
1501         if (obj->tiling_mode != I915_TILING_NONE) {
1502                 ret = i915_gem_object_get_fence(obj, pipelined, false);
1503                 if (ret)
1504                         goto err_unpin;
1505         }
1506
1507         return 0;
1508
1509 err_unpin:
1510         i915_gem_object_unpin(obj);
1511         return ret;
1512 }
1513
1514 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1515 static int
1516 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1517                            int x, int y, enum mode_set_atomic state)
1518 {
1519         struct drm_device *dev = crtc->dev;
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1522         struct intel_framebuffer *intel_fb;
1523         struct drm_i915_gem_object *obj;
1524         int plane = intel_crtc->plane;
1525         unsigned long Start, Offset;
1526         u32 dspcntr;
1527         u32 reg;
1528
1529         switch (plane) {
1530         case 0:
1531         case 1:
1532                 break;
1533         default:
1534                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1535                 return -EINVAL;
1536         }
1537
1538         intel_fb = to_intel_framebuffer(fb);
1539         obj = intel_fb->obj;
1540
1541         reg = DSPCNTR(plane);
1542         dspcntr = I915_READ(reg);
1543         /* Mask out pixel format bits in case we change it */
1544         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545         switch (fb->bits_per_pixel) {
1546         case 8:
1547                 dspcntr |= DISPPLANE_8BPP;
1548                 break;
1549         case 16:
1550                 if (fb->depth == 15)
1551                         dspcntr |= DISPPLANE_15_16BPP;
1552                 else
1553                         dspcntr |= DISPPLANE_16BPP;
1554                 break;
1555         case 24:
1556         case 32:
1557                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1558                 break;
1559         default:
1560                 DRM_ERROR("Unknown color depth\n");
1561                 return -EINVAL;
1562         }
1563         if (INTEL_INFO(dev)->gen >= 4) {
1564                 if (obj->tiling_mode != I915_TILING_NONE)
1565                         dspcntr |= DISPPLANE_TILED;
1566                 else
1567                         dspcntr &= ~DISPPLANE_TILED;
1568         }
1569
1570         if (HAS_PCH_SPLIT(dev))
1571                 /* must disable */
1572                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1573
1574         I915_WRITE(reg, dspcntr);
1575
1576         Start = obj->gtt_offset;
1577         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1578
1579         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1580                       Start, Offset, x, y, fb->pitch);
1581         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1582         if (INTEL_INFO(dev)->gen >= 4) {
1583                 I915_WRITE(DSPSURF(plane), Start);
1584                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1585                 I915_WRITE(DSPADDR(plane), Offset);
1586         } else
1587                 I915_WRITE(DSPADDR(plane), Start + Offset);
1588         POSTING_READ(reg);
1589
1590         intel_update_fbc(dev);
1591         intel_increase_pllclock(crtc);
1592
1593         return 0;
1594 }
1595
1596 static int
1597 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1598                     struct drm_framebuffer *old_fb)
1599 {
1600         struct drm_device *dev = crtc->dev;
1601         struct drm_i915_master_private *master_priv;
1602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1603         int ret;
1604
1605         /* no fb bound */
1606         if (!crtc->fb) {
1607                 DRM_DEBUG_KMS("No FB bound\n");
1608                 return 0;
1609         }
1610
1611         switch (intel_crtc->plane) {
1612         case 0:
1613         case 1:
1614                 break;
1615         default:
1616                 return -EINVAL;
1617         }
1618
1619         mutex_lock(&dev->struct_mutex);
1620         ret = intel_pin_and_fence_fb_obj(dev,
1621                                          to_intel_framebuffer(crtc->fb)->obj,
1622                                          NULL);
1623         if (ret != 0) {
1624                 mutex_unlock(&dev->struct_mutex);
1625                 return ret;
1626         }
1627
1628         if (old_fb) {
1629                 struct drm_i915_private *dev_priv = dev->dev_private;
1630                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1631
1632                 wait_event(dev_priv->pending_flip_queue,
1633                            atomic_read(&dev_priv->mm.wedged) ||
1634                            atomic_read(&obj->pending_flip) == 0);
1635
1636                 /* Big Hammer, we also need to ensure that any pending
1637                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1638                  * current scanout is retired before unpinning the old
1639                  * framebuffer.
1640                  *
1641                  * This should only fail upon a hung GPU, in which case we
1642                  * can safely continue.
1643                  */
1644                 ret = i915_gem_object_flush_gpu(obj, false);
1645                 (void) ret;
1646         }
1647
1648         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1649                                          LEAVE_ATOMIC_MODE_SET);
1650         if (ret) {
1651                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1652                 mutex_unlock(&dev->struct_mutex);
1653                 return ret;
1654         }
1655
1656         if (old_fb) {
1657                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1658                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1659         }
1660
1661         mutex_unlock(&dev->struct_mutex);
1662
1663         if (!dev->primary->master)
1664                 return 0;
1665
1666         master_priv = dev->primary->master->driver_priv;
1667         if (!master_priv->sarea_priv)
1668                 return 0;
1669
1670         if (intel_crtc->pipe) {
1671                 master_priv->sarea_priv->pipeB_x = x;
1672                 master_priv->sarea_priv->pipeB_y = y;
1673         } else {
1674                 master_priv->sarea_priv->pipeA_x = x;
1675                 master_priv->sarea_priv->pipeA_y = y;
1676         }
1677
1678         return 0;
1679 }
1680
1681 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1682 {
1683         struct drm_device *dev = crtc->dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         u32 dpa_ctl;
1686
1687         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1688         dpa_ctl = I915_READ(DP_A);
1689         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1690
1691         if (clock < 200000) {
1692                 u32 temp;
1693                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1694                 /* workaround for 160Mhz:
1695                    1) program 0x4600c bits 15:0 = 0x8124
1696                    2) program 0x46010 bit 0 = 1
1697                    3) program 0x46034 bit 24 = 1
1698                    4) program 0x64000 bit 14 = 1
1699                    */
1700                 temp = I915_READ(0x4600c);
1701                 temp &= 0xffff0000;
1702                 I915_WRITE(0x4600c, temp | 0x8124);
1703
1704                 temp = I915_READ(0x46010);
1705                 I915_WRITE(0x46010, temp | 1);
1706
1707                 temp = I915_READ(0x46034);
1708                 I915_WRITE(0x46034, temp | (1 << 24));
1709         } else {
1710                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1711         }
1712         I915_WRITE(DP_A, dpa_ctl);
1713
1714         POSTING_READ(DP_A);
1715         udelay(500);
1716 }
1717
1718 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1719 {
1720         struct drm_device *dev = crtc->dev;
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1723         int pipe = intel_crtc->pipe;
1724         u32 reg, temp;
1725
1726         /* enable normal train */
1727         reg = FDI_TX_CTL(pipe);
1728         temp = I915_READ(reg);
1729         temp &= ~FDI_LINK_TRAIN_NONE;
1730         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1731         I915_WRITE(reg, temp);
1732
1733         reg = FDI_RX_CTL(pipe);
1734         temp = I915_READ(reg);
1735         if (HAS_PCH_CPT(dev)) {
1736                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1737                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1738         } else {
1739                 temp &= ~FDI_LINK_TRAIN_NONE;
1740                 temp |= FDI_LINK_TRAIN_NONE;
1741         }
1742         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1743
1744         /* wait one idle pattern time */
1745         POSTING_READ(reg);
1746         udelay(1000);
1747 }
1748
1749 /* The FDI link training functions for ILK/Ibexpeak. */
1750 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1751 {
1752         struct drm_device *dev = crtc->dev;
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1755         int pipe = intel_crtc->pipe;
1756         u32 reg, temp, tries;
1757
1758         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1759            for train result */
1760         reg = FDI_RX_IMR(pipe);
1761         temp = I915_READ(reg);
1762         temp &= ~FDI_RX_SYMBOL_LOCK;
1763         temp &= ~FDI_RX_BIT_LOCK;
1764         I915_WRITE(reg, temp);
1765         I915_READ(reg);
1766         udelay(150);
1767
1768         /* enable CPU FDI TX and PCH FDI RX */
1769         reg = FDI_TX_CTL(pipe);
1770         temp = I915_READ(reg);
1771         temp &= ~(7 << 19);
1772         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1773         temp &= ~FDI_LINK_TRAIN_NONE;
1774         temp |= FDI_LINK_TRAIN_PATTERN_1;
1775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1776
1777         reg = FDI_RX_CTL(pipe);
1778         temp = I915_READ(reg);
1779         temp &= ~FDI_LINK_TRAIN_NONE;
1780         temp |= FDI_LINK_TRAIN_PATTERN_1;
1781         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1782
1783         POSTING_READ(reg);
1784         udelay(150);
1785
1786         /* Ironlake workaround, enable clock pointer after FDI enable*/
1787         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1788
1789         reg = FDI_RX_IIR(pipe);
1790         for (tries = 0; tries < 5; tries++) {
1791                 temp = I915_READ(reg);
1792                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1793
1794                 if ((temp & FDI_RX_BIT_LOCK)) {
1795                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1796                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1797                         break;
1798                 }
1799         }
1800         if (tries == 5)
1801                 DRM_ERROR("FDI train 1 fail!\n");
1802
1803         /* Train 2 */
1804         reg = FDI_TX_CTL(pipe);
1805         temp = I915_READ(reg);
1806         temp &= ~FDI_LINK_TRAIN_NONE;
1807         temp |= FDI_LINK_TRAIN_PATTERN_2;
1808         I915_WRITE(reg, temp);
1809
1810         reg = FDI_RX_CTL(pipe);
1811         temp = I915_READ(reg);
1812         temp &= ~FDI_LINK_TRAIN_NONE;
1813         temp |= FDI_LINK_TRAIN_PATTERN_2;
1814         I915_WRITE(reg, temp);
1815
1816         POSTING_READ(reg);
1817         udelay(150);
1818
1819         reg = FDI_RX_IIR(pipe);
1820         for (tries = 0; tries < 5; tries++) {
1821                 temp = I915_READ(reg);
1822                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1823
1824                 if (temp & FDI_RX_SYMBOL_LOCK) {
1825                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1826                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1827                         break;
1828                 }
1829         }
1830         if (tries == 5)
1831                 DRM_ERROR("FDI train 2 fail!\n");
1832
1833         DRM_DEBUG_KMS("FDI train done\n");
1834
1835 }
1836
1837 static const int const snb_b_fdi_train_param [] = {
1838         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1839         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1840         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1841         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1842 };
1843
1844 /* The FDI link training functions for SNB/Cougarpoint. */
1845 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1846 {
1847         struct drm_device *dev = crtc->dev;
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1850         int pipe = intel_crtc->pipe;
1851         u32 reg, temp, i;
1852
1853         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1854            for train result */
1855         reg = FDI_RX_IMR(pipe);
1856         temp = I915_READ(reg);
1857         temp &= ~FDI_RX_SYMBOL_LOCK;
1858         temp &= ~FDI_RX_BIT_LOCK;
1859         I915_WRITE(reg, temp);
1860
1861         POSTING_READ(reg);
1862         udelay(150);
1863
1864         /* enable CPU FDI TX and PCH FDI RX */
1865         reg = FDI_TX_CTL(pipe);
1866         temp = I915_READ(reg);
1867         temp &= ~(7 << 19);
1868         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1869         temp &= ~FDI_LINK_TRAIN_NONE;
1870         temp |= FDI_LINK_TRAIN_PATTERN_1;
1871         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1872         /* SNB-B */
1873         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1874         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1875
1876         reg = FDI_RX_CTL(pipe);
1877         temp = I915_READ(reg);
1878         if (HAS_PCH_CPT(dev)) {
1879                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1880                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1881         } else {
1882                 temp &= ~FDI_LINK_TRAIN_NONE;
1883                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1884         }
1885         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1886
1887         POSTING_READ(reg);
1888         udelay(150);
1889
1890         for (i = 0; i < 4; i++ ) {
1891                 reg = FDI_TX_CTL(pipe);
1892                 temp = I915_READ(reg);
1893                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1894                 temp |= snb_b_fdi_train_param[i];
1895                 I915_WRITE(reg, temp);
1896
1897                 POSTING_READ(reg);
1898                 udelay(500);
1899
1900                 reg = FDI_RX_IIR(pipe);
1901                 temp = I915_READ(reg);
1902                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1903
1904                 if (temp & FDI_RX_BIT_LOCK) {
1905                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1906                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1907                         break;
1908                 }
1909         }
1910         if (i == 4)
1911                 DRM_ERROR("FDI train 1 fail!\n");
1912
1913         /* Train 2 */
1914         reg = FDI_TX_CTL(pipe);
1915         temp = I915_READ(reg);
1916         temp &= ~FDI_LINK_TRAIN_NONE;
1917         temp |= FDI_LINK_TRAIN_PATTERN_2;
1918         if (IS_GEN6(dev)) {
1919                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1920                 /* SNB-B */
1921                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1922         }
1923         I915_WRITE(reg, temp);
1924
1925         reg = FDI_RX_CTL(pipe);
1926         temp = I915_READ(reg);
1927         if (HAS_PCH_CPT(dev)) {
1928                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1929                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1930         } else {
1931                 temp &= ~FDI_LINK_TRAIN_NONE;
1932                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1933         }
1934         I915_WRITE(reg, temp);
1935
1936         POSTING_READ(reg);
1937         udelay(150);
1938
1939         for (i = 0; i < 4; i++ ) {
1940                 reg = FDI_TX_CTL(pipe);
1941                 temp = I915_READ(reg);
1942                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1943                 temp |= snb_b_fdi_train_param[i];
1944                 I915_WRITE(reg, temp);
1945
1946                 POSTING_READ(reg);
1947                 udelay(500);
1948
1949                 reg = FDI_RX_IIR(pipe);
1950                 temp = I915_READ(reg);
1951                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1952
1953                 if (temp & FDI_RX_SYMBOL_LOCK) {
1954                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1955                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1956                         break;
1957                 }
1958         }
1959         if (i == 4)
1960                 DRM_ERROR("FDI train 2 fail!\n");
1961
1962         DRM_DEBUG_KMS("FDI train done.\n");
1963 }
1964
1965 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1966 {
1967         struct drm_device *dev = crtc->dev;
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1970         int pipe = intel_crtc->pipe;
1971         u32 reg, temp;
1972
1973         /* Write the TU size bits so error detection works */
1974         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1975                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1976
1977         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1978         reg = FDI_RX_CTL(pipe);
1979         temp = I915_READ(reg);
1980         temp &= ~((0x7 << 19) | (0x7 << 16));
1981         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1982         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1983         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1984
1985         POSTING_READ(reg);
1986         udelay(200);
1987
1988         /* Switch from Rawclk to PCDclk */
1989         temp = I915_READ(reg);
1990         I915_WRITE(reg, temp | FDI_PCDCLK);
1991
1992         POSTING_READ(reg);
1993         udelay(200);
1994
1995         /* Enable CPU FDI TX PLL, always on for Ironlake */
1996         reg = FDI_TX_CTL(pipe);
1997         temp = I915_READ(reg);
1998         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1999                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2000
2001                 POSTING_READ(reg);
2002                 udelay(100);
2003         }
2004 }
2005
2006 static void intel_flush_display_plane(struct drm_device *dev,
2007                                       int plane)
2008 {
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         u32 reg = DSPADDR(plane);
2011         I915_WRITE(reg, I915_READ(reg));
2012 }
2013
2014 /*
2015  * When we disable a pipe, we need to clear any pending scanline wait events
2016  * to avoid hanging the ring, which we assume we are waiting on.
2017  */
2018 static void intel_clear_scanline_wait(struct drm_device *dev)
2019 {
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_ring_buffer *ring;
2022         u32 tmp;
2023
2024         if (IS_GEN2(dev))
2025                 /* Can't break the hang on i8xx */
2026                 return;
2027
2028         ring = LP_RING(dev_priv);
2029         tmp = I915_READ_CTL(ring);
2030         if (tmp & RING_WAIT)
2031                 I915_WRITE_CTL(ring, tmp);
2032 }
2033
2034 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2035 {
2036         struct drm_i915_gem_object *obj;
2037         struct drm_i915_private *dev_priv;
2038
2039         if (crtc->fb == NULL)
2040                 return;
2041
2042         obj = to_intel_framebuffer(crtc->fb)->obj;
2043         dev_priv = crtc->dev->dev_private;
2044         wait_event(dev_priv->pending_flip_queue,
2045                    atomic_read(&obj->pending_flip) == 0);
2046 }
2047
2048 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2049 {
2050         struct drm_device *dev = crtc->dev;
2051         struct drm_mode_config *mode_config = &dev->mode_config;
2052         struct intel_encoder *encoder;
2053
2054         /*
2055          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2056          * must be driven by its own crtc; no sharing is possible.
2057          */
2058         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2059                 if (encoder->base.crtc != crtc)
2060                         continue;
2061
2062                 switch (encoder->type) {
2063                 case INTEL_OUTPUT_EDP:
2064                         if (!intel_encoder_is_pch_edp(&encoder->base))
2065                                 return false;
2066                         continue;
2067                 }
2068         }
2069
2070         return true;
2071 }
2072
2073 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2074 {
2075         struct drm_device *dev = crtc->dev;
2076         struct drm_i915_private *dev_priv = dev->dev_private;
2077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2078         int pipe = intel_crtc->pipe;
2079         int plane = intel_crtc->plane;
2080         u32 reg, temp;
2081         bool is_pch_port = false;
2082
2083         if (intel_crtc->active)
2084                 return;
2085
2086         intel_crtc->active = true;
2087         intel_update_watermarks(dev);
2088
2089         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2090                 temp = I915_READ(PCH_LVDS);
2091                 if ((temp & LVDS_PORT_EN) == 0)
2092                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2093         }
2094
2095         is_pch_port = intel_crtc_driving_pch(crtc);
2096
2097         if (is_pch_port)
2098                 ironlake_fdi_enable(crtc);
2099         else {
2100                 /* disable CPU FDI tx and PCH FDI rx */
2101                 reg = FDI_TX_CTL(pipe);
2102                 temp = I915_READ(reg);
2103                 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2104                 POSTING_READ(reg);
2105
2106                 reg = FDI_RX_CTL(pipe);
2107                 temp = I915_READ(reg);
2108                 temp &= ~(0x7 << 16);
2109                 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2110                 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2111
2112                 POSTING_READ(reg);
2113                 udelay(100);
2114
2115                 /* Ironlake workaround, disable clock pointer after downing FDI */
2116                 if (HAS_PCH_IBX(dev))
2117                         I915_WRITE(FDI_RX_CHICKEN(pipe),
2118                                    I915_READ(FDI_RX_CHICKEN(pipe) &
2119                                              ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2120
2121                 /* still set train pattern 1 */
2122                 reg = FDI_TX_CTL(pipe);
2123                 temp = I915_READ(reg);
2124                 temp &= ~FDI_LINK_TRAIN_NONE;
2125                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2126                 I915_WRITE(reg, temp);
2127
2128                 reg = FDI_RX_CTL(pipe);
2129                 temp = I915_READ(reg);
2130                 if (HAS_PCH_CPT(dev)) {
2131                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2132                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2133                 } else {
2134                         temp &= ~FDI_LINK_TRAIN_NONE;
2135                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2136                 }
2137                 /* BPC in FDI rx is consistent with that in PIPECONF */
2138                 temp &= ~(0x07 << 16);
2139                 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2140                 I915_WRITE(reg, temp);
2141
2142                 POSTING_READ(reg);
2143                 udelay(100);
2144         }
2145
2146         /* Enable panel fitting for LVDS */
2147         if (dev_priv->pch_pf_size &&
2148             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2149                 /* Force use of hard-coded filter coefficients
2150                  * as some pre-programmed values are broken,
2151                  * e.g. x201.
2152                  */
2153                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2154                            PF_ENABLE | PF_FILTER_MED_3x3);
2155                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2156                            dev_priv->pch_pf_pos);
2157                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2158                            dev_priv->pch_pf_size);
2159         }
2160
2161         /* Enable CPU pipe */
2162         reg = PIPECONF(pipe);
2163         temp = I915_READ(reg);
2164         if ((temp & PIPECONF_ENABLE) == 0) {
2165                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2166                 POSTING_READ(reg);
2167                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2168         }
2169
2170         /* configure and enable CPU plane */
2171         reg = DSPCNTR(plane);
2172         temp = I915_READ(reg);
2173         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2174                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2175                 intel_flush_display_plane(dev, plane);
2176         }
2177
2178         /* Skip the PCH stuff if possible */
2179         if (!is_pch_port)
2180                 goto done;
2181
2182         /* For PCH output, training FDI link */
2183         if (IS_GEN6(dev))
2184                 gen6_fdi_link_train(crtc);
2185         else
2186                 ironlake_fdi_link_train(crtc);
2187
2188         /* enable PCH DPLL */
2189         reg = PCH_DPLL(pipe);
2190         temp = I915_READ(reg);
2191         if ((temp & DPLL_VCO_ENABLE) == 0) {
2192                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2193                 POSTING_READ(reg);
2194                 udelay(200);
2195         }
2196
2197         if (HAS_PCH_CPT(dev)) {
2198                 /* Be sure PCH DPLL SEL is set */
2199                 temp = I915_READ(PCH_DPLL_SEL);
2200                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2201                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2202                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2203                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2204                 I915_WRITE(PCH_DPLL_SEL, temp);
2205         }
2206
2207         /* set transcoder timing */
2208         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2209         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2210         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2211
2212         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2213         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2214         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2215
2216         intel_fdi_normal_train(crtc);
2217
2218         /* For PCH DP, enable TRANS_DP_CTL */
2219         if (HAS_PCH_CPT(dev) &&
2220             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2221                 reg = TRANS_DP_CTL(pipe);
2222                 temp = I915_READ(reg);
2223                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2224                           TRANS_DP_SYNC_MASK |
2225                           TRANS_DP_BPC_MASK);
2226                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2227                          TRANS_DP_ENH_FRAMING);
2228                 temp |= TRANS_DP_8BPC;
2229
2230                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2231                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2232                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2233                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2234
2235                 switch (intel_trans_dp_port_sel(crtc)) {
2236                 case PCH_DP_B:
2237                         temp |= TRANS_DP_PORT_SEL_B;
2238                         break;
2239                 case PCH_DP_C:
2240                         temp |= TRANS_DP_PORT_SEL_C;
2241                         break;
2242                 case PCH_DP_D:
2243                         temp |= TRANS_DP_PORT_SEL_D;
2244                         break;
2245                 default:
2246                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2247                         temp |= TRANS_DP_PORT_SEL_B;
2248                         break;
2249                 }
2250
2251                 I915_WRITE(reg, temp);
2252         }
2253
2254         /* enable PCH transcoder */
2255         reg = TRANSCONF(pipe);
2256         temp = I915_READ(reg);
2257         /*
2258          * make the BPC in transcoder be consistent with
2259          * that in pipeconf reg.
2260          */
2261         temp &= ~PIPE_BPC_MASK;
2262         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2263         I915_WRITE(reg, temp | TRANS_ENABLE);
2264         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2265                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2266 done:
2267         intel_crtc_load_lut(crtc);
2268         intel_update_fbc(dev);
2269         intel_crtc_update_cursor(crtc, true);
2270 }
2271
2272 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2273 {
2274         struct drm_device *dev = crtc->dev;
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2277         int pipe = intel_crtc->pipe;
2278         int plane = intel_crtc->plane;
2279         u32 reg, temp;
2280
2281         if (!intel_crtc->active)
2282                 return;
2283
2284         intel_crtc_wait_for_pending_flips(crtc);
2285         drm_vblank_off(dev, pipe);
2286         intel_crtc_update_cursor(crtc, false);
2287
2288         /* Disable display plane */
2289         reg = DSPCNTR(plane);
2290         temp = I915_READ(reg);
2291         if (temp & DISPLAY_PLANE_ENABLE) {
2292                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2293                 intel_flush_display_plane(dev, plane);
2294         }
2295
2296         if (dev_priv->cfb_plane == plane &&
2297             dev_priv->display.disable_fbc)
2298                 dev_priv->display.disable_fbc(dev);
2299
2300         /* disable cpu pipe, disable after all planes disabled */
2301         reg = PIPECONF(pipe);
2302         temp = I915_READ(reg);
2303         if (temp & PIPECONF_ENABLE) {
2304                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2305                 POSTING_READ(reg);
2306                 /* wait for cpu pipe off, pipe state */
2307                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2308         }
2309
2310         /* Disable PF */
2311         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2312         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2313
2314         /* disable CPU FDI tx and PCH FDI rx */
2315         reg = FDI_TX_CTL(pipe);
2316         temp = I915_READ(reg);
2317         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2318         POSTING_READ(reg);
2319
2320         reg = FDI_RX_CTL(pipe);
2321         temp = I915_READ(reg);
2322         temp &= ~(0x7 << 16);
2323         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2324         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2325
2326         POSTING_READ(reg);
2327         udelay(100);
2328
2329         /* Ironlake workaround, disable clock pointer after downing FDI */
2330         if (HAS_PCH_IBX(dev))
2331                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2332                            I915_READ(FDI_RX_CHICKEN(pipe) &
2333                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2334
2335         /* still set train pattern 1 */
2336         reg = FDI_TX_CTL(pipe);
2337         temp = I915_READ(reg);
2338         temp &= ~FDI_LINK_TRAIN_NONE;
2339         temp |= FDI_LINK_TRAIN_PATTERN_1;
2340         I915_WRITE(reg, temp);
2341
2342         reg = FDI_RX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         if (HAS_PCH_CPT(dev)) {
2345                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2346                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2347         } else {
2348                 temp &= ~FDI_LINK_TRAIN_NONE;
2349                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2350         }
2351         /* BPC in FDI rx is consistent with that in PIPECONF */
2352         temp &= ~(0x07 << 16);
2353         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2354         I915_WRITE(reg, temp);
2355
2356         POSTING_READ(reg);
2357         udelay(100);
2358
2359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2360                 temp = I915_READ(PCH_LVDS);
2361                 if (temp & LVDS_PORT_EN) {
2362                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2363                         POSTING_READ(PCH_LVDS);
2364                         udelay(100);
2365                 }
2366         }
2367
2368         /* disable PCH transcoder */
2369         reg = TRANSCONF(plane);
2370         temp = I915_READ(reg);
2371         if (temp & TRANS_ENABLE) {
2372                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2373                 /* wait for PCH transcoder off, transcoder state */
2374                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2375                         DRM_ERROR("failed to disable transcoder\n");
2376         }
2377
2378         if (HAS_PCH_CPT(dev)) {
2379                 /* disable TRANS_DP_CTL */
2380                 reg = TRANS_DP_CTL(pipe);
2381                 temp = I915_READ(reg);
2382                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2383                 I915_WRITE(reg, temp);
2384
2385                 /* disable DPLL_SEL */
2386                 temp = I915_READ(PCH_DPLL_SEL);
2387                 if (pipe == 0)
2388                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2389                 else
2390                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2391                 I915_WRITE(PCH_DPLL_SEL, temp);
2392         }
2393
2394         /* disable PCH DPLL */
2395         reg = PCH_DPLL(pipe);
2396         temp = I915_READ(reg);
2397         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2398
2399         /* Switch from PCDclk to Rawclk */
2400         reg = FDI_RX_CTL(pipe);
2401         temp = I915_READ(reg);
2402         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2403
2404         /* Disable CPU FDI TX PLL */
2405         reg = FDI_TX_CTL(pipe);
2406         temp = I915_READ(reg);
2407         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2408
2409         POSTING_READ(reg);
2410         udelay(100);
2411
2412         reg = FDI_RX_CTL(pipe);
2413         temp = I915_READ(reg);
2414         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2415
2416         /* Wait for the clocks to turn off. */
2417         POSTING_READ(reg);
2418         udelay(100);
2419
2420         intel_crtc->active = false;
2421         intel_update_watermarks(dev);
2422         intel_update_fbc(dev);
2423         intel_clear_scanline_wait(dev);
2424 }
2425
2426 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2427 {
2428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2429         int pipe = intel_crtc->pipe;
2430         int plane = intel_crtc->plane;
2431
2432         /* XXX: When our outputs are all unaware of DPMS modes other than off
2433          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2434          */
2435         switch (mode) {
2436         case DRM_MODE_DPMS_ON:
2437         case DRM_MODE_DPMS_STANDBY:
2438         case DRM_MODE_DPMS_SUSPEND:
2439                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2440                 ironlake_crtc_enable(crtc);
2441                 break;
2442
2443         case DRM_MODE_DPMS_OFF:
2444                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2445                 ironlake_crtc_disable(crtc);
2446                 break;
2447         }
2448 }
2449
2450 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2451 {
2452         if (!enable && intel_crtc->overlay) {
2453                 struct drm_device *dev = intel_crtc->base.dev;
2454
2455                 mutex_lock(&dev->struct_mutex);
2456                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2457                 mutex_unlock(&dev->struct_mutex);
2458         }
2459
2460         /* Let userspace switch the overlay on again. In most cases userspace
2461          * has to recompute where to put it anyway.
2462          */
2463 }
2464
2465 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2466 {
2467         struct drm_device *dev = crtc->dev;
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470         int pipe = intel_crtc->pipe;
2471         int plane = intel_crtc->plane;
2472         u32 reg, temp;
2473
2474         if (intel_crtc->active)
2475                 return;
2476
2477         intel_crtc->active = true;
2478         intel_update_watermarks(dev);
2479
2480         /* Enable the DPLL */
2481         reg = DPLL(pipe);
2482         temp = I915_READ(reg);
2483         if ((temp & DPLL_VCO_ENABLE) == 0) {
2484                 I915_WRITE(reg, temp);
2485
2486                 /* Wait for the clocks to stabilize. */
2487                 POSTING_READ(reg);
2488                 udelay(150);
2489
2490                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2491
2492                 /* Wait for the clocks to stabilize. */
2493                 POSTING_READ(reg);
2494                 udelay(150);
2495
2496                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2497
2498                 /* Wait for the clocks to stabilize. */
2499                 POSTING_READ(reg);
2500                 udelay(150);
2501         }
2502
2503         /* Enable the pipe */
2504         reg = PIPECONF(pipe);
2505         temp = I915_READ(reg);
2506         if ((temp & PIPECONF_ENABLE) == 0)
2507                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2508
2509         /* Enable the plane */
2510         reg = DSPCNTR(plane);
2511         temp = I915_READ(reg);
2512         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2513                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2514                 intel_flush_display_plane(dev, plane);
2515         }
2516
2517         intel_crtc_load_lut(crtc);
2518         intel_update_fbc(dev);
2519
2520         /* Give the overlay scaler a chance to enable if it's on this pipe */
2521         intel_crtc_dpms_overlay(intel_crtc, true);
2522         intel_crtc_update_cursor(crtc, true);
2523 }
2524
2525 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2526 {
2527         struct drm_device *dev = crtc->dev;
2528         struct drm_i915_private *dev_priv = dev->dev_private;
2529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2530         int pipe = intel_crtc->pipe;
2531         int plane = intel_crtc->plane;
2532         u32 reg, temp;
2533
2534         if (!intel_crtc->active)
2535                 return;
2536
2537         /* Give the overlay scaler a chance to disable if it's on this pipe */
2538         intel_crtc_wait_for_pending_flips(crtc);
2539         drm_vblank_off(dev, pipe);
2540         intel_crtc_dpms_overlay(intel_crtc, false);
2541         intel_crtc_update_cursor(crtc, false);
2542
2543         if (dev_priv->cfb_plane == plane &&
2544             dev_priv->display.disable_fbc)
2545                 dev_priv->display.disable_fbc(dev);
2546
2547         /* Disable display plane */
2548         reg = DSPCNTR(plane);
2549         temp = I915_READ(reg);
2550         if (temp & DISPLAY_PLANE_ENABLE) {
2551                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2552                 /* Flush the plane changes */
2553                 intel_flush_display_plane(dev, plane);
2554
2555                 /* Wait for vblank for the disable to take effect */
2556                 if (IS_GEN2(dev))
2557                         intel_wait_for_vblank(dev, pipe);
2558         }
2559
2560         /* Don't disable pipe A or pipe A PLLs if needed */
2561         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2562                 goto done;
2563
2564         /* Next, disable display pipes */
2565         reg = PIPECONF(pipe);
2566         temp = I915_READ(reg);
2567         if (temp & PIPECONF_ENABLE) {
2568                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2569
2570                 /* Wait for the pipe to turn off */
2571                 POSTING_READ(reg);
2572                 intel_wait_for_pipe_off(dev, pipe);
2573         }
2574
2575         reg = DPLL(pipe);
2576         temp = I915_READ(reg);
2577         if (temp & DPLL_VCO_ENABLE) {
2578                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2579
2580                 /* Wait for the clocks to turn off. */
2581                 POSTING_READ(reg);
2582                 udelay(150);
2583         }
2584
2585 done:
2586         intel_crtc->active = false;
2587         intel_update_fbc(dev);
2588         intel_update_watermarks(dev);
2589         intel_clear_scanline_wait(dev);
2590 }
2591
2592 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2593 {
2594         /* XXX: When our outputs are all unaware of DPMS modes other than off
2595          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2596          */
2597         switch (mode) {
2598         case DRM_MODE_DPMS_ON:
2599         case DRM_MODE_DPMS_STANDBY:
2600         case DRM_MODE_DPMS_SUSPEND:
2601                 i9xx_crtc_enable(crtc);
2602                 break;
2603         case DRM_MODE_DPMS_OFF:
2604                 i9xx_crtc_disable(crtc);
2605                 break;
2606         }
2607 }
2608
2609 /**
2610  * Sets the power management mode of the pipe and plane.
2611  */
2612 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615         struct drm_i915_private *dev_priv = dev->dev_private;
2616         struct drm_i915_master_private *master_priv;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         int pipe = intel_crtc->pipe;
2619         bool enabled;
2620
2621         if (intel_crtc->dpms_mode == mode)
2622                 return;
2623
2624         intel_crtc->dpms_mode = mode;
2625
2626         dev_priv->display.dpms(crtc, mode);
2627
2628         if (!dev->primary->master)
2629                 return;
2630
2631         master_priv = dev->primary->master->driver_priv;
2632         if (!master_priv->sarea_priv)
2633                 return;
2634
2635         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2636
2637         switch (pipe) {
2638         case 0:
2639                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2640                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2641                 break;
2642         case 1:
2643                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2644                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2645                 break;
2646         default:
2647                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2648                 break;
2649         }
2650 }
2651
2652 static void intel_crtc_disable(struct drm_crtc *crtc)
2653 {
2654         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2655         struct drm_device *dev = crtc->dev;
2656
2657         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2658
2659         if (crtc->fb) {
2660                 mutex_lock(&dev->struct_mutex);
2661                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2662                 mutex_unlock(&dev->struct_mutex);
2663         }
2664 }
2665
2666 /* Prepare for a mode set.
2667  *
2668  * Note we could be a lot smarter here.  We need to figure out which outputs
2669  * will be enabled, which disabled (in short, how the config will changes)
2670  * and perform the minimum necessary steps to accomplish that, e.g. updating
2671  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2672  * panel fitting is in the proper state, etc.
2673  */
2674 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2675 {
2676         i9xx_crtc_disable(crtc);
2677 }
2678
2679 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2680 {
2681         i9xx_crtc_enable(crtc);
2682 }
2683
2684 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2685 {
2686         ironlake_crtc_disable(crtc);
2687 }
2688
2689 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2690 {
2691         ironlake_crtc_enable(crtc);
2692 }
2693
2694 void intel_encoder_prepare (struct drm_encoder *encoder)
2695 {
2696         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2697         /* lvds has its own version of prepare see intel_lvds_prepare */
2698         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2699 }
2700
2701 void intel_encoder_commit (struct drm_encoder *encoder)
2702 {
2703         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2704         /* lvds has its own version of commit see intel_lvds_commit */
2705         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2706 }
2707
2708 void intel_encoder_destroy(struct drm_encoder *encoder)
2709 {
2710         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2711
2712         drm_encoder_cleanup(encoder);
2713         kfree(intel_encoder);
2714 }
2715
2716 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2717                                   struct drm_display_mode *mode,
2718                                   struct drm_display_mode *adjusted_mode)
2719 {
2720         struct drm_device *dev = crtc->dev;
2721
2722         if (HAS_PCH_SPLIT(dev)) {
2723                 /* FDI link clock is fixed at 2.7G */
2724                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2725                         return false;
2726         }
2727
2728         /* XXX some encoders set the crtcinfo, others don't.
2729          * Obviously we need some form of conflict resolution here...
2730          */
2731         if (adjusted_mode->crtc_htotal == 0)
2732                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2733
2734         return true;
2735 }
2736
2737 static int i945_get_display_clock_speed(struct drm_device *dev)
2738 {
2739         return 400000;
2740 }
2741
2742 static int i915_get_display_clock_speed(struct drm_device *dev)
2743 {
2744         return 333000;
2745 }
2746
2747 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2748 {
2749         return 200000;
2750 }
2751
2752 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2753 {
2754         u16 gcfgc = 0;
2755
2756         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2757
2758         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2759                 return 133000;
2760         else {
2761                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2762                 case GC_DISPLAY_CLOCK_333_MHZ:
2763                         return 333000;
2764                 default:
2765                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2766                         return 190000;
2767                 }
2768         }
2769 }
2770
2771 static int i865_get_display_clock_speed(struct drm_device *dev)
2772 {
2773         return 266000;
2774 }
2775
2776 static int i855_get_display_clock_speed(struct drm_device *dev)
2777 {
2778         u16 hpllcc = 0;
2779         /* Assume that the hardware is in the high speed state.  This
2780          * should be the default.
2781          */
2782         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2783         case GC_CLOCK_133_200:
2784         case GC_CLOCK_100_200:
2785                 return 200000;
2786         case GC_CLOCK_166_250:
2787                 return 250000;
2788         case GC_CLOCK_100_133:
2789                 return 133000;
2790         }
2791
2792         /* Shouldn't happen */
2793         return 0;
2794 }
2795
2796 static int i830_get_display_clock_speed(struct drm_device *dev)
2797 {
2798         return 133000;
2799 }
2800
2801 struct fdi_m_n {
2802         u32        tu;
2803         u32        gmch_m;
2804         u32        gmch_n;
2805         u32        link_m;
2806         u32        link_n;
2807 };
2808
2809 static void
2810 fdi_reduce_ratio(u32 *num, u32 *den)
2811 {
2812         while (*num > 0xffffff || *den > 0xffffff) {
2813                 *num >>= 1;
2814                 *den >>= 1;
2815         }
2816 }
2817
2818 static void
2819 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2820                      int link_clock, struct fdi_m_n *m_n)
2821 {
2822         m_n->tu = 64; /* default size */
2823
2824         /* BUG_ON(pixel_clock > INT_MAX / 36); */
2825         m_n->gmch_m = bits_per_pixel * pixel_clock;
2826         m_n->gmch_n = link_clock * nlanes * 8;
2827         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2828
2829         m_n->link_m = pixel_clock;
2830         m_n->link_n = link_clock;
2831         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2832 }
2833
2834
2835 struct intel_watermark_params {
2836         unsigned long fifo_size;
2837         unsigned long max_wm;
2838         unsigned long default_wm;
2839         unsigned long guard_size;
2840         unsigned long cacheline_size;
2841 };
2842
2843 /* Pineview has different values for various configs */
2844 static struct intel_watermark_params pineview_display_wm = {
2845         PINEVIEW_DISPLAY_FIFO,
2846         PINEVIEW_MAX_WM,
2847         PINEVIEW_DFT_WM,
2848         PINEVIEW_GUARD_WM,
2849         PINEVIEW_FIFO_LINE_SIZE
2850 };
2851 static struct intel_watermark_params pineview_display_hplloff_wm = {
2852         PINEVIEW_DISPLAY_FIFO,
2853         PINEVIEW_MAX_WM,
2854         PINEVIEW_DFT_HPLLOFF_WM,
2855         PINEVIEW_GUARD_WM,
2856         PINEVIEW_FIFO_LINE_SIZE
2857 };
2858 static struct intel_watermark_params pineview_cursor_wm = {
2859         PINEVIEW_CURSOR_FIFO,
2860         PINEVIEW_CURSOR_MAX_WM,
2861         PINEVIEW_CURSOR_DFT_WM,
2862         PINEVIEW_CURSOR_GUARD_WM,
2863         PINEVIEW_FIFO_LINE_SIZE,
2864 };
2865 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2866         PINEVIEW_CURSOR_FIFO,
2867         PINEVIEW_CURSOR_MAX_WM,
2868         PINEVIEW_CURSOR_DFT_WM,
2869         PINEVIEW_CURSOR_GUARD_WM,
2870         PINEVIEW_FIFO_LINE_SIZE
2871 };
2872 static struct intel_watermark_params g4x_wm_info = {
2873         G4X_FIFO_SIZE,
2874         G4X_MAX_WM,
2875         G4X_MAX_WM,
2876         2,
2877         G4X_FIFO_LINE_SIZE,
2878 };
2879 static struct intel_watermark_params g4x_cursor_wm_info = {
2880         I965_CURSOR_FIFO,
2881         I965_CURSOR_MAX_WM,
2882         I965_CURSOR_DFT_WM,
2883         2,
2884         G4X_FIFO_LINE_SIZE,
2885 };
2886 static struct intel_watermark_params i965_cursor_wm_info = {
2887         I965_CURSOR_FIFO,
2888         I965_CURSOR_MAX_WM,
2889         I965_CURSOR_DFT_WM,
2890         2,
2891         I915_FIFO_LINE_SIZE,
2892 };
2893 static struct intel_watermark_params i945_wm_info = {
2894         I945_FIFO_SIZE,
2895         I915_MAX_WM,
2896         1,
2897         2,
2898         I915_FIFO_LINE_SIZE
2899 };
2900 static struct intel_watermark_params i915_wm_info = {
2901         I915_FIFO_SIZE,
2902         I915_MAX_WM,
2903         1,
2904         2,
2905         I915_FIFO_LINE_SIZE
2906 };
2907 static struct intel_watermark_params i855_wm_info = {
2908         I855GM_FIFO_SIZE,
2909         I915_MAX_WM,
2910         1,
2911         2,
2912         I830_FIFO_LINE_SIZE
2913 };
2914 static struct intel_watermark_params i830_wm_info = {
2915         I830_FIFO_SIZE,
2916         I915_MAX_WM,
2917         1,
2918         2,
2919         I830_FIFO_LINE_SIZE
2920 };
2921
2922 static struct intel_watermark_params ironlake_display_wm_info = {
2923         ILK_DISPLAY_FIFO,
2924         ILK_DISPLAY_MAXWM,
2925         ILK_DISPLAY_DFTWM,
2926         2,
2927         ILK_FIFO_LINE_SIZE
2928 };
2929
2930 static struct intel_watermark_params ironlake_cursor_wm_info = {
2931         ILK_CURSOR_FIFO,
2932         ILK_CURSOR_MAXWM,
2933         ILK_CURSOR_DFTWM,
2934         2,
2935         ILK_FIFO_LINE_SIZE
2936 };
2937
2938 static struct intel_watermark_params ironlake_display_srwm_info = {
2939         ILK_DISPLAY_SR_FIFO,
2940         ILK_DISPLAY_MAX_SRWM,
2941         ILK_DISPLAY_DFT_SRWM,
2942         2,
2943         ILK_FIFO_LINE_SIZE
2944 };
2945
2946 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2947         ILK_CURSOR_SR_FIFO,
2948         ILK_CURSOR_MAX_SRWM,
2949         ILK_CURSOR_DFT_SRWM,
2950         2,
2951         ILK_FIFO_LINE_SIZE
2952 };
2953
2954 static struct intel_watermark_params sandybridge_display_wm_info = {
2955         SNB_DISPLAY_FIFO,
2956         SNB_DISPLAY_MAXWM,
2957         SNB_DISPLAY_DFTWM,
2958         2,
2959         SNB_FIFO_LINE_SIZE
2960 };
2961
2962 static struct intel_watermark_params sandybridge_cursor_wm_info = {
2963         SNB_CURSOR_FIFO,
2964         SNB_CURSOR_MAXWM,
2965         SNB_CURSOR_DFTWM,
2966         2,
2967         SNB_FIFO_LINE_SIZE
2968 };
2969
2970 static struct intel_watermark_params sandybridge_display_srwm_info = {
2971         SNB_DISPLAY_SR_FIFO,
2972         SNB_DISPLAY_MAX_SRWM,
2973         SNB_DISPLAY_DFT_SRWM,
2974         2,
2975         SNB_FIFO_LINE_SIZE
2976 };
2977
2978 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2979         SNB_CURSOR_SR_FIFO,
2980         SNB_CURSOR_MAX_SRWM,
2981         SNB_CURSOR_DFT_SRWM,
2982         2,
2983         SNB_FIFO_LINE_SIZE
2984 };
2985
2986
2987 /**
2988  * intel_calculate_wm - calculate watermark level
2989  * @clock_in_khz: pixel clock
2990  * @wm: chip FIFO params
2991  * @pixel_size: display pixel size
2992  * @latency_ns: memory latency for the platform
2993  *
2994  * Calculate the watermark level (the level at which the display plane will
2995  * start fetching from memory again).  Each chip has a different display
2996  * FIFO size and allocation, so the caller needs to figure that out and pass
2997  * in the correct intel_watermark_params structure.
2998  *
2999  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3000  * on the pixel size.  When it reaches the watermark level, it'll start
3001  * fetching FIFO line sized based chunks from memory until the FIFO fills
3002  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3003  * will occur, and a display engine hang could result.
3004  */
3005 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3006                                         struct intel_watermark_params *wm,
3007                                         int pixel_size,
3008                                         unsigned long latency_ns)
3009 {
3010         long entries_required, wm_size;
3011
3012         /*
3013          * Note: we need to make sure we don't overflow for various clock &
3014          * latency values.
3015          * clocks go from a few thousand to several hundred thousand.
3016          * latency is usually a few thousand
3017          */
3018         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3019                 1000;
3020         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3021
3022         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3023
3024         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
3025
3026         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3027
3028         /* Don't promote wm_size to unsigned... */
3029         if (wm_size > (long)wm->max_wm)
3030                 wm_size = wm->max_wm;
3031         if (wm_size <= 0)
3032                 wm_size = wm->default_wm;
3033         return wm_size;
3034 }
3035
3036 struct cxsr_latency {
3037         int is_desktop;
3038         int is_ddr3;
3039         unsigned long fsb_freq;
3040         unsigned long mem_freq;
3041         unsigned long display_sr;
3042         unsigned long display_hpll_disable;
3043         unsigned long cursor_sr;
3044         unsigned long cursor_hpll_disable;
3045 };
3046
3047 static const struct cxsr_latency cxsr_latency_table[] = {
3048         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3049         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3050         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3051         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3052         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3053
3054         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3055         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3056         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3057         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3058         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3059
3060         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3061         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3062         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3063         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3064         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3065
3066         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3067         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3068         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3069         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3070         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3071
3072         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3073         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3074         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3075         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3076         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3077
3078         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3079         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3080         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3081         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3082         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3083 };
3084
3085 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3086                                                          int is_ddr3,
3087                                                          int fsb,
3088                                                          int mem)
3089 {
3090         const struct cxsr_latency *latency;
3091         int i;
3092
3093         if (fsb == 0 || mem == 0)
3094                 return NULL;
3095
3096         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3097                 latency = &cxsr_latency_table[i];
3098                 if (is_desktop == latency->is_desktop &&
3099                     is_ddr3 == latency->is_ddr3 &&
3100                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3101                         return latency;
3102         }
3103
3104         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3105
3106         return NULL;
3107 }
3108
3109 static void pineview_disable_cxsr(struct drm_device *dev)
3110 {
3111         struct drm_i915_private *dev_priv = dev->dev_private;
3112
3113         /* deactivate cxsr */
3114         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3115 }
3116
3117 /*
3118  * Latency for FIFO fetches is dependent on several factors:
3119  *   - memory configuration (speed, channels)
3120  *   - chipset
3121  *   - current MCH state
3122  * It can be fairly high in some situations, so here we assume a fairly
3123  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3124  * set this value too high, the FIFO will fetch frequently to stay full)
3125  * and power consumption (set it too low to save power and we might see
3126  * FIFO underruns and display "flicker").
3127  *
3128  * A value of 5us seems to be a good balance; safe for very low end
3129  * platforms but not overly aggressive on lower latency configs.
3130  */
3131 static const int latency_ns = 5000;
3132
3133 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3134 {
3135         struct drm_i915_private *dev_priv = dev->dev_private;
3136         uint32_t dsparb = I915_READ(DSPARB);
3137         int size;
3138
3139         size = dsparb & 0x7f;
3140         if (plane)
3141                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3142
3143         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3144                       plane ? "B" : "A", size);
3145
3146         return size;
3147 }
3148
3149 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3150 {
3151         struct drm_i915_private *dev_priv = dev->dev_private;
3152         uint32_t dsparb = I915_READ(DSPARB);
3153         int size;
3154
3155         size = dsparb & 0x1ff;
3156         if (plane)
3157                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3158         size >>= 1; /* Convert to cachelines */
3159
3160         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3161                       plane ? "B" : "A", size);
3162
3163         return size;
3164 }
3165
3166 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3167 {
3168         struct drm_i915_private *dev_priv = dev->dev_private;
3169         uint32_t dsparb = I915_READ(DSPARB);
3170         int size;
3171
3172         size = dsparb & 0x7f;
3173         size >>= 2; /* Convert to cachelines */
3174
3175         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3176                       plane ? "B" : "A",
3177                       size);
3178
3179         return size;
3180 }
3181
3182 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3183 {
3184         struct drm_i915_private *dev_priv = dev->dev_private;
3185         uint32_t dsparb = I915_READ(DSPARB);
3186         int size;
3187
3188         size = dsparb & 0x7f;
3189         size >>= 1; /* Convert to cachelines */
3190
3191         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3192                       plane ? "B" : "A", size);
3193
3194         return size;
3195 }
3196
3197 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3198                                int planeb_clock, int sr_hdisplay, int unused,
3199                                int pixel_size)
3200 {
3201         struct drm_i915_private *dev_priv = dev->dev_private;
3202         const struct cxsr_latency *latency;
3203         u32 reg;
3204         unsigned long wm;
3205         int sr_clock;
3206
3207         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3208                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3209         if (!latency) {
3210                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3211                 pineview_disable_cxsr(dev);
3212                 return;
3213         }
3214
3215         if (!planea_clock || !planeb_clock) {
3216                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3217
3218                 /* Display SR */
3219                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3220                                         pixel_size, latency->display_sr);
3221                 reg = I915_READ(DSPFW1);
3222                 reg &= ~DSPFW_SR_MASK;
3223                 reg |= wm << DSPFW_SR_SHIFT;
3224                 I915_WRITE(DSPFW1, reg);
3225                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3226
3227                 /* cursor SR */
3228                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3229                                         pixel_size, latency->cursor_sr);
3230                 reg = I915_READ(DSPFW3);
3231                 reg &= ~DSPFW_CURSOR_SR_MASK;
3232                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3233                 I915_WRITE(DSPFW3, reg);
3234
3235                 /* Display HPLL off SR */
3236                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3237                                         pixel_size, latency->display_hpll_disable);
3238                 reg = I915_READ(DSPFW3);
3239                 reg &= ~DSPFW_HPLL_SR_MASK;
3240                 reg |= wm & DSPFW_HPLL_SR_MASK;
3241                 I915_WRITE(DSPFW3, reg);
3242
3243                 /* cursor HPLL off SR */
3244                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3245                                         pixel_size, latency->cursor_hpll_disable);
3246                 reg = I915_READ(DSPFW3);
3247                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3248                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3249                 I915_WRITE(DSPFW3, reg);
3250                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3251
3252                 /* activate cxsr */
3253                 I915_WRITE(DSPFW3,
3254                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3255                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3256         } else {
3257                 pineview_disable_cxsr(dev);
3258                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3259         }
3260 }
3261
3262 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3263                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3264                           int pixel_size)
3265 {
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         int total_size, cacheline_size;
3268         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3269         struct intel_watermark_params planea_params, planeb_params;
3270         unsigned long line_time_us;
3271         int sr_clock, sr_entries = 0, entries_required;
3272
3273         /* Create copies of the base settings for each pipe */
3274         planea_params = planeb_params = g4x_wm_info;
3275
3276         /* Grab a couple of global values before we overwrite them */
3277         total_size = planea_params.fifo_size;
3278         cacheline_size = planea_params.cacheline_size;
3279
3280         /*
3281          * Note: we need to make sure we don't overflow for various clock &
3282          * latency values.
3283          * clocks go from a few thousand to several hundred thousand.
3284          * latency is usually a few thousand
3285          */
3286         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3287                 1000;
3288         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3289         planea_wm = entries_required + planea_params.guard_size;
3290
3291         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3292                 1000;
3293         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3294         planeb_wm = entries_required + planeb_params.guard_size;
3295
3296         cursora_wm = cursorb_wm = 16;
3297         cursor_sr = 32;
3298
3299         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3300
3301         /* Calc sr entries for one plane configs */
3302         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3303                 /* self-refresh has much higher latency */
3304                 static const int sr_latency_ns = 12000;
3305
3306                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3307                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3308
3309                 /* Use ns/us then divide to preserve precision */
3310                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3311                         pixel_size * sr_hdisplay;
3312                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3313
3314                 entries_required = (((sr_latency_ns / line_time_us) +
3315                                      1000) / 1000) * pixel_size * 64;
3316                 entries_required = DIV_ROUND_UP(entries_required,
3317                                                 g4x_cursor_wm_info.cacheline_size);
3318                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3319
3320                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3321                         cursor_sr = g4x_cursor_wm_info.max_wm;
3322                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3323                               "cursor %d\n", sr_entries, cursor_sr);
3324
3325                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3326         } else {
3327                 /* Turn off self refresh if both pipes are enabled */
3328                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3329                            & ~FW_BLC_SELF_EN);
3330         }
3331
3332         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3333                   planea_wm, planeb_wm, sr_entries);
3334
3335         planea_wm &= 0x3f;
3336         planeb_wm &= 0x3f;
3337
3338         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3339                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3340                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3341         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3342                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3343         /* HPLL off in SR has some issues on G4x... disable it */
3344         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3345                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3346 }
3347
3348 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3349                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3350                            int pixel_size)
3351 {
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         unsigned long line_time_us;
3354         int sr_clock, sr_entries, srwm = 1;
3355         int cursor_sr = 16;
3356
3357         /* Calc sr entries for one plane configs */
3358         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3359                 /* self-refresh has much higher latency */
3360                 static const int sr_latency_ns = 12000;
3361
3362                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3363                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3364
3365                 /* Use ns/us then divide to preserve precision */
3366                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3367                         pixel_size * sr_hdisplay;
3368                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3369                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3370                 srwm = I965_FIFO_SIZE - sr_entries;
3371                 if (srwm < 0)
3372                         srwm = 1;
3373                 srwm &= 0x1ff;
3374
3375                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3376                         pixel_size * 64;
3377                 sr_entries = DIV_ROUND_UP(sr_entries,
3378                                           i965_cursor_wm_info.cacheline_size);
3379                 cursor_sr = i965_cursor_wm_info.fifo_size -
3380                         (sr_entries + i965_cursor_wm_info.guard_size);
3381
3382                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3383                         cursor_sr = i965_cursor_wm_info.max_wm;
3384
3385                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3386                               "cursor %d\n", srwm, cursor_sr);
3387
3388                 if (IS_CRESTLINE(dev))
3389                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3390         } else {
3391                 /* Turn off self refresh if both pipes are enabled */
3392                 if (IS_CRESTLINE(dev))
3393                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3394                                    & ~FW_BLC_SELF_EN);
3395         }
3396
3397         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3398                       srwm);
3399
3400         /* 965 has limitations... */
3401         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3402                    (8 << 0));
3403         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3404         /* update cursor SR watermark */
3405         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3406 }
3407
3408 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3409                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3410                            int pixel_size)
3411 {
3412         struct drm_i915_private *dev_priv = dev->dev_private;
3413         uint32_t fwater_lo;
3414         uint32_t fwater_hi;
3415         int total_size, cacheline_size, cwm, srwm = 1;
3416         int planea_wm, planeb_wm;
3417         struct intel_watermark_params planea_params, planeb_params;
3418         unsigned long line_time_us;
3419         int sr_clock, sr_entries = 0;
3420
3421         /* Create copies of the base settings for each pipe */
3422         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3423                 planea_params = planeb_params = i945_wm_info;
3424         else if (!IS_GEN2(dev))
3425                 planea_params = planeb_params = i915_wm_info;
3426         else
3427                 planea_params = planeb_params = i855_wm_info;
3428
3429         /* Grab a couple of global values before we overwrite them */
3430         total_size = planea_params.fifo_size;
3431         cacheline_size = planea_params.cacheline_size;
3432
3433         /* Update per-plane FIFO sizes */
3434         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3435         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3436
3437         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3438                                        pixel_size, latency_ns);
3439         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3440                                        pixel_size, latency_ns);
3441         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3442
3443         /*
3444          * Overlay gets an aggressive default since video jitter is bad.
3445          */
3446         cwm = 2;
3447
3448         /* Calc sr entries for one plane configs */
3449         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3450             (!planea_clock || !planeb_clock)) {
3451                 /* self-refresh has much higher latency */
3452                 static const int sr_latency_ns = 6000;
3453
3454                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3455                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3456
3457                 /* Use ns/us then divide to preserve precision */
3458                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3459                         pixel_size * sr_hdisplay;
3460                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3461                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3462                 srwm = total_size - sr_entries;
3463                 if (srwm < 0)
3464                         srwm = 1;
3465
3466                 if (IS_I945G(dev) || IS_I945GM(dev))
3467                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3468                 else if (IS_I915GM(dev)) {
3469                         /* 915M has a smaller SRWM field */
3470                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3471                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3472                 }
3473         } else {
3474                 /* Turn off self refresh if both pipes are enabled */
3475                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3476                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3477                                    & ~FW_BLC_SELF_EN);
3478                 } else if (IS_I915GM(dev)) {
3479                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3480                 }
3481         }
3482
3483         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3484                       planea_wm, planeb_wm, cwm, srwm);
3485
3486         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3487         fwater_hi = (cwm & 0x1f);
3488
3489         /* Set request length to 8 cachelines per fetch */
3490         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3491         fwater_hi = fwater_hi | (1 << 8);
3492
3493         I915_WRITE(FW_BLC, fwater_lo);
3494         I915_WRITE(FW_BLC2, fwater_hi);
3495 }
3496
3497 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3498                            int unused2, int unused3, int pixel_size)
3499 {
3500         struct drm_i915_private *dev_priv = dev->dev_private;
3501         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3502         int planea_wm;
3503
3504         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3505
3506         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3507                                        pixel_size, latency_ns);
3508         fwater_lo |= (3<<8) | planea_wm;
3509
3510         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3511
3512         I915_WRITE(FW_BLC, fwater_lo);
3513 }
3514
3515 #define ILK_LP0_PLANE_LATENCY           700
3516 #define ILK_LP0_CURSOR_LATENCY          1300
3517
3518 static bool ironlake_compute_wm0(struct drm_device *dev,
3519                                  int pipe,
3520                                  const struct intel_watermark_params *display,
3521                                  int display_latency_ns,
3522                                  const struct intel_watermark_params *cursor,
3523                                  int cursor_latency_ns,
3524                                  int *plane_wm,
3525                                  int *cursor_wm)
3526 {
3527         struct drm_crtc *crtc;
3528         int htotal, hdisplay, clock, pixel_size;
3529         int line_time_us, line_count;
3530         int entries, tlb_miss;
3531
3532         crtc = intel_get_crtc_for_pipe(dev, pipe);
3533         if (crtc->fb == NULL || !crtc->enabled)
3534                 return false;
3535
3536         htotal = crtc->mode.htotal;
3537         hdisplay = crtc->mode.hdisplay;
3538         clock = crtc->mode.clock;
3539         pixel_size = crtc->fb->bits_per_pixel / 8;
3540
3541         /* Use the small buffer method to calculate plane watermark */
3542         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3543         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3544         if (tlb_miss > 0)
3545                 entries += tlb_miss;
3546         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3547         *plane_wm = entries + display->guard_size;
3548         if (*plane_wm > (int)display->max_wm)
3549                 *plane_wm = display->max_wm;
3550
3551         /* Use the large buffer method to calculate cursor watermark */
3552         line_time_us = ((htotal * 1000) / clock);
3553         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3554         entries = line_count * 64 * pixel_size;
3555         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3556         if (tlb_miss > 0)
3557                 entries += tlb_miss;
3558         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3559         *cursor_wm = entries + cursor->guard_size;
3560         if (*cursor_wm > (int)cursor->max_wm)
3561                 *cursor_wm = (int)cursor->max_wm;
3562
3563         return true;
3564 }
3565
3566 /*
3567  * Check the wm result.
3568  *
3569  * If any calculated watermark values is larger than the maximum value that
3570  * can be programmed into the associated watermark register, that watermark
3571  * must be disabled.
3572  */
3573 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3574                                 int fbc_wm, int display_wm, int cursor_wm,
3575                                 const struct intel_watermark_params *display,
3576                                 const struct intel_watermark_params *cursor)
3577 {
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579
3580         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3581                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3582
3583         if (fbc_wm > SNB_FBC_MAX_SRWM) {
3584                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3585                               fbc_wm, SNB_FBC_MAX_SRWM, level);
3586
3587                 /* fbc has it's own way to disable FBC WM */
3588                 I915_WRITE(DISP_ARB_CTL,
3589                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3590                 return false;
3591         }
3592
3593         if (display_wm > display->max_wm) {
3594                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3595                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
3596                 return false;
3597         }
3598
3599         if (cursor_wm > cursor->max_wm) {
3600                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3601                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3602                 return false;
3603         }
3604
3605         if (!(fbc_wm || display_wm || cursor_wm)) {
3606                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3607                 return false;
3608         }
3609
3610         return true;
3611 }
3612
3613 /*
3614  * Compute watermark values of WM[1-3],
3615  */
3616 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3617                                   int hdisplay, int htotal,
3618                                   int pixel_size, int clock, int latency_ns,
3619                                   const struct intel_watermark_params *display,
3620                                   const struct intel_watermark_params *cursor,
3621                                   int *fbc_wm, int *display_wm, int *cursor_wm)
3622 {
3623
3624         unsigned long line_time_us;
3625         int line_count, line_size;
3626         int small, large;
3627         int entries;
3628
3629         if (!latency_ns) {
3630                 *fbc_wm = *display_wm = *cursor_wm = 0;
3631                 return false;
3632         }
3633
3634         line_time_us = (htotal * 1000) / clock;
3635         line_count = (latency_ns / line_time_us + 1000) / 1000;
3636         line_size = hdisplay * pixel_size;
3637
3638         /* Use the minimum of the small and large buffer method for primary */
3639         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3640         large = line_count * line_size;
3641
3642         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3643         *display_wm = entries + display->guard_size;
3644
3645         /*
3646          * Spec says:
3647          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3648          */
3649         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3650
3651         /* calculate the self-refresh watermark for display cursor */
3652         entries = line_count * pixel_size * 64;
3653         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3654         *cursor_wm = entries + cursor->guard_size;
3655
3656         return ironlake_check_srwm(dev, level,
3657                                    *fbc_wm, *display_wm, *cursor_wm,
3658                                    display, cursor);
3659 }
3660
3661 static void ironlake_update_wm(struct drm_device *dev,
3662                                int planea_clock, int planeb_clock,
3663                                int hdisplay, int htotal,
3664                                int pixel_size)
3665 {
3666         struct drm_i915_private *dev_priv = dev->dev_private;
3667         int fbc_wm, plane_wm, cursor_wm, enabled;
3668         int clock;
3669
3670         enabled = 0;
3671         if (ironlake_compute_wm0(dev, 0,
3672                                  &ironlake_display_wm_info,
3673                                  ILK_LP0_PLANE_LATENCY,
3674                                  &ironlake_cursor_wm_info,
3675                                  ILK_LP0_CURSOR_LATENCY,
3676                                  &plane_wm, &cursor_wm)) {
3677                 I915_WRITE(WM0_PIPEA_ILK,
3678                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3679                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3680                               " plane %d, " "cursor: %d\n",
3681                               plane_wm, cursor_wm);
3682                 enabled++;
3683         }
3684
3685         if (ironlake_compute_wm0(dev, 1,
3686                                  &ironlake_display_wm_info,
3687                                  ILK_LP0_PLANE_LATENCY,
3688                                  &ironlake_cursor_wm_info,
3689                                  ILK_LP0_CURSOR_LATENCY,
3690                                  &plane_wm, &cursor_wm)) {
3691                 I915_WRITE(WM0_PIPEB_ILK,
3692                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3693                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3694                               " plane %d, cursor: %d\n",
3695                               plane_wm, cursor_wm);
3696                 enabled++;
3697         }
3698
3699         /*
3700          * Calculate and update the self-refresh watermark only when one
3701          * display plane is used.
3702          */
3703         I915_WRITE(WM3_LP_ILK, 0);
3704         I915_WRITE(WM2_LP_ILK, 0);
3705         I915_WRITE(WM1_LP_ILK, 0);
3706
3707         if (enabled != 1)
3708                 return;
3709
3710         clock = planea_clock ? planea_clock : planeb_clock;
3711
3712         /* WM1 */
3713         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3714                                    clock, ILK_READ_WM1_LATENCY() * 500,
3715                                    &ironlake_display_srwm_info,
3716                                    &ironlake_cursor_srwm_info,
3717                                    &fbc_wm, &plane_wm, &cursor_wm))
3718                 return;
3719
3720         I915_WRITE(WM1_LP_ILK,
3721                    WM1_LP_SR_EN |
3722                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3723                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3724                    (plane_wm << WM1_LP_SR_SHIFT) |
3725                    cursor_wm);
3726
3727         /* WM2 */
3728         if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
3729                                    clock, ILK_READ_WM2_LATENCY() * 500,
3730                                    &ironlake_display_srwm_info,
3731                                    &ironlake_cursor_srwm_info,
3732                                    &fbc_wm, &plane_wm, &cursor_wm))
3733                 return;
3734
3735         I915_WRITE(WM2_LP_ILK,
3736                    WM2_LP_EN |
3737                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3738                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3739                    (plane_wm << WM1_LP_SR_SHIFT) |
3740                    cursor_wm);
3741
3742         /*
3743          * WM3 is unsupported on ILK, probably because we don't have latency
3744          * data for that power state
3745          */
3746 }
3747
3748 static void sandybridge_update_wm(struct drm_device *dev,
3749                                int planea_clock, int planeb_clock,
3750                                int hdisplay, int htotal,
3751                                int pixel_size)
3752 {
3753         struct drm_i915_private *dev_priv = dev->dev_private;
3754         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
3755         int fbc_wm, plane_wm, cursor_wm, enabled;
3756         int clock;
3757
3758         enabled = 0;
3759         if (ironlake_compute_wm0(dev, 0,
3760                                  &sandybridge_display_wm_info, latency,
3761                                  &sandybridge_cursor_wm_info, latency,
3762                                  &plane_wm, &cursor_wm)) {
3763                 I915_WRITE(WM0_PIPEA_ILK,
3764                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3765                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3766                               " plane %d, " "cursor: %d\n",
3767                               plane_wm, cursor_wm);
3768                 enabled++;
3769         }
3770
3771         if (ironlake_compute_wm0(dev, 1,
3772                                  &sandybridge_display_wm_info, latency,
3773                                  &sandybridge_cursor_wm_info, latency,
3774                                  &plane_wm, &cursor_wm)) {
3775                 I915_WRITE(WM0_PIPEB_ILK,
3776                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3777                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3778                               " plane %d, cursor: %d\n",
3779                               plane_wm, cursor_wm);
3780                 enabled++;
3781         }
3782
3783         /*
3784          * Calculate and update the self-refresh watermark only when one
3785          * display plane is used.
3786          *
3787          * SNB support 3 levels of watermark.
3788          *
3789          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3790          * and disabled in the descending order
3791          *
3792          */
3793         I915_WRITE(WM3_LP_ILK, 0);
3794         I915_WRITE(WM2_LP_ILK, 0);
3795         I915_WRITE(WM1_LP_ILK, 0);
3796
3797         if (enabled != 1)
3798                 return;
3799
3800         clock = planea_clock ? planea_clock : planeb_clock;
3801
3802         /* WM1 */
3803         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3804                                    clock, SNB_READ_WM1_LATENCY() * 500,
3805                                    &sandybridge_display_srwm_info,
3806                                    &sandybridge_cursor_srwm_info,
3807                                    &fbc_wm, &plane_wm, &cursor_wm))
3808                 return;
3809
3810         I915_WRITE(WM1_LP_ILK,
3811                    WM1_LP_SR_EN |
3812                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3813                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3814                    (plane_wm << WM1_LP_SR_SHIFT) |
3815                    cursor_wm);
3816
3817         /* WM2 */
3818         if (!ironlake_compute_srwm(dev, 2,
3819                                    hdisplay, htotal, pixel_size,
3820                                    clock, SNB_READ_WM2_LATENCY() * 500,
3821                                    &sandybridge_display_srwm_info,
3822                                    &sandybridge_cursor_srwm_info,
3823                                    &fbc_wm, &plane_wm, &cursor_wm))
3824                 return;
3825
3826         I915_WRITE(WM2_LP_ILK,
3827                    WM2_LP_EN |
3828                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3829                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3830                    (plane_wm << WM1_LP_SR_SHIFT) |
3831                    cursor_wm);
3832
3833         /* WM3 */
3834         if (!ironlake_compute_srwm(dev, 3,
3835                                    hdisplay, htotal, pixel_size,
3836                                    clock, SNB_READ_WM3_LATENCY() * 500,
3837                                    &sandybridge_display_srwm_info,
3838                                    &sandybridge_cursor_srwm_info,
3839                                    &fbc_wm, &plane_wm, &cursor_wm))
3840                 return;
3841
3842         I915_WRITE(WM3_LP_ILK,
3843                    WM3_LP_EN |
3844                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3845                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3846                    (plane_wm << WM1_LP_SR_SHIFT) |
3847                    cursor_wm);
3848 }
3849
3850 /**
3851  * intel_update_watermarks - update FIFO watermark values based on current modes
3852  *
3853  * Calculate watermark values for the various WM regs based on current mode
3854  * and plane configuration.
3855  *
3856  * There are several cases to deal with here:
3857  *   - normal (i.e. non-self-refresh)
3858  *   - self-refresh (SR) mode
3859  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3860  *   - lines are small relative to FIFO size (buffer can hold more than 2
3861  *     lines), so need to account for TLB latency
3862  *
3863  *   The normal calculation is:
3864  *     watermark = dotclock * bytes per pixel * latency
3865  *   where latency is platform & configuration dependent (we assume pessimal
3866  *   values here).
3867  *
3868  *   The SR calculation is:
3869  *     watermark = (trunc(latency/line time)+1) * surface width *
3870  *       bytes per pixel
3871  *   where
3872  *     line time = htotal / dotclock
3873  *     surface width = hdisplay for normal plane and 64 for cursor
3874  *   and latency is assumed to be high, as above.
3875  *
3876  * The final value programmed to the register should always be rounded up,
3877  * and include an extra 2 entries to account for clock crossings.
3878  *
3879  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3880  * to set the non-SR watermarks to 8.
3881  */
3882 static void intel_update_watermarks(struct drm_device *dev)
3883 {
3884         struct drm_i915_private *dev_priv = dev->dev_private;
3885         struct drm_crtc *crtc;
3886         int sr_hdisplay = 0;
3887         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3888         int enabled = 0, pixel_size = 0;
3889         int sr_htotal = 0;
3890
3891         if (!dev_priv->display.update_wm)
3892                 return;
3893
3894         /* Get the clock config from both planes */
3895         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3896                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897                 if (intel_crtc->active) {
3898                         enabled++;
3899                         if (intel_crtc->plane == 0) {
3900                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3901                                               intel_crtc->pipe, crtc->mode.clock);
3902                                 planea_clock = crtc->mode.clock;
3903                         } else {
3904                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3905                                               intel_crtc->pipe, crtc->mode.clock);
3906                                 planeb_clock = crtc->mode.clock;
3907                         }
3908                         sr_hdisplay = crtc->mode.hdisplay;
3909                         sr_clock = crtc->mode.clock;
3910                         sr_htotal = crtc->mode.htotal;
3911                         if (crtc->fb)
3912                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3913                         else
3914                                 pixel_size = 4; /* by default */
3915                 }
3916         }
3917
3918         if (enabled <= 0)
3919                 return;
3920
3921         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3922                                     sr_hdisplay, sr_htotal, pixel_size);
3923 }
3924
3925 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3926 {
3927         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
3928 }
3929
3930 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3931                                struct drm_display_mode *mode,
3932                                struct drm_display_mode *adjusted_mode,
3933                                int x, int y,
3934                                struct drm_framebuffer *old_fb)
3935 {
3936         struct drm_device *dev = crtc->dev;
3937         struct drm_i915_private *dev_priv = dev->dev_private;
3938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3939         int pipe = intel_crtc->pipe;
3940         int plane = intel_crtc->plane;
3941         u32 fp_reg, dpll_reg;
3942         int refclk, num_connectors = 0;
3943         intel_clock_t clock, reduced_clock;
3944         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3945         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3946         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3947         struct intel_encoder *has_edp_encoder = NULL;
3948         struct drm_mode_config *mode_config = &dev->mode_config;
3949         struct intel_encoder *encoder;
3950         const intel_limit_t *limit;
3951         int ret;
3952         struct fdi_m_n m_n = {0};
3953         u32 reg, temp;
3954         int target_clock;
3955
3956         drm_vblank_pre_modeset(dev, pipe);
3957
3958         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3959                 if (encoder->base.crtc != crtc)
3960                         continue;
3961
3962                 switch (encoder->type) {
3963                 case INTEL_OUTPUT_LVDS:
3964                         is_lvds = true;
3965                         break;
3966                 case INTEL_OUTPUT_SDVO:
3967                 case INTEL_OUTPUT_HDMI:
3968                         is_sdvo = true;
3969                         if (encoder->needs_tv_clock)
3970                                 is_tv = true;
3971                         break;
3972                 case INTEL_OUTPUT_DVO:
3973                         is_dvo = true;
3974                         break;
3975                 case INTEL_OUTPUT_TVOUT:
3976                         is_tv = true;
3977                         break;
3978                 case INTEL_OUTPUT_ANALOG:
3979                         is_crt = true;
3980                         break;
3981                 case INTEL_OUTPUT_DISPLAYPORT:
3982                         is_dp = true;
3983                         break;
3984                 case INTEL_OUTPUT_EDP:
3985                         has_edp_encoder = encoder;
3986                         break;
3987                 }
3988
3989                 num_connectors++;
3990         }
3991
3992         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3993                 refclk = dev_priv->lvds_ssc_freq * 1000;
3994                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3995                               refclk / 1000);
3996         } else if (!IS_GEN2(dev)) {
3997                 refclk = 96000;
3998                 if (HAS_PCH_SPLIT(dev) &&
3999                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4000                         refclk = 120000; /* 120Mhz refclk */
4001         } else {
4002                 refclk = 48000;
4003         }
4004
4005         /*
4006          * Returns a set of divisors for the desired target clock with the given
4007          * refclk, or FALSE.  The returned values represent the clock equation:
4008          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4009          */
4010         limit = intel_limit(crtc, refclk);
4011         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4012         if (!ok) {
4013                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4014                 drm_vblank_post_modeset(dev, pipe);
4015                 return -EINVAL;
4016         }
4017
4018         /* Ensure that the cursor is valid for the new mode before changing... */
4019         intel_crtc_update_cursor(crtc, true);
4020
4021         if (is_lvds && dev_priv->lvds_downclock_avail) {
4022                 has_reduced_clock = limit->find_pll(limit, crtc,
4023                                                     dev_priv->lvds_downclock,
4024                                                     refclk,
4025                                                     &reduced_clock);
4026                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4027                         /*
4028                          * If the different P is found, it means that we can't
4029                          * switch the display clock by using the FP0/FP1.
4030                          * In such case we will disable the LVDS downclock
4031                          * feature.
4032                          */
4033                         DRM_DEBUG_KMS("Different P is found for "
4034                                       "LVDS clock/downclock\n");
4035                         has_reduced_clock = 0;
4036                 }
4037         }
4038         /* SDVO TV has fixed PLL values depend on its clock range,
4039            this mirrors vbios setting. */
4040         if (is_sdvo && is_tv) {
4041                 if (adjusted_mode->clock >= 100000
4042                     && adjusted_mode->clock < 140500) {
4043                         clock.p1 = 2;
4044                         clock.p2 = 10;
4045                         clock.n = 3;
4046                         clock.m1 = 16;
4047                         clock.m2 = 8;
4048                 } else if (adjusted_mode->clock >= 140500
4049                            && adjusted_mode->clock <= 200000) {
4050                         clock.p1 = 1;
4051                         clock.p2 = 10;
4052                         clock.n = 6;
4053                         clock.m1 = 12;
4054                         clock.m2 = 8;
4055                 }
4056         }
4057
4058         /* FDI link */
4059         if (HAS_PCH_SPLIT(dev)) {
4060                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4061                 int lane = 0, link_bw, bpp;
4062                 /* CPU eDP doesn't require FDI link, so just set DP M/N
4063                    according to current link config */
4064                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4065                         target_clock = mode->clock;
4066                         intel_edp_link_config(has_edp_encoder,
4067                                               &lane, &link_bw);
4068                 } else {
4069                         /* [e]DP over FDI requires target mode clock
4070                            instead of link clock */
4071                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4072                                 target_clock = mode->clock;
4073                         else
4074                                 target_clock = adjusted_mode->clock;
4075
4076                         /* FDI is a binary signal running at ~2.7GHz, encoding
4077                          * each output octet as 10 bits. The actual frequency
4078                          * is stored as a divider into a 100MHz clock, and the
4079                          * mode pixel clock is stored in units of 1KHz.
4080                          * Hence the bw of each lane in terms of the mode signal
4081                          * is:
4082                          */
4083                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4084                 }
4085
4086                 /* determine panel color depth */
4087                 temp = I915_READ(PIPECONF(pipe));
4088                 temp &= ~PIPE_BPC_MASK;
4089                 if (is_lvds) {
4090                         /* the BPC will be 6 if it is 18-bit LVDS panel */
4091                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4092                                 temp |= PIPE_8BPC;
4093                         else
4094                                 temp |= PIPE_6BPC;
4095                 } else if (has_edp_encoder) {
4096                         switch (dev_priv->edp.bpp/3) {
4097                         case 8:
4098                                 temp |= PIPE_8BPC;
4099                                 break;
4100                         case 10:
4101                                 temp |= PIPE_10BPC;
4102                                 break;
4103                         case 6:
4104                                 temp |= PIPE_6BPC;
4105                                 break;
4106                         case 12:
4107                                 temp |= PIPE_12BPC;
4108                                 break;
4109                         }
4110                 } else
4111                         temp |= PIPE_8BPC;
4112                 I915_WRITE(PIPECONF(pipe), temp);
4113
4114                 switch (temp & PIPE_BPC_MASK) {
4115                 case PIPE_8BPC:
4116                         bpp = 24;
4117                         break;
4118                 case PIPE_10BPC:
4119                         bpp = 30;
4120                         break;
4121                 case PIPE_6BPC:
4122                         bpp = 18;
4123                         break;
4124                 case PIPE_12BPC:
4125                         bpp = 36;
4126                         break;
4127                 default:
4128                         DRM_ERROR("unknown pipe bpc value\n");
4129                         bpp = 24;
4130                 }
4131
4132                 if (!lane) {
4133                         /*
4134                          * Account for spread spectrum to avoid
4135                          * oversubscribing the link. Max center spread
4136                          * is 2.5%; use 5% for safety's sake.
4137                          */
4138                         u32 bps = target_clock * bpp * 21 / 20;
4139                         lane = bps / (link_bw * 8) + 1;
4140                 }
4141
4142                 intel_crtc->fdi_lanes = lane;
4143
4144                 if (pixel_multiplier > 1)
4145                         link_bw *= pixel_multiplier;
4146                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4147         }
4148
4149         /* Ironlake: try to setup display ref clock before DPLL
4150          * enabling. This is only under driver's control after
4151          * PCH B stepping, previous chipset stepping should be
4152          * ignoring this setting.
4153          */
4154         if (HAS_PCH_SPLIT(dev)) {
4155                 temp = I915_READ(PCH_DREF_CONTROL);
4156                 /* Always enable nonspread source */
4157                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4158                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4159                 temp &= ~DREF_SSC_SOURCE_MASK;
4160                 temp |= DREF_SSC_SOURCE_ENABLE;
4161                 I915_WRITE(PCH_DREF_CONTROL, temp);
4162
4163                 POSTING_READ(PCH_DREF_CONTROL);
4164                 udelay(200);
4165
4166                 if (has_edp_encoder) {
4167                         if (intel_panel_use_ssc(dev_priv)) {
4168                                 temp |= DREF_SSC1_ENABLE;
4169                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4170
4171                                 POSTING_READ(PCH_DREF_CONTROL);
4172                                 udelay(200);
4173                         }
4174                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4175
4176                         /* Enable CPU source on CPU attached eDP */
4177                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4178                                 if (intel_panel_use_ssc(dev_priv))
4179                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4180                                 else
4181                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4182                         } else {
4183                                 /* Enable SSC on PCH eDP if needed */
4184                                 if (intel_panel_use_ssc(dev_priv)) {
4185                                         DRM_ERROR("enabling SSC on PCH\n");
4186                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4187                                 }
4188                         }
4189                         I915_WRITE(PCH_DREF_CONTROL, temp);
4190                         POSTING_READ(PCH_DREF_CONTROL);
4191                         udelay(200);
4192                 }
4193         }
4194
4195         if (IS_PINEVIEW(dev)) {
4196                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4197                 if (has_reduced_clock)
4198                         fp2 = (1 << reduced_clock.n) << 16 |
4199                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4200         } else {
4201                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4202                 if (has_reduced_clock)
4203                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4204                                 reduced_clock.m2;
4205         }
4206
4207         /* Enable autotuning of the PLL clock (if permissible) */
4208         if (HAS_PCH_SPLIT(dev)) {
4209                 int factor = 21;
4210
4211                 if (is_lvds) {
4212                         if ((intel_panel_use_ssc(dev_priv) &&
4213                              dev_priv->lvds_ssc_freq == 100) ||
4214                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4215                                 factor = 25;
4216                 } else if (is_sdvo && is_tv)
4217                         factor = 20;
4218
4219                 if (clock.m1 < factor * clock.n)
4220                         fp |= FP_CB_TUNE;
4221         }
4222
4223         dpll = 0;
4224         if (!HAS_PCH_SPLIT(dev))
4225                 dpll = DPLL_VGA_MODE_DIS;
4226
4227         if (!IS_GEN2(dev)) {
4228                 if (is_lvds)
4229                         dpll |= DPLLB_MODE_LVDS;
4230                 else
4231                         dpll |= DPLLB_MODE_DAC_SERIAL;
4232                 if (is_sdvo) {
4233                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4234                         if (pixel_multiplier > 1) {
4235                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4236                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4237                                 else if (HAS_PCH_SPLIT(dev))
4238                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4239                         }
4240                         dpll |= DPLL_DVO_HIGH_SPEED;
4241                 }
4242                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4243                         dpll |= DPLL_DVO_HIGH_SPEED;
4244
4245                 /* compute bitmask from p1 value */
4246                 if (IS_PINEVIEW(dev))
4247                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4248                 else {
4249                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4250                         /* also FPA1 */
4251                         if (HAS_PCH_SPLIT(dev))
4252                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4253                         if (IS_G4X(dev) && has_reduced_clock)
4254                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4255                 }
4256                 switch (clock.p2) {
4257                 case 5:
4258                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4259                         break;
4260                 case 7:
4261                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4262                         break;
4263                 case 10:
4264                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4265                         break;
4266                 case 14:
4267                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4268                         break;
4269                 }
4270                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4271                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4272         } else {
4273                 if (is_lvds) {
4274                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4275                 } else {
4276                         if (clock.p1 == 2)
4277                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4278                         else
4279                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4280                         if (clock.p2 == 4)
4281                                 dpll |= PLL_P2_DIVIDE_BY_4;
4282                 }
4283         }
4284
4285         if (is_sdvo && is_tv)
4286                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4287         else if (is_tv)
4288                 /* XXX: just matching BIOS for now */
4289                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4290                 dpll |= 3;
4291         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4292                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4293         else
4294                 dpll |= PLL_REF_INPUT_DREFCLK;
4295
4296         /* setup pipeconf */
4297         pipeconf = I915_READ(PIPECONF(pipe));
4298
4299         /* Set up the display plane register */
4300         dspcntr = DISPPLANE_GAMMA_ENABLE;
4301
4302         /* Ironlake's plane is forced to pipe, bit 24 is to
4303            enable color space conversion */
4304         if (!HAS_PCH_SPLIT(dev)) {
4305                 if (pipe == 0)
4306                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4307                 else
4308                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4309         }
4310
4311         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4312                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4313                  * core speed.
4314                  *
4315                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4316                  * pipe == 0 check?
4317                  */
4318                 if (mode->clock >
4319                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4320                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4321                 else
4322                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4323         }
4324
4325         dspcntr |= DISPLAY_PLANE_ENABLE;
4326         pipeconf |= PIPECONF_ENABLE;
4327         dpll |= DPLL_VCO_ENABLE;
4328
4329         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4330         drm_mode_debug_printmodeline(mode);
4331
4332         /* assign to Ironlake registers */
4333         if (HAS_PCH_SPLIT(dev)) {
4334                 fp_reg = PCH_FP0(pipe);
4335                 dpll_reg = PCH_DPLL(pipe);
4336         } else {
4337                 fp_reg = FP0(pipe);
4338                 dpll_reg = DPLL(pipe);
4339         }
4340
4341         /* PCH eDP needs FDI, but CPU eDP does not */
4342         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4343                 I915_WRITE(fp_reg, fp);
4344                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4345
4346                 POSTING_READ(dpll_reg);
4347                 udelay(150);
4348         }
4349
4350         /* enable transcoder DPLL */
4351         if (HAS_PCH_CPT(dev)) {
4352                 temp = I915_READ(PCH_DPLL_SEL);
4353                 if (pipe == 0)
4354                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4355                 else
4356                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4357                 I915_WRITE(PCH_DPLL_SEL, temp);
4358
4359                 POSTING_READ(PCH_DPLL_SEL);
4360                 udelay(150);
4361         }
4362
4363         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4364          * This is an exception to the general rule that mode_set doesn't turn
4365          * things on.
4366          */
4367         if (is_lvds) {
4368                 reg = LVDS;
4369                 if (HAS_PCH_SPLIT(dev))
4370                         reg = PCH_LVDS;
4371
4372                 temp = I915_READ(reg);
4373                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4374                 if (pipe == 1) {
4375                         if (HAS_PCH_CPT(dev))
4376                                 temp |= PORT_TRANS_B_SEL_CPT;
4377                         else
4378                                 temp |= LVDS_PIPEB_SELECT;
4379                 } else {
4380                         if (HAS_PCH_CPT(dev))
4381                                 temp &= ~PORT_TRANS_SEL_MASK;
4382                         else
4383                                 temp &= ~LVDS_PIPEB_SELECT;
4384                 }
4385                 /* set the corresponsding LVDS_BORDER bit */
4386                 temp |= dev_priv->lvds_border_bits;
4387                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4388                  * set the DPLLs for dual-channel mode or not.
4389                  */
4390                 if (clock.p2 == 7)
4391                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4392                 else
4393                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4394
4395                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4396                  * appropriately here, but we need to look more thoroughly into how
4397                  * panels behave in the two modes.
4398                  */
4399                 /* set the dithering flag on non-PCH LVDS as needed */
4400                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4401                         if (dev_priv->lvds_dither)
4402                                 temp |= LVDS_ENABLE_DITHER;
4403                         else
4404                                 temp &= ~LVDS_ENABLE_DITHER;
4405                 }
4406                 I915_WRITE(reg, temp);
4407         }
4408
4409         /* set the dithering flag and clear for anything other than a panel. */
4410         if (HAS_PCH_SPLIT(dev)) {
4411                 pipeconf &= ~PIPECONF_DITHER_EN;
4412                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4413                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4414                         pipeconf |= PIPECONF_DITHER_EN;
4415                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4416                 }
4417         }
4418
4419         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4420                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4421         } else if (HAS_PCH_SPLIT(dev)) {
4422                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4423                 if (pipe == 0) {
4424                         I915_WRITE(TRANSA_DATA_M1, 0);
4425                         I915_WRITE(TRANSA_DATA_N1, 0);
4426                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4427                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4428                 } else {
4429                         I915_WRITE(TRANSB_DATA_M1, 0);
4430                         I915_WRITE(TRANSB_DATA_N1, 0);
4431                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4432                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4433                 }
4434         }
4435
4436         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4437                 I915_WRITE(dpll_reg, dpll);
4438
4439                 /* Wait for the clocks to stabilize. */
4440                 POSTING_READ(dpll_reg);
4441                 udelay(150);
4442
4443                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4444                         temp = 0;
4445                         if (is_sdvo) {
4446                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4447                                 if (temp > 1)
4448                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4449                                 else
4450                                         temp = 0;
4451                         }
4452                         I915_WRITE(DPLL_MD(pipe), temp);
4453                 } else {
4454                         /* The pixel multiplier can only be updated once the
4455                          * DPLL is enabled and the clocks are stable.
4456                          *
4457                          * So write it again.
4458                          */
4459                         I915_WRITE(dpll_reg, dpll);
4460                 }
4461         }
4462
4463         intel_crtc->lowfreq_avail = false;
4464         if (is_lvds && has_reduced_clock && i915_powersave) {
4465                 I915_WRITE(fp_reg + 4, fp2);
4466                 intel_crtc->lowfreq_avail = true;
4467                 if (HAS_PIPE_CXSR(dev)) {
4468                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4469                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4470                 }
4471         } else {
4472                 I915_WRITE(fp_reg + 4, fp);
4473                 if (HAS_PIPE_CXSR(dev)) {
4474                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4475                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4476                 }
4477         }
4478
4479         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4480                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4481                 /* the chip adds 2 halflines automatically */
4482                 adjusted_mode->crtc_vdisplay -= 1;
4483                 adjusted_mode->crtc_vtotal -= 1;
4484                 adjusted_mode->crtc_vblank_start -= 1;
4485                 adjusted_mode->crtc_vblank_end -= 1;
4486                 adjusted_mode->crtc_vsync_end -= 1;
4487                 adjusted_mode->crtc_vsync_start -= 1;
4488         } else
4489                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4490
4491         I915_WRITE(HTOTAL(pipe),
4492                    (adjusted_mode->crtc_hdisplay - 1) |
4493                    ((adjusted_mode->crtc_htotal - 1) << 16));
4494         I915_WRITE(HBLANK(pipe),
4495                    (adjusted_mode->crtc_hblank_start - 1) |
4496                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4497         I915_WRITE(HSYNC(pipe),
4498                    (adjusted_mode->crtc_hsync_start - 1) |
4499                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4500
4501         I915_WRITE(VTOTAL(pipe),
4502                    (adjusted_mode->crtc_vdisplay - 1) |
4503                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4504         I915_WRITE(VBLANK(pipe),
4505                    (adjusted_mode->crtc_vblank_start - 1) |
4506                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4507         I915_WRITE(VSYNC(pipe),
4508                    (adjusted_mode->crtc_vsync_start - 1) |
4509                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4510
4511         /* pipesrc and dspsize control the size that is scaled from,
4512          * which should always be the user's requested size.
4513          */
4514         if (!HAS_PCH_SPLIT(dev)) {
4515                 I915_WRITE(DSPSIZE(plane),
4516                            ((mode->vdisplay - 1) << 16) |
4517                            (mode->hdisplay - 1));
4518                 I915_WRITE(DSPPOS(plane), 0);
4519         }
4520         I915_WRITE(PIPESRC(pipe),
4521                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4522
4523         if (HAS_PCH_SPLIT(dev)) {
4524                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4525                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4526                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4527                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4528
4529                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4530                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4531                 }
4532         }
4533
4534         I915_WRITE(PIPECONF(pipe), pipeconf);
4535         POSTING_READ(PIPECONF(pipe));
4536
4537         intel_wait_for_vblank(dev, pipe);
4538
4539         if (IS_GEN5(dev)) {
4540                 /* enable address swizzle for tiling buffer */
4541                 temp = I915_READ(DISP_ARB_CTL);
4542                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4543         }
4544
4545         I915_WRITE(DSPCNTR(plane), dspcntr);
4546
4547         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4548
4549         intel_update_watermarks(dev);
4550
4551         drm_vblank_post_modeset(dev, pipe);
4552
4553         return ret;
4554 }
4555
4556 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4557 void intel_crtc_load_lut(struct drm_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4562         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4563         int i;
4564
4565         /* The clocks have to be on to load the palette. */
4566         if (!crtc->enabled)
4567                 return;
4568
4569         /* use legacy palette for Ironlake */
4570         if (HAS_PCH_SPLIT(dev))
4571                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4572                                                    LGC_PALETTE_B;
4573
4574         for (i = 0; i < 256; i++) {
4575                 I915_WRITE(palreg + 4 * i,
4576                            (intel_crtc->lut_r[i] << 16) |
4577                            (intel_crtc->lut_g[i] << 8) |
4578                            intel_crtc->lut_b[i]);
4579         }
4580 }
4581
4582 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4583 {
4584         struct drm_device *dev = crtc->dev;
4585         struct drm_i915_private *dev_priv = dev->dev_private;
4586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4587         bool visible = base != 0;
4588         u32 cntl;
4589
4590         if (intel_crtc->cursor_visible == visible)
4591                 return;
4592
4593         cntl = I915_READ(CURACNTR);
4594         if (visible) {
4595                 /* On these chipsets we can only modify the base whilst
4596                  * the cursor is disabled.
4597                  */
4598                 I915_WRITE(CURABASE, base);
4599
4600                 cntl &= ~(CURSOR_FORMAT_MASK);
4601                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4602                 cntl |= CURSOR_ENABLE |
4603                         CURSOR_GAMMA_ENABLE |
4604                         CURSOR_FORMAT_ARGB;
4605         } else
4606                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4607         I915_WRITE(CURACNTR, cntl);
4608
4609         intel_crtc->cursor_visible = visible;
4610 }
4611
4612 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4613 {
4614         struct drm_device *dev = crtc->dev;
4615         struct drm_i915_private *dev_priv = dev->dev_private;
4616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4617         int pipe = intel_crtc->pipe;
4618         bool visible = base != 0;
4619
4620         if (intel_crtc->cursor_visible != visible) {
4621                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4622                 if (base) {
4623                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4624                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4625                         cntl |= pipe << 28; /* Connect to correct pipe */
4626                 } else {
4627                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4628                         cntl |= CURSOR_MODE_DISABLE;
4629                 }
4630                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4631
4632                 intel_crtc->cursor_visible = visible;
4633         }
4634         /* and commit changes on next vblank */
4635         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4636 }
4637
4638 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4639 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4640                                      bool on)
4641 {
4642         struct drm_device *dev = crtc->dev;
4643         struct drm_i915_private *dev_priv = dev->dev_private;
4644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645         int pipe = intel_crtc->pipe;
4646         int x = intel_crtc->cursor_x;
4647         int y = intel_crtc->cursor_y;
4648         u32 base, pos;
4649         bool visible;
4650
4651         pos = 0;
4652
4653         if (on && crtc->enabled && crtc->fb) {
4654                 base = intel_crtc->cursor_addr;
4655                 if (x > (int) crtc->fb->width)
4656                         base = 0;
4657
4658                 if (y > (int) crtc->fb->height)
4659                         base = 0;
4660         } else
4661                 base = 0;
4662
4663         if (x < 0) {
4664                 if (x + intel_crtc->cursor_width < 0)
4665                         base = 0;
4666
4667                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4668                 x = -x;
4669         }
4670         pos |= x << CURSOR_X_SHIFT;
4671
4672         if (y < 0) {
4673                 if (y + intel_crtc->cursor_height < 0)
4674                         base = 0;
4675
4676                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4677                 y = -y;
4678         }
4679         pos |= y << CURSOR_Y_SHIFT;
4680
4681         visible = base != 0;
4682         if (!visible && !intel_crtc->cursor_visible)
4683                 return;
4684
4685         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4686         if (IS_845G(dev) || IS_I865G(dev))
4687                 i845_update_cursor(crtc, base);
4688         else
4689                 i9xx_update_cursor(crtc, base);
4690
4691         if (visible)
4692                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4693 }
4694
4695 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4696                                  struct drm_file *file,
4697                                  uint32_t handle,
4698                                  uint32_t width, uint32_t height)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703         struct drm_i915_gem_object *obj;
4704         uint32_t addr;
4705         int ret;
4706
4707         DRM_DEBUG_KMS("\n");
4708
4709         /* if we want to turn off the cursor ignore width and height */
4710         if (!handle) {
4711                 DRM_DEBUG_KMS("cursor off\n");
4712                 addr = 0;
4713                 obj = NULL;
4714                 mutex_lock(&dev->struct_mutex);
4715                 goto finish;
4716         }
4717
4718         /* Currently we only support 64x64 cursors */
4719         if (width != 64 || height != 64) {
4720                 DRM_ERROR("we currently only support 64x64 cursors\n");
4721                 return -EINVAL;
4722         }
4723
4724         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4725         if (!obj)
4726                 return -ENOENT;
4727
4728         if (obj->base.size < width * height * 4) {
4729                 DRM_ERROR("buffer is to small\n");
4730                 ret = -ENOMEM;
4731                 goto fail;
4732         }
4733
4734         /* we only need to pin inside GTT if cursor is non-phy */
4735         mutex_lock(&dev->struct_mutex);
4736         if (!dev_priv->info->cursor_needs_physical) {
4737                 if (obj->tiling_mode) {
4738                         DRM_ERROR("cursor cannot be tiled\n");
4739                         ret = -EINVAL;
4740                         goto fail_locked;
4741                 }
4742
4743                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4744                 if (ret) {
4745                         DRM_ERROR("failed to pin cursor bo\n");
4746                         goto fail_locked;
4747                 }
4748
4749                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4750                 if (ret) {
4751                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4752                         goto fail_unpin;
4753                 }
4754
4755                 ret = i915_gem_object_put_fence(obj);
4756                 if (ret) {
4757                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4758                         goto fail_unpin;
4759                 }
4760
4761                 addr = obj->gtt_offset;
4762         } else {
4763                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4764                 ret = i915_gem_attach_phys_object(dev, obj,
4765                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4766                                                   align);
4767                 if (ret) {
4768                         DRM_ERROR("failed to attach phys object\n");
4769                         goto fail_locked;
4770                 }
4771                 addr = obj->phys_obj->handle->busaddr;
4772         }
4773
4774         if (IS_GEN2(dev))
4775                 I915_WRITE(CURSIZE, (height << 12) | width);
4776
4777  finish:
4778         if (intel_crtc->cursor_bo) {
4779                 if (dev_priv->info->cursor_needs_physical) {
4780                         if (intel_crtc->cursor_bo != obj)
4781                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4782                 } else
4783                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4784                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4785         }
4786
4787         mutex_unlock(&dev->struct_mutex);
4788
4789         intel_crtc->cursor_addr = addr;
4790         intel_crtc->cursor_bo = obj;
4791         intel_crtc->cursor_width = width;
4792         intel_crtc->cursor_height = height;
4793
4794         intel_crtc_update_cursor(crtc, true);
4795
4796         return 0;
4797 fail_unpin:
4798         i915_gem_object_unpin(obj);
4799 fail_locked:
4800         mutex_unlock(&dev->struct_mutex);
4801 fail:
4802         drm_gem_object_unreference_unlocked(&obj->base);
4803         return ret;
4804 }
4805
4806 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4807 {
4808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809
4810         intel_crtc->cursor_x = x;
4811         intel_crtc->cursor_y = y;
4812
4813         intel_crtc_update_cursor(crtc, true);
4814
4815         return 0;
4816 }
4817
4818 /** Sets the color ramps on behalf of RandR */
4819 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4820                                  u16 blue, int regno)
4821 {
4822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4823
4824         intel_crtc->lut_r[regno] = red >> 8;
4825         intel_crtc->lut_g[regno] = green >> 8;
4826         intel_crtc->lut_b[regno] = blue >> 8;
4827 }
4828
4829 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4830                              u16 *blue, int regno)
4831 {
4832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833
4834         *red = intel_crtc->lut_r[regno] << 8;
4835         *green = intel_crtc->lut_g[regno] << 8;
4836         *blue = intel_crtc->lut_b[regno] << 8;
4837 }
4838
4839 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4840                                  u16 *blue, uint32_t start, uint32_t size)
4841 {
4842         int end = (start + size > 256) ? 256 : start + size, i;
4843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844
4845         for (i = start; i < end; i++) {
4846                 intel_crtc->lut_r[i] = red[i] >> 8;
4847                 intel_crtc->lut_g[i] = green[i] >> 8;
4848                 intel_crtc->lut_b[i] = blue[i] >> 8;
4849         }
4850
4851         intel_crtc_load_lut(crtc);
4852 }
4853
4854 /**
4855  * Get a pipe with a simple mode set on it for doing load-based monitor
4856  * detection.
4857  *
4858  * It will be up to the load-detect code to adjust the pipe as appropriate for
4859  * its requirements.  The pipe will be connected to no other encoders.
4860  *
4861  * Currently this code will only succeed if there is a pipe with no encoders
4862  * configured for it.  In the future, it could choose to temporarily disable
4863  * some outputs to free up a pipe for its use.
4864  *
4865  * \return crtc, or NULL if no pipes are available.
4866  */
4867
4868 /* VESA 640x480x72Hz mode to set on the pipe */
4869 static struct drm_display_mode load_detect_mode = {
4870         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4871                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4872 };
4873
4874 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4875                                             struct drm_connector *connector,
4876                                             struct drm_display_mode *mode,
4877                                             int *dpms_mode)
4878 {
4879         struct intel_crtc *intel_crtc;
4880         struct drm_crtc *possible_crtc;
4881         struct drm_crtc *supported_crtc =NULL;
4882         struct drm_encoder *encoder = &intel_encoder->base;
4883         struct drm_crtc *crtc = NULL;
4884         struct drm_device *dev = encoder->dev;
4885         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4886         struct drm_crtc_helper_funcs *crtc_funcs;
4887         int i = -1;
4888
4889         /*
4890          * Algorithm gets a little messy:
4891          *   - if the connector already has an assigned crtc, use it (but make
4892          *     sure it's on first)
4893          *   - try to find the first unused crtc that can drive this connector,
4894          *     and use that if we find one
4895          *   - if there are no unused crtcs available, try to use the first
4896          *     one we found that supports the connector
4897          */
4898
4899         /* See if we already have a CRTC for this connector */
4900         if (encoder->crtc) {
4901                 crtc = encoder->crtc;
4902                 /* Make sure the crtc and connector are running */
4903                 intel_crtc = to_intel_crtc(crtc);
4904                 *dpms_mode = intel_crtc->dpms_mode;
4905                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4906                         crtc_funcs = crtc->helper_private;
4907                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4908                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4909                 }
4910                 return crtc;
4911         }
4912
4913         /* Find an unused one (if possible) */
4914         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4915                 i++;
4916                 if (!(encoder->possible_crtcs & (1 << i)))
4917                         continue;
4918                 if (!possible_crtc->enabled) {
4919                         crtc = possible_crtc;
4920                         break;
4921                 }
4922                 if (!supported_crtc)
4923                         supported_crtc = possible_crtc;
4924         }
4925
4926         /*
4927          * If we didn't find an unused CRTC, don't use any.
4928          */
4929         if (!crtc) {
4930                 return NULL;
4931         }
4932
4933         encoder->crtc = crtc;
4934         connector->encoder = encoder;
4935         intel_encoder->load_detect_temp = true;
4936
4937         intel_crtc = to_intel_crtc(crtc);
4938         *dpms_mode = intel_crtc->dpms_mode;
4939
4940         if (!crtc->enabled) {
4941                 if (!mode)
4942                         mode = &load_detect_mode;
4943                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4944         } else {
4945                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4946                         crtc_funcs = crtc->helper_private;
4947                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4948                 }
4949
4950                 /* Add this connector to the crtc */
4951                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4952                 encoder_funcs->commit(encoder);
4953         }
4954         /* let the connector get through one full cycle before testing */
4955         intel_wait_for_vblank(dev, intel_crtc->pipe);
4956
4957         return crtc;
4958 }
4959
4960 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4961                                     struct drm_connector *connector, int dpms_mode)
4962 {
4963         struct drm_encoder *encoder = &intel_encoder->base;
4964         struct drm_device *dev = encoder->dev;
4965         struct drm_crtc *crtc = encoder->crtc;
4966         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4967         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4968
4969         if (intel_encoder->load_detect_temp) {
4970                 encoder->crtc = NULL;
4971                 connector->encoder = NULL;
4972                 intel_encoder->load_detect_temp = false;
4973                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4974                 drm_helper_disable_unused_functions(dev);
4975         }
4976
4977         /* Switch crtc and encoder back off if necessary */
4978         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4979                 if (encoder->crtc == crtc)
4980                         encoder_funcs->dpms(encoder, dpms_mode);
4981                 crtc_funcs->dpms(crtc, dpms_mode);
4982         }
4983 }
4984
4985 /* Returns the clock of the currently programmed mode of the given pipe. */
4986 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4987 {
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4990         int pipe = intel_crtc->pipe;
4991         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4992         u32 fp;
4993         intel_clock_t clock;
4994
4995         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4996                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4997         else
4998                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4999
5000         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5001         if (IS_PINEVIEW(dev)) {
5002                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5003                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5004         } else {
5005                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5006                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5007         }
5008
5009         if (!IS_GEN2(dev)) {
5010                 if (IS_PINEVIEW(dev))
5011                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5012                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5013                 else
5014                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5015                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5016
5017                 switch (dpll & DPLL_MODE_MASK) {
5018                 case DPLLB_MODE_DAC_SERIAL:
5019                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5020                                 5 : 10;
5021                         break;
5022                 case DPLLB_MODE_LVDS:
5023                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5024                                 7 : 14;
5025                         break;
5026                 default:
5027                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5028                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5029                         return 0;
5030                 }
5031
5032                 /* XXX: Handle the 100Mhz refclk */
5033                 intel_clock(dev, 96000, &clock);
5034         } else {
5035                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5036
5037                 if (is_lvds) {
5038                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5039                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5040                         clock.p2 = 14;
5041
5042                         if ((dpll & PLL_REF_INPUT_MASK) ==
5043                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5044                                 /* XXX: might not be 66MHz */
5045                                 intel_clock(dev, 66000, &clock);
5046                         } else
5047                                 intel_clock(dev, 48000, &clock);
5048                 } else {
5049                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5050                                 clock.p1 = 2;
5051                         else {
5052                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5053                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5054                         }
5055                         if (dpll & PLL_P2_DIVIDE_BY_4)
5056                                 clock.p2 = 4;
5057                         else
5058                                 clock.p2 = 2;
5059
5060                         intel_clock(dev, 48000, &clock);
5061                 }
5062         }
5063
5064         /* XXX: It would be nice to validate the clocks, but we can't reuse
5065          * i830PllIsValid() because it relies on the xf86_config connector
5066          * configuration being accurate, which it isn't necessarily.
5067          */
5068
5069         return clock.dot;
5070 }
5071
5072 /** Returns the currently programmed mode of the given pipe. */
5073 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5074                                              struct drm_crtc *crtc)
5075 {
5076         struct drm_i915_private *dev_priv = dev->dev_private;
5077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5078         int pipe = intel_crtc->pipe;
5079         struct drm_display_mode *mode;
5080         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5081         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5082         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5083         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5084
5085         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5086         if (!mode)
5087                 return NULL;
5088
5089         mode->clock = intel_crtc_clock_get(dev, crtc);
5090         mode->hdisplay = (htot & 0xffff) + 1;
5091         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5092         mode->hsync_start = (hsync & 0xffff) + 1;
5093         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5094         mode->vdisplay = (vtot & 0xffff) + 1;
5095         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5096         mode->vsync_start = (vsync & 0xffff) + 1;
5097         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5098
5099         drm_mode_set_name(mode);
5100         drm_mode_set_crtcinfo(mode, 0);
5101
5102         return mode;
5103 }
5104
5105 #define GPU_IDLE_TIMEOUT 500 /* ms */
5106
5107 /* When this timer fires, we've been idle for awhile */
5108 static void intel_gpu_idle_timer(unsigned long arg)
5109 {
5110         struct drm_device *dev = (struct drm_device *)arg;
5111         drm_i915_private_t *dev_priv = dev->dev_private;
5112
5113         if (!list_empty(&dev_priv->mm.active_list)) {
5114                 /* Still processing requests, so just re-arm the timer. */
5115                 mod_timer(&dev_priv->idle_timer, jiffies +
5116                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5117                 return;
5118         }
5119
5120         dev_priv->busy = false;
5121         queue_work(dev_priv->wq, &dev_priv->idle_work);
5122 }
5123
5124 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5125
5126 static void intel_crtc_idle_timer(unsigned long arg)
5127 {
5128         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5129         struct drm_crtc *crtc = &intel_crtc->base;
5130         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5131         struct intel_framebuffer *intel_fb;
5132
5133         intel_fb = to_intel_framebuffer(crtc->fb);
5134         if (intel_fb && intel_fb->obj->active) {
5135                 /* The framebuffer is still being accessed by the GPU. */
5136                 mod_timer(&intel_crtc->idle_timer, jiffies +
5137                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5138                 return;
5139         }
5140
5141         intel_crtc->busy = false;
5142         queue_work(dev_priv->wq, &dev_priv->idle_work);
5143 }
5144
5145 static void intel_increase_pllclock(struct drm_crtc *crtc)
5146 {
5147         struct drm_device *dev = crtc->dev;
5148         drm_i915_private_t *dev_priv = dev->dev_private;
5149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150         int pipe = intel_crtc->pipe;
5151         int dpll_reg = DPLL(pipe);
5152         int dpll;
5153
5154         if (HAS_PCH_SPLIT(dev))
5155                 return;
5156
5157         if (!dev_priv->lvds_downclock_avail)
5158                 return;
5159
5160         dpll = I915_READ(dpll_reg);
5161         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5162                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5163
5164                 /* Unlock panel regs */
5165                 I915_WRITE(PP_CONTROL,
5166                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5167
5168                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5169                 I915_WRITE(dpll_reg, dpll);
5170                 POSTING_READ(dpll_reg);
5171                 intel_wait_for_vblank(dev, pipe);
5172
5173                 dpll = I915_READ(dpll_reg);
5174                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5175                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5176
5177                 /* ...and lock them again */
5178                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5179         }
5180
5181         /* Schedule downclock */
5182         mod_timer(&intel_crtc->idle_timer, jiffies +
5183                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5184 }
5185
5186 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5187 {
5188         struct drm_device *dev = crtc->dev;
5189         drm_i915_private_t *dev_priv = dev->dev_private;
5190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191         int pipe = intel_crtc->pipe;
5192         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5193         int dpll = I915_READ(dpll_reg);
5194
5195         if (HAS_PCH_SPLIT(dev))
5196                 return;
5197
5198         if (!dev_priv->lvds_downclock_avail)
5199                 return;
5200
5201         /*
5202          * Since this is called by a timer, we should never get here in
5203          * the manual case.
5204          */
5205         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5206                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5207
5208                 /* Unlock panel regs */
5209                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5210                            PANEL_UNLOCK_REGS);
5211
5212                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5213                 I915_WRITE(dpll_reg, dpll);
5214                 dpll = I915_READ(dpll_reg);
5215                 intel_wait_for_vblank(dev, pipe);
5216                 dpll = I915_READ(dpll_reg);
5217                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5218                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5219
5220                 /* ...and lock them again */
5221                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5222         }
5223
5224 }
5225
5226 /**
5227  * intel_idle_update - adjust clocks for idleness
5228  * @work: work struct
5229  *
5230  * Either the GPU or display (or both) went idle.  Check the busy status
5231  * here and adjust the CRTC and GPU clocks as necessary.
5232  */
5233 static void intel_idle_update(struct work_struct *work)
5234 {
5235         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5236                                                     idle_work);
5237         struct drm_device *dev = dev_priv->dev;
5238         struct drm_crtc *crtc;
5239         struct intel_crtc *intel_crtc;
5240         int enabled = 0;
5241
5242         if (!i915_powersave)
5243                 return;
5244
5245         mutex_lock(&dev->struct_mutex);
5246
5247         i915_update_gfx_val(dev_priv);
5248
5249         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5250                 /* Skip inactive CRTCs */
5251                 if (!crtc->fb)
5252                         continue;
5253
5254                 enabled++;
5255                 intel_crtc = to_intel_crtc(crtc);
5256                 if (!intel_crtc->busy)
5257                         intel_decrease_pllclock(crtc);
5258         }
5259
5260         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5261                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5262                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5263         }
5264
5265         mutex_unlock(&dev->struct_mutex);
5266 }
5267
5268 /**
5269  * intel_mark_busy - mark the GPU and possibly the display busy
5270  * @dev: drm device
5271  * @obj: object we're operating on
5272  *
5273  * Callers can use this function to indicate that the GPU is busy processing
5274  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5275  * buffer), we'll also mark the display as busy, so we know to increase its
5276  * clock frequency.
5277  */
5278 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5279 {
5280         drm_i915_private_t *dev_priv = dev->dev_private;
5281         struct drm_crtc *crtc = NULL;
5282         struct intel_framebuffer *intel_fb;
5283         struct intel_crtc *intel_crtc;
5284
5285         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5286                 return;
5287
5288         if (!dev_priv->busy) {
5289                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5290                         u32 fw_blc_self;
5291
5292                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5293                         fw_blc_self = I915_READ(FW_BLC_SELF);
5294                         fw_blc_self &= ~FW_BLC_SELF_EN;
5295                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5296                 }
5297                 dev_priv->busy = true;
5298         } else
5299                 mod_timer(&dev_priv->idle_timer, jiffies +
5300                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5301
5302         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5303                 if (!crtc->fb)
5304                         continue;
5305
5306                 intel_crtc = to_intel_crtc(crtc);
5307                 intel_fb = to_intel_framebuffer(crtc->fb);
5308                 if (intel_fb->obj == obj) {
5309                         if (!intel_crtc->busy) {
5310                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5311                                         u32 fw_blc_self;
5312
5313                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5314                                         fw_blc_self = I915_READ(FW_BLC_SELF);
5315                                         fw_blc_self &= ~FW_BLC_SELF_EN;
5316                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5317                                 }
5318                                 /* Non-busy -> busy, upclock */
5319                                 intel_increase_pllclock(crtc);
5320                                 intel_crtc->busy = true;
5321                         } else {
5322                                 /* Busy -> busy, put off timer */
5323                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5324                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5325                         }
5326                 }
5327         }
5328 }
5329
5330 static void intel_crtc_destroy(struct drm_crtc *crtc)
5331 {
5332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333         struct drm_device *dev = crtc->dev;
5334         struct intel_unpin_work *work;
5335         unsigned long flags;
5336
5337         spin_lock_irqsave(&dev->event_lock, flags);
5338         work = intel_crtc->unpin_work;
5339         intel_crtc->unpin_work = NULL;
5340         spin_unlock_irqrestore(&dev->event_lock, flags);
5341
5342         if (work) {
5343                 cancel_work_sync(&work->work);
5344                 kfree(work);
5345         }
5346
5347         drm_crtc_cleanup(crtc);
5348
5349         kfree(intel_crtc);
5350 }
5351
5352 static void intel_unpin_work_fn(struct work_struct *__work)
5353 {
5354         struct intel_unpin_work *work =
5355                 container_of(__work, struct intel_unpin_work, work);
5356
5357         mutex_lock(&work->dev->struct_mutex);
5358         i915_gem_object_unpin(work->old_fb_obj);
5359         drm_gem_object_unreference(&work->pending_flip_obj->base);
5360         drm_gem_object_unreference(&work->old_fb_obj->base);
5361
5362         mutex_unlock(&work->dev->struct_mutex);
5363         kfree(work);
5364 }
5365
5366 static void do_intel_finish_page_flip(struct drm_device *dev,
5367                                       struct drm_crtc *crtc)
5368 {
5369         drm_i915_private_t *dev_priv = dev->dev_private;
5370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5371         struct intel_unpin_work *work;
5372         struct drm_i915_gem_object *obj;
5373         struct drm_pending_vblank_event *e;
5374         struct timeval tnow, tvbl;
5375         unsigned long flags;
5376
5377         /* Ignore early vblank irqs */
5378         if (intel_crtc == NULL)
5379                 return;
5380
5381         do_gettimeofday(&tnow);
5382
5383         spin_lock_irqsave(&dev->event_lock, flags);
5384         work = intel_crtc->unpin_work;
5385         if (work == NULL || !work->pending) {
5386                 spin_unlock_irqrestore(&dev->event_lock, flags);
5387                 return;
5388         }
5389
5390         intel_crtc->unpin_work = NULL;
5391
5392         if (work->event) {
5393                 e = work->event;
5394                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5395
5396                 /* Called before vblank count and timestamps have
5397                  * been updated for the vblank interval of flip
5398                  * completion? Need to increment vblank count and
5399                  * add one videorefresh duration to returned timestamp
5400                  * to account for this. We assume this happened if we
5401                  * get called over 0.9 frame durations after the last
5402                  * timestamped vblank.
5403                  *
5404                  * This calculation can not be used with vrefresh rates
5405                  * below 5Hz (10Hz to be on the safe side) without
5406                  * promoting to 64 integers.
5407                  */
5408                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5409                     9 * crtc->framedur_ns) {
5410                         e->event.sequence++;
5411                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5412                                              crtc->framedur_ns);
5413                 }
5414
5415                 e->event.tv_sec = tvbl.tv_sec;
5416                 e->event.tv_usec = tvbl.tv_usec;
5417
5418                 list_add_tail(&e->base.link,
5419                               &e->base.file_priv->event_list);
5420                 wake_up_interruptible(&e->base.file_priv->event_wait);
5421         }
5422
5423         drm_vblank_put(dev, intel_crtc->pipe);
5424
5425         spin_unlock_irqrestore(&dev->event_lock, flags);
5426
5427         obj = work->old_fb_obj;
5428
5429         atomic_clear_mask(1 << intel_crtc->plane,
5430                           &obj->pending_flip.counter);
5431         if (atomic_read(&obj->pending_flip) == 0)
5432                 wake_up(&dev_priv->pending_flip_queue);
5433
5434         schedule_work(&work->work);
5435
5436         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5437 }
5438
5439 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5440 {
5441         drm_i915_private_t *dev_priv = dev->dev_private;
5442         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5443
5444         do_intel_finish_page_flip(dev, crtc);
5445 }
5446
5447 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5448 {
5449         drm_i915_private_t *dev_priv = dev->dev_private;
5450         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5451
5452         do_intel_finish_page_flip(dev, crtc);
5453 }
5454
5455 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5456 {
5457         drm_i915_private_t *dev_priv = dev->dev_private;
5458         struct intel_crtc *intel_crtc =
5459                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5460         unsigned long flags;
5461
5462         spin_lock_irqsave(&dev->event_lock, flags);
5463         if (intel_crtc->unpin_work) {
5464                 if ((++intel_crtc->unpin_work->pending) > 1)
5465                         DRM_ERROR("Prepared flip multiple times\n");
5466         } else {
5467                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5468         }
5469         spin_unlock_irqrestore(&dev->event_lock, flags);
5470 }
5471
5472 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5473                                 struct drm_framebuffer *fb,
5474                                 struct drm_pending_vblank_event *event)
5475 {
5476         struct drm_device *dev = crtc->dev;
5477         struct drm_i915_private *dev_priv = dev->dev_private;
5478         struct intel_framebuffer *intel_fb;
5479         struct drm_i915_gem_object *obj;
5480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5481         struct intel_unpin_work *work;
5482         unsigned long flags, offset;
5483         int pipe = intel_crtc->pipe;
5484         u32 pf, pipesrc;
5485         int ret;
5486
5487         work = kzalloc(sizeof *work, GFP_KERNEL);
5488         if (work == NULL)
5489                 return -ENOMEM;
5490
5491         work->event = event;
5492         work->dev = crtc->dev;
5493         intel_fb = to_intel_framebuffer(crtc->fb);
5494         work->old_fb_obj = intel_fb->obj;
5495         INIT_WORK(&work->work, intel_unpin_work_fn);
5496
5497         /* We borrow the event spin lock for protecting unpin_work */
5498         spin_lock_irqsave(&dev->event_lock, flags);
5499         if (intel_crtc->unpin_work) {
5500                 spin_unlock_irqrestore(&dev->event_lock, flags);
5501                 kfree(work);
5502
5503                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5504                 return -EBUSY;
5505         }
5506         intel_crtc->unpin_work = work;
5507         spin_unlock_irqrestore(&dev->event_lock, flags);
5508
5509         intel_fb = to_intel_framebuffer(fb);
5510         obj = intel_fb->obj;
5511
5512         mutex_lock(&dev->struct_mutex);
5513         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5514         if (ret)
5515                 goto cleanup_work;
5516
5517         /* Reference the objects for the scheduled work. */
5518         drm_gem_object_reference(&work->old_fb_obj->base);
5519         drm_gem_object_reference(&obj->base);
5520
5521         crtc->fb = fb;
5522
5523         ret = drm_vblank_get(dev, intel_crtc->pipe);
5524         if (ret)
5525                 goto cleanup_objs;
5526
5527         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5528                 u32 flip_mask;
5529
5530                 /* Can't queue multiple flips, so wait for the previous
5531                  * one to finish before executing the next.
5532                  */
5533                 ret = BEGIN_LP_RING(2);
5534                 if (ret)
5535                         goto cleanup_objs;
5536
5537                 if (intel_crtc->plane)
5538                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5539                 else
5540                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5541                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5542                 OUT_RING(MI_NOOP);
5543                 ADVANCE_LP_RING();
5544         }
5545
5546         work->pending_flip_obj = obj;
5547
5548         work->enable_stall_check = true;
5549
5550         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5551         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5552
5553         ret = BEGIN_LP_RING(4);
5554         if (ret)
5555                 goto cleanup_objs;
5556
5557         /* Block clients from rendering to the new back buffer until
5558          * the flip occurs and the object is no longer visible.
5559          */
5560         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5561
5562         switch (INTEL_INFO(dev)->gen) {
5563         case 2:
5564                 OUT_RING(MI_DISPLAY_FLIP |
5565                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5566                 OUT_RING(fb->pitch);
5567                 OUT_RING(obj->gtt_offset + offset);
5568                 OUT_RING(MI_NOOP);
5569                 break;
5570
5571         case 3:
5572                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5573                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5574                 OUT_RING(fb->pitch);
5575                 OUT_RING(obj->gtt_offset + offset);
5576                 OUT_RING(MI_NOOP);
5577                 break;
5578
5579         case 4:
5580         case 5:
5581                 /* i965+ uses the linear or tiled offsets from the
5582                  * Display Registers (which do not change across a page-flip)
5583                  * so we need only reprogram the base address.
5584                  */
5585                 OUT_RING(MI_DISPLAY_FLIP |
5586                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5587                 OUT_RING(fb->pitch);
5588                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5589
5590                 /* XXX Enabling the panel-fitter across page-flip is so far
5591                  * untested on non-native modes, so ignore it for now.
5592                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5593                  */
5594                 pf = 0;
5595                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5596                 OUT_RING(pf | pipesrc);
5597                 break;
5598
5599         case 6:
5600                 OUT_RING(MI_DISPLAY_FLIP |
5601                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5602                 OUT_RING(fb->pitch | obj->tiling_mode);
5603                 OUT_RING(obj->gtt_offset);
5604
5605                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5606                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5607                 OUT_RING(pf | pipesrc);
5608                 break;
5609         }
5610         ADVANCE_LP_RING();
5611
5612         mutex_unlock(&dev->struct_mutex);
5613
5614         trace_i915_flip_request(intel_crtc->plane, obj);
5615
5616         return 0;
5617
5618 cleanup_objs:
5619         drm_gem_object_unreference(&work->old_fb_obj->base);
5620         drm_gem_object_unreference(&obj->base);
5621 cleanup_work:
5622         mutex_unlock(&dev->struct_mutex);
5623
5624         spin_lock_irqsave(&dev->event_lock, flags);
5625         intel_crtc->unpin_work = NULL;
5626         spin_unlock_irqrestore(&dev->event_lock, flags);
5627
5628         kfree(work);
5629
5630         return ret;
5631 }
5632
5633 static void intel_sanitize_modesetting(struct drm_device *dev,
5634                                        int pipe, int plane)
5635 {
5636         struct drm_i915_private *dev_priv = dev->dev_private;
5637         u32 reg, val;
5638
5639         if (HAS_PCH_SPLIT(dev))
5640                 return;
5641
5642         /* Who knows what state these registers were left in by the BIOS or
5643          * grub?
5644          *
5645          * If we leave the registers in a conflicting state (e.g. with the
5646          * display plane reading from the other pipe than the one we intend
5647          * to use) then when we attempt to teardown the active mode, we will
5648          * not disable the pipes and planes in the correct order -- leaving
5649          * a plane reading from a disabled pipe and possibly leading to
5650          * undefined behaviour.
5651          */
5652
5653         reg = DSPCNTR(plane);
5654         val = I915_READ(reg);
5655
5656         if ((val & DISPLAY_PLANE_ENABLE) == 0)
5657                 return;
5658         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5659                 return;
5660
5661         /* This display plane is active and attached to the other CPU pipe. */
5662         pipe = !pipe;
5663
5664         /* Disable the plane and wait for it to stop reading from the pipe. */
5665         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5666         intel_flush_display_plane(dev, plane);
5667
5668         if (IS_GEN2(dev))
5669                 intel_wait_for_vblank(dev, pipe);
5670
5671         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5672                 return;
5673
5674         /* Switch off the pipe. */
5675         reg = PIPECONF(pipe);
5676         val = I915_READ(reg);
5677         if (val & PIPECONF_ENABLE) {
5678                 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5679                 intel_wait_for_pipe_off(dev, pipe);
5680         }
5681 }
5682
5683 static void intel_crtc_reset(struct drm_crtc *crtc)
5684 {
5685         struct drm_device *dev = crtc->dev;
5686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5687
5688         /* Reset flags back to the 'unknown' status so that they
5689          * will be correctly set on the initial modeset.
5690          */
5691         intel_crtc->dpms_mode = -1;
5692
5693         /* We need to fix up any BIOS configuration that conflicts with
5694          * our expectations.
5695          */
5696         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5697 }
5698
5699 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5700         .dpms = intel_crtc_dpms,
5701         .mode_fixup = intel_crtc_mode_fixup,
5702         .mode_set = intel_crtc_mode_set,
5703         .mode_set_base = intel_pipe_set_base,
5704         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5705         .load_lut = intel_crtc_load_lut,
5706         .disable = intel_crtc_disable,
5707 };
5708
5709 static const struct drm_crtc_funcs intel_crtc_funcs = {
5710         .reset = intel_crtc_reset,
5711         .cursor_set = intel_crtc_cursor_set,
5712         .cursor_move = intel_crtc_cursor_move,
5713         .gamma_set = intel_crtc_gamma_set,
5714         .set_config = drm_crtc_helper_set_config,
5715         .destroy = intel_crtc_destroy,
5716         .page_flip = intel_crtc_page_flip,
5717 };
5718
5719 static void intel_crtc_init(struct drm_device *dev, int pipe)
5720 {
5721         drm_i915_private_t *dev_priv = dev->dev_private;
5722         struct intel_crtc *intel_crtc;
5723         int i;
5724
5725         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5726         if (intel_crtc == NULL)
5727                 return;
5728
5729         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5730
5731         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5732         for (i = 0; i < 256; i++) {
5733                 intel_crtc->lut_r[i] = i;
5734                 intel_crtc->lut_g[i] = i;
5735                 intel_crtc->lut_b[i] = i;
5736         }
5737
5738         /* Swap pipes & planes for FBC on pre-965 */
5739         intel_crtc->pipe = pipe;
5740         intel_crtc->plane = pipe;
5741         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5742                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5743                 intel_crtc->plane = !pipe;
5744         }
5745
5746         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5747                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5748         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5749         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5750
5751         intel_crtc_reset(&intel_crtc->base);
5752         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5753
5754         if (HAS_PCH_SPLIT(dev)) {
5755                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5756                 intel_helper_funcs.commit = ironlake_crtc_commit;
5757         } else {
5758                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5759                 intel_helper_funcs.commit = i9xx_crtc_commit;
5760         }
5761
5762         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5763
5764         intel_crtc->busy = false;
5765
5766         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5767                     (unsigned long)intel_crtc);
5768 }
5769
5770 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5771                                 struct drm_file *file)
5772 {
5773         drm_i915_private_t *dev_priv = dev->dev_private;
5774         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5775         struct drm_mode_object *drmmode_obj;
5776         struct intel_crtc *crtc;
5777
5778         if (!dev_priv) {
5779                 DRM_ERROR("called with no initialization\n");
5780                 return -EINVAL;
5781         }
5782
5783         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5784                         DRM_MODE_OBJECT_CRTC);
5785
5786         if (!drmmode_obj) {
5787                 DRM_ERROR("no such CRTC id\n");
5788                 return -EINVAL;
5789         }
5790
5791         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5792         pipe_from_crtc_id->pipe = crtc->pipe;
5793
5794         return 0;
5795 }
5796
5797 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5798 {
5799         struct intel_encoder *encoder;
5800         int index_mask = 0;
5801         int entry = 0;
5802
5803         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5804                 if (type_mask & encoder->clone_mask)
5805                         index_mask |= (1 << entry);
5806                 entry++;
5807         }
5808
5809         return index_mask;
5810 }
5811
5812 static bool has_edp_a(struct drm_device *dev)
5813 {
5814         struct drm_i915_private *dev_priv = dev->dev_private;
5815
5816         if (!IS_MOBILE(dev))
5817                 return false;
5818
5819         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5820                 return false;
5821
5822         if (IS_GEN5(dev) &&
5823             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5824                 return false;
5825
5826         return true;
5827 }
5828
5829 static void intel_setup_outputs(struct drm_device *dev)
5830 {
5831         struct drm_i915_private *dev_priv = dev->dev_private;
5832         struct intel_encoder *encoder;
5833         bool dpd_is_edp = false;
5834         bool has_lvds = false;
5835
5836         if (IS_MOBILE(dev) && !IS_I830(dev))
5837                 has_lvds = intel_lvds_init(dev);
5838         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5839                 /* disable the panel fitter on everything but LVDS */
5840                 I915_WRITE(PFIT_CONTROL, 0);
5841         }
5842
5843         if (HAS_PCH_SPLIT(dev)) {
5844                 dpd_is_edp = intel_dpd_is_edp(dev);
5845
5846                 if (has_edp_a(dev))
5847                         intel_dp_init(dev, DP_A);
5848
5849                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5850                         intel_dp_init(dev, PCH_DP_D);
5851         }
5852
5853         intel_crt_init(dev);
5854
5855         if (HAS_PCH_SPLIT(dev)) {
5856                 int found;
5857
5858                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5859                         /* PCH SDVOB multiplex with HDMIB */
5860                         found = intel_sdvo_init(dev, PCH_SDVOB);
5861                         if (!found)
5862                                 intel_hdmi_init(dev, HDMIB);
5863                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5864                                 intel_dp_init(dev, PCH_DP_B);
5865                 }
5866
5867                 if (I915_READ(HDMIC) & PORT_DETECTED)
5868                         intel_hdmi_init(dev, HDMIC);
5869
5870                 if (I915_READ(HDMID) & PORT_DETECTED)
5871                         intel_hdmi_init(dev, HDMID);
5872
5873                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5874                         intel_dp_init(dev, PCH_DP_C);
5875
5876                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5877                         intel_dp_init(dev, PCH_DP_D);
5878
5879         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5880                 bool found = false;
5881
5882                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5883                         DRM_DEBUG_KMS("probing SDVOB\n");
5884                         found = intel_sdvo_init(dev, SDVOB);
5885                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5886                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5887                                 intel_hdmi_init(dev, SDVOB);
5888                         }
5889
5890                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5891                                 DRM_DEBUG_KMS("probing DP_B\n");
5892                                 intel_dp_init(dev, DP_B);
5893                         }
5894                 }
5895
5896                 /* Before G4X SDVOC doesn't have its own detect register */
5897
5898                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5899                         DRM_DEBUG_KMS("probing SDVOC\n");
5900                         found = intel_sdvo_init(dev, SDVOC);
5901                 }
5902
5903                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5904
5905                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5906                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5907                                 intel_hdmi_init(dev, SDVOC);
5908                         }
5909                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5910                                 DRM_DEBUG_KMS("probing DP_C\n");
5911                                 intel_dp_init(dev, DP_C);
5912                         }
5913                 }
5914
5915                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5916                     (I915_READ(DP_D) & DP_DETECTED)) {
5917                         DRM_DEBUG_KMS("probing DP_D\n");
5918                         intel_dp_init(dev, DP_D);
5919                 }
5920         } else if (IS_GEN2(dev))
5921                 intel_dvo_init(dev);
5922
5923         if (SUPPORTS_TV(dev))
5924                 intel_tv_init(dev);
5925
5926         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5927                 encoder->base.possible_crtcs = encoder->crtc_mask;
5928                 encoder->base.possible_clones =
5929                         intel_encoder_clones(dev, encoder->clone_mask);
5930         }
5931
5932         intel_panel_setup_backlight(dev);
5933 }
5934
5935 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5936 {
5937         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5938
5939         drm_framebuffer_cleanup(fb);
5940         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5941
5942         kfree(intel_fb);
5943 }
5944
5945 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5946                                                 struct drm_file *file,
5947                                                 unsigned int *handle)
5948 {
5949         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5950         struct drm_i915_gem_object *obj = intel_fb->obj;
5951
5952         return drm_gem_handle_create(file, &obj->base, handle);
5953 }
5954
5955 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5956         .destroy = intel_user_framebuffer_destroy,
5957         .create_handle = intel_user_framebuffer_create_handle,
5958 };
5959
5960 int intel_framebuffer_init(struct drm_device *dev,
5961                            struct intel_framebuffer *intel_fb,
5962                            struct drm_mode_fb_cmd *mode_cmd,
5963                            struct drm_i915_gem_object *obj)
5964 {
5965         int ret;
5966
5967         if (obj->tiling_mode == I915_TILING_Y)
5968                 return -EINVAL;
5969
5970         if (mode_cmd->pitch & 63)
5971                 return -EINVAL;
5972
5973         switch (mode_cmd->bpp) {
5974         case 8:
5975         case 16:
5976         case 24:
5977         case 32:
5978                 break;
5979         default:
5980                 return -EINVAL;
5981         }
5982
5983         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5984         if (ret) {
5985                 DRM_ERROR("framebuffer init failed %d\n", ret);
5986                 return ret;
5987         }
5988
5989         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5990         intel_fb->obj = obj;
5991         return 0;
5992 }
5993
5994 static struct drm_framebuffer *
5995 intel_user_framebuffer_create(struct drm_device *dev,
5996                               struct drm_file *filp,
5997                               struct drm_mode_fb_cmd *mode_cmd)
5998 {
5999         struct drm_i915_gem_object *obj;
6000         struct intel_framebuffer *intel_fb;
6001         int ret;
6002
6003         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6004         if (!obj)
6005                 return ERR_PTR(-ENOENT);
6006
6007         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6008         if (!intel_fb) {
6009                 drm_gem_object_unreference_unlocked(&obj->base);
6010                 return ERR_PTR(-ENOMEM);
6011         }
6012
6013         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6014         if (ret) {
6015                 drm_gem_object_unreference_unlocked(&obj->base);
6016                 kfree(intel_fb);
6017                 return ERR_PTR(ret);
6018         }
6019
6020         return &intel_fb->base;
6021 }
6022
6023 static const struct drm_mode_config_funcs intel_mode_funcs = {
6024         .fb_create = intel_user_framebuffer_create,
6025         .output_poll_changed = intel_fb_output_poll_changed,
6026 };
6027
6028 static struct drm_i915_gem_object *
6029 intel_alloc_context_page(struct drm_device *dev)
6030 {
6031         struct drm_i915_gem_object *ctx;
6032         int ret;
6033
6034         ctx = i915_gem_alloc_object(dev, 4096);
6035         if (!ctx) {
6036                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6037                 return NULL;
6038         }
6039
6040         mutex_lock(&dev->struct_mutex);
6041         ret = i915_gem_object_pin(ctx, 4096, true);
6042         if (ret) {
6043                 DRM_ERROR("failed to pin power context: %d\n", ret);
6044                 goto err_unref;
6045         }
6046
6047         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6048         if (ret) {
6049                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6050                 goto err_unpin;
6051         }
6052         mutex_unlock(&dev->struct_mutex);
6053
6054         return ctx;
6055
6056 err_unpin:
6057         i915_gem_object_unpin(ctx);
6058 err_unref:
6059         drm_gem_object_unreference(&ctx->base);
6060         mutex_unlock(&dev->struct_mutex);
6061         return NULL;
6062 }
6063
6064 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6065 {
6066         struct drm_i915_private *dev_priv = dev->dev_private;
6067         u16 rgvswctl;
6068
6069         rgvswctl = I915_READ16(MEMSWCTL);
6070         if (rgvswctl & MEMCTL_CMD_STS) {
6071                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6072                 return false; /* still busy with another command */
6073         }
6074
6075         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6076                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6077         I915_WRITE16(MEMSWCTL, rgvswctl);
6078         POSTING_READ16(MEMSWCTL);
6079
6080         rgvswctl |= MEMCTL_CMD_STS;
6081         I915_WRITE16(MEMSWCTL, rgvswctl);
6082
6083         return true;
6084 }
6085
6086 void ironlake_enable_drps(struct drm_device *dev)
6087 {
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089         u32 rgvmodectl = I915_READ(MEMMODECTL);
6090         u8 fmax, fmin, fstart, vstart;
6091
6092         /* Enable temp reporting */
6093         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6094         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6095
6096         /* 100ms RC evaluation intervals */
6097         I915_WRITE(RCUPEI, 100000);
6098         I915_WRITE(RCDNEI, 100000);
6099
6100         /* Set max/min thresholds to 90ms and 80ms respectively */
6101         I915_WRITE(RCBMAXAVG, 90000);
6102         I915_WRITE(RCBMINAVG, 80000);
6103
6104         I915_WRITE(MEMIHYST, 1);
6105
6106         /* Set up min, max, and cur for interrupt handling */
6107         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6108         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6109         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6110                 MEMMODE_FSTART_SHIFT;
6111
6112         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6113                 PXVFREQ_PX_SHIFT;
6114
6115         dev_priv->fmax = fmax; /* IPS callback will increase this */
6116         dev_priv->fstart = fstart;
6117
6118         dev_priv->max_delay = fstart;
6119         dev_priv->min_delay = fmin;
6120         dev_priv->cur_delay = fstart;
6121
6122         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6123                          fmax, fmin, fstart);
6124
6125         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6126
6127         /*
6128          * Interrupts will be enabled in ironlake_irq_postinstall
6129          */
6130
6131         I915_WRITE(VIDSTART, vstart);
6132         POSTING_READ(VIDSTART);
6133
6134         rgvmodectl |= MEMMODE_SWMODE_EN;
6135         I915_WRITE(MEMMODECTL, rgvmodectl);
6136
6137         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6138                 DRM_ERROR("stuck trying to change perf mode\n");
6139         msleep(1);
6140
6141         ironlake_set_drps(dev, fstart);
6142
6143         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6144                 I915_READ(0x112e0);
6145         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6146         dev_priv->last_count2 = I915_READ(0x112f4);
6147         getrawmonotonic(&dev_priv->last_time2);
6148 }
6149
6150 void ironlake_disable_drps(struct drm_device *dev)
6151 {
6152         struct drm_i915_private *dev_priv = dev->dev_private;
6153         u16 rgvswctl = I915_READ16(MEMSWCTL);
6154
6155         /* Ack interrupts, disable EFC interrupt */
6156         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6157         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6158         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6159         I915_WRITE(DEIIR, DE_PCU_EVENT);
6160         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6161
6162         /* Go back to the starting frequency */
6163         ironlake_set_drps(dev, dev_priv->fstart);
6164         msleep(1);
6165         rgvswctl |= MEMCTL_CMD_STS;
6166         I915_WRITE(MEMSWCTL, rgvswctl);
6167         msleep(1);
6168
6169 }
6170
6171 void gen6_set_rps(struct drm_device *dev, u8 val)
6172 {
6173         struct drm_i915_private *dev_priv = dev->dev_private;
6174         u32 swreq;
6175
6176         swreq = (val & 0x3ff) << 25;
6177         I915_WRITE(GEN6_RPNSWREQ, swreq);
6178 }
6179
6180 void gen6_disable_rps(struct drm_device *dev)
6181 {
6182         struct drm_i915_private *dev_priv = dev->dev_private;
6183
6184         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6185         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6186         I915_WRITE(GEN6_PMIER, 0);
6187         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6188 }
6189
6190 static unsigned long intel_pxfreq(u32 vidfreq)
6191 {
6192         unsigned long freq;
6193         int div = (vidfreq & 0x3f0000) >> 16;
6194         int post = (vidfreq & 0x3000) >> 12;
6195         int pre = (vidfreq & 0x7);
6196
6197         if (!pre)
6198                 return 0;
6199
6200         freq = ((div * 133333) / ((1<<post) * pre));
6201
6202         return freq;
6203 }
6204
6205 void intel_init_emon(struct drm_device *dev)
6206 {
6207         struct drm_i915_private *dev_priv = dev->dev_private;
6208         u32 lcfuse;
6209         u8 pxw[16];
6210         int i;
6211
6212         /* Disable to program */
6213         I915_WRITE(ECR, 0);
6214         POSTING_READ(ECR);
6215
6216         /* Program energy weights for various events */
6217         I915_WRITE(SDEW, 0x15040d00);
6218         I915_WRITE(CSIEW0, 0x007f0000);
6219         I915_WRITE(CSIEW1, 0x1e220004);
6220         I915_WRITE(CSIEW2, 0x04000004);
6221
6222         for (i = 0; i < 5; i++)
6223                 I915_WRITE(PEW + (i * 4), 0);
6224         for (i = 0; i < 3; i++)
6225                 I915_WRITE(DEW + (i * 4), 0);
6226
6227         /* Program P-state weights to account for frequency power adjustment */
6228         for (i = 0; i < 16; i++) {
6229                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6230                 unsigned long freq = intel_pxfreq(pxvidfreq);
6231                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6232                         PXVFREQ_PX_SHIFT;
6233                 unsigned long val;
6234
6235                 val = vid * vid;
6236                 val *= (freq / 1000);
6237                 val *= 255;
6238                 val /= (127*127*900);
6239                 if (val > 0xff)
6240                         DRM_ERROR("bad pxval: %ld\n", val);
6241                 pxw[i] = val;
6242         }
6243         /* Render standby states get 0 weight */
6244         pxw[14] = 0;
6245         pxw[15] = 0;
6246
6247         for (i = 0; i < 4; i++) {
6248                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6249                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6250                 I915_WRITE(PXW + (i * 4), val);
6251         }
6252
6253         /* Adjust magic regs to magic values (more experimental results) */
6254         I915_WRITE(OGW0, 0);
6255         I915_WRITE(OGW1, 0);
6256         I915_WRITE(EG0, 0x00007f00);
6257         I915_WRITE(EG1, 0x0000000e);
6258         I915_WRITE(EG2, 0x000e0000);
6259         I915_WRITE(EG3, 0x68000300);
6260         I915_WRITE(EG4, 0x42000000);
6261         I915_WRITE(EG5, 0x00140031);
6262         I915_WRITE(EG6, 0);
6263         I915_WRITE(EG7, 0);
6264
6265         for (i = 0; i < 8; i++)
6266                 I915_WRITE(PXWL + (i * 4), 0);
6267
6268         /* Enable PMON + select events */
6269         I915_WRITE(ECR, 0x80000019);
6270
6271         lcfuse = I915_READ(LCFUSE02);
6272
6273         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6274 }
6275
6276 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6277 {
6278         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6279         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6280         u32 pcu_mbox;
6281         int cur_freq, min_freq, max_freq;
6282         int i;
6283
6284         /* Here begins a magic sequence of register writes to enable
6285          * auto-downclocking.
6286          *
6287          * Perhaps there might be some value in exposing these to
6288          * userspace...
6289          */
6290         I915_WRITE(GEN6_RC_STATE, 0);
6291         __gen6_gt_force_wake_get(dev_priv);
6292
6293         /* disable the counters and set deterministic thresholds */
6294         I915_WRITE(GEN6_RC_CONTROL, 0);
6295
6296         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6297         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6298         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6299         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6300         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6301
6302         for (i = 0; i < I915_NUM_RINGS; i++)
6303                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6304
6305         I915_WRITE(GEN6_RC_SLEEP, 0);
6306         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6307         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6308         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6309         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6310
6311         I915_WRITE(GEN6_RC_CONTROL,
6312                    GEN6_RC_CTL_RC6p_ENABLE |
6313                    GEN6_RC_CTL_RC6_ENABLE |
6314                    GEN6_RC_CTL_EI_MODE(1) |
6315                    GEN6_RC_CTL_HW_ENABLE);
6316
6317         I915_WRITE(GEN6_RPNSWREQ,
6318                    GEN6_FREQUENCY(10) |
6319                    GEN6_OFFSET(0) |
6320                    GEN6_AGGRESSIVE_TURBO);
6321         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6322                    GEN6_FREQUENCY(12));
6323
6324         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6325         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6326                    18 << 24 |
6327                    6 << 16);
6328         I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6329         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6330         I915_WRITE(GEN6_RP_UP_EI, 100000);
6331         I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6332         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6333         I915_WRITE(GEN6_RP_CONTROL,
6334                    GEN6_RP_MEDIA_TURBO |
6335                    GEN6_RP_USE_NORMAL_FREQ |
6336                    GEN6_RP_MEDIA_IS_GFX |
6337                    GEN6_RP_ENABLE |
6338                    GEN6_RP_UP_BUSY_MAX |
6339                    GEN6_RP_DOWN_BUSY_MIN);
6340
6341         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6342                      500))
6343                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6344
6345         I915_WRITE(GEN6_PCODE_DATA, 0);
6346         I915_WRITE(GEN6_PCODE_MAILBOX,
6347                    GEN6_PCODE_READY |
6348                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6349         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6350                      500))
6351                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6352
6353         min_freq = (rp_state_cap & 0xff0000) >> 16;
6354         max_freq = rp_state_cap & 0xff;
6355         cur_freq = (gt_perf_status & 0xff00) >> 8;
6356
6357         /* Check for overclock support */
6358         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6359                      500))
6360                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6361         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6362         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6363         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6364                      500))
6365                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6366         if (pcu_mbox & (1<<31)) { /* OC supported */
6367                 max_freq = pcu_mbox & 0xff;
6368                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6369         }
6370
6371         /* In units of 100MHz */
6372         dev_priv->max_delay = max_freq;
6373         dev_priv->min_delay = min_freq;
6374         dev_priv->cur_delay = cur_freq;
6375
6376         /* requires MSI enabled */
6377         I915_WRITE(GEN6_PMIER,
6378                    GEN6_PM_MBOX_EVENT |
6379                    GEN6_PM_THERMAL_EVENT |
6380                    GEN6_PM_RP_DOWN_TIMEOUT |
6381                    GEN6_PM_RP_UP_THRESHOLD |
6382                    GEN6_PM_RP_DOWN_THRESHOLD |
6383                    GEN6_PM_RP_UP_EI_EXPIRED |
6384                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6385         I915_WRITE(GEN6_PMIMR, 0);
6386         /* enable all PM interrupts */
6387         I915_WRITE(GEN6_PMINTRMSK, 0);
6388
6389         __gen6_gt_force_wake_put(dev_priv);
6390 }
6391
6392 void intel_enable_clock_gating(struct drm_device *dev)
6393 {
6394         struct drm_i915_private *dev_priv = dev->dev_private;
6395
6396         /*
6397          * Disable clock gating reported to work incorrectly according to the
6398          * specs, but enable as much else as we can.
6399          */
6400         if (HAS_PCH_SPLIT(dev)) {
6401                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6402
6403                 if (IS_GEN5(dev)) {
6404                         /* Required for FBC */
6405                         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6406                                 DPFCRUNIT_CLOCK_GATE_DISABLE |
6407                                 DPFDUNIT_CLOCK_GATE_DISABLE;
6408                         /* Required for CxSR */
6409                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6410
6411                         I915_WRITE(PCH_3DCGDIS0,
6412                                    MARIUNIT_CLOCK_GATE_DISABLE |
6413                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6414                         I915_WRITE(PCH_3DCGDIS1,
6415                                    VFMUNIT_CLOCK_GATE_DISABLE);
6416                 }
6417
6418                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6419
6420                 /*
6421                  * On Ibex Peak and Cougar Point, we need to disable clock
6422                  * gating for the panel power sequencer or it will fail to
6423                  * start up when no ports are active.
6424                  */
6425                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6426
6427                 /*
6428                  * According to the spec the following bits should be set in
6429                  * order to enable memory self-refresh
6430                  * The bit 22/21 of 0x42004
6431                  * The bit 5 of 0x42020
6432                  * The bit 15 of 0x45000
6433                  */
6434                 if (IS_GEN5(dev)) {
6435                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6436                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
6437                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6438                         I915_WRITE(ILK_DSPCLK_GATE,
6439                                         (I915_READ(ILK_DSPCLK_GATE) |
6440                                                 ILK_DPARB_CLK_GATE));
6441                         I915_WRITE(DISP_ARB_CTL,
6442                                         (I915_READ(DISP_ARB_CTL) |
6443                                                 DISP_FBC_WM_DIS));
6444                         I915_WRITE(WM3_LP_ILK, 0);
6445                         I915_WRITE(WM2_LP_ILK, 0);
6446                         I915_WRITE(WM1_LP_ILK, 0);
6447                 }
6448                 /*
6449                  * Based on the document from hardware guys the following bits
6450                  * should be set unconditionally in order to enable FBC.
6451                  * The bit 22 of 0x42000
6452                  * The bit 22 of 0x42004
6453                  * The bit 7,8,9 of 0x42020.
6454                  */
6455                 if (IS_IRONLAKE_M(dev)) {
6456                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6457                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6458                                    ILK_FBCQ_DIS);
6459                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6460                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6461                                    ILK_DPARB_GATE);
6462                         I915_WRITE(ILK_DSPCLK_GATE,
6463                                    I915_READ(ILK_DSPCLK_GATE) |
6464                                    ILK_DPFC_DIS1 |
6465                                    ILK_DPFC_DIS2 |
6466                                    ILK_CLK_FBC);
6467                 }
6468
6469                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6470                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6471                            ILK_ELPIN_409_SELECT);
6472
6473                 if (IS_GEN5(dev)) {
6474                         I915_WRITE(_3D_CHICKEN2,
6475                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6476                                    _3D_CHICKEN2_WM_READ_PIPELINED);
6477                 }
6478
6479                 if (IS_GEN6(dev)) {
6480                         I915_WRITE(WM3_LP_ILK, 0);
6481                         I915_WRITE(WM2_LP_ILK, 0);
6482                         I915_WRITE(WM1_LP_ILK, 0);
6483
6484                         /*
6485                          * According to the spec the following bits should be
6486                          * set in order to enable memory self-refresh and fbc:
6487                          * The bit21 and bit22 of 0x42000
6488                          * The bit21 and bit22 of 0x42004
6489                          * The bit5 and bit7 of 0x42020
6490                          * The bit14 of 0x70180
6491                          * The bit14 of 0x71180
6492                          */
6493                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6494                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6495                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6496                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6497                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6498                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6499                         I915_WRITE(ILK_DSPCLK_GATE,
6500                                    I915_READ(ILK_DSPCLK_GATE) |
6501                                    ILK_DPARB_CLK_GATE  |
6502                                    ILK_DPFD_CLK_GATE);
6503
6504                         I915_WRITE(DSPACNTR,
6505                                    I915_READ(DSPACNTR) |
6506                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6507                         I915_WRITE(DSPBCNTR,
6508                                    I915_READ(DSPBCNTR) |
6509                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6510                 }
6511         } else if (IS_G4X(dev)) {
6512                 uint32_t dspclk_gate;
6513                 I915_WRITE(RENCLK_GATE_D1, 0);
6514                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6515                        GS_UNIT_CLOCK_GATE_DISABLE |
6516                        CL_UNIT_CLOCK_GATE_DISABLE);
6517                 I915_WRITE(RAMCLK_GATE_D, 0);
6518                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6519                         OVRUNIT_CLOCK_GATE_DISABLE |
6520                         OVCUNIT_CLOCK_GATE_DISABLE;
6521                 if (IS_GM45(dev))
6522                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6523                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6524         } else if (IS_CRESTLINE(dev)) {
6525                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6526                 I915_WRITE(RENCLK_GATE_D2, 0);
6527                 I915_WRITE(DSPCLK_GATE_D, 0);
6528                 I915_WRITE(RAMCLK_GATE_D, 0);
6529                 I915_WRITE16(DEUC, 0);
6530         } else if (IS_BROADWATER(dev)) {
6531                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6532                        I965_RCC_CLOCK_GATE_DISABLE |
6533                        I965_RCPB_CLOCK_GATE_DISABLE |
6534                        I965_ISC_CLOCK_GATE_DISABLE |
6535                        I965_FBC_CLOCK_GATE_DISABLE);
6536                 I915_WRITE(RENCLK_GATE_D2, 0);
6537         } else if (IS_GEN3(dev)) {
6538                 u32 dstate = I915_READ(D_STATE);
6539
6540                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6541                         DSTATE_DOT_CLOCK_GATING;
6542                 I915_WRITE(D_STATE, dstate);
6543         } else if (IS_I85X(dev) || IS_I865G(dev)) {
6544                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6545         } else if (IS_I830(dev)) {
6546                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6547         }
6548 }
6549
6550 static void ironlake_teardown_rc6(struct drm_device *dev)
6551 {
6552         struct drm_i915_private *dev_priv = dev->dev_private;
6553
6554         if (dev_priv->renderctx) {
6555                 i915_gem_object_unpin(dev_priv->renderctx);
6556                 drm_gem_object_unreference(&dev_priv->renderctx->base);
6557                 dev_priv->renderctx = NULL;
6558         }
6559
6560         if (dev_priv->pwrctx) {
6561                 i915_gem_object_unpin(dev_priv->pwrctx);
6562                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
6563                 dev_priv->pwrctx = NULL;
6564         }
6565 }
6566
6567 static void ironlake_disable_rc6(struct drm_device *dev)
6568 {
6569         struct drm_i915_private *dev_priv = dev->dev_private;
6570
6571         if (I915_READ(PWRCTXA)) {
6572                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6573                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6574                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6575                          50);
6576
6577                 I915_WRITE(PWRCTXA, 0);
6578                 POSTING_READ(PWRCTXA);
6579
6580                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6581                 POSTING_READ(RSTDBYCTL);
6582         }
6583
6584         ironlake_teardown_rc6(dev);
6585 }
6586
6587 static int ironlake_setup_rc6(struct drm_device *dev)
6588 {
6589         struct drm_i915_private *dev_priv = dev->dev_private;
6590
6591         if (dev_priv->renderctx == NULL)
6592                 dev_priv->renderctx = intel_alloc_context_page(dev);
6593         if (!dev_priv->renderctx)
6594                 return -ENOMEM;
6595
6596         if (dev_priv->pwrctx == NULL)
6597                 dev_priv->pwrctx = intel_alloc_context_page(dev);
6598         if (!dev_priv->pwrctx) {
6599                 ironlake_teardown_rc6(dev);
6600                 return -ENOMEM;
6601         }
6602
6603         return 0;
6604 }
6605
6606 void ironlake_enable_rc6(struct drm_device *dev)
6607 {
6608         struct drm_i915_private *dev_priv = dev->dev_private;
6609         int ret;
6610
6611         /* rc6 disabled by default due to repeated reports of hanging during
6612          * boot and resume.
6613          */
6614         if (!i915_enable_rc6)
6615                 return;
6616
6617         ret = ironlake_setup_rc6(dev);
6618         if (ret)
6619                 return;
6620
6621         /*
6622          * GPU can automatically power down the render unit if given a page
6623          * to save state.
6624          */
6625         ret = BEGIN_LP_RING(6);
6626         if (ret) {
6627                 ironlake_teardown_rc6(dev);
6628                 return;
6629         }
6630
6631         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6632         OUT_RING(MI_SET_CONTEXT);
6633         OUT_RING(dev_priv->renderctx->gtt_offset |
6634                  MI_MM_SPACE_GTT |
6635                  MI_SAVE_EXT_STATE_EN |
6636                  MI_RESTORE_EXT_STATE_EN |
6637                  MI_RESTORE_INHIBIT);
6638         OUT_RING(MI_SUSPEND_FLUSH);
6639         OUT_RING(MI_NOOP);
6640         OUT_RING(MI_FLUSH);
6641         ADVANCE_LP_RING();
6642
6643         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6644         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6645 }
6646
6647
6648 /* Set up chip specific display functions */
6649 static void intel_init_display(struct drm_device *dev)
6650 {
6651         struct drm_i915_private *dev_priv = dev->dev_private;
6652
6653         /* We always want a DPMS function */
6654         if (HAS_PCH_SPLIT(dev))
6655                 dev_priv->display.dpms = ironlake_crtc_dpms;
6656         else
6657                 dev_priv->display.dpms = i9xx_crtc_dpms;
6658
6659         if (I915_HAS_FBC(dev)) {
6660                 if (HAS_PCH_SPLIT(dev)) {
6661                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6662                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6663                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6664                 } else if (IS_GM45(dev)) {
6665                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6666                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6667                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6668                 } else if (IS_CRESTLINE(dev)) {
6669                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6670                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6671                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6672                 }
6673                 /* 855GM needs testing */
6674         }
6675
6676         /* Returns the core display clock speed */
6677         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6678                 dev_priv->display.get_display_clock_speed =
6679                         i945_get_display_clock_speed;
6680         else if (IS_I915G(dev))
6681                 dev_priv->display.get_display_clock_speed =
6682                         i915_get_display_clock_speed;
6683         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6684                 dev_priv->display.get_display_clock_speed =
6685                         i9xx_misc_get_display_clock_speed;
6686         else if (IS_I915GM(dev))
6687                 dev_priv->display.get_display_clock_speed =
6688                         i915gm_get_display_clock_speed;
6689         else if (IS_I865G(dev))
6690                 dev_priv->display.get_display_clock_speed =
6691                         i865_get_display_clock_speed;
6692         else if (IS_I85X(dev))
6693                 dev_priv->display.get_display_clock_speed =
6694                         i855_get_display_clock_speed;
6695         else /* 852, 830 */
6696                 dev_priv->display.get_display_clock_speed =
6697                         i830_get_display_clock_speed;
6698
6699         /* For FIFO watermark updates */
6700         if (HAS_PCH_SPLIT(dev)) {
6701                 if (IS_GEN5(dev)) {
6702                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6703                                 dev_priv->display.update_wm = ironlake_update_wm;
6704                         else {
6705                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6706                                               "Disable CxSR\n");
6707                                 dev_priv->display.update_wm = NULL;
6708                         }
6709                 } else if (IS_GEN6(dev)) {
6710                         if (SNB_READ_WM0_LATENCY()) {
6711                                 dev_priv->display.update_wm = sandybridge_update_wm;
6712                         } else {
6713                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6714                                               "Disable CxSR\n");
6715                                 dev_priv->display.update_wm = NULL;
6716                         }
6717                 } else
6718                         dev_priv->display.update_wm = NULL;
6719         } else if (IS_PINEVIEW(dev)) {
6720                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6721                                             dev_priv->is_ddr3,
6722                                             dev_priv->fsb_freq,
6723                                             dev_priv->mem_freq)) {
6724                         DRM_INFO("failed to find known CxSR latency "
6725                                  "(found ddr%s fsb freq %d, mem freq %d), "
6726                                  "disabling CxSR\n",
6727                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6728                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6729                         /* Disable CxSR and never update its watermark again */
6730                         pineview_disable_cxsr(dev);
6731                         dev_priv->display.update_wm = NULL;
6732                 } else
6733                         dev_priv->display.update_wm = pineview_update_wm;
6734         } else if (IS_G4X(dev))
6735                 dev_priv->display.update_wm = g4x_update_wm;
6736         else if (IS_GEN4(dev))
6737                 dev_priv->display.update_wm = i965_update_wm;
6738         else if (IS_GEN3(dev)) {
6739                 dev_priv->display.update_wm = i9xx_update_wm;
6740                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6741         } else if (IS_I85X(dev)) {
6742                 dev_priv->display.update_wm = i9xx_update_wm;
6743                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6744         } else {
6745                 dev_priv->display.update_wm = i830_update_wm;
6746                 if (IS_845G(dev))
6747                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6748                 else
6749                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6750         }
6751 }
6752
6753 /*
6754  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6755  * resume, or other times.  This quirk makes sure that's the case for
6756  * affected systems.
6757  */
6758 static void quirk_pipea_force (struct drm_device *dev)
6759 {
6760         struct drm_i915_private *dev_priv = dev->dev_private;
6761
6762         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6763         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6764 }
6765
6766 struct intel_quirk {
6767         int device;
6768         int subsystem_vendor;
6769         int subsystem_device;
6770         void (*hook)(struct drm_device *dev);
6771 };
6772
6773 struct intel_quirk intel_quirks[] = {
6774         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6775         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6776         /* HP Mini needs pipe A force quirk (LP: #322104) */
6777         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6778
6779         /* Thinkpad R31 needs pipe A force quirk */
6780         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6781         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6782         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6783
6784         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6785         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6786         /* ThinkPad X40 needs pipe A force quirk */
6787
6788         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6789         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6790
6791         /* 855 & before need to leave pipe A & dpll A up */
6792         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6793         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6794 };
6795
6796 static void intel_init_quirks(struct drm_device *dev)
6797 {
6798         struct pci_dev *d = dev->pdev;
6799         int i;
6800
6801         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6802                 struct intel_quirk *q = &intel_quirks[i];
6803
6804                 if (d->device == q->device &&
6805                     (d->subsystem_vendor == q->subsystem_vendor ||
6806                      q->subsystem_vendor == PCI_ANY_ID) &&
6807                     (d->subsystem_device == q->subsystem_device ||
6808                      q->subsystem_device == PCI_ANY_ID))
6809                         q->hook(dev);
6810         }
6811 }
6812
6813 /* Disable the VGA plane that we never use */
6814 static void i915_disable_vga(struct drm_device *dev)
6815 {
6816         struct drm_i915_private *dev_priv = dev->dev_private;
6817         u8 sr1;
6818         u32 vga_reg;
6819
6820         if (HAS_PCH_SPLIT(dev))
6821                 vga_reg = CPU_VGACNTRL;
6822         else
6823                 vga_reg = VGACNTRL;
6824
6825         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6826         outb(1, VGA_SR_INDEX);
6827         sr1 = inb(VGA_SR_DATA);
6828         outb(sr1 | 1<<5, VGA_SR_DATA);
6829         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6830         udelay(300);
6831
6832         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6833         POSTING_READ(vga_reg);
6834 }
6835
6836 void intel_modeset_init(struct drm_device *dev)
6837 {
6838         struct drm_i915_private *dev_priv = dev->dev_private;
6839         int i;
6840
6841         drm_mode_config_init(dev);
6842
6843         dev->mode_config.min_width = 0;
6844         dev->mode_config.min_height = 0;
6845
6846         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6847
6848         intel_init_quirks(dev);
6849
6850         intel_init_display(dev);
6851
6852         if (IS_GEN2(dev)) {
6853                 dev->mode_config.max_width = 2048;
6854                 dev->mode_config.max_height = 2048;
6855         } else if (IS_GEN3(dev)) {
6856                 dev->mode_config.max_width = 4096;
6857                 dev->mode_config.max_height = 4096;
6858         } else {
6859                 dev->mode_config.max_width = 8192;
6860                 dev->mode_config.max_height = 8192;
6861         }
6862         dev->mode_config.fb_base = dev->agp->base;
6863
6864         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6865                 dev_priv->num_pipe = 2;
6866         else
6867                 dev_priv->num_pipe = 1;
6868         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6869                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6870
6871         for (i = 0; i < dev_priv->num_pipe; i++) {
6872                 intel_crtc_init(dev, i);
6873         }
6874
6875         intel_setup_outputs(dev);
6876
6877         intel_enable_clock_gating(dev);
6878
6879         /* Just disable it once at startup */
6880         i915_disable_vga(dev);
6881
6882         if (IS_IRONLAKE_M(dev)) {
6883                 ironlake_enable_drps(dev);
6884                 intel_init_emon(dev);
6885         }
6886
6887         if (IS_GEN6(dev))
6888                 gen6_enable_rps(dev_priv);
6889
6890         if (IS_IRONLAKE_M(dev))
6891                 ironlake_enable_rc6(dev);
6892
6893         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6894         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6895                     (unsigned long)dev);
6896
6897         intel_setup_overlay(dev);
6898 }
6899
6900 void intel_modeset_cleanup(struct drm_device *dev)
6901 {
6902         struct drm_i915_private *dev_priv = dev->dev_private;
6903         struct drm_crtc *crtc;
6904         struct intel_crtc *intel_crtc;
6905
6906         drm_kms_helper_poll_fini(dev);
6907         mutex_lock(&dev->struct_mutex);
6908
6909         intel_unregister_dsm_handler();
6910
6911
6912         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6913                 /* Skip inactive CRTCs */
6914                 if (!crtc->fb)
6915                         continue;
6916
6917                 intel_crtc = to_intel_crtc(crtc);
6918                 intel_increase_pllclock(crtc);
6919         }
6920
6921         if (dev_priv->display.disable_fbc)
6922                 dev_priv->display.disable_fbc(dev);
6923
6924         if (IS_IRONLAKE_M(dev))
6925                 ironlake_disable_drps(dev);
6926         if (IS_GEN6(dev))
6927                 gen6_disable_rps(dev);
6928
6929         if (IS_IRONLAKE_M(dev))
6930                 ironlake_disable_rc6(dev);
6931
6932         mutex_unlock(&dev->struct_mutex);
6933
6934         /* Disable the irq before mode object teardown, for the irq might
6935          * enqueue unpin/hotplug work. */
6936         drm_irq_uninstall(dev);
6937         cancel_work_sync(&dev_priv->hotplug_work);
6938
6939         /* Shut off idle work before the crtcs get freed. */
6940         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6941                 intel_crtc = to_intel_crtc(crtc);
6942                 del_timer_sync(&intel_crtc->idle_timer);
6943         }
6944         del_timer_sync(&dev_priv->idle_timer);
6945         cancel_work_sync(&dev_priv->idle_work);
6946
6947         drm_mode_config_cleanup(dev);
6948 }
6949
6950 /*
6951  * Return which encoder is currently attached for connector.
6952  */
6953 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6954 {
6955         return &intel_attached_encoder(connector)->base;
6956 }
6957
6958 void intel_connector_attach_encoder(struct intel_connector *connector,
6959                                     struct intel_encoder *encoder)
6960 {
6961         connector->encoder = encoder;
6962         drm_mode_connector_attach_encoder(&connector->base,
6963                                           &encoder->base);
6964 }
6965
6966 /*
6967  * set vga decode state - true == enable VGA decode
6968  */
6969 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6970 {
6971         struct drm_i915_private *dev_priv = dev->dev_private;
6972         u16 gmch_ctrl;
6973
6974         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6975         if (state)
6976                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6977         else
6978                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6979         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6980         return 0;
6981 }
6982
6983 #ifdef CONFIG_DEBUG_FS
6984 #include <linux/seq_file.h>
6985
6986 struct intel_display_error_state {
6987         struct intel_cursor_error_state {
6988                 u32 control;
6989                 u32 position;
6990                 u32 base;
6991                 u32 size;
6992         } cursor[2];
6993
6994         struct intel_pipe_error_state {
6995                 u32 conf;
6996                 u32 source;
6997
6998                 u32 htotal;
6999                 u32 hblank;
7000                 u32 hsync;
7001                 u32 vtotal;
7002                 u32 vblank;
7003                 u32 vsync;
7004         } pipe[2];
7005
7006         struct intel_plane_error_state {
7007                 u32 control;
7008                 u32 stride;
7009                 u32 size;
7010                 u32 pos;
7011                 u32 addr;
7012                 u32 surface;
7013                 u32 tile_offset;
7014         } plane[2];
7015 };
7016
7017 struct intel_display_error_state *
7018 intel_display_capture_error_state(struct drm_device *dev)
7019 {
7020         drm_i915_private_t *dev_priv = dev->dev_private;
7021         struct intel_display_error_state *error;
7022         int i;
7023
7024         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7025         if (error == NULL)
7026                 return NULL;
7027
7028         for (i = 0; i < 2; i++) {
7029                 error->cursor[i].control = I915_READ(CURCNTR(i));
7030                 error->cursor[i].position = I915_READ(CURPOS(i));
7031                 error->cursor[i].base = I915_READ(CURBASE(i));
7032
7033                 error->plane[i].control = I915_READ(DSPCNTR(i));
7034                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7035                 error->plane[i].size = I915_READ(DSPSIZE(i));
7036                 error->plane[i].pos= I915_READ(DSPPOS(i));
7037                 error->plane[i].addr = I915_READ(DSPADDR(i));
7038                 if (INTEL_INFO(dev)->gen >= 4) {
7039                         error->plane[i].surface = I915_READ(DSPSURF(i));
7040                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7041                 }
7042
7043                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7044                 error->pipe[i].source = I915_READ(PIPESRC(i));
7045                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7046                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7047                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7048                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7049                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7050                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7051         }
7052
7053         return error;
7054 }
7055
7056 void
7057 intel_display_print_error_state(struct seq_file *m,
7058                                 struct drm_device *dev,
7059                                 struct intel_display_error_state *error)
7060 {
7061         int i;
7062
7063         for (i = 0; i < 2; i++) {
7064                 seq_printf(m, "Pipe [%d]:\n", i);
7065                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7066                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7067                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7068                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7069                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7070                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7071                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7072                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7073
7074                 seq_printf(m, "Plane [%d]:\n", i);
7075                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7076                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7077                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7078                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7079                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7080                 if (INTEL_INFO(dev)->gen >= 4) {
7081                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7082                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7083                 }
7084
7085                 seq_printf(m, "Cursor [%d]:\n", i);
7086                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7087                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7088                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7089         }
7090 }
7091 #endif