drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj = intel_fb->obj;
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj = intel_fb->obj;
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj = intel_fb->obj;
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj = intel_fb->obj;
1388
1389         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_i915_gem_object *obj,
1437                            struct intel_ring_buffer *pipelined)
1438 {
1439         u32 alignment;
1440         int ret;
1441
1442         switch (obj->tiling_mode) {
1443         case I915_TILING_NONE:
1444                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1445                         alignment = 128 * 1024;
1446                 else if (INTEL_INFO(dev)->gen >= 4)
1447                         alignment = 4 * 1024;
1448                 else
1449                         alignment = 64 * 1024;
1450                 break;
1451         case I915_TILING_X:
1452                 /* pin() will align the object as required by fence */
1453                 alignment = 0;
1454                 break;
1455         case I915_TILING_Y:
1456                 /* FIXME: Is this true? */
1457                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1458                 return -EINVAL;
1459         default:
1460                 BUG();
1461         }
1462
1463         ret = i915_gem_object_pin(obj, alignment, true);
1464         if (ret)
1465                 return ret;
1466
1467         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1468         if (ret)
1469                 goto err_unpin;
1470
1471         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1472          * fence, whereas 965+ only requires a fence if using
1473          * framebuffer compression.  For simplicity, we always install
1474          * a fence as the cost is not that onerous.
1475          */
1476         if (obj->tiling_mode != I915_TILING_NONE) {
1477                 ret = i915_gem_object_get_fence_reg(obj, false);
1478                 if (ret)
1479                         goto err_unpin;
1480         }
1481
1482         return 0;
1483
1484 err_unpin:
1485         i915_gem_object_unpin(obj);
1486         return ret;
1487 }
1488
1489 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1490 static int
1491 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1492                            int x, int y, enum mode_set_atomic state)
1493 {
1494         struct drm_device *dev = crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1497         struct intel_framebuffer *intel_fb;
1498         struct drm_i915_gem_object *obj;
1499         int plane = intel_crtc->plane;
1500         unsigned long Start, Offset;
1501         u32 dspcntr;
1502         u32 reg;
1503
1504         switch (plane) {
1505         case 0:
1506         case 1:
1507                 break;
1508         default:
1509                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1510                 return -EINVAL;
1511         }
1512
1513         intel_fb = to_intel_framebuffer(fb);
1514         obj = intel_fb->obj;
1515
1516         reg = DSPCNTR(plane);
1517         dspcntr = I915_READ(reg);
1518         /* Mask out pixel format bits in case we change it */
1519         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1520         switch (fb->bits_per_pixel) {
1521         case 8:
1522                 dspcntr |= DISPPLANE_8BPP;
1523                 break;
1524         case 16:
1525                 if (fb->depth == 15)
1526                         dspcntr |= DISPPLANE_15_16BPP;
1527                 else
1528                         dspcntr |= DISPPLANE_16BPP;
1529                 break;
1530         case 24:
1531         case 32:
1532                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1533                 break;
1534         default:
1535                 DRM_ERROR("Unknown color depth\n");
1536                 return -EINVAL;
1537         }
1538         if (INTEL_INFO(dev)->gen >= 4) {
1539                 if (obj->tiling_mode != I915_TILING_NONE)
1540                         dspcntr |= DISPPLANE_TILED;
1541                 else
1542                         dspcntr &= ~DISPPLANE_TILED;
1543         }
1544
1545         if (HAS_PCH_SPLIT(dev))
1546                 /* must disable */
1547                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1548
1549         I915_WRITE(reg, dspcntr);
1550
1551         Start = obj->gtt_offset;
1552         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1553
1554         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1555                       Start, Offset, x, y, fb->pitch);
1556         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1557         if (INTEL_INFO(dev)->gen >= 4) {
1558                 I915_WRITE(DSPSURF(plane), Start);
1559                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1560                 I915_WRITE(DSPADDR(plane), Offset);
1561         } else
1562                 I915_WRITE(DSPADDR(plane), Start + Offset);
1563         POSTING_READ(reg);
1564
1565         intel_update_fbc(dev);
1566         intel_increase_pllclock(crtc);
1567
1568         return 0;
1569 }
1570
1571 static int
1572 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1573                     struct drm_framebuffer *old_fb)
1574 {
1575         struct drm_device *dev = crtc->dev;
1576         struct drm_i915_master_private *master_priv;
1577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1578         int ret;
1579
1580         /* no fb bound */
1581         if (!crtc->fb) {
1582                 DRM_DEBUG_KMS("No FB bound\n");
1583                 return 0;
1584         }
1585
1586         switch (intel_crtc->plane) {
1587         case 0:
1588         case 1:
1589                 break;
1590         default:
1591                 return -EINVAL;
1592         }
1593
1594         mutex_lock(&dev->struct_mutex);
1595         ret = intel_pin_and_fence_fb_obj(dev,
1596                                          to_intel_framebuffer(crtc->fb)->obj,
1597                                          NULL);
1598         if (ret != 0) {
1599                 mutex_unlock(&dev->struct_mutex);
1600                 return ret;
1601         }
1602
1603         if (old_fb) {
1604                 struct drm_i915_private *dev_priv = dev->dev_private;
1605                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1606
1607                 wait_event(dev_priv->pending_flip_queue,
1608                            atomic_read(&obj->pending_flip) == 0);
1609
1610                 /* Big Hammer, we also need to ensure that any pending
1611                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1612                  * current scanout is retired before unpinning the old
1613                  * framebuffer.
1614                  */
1615                 ret = i915_gem_object_flush_gpu(obj, false);
1616                 if (ret) {
1617                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1618                         mutex_unlock(&dev->struct_mutex);
1619                         return ret;
1620                 }
1621         }
1622
1623         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1624                                          LEAVE_ATOMIC_MODE_SET);
1625         if (ret) {
1626                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1627                 mutex_unlock(&dev->struct_mutex);
1628                 return ret;
1629         }
1630
1631         if (old_fb)
1632                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1633
1634         mutex_unlock(&dev->struct_mutex);
1635
1636         if (!dev->primary->master)
1637                 return 0;
1638
1639         master_priv = dev->primary->master->driver_priv;
1640         if (!master_priv->sarea_priv)
1641                 return 0;
1642
1643         if (intel_crtc->pipe) {
1644                 master_priv->sarea_priv->pipeB_x = x;
1645                 master_priv->sarea_priv->pipeB_y = y;
1646         } else {
1647                 master_priv->sarea_priv->pipeA_x = x;
1648                 master_priv->sarea_priv->pipeA_y = y;
1649         }
1650
1651         return 0;
1652 }
1653
1654 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1655 {
1656         struct drm_device *dev = crtc->dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         u32 dpa_ctl;
1659
1660         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1661         dpa_ctl = I915_READ(DP_A);
1662         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1663
1664         if (clock < 200000) {
1665                 u32 temp;
1666                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1667                 /* workaround for 160Mhz:
1668                    1) program 0x4600c bits 15:0 = 0x8124
1669                    2) program 0x46010 bit 0 = 1
1670                    3) program 0x46034 bit 24 = 1
1671                    4) program 0x64000 bit 14 = 1
1672                    */
1673                 temp = I915_READ(0x4600c);
1674                 temp &= 0xffff0000;
1675                 I915_WRITE(0x4600c, temp | 0x8124);
1676
1677                 temp = I915_READ(0x46010);
1678                 I915_WRITE(0x46010, temp | 1);
1679
1680                 temp = I915_READ(0x46034);
1681                 I915_WRITE(0x46034, temp | (1 << 24));
1682         } else {
1683                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1684         }
1685         I915_WRITE(DP_A, dpa_ctl);
1686
1687         POSTING_READ(DP_A);
1688         udelay(500);
1689 }
1690
1691 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1692 {
1693         struct drm_device *dev = crtc->dev;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1696         int pipe = intel_crtc->pipe;
1697         u32 reg, temp;
1698
1699         /* enable normal train */
1700         reg = FDI_TX_CTL(pipe);
1701         temp = I915_READ(reg);
1702         temp &= ~FDI_LINK_TRAIN_NONE;
1703         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1704         I915_WRITE(reg, temp);
1705
1706         reg = FDI_RX_CTL(pipe);
1707         temp = I915_READ(reg);
1708         if (HAS_PCH_CPT(dev)) {
1709                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1710                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1711         } else {
1712                 temp &= ~FDI_LINK_TRAIN_NONE;
1713                 temp |= FDI_LINK_TRAIN_NONE;
1714         }
1715         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1716
1717         /* wait one idle pattern time */
1718         POSTING_READ(reg);
1719         udelay(1000);
1720 }
1721
1722 /* The FDI link training functions for ILK/Ibexpeak. */
1723 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1724 {
1725         struct drm_device *dev = crtc->dev;
1726         struct drm_i915_private *dev_priv = dev->dev_private;
1727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1728         int pipe = intel_crtc->pipe;
1729         u32 reg, temp, tries;
1730
1731         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1732            for train result */
1733         reg = FDI_RX_IMR(pipe);
1734         temp = I915_READ(reg);
1735         temp &= ~FDI_RX_SYMBOL_LOCK;
1736         temp &= ~FDI_RX_BIT_LOCK;
1737         I915_WRITE(reg, temp);
1738         I915_READ(reg);
1739         udelay(150);
1740
1741         /* enable CPU FDI TX and PCH FDI RX */
1742         reg = FDI_TX_CTL(pipe);
1743         temp = I915_READ(reg);
1744         temp &= ~(7 << 19);
1745         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1746         temp &= ~FDI_LINK_TRAIN_NONE;
1747         temp |= FDI_LINK_TRAIN_PATTERN_1;
1748         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1749
1750         reg = FDI_RX_CTL(pipe);
1751         temp = I915_READ(reg);
1752         temp &= ~FDI_LINK_TRAIN_NONE;
1753         temp |= FDI_LINK_TRAIN_PATTERN_1;
1754         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1755
1756         POSTING_READ(reg);
1757         udelay(150);
1758
1759         /* Ironlake workaround, enable clock pointer after FDI enable*/
1760         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1761
1762         reg = FDI_RX_IIR(pipe);
1763         for (tries = 0; tries < 5; tries++) {
1764                 temp = I915_READ(reg);
1765                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1766
1767                 if ((temp & FDI_RX_BIT_LOCK)) {
1768                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1769                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1770                         break;
1771                 }
1772         }
1773         if (tries == 5)
1774                 DRM_ERROR("FDI train 1 fail!\n");
1775
1776         /* Train 2 */
1777         reg = FDI_TX_CTL(pipe);
1778         temp = I915_READ(reg);
1779         temp &= ~FDI_LINK_TRAIN_NONE;
1780         temp |= FDI_LINK_TRAIN_PATTERN_2;
1781         I915_WRITE(reg, temp);
1782
1783         reg = FDI_RX_CTL(pipe);
1784         temp = I915_READ(reg);
1785         temp &= ~FDI_LINK_TRAIN_NONE;
1786         temp |= FDI_LINK_TRAIN_PATTERN_2;
1787         I915_WRITE(reg, temp);
1788
1789         POSTING_READ(reg);
1790         udelay(150);
1791
1792         reg = FDI_RX_IIR(pipe);
1793         for (tries = 0; tries < 5; tries++) {
1794                 temp = I915_READ(reg);
1795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1796
1797                 if (temp & FDI_RX_SYMBOL_LOCK) {
1798                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1799                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1800                         break;
1801                 }
1802         }
1803         if (tries == 5)
1804                 DRM_ERROR("FDI train 2 fail!\n");
1805
1806         DRM_DEBUG_KMS("FDI train done\n");
1807
1808 }
1809
1810 static const int const snb_b_fdi_train_param [] = {
1811         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1812         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1813         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1814         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1815 };
1816
1817 /* The FDI link training functions for SNB/Cougarpoint. */
1818 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1819 {
1820         struct drm_device *dev = crtc->dev;
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823         int pipe = intel_crtc->pipe;
1824         u32 reg, temp, i;
1825
1826         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1827            for train result */
1828         reg = FDI_RX_IMR(pipe);
1829         temp = I915_READ(reg);
1830         temp &= ~FDI_RX_SYMBOL_LOCK;
1831         temp &= ~FDI_RX_BIT_LOCK;
1832         I915_WRITE(reg, temp);
1833
1834         POSTING_READ(reg);
1835         udelay(150);
1836
1837         /* enable CPU FDI TX and PCH FDI RX */
1838         reg = FDI_TX_CTL(pipe);
1839         temp = I915_READ(reg);
1840         temp &= ~(7 << 19);
1841         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1842         temp &= ~FDI_LINK_TRAIN_NONE;
1843         temp |= FDI_LINK_TRAIN_PATTERN_1;
1844         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1845         /* SNB-B */
1846         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1847         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1848
1849         reg = FDI_RX_CTL(pipe);
1850         temp = I915_READ(reg);
1851         if (HAS_PCH_CPT(dev)) {
1852                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1853                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1854         } else {
1855                 temp &= ~FDI_LINK_TRAIN_NONE;
1856                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1857         }
1858         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1859
1860         POSTING_READ(reg);
1861         udelay(150);
1862
1863         for (i = 0; i < 4; i++ ) {
1864                 reg = FDI_TX_CTL(pipe);
1865                 temp = I915_READ(reg);
1866                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1867                 temp |= snb_b_fdi_train_param[i];
1868                 I915_WRITE(reg, temp);
1869
1870                 POSTING_READ(reg);
1871                 udelay(500);
1872
1873                 reg = FDI_RX_IIR(pipe);
1874                 temp = I915_READ(reg);
1875                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1876
1877                 if (temp & FDI_RX_BIT_LOCK) {
1878                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1879                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1880                         break;
1881                 }
1882         }
1883         if (i == 4)
1884                 DRM_ERROR("FDI train 1 fail!\n");
1885
1886         /* Train 2 */
1887         reg = FDI_TX_CTL(pipe);
1888         temp = I915_READ(reg);
1889         temp &= ~FDI_LINK_TRAIN_NONE;
1890         temp |= FDI_LINK_TRAIN_PATTERN_2;
1891         if (IS_GEN6(dev)) {
1892                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1893                 /* SNB-B */
1894                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1895         }
1896         I915_WRITE(reg, temp);
1897
1898         reg = FDI_RX_CTL(pipe);
1899         temp = I915_READ(reg);
1900         if (HAS_PCH_CPT(dev)) {
1901                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1902                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1903         } else {
1904                 temp &= ~FDI_LINK_TRAIN_NONE;
1905                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1906         }
1907         I915_WRITE(reg, temp);
1908
1909         POSTING_READ(reg);
1910         udelay(150);
1911
1912         for (i = 0; i < 4; i++ ) {
1913                 reg = FDI_TX_CTL(pipe);
1914                 temp = I915_READ(reg);
1915                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1916                 temp |= snb_b_fdi_train_param[i];
1917                 I915_WRITE(reg, temp);
1918
1919                 POSTING_READ(reg);
1920                 udelay(500);
1921
1922                 reg = FDI_RX_IIR(pipe);
1923                 temp = I915_READ(reg);
1924                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1925
1926                 if (temp & FDI_RX_SYMBOL_LOCK) {
1927                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1928                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1929                         break;
1930                 }
1931         }
1932         if (i == 4)
1933                 DRM_ERROR("FDI train 2 fail!\n");
1934
1935         DRM_DEBUG_KMS("FDI train done.\n");
1936 }
1937
1938 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1939 {
1940         struct drm_device *dev = crtc->dev;
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1943         int pipe = intel_crtc->pipe;
1944         u32 reg, temp;
1945
1946         /* Write the TU size bits so error detection works */
1947         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1948                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1949
1950         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1951         reg = FDI_RX_CTL(pipe);
1952         temp = I915_READ(reg);
1953         temp &= ~((0x7 << 19) | (0x7 << 16));
1954         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1955         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1956         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1957
1958         POSTING_READ(reg);
1959         udelay(200);
1960
1961         /* Switch from Rawclk to PCDclk */
1962         temp = I915_READ(reg);
1963         I915_WRITE(reg, temp | FDI_PCDCLK);
1964
1965         POSTING_READ(reg);
1966         udelay(200);
1967
1968         /* Enable CPU FDI TX PLL, always on for Ironlake */
1969         reg = FDI_TX_CTL(pipe);
1970         temp = I915_READ(reg);
1971         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1972                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1973
1974                 POSTING_READ(reg);
1975                 udelay(100);
1976         }
1977 }
1978
1979 static void intel_flush_display_plane(struct drm_device *dev,
1980                                       int plane)
1981 {
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         u32 reg = DSPADDR(plane);
1984         I915_WRITE(reg, I915_READ(reg));
1985 }
1986
1987 /*
1988  * When we disable a pipe, we need to clear any pending scanline wait events
1989  * to avoid hanging the ring, which we assume we are waiting on.
1990  */
1991 static void intel_clear_scanline_wait(struct drm_device *dev)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         struct intel_ring_buffer *ring;
1995         u32 tmp;
1996
1997         if (IS_GEN2(dev))
1998                 /* Can't break the hang on i8xx */
1999                 return;
2000
2001         ring = &dev_priv->render_ring;
2002         tmp = I915_READ_CTL(ring);
2003         if (tmp & RING_WAIT)
2004                 I915_WRITE_CTL(ring, tmp);
2005 }
2006
2007 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2008 {
2009         struct drm_i915_gem_object *obj;
2010         struct drm_i915_private *dev_priv;
2011
2012         if (crtc->fb == NULL)
2013                 return;
2014
2015         obj = to_intel_framebuffer(crtc->fb)->obj;
2016         dev_priv = crtc->dev->dev_private;
2017         wait_event(dev_priv->pending_flip_queue,
2018                    atomic_read(&obj->pending_flip) == 0);
2019 }
2020
2021 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2022 {
2023         struct drm_device *dev = crtc->dev;
2024         struct drm_i915_private *dev_priv = dev->dev_private;
2025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2026         int pipe = intel_crtc->pipe;
2027         int plane = intel_crtc->plane;
2028         u32 reg, temp;
2029
2030         if (intel_crtc->active)
2031                 return;
2032
2033         intel_crtc->active = true;
2034         intel_update_watermarks(dev);
2035
2036         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2037                 temp = I915_READ(PCH_LVDS);
2038                 if ((temp & LVDS_PORT_EN) == 0)
2039                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2040         }
2041
2042         ironlake_fdi_enable(crtc);
2043
2044         /* Enable panel fitting for LVDS */
2045         if (dev_priv->pch_pf_size &&
2046             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2047                 /* Force use of hard-coded filter coefficients
2048                  * as some pre-programmed values are broken,
2049                  * e.g. x201.
2050                  */
2051                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2052                            PF_ENABLE | PF_FILTER_MED_3x3);
2053                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2054                            dev_priv->pch_pf_pos);
2055                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2056                            dev_priv->pch_pf_size);
2057         }
2058
2059         /* Enable CPU pipe */
2060         reg = PIPECONF(pipe);
2061         temp = I915_READ(reg);
2062         if ((temp & PIPECONF_ENABLE) == 0) {
2063                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2064                 POSTING_READ(reg);
2065                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2066         }
2067
2068         /* configure and enable CPU plane */
2069         reg = DSPCNTR(plane);
2070         temp = I915_READ(reg);
2071         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2072                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2073                 intel_flush_display_plane(dev, plane);
2074         }
2075
2076         /* For PCH output, training FDI link */
2077         if (IS_GEN6(dev))
2078                 gen6_fdi_link_train(crtc);
2079         else
2080                 ironlake_fdi_link_train(crtc);
2081
2082         /* enable PCH DPLL */
2083         reg = PCH_DPLL(pipe);
2084         temp = I915_READ(reg);
2085         if ((temp & DPLL_VCO_ENABLE) == 0) {
2086                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2087                 POSTING_READ(reg);
2088                 udelay(200);
2089         }
2090
2091         if (HAS_PCH_CPT(dev)) {
2092                 /* Be sure PCH DPLL SEL is set */
2093                 temp = I915_READ(PCH_DPLL_SEL);
2094                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2095                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2096                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2097                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2098                 I915_WRITE(PCH_DPLL_SEL, temp);
2099         }
2100
2101         /* set transcoder timing */
2102         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2103         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2104         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2105
2106         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2107         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2108         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2109
2110         intel_fdi_normal_train(crtc);
2111
2112         /* For PCH DP, enable TRANS_DP_CTL */
2113         if (HAS_PCH_CPT(dev) &&
2114             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2115                 reg = TRANS_DP_CTL(pipe);
2116                 temp = I915_READ(reg);
2117                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2118                           TRANS_DP_SYNC_MASK);
2119                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2120                          TRANS_DP_ENH_FRAMING);
2121
2122                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2123                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2124                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2125                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2126
2127                 switch (intel_trans_dp_port_sel(crtc)) {
2128                 case PCH_DP_B:
2129                         temp |= TRANS_DP_PORT_SEL_B;
2130                         break;
2131                 case PCH_DP_C:
2132                         temp |= TRANS_DP_PORT_SEL_C;
2133                         break;
2134                 case PCH_DP_D:
2135                         temp |= TRANS_DP_PORT_SEL_D;
2136                         break;
2137                 default:
2138                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2139                         temp |= TRANS_DP_PORT_SEL_B;
2140                         break;
2141                 }
2142
2143                 I915_WRITE(reg, temp);
2144         }
2145
2146         /* enable PCH transcoder */
2147         reg = TRANSCONF(pipe);
2148         temp = I915_READ(reg);
2149         /*
2150          * make the BPC in transcoder be consistent with
2151          * that in pipeconf reg.
2152          */
2153         temp &= ~PIPE_BPC_MASK;
2154         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2155         I915_WRITE(reg, temp | TRANS_ENABLE);
2156         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2157                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2158
2159         intel_crtc_load_lut(crtc);
2160         intel_update_fbc(dev);
2161         intel_crtc_update_cursor(crtc, true);
2162 }
2163
2164 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2165 {
2166         struct drm_device *dev = crtc->dev;
2167         struct drm_i915_private *dev_priv = dev->dev_private;
2168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169         int pipe = intel_crtc->pipe;
2170         int plane = intel_crtc->plane;
2171         u32 reg, temp;
2172
2173         if (!intel_crtc->active)
2174                 return;
2175
2176         intel_crtc_wait_for_pending_flips(crtc);
2177         drm_vblank_off(dev, pipe);
2178         intel_crtc_update_cursor(crtc, false);
2179
2180         /* Disable display plane */
2181         reg = DSPCNTR(plane);
2182         temp = I915_READ(reg);
2183         if (temp & DISPLAY_PLANE_ENABLE) {
2184                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2185                 intel_flush_display_plane(dev, plane);
2186         }
2187
2188         if (dev_priv->cfb_plane == plane &&
2189             dev_priv->display.disable_fbc)
2190                 dev_priv->display.disable_fbc(dev);
2191
2192         /* disable cpu pipe, disable after all planes disabled */
2193         reg = PIPECONF(pipe);
2194         temp = I915_READ(reg);
2195         if (temp & PIPECONF_ENABLE) {
2196                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2197                 POSTING_READ(reg);
2198                 /* wait for cpu pipe off, pipe state */
2199                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2200         }
2201
2202         /* Disable PF */
2203         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2204         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2205
2206         /* disable CPU FDI tx and PCH FDI rx */
2207         reg = FDI_TX_CTL(pipe);
2208         temp = I915_READ(reg);
2209         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2210         POSTING_READ(reg);
2211
2212         reg = FDI_RX_CTL(pipe);
2213         temp = I915_READ(reg);
2214         temp &= ~(0x7 << 16);
2215         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2216         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2217
2218         POSTING_READ(reg);
2219         udelay(100);
2220
2221         /* Ironlake workaround, disable clock pointer after downing FDI */
2222         if (HAS_PCH_IBX(dev))
2223                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2224                            I915_READ(FDI_RX_CHICKEN(pipe) &
2225                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2226
2227         /* still set train pattern 1 */
2228         reg = FDI_TX_CTL(pipe);
2229         temp = I915_READ(reg);
2230         temp &= ~FDI_LINK_TRAIN_NONE;
2231         temp |= FDI_LINK_TRAIN_PATTERN_1;
2232         I915_WRITE(reg, temp);
2233
2234         reg = FDI_RX_CTL(pipe);
2235         temp = I915_READ(reg);
2236         if (HAS_PCH_CPT(dev)) {
2237                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2238                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2239         } else {
2240                 temp &= ~FDI_LINK_TRAIN_NONE;
2241                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2242         }
2243         /* BPC in FDI rx is consistent with that in PIPECONF */
2244         temp &= ~(0x07 << 16);
2245         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2246         I915_WRITE(reg, temp);
2247
2248         POSTING_READ(reg);
2249         udelay(100);
2250
2251         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2252                 temp = I915_READ(PCH_LVDS);
2253                 if (temp & LVDS_PORT_EN) {
2254                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2255                         POSTING_READ(PCH_LVDS);
2256                         udelay(100);
2257                 }
2258         }
2259
2260         /* disable PCH transcoder */
2261         reg = TRANSCONF(plane);
2262         temp = I915_READ(reg);
2263         if (temp & TRANS_ENABLE) {
2264                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2265                 /* wait for PCH transcoder off, transcoder state */
2266                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2267                         DRM_ERROR("failed to disable transcoder\n");
2268         }
2269
2270         if (HAS_PCH_CPT(dev)) {
2271                 /* disable TRANS_DP_CTL */
2272                 reg = TRANS_DP_CTL(pipe);
2273                 temp = I915_READ(reg);
2274                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2275                 I915_WRITE(reg, temp);
2276
2277                 /* disable DPLL_SEL */
2278                 temp = I915_READ(PCH_DPLL_SEL);
2279                 if (pipe == 0)
2280                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2281                 else
2282                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2283                 I915_WRITE(PCH_DPLL_SEL, temp);
2284         }
2285
2286         /* disable PCH DPLL */
2287         reg = PCH_DPLL(pipe);
2288         temp = I915_READ(reg);
2289         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2290
2291         /* Switch from PCDclk to Rawclk */
2292         reg = FDI_RX_CTL(pipe);
2293         temp = I915_READ(reg);
2294         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2295
2296         /* Disable CPU FDI TX PLL */
2297         reg = FDI_TX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2300
2301         POSTING_READ(reg);
2302         udelay(100);
2303
2304         reg = FDI_RX_CTL(pipe);
2305         temp = I915_READ(reg);
2306         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2307
2308         /* Wait for the clocks to turn off. */
2309         POSTING_READ(reg);
2310         udelay(100);
2311
2312         intel_crtc->active = false;
2313         intel_update_watermarks(dev);
2314         intel_update_fbc(dev);
2315         intel_clear_scanline_wait(dev);
2316 }
2317
2318 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2319 {
2320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321         int pipe = intel_crtc->pipe;
2322         int plane = intel_crtc->plane;
2323
2324         /* XXX: When our outputs are all unaware of DPMS modes other than off
2325          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2326          */
2327         switch (mode) {
2328         case DRM_MODE_DPMS_ON:
2329         case DRM_MODE_DPMS_STANDBY:
2330         case DRM_MODE_DPMS_SUSPEND:
2331                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2332                 ironlake_crtc_enable(crtc);
2333                 break;
2334
2335         case DRM_MODE_DPMS_OFF:
2336                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2337                 ironlake_crtc_disable(crtc);
2338                 break;
2339         }
2340 }
2341
2342 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2343 {
2344         if (!enable && intel_crtc->overlay) {
2345                 struct drm_device *dev = intel_crtc->base.dev;
2346
2347                 mutex_lock(&dev->struct_mutex);
2348                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2349                 mutex_unlock(&dev->struct_mutex);
2350         }
2351
2352         /* Let userspace switch the overlay on again. In most cases userspace
2353          * has to recompute where to put it anyway.
2354          */
2355 }
2356
2357 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2358 {
2359         struct drm_device *dev = crtc->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362         int pipe = intel_crtc->pipe;
2363         int plane = intel_crtc->plane;
2364         u32 reg, temp;
2365
2366         if (intel_crtc->active)
2367                 return;
2368
2369         intel_crtc->active = true;
2370         intel_update_watermarks(dev);
2371
2372         /* Enable the DPLL */
2373         reg = DPLL(pipe);
2374         temp = I915_READ(reg);
2375         if ((temp & DPLL_VCO_ENABLE) == 0) {
2376                 I915_WRITE(reg, temp);
2377
2378                 /* Wait for the clocks to stabilize. */
2379                 POSTING_READ(reg);
2380                 udelay(150);
2381
2382                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2383
2384                 /* Wait for the clocks to stabilize. */
2385                 POSTING_READ(reg);
2386                 udelay(150);
2387
2388                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2389
2390                 /* Wait for the clocks to stabilize. */
2391                 POSTING_READ(reg);
2392                 udelay(150);
2393         }
2394
2395         /* Enable the pipe */
2396         reg = PIPECONF(pipe);
2397         temp = I915_READ(reg);
2398         if ((temp & PIPECONF_ENABLE) == 0)
2399                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2400
2401         /* Enable the plane */
2402         reg = DSPCNTR(plane);
2403         temp = I915_READ(reg);
2404         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2405                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2406                 intel_flush_display_plane(dev, plane);
2407         }
2408
2409         intel_crtc_load_lut(crtc);
2410         intel_update_fbc(dev);
2411
2412         /* Give the overlay scaler a chance to enable if it's on this pipe */
2413         intel_crtc_dpms_overlay(intel_crtc, true);
2414         intel_crtc_update_cursor(crtc, true);
2415 }
2416
2417 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2418 {
2419         struct drm_device *dev = crtc->dev;
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422         int pipe = intel_crtc->pipe;
2423         int plane = intel_crtc->plane;
2424         u32 reg, temp;
2425
2426         if (!intel_crtc->active)
2427                 return;
2428
2429         /* Give the overlay scaler a chance to disable if it's on this pipe */
2430         intel_crtc_wait_for_pending_flips(crtc);
2431         drm_vblank_off(dev, pipe);
2432         intel_crtc_dpms_overlay(intel_crtc, false);
2433         intel_crtc_update_cursor(crtc, false);
2434
2435         if (dev_priv->cfb_plane == plane &&
2436             dev_priv->display.disable_fbc)
2437                 dev_priv->display.disable_fbc(dev);
2438
2439         /* Disable display plane */
2440         reg = DSPCNTR(plane);
2441         temp = I915_READ(reg);
2442         if (temp & DISPLAY_PLANE_ENABLE) {
2443                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2444                 /* Flush the plane changes */
2445                 intel_flush_display_plane(dev, plane);
2446
2447                 /* Wait for vblank for the disable to take effect */
2448                 if (IS_GEN2(dev))
2449                         intel_wait_for_vblank(dev, pipe);
2450         }
2451
2452         /* Don't disable pipe A or pipe A PLLs if needed */
2453         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2454                 goto done;
2455
2456         /* Next, disable display pipes */
2457         reg = PIPECONF(pipe);
2458         temp = I915_READ(reg);
2459         if (temp & PIPECONF_ENABLE) {
2460                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2461
2462                 /* Wait for the pipe to turn off */
2463                 POSTING_READ(reg);
2464                 intel_wait_for_pipe_off(dev, pipe);
2465         }
2466
2467         reg = DPLL(pipe);
2468         temp = I915_READ(reg);
2469         if (temp & DPLL_VCO_ENABLE) {
2470                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2471
2472                 /* Wait for the clocks to turn off. */
2473                 POSTING_READ(reg);
2474                 udelay(150);
2475         }
2476
2477 done:
2478         intel_crtc->active = false;
2479         intel_update_fbc(dev);
2480         intel_update_watermarks(dev);
2481         intel_clear_scanline_wait(dev);
2482 }
2483
2484 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2485 {
2486         /* XXX: When our outputs are all unaware of DPMS modes other than off
2487          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2488          */
2489         switch (mode) {
2490         case DRM_MODE_DPMS_ON:
2491         case DRM_MODE_DPMS_STANDBY:
2492         case DRM_MODE_DPMS_SUSPEND:
2493                 i9xx_crtc_enable(crtc);
2494                 break;
2495         case DRM_MODE_DPMS_OFF:
2496                 i9xx_crtc_disable(crtc);
2497                 break;
2498         }
2499 }
2500
2501 /**
2502  * Sets the power management mode of the pipe and plane.
2503  */
2504 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2505 {
2506         struct drm_device *dev = crtc->dev;
2507         struct drm_i915_private *dev_priv = dev->dev_private;
2508         struct drm_i915_master_private *master_priv;
2509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2510         int pipe = intel_crtc->pipe;
2511         bool enabled;
2512
2513         if (intel_crtc->dpms_mode == mode)
2514                 return;
2515
2516         intel_crtc->dpms_mode = mode;
2517
2518         dev_priv->display.dpms(crtc, mode);
2519
2520         if (!dev->primary->master)
2521                 return;
2522
2523         master_priv = dev->primary->master->driver_priv;
2524         if (!master_priv->sarea_priv)
2525                 return;
2526
2527         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2528
2529         switch (pipe) {
2530         case 0:
2531                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2532                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2533                 break;
2534         case 1:
2535                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2536                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2537                 break;
2538         default:
2539                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2540                 break;
2541         }
2542 }
2543
2544 static void intel_crtc_disable(struct drm_crtc *crtc)
2545 {
2546         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2547         struct drm_device *dev = crtc->dev;
2548
2549         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2550
2551         if (crtc->fb) {
2552                 mutex_lock(&dev->struct_mutex);
2553                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2554                 mutex_unlock(&dev->struct_mutex);
2555         }
2556 }
2557
2558 /* Prepare for a mode set.
2559  *
2560  * Note we could be a lot smarter here.  We need to figure out which outputs
2561  * will be enabled, which disabled (in short, how the config will changes)
2562  * and perform the minimum necessary steps to accomplish that, e.g. updating
2563  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2564  * panel fitting is in the proper state, etc.
2565  */
2566 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2567 {
2568         i9xx_crtc_disable(crtc);
2569 }
2570
2571 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2572 {
2573         i9xx_crtc_enable(crtc);
2574 }
2575
2576 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2577 {
2578         ironlake_crtc_disable(crtc);
2579 }
2580
2581 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2582 {
2583         ironlake_crtc_enable(crtc);
2584 }
2585
2586 void intel_encoder_prepare (struct drm_encoder *encoder)
2587 {
2588         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2589         /* lvds has its own version of prepare see intel_lvds_prepare */
2590         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2591 }
2592
2593 void intel_encoder_commit (struct drm_encoder *encoder)
2594 {
2595         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2596         /* lvds has its own version of commit see intel_lvds_commit */
2597         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2598 }
2599
2600 void intel_encoder_destroy(struct drm_encoder *encoder)
2601 {
2602         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2603
2604         drm_encoder_cleanup(encoder);
2605         kfree(intel_encoder);
2606 }
2607
2608 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2609                                   struct drm_display_mode *mode,
2610                                   struct drm_display_mode *adjusted_mode)
2611 {
2612         struct drm_device *dev = crtc->dev;
2613
2614         if (HAS_PCH_SPLIT(dev)) {
2615                 /* FDI link clock is fixed at 2.7G */
2616                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2617                         return false;
2618         }
2619
2620         /* XXX some encoders set the crtcinfo, others don't.
2621          * Obviously we need some form of conflict resolution here...
2622          */
2623         if (adjusted_mode->crtc_htotal == 0)
2624                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2625
2626         return true;
2627 }
2628
2629 static int i945_get_display_clock_speed(struct drm_device *dev)
2630 {
2631         return 400000;
2632 }
2633
2634 static int i915_get_display_clock_speed(struct drm_device *dev)
2635 {
2636         return 333000;
2637 }
2638
2639 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2640 {
2641         return 200000;
2642 }
2643
2644 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2645 {
2646         u16 gcfgc = 0;
2647
2648         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2649
2650         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2651                 return 133000;
2652         else {
2653                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2654                 case GC_DISPLAY_CLOCK_333_MHZ:
2655                         return 333000;
2656                 default:
2657                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2658                         return 190000;
2659                 }
2660         }
2661 }
2662
2663 static int i865_get_display_clock_speed(struct drm_device *dev)
2664 {
2665         return 266000;
2666 }
2667
2668 static int i855_get_display_clock_speed(struct drm_device *dev)
2669 {
2670         u16 hpllcc = 0;
2671         /* Assume that the hardware is in the high speed state.  This
2672          * should be the default.
2673          */
2674         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2675         case GC_CLOCK_133_200:
2676         case GC_CLOCK_100_200:
2677                 return 200000;
2678         case GC_CLOCK_166_250:
2679                 return 250000;
2680         case GC_CLOCK_100_133:
2681                 return 133000;
2682         }
2683
2684         /* Shouldn't happen */
2685         return 0;
2686 }
2687
2688 static int i830_get_display_clock_speed(struct drm_device *dev)
2689 {
2690         return 133000;
2691 }
2692
2693 struct fdi_m_n {
2694         u32        tu;
2695         u32        gmch_m;
2696         u32        gmch_n;
2697         u32        link_m;
2698         u32        link_n;
2699 };
2700
2701 static void
2702 fdi_reduce_ratio(u32 *num, u32 *den)
2703 {
2704         while (*num > 0xffffff || *den > 0xffffff) {
2705                 *num >>= 1;
2706                 *den >>= 1;
2707         }
2708 }
2709
2710 #define DATA_N 0x800000
2711 #define LINK_N 0x80000
2712
2713 static void
2714 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2715                      int link_clock, struct fdi_m_n *m_n)
2716 {
2717         u64 temp;
2718
2719         m_n->tu = 64; /* default size */
2720
2721         temp = (u64) DATA_N * pixel_clock;
2722         temp = div_u64(temp, link_clock);
2723         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2724         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2725         m_n->gmch_n = DATA_N;
2726         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2727
2728         temp = (u64) LINK_N * pixel_clock;
2729         m_n->link_m = div_u64(temp, link_clock);
2730         m_n->link_n = LINK_N;
2731         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2732 }
2733
2734
2735 struct intel_watermark_params {
2736         unsigned long fifo_size;
2737         unsigned long max_wm;
2738         unsigned long default_wm;
2739         unsigned long guard_size;
2740         unsigned long cacheline_size;
2741 };
2742
2743 /* Pineview has different values for various configs */
2744 static struct intel_watermark_params pineview_display_wm = {
2745         PINEVIEW_DISPLAY_FIFO,
2746         PINEVIEW_MAX_WM,
2747         PINEVIEW_DFT_WM,
2748         PINEVIEW_GUARD_WM,
2749         PINEVIEW_FIFO_LINE_SIZE
2750 };
2751 static struct intel_watermark_params pineview_display_hplloff_wm = {
2752         PINEVIEW_DISPLAY_FIFO,
2753         PINEVIEW_MAX_WM,
2754         PINEVIEW_DFT_HPLLOFF_WM,
2755         PINEVIEW_GUARD_WM,
2756         PINEVIEW_FIFO_LINE_SIZE
2757 };
2758 static struct intel_watermark_params pineview_cursor_wm = {
2759         PINEVIEW_CURSOR_FIFO,
2760         PINEVIEW_CURSOR_MAX_WM,
2761         PINEVIEW_CURSOR_DFT_WM,
2762         PINEVIEW_CURSOR_GUARD_WM,
2763         PINEVIEW_FIFO_LINE_SIZE,
2764 };
2765 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2766         PINEVIEW_CURSOR_FIFO,
2767         PINEVIEW_CURSOR_MAX_WM,
2768         PINEVIEW_CURSOR_DFT_WM,
2769         PINEVIEW_CURSOR_GUARD_WM,
2770         PINEVIEW_FIFO_LINE_SIZE
2771 };
2772 static struct intel_watermark_params g4x_wm_info = {
2773         G4X_FIFO_SIZE,
2774         G4X_MAX_WM,
2775         G4X_MAX_WM,
2776         2,
2777         G4X_FIFO_LINE_SIZE,
2778 };
2779 static struct intel_watermark_params g4x_cursor_wm_info = {
2780         I965_CURSOR_FIFO,
2781         I965_CURSOR_MAX_WM,
2782         I965_CURSOR_DFT_WM,
2783         2,
2784         G4X_FIFO_LINE_SIZE,
2785 };
2786 static struct intel_watermark_params i965_cursor_wm_info = {
2787         I965_CURSOR_FIFO,
2788         I965_CURSOR_MAX_WM,
2789         I965_CURSOR_DFT_WM,
2790         2,
2791         I915_FIFO_LINE_SIZE,
2792 };
2793 static struct intel_watermark_params i945_wm_info = {
2794         I945_FIFO_SIZE,
2795         I915_MAX_WM,
2796         1,
2797         2,
2798         I915_FIFO_LINE_SIZE
2799 };
2800 static struct intel_watermark_params i915_wm_info = {
2801         I915_FIFO_SIZE,
2802         I915_MAX_WM,
2803         1,
2804         2,
2805         I915_FIFO_LINE_SIZE
2806 };
2807 static struct intel_watermark_params i855_wm_info = {
2808         I855GM_FIFO_SIZE,
2809         I915_MAX_WM,
2810         1,
2811         2,
2812         I830_FIFO_LINE_SIZE
2813 };
2814 static struct intel_watermark_params i830_wm_info = {
2815         I830_FIFO_SIZE,
2816         I915_MAX_WM,
2817         1,
2818         2,
2819         I830_FIFO_LINE_SIZE
2820 };
2821
2822 static struct intel_watermark_params ironlake_display_wm_info = {
2823         ILK_DISPLAY_FIFO,
2824         ILK_DISPLAY_MAXWM,
2825         ILK_DISPLAY_DFTWM,
2826         2,
2827         ILK_FIFO_LINE_SIZE
2828 };
2829
2830 static struct intel_watermark_params ironlake_cursor_wm_info = {
2831         ILK_CURSOR_FIFO,
2832         ILK_CURSOR_MAXWM,
2833         ILK_CURSOR_DFTWM,
2834         2,
2835         ILK_FIFO_LINE_SIZE
2836 };
2837
2838 static struct intel_watermark_params ironlake_display_srwm_info = {
2839         ILK_DISPLAY_SR_FIFO,
2840         ILK_DISPLAY_MAX_SRWM,
2841         ILK_DISPLAY_DFT_SRWM,
2842         2,
2843         ILK_FIFO_LINE_SIZE
2844 };
2845
2846 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2847         ILK_CURSOR_SR_FIFO,
2848         ILK_CURSOR_MAX_SRWM,
2849         ILK_CURSOR_DFT_SRWM,
2850         2,
2851         ILK_FIFO_LINE_SIZE
2852 };
2853
2854 /**
2855  * intel_calculate_wm - calculate watermark level
2856  * @clock_in_khz: pixel clock
2857  * @wm: chip FIFO params
2858  * @pixel_size: display pixel size
2859  * @latency_ns: memory latency for the platform
2860  *
2861  * Calculate the watermark level (the level at which the display plane will
2862  * start fetching from memory again).  Each chip has a different display
2863  * FIFO size and allocation, so the caller needs to figure that out and pass
2864  * in the correct intel_watermark_params structure.
2865  *
2866  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2867  * on the pixel size.  When it reaches the watermark level, it'll start
2868  * fetching FIFO line sized based chunks from memory until the FIFO fills
2869  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2870  * will occur, and a display engine hang could result.
2871  */
2872 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2873                                         struct intel_watermark_params *wm,
2874                                         int pixel_size,
2875                                         unsigned long latency_ns)
2876 {
2877         long entries_required, wm_size;
2878
2879         /*
2880          * Note: we need to make sure we don't overflow for various clock &
2881          * latency values.
2882          * clocks go from a few thousand to several hundred thousand.
2883          * latency is usually a few thousand
2884          */
2885         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2886                 1000;
2887         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2888
2889         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2890
2891         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2892
2893         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2894
2895         /* Don't promote wm_size to unsigned... */
2896         if (wm_size > (long)wm->max_wm)
2897                 wm_size = wm->max_wm;
2898         if (wm_size <= 0)
2899                 wm_size = wm->default_wm;
2900         return wm_size;
2901 }
2902
2903 struct cxsr_latency {
2904         int is_desktop;
2905         int is_ddr3;
2906         unsigned long fsb_freq;
2907         unsigned long mem_freq;
2908         unsigned long display_sr;
2909         unsigned long display_hpll_disable;
2910         unsigned long cursor_sr;
2911         unsigned long cursor_hpll_disable;
2912 };
2913
2914 static const struct cxsr_latency cxsr_latency_table[] = {
2915         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2916         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2917         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2918         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2919         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2920
2921         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2922         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2923         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2924         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2925         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2926
2927         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2928         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2929         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2930         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2931         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2932
2933         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2934         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2935         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2936         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2937         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2938
2939         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2940         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2941         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2942         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2943         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2944
2945         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2946         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2947         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2948         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2949         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2950 };
2951
2952 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2953                                                          int is_ddr3,
2954                                                          int fsb,
2955                                                          int mem)
2956 {
2957         const struct cxsr_latency *latency;
2958         int i;
2959
2960         if (fsb == 0 || mem == 0)
2961                 return NULL;
2962
2963         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2964                 latency = &cxsr_latency_table[i];
2965                 if (is_desktop == latency->is_desktop &&
2966                     is_ddr3 == latency->is_ddr3 &&
2967                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2968                         return latency;
2969         }
2970
2971         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2972
2973         return NULL;
2974 }
2975
2976 static void pineview_disable_cxsr(struct drm_device *dev)
2977 {
2978         struct drm_i915_private *dev_priv = dev->dev_private;
2979
2980         /* deactivate cxsr */
2981         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2982 }
2983
2984 /*
2985  * Latency for FIFO fetches is dependent on several factors:
2986  *   - memory configuration (speed, channels)
2987  *   - chipset
2988  *   - current MCH state
2989  * It can be fairly high in some situations, so here we assume a fairly
2990  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2991  * set this value too high, the FIFO will fetch frequently to stay full)
2992  * and power consumption (set it too low to save power and we might see
2993  * FIFO underruns and display "flicker").
2994  *
2995  * A value of 5us seems to be a good balance; safe for very low end
2996  * platforms but not overly aggressive on lower latency configs.
2997  */
2998 static const int latency_ns = 5000;
2999
3000 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3001 {
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         uint32_t dsparb = I915_READ(DSPARB);
3004         int size;
3005
3006         size = dsparb & 0x7f;
3007         if (plane)
3008                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3009
3010         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3011                       plane ? "B" : "A", size);
3012
3013         return size;
3014 }
3015
3016 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3017 {
3018         struct drm_i915_private *dev_priv = dev->dev_private;
3019         uint32_t dsparb = I915_READ(DSPARB);
3020         int size;
3021
3022         size = dsparb & 0x1ff;
3023         if (plane)
3024                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3025         size >>= 1; /* Convert to cachelines */
3026
3027         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3028                       plane ? "B" : "A", size);
3029
3030         return size;
3031 }
3032
3033 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3034 {
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         uint32_t dsparb = I915_READ(DSPARB);
3037         int size;
3038
3039         size = dsparb & 0x7f;
3040         size >>= 2; /* Convert to cachelines */
3041
3042         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3043                       plane ? "B" : "A",
3044                       size);
3045
3046         return size;
3047 }
3048
3049 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3050 {
3051         struct drm_i915_private *dev_priv = dev->dev_private;
3052         uint32_t dsparb = I915_READ(DSPARB);
3053         int size;
3054
3055         size = dsparb & 0x7f;
3056         size >>= 1; /* Convert to cachelines */
3057
3058         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3059                       plane ? "B" : "A", size);
3060
3061         return size;
3062 }
3063
3064 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3065                                int planeb_clock, int sr_hdisplay, int unused,
3066                                int pixel_size)
3067 {
3068         struct drm_i915_private *dev_priv = dev->dev_private;
3069         const struct cxsr_latency *latency;
3070         u32 reg;
3071         unsigned long wm;
3072         int sr_clock;
3073
3074         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3075                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3076         if (!latency) {
3077                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3078                 pineview_disable_cxsr(dev);
3079                 return;
3080         }
3081
3082         if (!planea_clock || !planeb_clock) {
3083                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3084
3085                 /* Display SR */
3086                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3087                                         pixel_size, latency->display_sr);
3088                 reg = I915_READ(DSPFW1);
3089                 reg &= ~DSPFW_SR_MASK;
3090                 reg |= wm << DSPFW_SR_SHIFT;
3091                 I915_WRITE(DSPFW1, reg);
3092                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3093
3094                 /* cursor SR */
3095                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3096                                         pixel_size, latency->cursor_sr);
3097                 reg = I915_READ(DSPFW3);
3098                 reg &= ~DSPFW_CURSOR_SR_MASK;
3099                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3100                 I915_WRITE(DSPFW3, reg);
3101
3102                 /* Display HPLL off SR */
3103                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3104                                         pixel_size, latency->display_hpll_disable);
3105                 reg = I915_READ(DSPFW3);
3106                 reg &= ~DSPFW_HPLL_SR_MASK;
3107                 reg |= wm & DSPFW_HPLL_SR_MASK;
3108                 I915_WRITE(DSPFW3, reg);
3109
3110                 /* cursor HPLL off SR */
3111                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3112                                         pixel_size, latency->cursor_hpll_disable);
3113                 reg = I915_READ(DSPFW3);
3114                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3115                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3116                 I915_WRITE(DSPFW3, reg);
3117                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3118
3119                 /* activate cxsr */
3120                 I915_WRITE(DSPFW3,
3121                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3122                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3123         } else {
3124                 pineview_disable_cxsr(dev);
3125                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3126         }
3127 }
3128
3129 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3130                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3131                           int pixel_size)
3132 {
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134         int total_size, cacheline_size;
3135         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3136         struct intel_watermark_params planea_params, planeb_params;
3137         unsigned long line_time_us;
3138         int sr_clock, sr_entries = 0, entries_required;
3139
3140         /* Create copies of the base settings for each pipe */
3141         planea_params = planeb_params = g4x_wm_info;
3142
3143         /* Grab a couple of global values before we overwrite them */
3144         total_size = planea_params.fifo_size;
3145         cacheline_size = planea_params.cacheline_size;
3146
3147         /*
3148          * Note: we need to make sure we don't overflow for various clock &
3149          * latency values.
3150          * clocks go from a few thousand to several hundred thousand.
3151          * latency is usually a few thousand
3152          */
3153         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3154                 1000;
3155         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3156         planea_wm = entries_required + planea_params.guard_size;
3157
3158         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3159                 1000;
3160         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3161         planeb_wm = entries_required + planeb_params.guard_size;
3162
3163         cursora_wm = cursorb_wm = 16;
3164         cursor_sr = 32;
3165
3166         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3167
3168         /* Calc sr entries for one plane configs */
3169         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3170                 /* self-refresh has much higher latency */
3171                 static const int sr_latency_ns = 12000;
3172
3173                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3174                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3175
3176                 /* Use ns/us then divide to preserve precision */
3177                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3178                         pixel_size * sr_hdisplay;
3179                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3180
3181                 entries_required = (((sr_latency_ns / line_time_us) +
3182                                      1000) / 1000) * pixel_size * 64;
3183                 entries_required = DIV_ROUND_UP(entries_required,
3184                                                 g4x_cursor_wm_info.cacheline_size);
3185                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3186
3187                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3188                         cursor_sr = g4x_cursor_wm_info.max_wm;
3189                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3190                               "cursor %d\n", sr_entries, cursor_sr);
3191
3192                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3193         } else {
3194                 /* Turn off self refresh if both pipes are enabled */
3195                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3196                            & ~FW_BLC_SELF_EN);
3197         }
3198
3199         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3200                   planea_wm, planeb_wm, sr_entries);
3201
3202         planea_wm &= 0x3f;
3203         planeb_wm &= 0x3f;
3204
3205         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3206                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3207                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3208         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3209                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3210         /* HPLL off in SR has some issues on G4x... disable it */
3211         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3212                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3213 }
3214
3215 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3216                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3217                            int pixel_size)
3218 {
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         unsigned long line_time_us;
3221         int sr_clock, sr_entries, srwm = 1;
3222         int cursor_sr = 16;
3223
3224         /* Calc sr entries for one plane configs */
3225         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3226                 /* self-refresh has much higher latency */
3227                 static const int sr_latency_ns = 12000;
3228
3229                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3230                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3231
3232                 /* Use ns/us then divide to preserve precision */
3233                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3234                         pixel_size * sr_hdisplay;
3235                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3236                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3237                 srwm = I965_FIFO_SIZE - sr_entries;
3238                 if (srwm < 0)
3239                         srwm = 1;
3240                 srwm &= 0x1ff;
3241
3242                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3243                         pixel_size * 64;
3244                 sr_entries = DIV_ROUND_UP(sr_entries,
3245                                           i965_cursor_wm_info.cacheline_size);
3246                 cursor_sr = i965_cursor_wm_info.fifo_size -
3247                         (sr_entries + i965_cursor_wm_info.guard_size);
3248
3249                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3250                         cursor_sr = i965_cursor_wm_info.max_wm;
3251
3252                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3253                               "cursor %d\n", srwm, cursor_sr);
3254
3255                 if (IS_CRESTLINE(dev))
3256                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3257         } else {
3258                 /* Turn off self refresh if both pipes are enabled */
3259                 if (IS_CRESTLINE(dev))
3260                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3261                                    & ~FW_BLC_SELF_EN);
3262         }
3263
3264         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3265                       srwm);
3266
3267         /* 965 has limitations... */
3268         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3269                    (8 << 0));
3270         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3271         /* update cursor SR watermark */
3272         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3273 }
3274
3275 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3276                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3277                            int pixel_size)
3278 {
3279         struct drm_i915_private *dev_priv = dev->dev_private;
3280         uint32_t fwater_lo;
3281         uint32_t fwater_hi;
3282         int total_size, cacheline_size, cwm, srwm = 1;
3283         int planea_wm, planeb_wm;
3284         struct intel_watermark_params planea_params, planeb_params;
3285         unsigned long line_time_us;
3286         int sr_clock, sr_entries = 0;
3287
3288         /* Create copies of the base settings for each pipe */
3289         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3290                 planea_params = planeb_params = i945_wm_info;
3291         else if (!IS_GEN2(dev))
3292                 planea_params = planeb_params = i915_wm_info;
3293         else
3294                 planea_params = planeb_params = i855_wm_info;
3295
3296         /* Grab a couple of global values before we overwrite them */
3297         total_size = planea_params.fifo_size;
3298         cacheline_size = planea_params.cacheline_size;
3299
3300         /* Update per-plane FIFO sizes */
3301         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3302         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3303
3304         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3305                                        pixel_size, latency_ns);
3306         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3307                                        pixel_size, latency_ns);
3308         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3309
3310         /*
3311          * Overlay gets an aggressive default since video jitter is bad.
3312          */
3313         cwm = 2;
3314
3315         /* Calc sr entries for one plane configs */
3316         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3317             (!planea_clock || !planeb_clock)) {
3318                 /* self-refresh has much higher latency */
3319                 static const int sr_latency_ns = 6000;
3320
3321                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3322                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3323
3324                 /* Use ns/us then divide to preserve precision */
3325                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3326                         pixel_size * sr_hdisplay;
3327                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3328                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3329                 srwm = total_size - sr_entries;
3330                 if (srwm < 0)
3331                         srwm = 1;
3332
3333                 if (IS_I945G(dev) || IS_I945GM(dev))
3334                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3335                 else if (IS_I915GM(dev)) {
3336                         /* 915M has a smaller SRWM field */
3337                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3338                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3339                 }
3340         } else {
3341                 /* Turn off self refresh if both pipes are enabled */
3342                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3343                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3344                                    & ~FW_BLC_SELF_EN);
3345                 } else if (IS_I915GM(dev)) {
3346                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3347                 }
3348         }
3349
3350         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3351                       planea_wm, planeb_wm, cwm, srwm);
3352
3353         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3354         fwater_hi = (cwm & 0x1f);
3355
3356         /* Set request length to 8 cachelines per fetch */
3357         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3358         fwater_hi = fwater_hi | (1 << 8);
3359
3360         I915_WRITE(FW_BLC, fwater_lo);
3361         I915_WRITE(FW_BLC2, fwater_hi);
3362 }
3363
3364 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3365                            int unused2, int unused3, int pixel_size)
3366 {
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3369         int planea_wm;
3370
3371         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3372
3373         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3374                                        pixel_size, latency_ns);
3375         fwater_lo |= (3<<8) | planea_wm;
3376
3377         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3378
3379         I915_WRITE(FW_BLC, fwater_lo);
3380 }
3381
3382 #define ILK_LP0_PLANE_LATENCY           700
3383 #define ILK_LP0_CURSOR_LATENCY          1300
3384
3385 static bool ironlake_compute_wm0(struct drm_device *dev,
3386                                  int pipe,
3387                                  int *plane_wm,
3388                                  int *cursor_wm)
3389 {
3390         struct drm_crtc *crtc;
3391         int htotal, hdisplay, clock, pixel_size = 0;
3392         int line_time_us, line_count, entries;
3393
3394         crtc = intel_get_crtc_for_pipe(dev, pipe);
3395         if (crtc->fb == NULL || !crtc->enabled)
3396                 return false;
3397
3398         htotal = crtc->mode.htotal;
3399         hdisplay = crtc->mode.hdisplay;
3400         clock = crtc->mode.clock;
3401         pixel_size = crtc->fb->bits_per_pixel / 8;
3402
3403         /* Use the small buffer method to calculate plane watermark */
3404         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3405         entries = DIV_ROUND_UP(entries,
3406                                ironlake_display_wm_info.cacheline_size);
3407         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3408         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3409                 *plane_wm = ironlake_display_wm_info.max_wm;
3410
3411         /* Use the large buffer method to calculate cursor watermark */
3412         line_time_us = ((htotal * 1000) / clock);
3413         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3414         entries = line_count * 64 * pixel_size;
3415         entries = DIV_ROUND_UP(entries,
3416                                ironlake_cursor_wm_info.cacheline_size);
3417         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3418         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3419                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3420
3421         return true;
3422 }
3423
3424 static void ironlake_update_wm(struct drm_device *dev,
3425                                int planea_clock, int planeb_clock,
3426                                int sr_hdisplay, int sr_htotal,
3427                                int pixel_size)
3428 {
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         int plane_wm, cursor_wm, enabled;
3431         int tmp;
3432
3433         enabled = 0;
3434         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3435                 I915_WRITE(WM0_PIPEA_ILK,
3436                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3437                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3438                               " plane %d, " "cursor: %d\n",
3439                               plane_wm, cursor_wm);
3440                 enabled++;
3441         }
3442
3443         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3444                 I915_WRITE(WM0_PIPEB_ILK,
3445                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3446                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3447                               " plane %d, cursor: %d\n",
3448                               plane_wm, cursor_wm);
3449                 enabled++;
3450         }
3451
3452         /*
3453          * Calculate and update the self-refresh watermark only when one
3454          * display plane is used.
3455          */
3456         tmp = 0;
3457         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3458                 unsigned long line_time_us;
3459                 int small, large, plane_fbc;
3460                 int sr_clock, entries;
3461                 int line_count, line_size;
3462                 /* Read the self-refresh latency. The unit is 0.5us */
3463                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3464
3465                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3466                 line_time_us = (sr_htotal * 1000) / sr_clock;
3467
3468                 /* Use ns/us then divide to preserve precision */
3469                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3470                         / 1000;
3471                 line_size = sr_hdisplay * pixel_size;
3472
3473                 /* Use the minimum of the small and large buffer method for primary */
3474                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3475                 large = line_count * line_size;
3476
3477                 entries = DIV_ROUND_UP(min(small, large),
3478                                        ironlake_display_srwm_info.cacheline_size);
3479
3480                 plane_fbc = entries * 64;
3481                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3482
3483                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3484                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3485                         plane_wm = ironlake_display_srwm_info.max_wm;
3486
3487                 /* calculate the self-refresh watermark for display cursor */
3488                 entries = line_count * pixel_size * 64;
3489                 entries = DIV_ROUND_UP(entries,
3490                                        ironlake_cursor_srwm_info.cacheline_size);
3491
3492                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3493                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3494                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3495
3496                 /* configure watermark and enable self-refresh */
3497                 tmp = (WM1_LP_SR_EN |
3498                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3499                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3500                        (plane_wm << WM1_LP_SR_SHIFT) |
3501                        cursor_wm);
3502                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3503                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3504         }
3505         I915_WRITE(WM1_LP_ILK, tmp);
3506         /* XXX setup WM2 and WM3 */
3507 }
3508
3509 /**
3510  * intel_update_watermarks - update FIFO watermark values based on current modes
3511  *
3512  * Calculate watermark values for the various WM regs based on current mode
3513  * and plane configuration.
3514  *
3515  * There are several cases to deal with here:
3516  *   - normal (i.e. non-self-refresh)
3517  *   - self-refresh (SR) mode
3518  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3519  *   - lines are small relative to FIFO size (buffer can hold more than 2
3520  *     lines), so need to account for TLB latency
3521  *
3522  *   The normal calculation is:
3523  *     watermark = dotclock * bytes per pixel * latency
3524  *   where latency is platform & configuration dependent (we assume pessimal
3525  *   values here).
3526  *
3527  *   The SR calculation is:
3528  *     watermark = (trunc(latency/line time)+1) * surface width *
3529  *       bytes per pixel
3530  *   where
3531  *     line time = htotal / dotclock
3532  *     surface width = hdisplay for normal plane and 64 for cursor
3533  *   and latency is assumed to be high, as above.
3534  *
3535  * The final value programmed to the register should always be rounded up,
3536  * and include an extra 2 entries to account for clock crossings.
3537  *
3538  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3539  * to set the non-SR watermarks to 8.
3540  */
3541 static void intel_update_watermarks(struct drm_device *dev)
3542 {
3543         struct drm_i915_private *dev_priv = dev->dev_private;
3544         struct drm_crtc *crtc;
3545         int sr_hdisplay = 0;
3546         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3547         int enabled = 0, pixel_size = 0;
3548         int sr_htotal = 0;
3549
3550         if (!dev_priv->display.update_wm)
3551                 return;
3552
3553         /* Get the clock config from both planes */
3554         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3555                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3556                 if (intel_crtc->active) {
3557                         enabled++;
3558                         if (intel_crtc->plane == 0) {
3559                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3560                                               intel_crtc->pipe, crtc->mode.clock);
3561                                 planea_clock = crtc->mode.clock;
3562                         } else {
3563                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3564                                               intel_crtc->pipe, crtc->mode.clock);
3565                                 planeb_clock = crtc->mode.clock;
3566                         }
3567                         sr_hdisplay = crtc->mode.hdisplay;
3568                         sr_clock = crtc->mode.clock;
3569                         sr_htotal = crtc->mode.htotal;
3570                         if (crtc->fb)
3571                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3572                         else
3573                                 pixel_size = 4; /* by default */
3574                 }
3575         }
3576
3577         if (enabled <= 0)
3578                 return;
3579
3580         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3581                                     sr_hdisplay, sr_htotal, pixel_size);
3582 }
3583
3584 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3585                                struct drm_display_mode *mode,
3586                                struct drm_display_mode *adjusted_mode,
3587                                int x, int y,
3588                                struct drm_framebuffer *old_fb)
3589 {
3590         struct drm_device *dev = crtc->dev;
3591         struct drm_i915_private *dev_priv = dev->dev_private;
3592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593         int pipe = intel_crtc->pipe;
3594         int plane = intel_crtc->plane;
3595         u32 fp_reg, dpll_reg;
3596         int refclk, num_connectors = 0;
3597         intel_clock_t clock, reduced_clock;
3598         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3599         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3600         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3601         struct intel_encoder *has_edp_encoder = NULL;
3602         struct drm_mode_config *mode_config = &dev->mode_config;
3603         struct intel_encoder *encoder;
3604         const intel_limit_t *limit;
3605         int ret;
3606         struct fdi_m_n m_n = {0};
3607         u32 reg, temp;
3608         int target_clock;
3609
3610         drm_vblank_pre_modeset(dev, pipe);
3611
3612         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3613                 if (encoder->base.crtc != crtc)
3614                         continue;
3615
3616                 switch (encoder->type) {
3617                 case INTEL_OUTPUT_LVDS:
3618                         is_lvds = true;
3619                         break;
3620                 case INTEL_OUTPUT_SDVO:
3621                 case INTEL_OUTPUT_HDMI:
3622                         is_sdvo = true;
3623                         if (encoder->needs_tv_clock)
3624                                 is_tv = true;
3625                         break;
3626                 case INTEL_OUTPUT_DVO:
3627                         is_dvo = true;
3628                         break;
3629                 case INTEL_OUTPUT_TVOUT:
3630                         is_tv = true;
3631                         break;
3632                 case INTEL_OUTPUT_ANALOG:
3633                         is_crt = true;
3634                         break;
3635                 case INTEL_OUTPUT_DISPLAYPORT:
3636                         is_dp = true;
3637                         break;
3638                 case INTEL_OUTPUT_EDP:
3639                         has_edp_encoder = encoder;
3640                         break;
3641                 }
3642
3643                 num_connectors++;
3644         }
3645
3646         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3647                 refclk = dev_priv->lvds_ssc_freq * 1000;
3648                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3649                               refclk / 1000);
3650         } else if (!IS_GEN2(dev)) {
3651                 refclk = 96000;
3652                 if (HAS_PCH_SPLIT(dev) &&
3653                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3654                         refclk = 120000; /* 120Mhz refclk */
3655         } else {
3656                 refclk = 48000;
3657         }
3658
3659         /*
3660          * Returns a set of divisors for the desired target clock with the given
3661          * refclk, or FALSE.  The returned values represent the clock equation:
3662          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3663          */
3664         limit = intel_limit(crtc);
3665         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3666         if (!ok) {
3667                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3668                 drm_vblank_post_modeset(dev, pipe);
3669                 return -EINVAL;
3670         }
3671
3672         /* Ensure that the cursor is valid for the new mode before changing... */
3673         intel_crtc_update_cursor(crtc, true);
3674
3675         if (is_lvds && dev_priv->lvds_downclock_avail) {
3676                 has_reduced_clock = limit->find_pll(limit, crtc,
3677                                                     dev_priv->lvds_downclock,
3678                                                     refclk,
3679                                                     &reduced_clock);
3680                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3681                         /*
3682                          * If the different P is found, it means that we can't
3683                          * switch the display clock by using the FP0/FP1.
3684                          * In such case we will disable the LVDS downclock
3685                          * feature.
3686                          */
3687                         DRM_DEBUG_KMS("Different P is found for "
3688                                       "LVDS clock/downclock\n");
3689                         has_reduced_clock = 0;
3690                 }
3691         }
3692         /* SDVO TV has fixed PLL values depend on its clock range,
3693            this mirrors vbios setting. */
3694         if (is_sdvo && is_tv) {
3695                 if (adjusted_mode->clock >= 100000
3696                     && adjusted_mode->clock < 140500) {
3697                         clock.p1 = 2;
3698                         clock.p2 = 10;
3699                         clock.n = 3;
3700                         clock.m1 = 16;
3701                         clock.m2 = 8;
3702                 } else if (adjusted_mode->clock >= 140500
3703                            && adjusted_mode->clock <= 200000) {
3704                         clock.p1 = 1;
3705                         clock.p2 = 10;
3706                         clock.n = 6;
3707                         clock.m1 = 12;
3708                         clock.m2 = 8;
3709                 }
3710         }
3711
3712         /* FDI link */
3713         if (HAS_PCH_SPLIT(dev)) {
3714                 int lane = 0, link_bw, bpp;
3715                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3716                    according to current link config */
3717                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3718                         target_clock = mode->clock;
3719                         intel_edp_link_config(has_edp_encoder,
3720                                               &lane, &link_bw);
3721                 } else {
3722                         /* [e]DP over FDI requires target mode clock
3723                            instead of link clock */
3724                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3725                                 target_clock = mode->clock;
3726                         else
3727                                 target_clock = adjusted_mode->clock;
3728
3729                         /* FDI is a binary signal running at ~2.7GHz, encoding
3730                          * each output octet as 10 bits. The actual frequency
3731                          * is stored as a divider into a 100MHz clock, and the
3732                          * mode pixel clock is stored in units of 1KHz.
3733                          * Hence the bw of each lane in terms of the mode signal
3734                          * is:
3735                          */
3736                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3737                 }
3738
3739                 /* determine panel color depth */
3740                 temp = I915_READ(PIPECONF(pipe));
3741                 temp &= ~PIPE_BPC_MASK;
3742                 if (is_lvds) {
3743                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3744                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3745                                 temp |= PIPE_8BPC;
3746                         else
3747                                 temp |= PIPE_6BPC;
3748                 } else if (has_edp_encoder) {
3749                         switch (dev_priv->edp.bpp/3) {
3750                         case 8:
3751                                 temp |= PIPE_8BPC;
3752                                 break;
3753                         case 10:
3754                                 temp |= PIPE_10BPC;
3755                                 break;
3756                         case 6:
3757                                 temp |= PIPE_6BPC;
3758                                 break;
3759                         case 12:
3760                                 temp |= PIPE_12BPC;
3761                                 break;
3762                         }
3763                 } else
3764                         temp |= PIPE_8BPC;
3765                 I915_WRITE(PIPECONF(pipe), temp);
3766
3767                 switch (temp & PIPE_BPC_MASK) {
3768                 case PIPE_8BPC:
3769                         bpp = 24;
3770                         break;
3771                 case PIPE_10BPC:
3772                         bpp = 30;
3773                         break;
3774                 case PIPE_6BPC:
3775                         bpp = 18;
3776                         break;
3777                 case PIPE_12BPC:
3778                         bpp = 36;
3779                         break;
3780                 default:
3781                         DRM_ERROR("unknown pipe bpc value\n");
3782                         bpp = 24;
3783                 }
3784
3785                 if (!lane) {
3786                         /*
3787                          * Account for spread spectrum to avoid
3788                          * oversubscribing the link. Max center spread
3789                          * is 2.5%; use 5% for safety's sake.
3790                          */
3791                         u32 bps = target_clock * bpp * 21 / 20;
3792                         lane = bps / (link_bw * 8) + 1;
3793                 }
3794
3795                 intel_crtc->fdi_lanes = lane;
3796
3797                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3798         }
3799
3800         /* Ironlake: try to setup display ref clock before DPLL
3801          * enabling. This is only under driver's control after
3802          * PCH B stepping, previous chipset stepping should be
3803          * ignoring this setting.
3804          */
3805         if (HAS_PCH_SPLIT(dev)) {
3806                 temp = I915_READ(PCH_DREF_CONTROL);
3807                 /* Always enable nonspread source */
3808                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3809                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3810                 temp &= ~DREF_SSC_SOURCE_MASK;
3811                 temp |= DREF_SSC_SOURCE_ENABLE;
3812                 I915_WRITE(PCH_DREF_CONTROL, temp);
3813
3814                 POSTING_READ(PCH_DREF_CONTROL);
3815                 udelay(200);
3816
3817                 if (has_edp_encoder) {
3818                         if (dev_priv->lvds_use_ssc) {
3819                                 temp |= DREF_SSC1_ENABLE;
3820                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3821
3822                                 POSTING_READ(PCH_DREF_CONTROL);
3823                                 udelay(200);
3824                         }
3825                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3826
3827                         /* Enable CPU source on CPU attached eDP */
3828                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3829                                 if (dev_priv->lvds_use_ssc)
3830                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3831                                 else
3832                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3833                         } else {
3834                                 /* Enable SSC on PCH eDP if needed */
3835                                 if (dev_priv->lvds_use_ssc) {
3836                                         DRM_ERROR("enabling SSC on PCH\n");
3837                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3838                                 }
3839                         }
3840                         I915_WRITE(PCH_DREF_CONTROL, temp);
3841                         POSTING_READ(PCH_DREF_CONTROL);
3842                         udelay(200);
3843                 }
3844         }
3845
3846         if (IS_PINEVIEW(dev)) {
3847                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3848                 if (has_reduced_clock)
3849                         fp2 = (1 << reduced_clock.n) << 16 |
3850                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3851         } else {
3852                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3853                 if (has_reduced_clock)
3854                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3855                                 reduced_clock.m2;
3856         }
3857
3858         dpll = 0;
3859         if (!HAS_PCH_SPLIT(dev))
3860                 dpll = DPLL_VGA_MODE_DIS;
3861
3862         if (!IS_GEN2(dev)) {
3863                 if (is_lvds)
3864                         dpll |= DPLLB_MODE_LVDS;
3865                 else
3866                         dpll |= DPLLB_MODE_DAC_SERIAL;
3867                 if (is_sdvo) {
3868                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3869                         if (pixel_multiplier > 1) {
3870                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3871                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3872                                 else if (HAS_PCH_SPLIT(dev))
3873                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3874                         }
3875                         dpll |= DPLL_DVO_HIGH_SPEED;
3876                 }
3877                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3878                         dpll |= DPLL_DVO_HIGH_SPEED;
3879
3880                 /* compute bitmask from p1 value */
3881                 if (IS_PINEVIEW(dev))
3882                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3883                 else {
3884                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3885                         /* also FPA1 */
3886                         if (HAS_PCH_SPLIT(dev))
3887                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3888                         if (IS_G4X(dev) && has_reduced_clock)
3889                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3890                 }
3891                 switch (clock.p2) {
3892                 case 5:
3893                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3894                         break;
3895                 case 7:
3896                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3897                         break;
3898                 case 10:
3899                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3900                         break;
3901                 case 14:
3902                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3903                         break;
3904                 }
3905                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3906                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3907         } else {
3908                 if (is_lvds) {
3909                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3910                 } else {
3911                         if (clock.p1 == 2)
3912                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3913                         else
3914                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3915                         if (clock.p2 == 4)
3916                                 dpll |= PLL_P2_DIVIDE_BY_4;
3917                 }
3918         }
3919
3920         if (is_sdvo && is_tv)
3921                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3922         else if (is_tv)
3923                 /* XXX: just matching BIOS for now */
3924                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3925                 dpll |= 3;
3926         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3927                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3928         else
3929                 dpll |= PLL_REF_INPUT_DREFCLK;
3930
3931         /* setup pipeconf */
3932         pipeconf = I915_READ(PIPECONF(pipe));
3933
3934         /* Set up the display plane register */
3935         dspcntr = DISPPLANE_GAMMA_ENABLE;
3936
3937         /* Ironlake's plane is forced to pipe, bit 24 is to
3938            enable color space conversion */
3939         if (!HAS_PCH_SPLIT(dev)) {
3940                 if (pipe == 0)
3941                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3942                 else
3943                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3944         }
3945
3946         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3947                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3948                  * core speed.
3949                  *
3950                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3951                  * pipe == 0 check?
3952                  */
3953                 if (mode->clock >
3954                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3955                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3956                 else
3957                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3958         }
3959
3960         dspcntr |= DISPLAY_PLANE_ENABLE;
3961         pipeconf |= PIPECONF_ENABLE;
3962         dpll |= DPLL_VCO_ENABLE;
3963
3964         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3965         drm_mode_debug_printmodeline(mode);
3966
3967         /* assign to Ironlake registers */
3968         if (HAS_PCH_SPLIT(dev)) {
3969                 fp_reg = PCH_FP0(pipe);
3970                 dpll_reg = PCH_DPLL(pipe);
3971         } else {
3972                 fp_reg = FP0(pipe);
3973                 dpll_reg = DPLL(pipe);
3974         }
3975
3976         /* PCH eDP needs FDI, but CPU eDP does not */
3977         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3978                 I915_WRITE(fp_reg, fp);
3979                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3980
3981                 POSTING_READ(dpll_reg);
3982                 udelay(150);
3983         }
3984
3985         /* enable transcoder DPLL */
3986         if (HAS_PCH_CPT(dev)) {
3987                 temp = I915_READ(PCH_DPLL_SEL);
3988                 if (pipe == 0)
3989                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3990                 else
3991                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3992                 I915_WRITE(PCH_DPLL_SEL, temp);
3993
3994                 POSTING_READ(PCH_DPLL_SEL);
3995                 udelay(150);
3996         }
3997
3998         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3999          * This is an exception to the general rule that mode_set doesn't turn
4000          * things on.
4001          */
4002         if (is_lvds) {
4003                 reg = LVDS;
4004                 if (HAS_PCH_SPLIT(dev))
4005                         reg = PCH_LVDS;
4006
4007                 temp = I915_READ(reg);
4008                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4009                 if (pipe == 1) {
4010                         if (HAS_PCH_CPT(dev))
4011                                 temp |= PORT_TRANS_B_SEL_CPT;
4012                         else
4013                                 temp |= LVDS_PIPEB_SELECT;
4014                 } else {
4015                         if (HAS_PCH_CPT(dev))
4016                                 temp &= ~PORT_TRANS_SEL_MASK;
4017                         else
4018                                 temp &= ~LVDS_PIPEB_SELECT;
4019                 }
4020                 /* set the corresponsding LVDS_BORDER bit */
4021                 temp |= dev_priv->lvds_border_bits;
4022                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4023                  * set the DPLLs for dual-channel mode or not.
4024                  */
4025                 if (clock.p2 == 7)
4026                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4027                 else
4028                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4029
4030                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4031                  * appropriately here, but we need to look more thoroughly into how
4032                  * panels behave in the two modes.
4033                  */
4034                 /* set the dithering flag on non-PCH LVDS as needed */
4035                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4036                         if (dev_priv->lvds_dither)
4037                                 temp |= LVDS_ENABLE_DITHER;
4038                         else
4039                                 temp &= ~LVDS_ENABLE_DITHER;
4040                 }
4041                 I915_WRITE(reg, temp);
4042         }
4043
4044         /* set the dithering flag and clear for anything other than a panel. */
4045         if (HAS_PCH_SPLIT(dev)) {
4046                 pipeconf &= ~PIPECONF_DITHER_EN;
4047                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4048                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4049                         pipeconf |= PIPECONF_DITHER_EN;
4050                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4051                 }
4052         }
4053
4054         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4055                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4056         } else if (HAS_PCH_SPLIT(dev)) {
4057                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4058                 if (pipe == 0) {
4059                         I915_WRITE(TRANSA_DATA_M1, 0);
4060                         I915_WRITE(TRANSA_DATA_N1, 0);
4061                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4062                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4063                 } else {
4064                         I915_WRITE(TRANSB_DATA_M1, 0);
4065                         I915_WRITE(TRANSB_DATA_N1, 0);
4066                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4067                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4068                 }
4069         }
4070
4071         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4072                 I915_WRITE(fp_reg, fp);
4073                 I915_WRITE(dpll_reg, dpll);
4074
4075                 /* Wait for the clocks to stabilize. */
4076                 POSTING_READ(dpll_reg);
4077                 udelay(150);
4078
4079                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4080                         temp = 0;
4081                         if (is_sdvo) {
4082                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4083                                 if (temp > 1)
4084                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4085                                 else
4086                                         temp = 0;
4087                         }
4088                         I915_WRITE(DPLL_MD(pipe), temp);
4089                 } else {
4090                         /* write it again -- the BIOS does, after all */
4091                         I915_WRITE(dpll_reg, dpll);
4092                 }
4093
4094                 /* Wait for the clocks to stabilize. */
4095                 POSTING_READ(dpll_reg);
4096                 udelay(150);
4097         }
4098
4099         intel_crtc->lowfreq_avail = false;
4100         if (is_lvds && has_reduced_clock && i915_powersave) {
4101                 I915_WRITE(fp_reg + 4, fp2);
4102                 intel_crtc->lowfreq_avail = true;
4103                 if (HAS_PIPE_CXSR(dev)) {
4104                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4105                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4106                 }
4107         } else {
4108                 I915_WRITE(fp_reg + 4, fp);
4109                 if (HAS_PIPE_CXSR(dev)) {
4110                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4111                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4112                 }
4113         }
4114
4115         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4116                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4117                 /* the chip adds 2 halflines automatically */
4118                 adjusted_mode->crtc_vdisplay -= 1;
4119                 adjusted_mode->crtc_vtotal -= 1;
4120                 adjusted_mode->crtc_vblank_start -= 1;
4121                 adjusted_mode->crtc_vblank_end -= 1;
4122                 adjusted_mode->crtc_vsync_end -= 1;
4123                 adjusted_mode->crtc_vsync_start -= 1;
4124         } else
4125                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4126
4127         I915_WRITE(HTOTAL(pipe),
4128                    (adjusted_mode->crtc_hdisplay - 1) |
4129                    ((adjusted_mode->crtc_htotal - 1) << 16));
4130         I915_WRITE(HBLANK(pipe),
4131                    (adjusted_mode->crtc_hblank_start - 1) |
4132                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4133         I915_WRITE(HSYNC(pipe),
4134                    (adjusted_mode->crtc_hsync_start - 1) |
4135                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4136
4137         I915_WRITE(VTOTAL(pipe),
4138                    (adjusted_mode->crtc_vdisplay - 1) |
4139                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4140         I915_WRITE(VBLANK(pipe),
4141                    (adjusted_mode->crtc_vblank_start - 1) |
4142                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4143         I915_WRITE(VSYNC(pipe),
4144                    (adjusted_mode->crtc_vsync_start - 1) |
4145                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4146
4147         /* pipesrc and dspsize control the size that is scaled from,
4148          * which should always be the user's requested size.
4149          */
4150         if (!HAS_PCH_SPLIT(dev)) {
4151                 I915_WRITE(DSPSIZE(plane),
4152                            ((mode->vdisplay - 1) << 16) |
4153                            (mode->hdisplay - 1));
4154                 I915_WRITE(DSPPOS(plane), 0);
4155         }
4156         I915_WRITE(PIPESRC(pipe),
4157                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4158
4159         if (HAS_PCH_SPLIT(dev)) {
4160                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4161                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4162                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4163                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4164
4165                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4166                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4167                 }
4168         }
4169
4170         I915_WRITE(PIPECONF(pipe), pipeconf);
4171         POSTING_READ(PIPECONF(pipe));
4172
4173         intel_wait_for_vblank(dev, pipe);
4174
4175         if (IS_GEN5(dev)) {
4176                 /* enable address swizzle for tiling buffer */
4177                 temp = I915_READ(DISP_ARB_CTL);
4178                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4179         }
4180
4181         I915_WRITE(DSPCNTR(plane), dspcntr);
4182
4183         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4184
4185         intel_update_watermarks(dev);
4186
4187         drm_vblank_post_modeset(dev, pipe);
4188
4189         return ret;
4190 }
4191
4192 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4193 void intel_crtc_load_lut(struct drm_crtc *crtc)
4194 {
4195         struct drm_device *dev = crtc->dev;
4196         struct drm_i915_private *dev_priv = dev->dev_private;
4197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4198         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4199         int i;
4200
4201         /* The clocks have to be on to load the palette. */
4202         if (!crtc->enabled)
4203                 return;
4204
4205         /* use legacy palette for Ironlake */
4206         if (HAS_PCH_SPLIT(dev))
4207                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4208                                                    LGC_PALETTE_B;
4209
4210         for (i = 0; i < 256; i++) {
4211                 I915_WRITE(palreg + 4 * i,
4212                            (intel_crtc->lut_r[i] << 16) |
4213                            (intel_crtc->lut_g[i] << 8) |
4214                            intel_crtc->lut_b[i]);
4215         }
4216 }
4217
4218 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4219 {
4220         struct drm_device *dev = crtc->dev;
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223         bool visible = base != 0;
4224         u32 cntl;
4225
4226         if (intel_crtc->cursor_visible == visible)
4227                 return;
4228
4229         cntl = I915_READ(CURACNTR);
4230         if (visible) {
4231                 /* On these chipsets we can only modify the base whilst
4232                  * the cursor is disabled.
4233                  */
4234                 I915_WRITE(CURABASE, base);
4235
4236                 cntl &= ~(CURSOR_FORMAT_MASK);
4237                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4238                 cntl |= CURSOR_ENABLE |
4239                         CURSOR_GAMMA_ENABLE |
4240                         CURSOR_FORMAT_ARGB;
4241         } else
4242                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4243         I915_WRITE(CURACNTR, cntl);
4244
4245         intel_crtc->cursor_visible = visible;
4246 }
4247
4248 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4249 {
4250         struct drm_device *dev = crtc->dev;
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253         int pipe = intel_crtc->pipe;
4254         bool visible = base != 0;
4255
4256         if (intel_crtc->cursor_visible != visible) {
4257                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4258                 if (base) {
4259                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4260                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4261                         cntl |= pipe << 28; /* Connect to correct pipe */
4262                 } else {
4263                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4264                         cntl |= CURSOR_MODE_DISABLE;
4265                 }
4266                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4267
4268                 intel_crtc->cursor_visible = visible;
4269         }
4270         /* and commit changes on next vblank */
4271         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4272 }
4273
4274 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4275 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4276                                      bool on)
4277 {
4278         struct drm_device *dev = crtc->dev;
4279         struct drm_i915_private *dev_priv = dev->dev_private;
4280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4281         int pipe = intel_crtc->pipe;
4282         int x = intel_crtc->cursor_x;
4283         int y = intel_crtc->cursor_y;
4284         u32 base, pos;
4285         bool visible;
4286
4287         pos = 0;
4288
4289         if (on && crtc->enabled && crtc->fb) {
4290                 base = intel_crtc->cursor_addr;
4291                 if (x > (int) crtc->fb->width)
4292                         base = 0;
4293
4294                 if (y > (int) crtc->fb->height)
4295                         base = 0;
4296         } else
4297                 base = 0;
4298
4299         if (x < 0) {
4300                 if (x + intel_crtc->cursor_width < 0)
4301                         base = 0;
4302
4303                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4304                 x = -x;
4305         }
4306         pos |= x << CURSOR_X_SHIFT;
4307
4308         if (y < 0) {
4309                 if (y + intel_crtc->cursor_height < 0)
4310                         base = 0;
4311
4312                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4313                 y = -y;
4314         }
4315         pos |= y << CURSOR_Y_SHIFT;
4316
4317         visible = base != 0;
4318         if (!visible && !intel_crtc->cursor_visible)
4319                 return;
4320
4321         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4322         if (IS_845G(dev) || IS_I865G(dev))
4323                 i845_update_cursor(crtc, base);
4324         else
4325                 i9xx_update_cursor(crtc, base);
4326
4327         if (visible)
4328                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4329 }
4330
4331 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4332                                  struct drm_file *file,
4333                                  uint32_t handle,
4334                                  uint32_t width, uint32_t height)
4335 {
4336         struct drm_device *dev = crtc->dev;
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4339         struct drm_i915_gem_object *obj;
4340         uint32_t addr;
4341         int ret;
4342
4343         DRM_DEBUG_KMS("\n");
4344
4345         /* if we want to turn off the cursor ignore width and height */
4346         if (!handle) {
4347                 DRM_DEBUG_KMS("cursor off\n");
4348                 addr = 0;
4349                 obj = NULL;
4350                 mutex_lock(&dev->struct_mutex);
4351                 goto finish;
4352         }
4353
4354         /* Currently we only support 64x64 cursors */
4355         if (width != 64 || height != 64) {
4356                 DRM_ERROR("we currently only support 64x64 cursors\n");
4357                 return -EINVAL;
4358         }
4359
4360         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4361         if (!obj)
4362                 return -ENOENT;
4363
4364         if (obj->base.size < width * height * 4) {
4365                 DRM_ERROR("buffer is to small\n");
4366                 ret = -ENOMEM;
4367                 goto fail;
4368         }
4369
4370         /* we only need to pin inside GTT if cursor is non-phy */
4371         mutex_lock(&dev->struct_mutex);
4372         if (!dev_priv->info->cursor_needs_physical) {
4373                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4374                 if (ret) {
4375                         DRM_ERROR("failed to pin cursor bo\n");
4376                         goto fail_locked;
4377                 }
4378
4379                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4380                 if (ret) {
4381                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4382                         goto fail_unpin;
4383                 }
4384
4385                 addr = obj->gtt_offset;
4386         } else {
4387                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4388                 ret = i915_gem_attach_phys_object(dev, obj,
4389                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4390                                                   align);
4391                 if (ret) {
4392                         DRM_ERROR("failed to attach phys object\n");
4393                         goto fail_locked;
4394                 }
4395                 addr = obj->phys_obj->handle->busaddr;
4396         }
4397
4398         if (IS_GEN2(dev))
4399                 I915_WRITE(CURSIZE, (height << 12) | width);
4400
4401  finish:
4402         if (intel_crtc->cursor_bo) {
4403                 if (dev_priv->info->cursor_needs_physical) {
4404                         if (intel_crtc->cursor_bo != obj)
4405                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4406                 } else
4407                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4408                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4409         }
4410
4411         mutex_unlock(&dev->struct_mutex);
4412
4413         intel_crtc->cursor_addr = addr;
4414         intel_crtc->cursor_bo = obj;
4415         intel_crtc->cursor_width = width;
4416         intel_crtc->cursor_height = height;
4417
4418         intel_crtc_update_cursor(crtc, true);
4419
4420         return 0;
4421 fail_unpin:
4422         i915_gem_object_unpin(obj);
4423 fail_locked:
4424         mutex_unlock(&dev->struct_mutex);
4425 fail:
4426         drm_gem_object_unreference_unlocked(&obj->base);
4427         return ret;
4428 }
4429
4430 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4431 {
4432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4433
4434         intel_crtc->cursor_x = x;
4435         intel_crtc->cursor_y = y;
4436
4437         intel_crtc_update_cursor(crtc, true);
4438
4439         return 0;
4440 }
4441
4442 /** Sets the color ramps on behalf of RandR */
4443 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4444                                  u16 blue, int regno)
4445 {
4446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4447
4448         intel_crtc->lut_r[regno] = red >> 8;
4449         intel_crtc->lut_g[regno] = green >> 8;
4450         intel_crtc->lut_b[regno] = blue >> 8;
4451 }
4452
4453 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4454                              u16 *blue, int regno)
4455 {
4456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4457
4458         *red = intel_crtc->lut_r[regno] << 8;
4459         *green = intel_crtc->lut_g[regno] << 8;
4460         *blue = intel_crtc->lut_b[regno] << 8;
4461 }
4462
4463 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4464                                  u16 *blue, uint32_t start, uint32_t size)
4465 {
4466         int end = (start + size > 256) ? 256 : start + size, i;
4467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4468
4469         for (i = start; i < end; i++) {
4470                 intel_crtc->lut_r[i] = red[i] >> 8;
4471                 intel_crtc->lut_g[i] = green[i] >> 8;
4472                 intel_crtc->lut_b[i] = blue[i] >> 8;
4473         }
4474
4475         intel_crtc_load_lut(crtc);
4476 }
4477
4478 /**
4479  * Get a pipe with a simple mode set on it for doing load-based monitor
4480  * detection.
4481  *
4482  * It will be up to the load-detect code to adjust the pipe as appropriate for
4483  * its requirements.  The pipe will be connected to no other encoders.
4484  *
4485  * Currently this code will only succeed if there is a pipe with no encoders
4486  * configured for it.  In the future, it could choose to temporarily disable
4487  * some outputs to free up a pipe for its use.
4488  *
4489  * \return crtc, or NULL if no pipes are available.
4490  */
4491
4492 /* VESA 640x480x72Hz mode to set on the pipe */
4493 static struct drm_display_mode load_detect_mode = {
4494         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4495                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4496 };
4497
4498 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4499                                             struct drm_connector *connector,
4500                                             struct drm_display_mode *mode,
4501                                             int *dpms_mode)
4502 {
4503         struct intel_crtc *intel_crtc;
4504         struct drm_crtc *possible_crtc;
4505         struct drm_crtc *supported_crtc =NULL;
4506         struct drm_encoder *encoder = &intel_encoder->base;
4507         struct drm_crtc *crtc = NULL;
4508         struct drm_device *dev = encoder->dev;
4509         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4510         struct drm_crtc_helper_funcs *crtc_funcs;
4511         int i = -1;
4512
4513         /*
4514          * Algorithm gets a little messy:
4515          *   - if the connector already has an assigned crtc, use it (but make
4516          *     sure it's on first)
4517          *   - try to find the first unused crtc that can drive this connector,
4518          *     and use that if we find one
4519          *   - if there are no unused crtcs available, try to use the first
4520          *     one we found that supports the connector
4521          */
4522
4523         /* See if we already have a CRTC for this connector */
4524         if (encoder->crtc) {
4525                 crtc = encoder->crtc;
4526                 /* Make sure the crtc and connector are running */
4527                 intel_crtc = to_intel_crtc(crtc);
4528                 *dpms_mode = intel_crtc->dpms_mode;
4529                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4530                         crtc_funcs = crtc->helper_private;
4531                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4532                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4533                 }
4534                 return crtc;
4535         }
4536
4537         /* Find an unused one (if possible) */
4538         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4539                 i++;
4540                 if (!(encoder->possible_crtcs & (1 << i)))
4541                         continue;
4542                 if (!possible_crtc->enabled) {
4543                         crtc = possible_crtc;
4544                         break;
4545                 }
4546                 if (!supported_crtc)
4547                         supported_crtc = possible_crtc;
4548         }
4549
4550         /*
4551          * If we didn't find an unused CRTC, don't use any.
4552          */
4553         if (!crtc) {
4554                 return NULL;
4555         }
4556
4557         encoder->crtc = crtc;
4558         connector->encoder = encoder;
4559         intel_encoder->load_detect_temp = true;
4560
4561         intel_crtc = to_intel_crtc(crtc);
4562         *dpms_mode = intel_crtc->dpms_mode;
4563
4564         if (!crtc->enabled) {
4565                 if (!mode)
4566                         mode = &load_detect_mode;
4567                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4568         } else {
4569                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4570                         crtc_funcs = crtc->helper_private;
4571                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4572                 }
4573
4574                 /* Add this connector to the crtc */
4575                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4576                 encoder_funcs->commit(encoder);
4577         }
4578         /* let the connector get through one full cycle before testing */
4579         intel_wait_for_vblank(dev, intel_crtc->pipe);
4580
4581         return crtc;
4582 }
4583
4584 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4585                                     struct drm_connector *connector, int dpms_mode)
4586 {
4587         struct drm_encoder *encoder = &intel_encoder->base;
4588         struct drm_device *dev = encoder->dev;
4589         struct drm_crtc *crtc = encoder->crtc;
4590         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4591         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4592
4593         if (intel_encoder->load_detect_temp) {
4594                 encoder->crtc = NULL;
4595                 connector->encoder = NULL;
4596                 intel_encoder->load_detect_temp = false;
4597                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4598                 drm_helper_disable_unused_functions(dev);
4599         }
4600
4601         /* Switch crtc and encoder back off if necessary */
4602         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4603                 if (encoder->crtc == crtc)
4604                         encoder_funcs->dpms(encoder, dpms_mode);
4605                 crtc_funcs->dpms(crtc, dpms_mode);
4606         }
4607 }
4608
4609 /* Returns the clock of the currently programmed mode of the given pipe. */
4610 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4611 {
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4614         int pipe = intel_crtc->pipe;
4615         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4616         u32 fp;
4617         intel_clock_t clock;
4618
4619         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4620                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4621         else
4622                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4623
4624         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4625         if (IS_PINEVIEW(dev)) {
4626                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4627                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4628         } else {
4629                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4630                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4631         }
4632
4633         if (!IS_GEN2(dev)) {
4634                 if (IS_PINEVIEW(dev))
4635                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4636                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4637                 else
4638                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4639                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4640
4641                 switch (dpll & DPLL_MODE_MASK) {
4642                 case DPLLB_MODE_DAC_SERIAL:
4643                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4644                                 5 : 10;
4645                         break;
4646                 case DPLLB_MODE_LVDS:
4647                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4648                                 7 : 14;
4649                         break;
4650                 default:
4651                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4652                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4653                         return 0;
4654                 }
4655
4656                 /* XXX: Handle the 100Mhz refclk */
4657                 intel_clock(dev, 96000, &clock);
4658         } else {
4659                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4660
4661                 if (is_lvds) {
4662                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4663                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4664                         clock.p2 = 14;
4665
4666                         if ((dpll & PLL_REF_INPUT_MASK) ==
4667                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4668                                 /* XXX: might not be 66MHz */
4669                                 intel_clock(dev, 66000, &clock);
4670                         } else
4671                                 intel_clock(dev, 48000, &clock);
4672                 } else {
4673                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4674                                 clock.p1 = 2;
4675                         else {
4676                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4677                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4678                         }
4679                         if (dpll & PLL_P2_DIVIDE_BY_4)
4680                                 clock.p2 = 4;
4681                         else
4682                                 clock.p2 = 2;
4683
4684                         intel_clock(dev, 48000, &clock);
4685                 }
4686         }
4687
4688         /* XXX: It would be nice to validate the clocks, but we can't reuse
4689          * i830PllIsValid() because it relies on the xf86_config connector
4690          * configuration being accurate, which it isn't necessarily.
4691          */
4692
4693         return clock.dot;
4694 }
4695
4696 /** Returns the currently programmed mode of the given pipe. */
4697 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4698                                              struct drm_crtc *crtc)
4699 {
4700         struct drm_i915_private *dev_priv = dev->dev_private;
4701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702         int pipe = intel_crtc->pipe;
4703         struct drm_display_mode *mode;
4704         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4705         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4706         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4707         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4708
4709         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4710         if (!mode)
4711                 return NULL;
4712
4713         mode->clock = intel_crtc_clock_get(dev, crtc);
4714         mode->hdisplay = (htot & 0xffff) + 1;
4715         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4716         mode->hsync_start = (hsync & 0xffff) + 1;
4717         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4718         mode->vdisplay = (vtot & 0xffff) + 1;
4719         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4720         mode->vsync_start = (vsync & 0xffff) + 1;
4721         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4722
4723         drm_mode_set_name(mode);
4724         drm_mode_set_crtcinfo(mode, 0);
4725
4726         return mode;
4727 }
4728
4729 #define GPU_IDLE_TIMEOUT 500 /* ms */
4730
4731 /* When this timer fires, we've been idle for awhile */
4732 static void intel_gpu_idle_timer(unsigned long arg)
4733 {
4734         struct drm_device *dev = (struct drm_device *)arg;
4735         drm_i915_private_t *dev_priv = dev->dev_private;
4736
4737         dev_priv->busy = false;
4738
4739         queue_work(dev_priv->wq, &dev_priv->idle_work);
4740 }
4741
4742 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4743
4744 static void intel_crtc_idle_timer(unsigned long arg)
4745 {
4746         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4747         struct drm_crtc *crtc = &intel_crtc->base;
4748         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4749
4750         intel_crtc->busy = false;
4751
4752         queue_work(dev_priv->wq, &dev_priv->idle_work);
4753 }
4754
4755 static void intel_increase_pllclock(struct drm_crtc *crtc)
4756 {
4757         struct drm_device *dev = crtc->dev;
4758         drm_i915_private_t *dev_priv = dev->dev_private;
4759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4760         int pipe = intel_crtc->pipe;
4761         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4762         int dpll = I915_READ(dpll_reg);
4763
4764         if (HAS_PCH_SPLIT(dev))
4765                 return;
4766
4767         if (!dev_priv->lvds_downclock_avail)
4768                 return;
4769
4770         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4771                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4772
4773                 /* Unlock panel regs */
4774                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4775                            PANEL_UNLOCK_REGS);
4776
4777                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4778                 I915_WRITE(dpll_reg, dpll);
4779                 dpll = I915_READ(dpll_reg);
4780                 intel_wait_for_vblank(dev, pipe);
4781                 dpll = I915_READ(dpll_reg);
4782                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4783                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4784
4785                 /* ...and lock them again */
4786                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4787         }
4788
4789         /* Schedule downclock */
4790         mod_timer(&intel_crtc->idle_timer, jiffies +
4791                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4792 }
4793
4794 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4795 {
4796         struct drm_device *dev = crtc->dev;
4797         drm_i915_private_t *dev_priv = dev->dev_private;
4798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4799         int pipe = intel_crtc->pipe;
4800         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4801         int dpll = I915_READ(dpll_reg);
4802
4803         if (HAS_PCH_SPLIT(dev))
4804                 return;
4805
4806         if (!dev_priv->lvds_downclock_avail)
4807                 return;
4808
4809         /*
4810          * Since this is called by a timer, we should never get here in
4811          * the manual case.
4812          */
4813         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4814                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4815
4816                 /* Unlock panel regs */
4817                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4818                            PANEL_UNLOCK_REGS);
4819
4820                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4821                 I915_WRITE(dpll_reg, dpll);
4822                 dpll = I915_READ(dpll_reg);
4823                 intel_wait_for_vblank(dev, pipe);
4824                 dpll = I915_READ(dpll_reg);
4825                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4826                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4827
4828                 /* ...and lock them again */
4829                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4830         }
4831
4832 }
4833
4834 /**
4835  * intel_idle_update - adjust clocks for idleness
4836  * @work: work struct
4837  *
4838  * Either the GPU or display (or both) went idle.  Check the busy status
4839  * here and adjust the CRTC and GPU clocks as necessary.
4840  */
4841 static void intel_idle_update(struct work_struct *work)
4842 {
4843         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4844                                                     idle_work);
4845         struct drm_device *dev = dev_priv->dev;
4846         struct drm_crtc *crtc;
4847         struct intel_crtc *intel_crtc;
4848         int enabled = 0;
4849
4850         if (!i915_powersave)
4851                 return;
4852
4853         mutex_lock(&dev->struct_mutex);
4854
4855         i915_update_gfx_val(dev_priv);
4856
4857         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4858                 /* Skip inactive CRTCs */
4859                 if (!crtc->fb)
4860                         continue;
4861
4862                 enabled++;
4863                 intel_crtc = to_intel_crtc(crtc);
4864                 if (!intel_crtc->busy)
4865                         intel_decrease_pllclock(crtc);
4866         }
4867
4868         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4869                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4870                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4871         }
4872
4873         mutex_unlock(&dev->struct_mutex);
4874 }
4875
4876 /**
4877  * intel_mark_busy - mark the GPU and possibly the display busy
4878  * @dev: drm device
4879  * @obj: object we're operating on
4880  *
4881  * Callers can use this function to indicate that the GPU is busy processing
4882  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4883  * buffer), we'll also mark the display as busy, so we know to increase its
4884  * clock frequency.
4885  */
4886 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
4887 {
4888         drm_i915_private_t *dev_priv = dev->dev_private;
4889         struct drm_crtc *crtc = NULL;
4890         struct intel_framebuffer *intel_fb;
4891         struct intel_crtc *intel_crtc;
4892
4893         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4894                 return;
4895
4896         if (!dev_priv->busy) {
4897                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4898                         u32 fw_blc_self;
4899
4900                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4901                         fw_blc_self = I915_READ(FW_BLC_SELF);
4902                         fw_blc_self &= ~FW_BLC_SELF_EN;
4903                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4904                 }
4905                 dev_priv->busy = true;
4906         } else
4907                 mod_timer(&dev_priv->idle_timer, jiffies +
4908                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4909
4910         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4911                 if (!crtc->fb)
4912                         continue;
4913
4914                 intel_crtc = to_intel_crtc(crtc);
4915                 intel_fb = to_intel_framebuffer(crtc->fb);
4916                 if (intel_fb->obj == obj) {
4917                         if (!intel_crtc->busy) {
4918                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4919                                         u32 fw_blc_self;
4920
4921                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4922                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4923                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4924                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4925                                 }
4926                                 /* Non-busy -> busy, upclock */
4927                                 intel_increase_pllclock(crtc);
4928                                 intel_crtc->busy = true;
4929                         } else {
4930                                 /* Busy -> busy, put off timer */
4931                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4932                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4933                         }
4934                 }
4935         }
4936 }
4937
4938 static void intel_crtc_destroy(struct drm_crtc *crtc)
4939 {
4940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941         struct drm_device *dev = crtc->dev;
4942         struct intel_unpin_work *work;
4943         unsigned long flags;
4944
4945         spin_lock_irqsave(&dev->event_lock, flags);
4946         work = intel_crtc->unpin_work;
4947         intel_crtc->unpin_work = NULL;
4948         spin_unlock_irqrestore(&dev->event_lock, flags);
4949
4950         if (work) {
4951                 cancel_work_sync(&work->work);
4952                 kfree(work);
4953         }
4954
4955         drm_crtc_cleanup(crtc);
4956
4957         kfree(intel_crtc);
4958 }
4959
4960 static void intel_unpin_work_fn(struct work_struct *__work)
4961 {
4962         struct intel_unpin_work *work =
4963                 container_of(__work, struct intel_unpin_work, work);
4964
4965         mutex_lock(&work->dev->struct_mutex);
4966         i915_gem_object_unpin(work->old_fb_obj);
4967         drm_gem_object_unreference(&work->pending_flip_obj->base);
4968         drm_gem_object_unreference(&work->old_fb_obj->base);
4969         mutex_unlock(&work->dev->struct_mutex);
4970         kfree(work);
4971 }
4972
4973 static void do_intel_finish_page_flip(struct drm_device *dev,
4974                                       struct drm_crtc *crtc)
4975 {
4976         drm_i915_private_t *dev_priv = dev->dev_private;
4977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978         struct intel_unpin_work *work;
4979         struct drm_i915_gem_object *obj;
4980         struct drm_pending_vblank_event *e;
4981         struct timeval now;
4982         unsigned long flags;
4983
4984         /* Ignore early vblank irqs */
4985         if (intel_crtc == NULL)
4986                 return;
4987
4988         spin_lock_irqsave(&dev->event_lock, flags);
4989         work = intel_crtc->unpin_work;
4990         if (work == NULL || !work->pending) {
4991                 spin_unlock_irqrestore(&dev->event_lock, flags);
4992                 return;
4993         }
4994
4995         intel_crtc->unpin_work = NULL;
4996         drm_vblank_put(dev, intel_crtc->pipe);
4997
4998         if (work->event) {
4999                 e = work->event;
5000                 do_gettimeofday(&now);
5001                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5002                 e->event.tv_sec = now.tv_sec;
5003                 e->event.tv_usec = now.tv_usec;
5004                 list_add_tail(&e->base.link,
5005                               &e->base.file_priv->event_list);
5006                 wake_up_interruptible(&e->base.file_priv->event_wait);
5007         }
5008
5009         spin_unlock_irqrestore(&dev->event_lock, flags);
5010
5011         obj = work->old_fb_obj;
5012         atomic_clear_mask(1 << intel_crtc->plane,
5013                           &obj->pending_flip.counter);
5014         if (atomic_read(&obj->pending_flip) == 0)
5015                 wake_up(&dev_priv->pending_flip_queue);
5016         schedule_work(&work->work);
5017
5018         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5019 }
5020
5021 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5022 {
5023         drm_i915_private_t *dev_priv = dev->dev_private;
5024         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5025
5026         do_intel_finish_page_flip(dev, crtc);
5027 }
5028
5029 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5030 {
5031         drm_i915_private_t *dev_priv = dev->dev_private;
5032         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5033
5034         do_intel_finish_page_flip(dev, crtc);
5035 }
5036
5037 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5038 {
5039         drm_i915_private_t *dev_priv = dev->dev_private;
5040         struct intel_crtc *intel_crtc =
5041                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5042         unsigned long flags;
5043
5044         spin_lock_irqsave(&dev->event_lock, flags);
5045         if (intel_crtc->unpin_work) {
5046                 if ((++intel_crtc->unpin_work->pending) > 1)
5047                         DRM_ERROR("Prepared flip multiple times\n");
5048         } else {
5049                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5050         }
5051         spin_unlock_irqrestore(&dev->event_lock, flags);
5052 }
5053
5054 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5055                                 struct drm_framebuffer *fb,
5056                                 struct drm_pending_vblank_event *event)
5057 {
5058         struct drm_device *dev = crtc->dev;
5059         struct drm_i915_private *dev_priv = dev->dev_private;
5060         struct intel_framebuffer *intel_fb;
5061         struct drm_i915_gem_object *obj;
5062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5063         struct intel_unpin_work *work;
5064         unsigned long flags, offset;
5065         int pipe = intel_crtc->pipe;
5066         u32 pf, pipesrc;
5067         int ret;
5068
5069         work = kzalloc(sizeof *work, GFP_KERNEL);
5070         if (work == NULL)
5071                 return -ENOMEM;
5072
5073         work->event = event;
5074         work->dev = crtc->dev;
5075         intel_fb = to_intel_framebuffer(crtc->fb);
5076         work->old_fb_obj = intel_fb->obj;
5077         INIT_WORK(&work->work, intel_unpin_work_fn);
5078
5079         /* We borrow the event spin lock for protecting unpin_work */
5080         spin_lock_irqsave(&dev->event_lock, flags);
5081         if (intel_crtc->unpin_work) {
5082                 spin_unlock_irqrestore(&dev->event_lock, flags);
5083                 kfree(work);
5084
5085                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5086                 return -EBUSY;
5087         }
5088         intel_crtc->unpin_work = work;
5089         spin_unlock_irqrestore(&dev->event_lock, flags);
5090
5091         intel_fb = to_intel_framebuffer(fb);
5092         obj = intel_fb->obj;
5093
5094         mutex_lock(&dev->struct_mutex);
5095         ret = intel_pin_and_fence_fb_obj(dev, obj, &dev_priv->render_ring);
5096         if (ret)
5097                 goto cleanup_work;
5098
5099         /* Reference the objects for the scheduled work. */
5100         drm_gem_object_reference(&work->old_fb_obj->base);
5101         drm_gem_object_reference(&obj->base);
5102
5103         crtc->fb = fb;
5104
5105         ret = drm_vblank_get(dev, intel_crtc->pipe);
5106         if (ret)
5107                 goto cleanup_objs;
5108
5109         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5110                 u32 flip_mask;
5111
5112                 /* Can't queue multiple flips, so wait for the previous
5113                  * one to finish before executing the next.
5114                  */
5115                 ret = BEGIN_LP_RING(2);
5116                 if (ret)
5117                         goto cleanup_objs;
5118
5119                 if (intel_crtc->plane)
5120                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5121                 else
5122                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5123                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5124                 OUT_RING(MI_NOOP);
5125                 ADVANCE_LP_RING();
5126         }
5127
5128         work->pending_flip_obj = obj;
5129
5130         work->enable_stall_check = true;
5131
5132         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5133         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5134
5135         ret = BEGIN_LP_RING(4);
5136         if (ret)
5137                 goto cleanup_objs;
5138
5139         /* Block clients from rendering to the new back buffer until
5140          * the flip occurs and the object is no longer visible.
5141          */
5142         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5143
5144         switch (INTEL_INFO(dev)->gen) {
5145         case 2:
5146                 OUT_RING(MI_DISPLAY_FLIP |
5147                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5148                 OUT_RING(fb->pitch);
5149                 OUT_RING(obj->gtt_offset + offset);
5150                 OUT_RING(MI_NOOP);
5151                 break;
5152
5153         case 3:
5154                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5155                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5156                 OUT_RING(fb->pitch);
5157                 OUT_RING(obj->gtt_offset + offset);
5158                 OUT_RING(MI_NOOP);
5159                 break;
5160
5161         case 4:
5162         case 5:
5163                 /* i965+ uses the linear or tiled offsets from the
5164                  * Display Registers (which do not change across a page-flip)
5165                  * so we need only reprogram the base address.
5166                  */
5167                 OUT_RING(MI_DISPLAY_FLIP |
5168                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5169                 OUT_RING(fb->pitch);
5170                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5171
5172                 /* XXX Enabling the panel-fitter across page-flip is so far
5173                  * untested on non-native modes, so ignore it for now.
5174                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5175                  */
5176                 pf = 0;
5177                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5178                 OUT_RING(pf | pipesrc);
5179                 break;
5180
5181         case 6:
5182                 OUT_RING(MI_DISPLAY_FLIP |
5183                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5184                 OUT_RING(fb->pitch | obj->tiling_mode);
5185                 OUT_RING(obj->gtt_offset);
5186
5187                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5188                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5189                 OUT_RING(pf | pipesrc);
5190                 break;
5191         }
5192         ADVANCE_LP_RING();
5193
5194         mutex_unlock(&dev->struct_mutex);
5195
5196         trace_i915_flip_request(intel_crtc->plane, obj);
5197
5198         return 0;
5199
5200 cleanup_objs:
5201         drm_gem_object_unreference(&work->old_fb_obj->base);
5202         drm_gem_object_unreference(&obj->base);
5203 cleanup_work:
5204         mutex_unlock(&dev->struct_mutex);
5205
5206         spin_lock_irqsave(&dev->event_lock, flags);
5207         intel_crtc->unpin_work = NULL;
5208         spin_unlock_irqrestore(&dev->event_lock, flags);
5209
5210         kfree(work);
5211
5212         return ret;
5213 }
5214
5215 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5216         .dpms = intel_crtc_dpms,
5217         .mode_fixup = intel_crtc_mode_fixup,
5218         .mode_set = intel_crtc_mode_set,
5219         .mode_set_base = intel_pipe_set_base,
5220         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5221         .load_lut = intel_crtc_load_lut,
5222         .disable = intel_crtc_disable,
5223 };
5224
5225 static const struct drm_crtc_funcs intel_crtc_funcs = {
5226         .cursor_set = intel_crtc_cursor_set,
5227         .cursor_move = intel_crtc_cursor_move,
5228         .gamma_set = intel_crtc_gamma_set,
5229         .set_config = drm_crtc_helper_set_config,
5230         .destroy = intel_crtc_destroy,
5231         .page_flip = intel_crtc_page_flip,
5232 };
5233
5234
5235 static void intel_crtc_init(struct drm_device *dev, int pipe)
5236 {
5237         drm_i915_private_t *dev_priv = dev->dev_private;
5238         struct intel_crtc *intel_crtc;
5239         int i;
5240
5241         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5242         if (intel_crtc == NULL)
5243                 return;
5244
5245         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5246
5247         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5248         for (i = 0; i < 256; i++) {
5249                 intel_crtc->lut_r[i] = i;
5250                 intel_crtc->lut_g[i] = i;
5251                 intel_crtc->lut_b[i] = i;
5252         }
5253
5254         /* Swap pipes & planes for FBC on pre-965 */
5255         intel_crtc->pipe = pipe;
5256         intel_crtc->plane = pipe;
5257         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5258                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5259                 intel_crtc->plane = !pipe;
5260         }
5261
5262         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5263                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5264         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5265         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5266
5267         intel_crtc->cursor_addr = 0;
5268         intel_crtc->dpms_mode = -1;
5269         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5270
5271         if (HAS_PCH_SPLIT(dev)) {
5272                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5273                 intel_helper_funcs.commit = ironlake_crtc_commit;
5274         } else {
5275                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5276                 intel_helper_funcs.commit = i9xx_crtc_commit;
5277         }
5278
5279         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5280
5281         intel_crtc->busy = false;
5282
5283         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5284                     (unsigned long)intel_crtc);
5285 }
5286
5287 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5288                                 struct drm_file *file)
5289 {
5290         drm_i915_private_t *dev_priv = dev->dev_private;
5291         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5292         struct drm_mode_object *drmmode_obj;
5293         struct intel_crtc *crtc;
5294
5295         if (!dev_priv) {
5296                 DRM_ERROR("called with no initialization\n");
5297                 return -EINVAL;
5298         }
5299
5300         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5301                         DRM_MODE_OBJECT_CRTC);
5302
5303         if (!drmmode_obj) {
5304                 DRM_ERROR("no such CRTC id\n");
5305                 return -EINVAL;
5306         }
5307
5308         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5309         pipe_from_crtc_id->pipe = crtc->pipe;
5310
5311         return 0;
5312 }
5313
5314 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5315 {
5316         struct intel_encoder *encoder;
5317         int index_mask = 0;
5318         int entry = 0;
5319
5320         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5321                 if (type_mask & encoder->clone_mask)
5322                         index_mask |= (1 << entry);
5323                 entry++;
5324         }
5325
5326         return index_mask;
5327 }
5328
5329 static void intel_setup_outputs(struct drm_device *dev)
5330 {
5331         struct drm_i915_private *dev_priv = dev->dev_private;
5332         struct intel_encoder *encoder;
5333         bool dpd_is_edp = false;
5334
5335         if (IS_MOBILE(dev) && !IS_I830(dev))
5336                 intel_lvds_init(dev);
5337
5338         if (HAS_PCH_SPLIT(dev)) {
5339                 dpd_is_edp = intel_dpd_is_edp(dev);
5340
5341                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5342                         intel_dp_init(dev, DP_A);
5343
5344                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5345                         intel_dp_init(dev, PCH_DP_D);
5346         }
5347
5348         intel_crt_init(dev);
5349
5350         if (HAS_PCH_SPLIT(dev)) {
5351                 int found;
5352
5353                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5354                         /* PCH SDVOB multiplex with HDMIB */
5355                         found = intel_sdvo_init(dev, PCH_SDVOB);
5356                         if (!found)
5357                                 intel_hdmi_init(dev, HDMIB);
5358                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5359                                 intel_dp_init(dev, PCH_DP_B);
5360                 }
5361
5362                 if (I915_READ(HDMIC) & PORT_DETECTED)
5363                         intel_hdmi_init(dev, HDMIC);
5364
5365                 if (I915_READ(HDMID) & PORT_DETECTED)
5366                         intel_hdmi_init(dev, HDMID);
5367
5368                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5369                         intel_dp_init(dev, PCH_DP_C);
5370
5371                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5372                         intel_dp_init(dev, PCH_DP_D);
5373
5374         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5375                 bool found = false;
5376
5377                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5378                         DRM_DEBUG_KMS("probing SDVOB\n");
5379                         found = intel_sdvo_init(dev, SDVOB);
5380                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5381                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5382                                 intel_hdmi_init(dev, SDVOB);
5383                         }
5384
5385                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5386                                 DRM_DEBUG_KMS("probing DP_B\n");
5387                                 intel_dp_init(dev, DP_B);
5388                         }
5389                 }
5390
5391                 /* Before G4X SDVOC doesn't have its own detect register */
5392
5393                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5394                         DRM_DEBUG_KMS("probing SDVOC\n");
5395                         found = intel_sdvo_init(dev, SDVOC);
5396                 }
5397
5398                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5399
5400                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5401                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5402                                 intel_hdmi_init(dev, SDVOC);
5403                         }
5404                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5405                                 DRM_DEBUG_KMS("probing DP_C\n");
5406                                 intel_dp_init(dev, DP_C);
5407                         }
5408                 }
5409
5410                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5411                     (I915_READ(DP_D) & DP_DETECTED)) {
5412                         DRM_DEBUG_KMS("probing DP_D\n");
5413                         intel_dp_init(dev, DP_D);
5414                 }
5415         } else if (IS_GEN2(dev))
5416                 intel_dvo_init(dev);
5417
5418         if (SUPPORTS_TV(dev))
5419                 intel_tv_init(dev);
5420
5421         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5422                 encoder->base.possible_crtcs = encoder->crtc_mask;
5423                 encoder->base.possible_clones =
5424                         intel_encoder_clones(dev, encoder->clone_mask);
5425         }
5426 }
5427
5428 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5429 {
5430         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5431
5432         drm_framebuffer_cleanup(fb);
5433         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5434
5435         kfree(intel_fb);
5436 }
5437
5438 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5439                                                 struct drm_file *file,
5440                                                 unsigned int *handle)
5441 {
5442         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5443         struct drm_i915_gem_object *obj = intel_fb->obj;
5444
5445         return drm_gem_handle_create(file, &obj->base, handle);
5446 }
5447
5448 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5449         .destroy = intel_user_framebuffer_destroy,
5450         .create_handle = intel_user_framebuffer_create_handle,
5451 };
5452
5453 int intel_framebuffer_init(struct drm_device *dev,
5454                            struct intel_framebuffer *intel_fb,
5455                            struct drm_mode_fb_cmd *mode_cmd,
5456                            struct drm_i915_gem_object *obj)
5457 {
5458         int ret;
5459
5460         if (obj->tiling_mode == I915_TILING_Y)
5461                 return -EINVAL;
5462
5463         if (mode_cmd->pitch & 63)
5464                 return -EINVAL;
5465
5466         switch (mode_cmd->bpp) {
5467         case 8:
5468         case 16:
5469         case 24:
5470         case 32:
5471                 break;
5472         default:
5473                 return -EINVAL;
5474         }
5475
5476         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5477         if (ret) {
5478                 DRM_ERROR("framebuffer init failed %d\n", ret);
5479                 return ret;
5480         }
5481
5482         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5483         intel_fb->obj = obj;
5484         return 0;
5485 }
5486
5487 static struct drm_framebuffer *
5488 intel_user_framebuffer_create(struct drm_device *dev,
5489                               struct drm_file *filp,
5490                               struct drm_mode_fb_cmd *mode_cmd)
5491 {
5492         struct drm_i915_gem_object *obj;
5493         struct intel_framebuffer *intel_fb;
5494         int ret;
5495
5496         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
5497         if (!obj)
5498                 return ERR_PTR(-ENOENT);
5499
5500         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5501         if (!intel_fb)
5502                 return ERR_PTR(-ENOMEM);
5503
5504         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5505         if (ret) {
5506                 drm_gem_object_unreference_unlocked(&obj->base);
5507                 kfree(intel_fb);
5508                 return ERR_PTR(ret);
5509         }
5510
5511         return &intel_fb->base;
5512 }
5513
5514 static const struct drm_mode_config_funcs intel_mode_funcs = {
5515         .fb_create = intel_user_framebuffer_create,
5516         .output_poll_changed = intel_fb_output_poll_changed,
5517 };
5518
5519 static struct drm_i915_gem_object *
5520 intel_alloc_context_page(struct drm_device *dev)
5521 {
5522         struct drm_i915_gem_object *ctx;
5523         int ret;
5524
5525         ctx = i915_gem_alloc_object(dev, 4096);
5526         if (!ctx) {
5527                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5528                 return NULL;
5529         }
5530
5531         mutex_lock(&dev->struct_mutex);
5532         ret = i915_gem_object_pin(ctx, 4096, true);
5533         if (ret) {
5534                 DRM_ERROR("failed to pin power context: %d\n", ret);
5535                 goto err_unref;
5536         }
5537
5538         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5539         if (ret) {
5540                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5541                 goto err_unpin;
5542         }
5543         mutex_unlock(&dev->struct_mutex);
5544
5545         return ctx;
5546
5547 err_unpin:
5548         i915_gem_object_unpin(ctx);
5549 err_unref:
5550         drm_gem_object_unreference(&ctx->base);
5551         mutex_unlock(&dev->struct_mutex);
5552         return NULL;
5553 }
5554
5555 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5556 {
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         u16 rgvswctl;
5559
5560         rgvswctl = I915_READ16(MEMSWCTL);
5561         if (rgvswctl & MEMCTL_CMD_STS) {
5562                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5563                 return false; /* still busy with another command */
5564         }
5565
5566         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5567                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5568         I915_WRITE16(MEMSWCTL, rgvswctl);
5569         POSTING_READ16(MEMSWCTL);
5570
5571         rgvswctl |= MEMCTL_CMD_STS;
5572         I915_WRITE16(MEMSWCTL, rgvswctl);
5573
5574         return true;
5575 }
5576
5577 void ironlake_enable_drps(struct drm_device *dev)
5578 {
5579         struct drm_i915_private *dev_priv = dev->dev_private;
5580         u32 rgvmodectl = I915_READ(MEMMODECTL);
5581         u8 fmax, fmin, fstart, vstart;
5582
5583         /* Enable temp reporting */
5584         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5585         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5586
5587         /* 100ms RC evaluation intervals */
5588         I915_WRITE(RCUPEI, 100000);
5589         I915_WRITE(RCDNEI, 100000);
5590
5591         /* Set max/min thresholds to 90ms and 80ms respectively */
5592         I915_WRITE(RCBMAXAVG, 90000);
5593         I915_WRITE(RCBMINAVG, 80000);
5594
5595         I915_WRITE(MEMIHYST, 1);
5596
5597         /* Set up min, max, and cur for interrupt handling */
5598         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5599         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5600         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5601                 MEMMODE_FSTART_SHIFT;
5602
5603         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5604                 PXVFREQ_PX_SHIFT;
5605
5606         dev_priv->fmax = fmax; /* IPS callback will increase this */
5607         dev_priv->fstart = fstart;
5608
5609         dev_priv->max_delay = fstart;
5610         dev_priv->min_delay = fmin;
5611         dev_priv->cur_delay = fstart;
5612
5613         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5614                          fmax, fmin, fstart);
5615
5616         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5617
5618         /*
5619          * Interrupts will be enabled in ironlake_irq_postinstall
5620          */
5621
5622         I915_WRITE(VIDSTART, vstart);
5623         POSTING_READ(VIDSTART);
5624
5625         rgvmodectl |= MEMMODE_SWMODE_EN;
5626         I915_WRITE(MEMMODECTL, rgvmodectl);
5627
5628         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5629                 DRM_ERROR("stuck trying to change perf mode\n");
5630         msleep(1);
5631
5632         ironlake_set_drps(dev, fstart);
5633
5634         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5635                 I915_READ(0x112e0);
5636         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5637         dev_priv->last_count2 = I915_READ(0x112f4);
5638         getrawmonotonic(&dev_priv->last_time2);
5639 }
5640
5641 void ironlake_disable_drps(struct drm_device *dev)
5642 {
5643         struct drm_i915_private *dev_priv = dev->dev_private;
5644         u16 rgvswctl = I915_READ16(MEMSWCTL);
5645
5646         /* Ack interrupts, disable EFC interrupt */
5647         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5648         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5649         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5650         I915_WRITE(DEIIR, DE_PCU_EVENT);
5651         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5652
5653         /* Go back to the starting frequency */
5654         ironlake_set_drps(dev, dev_priv->fstart);
5655         msleep(1);
5656         rgvswctl |= MEMCTL_CMD_STS;
5657         I915_WRITE(MEMSWCTL, rgvswctl);
5658         msleep(1);
5659
5660 }
5661
5662 static unsigned long intel_pxfreq(u32 vidfreq)
5663 {
5664         unsigned long freq;
5665         int div = (vidfreq & 0x3f0000) >> 16;
5666         int post = (vidfreq & 0x3000) >> 12;
5667         int pre = (vidfreq & 0x7);
5668
5669         if (!pre)
5670                 return 0;
5671
5672         freq = ((div * 133333) / ((1<<post) * pre));
5673
5674         return freq;
5675 }
5676
5677 void intel_init_emon(struct drm_device *dev)
5678 {
5679         struct drm_i915_private *dev_priv = dev->dev_private;
5680         u32 lcfuse;
5681         u8 pxw[16];
5682         int i;
5683
5684         /* Disable to program */
5685         I915_WRITE(ECR, 0);
5686         POSTING_READ(ECR);
5687
5688         /* Program energy weights for various events */
5689         I915_WRITE(SDEW, 0x15040d00);
5690         I915_WRITE(CSIEW0, 0x007f0000);
5691         I915_WRITE(CSIEW1, 0x1e220004);
5692         I915_WRITE(CSIEW2, 0x04000004);
5693
5694         for (i = 0; i < 5; i++)
5695                 I915_WRITE(PEW + (i * 4), 0);
5696         for (i = 0; i < 3; i++)
5697                 I915_WRITE(DEW + (i * 4), 0);
5698
5699         /* Program P-state weights to account for frequency power adjustment */
5700         for (i = 0; i < 16; i++) {
5701                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5702                 unsigned long freq = intel_pxfreq(pxvidfreq);
5703                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5704                         PXVFREQ_PX_SHIFT;
5705                 unsigned long val;
5706
5707                 val = vid * vid;
5708                 val *= (freq / 1000);
5709                 val *= 255;
5710                 val /= (127*127*900);
5711                 if (val > 0xff)
5712                         DRM_ERROR("bad pxval: %ld\n", val);
5713                 pxw[i] = val;
5714         }
5715         /* Render standby states get 0 weight */
5716         pxw[14] = 0;
5717         pxw[15] = 0;
5718
5719         for (i = 0; i < 4; i++) {
5720                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5721                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5722                 I915_WRITE(PXW + (i * 4), val);
5723         }
5724
5725         /* Adjust magic regs to magic values (more experimental results) */
5726         I915_WRITE(OGW0, 0);
5727         I915_WRITE(OGW1, 0);
5728         I915_WRITE(EG0, 0x00007f00);
5729         I915_WRITE(EG1, 0x0000000e);
5730         I915_WRITE(EG2, 0x000e0000);
5731         I915_WRITE(EG3, 0x68000300);
5732         I915_WRITE(EG4, 0x42000000);
5733         I915_WRITE(EG5, 0x00140031);
5734         I915_WRITE(EG6, 0);
5735         I915_WRITE(EG7, 0);
5736
5737         for (i = 0; i < 8; i++)
5738                 I915_WRITE(PXWL + (i * 4), 0);
5739
5740         /* Enable PMON + select events */
5741         I915_WRITE(ECR, 0x80000019);
5742
5743         lcfuse = I915_READ(LCFUSE02);
5744
5745         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5746 }
5747
5748 void intel_init_clock_gating(struct drm_device *dev)
5749 {
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751
5752         /*
5753          * Disable clock gating reported to work incorrectly according to the
5754          * specs, but enable as much else as we can.
5755          */
5756         if (HAS_PCH_SPLIT(dev)) {
5757                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5758
5759                 if (IS_GEN5(dev)) {
5760                         /* Required for FBC */
5761                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5762                         /* Required for CxSR */
5763                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5764
5765                         I915_WRITE(PCH_3DCGDIS0,
5766                                    MARIUNIT_CLOCK_GATE_DISABLE |
5767                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5768                 }
5769
5770                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5771
5772                 /*
5773                  * On Ibex Peak and Cougar Point, we need to disable clock
5774                  * gating for the panel power sequencer or it will fail to
5775                  * start up when no ports are active.
5776                  */
5777                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5778
5779                 /*
5780                  * According to the spec the following bits should be set in
5781                  * order to enable memory self-refresh
5782                  * The bit 22/21 of 0x42004
5783                  * The bit 5 of 0x42020
5784                  * The bit 15 of 0x45000
5785                  */
5786                 if (IS_GEN5(dev)) {
5787                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5788                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5789                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5790                         I915_WRITE(ILK_DSPCLK_GATE,
5791                                         (I915_READ(ILK_DSPCLK_GATE) |
5792                                                 ILK_DPARB_CLK_GATE));
5793                         I915_WRITE(DISP_ARB_CTL,
5794                                         (I915_READ(DISP_ARB_CTL) |
5795                                                 DISP_FBC_WM_DIS));
5796                 I915_WRITE(WM3_LP_ILK, 0);
5797                 I915_WRITE(WM2_LP_ILK, 0);
5798                 I915_WRITE(WM1_LP_ILK, 0);
5799                 }
5800                 /*
5801                  * Based on the document from hardware guys the following bits
5802                  * should be set unconditionally in order to enable FBC.
5803                  * The bit 22 of 0x42000
5804                  * The bit 22 of 0x42004
5805                  * The bit 7,8,9 of 0x42020.
5806                  */
5807                 if (IS_IRONLAKE_M(dev)) {
5808                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5809                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5810                                    ILK_FBCQ_DIS);
5811                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5812                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5813                                    ILK_DPARB_GATE);
5814                         I915_WRITE(ILK_DSPCLK_GATE,
5815                                    I915_READ(ILK_DSPCLK_GATE) |
5816                                    ILK_DPFC_DIS1 |
5817                                    ILK_DPFC_DIS2 |
5818                                    ILK_CLK_FBC);
5819                 }
5820
5821                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5822                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5823                            ILK_ELPIN_409_SELECT);
5824
5825                 if (IS_GEN5(dev)) {
5826                         I915_WRITE(_3D_CHICKEN2,
5827                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5828                                    _3D_CHICKEN2_WM_READ_PIPELINED);
5829                 }
5830                 return;
5831         } else if (IS_G4X(dev)) {
5832                 uint32_t dspclk_gate;
5833                 I915_WRITE(RENCLK_GATE_D1, 0);
5834                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5835                        GS_UNIT_CLOCK_GATE_DISABLE |
5836                        CL_UNIT_CLOCK_GATE_DISABLE);
5837                 I915_WRITE(RAMCLK_GATE_D, 0);
5838                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5839                         OVRUNIT_CLOCK_GATE_DISABLE |
5840                         OVCUNIT_CLOCK_GATE_DISABLE;
5841                 if (IS_GM45(dev))
5842                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5843                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5844         } else if (IS_CRESTLINE(dev)) {
5845                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5846                 I915_WRITE(RENCLK_GATE_D2, 0);
5847                 I915_WRITE(DSPCLK_GATE_D, 0);
5848                 I915_WRITE(RAMCLK_GATE_D, 0);
5849                 I915_WRITE16(DEUC, 0);
5850         } else if (IS_BROADWATER(dev)) {
5851                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5852                        I965_RCC_CLOCK_GATE_DISABLE |
5853                        I965_RCPB_CLOCK_GATE_DISABLE |
5854                        I965_ISC_CLOCK_GATE_DISABLE |
5855                        I965_FBC_CLOCK_GATE_DISABLE);
5856                 I915_WRITE(RENCLK_GATE_D2, 0);
5857         } else if (IS_GEN3(dev)) {
5858                 u32 dstate = I915_READ(D_STATE);
5859
5860                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5861                         DSTATE_DOT_CLOCK_GATING;
5862                 I915_WRITE(D_STATE, dstate);
5863         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5864                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5865         } else if (IS_I830(dev)) {
5866                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5867         }
5868
5869         /*
5870          * GPU can automatically power down the render unit if given a page
5871          * to save state.
5872          */
5873         if (IS_IRONLAKE_M(dev)) {
5874                 if (dev_priv->renderctx == NULL)
5875                         dev_priv->renderctx = intel_alloc_context_page(dev);
5876                 if (dev_priv->renderctx) {
5877                         struct drm_i915_gem_object *obj = dev_priv->renderctx;
5878                         if (BEGIN_LP_RING(4) == 0) {
5879                                 OUT_RING(MI_SET_CONTEXT);
5880                                 OUT_RING(obj->gtt_offset |
5881                                          MI_MM_SPACE_GTT |
5882                                          MI_SAVE_EXT_STATE_EN |
5883                                          MI_RESTORE_EXT_STATE_EN |
5884                                          MI_RESTORE_INHIBIT);
5885                                 OUT_RING(MI_NOOP);
5886                                 OUT_RING(MI_FLUSH);
5887                                 ADVANCE_LP_RING();
5888                         }
5889                 } else
5890                         DRM_DEBUG_KMS("Failed to allocate render context."
5891                                        "Disable RC6\n");
5892         }
5893
5894         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5895                 if (dev_priv->pwrctx == NULL)
5896                         dev_priv->pwrctx = intel_alloc_context_page(dev);
5897                 if (dev_priv->pwrctx) {
5898                         struct drm_i915_gem_object *obj = dev_priv->pwrctx;
5899                         I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
5900                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5901                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5902                 }
5903         }
5904 }
5905
5906 /* Set up chip specific display functions */
5907 static void intel_init_display(struct drm_device *dev)
5908 {
5909         struct drm_i915_private *dev_priv = dev->dev_private;
5910
5911         /* We always want a DPMS function */
5912         if (HAS_PCH_SPLIT(dev))
5913                 dev_priv->display.dpms = ironlake_crtc_dpms;
5914         else
5915                 dev_priv->display.dpms = i9xx_crtc_dpms;
5916
5917         if (I915_HAS_FBC(dev)) {
5918                 if (IS_IRONLAKE_M(dev)) {
5919                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5920                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5921                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5922                 } else if (IS_GM45(dev)) {
5923                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5924                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5925                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5926                 } else if (IS_CRESTLINE(dev)) {
5927                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5928                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5929                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5930                 }
5931                 /* 855GM needs testing */
5932         }
5933
5934         /* Returns the core display clock speed */
5935         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5936                 dev_priv->display.get_display_clock_speed =
5937                         i945_get_display_clock_speed;
5938         else if (IS_I915G(dev))
5939                 dev_priv->display.get_display_clock_speed =
5940                         i915_get_display_clock_speed;
5941         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5942                 dev_priv->display.get_display_clock_speed =
5943                         i9xx_misc_get_display_clock_speed;
5944         else if (IS_I915GM(dev))
5945                 dev_priv->display.get_display_clock_speed =
5946                         i915gm_get_display_clock_speed;
5947         else if (IS_I865G(dev))
5948                 dev_priv->display.get_display_clock_speed =
5949                         i865_get_display_clock_speed;
5950         else if (IS_I85X(dev))
5951                 dev_priv->display.get_display_clock_speed =
5952                         i855_get_display_clock_speed;
5953         else /* 852, 830 */
5954                 dev_priv->display.get_display_clock_speed =
5955                         i830_get_display_clock_speed;
5956
5957         /* For FIFO watermark updates */
5958         if (HAS_PCH_SPLIT(dev)) {
5959                 if (IS_GEN5(dev)) {
5960                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5961                                 dev_priv->display.update_wm = ironlake_update_wm;
5962                         else {
5963                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5964                                               "Disable CxSR\n");
5965                                 dev_priv->display.update_wm = NULL;
5966                         }
5967                 } else
5968                         dev_priv->display.update_wm = NULL;
5969         } else if (IS_PINEVIEW(dev)) {
5970                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5971                                             dev_priv->is_ddr3,
5972                                             dev_priv->fsb_freq,
5973                                             dev_priv->mem_freq)) {
5974                         DRM_INFO("failed to find known CxSR latency "
5975                                  "(found ddr%s fsb freq %d, mem freq %d), "
5976                                  "disabling CxSR\n",
5977                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5978                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5979                         /* Disable CxSR and never update its watermark again */
5980                         pineview_disable_cxsr(dev);
5981                         dev_priv->display.update_wm = NULL;
5982                 } else
5983                         dev_priv->display.update_wm = pineview_update_wm;
5984         } else if (IS_G4X(dev))
5985                 dev_priv->display.update_wm = g4x_update_wm;
5986         else if (IS_GEN4(dev))
5987                 dev_priv->display.update_wm = i965_update_wm;
5988         else if (IS_GEN3(dev)) {
5989                 dev_priv->display.update_wm = i9xx_update_wm;
5990                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5991         } else if (IS_I85X(dev)) {
5992                 dev_priv->display.update_wm = i9xx_update_wm;
5993                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5994         } else {
5995                 dev_priv->display.update_wm = i830_update_wm;
5996                 if (IS_845G(dev))
5997                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5998                 else
5999                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6000         }
6001 }
6002
6003 /*
6004  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6005  * resume, or other times.  This quirk makes sure that's the case for
6006  * affected systems.
6007  */
6008 static void quirk_pipea_force (struct drm_device *dev)
6009 {
6010         struct drm_i915_private *dev_priv = dev->dev_private;
6011
6012         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6013         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6014 }
6015
6016 struct intel_quirk {
6017         int device;
6018         int subsystem_vendor;
6019         int subsystem_device;
6020         void (*hook)(struct drm_device *dev);
6021 };
6022
6023 struct intel_quirk intel_quirks[] = {
6024         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6025         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6026         /* HP Mini needs pipe A force quirk (LP: #322104) */
6027         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6028
6029         /* Thinkpad R31 needs pipe A force quirk */
6030         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6031         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6032         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6033
6034         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6035         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6036         /* ThinkPad X40 needs pipe A force quirk */
6037
6038         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6039         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6040
6041         /* 855 & before need to leave pipe A & dpll A up */
6042         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6043         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6044 };
6045
6046 static void intel_init_quirks(struct drm_device *dev)
6047 {
6048         struct pci_dev *d = dev->pdev;
6049         int i;
6050
6051         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6052                 struct intel_quirk *q = &intel_quirks[i];
6053
6054                 if (d->device == q->device &&
6055                     (d->subsystem_vendor == q->subsystem_vendor ||
6056                      q->subsystem_vendor == PCI_ANY_ID) &&
6057                     (d->subsystem_device == q->subsystem_device ||
6058                      q->subsystem_device == PCI_ANY_ID))
6059                         q->hook(dev);
6060         }
6061 }
6062
6063 /* Disable the VGA plane that we never use */
6064 static void i915_disable_vga(struct drm_device *dev)
6065 {
6066         struct drm_i915_private *dev_priv = dev->dev_private;
6067         u8 sr1;
6068         u32 vga_reg;
6069
6070         if (HAS_PCH_SPLIT(dev))
6071                 vga_reg = CPU_VGACNTRL;
6072         else
6073                 vga_reg = VGACNTRL;
6074
6075         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6076         outb(1, VGA_SR_INDEX);
6077         sr1 = inb(VGA_SR_DATA);
6078         outb(sr1 | 1<<5, VGA_SR_DATA);
6079         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6080         udelay(300);
6081
6082         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6083         POSTING_READ(vga_reg);
6084 }
6085
6086 void intel_modeset_init(struct drm_device *dev)
6087 {
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089         int i;
6090
6091         drm_mode_config_init(dev);
6092
6093         dev->mode_config.min_width = 0;
6094         dev->mode_config.min_height = 0;
6095
6096         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6097
6098         intel_init_quirks(dev);
6099
6100         intel_init_display(dev);
6101
6102         if (IS_GEN2(dev)) {
6103                 dev->mode_config.max_width = 2048;
6104                 dev->mode_config.max_height = 2048;
6105         } else if (IS_GEN3(dev)) {
6106                 dev->mode_config.max_width = 4096;
6107                 dev->mode_config.max_height = 4096;
6108         } else {
6109                 dev->mode_config.max_width = 8192;
6110                 dev->mode_config.max_height = 8192;
6111         }
6112
6113         /* set memory base */
6114         if (IS_GEN2(dev))
6115                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6116         else
6117                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6118
6119         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6120                 dev_priv->num_pipe = 2;
6121         else
6122                 dev_priv->num_pipe = 1;
6123         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6124                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6125
6126         for (i = 0; i < dev_priv->num_pipe; i++) {
6127                 intel_crtc_init(dev, i);
6128         }
6129
6130         intel_setup_outputs(dev);
6131
6132         intel_init_clock_gating(dev);
6133
6134         /* Just disable it once at startup */
6135         i915_disable_vga(dev);
6136
6137         if (IS_IRONLAKE_M(dev)) {
6138                 ironlake_enable_drps(dev);
6139                 intel_init_emon(dev);
6140         }
6141
6142         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6143         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6144                     (unsigned long)dev);
6145
6146         intel_setup_overlay(dev);
6147 }
6148
6149 void intel_modeset_cleanup(struct drm_device *dev)
6150 {
6151         struct drm_i915_private *dev_priv = dev->dev_private;
6152         struct drm_crtc *crtc;
6153         struct intel_crtc *intel_crtc;
6154
6155         drm_kms_helper_poll_fini(dev);
6156         mutex_lock(&dev->struct_mutex);
6157
6158         intel_unregister_dsm_handler();
6159
6160
6161         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6162                 /* Skip inactive CRTCs */
6163                 if (!crtc->fb)
6164                         continue;
6165
6166                 intel_crtc = to_intel_crtc(crtc);
6167                 intel_increase_pllclock(crtc);
6168         }
6169
6170         if (dev_priv->display.disable_fbc)
6171                 dev_priv->display.disable_fbc(dev);
6172
6173         if (dev_priv->renderctx) {
6174                 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6175
6176                 I915_WRITE(CCID, obj->gtt_offset &~ CCID_EN);
6177                 POSTING_READ(CCID);
6178
6179                 i915_gem_object_unpin(obj);
6180                 drm_gem_object_unreference(&obj->base);
6181                 dev_priv->renderctx = NULL;
6182         }
6183
6184         if (dev_priv->pwrctx) {
6185                 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6186
6187                 I915_WRITE(PWRCTXA, obj->gtt_offset &~ PWRCTX_EN);
6188                 POSTING_READ(PWRCTXA);
6189
6190                 i915_gem_object_unpin(obj);
6191                 drm_gem_object_unreference(&obj->base);
6192                 dev_priv->pwrctx = NULL;
6193         }
6194
6195         if (IS_IRONLAKE_M(dev))
6196                 ironlake_disable_drps(dev);
6197
6198         mutex_unlock(&dev->struct_mutex);
6199
6200         /* Disable the irq before mode object teardown, for the irq might
6201          * enqueue unpin/hotplug work. */
6202         drm_irq_uninstall(dev);
6203         cancel_work_sync(&dev_priv->hotplug_work);
6204
6205         /* Shut off idle work before the crtcs get freed. */
6206         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6207                 intel_crtc = to_intel_crtc(crtc);
6208                 del_timer_sync(&intel_crtc->idle_timer);
6209         }
6210         del_timer_sync(&dev_priv->idle_timer);
6211         cancel_work_sync(&dev_priv->idle_work);
6212
6213         drm_mode_config_cleanup(dev);
6214 }
6215
6216 /*
6217  * Return which encoder is currently attached for connector.
6218  */
6219 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6220 {
6221         return &intel_attached_encoder(connector)->base;
6222 }
6223
6224 void intel_connector_attach_encoder(struct intel_connector *connector,
6225                                     struct intel_encoder *encoder)
6226 {
6227         connector->encoder = encoder;
6228         drm_mode_connector_attach_encoder(&connector->base,
6229                                           &encoder->base);
6230 }
6231
6232 /*
6233  * set vga decode state - true == enable VGA decode
6234  */
6235 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6236 {
6237         struct drm_i915_private *dev_priv = dev->dev_private;
6238         u16 gmch_ctrl;
6239
6240         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6241         if (state)
6242                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6243         else
6244                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6245         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6246         return 0;
6247 }
6248
6249 #ifdef CONFIG_DEBUG_FS
6250 #include <linux/seq_file.h>
6251
6252 struct intel_display_error_state {
6253         struct intel_cursor_error_state {
6254                 u32 control;
6255                 u32 position;
6256                 u32 base;
6257                 u32 size;
6258         } cursor[2];
6259
6260         struct intel_pipe_error_state {
6261                 u32 conf;
6262                 u32 source;
6263
6264                 u32 htotal;
6265                 u32 hblank;
6266                 u32 hsync;
6267                 u32 vtotal;
6268                 u32 vblank;
6269                 u32 vsync;
6270         } pipe[2];
6271
6272         struct intel_plane_error_state {
6273                 u32 control;
6274                 u32 stride;
6275                 u32 size;
6276                 u32 pos;
6277                 u32 addr;
6278                 u32 surface;
6279                 u32 tile_offset;
6280         } plane[2];
6281 };
6282
6283 struct intel_display_error_state *
6284 intel_display_capture_error_state(struct drm_device *dev)
6285 {
6286         drm_i915_private_t *dev_priv = dev->dev_private;
6287         struct intel_display_error_state *error;
6288         int i;
6289
6290         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6291         if (error == NULL)
6292                 return NULL;
6293
6294         for (i = 0; i < 2; i++) {
6295                 error->cursor[i].control = I915_READ(CURCNTR(i));
6296                 error->cursor[i].position = I915_READ(CURPOS(i));
6297                 error->cursor[i].base = I915_READ(CURBASE(i));
6298
6299                 error->plane[i].control = I915_READ(DSPCNTR(i));
6300                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6301                 error->plane[i].size = I915_READ(DSPSIZE(i));
6302                 error->plane[i].pos= I915_READ(DSPPOS(i));
6303                 error->plane[i].addr = I915_READ(DSPADDR(i));
6304                 if (INTEL_INFO(dev)->gen >= 4) {
6305                         error->plane[i].surface = I915_READ(DSPSURF(i));
6306                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6307                 }
6308
6309                 error->pipe[i].conf = I915_READ(PIPECONF(i));
6310                 error->pipe[i].source = I915_READ(PIPESRC(i));
6311                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6312                 error->pipe[i].hblank = I915_READ(HBLANK(i));
6313                 error->pipe[i].hsync = I915_READ(HSYNC(i));
6314                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6315                 error->pipe[i].vblank = I915_READ(VBLANK(i));
6316                 error->pipe[i].vsync = I915_READ(VSYNC(i));
6317         }
6318
6319         return error;
6320 }
6321
6322 void
6323 intel_display_print_error_state(struct seq_file *m,
6324                                 struct drm_device *dev,
6325                                 struct intel_display_error_state *error)
6326 {
6327         int i;
6328
6329         for (i = 0; i < 2; i++) {
6330                 seq_printf(m, "Pipe [%d]:\n", i);
6331                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
6332                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
6333                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
6334                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
6335                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
6336                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
6337                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
6338                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
6339
6340                 seq_printf(m, "Plane [%d]:\n", i);
6341                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
6342                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
6343                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
6344                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
6345                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
6346                 if (INTEL_INFO(dev)->gen >= 4) {
6347                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
6348                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
6349                 }
6350
6351                 seq_printf(m, "Cursor [%d]:\n", i);
6352                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
6353                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
6354                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
6355         }
6356 }
6357 #endif