drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  45 {
  46         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  47         u32 tmp;
  48
  49         /* make sure flip is at vb rather than hb */
  50         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
  51         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
  52         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
  53
  54         /* set pageflip to happen anywhere in vblank interval */
  55         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
  56
  57         /* enable the pflip int */
  58         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  59 }
  60
  61 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  62 {
  63         /* disable the pflip int */
  64         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  65 }
  66
  67 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  68 {
  69         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  70         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  71
  72         /* Lock the graphics update lock */
  73         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  74         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* update the scanout addresses */
  77         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  78                upper_32_bits(crtc_base));
  79         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  80                (u32)crtc_base);
  81
  82         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  83                upper_32_bits(crtc_base));
  84         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  85                (u32)crtc_base);
  86
  87         /* Wait for update_pending to go high. */
  88         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
  89         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  90
  91         /* Unlock the lock, so double-buffering can take place inside vblank */
  92         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
  93         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  94
  95         /* Return current update_pending status: */
  96         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
  97 }
  98
  99 /* get temperature in millidegrees */
 100 int evergreen_get_temp(struct radeon_device *rdev)
 101 {
 102         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 103                 ASIC_T_SHIFT;
 104         u32 actual_temp = 0;
 105
 106         if (temp & 0x400)
 107                 actual_temp = -256;
 108         else if (temp & 0x200)
 109                 actual_temp = 255;
 110         else if (temp & 0x100) {
 111                 actual_temp = temp & 0x1ff;
 112                 actual_temp |= ~0x1ff;
 113         } else
 114                 actual_temp = temp & 0xff;
 115
 116         return (actual_temp * 1000) / 2;
 117 }
 118
 119 int sumo_get_temp(struct radeon_device *rdev)
 120 {
 121         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 122         int actual_temp = temp - 49;
 123
 124         return actual_temp * 1000;
 125 }
 126
 127 void evergreen_pm_misc(struct radeon_device *rdev)
 128 {
 129         int req_ps_idx = rdev->pm.requested_power_state_index;
 130         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 131         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 132         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 133
 134         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 135                 if (voltage->voltage != rdev->pm.current_vddc) {
 136                         radeon_atom_set_voltage(rdev, voltage->voltage);
 137                         rdev->pm.current_vddc = voltage->voltage;
 138                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 139                 }
 140         }
 141 }
 142
 143 void evergreen_pm_prepare(struct radeon_device *rdev)
 144 {
 145         struct drm_device *ddev = rdev->ddev;
 146         struct drm_crtc *crtc;
 147         struct radeon_crtc *radeon_crtc;
 148         u32 tmp;
 149
 150         /* disable any active CRTCs */
 151         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 152                 radeon_crtc = to_radeon_crtc(crtc);
 153                 if (radeon_crtc->enabled) {
 154                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 155                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 156                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 157                 }
 158         }
 159 }
 160
 161 void evergreen_pm_finish(struct radeon_device *rdev)
 162 {
 163         struct drm_device *ddev = rdev->ddev;
 164         struct drm_crtc *crtc;
 165         struct radeon_crtc *radeon_crtc;
 166         u32 tmp;
 167
 168         /* enable any active CRTCs */
 169         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 170                 radeon_crtc = to_radeon_crtc(crtc);
 171                 if (radeon_crtc->enabled) {
 172                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 173                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 174                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 175                 }
 176         }
 177 }
 178
 179 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 180 {
 181         bool connected = false;
 182
 183         switch (hpd) {
 184         case RADEON_HPD_1:
 185                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 186                         connected = true;
 187                 break;
 188         case RADEON_HPD_2:
 189                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 190                         connected = true;
 191                 break;
 192         case RADEON_HPD_3:
 193                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 194                         connected = true;
 195                 break;
 196         case RADEON_HPD_4:
 197                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 198                         connected = true;
 199                 break;
 200         case RADEON_HPD_5:
 201                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 202                         connected = true;
 203                 break;
 204         case RADEON_HPD_6:
 205                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 206                         connected = true;
 207                         break;
 208         default:
 209                 break;
 210         }
 211
 212         return connected;
 213 }
 214
 215 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 216                                 enum radeon_hpd_id hpd)
 217 {
 218         u32 tmp;
 219         bool connected = evergreen_hpd_sense(rdev, hpd);
 220
 221         switch (hpd) {
 222         case RADEON_HPD_1:
 223                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 224                 if (connected)
 225                         tmp &= ~DC_HPDx_INT_POLARITY;
 226                 else
 227                         tmp |= DC_HPDx_INT_POLARITY;
 228                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 229                 break;
 230         case RADEON_HPD_2:
 231                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 232                 if (connected)
 233                         tmp &= ~DC_HPDx_INT_POLARITY;
 234                 else
 235                         tmp |= DC_HPDx_INT_POLARITY;
 236                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 237                 break;
 238         case RADEON_HPD_3:
 239                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 240                 if (connected)
 241                         tmp &= ~DC_HPDx_INT_POLARITY;
 242                 else
 243                         tmp |= DC_HPDx_INT_POLARITY;
 244                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 245                 break;
 246         case RADEON_HPD_4:
 247                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 248                 if (connected)
 249                         tmp &= ~DC_HPDx_INT_POLARITY;
 250                 else
 251                         tmp |= DC_HPDx_INT_POLARITY;
 252                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 253                 break;
 254         case RADEON_HPD_5:
 255                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 256                 if (connected)
 257                         tmp &= ~DC_HPDx_INT_POLARITY;
 258                 else
 259                         tmp |= DC_HPDx_INT_POLARITY;
 260                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 261                         break;
 262         case RADEON_HPD_6:
 263                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 264                 if (connected)
 265                         tmp &= ~DC_HPDx_INT_POLARITY;
 266                 else
 267                         tmp |= DC_HPDx_INT_POLARITY;
 268                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 269                 break;
 270         default:
 271                 break;
 272         }
 273 }
 274
 275 void evergreen_hpd_init(struct radeon_device *rdev)
 276 {
 277         struct drm_device *dev = rdev->ddev;
 278         struct drm_connector *connector;
 279         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 280                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 281
 282         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 283                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 284                 switch (radeon_connector->hpd.hpd) {
 285                 case RADEON_HPD_1:
 286                         WREG32(DC_HPD1_CONTROL, tmp);
 287                         rdev->irq.hpd[0] = true;
 288                         break;
 289                 case RADEON_HPD_2:
 290                         WREG32(DC_HPD2_CONTROL, tmp);
 291                         rdev->irq.hpd[1] = true;
 292                         break;
 293                 case RADEON_HPD_3:
 294                         WREG32(DC_HPD3_CONTROL, tmp);
 295                         rdev->irq.hpd[2] = true;
 296                         break;
 297                 case RADEON_HPD_4:
 298                         WREG32(DC_HPD4_CONTROL, tmp);
 299                         rdev->irq.hpd[3] = true;
 300                         break;
 301                 case RADEON_HPD_5:
 302                         WREG32(DC_HPD5_CONTROL, tmp);
 303                         rdev->irq.hpd[4] = true;
 304                         break;
 305                 case RADEON_HPD_6:
 306                         WREG32(DC_HPD6_CONTROL, tmp);
 307                         rdev->irq.hpd[5] = true;
 308                         break;
 309                 default:
 310                         break;
 311                 }
 312         }
 313         if (rdev->irq.installed)
 314                 evergreen_irq_set(rdev);
 315 }
 316
 317 void evergreen_hpd_fini(struct radeon_device *rdev)
 318 {
 319         struct drm_device *dev = rdev->ddev;
 320         struct drm_connector *connector;
 321
 322         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 323                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 324                 switch (radeon_connector->hpd.hpd) {
 325                 case RADEON_HPD_1:
 326                         WREG32(DC_HPD1_CONTROL, 0);
 327                         rdev->irq.hpd[0] = false;
 328                         break;
 329                 case RADEON_HPD_2:
 330                         WREG32(DC_HPD2_CONTROL, 0);
 331                         rdev->irq.hpd[1] = false;
 332                         break;
 333                 case RADEON_HPD_3:
 334                         WREG32(DC_HPD3_CONTROL, 0);
 335                         rdev->irq.hpd[2] = false;
 336                         break;
 337                 case RADEON_HPD_4:
 338                         WREG32(DC_HPD4_CONTROL, 0);
 339                         rdev->irq.hpd[3] = false;
 340                         break;
 341                 case RADEON_HPD_5:
 342                         WREG32(DC_HPD5_CONTROL, 0);
 343                         rdev->irq.hpd[4] = false;
 344                         break;
 345                 case RADEON_HPD_6:
 346                         WREG32(DC_HPD6_CONTROL, 0);
 347                         rdev->irq.hpd[5] = false;
 348                         break;
 349                 default:
 350                         break;
 351                 }
 352         }
 353 }
 354
 355 /* watermark setup */
 356
 357 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 358                                         struct radeon_crtc *radeon_crtc,
 359                                         struct drm_display_mode *mode,
 360                                         struct drm_display_mode *other_mode)
 361 {
 362         u32 tmp = 0;
 363         /*
 364          * Line Buffer Setup
 365          * There are 3 line buffers, each one shared by 2 display controllers.
 366          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 367          * the display controllers.  The paritioning is done via one of four
 368          * preset allocations specified in bits 2:0:
 369          * first display controller
 370          *  0 - first half of lb (3840 * 2)
 371          *  1 - first 3/4 of lb (5760 * 2)
 372          *  2 - whole lb (7680 * 2)
 373          *  3 - first 1/4 of lb (1920 * 2)
 374          * second display controller
 375          *  4 - second half of lb (3840 * 2)
 376          *  5 - second 3/4 of lb (5760 * 2)
 377          *  6 - whole lb (7680 * 2)
 378          *  7 - last 1/4 of lb (1920 * 2)
 379          */
 380         if (mode && other_mode) {
 381                 if (mode->hdisplay > other_mode->hdisplay) {
 382                         if (mode->hdisplay > 2560)
 383                                 tmp = 1; /* 3/4 */
 384                         else
 385                                 tmp = 0; /* 1/2 */
 386                 } else if (other_mode->hdisplay > mode->hdisplay) {
 387                         if (other_mode->hdisplay > 2560)
 388                                 tmp = 3; /* 1/4 */
 389                         else
 390                                 tmp = 0; /* 1/2 */
 391                 } else
 392                         tmp = 0; /* 1/2 */
 393         } else if (mode)
 394                 tmp = 2; /* whole */
 395         else if (other_mode)
 396                 tmp = 3; /* 1/4 */
 397
 398         /* second controller of the pair uses second half of the lb */
 399         if (radeon_crtc->crtc_id % 2)
 400                 tmp += 4;
 401         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 402
 403         switch (tmp) {
 404         case 0:
 405         case 4:
 406         default:
 407                 if (ASIC_IS_DCE5(rdev))
 408                         return 4096 * 2;
 409                 else
 410                         return 3840 * 2;
 411         case 1:
 412         case 5:
 413                 if (ASIC_IS_DCE5(rdev))
 414                         return 6144 * 2;
 415                 else
 416                         return 5760 * 2;
 417         case 2:
 418         case 6:
 419                 if (ASIC_IS_DCE5(rdev))
 420                         return 8192 * 2;
 421                 else
 422                         return 7680 * 2;
 423         case 3:
 424         case 7:
 425                 if (ASIC_IS_DCE5(rdev))
 426                         return 2048 * 2;
 427                 else
 428                         return 1920 * 2;
 429         }
 430 }
 431
 432 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 433 {
 434         u32 tmp = RREG32(MC_SHARED_CHMAP);
 435
 436         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 437         case 0:
 438         default:
 439                 return 1;
 440         case 1:
 441                 return 2;
 442         case 2:
 443                 return 4;
 444         case 3:
 445                 return 8;
 446         }
 447 }
 448
 449 struct evergreen_wm_params {
 450         u32 dram_channels; /* number of dram channels */
 451         u32 yclk;          /* bandwidth per dram data pin in kHz */
 452         u32 sclk;          /* engine clock in kHz */
 453         u32 disp_clk;      /* display clock in kHz */
 454         u32 src_width;     /* viewport width */
 455         u32 active_time;   /* active display time in ns */
 456         u32 blank_time;    /* blank time in ns */
 457         bool interlaced;    /* mode is interlaced */
 458         fixed20_12 vsc;    /* vertical scale ratio */
 459         u32 num_heads;     /* number of active crtcs */
 460         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 461         u32 lb_size;       /* line buffer allocated to pipe */
 462         u32 vtaps;         /* vertical scaler taps */
 463 };
 464
 465 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 466 {
 467         /* Calculate DRAM Bandwidth and the part allocated to display. */
 468         fixed20_12 dram_efficiency; /* 0.7 */
 469         fixed20_12 yclk, dram_channels, bandwidth;
 470         fixed20_12 a;
 471
 472         a.full = dfixed_const(1000);
 473         yclk.full = dfixed_const(wm->yclk);
 474         yclk.full = dfixed_div(yclk, a);
 475         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 476         a.full = dfixed_const(10);
 477         dram_efficiency.full = dfixed_const(7);
 478         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 479         bandwidth.full = dfixed_mul(dram_channels, yclk);
 480         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 481
 482         return dfixed_trunc(bandwidth);
 483 }
 484
 485 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 486 {
 487         /* Calculate DRAM Bandwidth and the part allocated to display. */
 488         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 489         fixed20_12 yclk, dram_channels, bandwidth;
 490         fixed20_12 a;
 491
 492         a.full = dfixed_const(1000);
 493         yclk.full = dfixed_const(wm->yclk);
 494         yclk.full = dfixed_div(yclk, a);
 495         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 496         a.full = dfixed_const(10);
 497         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 498         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 499         bandwidth.full = dfixed_mul(dram_channels, yclk);
 500         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 501
 502         return dfixed_trunc(bandwidth);
 503 }
 504
 505 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 506 {
 507         /* Calculate the display Data return Bandwidth */
 508         fixed20_12 return_efficiency; /* 0.8 */
 509         fixed20_12 sclk, bandwidth;
 510         fixed20_12 a;
 511
 512         a.full = dfixed_const(1000);
 513         sclk.full = dfixed_const(wm->sclk);
 514         sclk.full = dfixed_div(sclk, a);
 515         a.full = dfixed_const(10);
 516         return_efficiency.full = dfixed_const(8);
 517         return_efficiency.full = dfixed_div(return_efficiency, a);
 518         a.full = dfixed_const(32);
 519         bandwidth.full = dfixed_mul(a, sclk);
 520         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 521
 522         return dfixed_trunc(bandwidth);
 523 }
 524
 525 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 526 {
 527         /* Calculate the DMIF Request Bandwidth */
 528         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 529         fixed20_12 disp_clk, bandwidth;
 530         fixed20_12 a;
 531
 532         a.full = dfixed_const(1000);
 533         disp_clk.full = dfixed_const(wm->disp_clk);
 534         disp_clk.full = dfixed_div(disp_clk, a);
 535         a.full = dfixed_const(10);
 536         disp_clk_request_efficiency.full = dfixed_const(8);
 537         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 538         a.full = dfixed_const(32);
 539         bandwidth.full = dfixed_mul(a, disp_clk);
 540         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 541
 542         return dfixed_trunc(bandwidth);
 543 }
 544
 545 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 546 {
 547         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 548         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 549         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 550         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 551
 552         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 553 }
 554
 555 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 556 {
 557         /* Calculate the display mode Average Bandwidth
 558          * DisplayMode should contain the source and destination dimensions,
 559          * timing, etc.
 560          */
 561         fixed20_12 bpp;
 562         fixed20_12 line_time;
 563         fixed20_12 src_width;
 564         fixed20_12 bandwidth;
 565         fixed20_12 a;
 566
 567         a.full = dfixed_const(1000);
 568         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 569         line_time.full = dfixed_div(line_time, a);
 570         bpp.full = dfixed_const(wm->bytes_per_pixel);
 571         src_width.full = dfixed_const(wm->src_width);
 572         bandwidth.full = dfixed_mul(src_width, bpp);
 573         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 574         bandwidth.full = dfixed_div(bandwidth, line_time);
 575
 576         return dfixed_trunc(bandwidth);
 577 }
 578
 579 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 580 {
 581         /* First calcualte the latency in ns */
 582         u32 mc_latency = 2000; /* 2000 ns. */
 583         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 584         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 585         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 586         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 587         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 588                 (wm->num_heads * cursor_line_pair_return_time);
 589         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 590         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 591         fixed20_12 a, b, c;
 592
 593         if (wm->num_heads == 0)
 594                 return 0;
 595
 596         a.full = dfixed_const(2);
 597         b.full = dfixed_const(1);
 598         if ((wm->vsc.full > a.full) ||
 599             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 600             (wm->vtaps >= 5) ||
 601             ((wm->vsc.full >= a.full) && wm->interlaced))
 602                 max_src_lines_per_dst_line = 4;
 603         else
 604                 max_src_lines_per_dst_line = 2;
 605
 606         a.full = dfixed_const(available_bandwidth);
 607         b.full = dfixed_const(wm->num_heads);
 608         a.full = dfixed_div(a, b);
 609
 610         b.full = dfixed_const(1000);
 611         c.full = dfixed_const(wm->disp_clk);
 612         b.full = dfixed_div(c, b);
 613         c.full = dfixed_const(wm->bytes_per_pixel);
 614         b.full = dfixed_mul(b, c);
 615
 616         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 617
 618         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 619         b.full = dfixed_const(1000);
 620         c.full = dfixed_const(lb_fill_bw);
 621         b.full = dfixed_div(c, b);
 622         a.full = dfixed_div(a, b);
 623         line_fill_time = dfixed_trunc(a);
 624
 625         if (line_fill_time < wm->active_time)
 626                 return latency;
 627         else
 628                 return latency + (line_fill_time - wm->active_time);
 629
 630 }
 631
 632 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 633 {
 634         if (evergreen_average_bandwidth(wm) <=
 635             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 636                 return true;
 637         else
 638                 return false;
 639 };
 640
 641 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 642 {
 643         if (evergreen_average_bandwidth(wm) <=
 644             (evergreen_available_bandwidth(wm) / wm->num_heads))
 645                 return true;
 646         else
 647                 return false;
 648 };
 649
 650 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 651 {
 652         u32 lb_partitions = wm->lb_size / wm->src_width;
 653         u32 line_time = wm->active_time + wm->blank_time;
 654         u32 latency_tolerant_lines;
 655         u32 latency_hiding;
 656         fixed20_12 a;
 657
 658         a.full = dfixed_const(1);
 659         if (wm->vsc.full > a.full)
 660                 latency_tolerant_lines = 1;
 661         else {
 662                 if (lb_partitions <= (wm->vtaps + 1))
 663                         latency_tolerant_lines = 1;
 664                 else
 665                         latency_tolerant_lines = 2;
 666         }
 667
 668         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 669
 670         if (evergreen_latency_watermark(wm) <= latency_hiding)
 671                 return true;
 672         else
 673                 return false;
 674 }
 675
 676 static void evergreen_program_watermarks(struct radeon_device *rdev,
 677                                          struct radeon_crtc *radeon_crtc,
 678                                          u32 lb_size, u32 num_heads)
 679 {
 680         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 681         struct evergreen_wm_params wm;
 682         u32 pixel_period;
 683         u32 line_time = 0;
 684         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 685         u32 priority_a_mark = 0, priority_b_mark = 0;
 686         u32 priority_a_cnt = PRIORITY_OFF;
 687         u32 priority_b_cnt = PRIORITY_OFF;
 688         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 689         u32 tmp, arb_control3;
 690         fixed20_12 a, b, c;
 691
 692         if (radeon_crtc->base.enabled && num_heads && mode) {
 693                 pixel_period = 1000000 / (u32)mode->clock;
 694                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 695                 priority_a_cnt = 0;
 696                 priority_b_cnt = 0;
 697
 698                 wm.yclk = rdev->pm.current_mclk * 10;
 699                 wm.sclk = rdev->pm.current_sclk * 10;
 700                 wm.disp_clk = mode->clock;
 701                 wm.src_width = mode->crtc_hdisplay;
 702                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 703                 wm.blank_time = line_time - wm.active_time;
 704                 wm.interlaced = false;
 705                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 706                         wm.interlaced = true;
 707                 wm.vsc = radeon_crtc->vsc;
 708                 wm.vtaps = 1;
 709                 if (radeon_crtc->rmx_type != RMX_OFF)
 710                         wm.vtaps = 2;
 711                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 712                 wm.lb_size = lb_size;
 713                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 714                 wm.num_heads = num_heads;
 715
 716                 /* set for high clocks */
 717                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 718                 /* set for low clocks */
 719                 /* wm.yclk = low clk; wm.sclk = low clk */
 720                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 721
 722                 /* possibly force display priority to high */
 723                 /* should really do this at mode validation time... */
 724                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 725                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 726                     !evergreen_check_latency_hiding(&wm) ||
 727                     (rdev->disp_priority == 2)) {
 728                         DRM_INFO("force priority to high\n");
 729                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 730                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 731                 }
 732
 733                 a.full = dfixed_const(1000);
 734                 b.full = dfixed_const(mode->clock);
 735                 b.full = dfixed_div(b, a);
 736                 c.full = dfixed_const(latency_watermark_a);
 737                 c.full = dfixed_mul(c, b);
 738                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 739                 c.full = dfixed_div(c, a);
 740                 a.full = dfixed_const(16);
 741                 c.full = dfixed_div(c, a);
 742                 priority_a_mark = dfixed_trunc(c);
 743                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 744
 745                 a.full = dfixed_const(1000);
 746                 b.full = dfixed_const(mode->clock);
 747                 b.full = dfixed_div(b, a);
 748                 c.full = dfixed_const(latency_watermark_b);
 749                 c.full = dfixed_mul(c, b);
 750                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 751                 c.full = dfixed_div(c, a);
 752                 a.full = dfixed_const(16);
 753                 c.full = dfixed_div(c, a);
 754                 priority_b_mark = dfixed_trunc(c);
 755                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 756         }
 757
 758         /* select wm A */
 759         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 760         tmp = arb_control3;
 761         tmp &= ~LATENCY_WATERMARK_MASK(3);
 762         tmp |= LATENCY_WATERMARK_MASK(1);
 763         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 764         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 765                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 766                 LATENCY_HIGH_WATERMARK(line_time)));
 767         /* select wm B */
 768         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 769         tmp &= ~LATENCY_WATERMARK_MASK(3);
 770         tmp |= LATENCY_WATERMARK_MASK(2);
 771         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 772         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 773                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 774                 LATENCY_HIGH_WATERMARK(line_time)));
 775         /* restore original selection */
 776         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 777
 778         /* write the priority marks */
 779         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 780         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 781
 782 }
 783
 784 void evergreen_bandwidth_update(struct radeon_device *rdev)
 785 {
 786         struct drm_display_mode *mode0 = NULL;
 787         struct drm_display_mode *mode1 = NULL;
 788         u32 num_heads = 0, lb_size;
 789         int i;
 790
 791         radeon_update_display_priority(rdev);
 792
 793         for (i = 0; i < rdev->num_crtc; i++) {
 794                 if (rdev->mode_info.crtcs[i]->base.enabled)
 795                         num_heads++;
 796         }
 797         for (i = 0; i < rdev->num_crtc; i += 2) {
 798                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 799                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 800                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 801                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 802                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 803                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 804         }
 805 }
 806
 807 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 808 {
 809         unsigned i;
 810         u32 tmp;
 811
 812         for (i = 0; i < rdev->usec_timeout; i++) {
 813                 /* read MC_STATUS */
 814                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 815                 if (!tmp)
 816                         return 0;
 817                 udelay(1);
 818         }
 819         return -1;
 820 }
 821
 822 /*
 823  * GART
 824  */
 825 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 826 {
 827         unsigned i;
 828         u32 tmp;
 829
 830         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 831
 832         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 833         for (i = 0; i < rdev->usec_timeout; i++) {
 834                 /* read MC_STATUS */
 835                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 836                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 837                 if (tmp == 2) {
 838                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 839                         return;
 840                 }
 841                 if (tmp) {
 842                         return;
 843                 }
 844                 udelay(1);
 845         }
 846 }
 847
 848 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 849 {
 850         u32 tmp;
 851         int r;
 852
 853         if (rdev->gart.table.vram.robj == NULL) {
 854                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 855                 return -EINVAL;
 856         }
 857         r = radeon_gart_table_vram_pin(rdev);
 858         if (r)
 859                 return r;
 860         radeon_gart_restore(rdev);
 861         /* Setup L2 cache */
 862         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 863                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 864                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 865         WREG32(VM_L2_CNTL2, 0);
 866         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 867         /* Setup TLB control */
 868         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 869                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 870                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 871                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 872         if (rdev->flags & RADEON_IS_IGP) {
 873                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
 874                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
 875                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
 876         } else {
 877                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 878                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 879                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 880         }
 881         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 882         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 883         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 884         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 885         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 886         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 887         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 888         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 889                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 890         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 891                         (u32)(rdev->dummy_page.addr >> 12));
 892         WREG32(VM_CONTEXT1_CNTL, 0);
 893
 894         evergreen_pcie_gart_tlb_flush(rdev);
 895         rdev->gart.ready = true;
 896         return 0;
 897 }
 898
 899 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 900 {
 901         u32 tmp;
 902         int r;
 903
 904         /* Disable all tables */
 905         WREG32(VM_CONTEXT0_CNTL, 0);
 906         WREG32(VM_CONTEXT1_CNTL, 0);
 907
 908         /* Setup L2 cache */
 909         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 910                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 911         WREG32(VM_L2_CNTL2, 0);
 912         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 913         /* Setup TLB control */
 914         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 915         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 916         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 917         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 918         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 919         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 920         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 921         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 922         if (rdev->gart.table.vram.robj) {
 923                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 924                 if (likely(r == 0)) {
 925                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 926                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 927                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 928                 }
 929         }
 930 }
 931
 932 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 933 {
 934         evergreen_pcie_gart_disable(rdev);
 935         radeon_gart_table_vram_free(rdev);
 936         radeon_gart_fini(rdev);
 937 }
 938
 939
 940 void evergreen_agp_enable(struct radeon_device *rdev)
 941 {
 942         u32 tmp;
 943
 944         /* Setup L2 cache */
 945         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 946                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 947                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 948         WREG32(VM_L2_CNTL2, 0);
 949         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 950         /* Setup TLB control */
 951         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 952                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 953                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 954                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 955         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 956         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 957         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 958         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 959         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 960         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 961         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 962         WREG32(VM_CONTEXT0_CNTL, 0);
 963         WREG32(VM_CONTEXT1_CNTL, 0);
 964 }
 965
 966 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 967 {
 968         save->vga_control[0] = RREG32(D1VGA_CONTROL);
 969         save->vga_control[1] = RREG32(D2VGA_CONTROL);
 970         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 971         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 972         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 973         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 974         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 975         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 976         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 977         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 978         if (!(rdev->flags & RADEON_IS_IGP)) {
 979                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 980                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 981                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 982                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 983         }
 984
 985         /* Stop all video */
 986         WREG32(VGA_RENDER_CONTROL, 0);
 987         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 988         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 989         if (!(rdev->flags & RADEON_IS_IGP)) {
 990                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 991                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 992                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 993                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 994         }
 995         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 996         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 997         if (!(rdev->flags & RADEON_IS_IGP)) {
 998                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 999                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1000                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1001                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1002         }
1003         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1004         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1005         if (!(rdev->flags & RADEON_IS_IGP)) {
1006                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1007                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1008                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1009                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1010         }
1011
1012         WREG32(D1VGA_CONTROL, 0);
1013         WREG32(D2VGA_CONTROL, 0);
1014         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1015         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1016         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1017         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1018 }
1019
1020 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1021 {
1022         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1023                upper_32_bits(rdev->mc.vram_start));
1024         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1025                upper_32_bits(rdev->mc.vram_start));
1026         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1027                (u32)rdev->mc.vram_start);
1028         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1029                (u32)rdev->mc.vram_start);
1030
1031         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1032                upper_32_bits(rdev->mc.vram_start));
1033         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1034                upper_32_bits(rdev->mc.vram_start));
1035         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1036                (u32)rdev->mc.vram_start);
1037         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1038                (u32)rdev->mc.vram_start);
1039
1040         if (!(rdev->flags & RADEON_IS_IGP)) {
1041                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1042                        upper_32_bits(rdev->mc.vram_start));
1043                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1044                        upper_32_bits(rdev->mc.vram_start));
1045                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1046                        (u32)rdev->mc.vram_start);
1047                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1048                        (u32)rdev->mc.vram_start);
1049
1050                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1051                        upper_32_bits(rdev->mc.vram_start));
1052                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1053                        upper_32_bits(rdev->mc.vram_start));
1054                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1055                        (u32)rdev->mc.vram_start);
1056                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1057                        (u32)rdev->mc.vram_start);
1058
1059                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1060                        upper_32_bits(rdev->mc.vram_start));
1061                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1062                        upper_32_bits(rdev->mc.vram_start));
1063                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1064                        (u32)rdev->mc.vram_start);
1065                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1066                        (u32)rdev->mc.vram_start);
1067
1068                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1069                        upper_32_bits(rdev->mc.vram_start));
1070                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1071                        upper_32_bits(rdev->mc.vram_start));
1072                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1073                        (u32)rdev->mc.vram_start);
1074                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1075                        (u32)rdev->mc.vram_start);
1076         }
1077
1078         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1079         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1080         /* Unlock host access */
1081         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1082         mdelay(1);
1083         /* Restore video state */
1084         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1085         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1086         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1087         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1088         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1089         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1090         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1091         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1092         if (!(rdev->flags & RADEON_IS_IGP)) {
1093                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1094                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1095                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1096                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1097         }
1098         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1099         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1100         if (!(rdev->flags & RADEON_IS_IGP)) {
1101                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1102                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1103                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1104                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1105         }
1106         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1107         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1108         if (!(rdev->flags & RADEON_IS_IGP)) {
1109                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1110                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1111                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1112                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1113         }
1114         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1115 }
1116
1117 static void evergreen_mc_program(struct radeon_device *rdev)
1118 {
1119         struct evergreen_mc_save save;
1120         u32 tmp;
1121         int i, j;
1122
1123         /* Initialize HDP */
1124         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1125                 WREG32((0x2c14 + j), 0x00000000);
1126                 WREG32((0x2c18 + j), 0x00000000);
1127                 WREG32((0x2c1c + j), 0x00000000);
1128                 WREG32((0x2c20 + j), 0x00000000);
1129                 WREG32((0x2c24 + j), 0x00000000);
1130         }
1131         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1132
1133         evergreen_mc_stop(rdev, &save);
1134         if (evergreen_mc_wait_for_idle(rdev)) {
1135                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1136         }
1137         /* Lockout access through VGA aperture*/
1138         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1139         /* Update configuration */
1140         if (rdev->flags & RADEON_IS_AGP) {
1141                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1142                         /* VRAM before AGP */
1143                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1144                                 rdev->mc.vram_start >> 12);
1145                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1146                                 rdev->mc.gtt_end >> 12);
1147                 } else {
1148                         /* VRAM after AGP */
1149                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1150                                 rdev->mc.gtt_start >> 12);
1151                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1152                                 rdev->mc.vram_end >> 12);
1153                 }
1154         } else {
1155                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1156                         rdev->mc.vram_start >> 12);
1157                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1158                         rdev->mc.vram_end >> 12);
1159         }
1160         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1161         if (rdev->flags & RADEON_IS_IGP) {
1162                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1163                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1164                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1165                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1166         }
1167         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1168         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1169         WREG32(MC_VM_FB_LOCATION, tmp);
1170         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1171         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1172         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1173         if (rdev->flags & RADEON_IS_AGP) {
1174                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1175                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1176                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1177         } else {
1178                 WREG32(MC_VM_AGP_BASE, 0);
1179                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1180                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1181         }
1182         if (evergreen_mc_wait_for_idle(rdev)) {
1183                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1184         }
1185         evergreen_mc_resume(rdev, &save);
1186         /* we need to own VRAM, so turn off the VGA renderer here
1187          * to stop it overwriting our objects */
1188         rv515_vga_render_disable(rdev);
1189 }
1190
1191 /*
1192  * CP.
1193  */
1194 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1195 {
1196         /* set to DX10/11 mode */
1197         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1198         radeon_ring_write(rdev, 1);
1199         /* FIXME: implement */
1200         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1201         radeon_ring_write(rdev,
1202 #ifdef __BIG_ENDIAN
1203                           (2 << 0) |
1204 #endif
1205                           (ib->gpu_addr & 0xFFFFFFFC));
1206         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1207         radeon_ring_write(rdev, ib->length_dw);
1208 }
1209
1210
1211 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1212 {
1213         const __be32 *fw_data;
1214         int i;
1215
1216         if (!rdev->me_fw || !rdev->pfp_fw)
1217                 return -EINVAL;
1218
1219         r700_cp_stop(rdev);
1220         WREG32(CP_RB_CNTL,
1221 #ifdef __BIG_ENDIAN
1222                BUF_SWAP_32BIT |
1223 #endif
1224                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1225
1226         fw_data = (const __be32 *)rdev->pfp_fw->data;
1227         WREG32(CP_PFP_UCODE_ADDR, 0);
1228         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1229                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1230         WREG32(CP_PFP_UCODE_ADDR, 0);
1231
1232         fw_data = (const __be32 *)rdev->me_fw->data;
1233         WREG32(CP_ME_RAM_WADDR, 0);
1234         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1235                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1236
1237         WREG32(CP_PFP_UCODE_ADDR, 0);
1238         WREG32(CP_ME_RAM_WADDR, 0);
1239         WREG32(CP_ME_RAM_RADDR, 0);
1240         return 0;
1241 }
1242
1243 static int evergreen_cp_start(struct radeon_device *rdev)
1244 {
1245         int r, i;
1246         uint32_t cp_me;
1247
1248         r = radeon_ring_lock(rdev, 7);
1249         if (r) {
1250                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1251                 return r;
1252         }
1253         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1254         radeon_ring_write(rdev, 0x1);
1255         radeon_ring_write(rdev, 0x0);
1256         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1257         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1258         radeon_ring_write(rdev, 0);
1259         radeon_ring_write(rdev, 0);
1260         radeon_ring_unlock_commit(rdev);
1261
1262         cp_me = 0xff;
1263         WREG32(CP_ME_CNTL, cp_me);
1264
1265         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1266         if (r) {
1267                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1268                 return r;
1269         }
1270
1271         /* setup clear context state */
1272         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1273         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1274
1275         for (i = 0; i < evergreen_default_size; i++)
1276                 radeon_ring_write(rdev, evergreen_default_state[i]);
1277
1278         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1279         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1280
1281         /* set clear context state */
1282         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1283         radeon_ring_write(rdev, 0);
1284
1285         /* SQ_VTX_BASE_VTX_LOC */
1286         radeon_ring_write(rdev, 0xc0026f00);
1287         radeon_ring_write(rdev, 0x00000000);
1288         radeon_ring_write(rdev, 0x00000000);
1289         radeon_ring_write(rdev, 0x00000000);
1290
1291         /* Clear consts */
1292         radeon_ring_write(rdev, 0xc0036f00);
1293         radeon_ring_write(rdev, 0x00000bc4);
1294         radeon_ring_write(rdev, 0xffffffff);
1295         radeon_ring_write(rdev, 0xffffffff);
1296         radeon_ring_write(rdev, 0xffffffff);
1297
1298         radeon_ring_write(rdev, 0xc0026900);
1299         radeon_ring_write(rdev, 0x00000316);
1300         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1301         radeon_ring_write(rdev, 0x00000010); /*  */
1302
1303         radeon_ring_unlock_commit(rdev);
1304
1305         return 0;
1306 }
1307
1308 int evergreen_cp_resume(struct radeon_device *rdev)
1309 {
1310         u32 tmp;
1311         u32 rb_bufsz;
1312         int r;
1313
1314         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1315         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1316                                  SOFT_RESET_PA |
1317                                  SOFT_RESET_SH |
1318                                  SOFT_RESET_VGT |
1319                                  SOFT_RESET_SX));
1320         RREG32(GRBM_SOFT_RESET);
1321         mdelay(15);
1322         WREG32(GRBM_SOFT_RESET, 0);
1323         RREG32(GRBM_SOFT_RESET);
1324
1325         /* Set ring buffer size */
1326         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1327         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1328 #ifdef __BIG_ENDIAN
1329         tmp |= BUF_SWAP_32BIT;
1330 #endif
1331         WREG32(CP_RB_CNTL, tmp);
1332         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1333
1334         /* Set the write pointer delay */
1335         WREG32(CP_RB_WPTR_DELAY, 0);
1336
1337         /* Initialize the ring buffer's read and write pointers */
1338         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1339         WREG32(CP_RB_RPTR_WR, 0);
1340         WREG32(CP_RB_WPTR, 0);
1341
1342         /* set the wb address wether it's enabled or not */
1343         WREG32(CP_RB_RPTR_ADDR,
1344 #ifdef __BIG_ENDIAN
1345                RB_RPTR_SWAP(2) |
1346 #endif
1347                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1348         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1349         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1350
1351         if (rdev->wb.enabled)
1352                 WREG32(SCRATCH_UMSK, 0xff);
1353         else {
1354                 tmp |= RB_NO_UPDATE;
1355                 WREG32(SCRATCH_UMSK, 0);
1356         }
1357
1358         mdelay(1);
1359         WREG32(CP_RB_CNTL, tmp);
1360
1361         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1362         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1363
1364         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1365         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1366
1367         evergreen_cp_start(rdev);
1368         rdev->cp.ready = true;
1369         r = radeon_ring_test(rdev);
1370         if (r) {
1371                 rdev->cp.ready = false;
1372                 return r;
1373         }
1374         return 0;
1375 }
1376
1377 /*
1378  * Core functions
1379  */
1380 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1381                                                   u32 num_tile_pipes,
1382                                                   u32 num_backends,
1383                                                   u32 backend_disable_mask)
1384 {
1385         u32 backend_map = 0;
1386         u32 enabled_backends_mask = 0;
1387         u32 enabled_backends_count = 0;
1388         u32 cur_pipe;
1389         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1390         u32 cur_backend = 0;
1391         u32 i;
1392         bool force_no_swizzle;
1393
1394         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1395                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1396         if (num_tile_pipes < 1)
1397                 num_tile_pipes = 1;
1398         if (num_backends > EVERGREEN_MAX_BACKENDS)
1399                 num_backends = EVERGREEN_MAX_BACKENDS;
1400         if (num_backends < 1)
1401                 num_backends = 1;
1402
1403         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1404                 if (((backend_disable_mask >> i) & 1) == 0) {
1405                         enabled_backends_mask |= (1 << i);
1406                         ++enabled_backends_count;
1407                 }
1408                 if (enabled_backends_count == num_backends)
1409                         break;
1410         }
1411
1412         if (enabled_backends_count == 0) {
1413                 enabled_backends_mask = 1;
1414                 enabled_backends_count = 1;
1415         }
1416
1417         if (enabled_backends_count != num_backends)
1418                 num_backends = enabled_backends_count;
1419
1420         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1421         switch (rdev->family) {
1422         case CHIP_CEDAR:
1423         case CHIP_REDWOOD:
1424         case CHIP_PALM:
1425         case CHIP_TURKS:
1426         case CHIP_CAICOS:
1427                 force_no_swizzle = false;
1428                 break;
1429         case CHIP_CYPRESS:
1430         case CHIP_HEMLOCK:
1431         case CHIP_JUNIPER:
1432         case CHIP_BARTS:
1433         default:
1434                 force_no_swizzle = true;
1435                 break;
1436         }
1437         if (force_no_swizzle) {
1438                 bool last_backend_enabled = false;
1439
1440                 force_no_swizzle = false;
1441                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1442                         if (((enabled_backends_mask >> i) & 1) == 1) {
1443                                 if (last_backend_enabled)
1444                                         force_no_swizzle = true;
1445                                 last_backend_enabled = true;
1446                         } else
1447                                 last_backend_enabled = false;
1448                 }
1449         }
1450
1451         switch (num_tile_pipes) {
1452         case 1:
1453         case 3:
1454         case 5:
1455         case 7:
1456                 DRM_ERROR("odd number of pipes!\n");
1457                 break;
1458         case 2:
1459                 swizzle_pipe[0] = 0;
1460                 swizzle_pipe[1] = 1;
1461                 break;
1462         case 4:
1463                 if (force_no_swizzle) {
1464                         swizzle_pipe[0] = 0;
1465                         swizzle_pipe[1] = 1;
1466                         swizzle_pipe[2] = 2;
1467                         swizzle_pipe[3] = 3;
1468                 } else {
1469                         swizzle_pipe[0] = 0;
1470                         swizzle_pipe[1] = 2;
1471                         swizzle_pipe[2] = 1;
1472                         swizzle_pipe[3] = 3;
1473                 }
1474                 break;
1475         case 6:
1476                 if (force_no_swizzle) {
1477                         swizzle_pipe[0] = 0;
1478                         swizzle_pipe[1] = 1;
1479                         swizzle_pipe[2] = 2;
1480                         swizzle_pipe[3] = 3;
1481                         swizzle_pipe[4] = 4;
1482                         swizzle_pipe[5] = 5;
1483                 } else {
1484                         swizzle_pipe[0] = 0;
1485                         swizzle_pipe[1] = 2;
1486                         swizzle_pipe[2] = 4;
1487                         swizzle_pipe[3] = 1;
1488                         swizzle_pipe[4] = 3;
1489                         swizzle_pipe[5] = 5;
1490                 }
1491                 break;
1492         case 8:
1493                 if (force_no_swizzle) {
1494                         swizzle_pipe[0] = 0;
1495                         swizzle_pipe[1] = 1;
1496                         swizzle_pipe[2] = 2;
1497                         swizzle_pipe[3] = 3;
1498                         swizzle_pipe[4] = 4;
1499                         swizzle_pipe[5] = 5;
1500                         swizzle_pipe[6] = 6;
1501                         swizzle_pipe[7] = 7;
1502                 } else {
1503                         swizzle_pipe[0] = 0;
1504                         swizzle_pipe[1] = 2;
1505                         swizzle_pipe[2] = 4;
1506                         swizzle_pipe[3] = 6;
1507                         swizzle_pipe[4] = 1;
1508                         swizzle_pipe[5] = 3;
1509                         swizzle_pipe[6] = 5;
1510                         swizzle_pipe[7] = 7;
1511                 }
1512                 break;
1513         }
1514
1515         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1516                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1517                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1518
1519                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1520
1521                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1522         }
1523
1524         return backend_map;
1525 }
1526
1527 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1528 {
1529         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1530
1531         tmp = RREG32(MC_SHARED_CHMAP);
1532         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1533         case 0:
1534         case 1:
1535         case 2:
1536         case 3:
1537         default:
1538                 /* default mapping */
1539                 mc_shared_chremap = 0x00fac688;
1540                 break;
1541         }
1542
1543         switch (rdev->family) {
1544         case CHIP_HEMLOCK:
1545         case CHIP_CYPRESS:
1546         case CHIP_BARTS:
1547                 tcp_chan_steer_lo = 0x54763210;
1548                 tcp_chan_steer_hi = 0x0000ba98;
1549                 break;
1550         case CHIP_JUNIPER:
1551         case CHIP_REDWOOD:
1552         case CHIP_CEDAR:
1553         case CHIP_PALM:
1554         case CHIP_TURKS:
1555         case CHIP_CAICOS:
1556         default:
1557                 tcp_chan_steer_lo = 0x76543210;
1558                 tcp_chan_steer_hi = 0x0000ba98;
1559                 break;
1560         }
1561
1562         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1563         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1564         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1565 }
1566
1567 static void evergreen_gpu_init(struct radeon_device *rdev)
1568 {
1569         u32 cc_rb_backend_disable = 0;
1570         u32 cc_gc_shader_pipe_config;
1571         u32 gb_addr_config = 0;
1572         u32 mc_shared_chmap, mc_arb_ramcfg;
1573         u32 gb_backend_map;
1574         u32 grbm_gfx_index;
1575         u32 sx_debug_1;
1576         u32 smx_dc_ctl0;
1577         u32 sq_config;
1578         u32 sq_lds_resource_mgmt;
1579         u32 sq_gpr_resource_mgmt_1;
1580         u32 sq_gpr_resource_mgmt_2;
1581         u32 sq_gpr_resource_mgmt_3;
1582         u32 sq_thread_resource_mgmt;
1583         u32 sq_thread_resource_mgmt_2;
1584         u32 sq_stack_resource_mgmt_1;
1585         u32 sq_stack_resource_mgmt_2;
1586         u32 sq_stack_resource_mgmt_3;
1587         u32 vgt_cache_invalidation;
1588         u32 hdp_host_path_cntl, tmp;
1589         int i, j, num_shader_engines, ps_thread_count;
1590
1591         switch (rdev->family) {
1592         case CHIP_CYPRESS:
1593         case CHIP_HEMLOCK:
1594                 rdev->config.evergreen.num_ses = 2;
1595                 rdev->config.evergreen.max_pipes = 4;
1596                 rdev->config.evergreen.max_tile_pipes = 8;
1597                 rdev->config.evergreen.max_simds = 10;
1598                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1599                 rdev->config.evergreen.max_gprs = 256;
1600                 rdev->config.evergreen.max_threads = 248;
1601                 rdev->config.evergreen.max_gs_threads = 32;
1602                 rdev->config.evergreen.max_stack_entries = 512;
1603                 rdev->config.evergreen.sx_num_of_sets = 4;
1604                 rdev->config.evergreen.sx_max_export_size = 256;
1605                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1606                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1607                 rdev->config.evergreen.max_hw_contexts = 8;
1608                 rdev->config.evergreen.sq_num_cf_insts = 2;
1609
1610                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1611                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1612                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1613                 break;
1614         case CHIP_JUNIPER:
1615                 rdev->config.evergreen.num_ses = 1;
1616                 rdev->config.evergreen.max_pipes = 4;
1617                 rdev->config.evergreen.max_tile_pipes = 4;
1618                 rdev->config.evergreen.max_simds = 10;
1619                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1620                 rdev->config.evergreen.max_gprs = 256;
1621                 rdev->config.evergreen.max_threads = 248;
1622                 rdev->config.evergreen.max_gs_threads = 32;
1623                 rdev->config.evergreen.max_stack_entries = 512;
1624                 rdev->config.evergreen.sx_num_of_sets = 4;
1625                 rdev->config.evergreen.sx_max_export_size = 256;
1626                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1627                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1628                 rdev->config.evergreen.max_hw_contexts = 8;
1629                 rdev->config.evergreen.sq_num_cf_insts = 2;
1630
1631                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1632                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1633                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1634                 break;
1635         case CHIP_REDWOOD:
1636                 rdev->config.evergreen.num_ses = 1;
1637                 rdev->config.evergreen.max_pipes = 4;
1638                 rdev->config.evergreen.max_tile_pipes = 4;
1639                 rdev->config.evergreen.max_simds = 5;
1640                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1641                 rdev->config.evergreen.max_gprs = 256;
1642                 rdev->config.evergreen.max_threads = 248;
1643                 rdev->config.evergreen.max_gs_threads = 32;
1644                 rdev->config.evergreen.max_stack_entries = 256;
1645                 rdev->config.evergreen.sx_num_of_sets = 4;
1646                 rdev->config.evergreen.sx_max_export_size = 256;
1647                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1648                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1649                 rdev->config.evergreen.max_hw_contexts = 8;
1650                 rdev->config.evergreen.sq_num_cf_insts = 2;
1651
1652                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1653                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1654                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1655                 break;
1656         case CHIP_CEDAR:
1657         default:
1658                 rdev->config.evergreen.num_ses = 1;
1659                 rdev->config.evergreen.max_pipes = 2;
1660                 rdev->config.evergreen.max_tile_pipes = 2;
1661                 rdev->config.evergreen.max_simds = 2;
1662                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1663                 rdev->config.evergreen.max_gprs = 256;
1664                 rdev->config.evergreen.max_threads = 192;
1665                 rdev->config.evergreen.max_gs_threads = 16;
1666                 rdev->config.evergreen.max_stack_entries = 256;
1667                 rdev->config.evergreen.sx_num_of_sets = 4;
1668                 rdev->config.evergreen.sx_max_export_size = 128;
1669                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1670                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1671                 rdev->config.evergreen.max_hw_contexts = 4;
1672                 rdev->config.evergreen.sq_num_cf_insts = 1;
1673
1674                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1675                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1676                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1677                 break;
1678         case CHIP_PALM:
1679                 rdev->config.evergreen.num_ses = 1;
1680                 rdev->config.evergreen.max_pipes = 2;
1681                 rdev->config.evergreen.max_tile_pipes = 2;
1682                 rdev->config.evergreen.max_simds = 2;
1683                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1684                 rdev->config.evergreen.max_gprs = 256;
1685                 rdev->config.evergreen.max_threads = 192;
1686                 rdev->config.evergreen.max_gs_threads = 16;
1687                 rdev->config.evergreen.max_stack_entries = 256;
1688                 rdev->config.evergreen.sx_num_of_sets = 4;
1689                 rdev->config.evergreen.sx_max_export_size = 128;
1690                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1691                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1692                 rdev->config.evergreen.max_hw_contexts = 4;
1693                 rdev->config.evergreen.sq_num_cf_insts = 1;
1694
1695                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1696                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1697                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1698                 break;
1699         case CHIP_BARTS:
1700                 rdev->config.evergreen.num_ses = 2;
1701                 rdev->config.evergreen.max_pipes = 4;
1702                 rdev->config.evergreen.max_tile_pipes = 8;
1703                 rdev->config.evergreen.max_simds = 7;
1704                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1705                 rdev->config.evergreen.max_gprs = 256;
1706                 rdev->config.evergreen.max_threads = 248;
1707                 rdev->config.evergreen.max_gs_threads = 32;
1708                 rdev->config.evergreen.max_stack_entries = 512;
1709                 rdev->config.evergreen.sx_num_of_sets = 4;
1710                 rdev->config.evergreen.sx_max_export_size = 256;
1711                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1712                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1713                 rdev->config.evergreen.max_hw_contexts = 8;
1714                 rdev->config.evergreen.sq_num_cf_insts = 2;
1715
1716                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1717                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1718                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1719                 break;
1720         case CHIP_TURKS:
1721                 rdev->config.evergreen.num_ses = 1;
1722                 rdev->config.evergreen.max_pipes = 4;
1723                 rdev->config.evergreen.max_tile_pipes = 4;
1724                 rdev->config.evergreen.max_simds = 6;
1725                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1726                 rdev->config.evergreen.max_gprs = 256;
1727                 rdev->config.evergreen.max_threads = 248;
1728                 rdev->config.evergreen.max_gs_threads = 32;
1729                 rdev->config.evergreen.max_stack_entries = 256;
1730                 rdev->config.evergreen.sx_num_of_sets = 4;
1731                 rdev->config.evergreen.sx_max_export_size = 256;
1732                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1733                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1734                 rdev->config.evergreen.max_hw_contexts = 8;
1735                 rdev->config.evergreen.sq_num_cf_insts = 2;
1736
1737                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1738                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1739                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1740                 break;
1741         case CHIP_CAICOS:
1742                 rdev->config.evergreen.num_ses = 1;
1743                 rdev->config.evergreen.max_pipes = 4;
1744                 rdev->config.evergreen.max_tile_pipes = 2;
1745                 rdev->config.evergreen.max_simds = 2;
1746                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1747                 rdev->config.evergreen.max_gprs = 256;
1748                 rdev->config.evergreen.max_threads = 192;
1749                 rdev->config.evergreen.max_gs_threads = 16;
1750                 rdev->config.evergreen.max_stack_entries = 256;
1751                 rdev->config.evergreen.sx_num_of_sets = 4;
1752                 rdev->config.evergreen.sx_max_export_size = 128;
1753                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1754                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1755                 rdev->config.evergreen.max_hw_contexts = 4;
1756                 rdev->config.evergreen.sq_num_cf_insts = 1;
1757
1758                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1759                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1760                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1761                 break;
1762         }
1763
1764         /* Initialize HDP */
1765         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1766                 WREG32((0x2c14 + j), 0x00000000);
1767                 WREG32((0x2c18 + j), 0x00000000);
1768                 WREG32((0x2c1c + j), 0x00000000);
1769                 WREG32((0x2c20 + j), 0x00000000);
1770                 WREG32((0x2c24 + j), 0x00000000);
1771         }
1772
1773         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1774
1775         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1776
1777         cc_gc_shader_pipe_config |=
1778                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1779                                   & EVERGREEN_MAX_PIPES_MASK);
1780         cc_gc_shader_pipe_config |=
1781                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1782                                & EVERGREEN_MAX_SIMDS_MASK);
1783
1784         cc_rb_backend_disable =
1785                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1786                                 & EVERGREEN_MAX_BACKENDS_MASK);
1787
1788
1789         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1790         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1791
1792         switch (rdev->config.evergreen.max_tile_pipes) {
1793         case 1:
1794         default:
1795                 gb_addr_config |= NUM_PIPES(0);
1796                 break;
1797         case 2:
1798                 gb_addr_config |= NUM_PIPES(1);
1799                 break;
1800         case 4:
1801                 gb_addr_config |= NUM_PIPES(2);
1802                 break;
1803         case 8:
1804                 gb_addr_config |= NUM_PIPES(3);
1805                 break;
1806         }
1807
1808         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1809         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1810         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1811         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1812         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1813         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1814
1815         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1816                 gb_addr_config |= ROW_SIZE(2);
1817         else
1818                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1819
1820         if (rdev->ddev->pdev->device == 0x689e) {
1821                 u32 efuse_straps_4;
1822                 u32 efuse_straps_3;
1823                 u8 efuse_box_bit_131_124;
1824
1825                 WREG32(RCU_IND_INDEX, 0x204);
1826                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1827                 WREG32(RCU_IND_INDEX, 0x203);
1828                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1829                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1830
1831                 switch(efuse_box_bit_131_124) {
1832                 case 0x00:
1833                         gb_backend_map = 0x76543210;
1834                         break;
1835                 case 0x55:
1836                         gb_backend_map = 0x77553311;
1837                         break;
1838                 case 0x56:
1839                         gb_backend_map = 0x77553300;
1840                         break;
1841                 case 0x59:
1842                         gb_backend_map = 0x77552211;
1843                         break;
1844                 case 0x66:
1845                         gb_backend_map = 0x77443300;
1846                         break;
1847                 case 0x99:
1848                         gb_backend_map = 0x66552211;
1849                         break;
1850                 case 0x5a:
1851                         gb_backend_map = 0x77552200;
1852                         break;
1853                 case 0xaa:
1854                         gb_backend_map = 0x66442200;
1855                         break;
1856                 case 0x95:
1857                         gb_backend_map = 0x66553311;
1858                         break;
1859                 default:
1860                         DRM_ERROR("bad backend map, using default\n");
1861                         gb_backend_map =
1862                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1863                                                                        rdev->config.evergreen.max_tile_pipes,
1864                                                                        rdev->config.evergreen.max_backends,
1865                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1866                                                                    rdev->config.evergreen.max_backends) &
1867                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1868                         break;
1869                 }
1870         } else if (rdev->ddev->pdev->device == 0x68b9) {
1871                 u32 efuse_straps_3;
1872                 u8 efuse_box_bit_127_124;
1873
1874                 WREG32(RCU_IND_INDEX, 0x203);
1875                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1876                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1877
1878                 switch(efuse_box_bit_127_124) {
1879                 case 0x0:
1880                         gb_backend_map = 0x00003210;
1881                         break;
1882                 case 0x5:
1883                 case 0x6:
1884                 case 0x9:
1885                 case 0xa:
1886                         gb_backend_map = 0x00003311;
1887                         break;
1888                 default:
1889                         DRM_ERROR("bad backend map, using default\n");
1890                         gb_backend_map =
1891                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1892                                                                        rdev->config.evergreen.max_tile_pipes,
1893                                                                        rdev->config.evergreen.max_backends,
1894                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1895                                                                    rdev->config.evergreen.max_backends) &
1896                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1897                         break;
1898                 }
1899         } else {
1900                 switch (rdev->family) {
1901                 case CHIP_CYPRESS:
1902                 case CHIP_HEMLOCK:
1903                 case CHIP_BARTS:
1904                         gb_backend_map = 0x66442200;
1905                         break;
1906                 case CHIP_JUNIPER:
1907                         gb_backend_map = 0x00006420;
1908                         break;
1909                 default:
1910                         gb_backend_map =
1911                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1912                                                                        rdev->config.evergreen.max_tile_pipes,
1913                                                                        rdev->config.evergreen.max_backends,
1914                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1915                                                                          rdev->config.evergreen.max_backends) &
1916                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1917                 }
1918         }
1919
1920         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1921          * not have bank info, so create a custom tiling dword.
1922          * bits 3:0   num_pipes
1923          * bits 7:4   num_banks
1924          * bits 11:8  group_size
1925          * bits 15:12 row_size
1926          */
1927         rdev->config.evergreen.tile_config = 0;
1928         switch (rdev->config.evergreen.max_tile_pipes) {
1929         case 1:
1930         default:
1931                 rdev->config.evergreen.tile_config |= (0 << 0);
1932                 break;
1933         case 2:
1934                 rdev->config.evergreen.tile_config |= (1 << 0);
1935                 break;
1936         case 4:
1937                 rdev->config.evergreen.tile_config |= (2 << 0);
1938                 break;
1939         case 8:
1940                 rdev->config.evergreen.tile_config |= (3 << 0);
1941                 break;
1942         }
1943         rdev->config.evergreen.tile_config |=
1944                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1945         rdev->config.evergreen.tile_config |=
1946                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1947         rdev->config.evergreen.tile_config |=
1948                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1949
1950         WREG32(GB_BACKEND_MAP, gb_backend_map);
1951         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1952         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1953         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1954
1955         evergreen_program_channel_remap(rdev);
1956
1957         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1958         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1959
1960         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1961                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1962                 u32 sp = cc_gc_shader_pipe_config;
1963                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1964
1965                 if (i == num_shader_engines) {
1966                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1967                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1968                 }
1969
1970                 WREG32(GRBM_GFX_INDEX, gfx);
1971                 WREG32(RLC_GFX_INDEX, gfx);
1972
1973                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1974                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1975                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1976                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1977         }
1978
1979         grbm_gfx_index |= SE_BROADCAST_WRITES;
1980         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1981         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1982
1983         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1984         WREG32(CGTS_TCC_DISABLE, 0);
1985         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1986         WREG32(CGTS_USER_TCC_DISABLE, 0);
1987
1988         /* set HW defaults for 3D engine */
1989         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1990                                      ROQ_IB2_START(0x2b)));
1991
1992         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1993
1994         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1995                              SYNC_GRADIENT |
1996                              SYNC_WALKER |
1997                              SYNC_ALIGNER));
1998
1999         sx_debug_1 = RREG32(SX_DEBUG_1);
2000         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2001         WREG32(SX_DEBUG_1, sx_debug_1);
2002
2003
2004         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2005         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2006         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2007         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2008
2009         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2010                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2011                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2012
2013         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2014                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2015                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2016
2017         WREG32(VGT_NUM_INSTANCES, 1);
2018         WREG32(SPI_CONFIG_CNTL, 0);
2019         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2020         WREG32(CP_PERFMON_CNTL, 0);
2021
2022         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2023                                   FETCH_FIFO_HIWATER(0x4) |
2024                                   DONE_FIFO_HIWATER(0xe0) |
2025                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2026
2027         sq_config = RREG32(SQ_CONFIG);
2028         sq_config &= ~(PS_PRIO(3) |
2029                        VS_PRIO(3) |
2030                        GS_PRIO(3) |
2031                        ES_PRIO(3));
2032         sq_config |= (VC_ENABLE |
2033                       EXPORT_SRC_C |
2034                       PS_PRIO(0) |
2035                       VS_PRIO(1) |
2036                       GS_PRIO(2) |
2037                       ES_PRIO(3));
2038
2039         switch (rdev->family) {
2040         case CHIP_CEDAR:
2041         case CHIP_PALM:
2042         case CHIP_CAICOS:
2043                 /* no vertex cache */
2044                 sq_config &= ~VC_ENABLE;
2045                 break;
2046         default:
2047                 break;
2048         }
2049
2050         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2051
2052         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2053         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2054         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2055         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2056         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2057         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2058         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2059
2060         switch (rdev->family) {
2061         case CHIP_CEDAR:
2062         case CHIP_PALM:
2063                 ps_thread_count = 96;
2064                 break;
2065         default:
2066                 ps_thread_count = 128;
2067                 break;
2068         }
2069
2070         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2071         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2072         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2073         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2074         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2075         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2076
2077         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2078         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2079         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2080         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2081         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2082         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2083
2084         WREG32(SQ_CONFIG, sq_config);
2085         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2086         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2087         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2088         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2089         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2090         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2091         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2092         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2093         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2094         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2095
2096         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2097                                           FORCE_EOV_MAX_REZ_CNT(255)));
2098
2099         switch (rdev->family) {
2100         case CHIP_CEDAR:
2101         case CHIP_PALM:
2102         case CHIP_CAICOS:
2103                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2104                 break;
2105         default:
2106                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2107                 break;
2108         }
2109         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2110         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2111
2112         WREG32(VGT_GS_VERTEX_REUSE, 16);
2113         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2114         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2115
2116         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2117         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2118
2119         WREG32(CB_PERF_CTR0_SEL_0, 0);
2120         WREG32(CB_PERF_CTR0_SEL_1, 0);
2121         WREG32(CB_PERF_CTR1_SEL_0, 0);
2122         WREG32(CB_PERF_CTR1_SEL_1, 0);
2123         WREG32(CB_PERF_CTR2_SEL_0, 0);
2124         WREG32(CB_PERF_CTR2_SEL_1, 0);
2125         WREG32(CB_PERF_CTR3_SEL_0, 0);
2126         WREG32(CB_PERF_CTR3_SEL_1, 0);
2127
2128         /* clear render buffer base addresses */
2129         WREG32(CB_COLOR0_BASE, 0);
2130         WREG32(CB_COLOR1_BASE, 0);
2131         WREG32(CB_COLOR2_BASE, 0);
2132         WREG32(CB_COLOR3_BASE, 0);
2133         WREG32(CB_COLOR4_BASE, 0);
2134         WREG32(CB_COLOR5_BASE, 0);
2135         WREG32(CB_COLOR6_BASE, 0);
2136         WREG32(CB_COLOR7_BASE, 0);
2137         WREG32(CB_COLOR8_BASE, 0);
2138         WREG32(CB_COLOR9_BASE, 0);
2139         WREG32(CB_COLOR10_BASE, 0);
2140         WREG32(CB_COLOR11_BASE, 0);
2141
2142         /* set the shader const cache sizes to 0 */
2143         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2144                 WREG32(i, 0);
2145         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2146                 WREG32(i, 0);
2147
2148         tmp = RREG32(HDP_MISC_CNTL);
2149         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2150         WREG32(HDP_MISC_CNTL, tmp);
2151
2152         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2153         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2154
2155         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2156
2157         udelay(50);
2158
2159 }
2160
2161 int evergreen_mc_init(struct radeon_device *rdev)
2162 {
2163         u32 tmp;
2164         int chansize, numchan;
2165
2166         /* Get VRAM informations */
2167         rdev->mc.vram_is_ddr = true;
2168         tmp = RREG32(MC_ARB_RAMCFG);
2169         if (tmp & CHANSIZE_OVERRIDE) {
2170                 chansize = 16;
2171         } else if (tmp & CHANSIZE_MASK) {
2172                 chansize = 64;
2173         } else {
2174                 chansize = 32;
2175         }
2176         tmp = RREG32(MC_SHARED_CHMAP);
2177         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2178         case 0:
2179         default:
2180                 numchan = 1;
2181                 break;
2182         case 1:
2183                 numchan = 2;
2184                 break;
2185         case 2:
2186                 numchan = 4;
2187                 break;
2188         case 3:
2189                 numchan = 8;
2190                 break;
2191         }
2192         rdev->mc.vram_width = numchan * chansize;
2193         /* Could aper size report 0 ? */
2194         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2195         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2196         /* Setup GPU memory space */
2197         if (rdev->flags & RADEON_IS_IGP) {
2198                 /* size in bytes on fusion */
2199                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2200                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2201         } else {
2202                 /* size in MB on evergreen */
2203                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2204                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2205         }
2206         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2207         r700_vram_gtt_location(rdev, &rdev->mc);
2208         radeon_update_bandwidth_info(rdev);
2209
2210         return 0;
2211 }
2212
2213 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2214 {
2215         u32 srbm_status;
2216         u32 grbm_status;
2217         u32 grbm_status_se0, grbm_status_se1;
2218         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2219         int r;
2220
2221         srbm_status = RREG32(SRBM_STATUS);
2222         grbm_status = RREG32(GRBM_STATUS);
2223         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2224         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2225         if (!(grbm_status & GUI_ACTIVE)) {
2226                 r100_gpu_lockup_update(lockup, &rdev->cp);
2227                 return false;
2228         }
2229         /* force CP activities */
2230         r = radeon_ring_lock(rdev, 2);
2231         if (!r) {
2232                 /* PACKET2 NOP */
2233                 radeon_ring_write(rdev, 0x80000000);
2234                 radeon_ring_write(rdev, 0x80000000);
2235                 radeon_ring_unlock_commit(rdev);
2236         }
2237         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2238         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2239 }
2240
2241 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2242 {
2243         struct evergreen_mc_save save;
2244         u32 grbm_reset = 0;
2245
2246         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2247                 return 0;
2248
2249         dev_info(rdev->dev, "GPU softreset \n");
2250         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2251                 RREG32(GRBM_STATUS));
2252         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2253                 RREG32(GRBM_STATUS_SE0));
2254         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2255                 RREG32(GRBM_STATUS_SE1));
2256         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2257                 RREG32(SRBM_STATUS));
2258         evergreen_mc_stop(rdev, &save);
2259         if (evergreen_mc_wait_for_idle(rdev)) {
2260                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2261         }
2262         /* Disable CP parsing/prefetching */
2263         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2264
2265         /* reset all the gfx blocks */
2266         grbm_reset = (SOFT_RESET_CP |
2267                       SOFT_RESET_CB |
2268                       SOFT_RESET_DB |
2269                       SOFT_RESET_PA |
2270                       SOFT_RESET_SC |
2271                       SOFT_RESET_SPI |
2272                       SOFT_RESET_SH |
2273                       SOFT_RESET_SX |
2274                       SOFT_RESET_TC |
2275                       SOFT_RESET_TA |
2276                       SOFT_RESET_VC |
2277                       SOFT_RESET_VGT);
2278
2279         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2280         WREG32(GRBM_SOFT_RESET, grbm_reset);
2281         (void)RREG32(GRBM_SOFT_RESET);
2282         udelay(50);
2283         WREG32(GRBM_SOFT_RESET, 0);
2284         (void)RREG32(GRBM_SOFT_RESET);
2285         /* Wait a little for things to settle down */
2286         udelay(50);
2287         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2288                 RREG32(GRBM_STATUS));
2289         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2290                 RREG32(GRBM_STATUS_SE0));
2291         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2292                 RREG32(GRBM_STATUS_SE1));
2293         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2294                 RREG32(SRBM_STATUS));
2295         evergreen_mc_resume(rdev, &save);
2296         return 0;
2297 }
2298
2299 int evergreen_asic_reset(struct radeon_device *rdev)
2300 {
2301         return evergreen_gpu_soft_reset(rdev);
2302 }
2303
2304 /* Interrupts */
2305
2306 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2307 {
2308         switch (crtc) {
2309         case 0:
2310                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2311         case 1:
2312                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2313         case 2:
2314                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2315         case 3:
2316                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2317         case 4:
2318                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2319         case 5:
2320                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2321         default:
2322                 return 0;
2323         }
2324 }
2325
2326 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2327 {
2328         u32 tmp;
2329
2330         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2331         WREG32(GRBM_INT_CNTL, 0);
2332         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2333         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2334         if (!(rdev->flags & RADEON_IS_IGP)) {
2335                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2336                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2337                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2338                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2339         }
2340
2341         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2342         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2343         if (!(rdev->flags & RADEON_IS_IGP)) {
2344                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2345                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2346                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2347                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2348         }
2349
2350         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2351         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2352
2353         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2354         WREG32(DC_HPD1_INT_CONTROL, tmp);
2355         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2356         WREG32(DC_HPD2_INT_CONTROL, tmp);
2357         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2358         WREG32(DC_HPD3_INT_CONTROL, tmp);
2359         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2360         WREG32(DC_HPD4_INT_CONTROL, tmp);
2361         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2362         WREG32(DC_HPD5_INT_CONTROL, tmp);
2363         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2364         WREG32(DC_HPD6_INT_CONTROL, tmp);
2365
2366 }
2367
2368 int evergreen_irq_set(struct radeon_device *rdev)
2369 {
2370         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2371         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2372         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2373         u32 grbm_int_cntl = 0;
2374         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2375
2376         if (!rdev->irq.installed) {
2377                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2378                 return -EINVAL;
2379         }
2380         /* don't enable anything if the ih is disabled */
2381         if (!rdev->ih.enabled) {
2382                 r600_disable_interrupts(rdev);
2383                 /* force the active interrupt state to all disabled */
2384                 evergreen_disable_interrupt_state(rdev);
2385                 return 0;
2386         }
2387
2388         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2389         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2390         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2391         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2392         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2393         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2394
2395         if (rdev->irq.sw_int) {
2396                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2397                 cp_int_cntl |= RB_INT_ENABLE;
2398                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2399         }
2400         if (rdev->irq.crtc_vblank_int[0] ||
2401             rdev->irq.pflip[0]) {
2402                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2403                 crtc1 |= VBLANK_INT_MASK;
2404         }
2405         if (rdev->irq.crtc_vblank_int[1] ||
2406             rdev->irq.pflip[1]) {
2407                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2408                 crtc2 |= VBLANK_INT_MASK;
2409         }
2410         if (rdev->irq.crtc_vblank_int[2] ||
2411             rdev->irq.pflip[2]) {
2412                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2413                 crtc3 |= VBLANK_INT_MASK;
2414         }
2415         if (rdev->irq.crtc_vblank_int[3] ||
2416             rdev->irq.pflip[3]) {
2417                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2418                 crtc4 |= VBLANK_INT_MASK;
2419         }
2420         if (rdev->irq.crtc_vblank_int[4] ||
2421             rdev->irq.pflip[4]) {
2422                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2423                 crtc5 |= VBLANK_INT_MASK;
2424         }
2425         if (rdev->irq.crtc_vblank_int[5] ||
2426             rdev->irq.pflip[5]) {
2427                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2428                 crtc6 |= VBLANK_INT_MASK;
2429         }
2430         if (rdev->irq.hpd[0]) {
2431                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2432                 hpd1 |= DC_HPDx_INT_EN;
2433         }
2434         if (rdev->irq.hpd[1]) {
2435                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2436                 hpd2 |= DC_HPDx_INT_EN;
2437         }
2438         if (rdev->irq.hpd[2]) {
2439                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2440                 hpd3 |= DC_HPDx_INT_EN;
2441         }
2442         if (rdev->irq.hpd[3]) {
2443                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2444                 hpd4 |= DC_HPDx_INT_EN;
2445         }
2446         if (rdev->irq.hpd[4]) {
2447                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2448                 hpd5 |= DC_HPDx_INT_EN;
2449         }
2450         if (rdev->irq.hpd[5]) {
2451                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2452                 hpd6 |= DC_HPDx_INT_EN;
2453         }
2454         if (rdev->irq.gui_idle) {
2455                 DRM_DEBUG("gui idle\n");
2456                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2457         }
2458
2459         WREG32(CP_INT_CNTL, cp_int_cntl);
2460         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2461
2462         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2463         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2464         if (!(rdev->flags & RADEON_IS_IGP)) {
2465                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2466                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2467                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2468                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2469         }
2470
2471         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2472         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2473         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2474         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2475         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2476         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2477
2478         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2479         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2480         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2481         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2482         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2483         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2484
2485         return 0;
2486 }
2487
2488 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2489 {
2490         u32 tmp;
2491
2492         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2493         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2494         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2495         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2496         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2497         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2498         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2499         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2500         rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2501         rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2502         rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2503         rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2504
2505         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2506                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2507         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2508                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2509         if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2510                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2511         if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2512                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2513         if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2514                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2515         if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2516                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2517
2518         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2519                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2520         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2521                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2522
2523         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2524                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2525         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2526                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2527
2528         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2529                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2530         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2531                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2532
2533         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2534                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2535         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2536                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2537
2538         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2539                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2540         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2541                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2542
2543         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2544                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2545         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2546                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2547
2548         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2549                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2550                 tmp |= DC_HPDx_INT_ACK;
2551                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2552         }
2553         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2554                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2555                 tmp |= DC_HPDx_INT_ACK;
2556                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2557         }
2558         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2559                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2560                 tmp |= DC_HPDx_INT_ACK;
2561                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2562         }
2563         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2564                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2565                 tmp |= DC_HPDx_INT_ACK;
2566                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2567         }
2568         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2569                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2570                 tmp |= DC_HPDx_INT_ACK;
2571                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2572         }
2573         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2574                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2575                 tmp |= DC_HPDx_INT_ACK;
2576                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2577         }
2578 }
2579
2580 void evergreen_irq_disable(struct radeon_device *rdev)
2581 {
2582         r600_disable_interrupts(rdev);
2583         /* Wait and acknowledge irq */
2584         mdelay(1);
2585         evergreen_irq_ack(rdev);
2586         evergreen_disable_interrupt_state(rdev);
2587 }
2588
2589 static void evergreen_irq_suspend(struct radeon_device *rdev)
2590 {
2591         evergreen_irq_disable(rdev);
2592         r600_rlc_stop(rdev);
2593 }
2594
2595 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2596 {
2597         u32 wptr, tmp;
2598
2599         if (rdev->wb.enabled)
2600                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2601         else
2602                 wptr = RREG32(IH_RB_WPTR);
2603
2604         if (wptr & RB_OVERFLOW) {
2605                 /* When a ring buffer overflow happen start parsing interrupt
2606                  * from the last not overwritten vector (wptr + 16). Hopefully
2607                  * this should allow us to catchup.
2608                  */
2609                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2610                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2611                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2612                 tmp = RREG32(IH_RB_CNTL);
2613                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2614                 WREG32(IH_RB_CNTL, tmp);
2615         }
2616         return (wptr & rdev->ih.ptr_mask);
2617 }
2618
2619 int evergreen_irq_process(struct radeon_device *rdev)
2620 {
2621         u32 wptr = evergreen_get_ih_wptr(rdev);
2622         u32 rptr = rdev->ih.rptr;
2623         u32 src_id, src_data;
2624         u32 ring_index;
2625         unsigned long flags;
2626         bool queue_hotplug = false;
2627
2628         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2629         if (!rdev->ih.enabled)
2630                 return IRQ_NONE;
2631
2632         spin_lock_irqsave(&rdev->ih.lock, flags);
2633
2634         if (rptr == wptr) {
2635                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2636                 return IRQ_NONE;
2637         }
2638         if (rdev->shutdown) {
2639                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2640                 return IRQ_NONE;
2641         }
2642
2643 restart_ih:
2644         /* display interrupts */
2645         evergreen_irq_ack(rdev);
2646
2647         rdev->ih.wptr = wptr;
2648         while (rptr != wptr) {
2649                 /* wptr/rptr are in bytes! */
2650                 ring_index = rptr / 4;
2651                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2652                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2653
2654                 switch (src_id) {
2655                 case 1: /* D1 vblank/vline */
2656                         switch (src_data) {
2657                         case 0: /* D1 vblank */
2658                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2659                                         if (rdev->irq.crtc_vblank_int[0]) {
2660                                                 drm_handle_vblank(rdev->ddev, 0);
2661                                                 rdev->pm.vblank_sync = true;
2662                                                 wake_up(&rdev->irq.vblank_queue);
2663                                         }
2664                                         if (rdev->irq.pflip[0])
2665                                                 radeon_crtc_handle_flip(rdev, 0);
2666                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2667                                         DRM_DEBUG("IH: D1 vblank\n");
2668                                 }
2669                                 break;
2670                         case 1: /* D1 vline */
2671                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2672                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2673                                         DRM_DEBUG("IH: D1 vline\n");
2674                                 }
2675                                 break;
2676                         default:
2677                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2678                                 break;
2679                         }
2680                         break;
2681                 case 2: /* D2 vblank/vline */
2682                         switch (src_data) {
2683                         case 0: /* D2 vblank */
2684                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2685                                         if (rdev->irq.crtc_vblank_int[1]) {
2686                                                 drm_handle_vblank(rdev->ddev, 1);
2687                                                 rdev->pm.vblank_sync = true;
2688                                                 wake_up(&rdev->irq.vblank_queue);
2689                                         }
2690                                         if (rdev->irq.pflip[1])
2691                                                 radeon_crtc_handle_flip(rdev, 1);
2692                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2693                                         DRM_DEBUG("IH: D2 vblank\n");
2694                                 }
2695                                 break;
2696                         case 1: /* D2 vline */
2697                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2698                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2699                                         DRM_DEBUG("IH: D2 vline\n");
2700                                 }
2701                                 break;
2702                         default:
2703                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2704                                 break;
2705                         }
2706                         break;
2707                 case 3: /* D3 vblank/vline */
2708                         switch (src_data) {
2709                         case 0: /* D3 vblank */
2710                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2711                                         if (rdev->irq.crtc_vblank_int[2]) {
2712                                                 drm_handle_vblank(rdev->ddev, 2);
2713                                                 rdev->pm.vblank_sync = true;
2714                                                 wake_up(&rdev->irq.vblank_queue);
2715                                         }
2716                                         if (rdev->irq.pflip[2])
2717                                                 radeon_crtc_handle_flip(rdev, 2);
2718                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2719                                         DRM_DEBUG("IH: D3 vblank\n");
2720                                 }
2721                                 break;
2722                         case 1: /* D3 vline */
2723                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2724                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2725                                         DRM_DEBUG("IH: D3 vline\n");
2726                                 }
2727                                 break;
2728                         default:
2729                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2730                                 break;
2731                         }
2732                         break;
2733                 case 4: /* D4 vblank/vline */
2734                         switch (src_data) {
2735                         case 0: /* D4 vblank */
2736                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2737                                         if (rdev->irq.crtc_vblank_int[3]) {
2738                                                 drm_handle_vblank(rdev->ddev, 3);
2739                                                 rdev->pm.vblank_sync = true;
2740                                                 wake_up(&rdev->irq.vblank_queue);
2741                                         }
2742                                         if (rdev->irq.pflip[3])
2743                                                 radeon_crtc_handle_flip(rdev, 3);
2744                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2745                                         DRM_DEBUG("IH: D4 vblank\n");
2746                                 }
2747                                 break;
2748                         case 1: /* D4 vline */
2749                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2750                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2751                                         DRM_DEBUG("IH: D4 vline\n");
2752                                 }
2753                                 break;
2754                         default:
2755                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2756                                 break;
2757                         }
2758                         break;
2759                 case 5: /* D5 vblank/vline */
2760                         switch (src_data) {
2761                         case 0: /* D5 vblank */
2762                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2763                                         if (rdev->irq.crtc_vblank_int[4]) {
2764                                                 drm_handle_vblank(rdev->ddev, 4);
2765                                                 rdev->pm.vblank_sync = true;
2766                                                 wake_up(&rdev->irq.vblank_queue);
2767                                         }
2768                                         if (rdev->irq.pflip[4])
2769                                                 radeon_crtc_handle_flip(rdev, 4);
2770                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2771                                         DRM_DEBUG("IH: D5 vblank\n");
2772                                 }
2773                                 break;
2774                         case 1: /* D5 vline */
2775                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2776                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2777                                         DRM_DEBUG("IH: D5 vline\n");
2778                                 }
2779                                 break;
2780                         default:
2781                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2782                                 break;
2783                         }
2784                         break;
2785                 case 6: /* D6 vblank/vline */
2786                         switch (src_data) {
2787                         case 0: /* D6 vblank */
2788                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2789                                         if (rdev->irq.crtc_vblank_int[5]) {
2790                                                 drm_handle_vblank(rdev->ddev, 5);
2791                                                 rdev->pm.vblank_sync = true;
2792                                                 wake_up(&rdev->irq.vblank_queue);
2793                                         }
2794                                         if (rdev->irq.pflip[5])
2795                                                 radeon_crtc_handle_flip(rdev, 5);
2796                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2797                                         DRM_DEBUG("IH: D6 vblank\n");
2798                                 }
2799                                 break;
2800                         case 1: /* D6 vline */
2801                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2802                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2803                                         DRM_DEBUG("IH: D6 vline\n");
2804                                 }
2805                                 break;
2806                         default:
2807                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2808                                 break;
2809                         }
2810                         break;
2811                 case 42: /* HPD hotplug */
2812                         switch (src_data) {
2813                         case 0:
2814                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2815                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2816                                         queue_hotplug = true;
2817                                         DRM_DEBUG("IH: HPD1\n");
2818                                 }
2819                                 break;
2820                         case 1:
2821                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2822                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2823                                         queue_hotplug = true;
2824                                         DRM_DEBUG("IH: HPD2\n");
2825                                 }
2826                                 break;
2827                         case 2:
2828                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2829                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2830                                         queue_hotplug = true;
2831                                         DRM_DEBUG("IH: HPD3\n");
2832                                 }
2833                                 break;
2834                         case 3:
2835                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2836                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2837                                         queue_hotplug = true;
2838                                         DRM_DEBUG("IH: HPD4\n");
2839                                 }
2840                                 break;
2841                         case 4:
2842                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2843                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2844                                         queue_hotplug = true;
2845                                         DRM_DEBUG("IH: HPD5\n");
2846                                 }
2847                                 break;
2848                         case 5:
2849                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2850                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2851                                         queue_hotplug = true;
2852                                         DRM_DEBUG("IH: HPD6\n");
2853                                 }
2854                                 break;
2855                         default:
2856                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2857                                 break;
2858                         }
2859                         break;
2860                 case 176: /* CP_INT in ring buffer */
2861                 case 177: /* CP_INT in IB1 */
2862                 case 178: /* CP_INT in IB2 */
2863                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2864                         radeon_fence_process(rdev);
2865                         break;
2866                 case 181: /* CP EOP event */
2867                         DRM_DEBUG("IH: CP EOP\n");
2868                         radeon_fence_process(rdev);
2869                         break;
2870                 case 233: /* GUI IDLE */
2871                         DRM_DEBUG("IH: CP EOP\n");
2872                         rdev->pm.gui_idle = true;
2873                         wake_up(&rdev->irq.idle_queue);
2874                         break;
2875                 default:
2876                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2877                         break;
2878                 }
2879
2880                 /* wptr/rptr are in bytes! */
2881                 rptr += 16;
2882                 rptr &= rdev->ih.ptr_mask;
2883         }
2884         /* make sure wptr hasn't changed while processing */
2885         wptr = evergreen_get_ih_wptr(rdev);
2886         if (wptr != rdev->ih.wptr)
2887                 goto restart_ih;
2888         if (queue_hotplug)
2889                 schedule_work(&rdev->hotplug_work);
2890         rdev->ih.rptr = rptr;
2891         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2892         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2893         return IRQ_HANDLED;
2894 }
2895
2896 static int evergreen_startup(struct radeon_device *rdev)
2897 {
2898         int r;
2899
2900         /* enable pcie gen2 link */
2901         if (!ASIC_IS_DCE5(rdev))
2902                 evergreen_pcie_gen2_enable(rdev);
2903
2904         if (ASIC_IS_DCE5(rdev)) {
2905                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2906                         r = ni_init_microcode(rdev);
2907                         if (r) {
2908                                 DRM_ERROR("Failed to load firmware!\n");
2909                                 return r;
2910                         }
2911                 }
2912                 r = btc_mc_load_microcode(rdev);
2913                 if (r) {
2914                         DRM_ERROR("Failed to load MC firmware!\n");
2915                         return r;
2916                 }
2917         } else {
2918                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2919                         r = r600_init_microcode(rdev);
2920                         if (r) {
2921                                 DRM_ERROR("Failed to load firmware!\n");
2922                                 return r;
2923                         }
2924                 }
2925         }
2926
2927         evergreen_mc_program(rdev);
2928         if (rdev->flags & RADEON_IS_AGP) {
2929                 evergreen_agp_enable(rdev);
2930         } else {
2931                 r = evergreen_pcie_gart_enable(rdev);
2932                 if (r)
2933                         return r;
2934         }
2935         evergreen_gpu_init(rdev);
2936
2937         r = evergreen_blit_init(rdev);
2938         if (r) {
2939                 evergreen_blit_fini(rdev);
2940                 rdev->asic->copy = NULL;
2941                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2942         }
2943
2944         /* allocate wb buffer */
2945         r = radeon_wb_init(rdev);
2946         if (r)
2947                 return r;
2948
2949         /* Enable IRQ */
2950         r = r600_irq_init(rdev);
2951         if (r) {
2952                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2953                 radeon_irq_kms_fini(rdev);
2954                 return r;
2955         }
2956         evergreen_irq_set(rdev);
2957
2958         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2959         if (r)
2960                 return r;
2961         r = evergreen_cp_load_microcode(rdev);
2962         if (r)
2963                 return r;
2964         r = evergreen_cp_resume(rdev);
2965         if (r)
2966                 return r;
2967
2968         return 0;
2969 }
2970
2971 int evergreen_resume(struct radeon_device *rdev)
2972 {
2973         int r;
2974
2975         /* reset the asic, the gfx blocks are often in a bad state
2976          * after the driver is unloaded or after a resume
2977          */
2978         if (radeon_asic_reset(rdev))
2979                 dev_warn(rdev->dev, "GPU reset failed !\n");
2980         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2981          * posting will perform necessary task to bring back GPU into good
2982          * shape.
2983          */
2984         /* post card */
2985         atom_asic_init(rdev->mode_info.atom_context);
2986
2987         r = evergreen_startup(rdev);
2988         if (r) {
2989                 DRM_ERROR("r600 startup failed on resume\n");
2990                 return r;
2991         }
2992
2993         r = r600_ib_test(rdev);
2994         if (r) {
2995                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2996                 return r;
2997         }
2998
2999         return r;
3000
3001 }
3002
3003 int evergreen_suspend(struct radeon_device *rdev)
3004 {
3005         int r;
3006
3007         /* FIXME: we should wait for ring to be empty */
3008         r700_cp_stop(rdev);
3009         rdev->cp.ready = false;
3010         evergreen_irq_suspend(rdev);
3011         radeon_wb_disable(rdev);
3012         evergreen_pcie_gart_disable(rdev);
3013
3014         /* unpin shaders bo */
3015         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3016         if (likely(r == 0)) {
3017                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3018                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3019         }
3020
3021         return 0;
3022 }
3023
3024 int evergreen_copy_blit(struct radeon_device *rdev,
3025                         uint64_t src_offset, uint64_t dst_offset,
3026                         unsigned num_pages, struct radeon_fence *fence)
3027 {
3028         int r;
3029
3030         mutex_lock(&rdev->r600_blit.mutex);
3031         rdev->r600_blit.vb_ib = NULL;
3032         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
3033         if (r) {
3034                 if (rdev->r600_blit.vb_ib)
3035                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3036                 mutex_unlock(&rdev->r600_blit.mutex);
3037                 return r;
3038         }
3039         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3040         evergreen_blit_done_copy(rdev, fence);
3041         mutex_unlock(&rdev->r600_blit.mutex);
3042         return 0;
3043 }
3044
3045 /* Plan is to move initialization in that function and use
3046  * helper function so that radeon_device_init pretty much
3047  * do nothing more than calling asic specific function. This
3048  * should also allow to remove a bunch of callback function
3049  * like vram_info.
3050  */
3051 int evergreen_init(struct radeon_device *rdev)
3052 {
3053         int r;
3054
3055         r = radeon_dummy_page_init(rdev);
3056         if (r)
3057                 return r;
3058         /* This don't do much */
3059         r = radeon_gem_init(rdev);
3060         if (r)
3061                 return r;
3062         /* Read BIOS */
3063         if (!radeon_get_bios(rdev)) {
3064                 if (ASIC_IS_AVIVO(rdev))
3065                         return -EINVAL;
3066         }
3067         /* Must be an ATOMBIOS */
3068         if (!rdev->is_atom_bios) {
3069                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3070                 return -EINVAL;
3071         }
3072         r = radeon_atombios_init(rdev);
3073         if (r)
3074                 return r;
3075         /* reset the asic, the gfx blocks are often in a bad state
3076          * after the driver is unloaded or after a resume
3077          */
3078         if (radeon_asic_reset(rdev))
3079                 dev_warn(rdev->dev, "GPU reset failed !\n");
3080         /* Post card if necessary */
3081         if (!radeon_card_posted(rdev)) {
3082                 if (!rdev->bios) {
3083                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3084                         return -EINVAL;
3085                 }
3086                 DRM_INFO("GPU not posted. posting now...\n");
3087                 atom_asic_init(rdev->mode_info.atom_context);
3088         }
3089         /* Initialize scratch registers */
3090         r600_scratch_init(rdev);
3091         /* Initialize surface registers */
3092         radeon_surface_init(rdev);
3093         /* Initialize clocks */
3094         radeon_get_clock_info(rdev->ddev);
3095         /* Fence driver */
3096         r = radeon_fence_driver_init(rdev);
3097         if (r)
3098                 return r;
3099         /* initialize AGP */
3100         if (rdev->flags & RADEON_IS_AGP) {
3101                 r = radeon_agp_init(rdev);
3102                 if (r)
3103                         radeon_agp_disable(rdev);
3104         }
3105         /* initialize memory controller */
3106         r = evergreen_mc_init(rdev);
3107         if (r)
3108                 return r;
3109         /* Memory manager */
3110         r = radeon_bo_init(rdev);
3111         if (r)
3112                 return r;
3113
3114         r = radeon_irq_kms_init(rdev);
3115         if (r)
3116                 return r;
3117
3118         rdev->cp.ring_obj = NULL;
3119         r600_ring_init(rdev, 1024 * 1024);
3120
3121         rdev->ih.ring_obj = NULL;
3122         r600_ih_ring_init(rdev, 64 * 1024);
3123
3124         r = r600_pcie_gart_init(rdev);
3125         if (r)
3126                 return r;
3127
3128         rdev->accel_working = true;
3129         r = evergreen_startup(rdev);
3130         if (r) {
3131                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3132                 r700_cp_fini(rdev);
3133                 r600_irq_fini(rdev);
3134                 radeon_wb_fini(rdev);
3135                 radeon_irq_kms_fini(rdev);
3136                 evergreen_pcie_gart_fini(rdev);
3137                 rdev->accel_working = false;
3138         }
3139         if (rdev->accel_working) {
3140                 r = radeon_ib_pool_init(rdev);
3141                 if (r) {
3142                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3143                         rdev->accel_working = false;
3144                 }
3145                 r = r600_ib_test(rdev);
3146                 if (r) {
3147                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3148                         rdev->accel_working = false;
3149                 }
3150         }
3151         return 0;
3152 }
3153
3154 void evergreen_fini(struct radeon_device *rdev)
3155 {
3156         evergreen_blit_fini(rdev);
3157         r700_cp_fini(rdev);
3158         r600_irq_fini(rdev);
3159         radeon_wb_fini(rdev);
3160         radeon_irq_kms_fini(rdev);
3161         evergreen_pcie_gart_fini(rdev);
3162         radeon_gem_fini(rdev);
3163         radeon_fence_driver_fini(rdev);
3164         radeon_agp_fini(rdev);
3165         radeon_bo_fini(rdev);
3166         radeon_atombios_fini(rdev);
3167         kfree(rdev->bios);
3168         rdev->bios = NULL;
3169         radeon_dummy_page_fini(rdev);
3170 }
3171
3172 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3173 {
3174         u32 link_width_cntl, speed_cntl;
3175
3176         if (radeon_pcie_gen2 == 0)
3177                 return;
3178
3179         if (rdev->flags & RADEON_IS_IGP)
3180                 return;
3181
3182         if (!(rdev->flags & RADEON_IS_PCIE))
3183                 return;
3184
3185         /* x2 cards have a special sequence */
3186         if (ASIC_IS_X2(rdev))
3187                 return;
3188
3189         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3190         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3191             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3192
3193                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3194                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3195                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3196
3197                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3198                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3199                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3200
3201                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3202                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3203                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3204
3205                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3206                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3207                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3208
3209                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3210                 speed_cntl |= LC_GEN2_EN_STRAP;
3211                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3212
3213         } else {
3214                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3215                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3216                 if (1)
3217                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3218                 else
3219                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3220                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3221         }
3222 }