2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
44 #include <asm/system.h>
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
53 #define DESCRIPTOR_OUTPUT_MORE 0
54 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST (3 << 12)
57 #define DESCRIPTOR_STATUS (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59 #define DESCRIPTOR_PING (1 << 7)
60 #define DESCRIPTOR_YY (1 << 6)
61 #define DESCRIPTOR_NO_IRQ (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65 #define DESCRIPTOR_WAIT (3 << 0)
71 __le32 branch_address;
73 __le16 transfer_status;
74 } __attribute__((aligned(16)));
76 struct db_descriptor {
79 __le16 second_req_count;
80 __le16 first_req_count;
81 __le32 branch_address;
82 __le16 second_res_count;
83 __le16 first_res_count;
88 } __attribute__((aligned(16)));
90 #define CONTROL_SET(regs) (regs)
91 #define CONTROL_CLEAR(regs) ((regs) + 4)
92 #define COMMAND_PTR(regs) ((regs) + 12)
93 #define CONTEXT_MATCH(regs) ((regs) + 16)
96 struct descriptor descriptor;
97 struct ar_buffer *next;
102 struct fw_ohci *ohci;
103 struct ar_buffer *current_buffer;
104 struct ar_buffer *last_buffer;
107 struct tasklet_struct tasklet;
112 typedef int (*descriptor_callback_t)(struct context *ctx,
113 struct descriptor *d,
114 struct descriptor *last);
117 * A buffer that contains a block of DMA-able coherent memory used for
118 * storing a portion of a DMA descriptor program.
120 struct descriptor_buffer {
121 struct list_head list;
122 dma_addr_t buffer_bus;
125 struct descriptor buffer[0];
129 struct fw_ohci *ohci;
131 int total_allocation;
134 * List of page-sized buffers for storing DMA descriptors.
135 * Head of list contains buffers in use and tail of list contains
138 struct list_head buffer_list;
141 * Pointer to a buffer inside buffer_list that contains the tail
142 * end of the current DMA program.
144 struct descriptor_buffer *buffer_tail;
147 * The descriptor containing the branch address of the first
148 * descriptor that has not yet been filled by the device.
150 struct descriptor *last;
153 * The last descriptor in the DMA program. It contains the branch
154 * address that must be updated upon appending a new descriptor.
156 struct descriptor *prev;
158 descriptor_callback_t callback;
160 struct tasklet_struct tasklet;
163 #define IT_HEADER_SY(v) ((v) << 0)
164 #define IT_HEADER_TCODE(v) ((v) << 4)
165 #define IT_HEADER_CHANNEL(v) ((v) << 8)
166 #define IT_HEADER_TAG(v) ((v) << 14)
167 #define IT_HEADER_SPEED(v) ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
171 struct fw_iso_context base;
172 struct context context;
175 size_t header_length;
178 #define CONFIG_ROM_SIZE 1024
183 __iomem char *registers;
184 dma_addr_t self_id_bus;
186 struct tasklet_struct bus_reset_tasklet;
189 int request_generation; /* for timestamping incoming requests */
190 atomic_t bus_seconds;
194 bool bus_reset_packet_quirk;
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
201 u32 self_id_buffer[512];
203 /* Config rom buffers */
205 dma_addr_t config_rom_bus;
206 __be32 *next_config_rom;
207 dma_addr_t next_config_rom_bus;
210 struct ar_context ar_request_ctx;
211 struct ar_context ar_response_ctx;
212 struct context at_request_ctx;
213 struct context at_response_ctx;
216 struct iso_context *it_context_list;
217 u64 ir_context_channels;
219 struct iso_context *ir_context_list;
222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
224 return container_of(card, struct fw_ohci, card);
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228 #define IR_CONTEXT_BUFFER_FILL 0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
234 #define CONTEXT_RUN 0x8000
235 #define CONTEXT_WAKE 0x1000
236 #define CONTEXT_DEAD 0x0800
237 #define CONTEXT_ACTIVE 0x0400
239 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
243 #define OHCI1394_REGISTER_SIZE 0x800
244 #define OHCI_LOOP_COUNT 500
245 #define OHCI1394_PCI_HCI_Control 0x40
246 #define SELF_ID_BUF_SIZE 0x800
247 #define OHCI_TCODE_PHY_PACKET 0x0e
248 #define OHCI_VERSION_1_1 0x010010
250 static char ohci_driver_name[] = KBUILD_MODNAME;
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
254 #define OHCI_PARAM_DEBUG_AT_AR 1
255 #define OHCI_PARAM_DEBUG_SELFIDS 2
256 #define OHCI_PARAM_DEBUG_IRQS 4
257 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
259 static int param_debug;
260 module_param_named(debug, param_debug, int, 0644);
261 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
262 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
263 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
264 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
265 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266 ", or a combination, or all = -1)");
268 static void log_irqs(u32 evt)
270 if (likely(!(param_debug &
271 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
274 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
275 !(evt & OHCI1394_busReset))
278 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279 evt & OHCI1394_selfIDComplete ? " selfID" : "",
280 evt & OHCI1394_RQPkt ? " AR_req" : "",
281 evt & OHCI1394_RSPkt ? " AR_resp" : "",
282 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
283 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
284 evt & OHCI1394_isochRx ? " IR" : "",
285 evt & OHCI1394_isochTx ? " IT" : "",
286 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
287 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
288 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
289 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
290 evt & OHCI1394_busReset ? " busReset" : "",
291 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
292 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
293 OHCI1394_respTxComplete | OHCI1394_isochRx |
294 OHCI1394_isochTx | OHCI1394_postedWriteErr |
295 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
296 OHCI1394_regAccessFail | OHCI1394_busReset)
300 static const char *speed[] = {
301 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
303 static const char *power[] = {
304 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
305 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
307 static const char port[] = { '.', '-', 'p', 'c', };
309 static char _p(u32 *s, int shift)
311 return port[*s >> shift & 3];
314 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
316 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
319 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
320 self_id_count, generation, node_id);
322 for (; self_id_count--; ++s)
323 if ((*s & 1 << 23) == 0)
324 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
325 "%s gc=%d %s %s%s%s\n",
326 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
327 speed[*s >> 14 & 3], *s >> 16 & 63,
328 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
329 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
331 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
333 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
334 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
337 static const char *evts[] = {
338 [0x00] = "evt_no_status", [0x01] = "-reserved-",
339 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
340 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
341 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
342 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
343 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
344 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
345 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
346 [0x10] = "-reserved-", [0x11] = "ack_complete",
347 [0x12] = "ack_pending ", [0x13] = "-reserved-",
348 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
349 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
350 [0x18] = "-reserved-", [0x19] = "-reserved-",
351 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
352 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
353 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
354 [0x20] = "pending/cancelled",
356 static const char *tcodes[] = {
357 [0x0] = "QW req", [0x1] = "BW req",
358 [0x2] = "W resp", [0x3] = "-reserved-",
359 [0x4] = "QR req", [0x5] = "BR req",
360 [0x6] = "QR resp", [0x7] = "BR resp",
361 [0x8] = "cycle start", [0x9] = "Lk req",
362 [0xa] = "async stream packet", [0xb] = "Lk resp",
363 [0xc] = "-reserved-", [0xd] = "-reserved-",
364 [0xe] = "link internal", [0xf] = "-reserved-",
366 static const char *phys[] = {
367 [0x0] = "phy config packet", [0x1] = "link-on packet",
368 [0x2] = "self-id packet", [0x3] = "-reserved-",
371 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
373 int tcode = header[0] >> 4 & 0xf;
376 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
379 if (unlikely(evt >= ARRAY_SIZE(evts)))
382 if (evt == OHCI1394_evt_bus_reset) {
383 fw_notify("A%c evt_bus_reset, generation %d\n",
384 dir, (header[2] >> 16) & 0xff);
388 if (header[0] == ~header[1]) {
389 fw_notify("A%c %s, %s, %08x\n",
390 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
395 case 0x0: case 0x6: case 0x8:
396 snprintf(specific, sizeof(specific), " = %08x",
397 be32_to_cpu((__force __be32)header[3]));
399 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
400 snprintf(specific, sizeof(specific), " %x,%x",
401 header[3] >> 16, header[3] & 0xffff);
409 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
411 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
412 fw_notify("A%c spd %x tl %02x, "
415 dir, speed, header[0] >> 10 & 0x3f,
416 header[1] >> 16, header[0] >> 16, evts[evt],
417 tcodes[tcode], header[1] & 0xffff, header[2], specific);
420 fw_notify("A%c spd %x tl %02x, "
423 dir, speed, header[0] >> 10 & 0x3f,
424 header[1] >> 16, header[0] >> 16, evts[evt],
425 tcodes[tcode], specific);
431 #define log_irqs(evt)
432 #define log_selfids(node_id, generation, self_id_count, sid)
433 #define log_ar_at_event(dir, speed, header, evt)
435 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
437 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
439 writel(data, ohci->registers + offset);
442 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
444 return readl(ohci->registers + offset);
447 static inline void flush_writes(const struct fw_ohci *ohci)
449 /* Do a dummy read to flush writes. */
450 reg_read(ohci, OHCI1394_Version);
453 static int ohci_update_phy_reg(struct fw_card *card, int addr,
454 int clear_bits, int set_bits)
456 struct fw_ohci *ohci = fw_ohci(card);
459 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
462 val = reg_read(ohci, OHCI1394_PhyControl);
463 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
464 fw_error("failed to set phy reg bits.\n");
468 old = OHCI1394_PhyControl_ReadData(val);
469 old = (old & ~clear_bits) | set_bits;
470 reg_write(ohci, OHCI1394_PhyControl,
471 OHCI1394_PhyControl_Write(addr, old));
476 static int ar_context_add_page(struct ar_context *ctx)
478 struct device *dev = ctx->ohci->card.device;
479 struct ar_buffer *ab;
480 dma_addr_t uninitialized_var(ab_bus);
483 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
488 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
489 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
491 DESCRIPTOR_BRANCH_ALWAYS);
492 offset = offsetof(struct ar_buffer, data);
493 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
494 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
495 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
496 ab->descriptor.branch_address = 0;
498 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
499 ctx->last_buffer->next = ab;
500 ctx->last_buffer = ab;
502 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
503 flush_writes(ctx->ohci);
508 static void ar_context_release(struct ar_context *ctx)
510 struct ar_buffer *ab, *ab_next;
514 for (ab = ctx->current_buffer; ab; ab = ab_next) {
516 offset = offsetof(struct ar_buffer, data);
517 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
518 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
523 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
524 #define cond_le32_to_cpu(v) \
525 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
527 #define cond_le32_to_cpu(v) le32_to_cpu(v)
530 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
532 struct fw_ohci *ohci = ctx->ohci;
534 u32 status, length, tcode;
537 p.header[0] = cond_le32_to_cpu(buffer[0]);
538 p.header[1] = cond_le32_to_cpu(buffer[1]);
539 p.header[2] = cond_le32_to_cpu(buffer[2]);
541 tcode = (p.header[0] >> 4) & 0x0f;
543 case TCODE_WRITE_QUADLET_REQUEST:
544 case TCODE_READ_QUADLET_RESPONSE:
545 p.header[3] = (__force __u32) buffer[3];
546 p.header_length = 16;
547 p.payload_length = 0;
550 case TCODE_READ_BLOCK_REQUEST :
551 p.header[3] = cond_le32_to_cpu(buffer[3]);
552 p.header_length = 16;
553 p.payload_length = 0;
556 case TCODE_WRITE_BLOCK_REQUEST:
557 case TCODE_READ_BLOCK_RESPONSE:
558 case TCODE_LOCK_REQUEST:
559 case TCODE_LOCK_RESPONSE:
560 p.header[3] = cond_le32_to_cpu(buffer[3]);
561 p.header_length = 16;
562 p.payload_length = p.header[3] >> 16;
565 case TCODE_WRITE_RESPONSE:
566 case TCODE_READ_QUADLET_REQUEST:
567 case OHCI_TCODE_PHY_PACKET:
568 p.header_length = 12;
569 p.payload_length = 0;
573 /* FIXME: Stop context, discard everything, and restart? */
575 p.payload_length = 0;
578 p.payload = (void *) buffer + p.header_length;
580 /* FIXME: What to do about evt_* errors? */
581 length = (p.header_length + p.payload_length + 3) / 4;
582 status = cond_le32_to_cpu(buffer[length]);
583 evt = (status >> 16) & 0x1f;
586 p.speed = (status >> 21) & 0x7;
587 p.timestamp = status & 0xffff;
588 p.generation = ohci->request_generation;
590 log_ar_at_event('R', p.speed, p.header, evt);
593 * The OHCI bus reset handler synthesizes a phy packet with
594 * the new generation number when a bus reset happens (see
595 * section 8.4.2.3). This helps us determine when a request
596 * was received and make sure we send the response in the same
597 * generation. We only need this for requests; for responses
598 * we use the unique tlabel for finding the matching
601 * Alas some chips sometimes emit bus reset packets with a
602 * wrong generation. We set the correct generation for these
603 * at a slightly incorrect time (in bus_reset_tasklet).
605 if (evt == OHCI1394_evt_bus_reset) {
606 if (!ohci->bus_reset_packet_quirk)
607 ohci->request_generation = (p.header[2] >> 16) & 0xff;
608 } else if (ctx == &ohci->ar_request_ctx) {
609 fw_core_handle_request(&ohci->card, &p);
611 fw_core_handle_response(&ohci->card, &p);
614 return buffer + length + 1;
617 static void ar_context_tasklet(unsigned long data)
619 struct ar_context *ctx = (struct ar_context *)data;
620 struct fw_ohci *ohci = ctx->ohci;
621 struct ar_buffer *ab;
622 struct descriptor *d;
625 ab = ctx->current_buffer;
628 if (d->res_count == 0) {
629 size_t size, rest, offset;
630 dma_addr_t start_bus;
634 * This descriptor is finished and we may have a
635 * packet split across this and the next buffer. We
636 * reuse the page for reassembling the split packet.
639 offset = offsetof(struct ar_buffer, data);
641 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
645 size = buffer + PAGE_SIZE - ctx->pointer;
646 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
647 memmove(buffer, ctx->pointer, size);
648 memcpy(buffer + size, ab->data, rest);
649 ctx->current_buffer = ab;
650 ctx->pointer = (void *) ab->data + rest;
651 end = buffer + size + rest;
654 buffer = handle_ar_packet(ctx, buffer);
656 dma_free_coherent(ohci->card.device, PAGE_SIZE,
658 ar_context_add_page(ctx);
660 buffer = ctx->pointer;
662 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
665 buffer = handle_ar_packet(ctx, buffer);
669 static int ar_context_init(struct ar_context *ctx,
670 struct fw_ohci *ohci, u32 regs)
676 ctx->last_buffer = &ab;
677 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
679 ar_context_add_page(ctx);
680 ar_context_add_page(ctx);
681 ctx->current_buffer = ab.next;
682 ctx->pointer = ctx->current_buffer->data;
687 static void ar_context_run(struct ar_context *ctx)
689 struct ar_buffer *ab = ctx->current_buffer;
693 offset = offsetof(struct ar_buffer, data);
694 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
696 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
697 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
698 flush_writes(ctx->ohci);
701 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
705 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
706 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
708 /* figure out which descriptor the branch address goes in */
709 if (z == 2 && (b == 3 || key == 2))
715 static void context_tasklet(unsigned long data)
717 struct context *ctx = (struct context *) data;
718 struct descriptor *d, *last;
721 struct descriptor_buffer *desc;
723 desc = list_entry(ctx->buffer_list.next,
724 struct descriptor_buffer, list);
726 while (last->branch_address != 0) {
727 struct descriptor_buffer *old_desc = desc;
728 address = le32_to_cpu(last->branch_address);
732 /* If the branch address points to a buffer outside of the
733 * current buffer, advance to the next buffer. */
734 if (address < desc->buffer_bus ||
735 address >= desc->buffer_bus + desc->used)
736 desc = list_entry(desc->list.next,
737 struct descriptor_buffer, list);
738 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
739 last = find_branch_descriptor(d, z);
741 if (!ctx->callback(ctx, d, last))
744 if (old_desc != desc) {
745 /* If we've advanced to the next buffer, move the
746 * previous buffer to the free list. */
749 spin_lock_irqsave(&ctx->ohci->lock, flags);
750 list_move_tail(&old_desc->list, &ctx->buffer_list);
751 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
758 * Allocate a new buffer and add it to the list of free buffers for this
759 * context. Must be called with ohci->lock held.
761 static int context_add_buffer(struct context *ctx)
763 struct descriptor_buffer *desc;
764 dma_addr_t uninitialized_var(bus_addr);
768 * 16MB of descriptors should be far more than enough for any DMA
769 * program. This will catch run-away userspace or DoS attacks.
771 if (ctx->total_allocation >= 16*1024*1024)
774 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
775 &bus_addr, GFP_ATOMIC);
779 offset = (void *)&desc->buffer - (void *)desc;
780 desc->buffer_size = PAGE_SIZE - offset;
781 desc->buffer_bus = bus_addr + offset;
784 list_add_tail(&desc->list, &ctx->buffer_list);
785 ctx->total_allocation += PAGE_SIZE;
790 static int context_init(struct context *ctx, struct fw_ohci *ohci,
791 u32 regs, descriptor_callback_t callback)
795 ctx->total_allocation = 0;
797 INIT_LIST_HEAD(&ctx->buffer_list);
798 if (context_add_buffer(ctx) < 0)
801 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
802 struct descriptor_buffer, list);
804 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
805 ctx->callback = callback;
808 * We put a dummy descriptor in the buffer that has a NULL
809 * branch address and looks like it's been sent. That way we
810 * have a descriptor to append DMA programs to.
812 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
813 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
814 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
815 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
816 ctx->last = ctx->buffer_tail->buffer;
817 ctx->prev = ctx->buffer_tail->buffer;
822 static void context_release(struct context *ctx)
824 struct fw_card *card = &ctx->ohci->card;
825 struct descriptor_buffer *desc, *tmp;
827 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
828 dma_free_coherent(card->device, PAGE_SIZE, desc,
830 ((void *)&desc->buffer - (void *)desc));
833 /* Must be called with ohci->lock held */
834 static struct descriptor *context_get_descriptors(struct context *ctx,
835 int z, dma_addr_t *d_bus)
837 struct descriptor *d = NULL;
838 struct descriptor_buffer *desc = ctx->buffer_tail;
840 if (z * sizeof(*d) > desc->buffer_size)
843 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
844 /* No room for the descriptor in this buffer, so advance to the
847 if (desc->list.next == &ctx->buffer_list) {
848 /* If there is no free buffer next in the list,
850 if (context_add_buffer(ctx) < 0)
853 desc = list_entry(desc->list.next,
854 struct descriptor_buffer, list);
855 ctx->buffer_tail = desc;
858 d = desc->buffer + desc->used / sizeof(*d);
859 memset(d, 0, z * sizeof(*d));
860 *d_bus = desc->buffer_bus + desc->used;
865 static void context_run(struct context *ctx, u32 extra)
867 struct fw_ohci *ohci = ctx->ohci;
869 reg_write(ohci, COMMAND_PTR(ctx->regs),
870 le32_to_cpu(ctx->last->branch_address));
871 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
872 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
876 static void context_append(struct context *ctx,
877 struct descriptor *d, int z, int extra)
880 struct descriptor_buffer *desc = ctx->buffer_tail;
882 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
884 desc->used += (z + extra) * sizeof(*d);
885 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
886 ctx->prev = find_branch_descriptor(d, z);
888 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
889 flush_writes(ctx->ohci);
892 static void context_stop(struct context *ctx)
897 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
898 flush_writes(ctx->ohci);
900 for (i = 0; i < 10; i++) {
901 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
902 if ((reg & CONTEXT_ACTIVE) == 0)
907 fw_error("Error: DMA context still active (0x%08x)\n", reg);
911 struct fw_packet *packet;
915 * This function apppends a packet to the DMA queue for transmission.
916 * Must always be called with the ochi->lock held to ensure proper
917 * generation handling and locking around packet queue manipulation.
919 static int at_context_queue_packet(struct context *ctx,
920 struct fw_packet *packet)
922 struct fw_ohci *ohci = ctx->ohci;
923 dma_addr_t d_bus, uninitialized_var(payload_bus);
924 struct driver_data *driver_data;
925 struct descriptor *d, *last;
930 d = context_get_descriptors(ctx, 4, &d_bus);
932 packet->ack = RCODE_SEND_ERROR;
936 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
937 d[0].res_count = cpu_to_le16(packet->timestamp);
940 * The DMA format for asyncronous link packets is different
941 * from the IEEE1394 layout, so shift the fields around
942 * accordingly. If header_length is 8, it's a PHY packet, to
943 * which we need to prepend an extra quadlet.
946 header = (__le32 *) &d[1];
947 switch (packet->header_length) {
950 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
951 (packet->speed << 16));
952 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
953 (packet->header[0] & 0xffff0000));
954 header[2] = cpu_to_le32(packet->header[2]);
956 tcode = (packet->header[0] >> 4) & 0x0f;
957 if (TCODE_IS_BLOCK_PACKET(tcode))
958 header[3] = cpu_to_le32(packet->header[3]);
960 header[3] = (__force __le32) packet->header[3];
962 d[0].req_count = cpu_to_le16(packet->header_length);
966 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
967 (packet->speed << 16));
968 header[1] = cpu_to_le32(packet->header[0]);
969 header[2] = cpu_to_le32(packet->header[1]);
970 d[0].req_count = cpu_to_le16(12);
974 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
975 (packet->speed << 16));
976 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
977 d[0].req_count = cpu_to_le16(8);
982 packet->ack = RCODE_SEND_ERROR;
986 driver_data = (struct driver_data *) &d[3];
987 driver_data->packet = packet;
988 packet->driver_data = driver_data;
990 if (packet->payload_length > 0) {
992 dma_map_single(ohci->card.device, packet->payload,
993 packet->payload_length, DMA_TO_DEVICE);
994 if (dma_mapping_error(ohci->card.device, payload_bus)) {
995 packet->ack = RCODE_SEND_ERROR;
998 packet->payload_bus = payload_bus;
1000 d[2].req_count = cpu_to_le16(packet->payload_length);
1001 d[2].data_address = cpu_to_le32(payload_bus);
1009 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1010 DESCRIPTOR_IRQ_ALWAYS |
1011 DESCRIPTOR_BRANCH_ALWAYS);
1014 * If the controller and packet generations don't match, we need to
1015 * bail out and try again. If IntEvent.busReset is set, the AT context
1016 * is halted, so appending to the context and trying to run it is
1017 * futile. Most controllers do the right thing and just flush the AT
1018 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1019 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1020 * up stalling out. So we just bail out in software and try again
1021 * later, and everyone is happy.
1022 * FIXME: Document how the locking works.
1024 if (ohci->generation != packet->generation ||
1025 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1026 if (packet->payload_length > 0)
1027 dma_unmap_single(ohci->card.device, payload_bus,
1028 packet->payload_length, DMA_TO_DEVICE);
1029 packet->ack = RCODE_GENERATION;
1033 context_append(ctx, d, z, 4 - z);
1035 /* If the context isn't already running, start it up. */
1036 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1037 if ((reg & CONTEXT_RUN) == 0)
1038 context_run(ctx, 0);
1043 static int handle_at_packet(struct context *context,
1044 struct descriptor *d,
1045 struct descriptor *last)
1047 struct driver_data *driver_data;
1048 struct fw_packet *packet;
1049 struct fw_ohci *ohci = context->ohci;
1052 if (last->transfer_status == 0)
1053 /* This descriptor isn't done yet, stop iteration. */
1056 driver_data = (struct driver_data *) &d[3];
1057 packet = driver_data->packet;
1059 /* This packet was cancelled, just continue. */
1062 if (packet->payload_bus)
1063 dma_unmap_single(ohci->card.device, packet->payload_bus,
1064 packet->payload_length, DMA_TO_DEVICE);
1066 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1067 packet->timestamp = le16_to_cpu(last->res_count);
1069 log_ar_at_event('T', packet->speed, packet->header, evt);
1072 case OHCI1394_evt_timeout:
1073 /* Async response transmit timed out. */
1074 packet->ack = RCODE_CANCELLED;
1077 case OHCI1394_evt_flushed:
1079 * The packet was flushed should give same error as
1080 * when we try to use a stale generation count.
1082 packet->ack = RCODE_GENERATION;
1085 case OHCI1394_evt_missing_ack:
1087 * Using a valid (current) generation count, but the
1088 * node is not on the bus or not sending acks.
1090 packet->ack = RCODE_NO_ACK;
1093 case ACK_COMPLETE + 0x10:
1094 case ACK_PENDING + 0x10:
1095 case ACK_BUSY_X + 0x10:
1096 case ACK_BUSY_A + 0x10:
1097 case ACK_BUSY_B + 0x10:
1098 case ACK_DATA_ERROR + 0x10:
1099 case ACK_TYPE_ERROR + 0x10:
1100 packet->ack = evt - 0x10;
1104 packet->ack = RCODE_SEND_ERROR;
1108 packet->callback(packet, &ohci->card, packet->ack);
1113 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1114 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1115 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1116 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1117 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1119 static void handle_local_rom(struct fw_ohci *ohci,
1120 struct fw_packet *packet, u32 csr)
1122 struct fw_packet response;
1123 int tcode, length, i;
1125 tcode = HEADER_GET_TCODE(packet->header[0]);
1126 if (TCODE_IS_BLOCK_PACKET(tcode))
1127 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1131 i = csr - CSR_CONFIG_ROM;
1132 if (i + length > CONFIG_ROM_SIZE) {
1133 fw_fill_response(&response, packet->header,
1134 RCODE_ADDRESS_ERROR, NULL, 0);
1135 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1136 fw_fill_response(&response, packet->header,
1137 RCODE_TYPE_ERROR, NULL, 0);
1139 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1140 (void *) ohci->config_rom + i, length);
1143 fw_core_handle_response(&ohci->card, &response);
1146 static void handle_local_lock(struct fw_ohci *ohci,
1147 struct fw_packet *packet, u32 csr)
1149 struct fw_packet response;
1150 int tcode, length, ext_tcode, sel;
1151 __be32 *payload, lock_old;
1152 u32 lock_arg, lock_data;
1154 tcode = HEADER_GET_TCODE(packet->header[0]);
1155 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1156 payload = packet->payload;
1157 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1159 if (tcode == TCODE_LOCK_REQUEST &&
1160 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1161 lock_arg = be32_to_cpu(payload[0]);
1162 lock_data = be32_to_cpu(payload[1]);
1163 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1167 fw_fill_response(&response, packet->header,
1168 RCODE_TYPE_ERROR, NULL, 0);
1172 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1173 reg_write(ohci, OHCI1394_CSRData, lock_data);
1174 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1175 reg_write(ohci, OHCI1394_CSRControl, sel);
1177 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1178 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1180 fw_notify("swap not done yet\n");
1182 fw_fill_response(&response, packet->header,
1183 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1185 fw_core_handle_response(&ohci->card, &response);
1188 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1193 if (ctx == &ctx->ohci->at_request_ctx) {
1194 packet->ack = ACK_PENDING;
1195 packet->callback(packet, &ctx->ohci->card, packet->ack);
1199 ((unsigned long long)
1200 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1202 csr = offset - CSR_REGISTER_BASE;
1204 /* Handle config rom reads. */
1205 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1206 handle_local_rom(ctx->ohci, packet, csr);
1208 case CSR_BUS_MANAGER_ID:
1209 case CSR_BANDWIDTH_AVAILABLE:
1210 case CSR_CHANNELS_AVAILABLE_HI:
1211 case CSR_CHANNELS_AVAILABLE_LO:
1212 handle_local_lock(ctx->ohci, packet, csr);
1215 if (ctx == &ctx->ohci->at_request_ctx)
1216 fw_core_handle_request(&ctx->ohci->card, packet);
1218 fw_core_handle_response(&ctx->ohci->card, packet);
1222 if (ctx == &ctx->ohci->at_response_ctx) {
1223 packet->ack = ACK_COMPLETE;
1224 packet->callback(packet, &ctx->ohci->card, packet->ack);
1228 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1230 unsigned long flags;
1233 spin_lock_irqsave(&ctx->ohci->lock, flags);
1235 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1236 ctx->ohci->generation == packet->generation) {
1237 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1238 handle_local_request(ctx, packet);
1242 ret = at_context_queue_packet(ctx, packet);
1243 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1246 packet->callback(packet, &ctx->ohci->card, packet->ack);
1250 static void bus_reset_tasklet(unsigned long data)
1252 struct fw_ohci *ohci = (struct fw_ohci *)data;
1253 int self_id_count, i, j, reg;
1254 int generation, new_generation;
1255 unsigned long flags;
1256 void *free_rom = NULL;
1257 dma_addr_t free_rom_bus = 0;
1259 reg = reg_read(ohci, OHCI1394_NodeID);
1260 if (!(reg & OHCI1394_NodeID_idValid)) {
1261 fw_notify("node ID not valid, new bus reset in progress\n");
1264 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1265 fw_notify("malconfigured bus\n");
1268 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1269 OHCI1394_NodeID_nodeNumber);
1271 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1272 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1273 fw_notify("inconsistent self IDs\n");
1277 * The count in the SelfIDCount register is the number of
1278 * bytes in the self ID receive buffer. Since we also receive
1279 * the inverted quadlets and a header quadlet, we shift one
1280 * bit extra to get the actual number of self IDs.
1282 self_id_count = (reg >> 3) & 0xff;
1283 if (self_id_count == 0 || self_id_count > 252) {
1284 fw_notify("inconsistent self IDs\n");
1287 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1290 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1291 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1292 fw_notify("inconsistent self IDs\n");
1295 ohci->self_id_buffer[j] =
1296 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1301 * Check the consistency of the self IDs we just read. The
1302 * problem we face is that a new bus reset can start while we
1303 * read out the self IDs from the DMA buffer. If this happens,
1304 * the DMA buffer will be overwritten with new self IDs and we
1305 * will read out inconsistent data. The OHCI specification
1306 * (section 11.2) recommends a technique similar to
1307 * linux/seqlock.h, where we remember the generation of the
1308 * self IDs in the buffer before reading them out and compare
1309 * it to the current generation after reading them out. If
1310 * the two generations match we know we have a consistent set
1314 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1315 if (new_generation != generation) {
1316 fw_notify("recursive bus reset detected, "
1317 "discarding self ids\n");
1321 /* FIXME: Document how the locking works. */
1322 spin_lock_irqsave(&ohci->lock, flags);
1324 ohci->generation = generation;
1325 context_stop(&ohci->at_request_ctx);
1326 context_stop(&ohci->at_response_ctx);
1327 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1329 if (ohci->bus_reset_packet_quirk)
1330 ohci->request_generation = generation;
1333 * This next bit is unrelated to the AT context stuff but we
1334 * have to do it under the spinlock also. If a new config rom
1335 * was set up before this reset, the old one is now no longer
1336 * in use and we can free it. Update the config rom pointers
1337 * to point to the current config rom and clear the
1338 * next_config_rom pointer so a new udpate can take place.
1341 if (ohci->next_config_rom != NULL) {
1342 if (ohci->next_config_rom != ohci->config_rom) {
1343 free_rom = ohci->config_rom;
1344 free_rom_bus = ohci->config_rom_bus;
1346 ohci->config_rom = ohci->next_config_rom;
1347 ohci->config_rom_bus = ohci->next_config_rom_bus;
1348 ohci->next_config_rom = NULL;
1351 * Restore config_rom image and manually update
1352 * config_rom registers. Writing the header quadlet
1353 * will indicate that the config rom is ready, so we
1356 reg_write(ohci, OHCI1394_BusOptions,
1357 be32_to_cpu(ohci->config_rom[2]));
1358 ohci->config_rom[0] = ohci->next_header;
1359 reg_write(ohci, OHCI1394_ConfigROMhdr,
1360 be32_to_cpu(ohci->next_header));
1363 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1364 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1365 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1368 spin_unlock_irqrestore(&ohci->lock, flags);
1371 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1372 free_rom, free_rom_bus);
1374 log_selfids(ohci->node_id, generation,
1375 self_id_count, ohci->self_id_buffer);
1377 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1378 self_id_count, ohci->self_id_buffer);
1381 static irqreturn_t irq_handler(int irq, void *data)
1383 struct fw_ohci *ohci = data;
1384 u32 event, iso_event, cycle_time;
1387 event = reg_read(ohci, OHCI1394_IntEventClear);
1389 if (!event || !~event)
1392 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1393 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1396 if (event & OHCI1394_selfIDComplete)
1397 tasklet_schedule(&ohci->bus_reset_tasklet);
1399 if (event & OHCI1394_RQPkt)
1400 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1402 if (event & OHCI1394_RSPkt)
1403 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1405 if (event & OHCI1394_reqTxComplete)
1406 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1408 if (event & OHCI1394_respTxComplete)
1409 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1411 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1412 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1415 i = ffs(iso_event) - 1;
1416 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1417 iso_event &= ~(1 << i);
1420 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1421 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1424 i = ffs(iso_event) - 1;
1425 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1426 iso_event &= ~(1 << i);
1429 if (unlikely(event & OHCI1394_regAccessFail))
1430 fw_error("Register access failure - "
1431 "please notify linux1394-devel@lists.sf.net\n");
1433 if (unlikely(event & OHCI1394_postedWriteErr))
1434 fw_error("PCI posted write error\n");
1436 if (unlikely(event & OHCI1394_cycleTooLong)) {
1437 if (printk_ratelimit())
1438 fw_notify("isochronous cycle too long\n");
1439 reg_write(ohci, OHCI1394_LinkControlSet,
1440 OHCI1394_LinkControl_cycleMaster);
1443 if (event & OHCI1394_cycle64Seconds) {
1444 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1445 if ((cycle_time & 0x80000000) == 0)
1446 atomic_inc(&ohci->bus_seconds);
1452 static int software_reset(struct fw_ohci *ohci)
1456 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1458 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1459 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1460 OHCI1394_HCControl_softReset) == 0)
1468 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1470 size_t size = length * 4;
1472 memcpy(dest, src, size);
1473 if (size < CONFIG_ROM_SIZE)
1474 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1477 static int ohci_enable(struct fw_card *card,
1478 const __be32 *config_rom, size_t length)
1480 struct fw_ohci *ohci = fw_ohci(card);
1481 struct pci_dev *dev = to_pci_dev(card->device);
1485 if (software_reset(ohci)) {
1486 fw_error("Failed to reset ohci card.\n");
1491 * Now enable LPS, which we need in order to start accessing
1492 * most of the registers. In fact, on some cards (ALI M5251),
1493 * accessing registers in the SClk domain without LPS enabled
1494 * will lock up the machine. Wait 50msec to make sure we have
1495 * full link enabled. However, with some cards (well, at least
1496 * a JMicron PCIe card), we have to try again sometimes.
1498 reg_write(ohci, OHCI1394_HCControlSet,
1499 OHCI1394_HCControl_LPS |
1500 OHCI1394_HCControl_postedWriteEnable);
1503 for (lps = 0, i = 0; !lps && i < 3; i++) {
1505 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1506 OHCI1394_HCControl_LPS;
1510 fw_error("Failed to set Link Power Status\n");
1514 reg_write(ohci, OHCI1394_HCControlClear,
1515 OHCI1394_HCControl_noByteSwapData);
1517 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1518 reg_write(ohci, OHCI1394_LinkControlClear,
1519 OHCI1394_LinkControl_rcvPhyPkt);
1520 reg_write(ohci, OHCI1394_LinkControlSet,
1521 OHCI1394_LinkControl_rcvSelfID |
1522 OHCI1394_LinkControl_cycleTimerEnable |
1523 OHCI1394_LinkControl_cycleMaster);
1525 reg_write(ohci, OHCI1394_ATRetries,
1526 OHCI1394_MAX_AT_REQ_RETRIES |
1527 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1528 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1530 ar_context_run(&ohci->ar_request_ctx);
1531 ar_context_run(&ohci->ar_response_ctx);
1533 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1534 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1535 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1536 reg_write(ohci, OHCI1394_IntMaskSet,
1537 OHCI1394_selfIDComplete |
1538 OHCI1394_RQPkt | OHCI1394_RSPkt |
1539 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1540 OHCI1394_isochRx | OHCI1394_isochTx |
1541 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1542 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1543 OHCI1394_masterIntEnable);
1544 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1545 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1547 /* Activate link_on bit and contender bit in our self ID packets.*/
1548 if (ohci_update_phy_reg(card, 4, 0,
1549 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1553 * When the link is not yet enabled, the atomic config rom
1554 * update mechanism described below in ohci_set_config_rom()
1555 * is not active. We have to update ConfigRomHeader and
1556 * BusOptions manually, and the write to ConfigROMmap takes
1557 * effect immediately. We tie this to the enabling of the
1558 * link, so we have a valid config rom before enabling - the
1559 * OHCI requires that ConfigROMhdr and BusOptions have valid
1560 * values before enabling.
1562 * However, when the ConfigROMmap is written, some controllers
1563 * always read back quadlets 0 and 2 from the config rom to
1564 * the ConfigRomHeader and BusOptions registers on bus reset.
1565 * They shouldn't do that in this initial case where the link
1566 * isn't enabled. This means we have to use the same
1567 * workaround here, setting the bus header to 0 and then write
1568 * the right values in the bus reset tasklet.
1572 ohci->next_config_rom =
1573 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1574 &ohci->next_config_rom_bus,
1576 if (ohci->next_config_rom == NULL)
1579 copy_config_rom(ohci->next_config_rom, config_rom, length);
1582 * In the suspend case, config_rom is NULL, which
1583 * means that we just reuse the old config rom.
1585 ohci->next_config_rom = ohci->config_rom;
1586 ohci->next_config_rom_bus = ohci->config_rom_bus;
1589 ohci->next_header = ohci->next_config_rom[0];
1590 ohci->next_config_rom[0] = 0;
1591 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1592 reg_write(ohci, OHCI1394_BusOptions,
1593 be32_to_cpu(ohci->next_config_rom[2]));
1594 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1596 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1598 if (request_irq(dev->irq, irq_handler,
1599 IRQF_SHARED, ohci_driver_name, ohci)) {
1600 fw_error("Failed to allocate shared interrupt %d.\n",
1602 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1603 ohci->config_rom, ohci->config_rom_bus);
1607 reg_write(ohci, OHCI1394_HCControlSet,
1608 OHCI1394_HCControl_linkEnable |
1609 OHCI1394_HCControl_BIBimageValid);
1613 * We are ready to go, initiate bus reset to finish the
1617 fw_core_initiate_bus_reset(&ohci->card, 1);
1622 static int ohci_set_config_rom(struct fw_card *card,
1623 const __be32 *config_rom, size_t length)
1625 struct fw_ohci *ohci;
1626 unsigned long flags;
1628 __be32 *next_config_rom;
1629 dma_addr_t uninitialized_var(next_config_rom_bus);
1631 ohci = fw_ohci(card);
1634 * When the OHCI controller is enabled, the config rom update
1635 * mechanism is a bit tricky, but easy enough to use. See
1636 * section 5.5.6 in the OHCI specification.
1638 * The OHCI controller caches the new config rom address in a
1639 * shadow register (ConfigROMmapNext) and needs a bus reset
1640 * for the changes to take place. When the bus reset is
1641 * detected, the controller loads the new values for the
1642 * ConfigRomHeader and BusOptions registers from the specified
1643 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1644 * shadow register. All automatically and atomically.
1646 * Now, there's a twist to this story. The automatic load of
1647 * ConfigRomHeader and BusOptions doesn't honor the
1648 * noByteSwapData bit, so with a be32 config rom, the
1649 * controller will load be32 values in to these registers
1650 * during the atomic update, even on litte endian
1651 * architectures. The workaround we use is to put a 0 in the
1652 * header quadlet; 0 is endian agnostic and means that the
1653 * config rom isn't ready yet. In the bus reset tasklet we
1654 * then set up the real values for the two registers.
1656 * We use ohci->lock to avoid racing with the code that sets
1657 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1661 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1662 &next_config_rom_bus, GFP_KERNEL);
1663 if (next_config_rom == NULL)
1666 spin_lock_irqsave(&ohci->lock, flags);
1668 if (ohci->next_config_rom == NULL) {
1669 ohci->next_config_rom = next_config_rom;
1670 ohci->next_config_rom_bus = next_config_rom_bus;
1672 copy_config_rom(ohci->next_config_rom, config_rom, length);
1674 ohci->next_header = config_rom[0];
1675 ohci->next_config_rom[0] = 0;
1677 reg_write(ohci, OHCI1394_ConfigROMmap,
1678 ohci->next_config_rom_bus);
1682 spin_unlock_irqrestore(&ohci->lock, flags);
1685 * Now initiate a bus reset to have the changes take
1686 * effect. We clean up the old config rom memory and DMA
1687 * mappings in the bus reset tasklet, since the OHCI
1688 * controller could need to access it before the bus reset
1692 fw_core_initiate_bus_reset(&ohci->card, 1);
1694 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1695 next_config_rom, next_config_rom_bus);
1700 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1702 struct fw_ohci *ohci = fw_ohci(card);
1704 at_context_transmit(&ohci->at_request_ctx, packet);
1707 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1709 struct fw_ohci *ohci = fw_ohci(card);
1711 at_context_transmit(&ohci->at_response_ctx, packet);
1714 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1716 struct fw_ohci *ohci = fw_ohci(card);
1717 struct context *ctx = &ohci->at_request_ctx;
1718 struct driver_data *driver_data = packet->driver_data;
1721 tasklet_disable(&ctx->tasklet);
1723 if (packet->ack != 0)
1726 if (packet->payload_bus)
1727 dma_unmap_single(ohci->card.device, packet->payload_bus,
1728 packet->payload_length, DMA_TO_DEVICE);
1730 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1731 driver_data->packet = NULL;
1732 packet->ack = RCODE_CANCELLED;
1733 packet->callback(packet, &ohci->card, packet->ack);
1736 tasklet_enable(&ctx->tasklet);
1741 static int ohci_enable_phys_dma(struct fw_card *card,
1742 int node_id, int generation)
1744 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1747 struct fw_ohci *ohci = fw_ohci(card);
1748 unsigned long flags;
1752 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1753 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1756 spin_lock_irqsave(&ohci->lock, flags);
1758 if (ohci->generation != generation) {
1764 * Note, if the node ID contains a non-local bus ID, physical DMA is
1765 * enabled for _all_ nodes on remote buses.
1768 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1770 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1772 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1776 spin_unlock_irqrestore(&ohci->lock, flags);
1779 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1782 static u64 ohci_get_bus_time(struct fw_card *card)
1784 struct fw_ohci *ohci = fw_ohci(card);
1788 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1789 bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1794 static void copy_iso_headers(struct iso_context *ctx, void *p)
1796 int i = ctx->header_length;
1798 if (i + ctx->base.header_size > PAGE_SIZE)
1802 * The iso header is byteswapped to little endian by
1803 * the controller, but the remaining header quadlets
1804 * are big endian. We want to present all the headers
1805 * as big endian, so we have to swap the first quadlet.
1807 if (ctx->base.header_size > 0)
1808 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1809 if (ctx->base.header_size > 4)
1810 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1811 if (ctx->base.header_size > 8)
1812 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1813 ctx->header_length += ctx->base.header_size;
1816 static int handle_ir_dualbuffer_packet(struct context *context,
1817 struct descriptor *d,
1818 struct descriptor *last)
1820 struct iso_context *ctx =
1821 container_of(context, struct iso_context, context);
1822 struct db_descriptor *db = (struct db_descriptor *) d;
1824 size_t header_length;
1827 if (db->first_res_count != 0 && db->second_res_count != 0) {
1828 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1829 /* This descriptor isn't done yet, stop iteration. */
1832 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1835 header_length = le16_to_cpu(db->first_req_count) -
1836 le16_to_cpu(db->first_res_count);
1839 end = p + header_length;
1841 copy_iso_headers(ctx, p);
1842 ctx->excess_bytes +=
1843 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1844 p += max(ctx->base.header_size, (size_t)8);
1847 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1848 le16_to_cpu(db->second_res_count);
1850 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1851 ir_header = (__le32 *) (db + 1);
1852 ctx->base.callback(&ctx->base,
1853 le32_to_cpu(ir_header[0]) & 0xffff,
1854 ctx->header_length, ctx->header,
1855 ctx->base.callback_data);
1856 ctx->header_length = 0;
1862 static int handle_ir_packet_per_buffer(struct context *context,
1863 struct descriptor *d,
1864 struct descriptor *last)
1866 struct iso_context *ctx =
1867 container_of(context, struct iso_context, context);
1868 struct descriptor *pd;
1872 for (pd = d; pd <= last; pd++) {
1873 if (pd->transfer_status)
1877 /* Descriptor(s) not done yet, stop iteration */
1881 copy_iso_headers(ctx, p);
1883 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1884 ir_header = (__le32 *) p;
1885 ctx->base.callback(&ctx->base,
1886 le32_to_cpu(ir_header[0]) & 0xffff,
1887 ctx->header_length, ctx->header,
1888 ctx->base.callback_data);
1889 ctx->header_length = 0;
1895 static int handle_it_packet(struct context *context,
1896 struct descriptor *d,
1897 struct descriptor *last)
1899 struct iso_context *ctx =
1900 container_of(context, struct iso_context, context);
1902 if (last->transfer_status == 0)
1903 /* This descriptor isn't done yet, stop iteration. */
1906 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1907 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1908 0, NULL, ctx->base.callback_data);
1913 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1914 int type, int channel, size_t header_size)
1916 struct fw_ohci *ohci = fw_ohci(card);
1917 struct iso_context *ctx, *list;
1918 descriptor_callback_t callback;
1919 u64 *channels, dont_care = ~0ULL;
1921 unsigned long flags;
1922 int index, ret = -ENOMEM;
1924 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1925 channels = &dont_care;
1926 mask = &ohci->it_context_mask;
1927 list = ohci->it_context_list;
1928 callback = handle_it_packet;
1930 channels = &ohci->ir_context_channels;
1931 mask = &ohci->ir_context_mask;
1932 list = ohci->ir_context_list;
1933 if (ohci->use_dualbuffer)
1934 callback = handle_ir_dualbuffer_packet;
1936 callback = handle_ir_packet_per_buffer;
1939 spin_lock_irqsave(&ohci->lock, flags);
1940 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1942 *channels &= ~(1ULL << channel);
1943 *mask &= ~(1 << index);
1945 spin_unlock_irqrestore(&ohci->lock, flags);
1948 return ERR_PTR(-EBUSY);
1950 if (type == FW_ISO_CONTEXT_TRANSMIT)
1951 regs = OHCI1394_IsoXmitContextBase(index);
1953 regs = OHCI1394_IsoRcvContextBase(index);
1956 memset(ctx, 0, sizeof(*ctx));
1957 ctx->header_length = 0;
1958 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1959 if (ctx->header == NULL)
1962 ret = context_init(&ctx->context, ohci, regs, callback);
1964 goto out_with_header;
1969 free_page((unsigned long)ctx->header);
1971 spin_lock_irqsave(&ohci->lock, flags);
1972 *mask |= 1 << index;
1973 spin_unlock_irqrestore(&ohci->lock, flags);
1975 return ERR_PTR(ret);
1978 static int ohci_start_iso(struct fw_iso_context *base,
1979 s32 cycle, u32 sync, u32 tags)
1981 struct iso_context *ctx = container_of(base, struct iso_context, base);
1982 struct fw_ohci *ohci = ctx->context.ohci;
1986 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1987 index = ctx - ohci->it_context_list;
1990 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1991 (cycle & 0x7fff) << 16;
1993 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1994 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1995 context_run(&ctx->context, match);
1997 index = ctx - ohci->ir_context_list;
1998 control = IR_CONTEXT_ISOCH_HEADER;
1999 if (ohci->use_dualbuffer)
2000 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2001 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2003 match |= (cycle & 0x07fff) << 12;
2004 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2007 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2008 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2009 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2010 context_run(&ctx->context, control);
2016 static int ohci_stop_iso(struct fw_iso_context *base)
2018 struct fw_ohci *ohci = fw_ohci(base->card);
2019 struct iso_context *ctx = container_of(base, struct iso_context, base);
2022 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2023 index = ctx - ohci->it_context_list;
2024 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2026 index = ctx - ohci->ir_context_list;
2027 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2030 context_stop(&ctx->context);
2035 static void ohci_free_iso_context(struct fw_iso_context *base)
2037 struct fw_ohci *ohci = fw_ohci(base->card);
2038 struct iso_context *ctx = container_of(base, struct iso_context, base);
2039 unsigned long flags;
2042 ohci_stop_iso(base);
2043 context_release(&ctx->context);
2044 free_page((unsigned long)ctx->header);
2046 spin_lock_irqsave(&ohci->lock, flags);
2048 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2049 index = ctx - ohci->it_context_list;
2050 ohci->it_context_mask |= 1 << index;
2052 index = ctx - ohci->ir_context_list;
2053 ohci->ir_context_mask |= 1 << index;
2054 ohci->ir_context_channels |= 1ULL << base->channel;
2057 spin_unlock_irqrestore(&ohci->lock, flags);
2060 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2061 struct fw_iso_packet *packet,
2062 struct fw_iso_buffer *buffer,
2063 unsigned long payload)
2065 struct iso_context *ctx = container_of(base, struct iso_context, base);
2066 struct descriptor *d, *last, *pd;
2067 struct fw_iso_packet *p;
2069 dma_addr_t d_bus, page_bus;
2070 u32 z, header_z, payload_z, irq;
2071 u32 payload_index, payload_end_index, next_page_index;
2072 int page, end_page, i, length, offset;
2075 * FIXME: Cycle lost behavior should be configurable: lose
2076 * packet, retransmit or terminate..
2080 payload_index = payload;
2086 if (p->header_length > 0)
2089 /* Determine the first page the payload isn't contained in. */
2090 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2091 if (p->payload_length > 0)
2092 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2098 /* Get header size in number of descriptors. */
2099 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2101 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2106 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2107 d[0].req_count = cpu_to_le16(8);
2109 header = (__le32 *) &d[1];
2110 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2111 IT_HEADER_TAG(p->tag) |
2112 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2113 IT_HEADER_CHANNEL(ctx->base.channel) |
2114 IT_HEADER_SPEED(ctx->base.speed));
2116 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2117 p->payload_length));
2120 if (p->header_length > 0) {
2121 d[2].req_count = cpu_to_le16(p->header_length);
2122 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2123 memcpy(&d[z], p->header, p->header_length);
2126 pd = d + z - payload_z;
2127 payload_end_index = payload_index + p->payload_length;
2128 for (i = 0; i < payload_z; i++) {
2129 page = payload_index >> PAGE_SHIFT;
2130 offset = payload_index & ~PAGE_MASK;
2131 next_page_index = (page + 1) << PAGE_SHIFT;
2133 min(next_page_index, payload_end_index) - payload_index;
2134 pd[i].req_count = cpu_to_le16(length);
2136 page_bus = page_private(buffer->pages[page]);
2137 pd[i].data_address = cpu_to_le32(page_bus + offset);
2139 payload_index += length;
2143 irq = DESCRIPTOR_IRQ_ALWAYS;
2145 irq = DESCRIPTOR_NO_IRQ;
2147 last = z == 2 ? d : d + z - 1;
2148 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2150 DESCRIPTOR_BRANCH_ALWAYS |
2153 context_append(&ctx->context, d, z, header_z);
2158 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2159 struct fw_iso_packet *packet,
2160 struct fw_iso_buffer *buffer,
2161 unsigned long payload)
2163 struct iso_context *ctx = container_of(base, struct iso_context, base);
2164 struct db_descriptor *db = NULL;
2165 struct descriptor *d;
2166 struct fw_iso_packet *p;
2167 dma_addr_t d_bus, page_bus;
2168 u32 z, header_z, length, rest;
2169 int page, offset, packet_count, header_size;
2172 * FIXME: Cycle lost behavior should be configurable: lose
2173 * packet, retransmit or terminate..
2180 * The OHCI controller puts the isochronous header and trailer in the
2181 * buffer, so we need at least 8 bytes.
2183 packet_count = p->header_length / ctx->base.header_size;
2184 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2186 /* Get header size in number of descriptors. */
2187 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2188 page = payload >> PAGE_SHIFT;
2189 offset = payload & ~PAGE_MASK;
2190 rest = p->payload_length;
2192 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2194 d = context_get_descriptors(&ctx->context,
2195 z + header_z, &d_bus);
2199 db = (struct db_descriptor *) d;
2200 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2201 DESCRIPTOR_BRANCH_ALWAYS);
2203 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2204 if (p->skip && rest == p->payload_length) {
2205 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2206 db->first_req_count = db->first_size;
2208 db->first_req_count = cpu_to_le16(header_size);
2210 db->first_res_count = db->first_req_count;
2211 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2213 if (p->skip && rest == p->payload_length)
2215 else if (offset + rest < PAGE_SIZE)
2218 length = PAGE_SIZE - offset;
2220 db->second_req_count = cpu_to_le16(length);
2221 db->second_res_count = db->second_req_count;
2222 page_bus = page_private(buffer->pages[page]);
2223 db->second_buffer = cpu_to_le32(page_bus + offset);
2225 if (p->interrupt && length == rest)
2226 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2228 context_append(&ctx->context, d, z, header_z);
2229 offset = (offset + length) & ~PAGE_MASK;
2238 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2239 struct fw_iso_packet *packet,
2240 struct fw_iso_buffer *buffer,
2241 unsigned long payload)
2243 struct iso_context *ctx = container_of(base, struct iso_context, base);
2244 struct descriptor *d = NULL, *pd = NULL;
2245 struct fw_iso_packet *p = packet;
2246 dma_addr_t d_bus, page_bus;
2247 u32 z, header_z, rest;
2249 int page, offset, packet_count, header_size, payload_per_buffer;
2252 * The OHCI controller puts the isochronous header and trailer in the
2253 * buffer, so we need at least 8 bytes.
2255 packet_count = p->header_length / ctx->base.header_size;
2256 header_size = max(ctx->base.header_size, (size_t)8);
2258 /* Get header size in number of descriptors. */
2259 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2260 page = payload >> PAGE_SHIFT;
2261 offset = payload & ~PAGE_MASK;
2262 payload_per_buffer = p->payload_length / packet_count;
2264 for (i = 0; i < packet_count; i++) {
2265 /* d points to the header descriptor */
2266 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2267 d = context_get_descriptors(&ctx->context,
2268 z + header_z, &d_bus);
2272 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2273 DESCRIPTOR_INPUT_MORE);
2274 if (p->skip && i == 0)
2275 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2276 d->req_count = cpu_to_le16(header_size);
2277 d->res_count = d->req_count;
2278 d->transfer_status = 0;
2279 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2281 rest = payload_per_buffer;
2282 for (j = 1; j < z; j++) {
2284 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2285 DESCRIPTOR_INPUT_MORE);
2287 if (offset + rest < PAGE_SIZE)
2290 length = PAGE_SIZE - offset;
2291 pd->req_count = cpu_to_le16(length);
2292 pd->res_count = pd->req_count;
2293 pd->transfer_status = 0;
2295 page_bus = page_private(buffer->pages[page]);
2296 pd->data_address = cpu_to_le32(page_bus + offset);
2298 offset = (offset + length) & ~PAGE_MASK;
2303 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2304 DESCRIPTOR_INPUT_LAST |
2305 DESCRIPTOR_BRANCH_ALWAYS);
2306 if (p->interrupt && i == packet_count - 1)
2307 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2309 context_append(&ctx->context, d, z, header_z);
2315 static int ohci_queue_iso(struct fw_iso_context *base,
2316 struct fw_iso_packet *packet,
2317 struct fw_iso_buffer *buffer,
2318 unsigned long payload)
2320 struct iso_context *ctx = container_of(base, struct iso_context, base);
2321 unsigned long flags;
2324 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2325 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2326 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2327 else if (ctx->context.ohci->use_dualbuffer)
2328 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2331 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2333 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2338 static const struct fw_card_driver ohci_driver = {
2339 .enable = ohci_enable,
2340 .update_phy_reg = ohci_update_phy_reg,
2341 .set_config_rom = ohci_set_config_rom,
2342 .send_request = ohci_send_request,
2343 .send_response = ohci_send_response,
2344 .cancel_packet = ohci_cancel_packet,
2345 .enable_phys_dma = ohci_enable_phys_dma,
2346 .get_bus_time = ohci_get_bus_time,
2348 .allocate_iso_context = ohci_allocate_iso_context,
2349 .free_iso_context = ohci_free_iso_context,
2350 .queue_iso = ohci_queue_iso,
2351 .start_iso = ohci_start_iso,
2352 .stop_iso = ohci_stop_iso,
2355 #ifdef CONFIG_PPC_PMAC
2356 static void ohci_pmac_on(struct pci_dev *dev)
2358 if (machine_is(powermac)) {
2359 struct device_node *ofn = pci_device_to_OF_node(dev);
2362 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2363 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2368 static void ohci_pmac_off(struct pci_dev *dev)
2370 if (machine_is(powermac)) {
2371 struct device_node *ofn = pci_device_to_OF_node(dev);
2374 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2375 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2380 #define ohci_pmac_on(dev)
2381 #define ohci_pmac_off(dev)
2382 #endif /* CONFIG_PPC_PMAC */
2384 #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2385 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
2387 static int __devinit pci_probe(struct pci_dev *dev,
2388 const struct pci_device_id *ent)
2390 struct fw_ohci *ohci;
2391 u32 bus_options, max_receive, link_speed, version;
2396 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2402 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2406 err = pci_enable_device(dev);
2408 fw_error("Failed to enable OHCI hardware\n");
2412 pci_set_master(dev);
2413 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2414 pci_set_drvdata(dev, ohci);
2416 spin_lock_init(&ohci->lock);
2418 tasklet_init(&ohci->bus_reset_tasklet,
2419 bus_reset_tasklet, (unsigned long)ohci);
2421 err = pci_request_region(dev, 0, ohci_driver_name);
2423 fw_error("MMIO resource unavailable\n");
2427 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2428 if (ohci->registers == NULL) {
2429 fw_error("Failed to remap registers\n");
2434 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2435 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2437 /* dual-buffer mode is broken if more than one IR context is active */
2438 if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2439 dev->device == PCI_DEVICE_ID_AGERE_FW643)
2440 ohci->use_dualbuffer = false;
2442 /* dual-buffer mode is broken */
2443 if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2444 dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2445 ohci->use_dualbuffer = false;
2447 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2448 #if !defined(CONFIG_X86_32)
2449 /* dual-buffer mode is broken with descriptor addresses above 2G */
2450 if (dev->vendor == PCI_VENDOR_ID_TI &&
2451 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2452 ohci->use_dualbuffer = false;
2455 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2456 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2457 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2459 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2461 ar_context_init(&ohci->ar_request_ctx, ohci,
2462 OHCI1394_AsReqRcvContextControlSet);
2464 ar_context_init(&ohci->ar_response_ctx, ohci,
2465 OHCI1394_AsRspRcvContextControlSet);
2467 context_init(&ohci->at_request_ctx, ohci,
2468 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2470 context_init(&ohci->at_response_ctx, ohci,
2471 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2473 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2474 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2475 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2476 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2477 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2479 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2480 ohci->ir_context_channels = ~0ULL;
2481 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2482 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2483 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2484 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2486 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2491 /* self-id dma buffer allocation */
2492 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2496 if (ohci->self_id_cpu == NULL) {
2501 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2502 max_receive = (bus_options >> 12) & 0xf;
2503 link_speed = bus_options & 0x7;
2504 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2505 reg_read(ohci, OHCI1394_GUIDLo);
2507 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2511 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2512 dev_name(&dev->dev), version >> 16, version & 0xff);
2517 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2518 ohci->self_id_cpu, ohci->self_id_bus);
2520 kfree(ohci->ir_context_list);
2521 kfree(ohci->it_context_list);
2522 context_release(&ohci->at_response_ctx);
2523 context_release(&ohci->at_request_ctx);
2524 ar_context_release(&ohci->ar_response_ctx);
2525 ar_context_release(&ohci->ar_request_ctx);
2526 pci_iounmap(dev, ohci->registers);
2528 pci_release_region(dev, 0);
2530 pci_disable_device(dev);
2536 fw_error("Out of memory\n");
2541 static void pci_remove(struct pci_dev *dev)
2543 struct fw_ohci *ohci;
2545 ohci = pci_get_drvdata(dev);
2546 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2548 fw_core_remove_card(&ohci->card);
2551 * FIXME: Fail all pending packets here, now that the upper
2552 * layers can't queue any more.
2555 software_reset(ohci);
2556 free_irq(dev->irq, ohci);
2558 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2559 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2560 ohci->next_config_rom, ohci->next_config_rom_bus);
2561 if (ohci->config_rom)
2562 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2563 ohci->config_rom, ohci->config_rom_bus);
2564 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2565 ohci->self_id_cpu, ohci->self_id_bus);
2566 ar_context_release(&ohci->ar_request_ctx);
2567 ar_context_release(&ohci->ar_response_ctx);
2568 context_release(&ohci->at_request_ctx);
2569 context_release(&ohci->at_response_ctx);
2570 kfree(ohci->it_context_list);
2571 kfree(ohci->ir_context_list);
2572 pci_iounmap(dev, ohci->registers);
2573 pci_release_region(dev, 0);
2574 pci_disable_device(dev);
2578 fw_notify("Removed fw-ohci device.\n");
2582 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2584 struct fw_ohci *ohci = pci_get_drvdata(dev);
2587 software_reset(ohci);
2588 free_irq(dev->irq, ohci);
2589 err = pci_save_state(dev);
2591 fw_error("pci_save_state failed\n");
2594 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2596 fw_error("pci_set_power_state failed with %d\n", err);
2602 static int pci_resume(struct pci_dev *dev)
2604 struct fw_ohci *ohci = pci_get_drvdata(dev);
2608 pci_set_power_state(dev, PCI_D0);
2609 pci_restore_state(dev);
2610 err = pci_enable_device(dev);
2612 fw_error("pci_enable_device failed\n");
2616 return ohci_enable(&ohci->card, NULL, 0);
2620 static struct pci_device_id pci_table[] = {
2621 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2625 MODULE_DEVICE_TABLE(pci, pci_table);
2627 static struct pci_driver fw_ohci_pci_driver = {
2628 .name = ohci_driver_name,
2629 .id_table = pci_table,
2631 .remove = pci_remove,
2633 .resume = pci_resume,
2634 .suspend = pci_suspend,
2638 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2639 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2640 MODULE_LICENSE("GPL");
2642 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2643 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2644 MODULE_ALIAS("ohci1394");
2647 static int __init fw_ohci_init(void)
2649 return pci_register_driver(&fw_ohci_pci_driver);
2652 static void __exit fw_ohci_cleanup(void)
2654 pci_unregister_driver(&fw_ohci_pci_driver);
2657 module_init(fw_ohci_init);
2658 module_exit(fw_ohci_cleanup);