drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj_priv->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj_priv->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj_priv->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj_priv->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj_priv->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj_priv->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj_priv;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj_priv = to_intel_bo(intel_fb->obj);
1388
1389         if (intel_fb->obj->size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj_priv->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_gem_object *obj,
1437                            bool pipelined)
1438 {
1439         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440         u32 alignment;
1441         int ret;
1442
1443         switch (obj_priv->tiling_mode) {
1444         case I915_TILING_NONE:
1445                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446                         alignment = 128 * 1024;
1447                 else if (INTEL_INFO(dev)->gen >= 4)
1448                         alignment = 4 * 1024;
1449                 else
1450                         alignment = 64 * 1024;
1451                 break;
1452         case I915_TILING_X:
1453                 /* pin() will align the object as required by fence */
1454                 alignment = 0;
1455                 break;
1456         case I915_TILING_Y:
1457                 /* FIXME: Is this true? */
1458                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459                 return -EINVAL;
1460         default:
1461                 BUG();
1462         }
1463
1464         ret = i915_gem_object_pin(obj, alignment,
1465                                   !pipelined, obj_priv->tiling_mode);
1466         if (ret)
1467                 return ret;
1468
1469         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1470         if (ret)
1471                 goto err_unpin;
1472
1473         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1474          * fence, whereas 965+ only requires a fence if using
1475          * framebuffer compression.  For simplicity, we always install
1476          * a fence as the cost is not that onerous.
1477          */
1478         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1479             obj_priv->tiling_mode != I915_TILING_NONE) {
1480                 ret = i915_gem_object_get_fence_reg(obj, false);
1481                 if (ret)
1482                         goto err_unpin;
1483         }
1484
1485         return 0;
1486
1487 err_unpin:
1488         i915_gem_object_unpin(obj);
1489         return ret;
1490 }
1491
1492 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1493 static int
1494 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1495                            int x, int y, enum mode_set_atomic state)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1500         struct intel_framebuffer *intel_fb;
1501         struct drm_i915_gem_object *obj_priv;
1502         struct drm_gem_object *obj;
1503         int plane = intel_crtc->plane;
1504         unsigned long Start, Offset;
1505         u32 dspcntr;
1506         u32 reg;
1507
1508         switch (plane) {
1509         case 0:
1510         case 1:
1511                 break;
1512         default:
1513                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1514                 return -EINVAL;
1515         }
1516
1517         intel_fb = to_intel_framebuffer(fb);
1518         obj = intel_fb->obj;
1519         obj_priv = to_intel_bo(obj);
1520
1521         reg = DSPCNTR(plane);
1522         dspcntr = I915_READ(reg);
1523         /* Mask out pixel format bits in case we change it */
1524         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1525         switch (fb->bits_per_pixel) {
1526         case 8:
1527                 dspcntr |= DISPPLANE_8BPP;
1528                 break;
1529         case 16:
1530                 if (fb->depth == 15)
1531                         dspcntr |= DISPPLANE_15_16BPP;
1532                 else
1533                         dspcntr |= DISPPLANE_16BPP;
1534                 break;
1535         case 24:
1536         case 32:
1537                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1538                 break;
1539         default:
1540                 DRM_ERROR("Unknown color depth\n");
1541                 return -EINVAL;
1542         }
1543         if (INTEL_INFO(dev)->gen >= 4) {
1544                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1545                         dspcntr |= DISPPLANE_TILED;
1546                 else
1547                         dspcntr &= ~DISPPLANE_TILED;
1548         }
1549
1550         if (HAS_PCH_SPLIT(dev))
1551                 /* must disable */
1552                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1553
1554         I915_WRITE(reg, dspcntr);
1555
1556         Start = obj_priv->gtt_offset;
1557         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1558
1559         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1560                       Start, Offset, x, y, fb->pitch);
1561         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1562         if (INTEL_INFO(dev)->gen >= 4) {
1563                 I915_WRITE(DSPSURF(plane), Start);
1564                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1565                 I915_WRITE(DSPADDR(plane), Offset);
1566         } else
1567                 I915_WRITE(DSPADDR(plane), Start + Offset);
1568         POSTING_READ(reg);
1569
1570         intel_update_fbc(dev);
1571         intel_increase_pllclock(crtc);
1572
1573         return 0;
1574 }
1575
1576 static int
1577 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1578                     struct drm_framebuffer *old_fb)
1579 {
1580         struct drm_device *dev = crtc->dev;
1581         struct drm_i915_master_private *master_priv;
1582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1583         int ret;
1584
1585         /* no fb bound */
1586         if (!crtc->fb) {
1587                 DRM_DEBUG_KMS("No FB bound\n");
1588                 return 0;
1589         }
1590
1591         switch (intel_crtc->plane) {
1592         case 0:
1593         case 1:
1594                 break;
1595         default:
1596                 return -EINVAL;
1597         }
1598
1599         mutex_lock(&dev->struct_mutex);
1600         ret = intel_pin_and_fence_fb_obj(dev,
1601                                          to_intel_framebuffer(crtc->fb)->obj,
1602                                          false);
1603         if (ret != 0) {
1604                 mutex_unlock(&dev->struct_mutex);
1605                 return ret;
1606         }
1607
1608         if (old_fb) {
1609                 struct drm_i915_private *dev_priv = dev->dev_private;
1610                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1611                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1612
1613                 wait_event(dev_priv->pending_flip_queue,
1614                            atomic_read(&obj_priv->pending_flip) == 0);
1615         }
1616
1617         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1618                                          LEAVE_ATOMIC_MODE_SET);
1619         if (ret) {
1620                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1621                 mutex_unlock(&dev->struct_mutex);
1622                 return ret;
1623         }
1624
1625         if (old_fb)
1626                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1627
1628         mutex_unlock(&dev->struct_mutex);
1629
1630         if (!dev->primary->master)
1631                 return 0;
1632
1633         master_priv = dev->primary->master->driver_priv;
1634         if (!master_priv->sarea_priv)
1635                 return 0;
1636
1637         if (intel_crtc->pipe) {
1638                 master_priv->sarea_priv->pipeB_x = x;
1639                 master_priv->sarea_priv->pipeB_y = y;
1640         } else {
1641                 master_priv->sarea_priv->pipeA_x = x;
1642                 master_priv->sarea_priv->pipeA_y = y;
1643         }
1644
1645         return 0;
1646 }
1647
1648 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1649 {
1650         struct drm_device *dev = crtc->dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         u32 dpa_ctl;
1653
1654         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1655         dpa_ctl = I915_READ(DP_A);
1656         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1657
1658         if (clock < 200000) {
1659                 u32 temp;
1660                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1661                 /* workaround for 160Mhz:
1662                    1) program 0x4600c bits 15:0 = 0x8124
1663                    2) program 0x46010 bit 0 = 1
1664                    3) program 0x46034 bit 24 = 1
1665                    4) program 0x64000 bit 14 = 1
1666                    */
1667                 temp = I915_READ(0x4600c);
1668                 temp &= 0xffff0000;
1669                 I915_WRITE(0x4600c, temp | 0x8124);
1670
1671                 temp = I915_READ(0x46010);
1672                 I915_WRITE(0x46010, temp | 1);
1673
1674                 temp = I915_READ(0x46034);
1675                 I915_WRITE(0x46034, temp | (1 << 24));
1676         } else {
1677                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1678         }
1679         I915_WRITE(DP_A, dpa_ctl);
1680
1681         POSTING_READ(DP_A);
1682         udelay(500);
1683 }
1684
1685 /* The FDI link training functions for ILK/Ibexpeak. */
1686 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1687 {
1688         struct drm_device *dev = crtc->dev;
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1691         int pipe = intel_crtc->pipe;
1692         u32 reg, temp, tries;
1693
1694         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1695            for train result */
1696         reg = FDI_RX_IMR(pipe);
1697         temp = I915_READ(reg);
1698         temp &= ~FDI_RX_SYMBOL_LOCK;
1699         temp &= ~FDI_RX_BIT_LOCK;
1700         I915_WRITE(reg, temp);
1701         I915_READ(reg);
1702         udelay(150);
1703
1704         /* enable CPU FDI TX and PCH FDI RX */
1705         reg = FDI_TX_CTL(pipe);
1706         temp = I915_READ(reg);
1707         temp &= ~(7 << 19);
1708         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1709         temp &= ~FDI_LINK_TRAIN_NONE;
1710         temp |= FDI_LINK_TRAIN_PATTERN_1;
1711         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1712
1713         reg = FDI_RX_CTL(pipe);
1714         temp = I915_READ(reg);
1715         temp &= ~FDI_LINK_TRAIN_NONE;
1716         temp |= FDI_LINK_TRAIN_PATTERN_1;
1717         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1718
1719         POSTING_READ(reg);
1720         udelay(150);
1721
1722         /* Ironlake workaround, enable clock pointer after FDI enable*/
1723         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1724
1725         reg = FDI_RX_IIR(pipe);
1726         for (tries = 0; tries < 5; tries++) {
1727                 temp = I915_READ(reg);
1728                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1729
1730                 if ((temp & FDI_RX_BIT_LOCK)) {
1731                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1732                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1733                         break;
1734                 }
1735         }
1736         if (tries == 5)
1737                 DRM_ERROR("FDI train 1 fail!\n");
1738
1739         /* Train 2 */
1740         reg = FDI_TX_CTL(pipe);
1741         temp = I915_READ(reg);
1742         temp &= ~FDI_LINK_TRAIN_NONE;
1743         temp |= FDI_LINK_TRAIN_PATTERN_2;
1744         I915_WRITE(reg, temp);
1745
1746         reg = FDI_RX_CTL(pipe);
1747         temp = I915_READ(reg);
1748         temp &= ~FDI_LINK_TRAIN_NONE;
1749         temp |= FDI_LINK_TRAIN_PATTERN_2;
1750         I915_WRITE(reg, temp);
1751
1752         POSTING_READ(reg);
1753         udelay(150);
1754
1755         reg = FDI_RX_IIR(pipe);
1756         for (tries = 0; tries < 5; tries++) {
1757                 temp = I915_READ(reg);
1758                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1759
1760                 if (temp & FDI_RX_SYMBOL_LOCK) {
1761                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1762                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1763                         break;
1764                 }
1765         }
1766         if (tries == 5)
1767                 DRM_ERROR("FDI train 2 fail!\n");
1768
1769         DRM_DEBUG_KMS("FDI train done\n");
1770
1771         /* enable normal train */
1772         reg = FDI_TX_CTL(pipe);
1773         temp = I915_READ(reg);
1774         temp &= ~FDI_LINK_TRAIN_NONE;
1775         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1776         I915_WRITE(reg, temp);
1777
1778         reg = FDI_RX_CTL(pipe);
1779         temp = I915_READ(reg);
1780         if (HAS_PCH_CPT(dev)) {
1781                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1782                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1783         } else {
1784                 temp &= ~FDI_LINK_TRAIN_NONE;
1785                 temp |= FDI_LINK_TRAIN_NONE;
1786         }
1787         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1788
1789         /* wait one idle pattern time */
1790         POSTING_READ(reg);
1791         udelay(1000);
1792 }
1793
1794 static const int const snb_b_fdi_train_param [] = {
1795         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1796         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1797         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1798         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1799 };
1800
1801 /* The FDI link training functions for SNB/Cougarpoint. */
1802 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1803 {
1804         struct drm_device *dev = crtc->dev;
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1807         int pipe = intel_crtc->pipe;
1808         u32 reg, temp, i;
1809
1810         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1811            for train result */
1812         reg = FDI_RX_IMR(pipe);
1813         temp = I915_READ(reg);
1814         temp &= ~FDI_RX_SYMBOL_LOCK;
1815         temp &= ~FDI_RX_BIT_LOCK;
1816         I915_WRITE(reg, temp);
1817
1818         POSTING_READ(reg);
1819         udelay(150);
1820
1821         /* enable CPU FDI TX and PCH FDI RX */
1822         reg = FDI_TX_CTL(pipe);
1823         temp = I915_READ(reg);
1824         temp &= ~(7 << 19);
1825         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1826         temp &= ~FDI_LINK_TRAIN_NONE;
1827         temp |= FDI_LINK_TRAIN_PATTERN_1;
1828         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1829         /* SNB-B */
1830         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1831         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1832
1833         reg = FDI_RX_CTL(pipe);
1834         temp = I915_READ(reg);
1835         if (HAS_PCH_CPT(dev)) {
1836                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1837                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1838         } else {
1839                 temp &= ~FDI_LINK_TRAIN_NONE;
1840                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1841         }
1842         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1843
1844         POSTING_READ(reg);
1845         udelay(150);
1846
1847         for (i = 0; i < 4; i++ ) {
1848                 reg = FDI_TX_CTL(pipe);
1849                 temp = I915_READ(reg);
1850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1851                 temp |= snb_b_fdi_train_param[i];
1852                 I915_WRITE(reg, temp);
1853
1854                 POSTING_READ(reg);
1855                 udelay(500);
1856
1857                 reg = FDI_RX_IIR(pipe);
1858                 temp = I915_READ(reg);
1859                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1860
1861                 if (temp & FDI_RX_BIT_LOCK) {
1862                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1863                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1864                         break;
1865                 }
1866         }
1867         if (i == 4)
1868                 DRM_ERROR("FDI train 1 fail!\n");
1869
1870         /* Train 2 */
1871         reg = FDI_TX_CTL(pipe);
1872         temp = I915_READ(reg);
1873         temp &= ~FDI_LINK_TRAIN_NONE;
1874         temp |= FDI_LINK_TRAIN_PATTERN_2;
1875         if (IS_GEN6(dev)) {
1876                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1877                 /* SNB-B */
1878                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1879         }
1880         I915_WRITE(reg, temp);
1881
1882         reg = FDI_RX_CTL(pipe);
1883         temp = I915_READ(reg);
1884         if (HAS_PCH_CPT(dev)) {
1885                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1886                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1887         } else {
1888                 temp &= ~FDI_LINK_TRAIN_NONE;
1889                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1890         }
1891         I915_WRITE(reg, temp);
1892
1893         POSTING_READ(reg);
1894         udelay(150);
1895
1896         for (i = 0; i < 4; i++ ) {
1897                 reg = FDI_TX_CTL(pipe);
1898                 temp = I915_READ(reg);
1899                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1900                 temp |= snb_b_fdi_train_param[i];
1901                 I915_WRITE(reg, temp);
1902
1903                 POSTING_READ(reg);
1904                 udelay(500);
1905
1906                 reg = FDI_RX_IIR(pipe);
1907                 temp = I915_READ(reg);
1908                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1909
1910                 if (temp & FDI_RX_SYMBOL_LOCK) {
1911                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1912                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1913                         break;
1914                 }
1915         }
1916         if (i == 4)
1917                 DRM_ERROR("FDI train 2 fail!\n");
1918
1919         DRM_DEBUG_KMS("FDI train done.\n");
1920 }
1921
1922 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1927         int pipe = intel_crtc->pipe;
1928         u32 reg, temp;
1929
1930         /* Write the TU size bits so error detection works */
1931         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1932                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1933
1934         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1935         reg = FDI_RX_CTL(pipe);
1936         temp = I915_READ(reg);
1937         temp &= ~((0x7 << 19) | (0x7 << 16));
1938         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1939         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1940         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1941
1942         POSTING_READ(reg);
1943         udelay(200);
1944
1945         /* Switch from Rawclk to PCDclk */
1946         temp = I915_READ(reg);
1947         I915_WRITE(reg, temp | FDI_PCDCLK);
1948
1949         POSTING_READ(reg);
1950         udelay(200);
1951
1952         /* Enable CPU FDI TX PLL, always on for Ironlake */
1953         reg = FDI_TX_CTL(pipe);
1954         temp = I915_READ(reg);
1955         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1956                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1957
1958                 POSTING_READ(reg);
1959                 udelay(100);
1960         }
1961 }
1962
1963 static void intel_flush_display_plane(struct drm_device *dev,
1964                                       int plane)
1965 {
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         u32 reg = DSPADDR(plane);
1968         I915_WRITE(reg, I915_READ(reg));
1969 }
1970
1971 /*
1972  * When we disable a pipe, we need to clear any pending scanline wait events
1973  * to avoid hanging the ring, which we assume we are waiting on.
1974  */
1975 static void intel_clear_scanline_wait(struct drm_device *dev)
1976 {
1977         struct drm_i915_private *dev_priv = dev->dev_private;
1978         u32 tmp;
1979
1980         if (IS_GEN2(dev))
1981                 /* Can't break the hang on i8xx */
1982                 return;
1983
1984         tmp = I915_READ(PRB0_CTL);
1985         if (tmp & RING_WAIT) {
1986                 I915_WRITE(PRB0_CTL, tmp);
1987                 POSTING_READ(PRB0_CTL);
1988         }
1989 }
1990
1991 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
1992 {
1993         struct drm_i915_gem_object *obj_priv;
1994         struct drm_i915_private *dev_priv;
1995
1996         if (crtc->fb == NULL)
1997                 return;
1998
1999         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2000         dev_priv = crtc->dev->dev_private;
2001         wait_event(dev_priv->pending_flip_queue,
2002                    atomic_read(&obj_priv->pending_flip) == 0);
2003 }
2004
2005 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2006 {
2007         struct drm_device *dev = crtc->dev;
2008         struct drm_i915_private *dev_priv = dev->dev_private;
2009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2010         int pipe = intel_crtc->pipe;
2011         int plane = intel_crtc->plane;
2012         u32 reg, temp;
2013
2014         if (intel_crtc->active)
2015                 return;
2016
2017         intel_crtc->active = true;
2018         intel_update_watermarks(dev);
2019
2020         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2021                 temp = I915_READ(PCH_LVDS);
2022                 if ((temp & LVDS_PORT_EN) == 0)
2023                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2024         }
2025
2026         ironlake_fdi_enable(crtc);
2027
2028         /* Enable panel fitting for LVDS */
2029         if (dev_priv->pch_pf_size &&
2030             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2031                 /* Force use of hard-coded filter coefficients
2032                  * as some pre-programmed values are broken,
2033                  * e.g. x201.
2034                  */
2035                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2036                            PF_ENABLE | PF_FILTER_MED_3x3);
2037                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2038                            dev_priv->pch_pf_pos);
2039                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2040                            dev_priv->pch_pf_size);
2041         }
2042
2043         /* Enable CPU pipe */
2044         reg = PIPECONF(pipe);
2045         temp = I915_READ(reg);
2046         if ((temp & PIPECONF_ENABLE) == 0) {
2047                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2048                 POSTING_READ(reg);
2049                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2050         }
2051
2052         /* configure and enable CPU plane */
2053         reg = DSPCNTR(plane);
2054         temp = I915_READ(reg);
2055         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2056                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2057                 intel_flush_display_plane(dev, plane);
2058         }
2059
2060         /* For PCH output, training FDI link */
2061         if (IS_GEN6(dev))
2062                 gen6_fdi_link_train(crtc);
2063         else
2064                 ironlake_fdi_link_train(crtc);
2065
2066         /* enable PCH DPLL */
2067         reg = PCH_DPLL(pipe);
2068         temp = I915_READ(reg);
2069         if ((temp & DPLL_VCO_ENABLE) == 0) {
2070                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2071                 POSTING_READ(reg);
2072                 udelay(200);
2073         }
2074
2075         if (HAS_PCH_CPT(dev)) {
2076                 /* Be sure PCH DPLL SEL is set */
2077                 temp = I915_READ(PCH_DPLL_SEL);
2078                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2079                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2080                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2081                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2082                 I915_WRITE(PCH_DPLL_SEL, temp);
2083         }
2084
2085         /* set transcoder timing */
2086         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2087         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2088         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2089
2090         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2091         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2092         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2093
2094         /* For PCH DP, enable TRANS_DP_CTL */
2095         if (HAS_PCH_CPT(dev) &&
2096             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2097                 reg = TRANS_DP_CTL(pipe);
2098                 temp = I915_READ(reg);
2099                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2100                           TRANS_DP_SYNC_MASK);
2101                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2102                          TRANS_DP_ENH_FRAMING);
2103
2104                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2105                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2106                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2107                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2108
2109                 switch (intel_trans_dp_port_sel(crtc)) {
2110                 case PCH_DP_B:
2111                         temp |= TRANS_DP_PORT_SEL_B;
2112                         break;
2113                 case PCH_DP_C:
2114                         temp |= TRANS_DP_PORT_SEL_C;
2115                         break;
2116                 case PCH_DP_D:
2117                         temp |= TRANS_DP_PORT_SEL_D;
2118                         break;
2119                 default:
2120                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2121                         temp |= TRANS_DP_PORT_SEL_B;
2122                         break;
2123                 }
2124
2125                 I915_WRITE(reg, temp);
2126         }
2127
2128         /* enable PCH transcoder */
2129         reg = TRANSCONF(pipe);
2130         temp = I915_READ(reg);
2131         /*
2132          * make the BPC in transcoder be consistent with
2133          * that in pipeconf reg.
2134          */
2135         temp &= ~PIPE_BPC_MASK;
2136         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2137         I915_WRITE(reg, temp | TRANS_ENABLE);
2138         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2139                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2140
2141         intel_crtc_load_lut(crtc);
2142         intel_update_fbc(dev);
2143         intel_crtc_update_cursor(crtc, true);
2144 }
2145
2146 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2147 {
2148         struct drm_device *dev = crtc->dev;
2149         struct drm_i915_private *dev_priv = dev->dev_private;
2150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151         int pipe = intel_crtc->pipe;
2152         int plane = intel_crtc->plane;
2153         u32 reg, temp;
2154
2155         if (!intel_crtc->active)
2156                 return;
2157
2158         intel_crtc_wait_for_pending_flips(crtc);
2159         drm_vblank_off(dev, pipe);
2160         intel_crtc_update_cursor(crtc, false);
2161
2162         /* Disable display plane */
2163         reg = DSPCNTR(plane);
2164         temp = I915_READ(reg);
2165         if (temp & DISPLAY_PLANE_ENABLE) {
2166                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2167                 intel_flush_display_plane(dev, plane);
2168         }
2169
2170         if (dev_priv->cfb_plane == plane &&
2171             dev_priv->display.disable_fbc)
2172                 dev_priv->display.disable_fbc(dev);
2173
2174         /* disable cpu pipe, disable after all planes disabled */
2175         reg = PIPECONF(pipe);
2176         temp = I915_READ(reg);
2177         if (temp & PIPECONF_ENABLE) {
2178                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2179                 POSTING_READ(reg);
2180                 /* wait for cpu pipe off, pipe state */
2181                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2182         }
2183
2184         /* Disable PF */
2185         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2186         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2187
2188         /* disable CPU FDI tx and PCH FDI rx */
2189         reg = FDI_TX_CTL(pipe);
2190         temp = I915_READ(reg);
2191         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2192         POSTING_READ(reg);
2193
2194         reg = FDI_RX_CTL(pipe);
2195         temp = I915_READ(reg);
2196         temp &= ~(0x7 << 16);
2197         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2198         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2199
2200         POSTING_READ(reg);
2201         udelay(100);
2202
2203         /* Ironlake workaround, disable clock pointer after downing FDI */
2204         I915_WRITE(FDI_RX_CHICKEN(pipe),
2205                    I915_READ(FDI_RX_CHICKEN(pipe) &
2206                              ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2207
2208         /* still set train pattern 1 */
2209         reg = FDI_TX_CTL(pipe);
2210         temp = I915_READ(reg);
2211         temp &= ~FDI_LINK_TRAIN_NONE;
2212         temp |= FDI_LINK_TRAIN_PATTERN_1;
2213         I915_WRITE(reg, temp);
2214
2215         reg = FDI_RX_CTL(pipe);
2216         temp = I915_READ(reg);
2217         if (HAS_PCH_CPT(dev)) {
2218                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2219                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2220         } else {
2221                 temp &= ~FDI_LINK_TRAIN_NONE;
2222                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2223         }
2224         /* BPC in FDI rx is consistent with that in PIPECONF */
2225         temp &= ~(0x07 << 16);
2226         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2227         I915_WRITE(reg, temp);
2228
2229         POSTING_READ(reg);
2230         udelay(100);
2231
2232         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2233                 temp = I915_READ(PCH_LVDS);
2234                 if (temp & LVDS_PORT_EN) {
2235                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2236                         POSTING_READ(PCH_LVDS);
2237                         udelay(100);
2238                 }
2239         }
2240
2241         /* disable PCH transcoder */
2242         reg = TRANSCONF(plane);
2243         temp = I915_READ(reg);
2244         if (temp & TRANS_ENABLE) {
2245                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2246                 /* wait for PCH transcoder off, transcoder state */
2247                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2248                         DRM_ERROR("failed to disable transcoder\n");
2249         }
2250
2251         if (HAS_PCH_CPT(dev)) {
2252                 /* disable TRANS_DP_CTL */
2253                 reg = TRANS_DP_CTL(pipe);
2254                 temp = I915_READ(reg);
2255                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2256                 I915_WRITE(reg, temp);
2257
2258                 /* disable DPLL_SEL */
2259                 temp = I915_READ(PCH_DPLL_SEL);
2260                 if (pipe == 0)
2261                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2262                 else
2263                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2264                 I915_WRITE(PCH_DPLL_SEL, temp);
2265         }
2266
2267         /* disable PCH DPLL */
2268         reg = PCH_DPLL(pipe);
2269         temp = I915_READ(reg);
2270         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2271
2272         /* Switch from PCDclk to Rawclk */
2273         reg = FDI_RX_CTL(pipe);
2274         temp = I915_READ(reg);
2275         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2276
2277         /* Disable CPU FDI TX PLL */
2278         reg = FDI_TX_CTL(pipe);
2279         temp = I915_READ(reg);
2280         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2281
2282         POSTING_READ(reg);
2283         udelay(100);
2284
2285         reg = FDI_RX_CTL(pipe);
2286         temp = I915_READ(reg);
2287         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2288
2289         /* Wait for the clocks to turn off. */
2290         POSTING_READ(reg);
2291         udelay(100);
2292
2293         intel_crtc->active = false;
2294         intel_update_watermarks(dev);
2295         intel_update_fbc(dev);
2296         intel_clear_scanline_wait(dev);
2297 }
2298
2299 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2300 {
2301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2302         int pipe = intel_crtc->pipe;
2303         int plane = intel_crtc->plane;
2304
2305         /* XXX: When our outputs are all unaware of DPMS modes other than off
2306          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2307          */
2308         switch (mode) {
2309         case DRM_MODE_DPMS_ON:
2310         case DRM_MODE_DPMS_STANDBY:
2311         case DRM_MODE_DPMS_SUSPEND:
2312                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2313                 ironlake_crtc_enable(crtc);
2314                 break;
2315
2316         case DRM_MODE_DPMS_OFF:
2317                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2318                 ironlake_crtc_disable(crtc);
2319                 break;
2320         }
2321 }
2322
2323 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2324 {
2325         if (!enable && intel_crtc->overlay) {
2326                 struct drm_device *dev = intel_crtc->base.dev;
2327
2328                 mutex_lock(&dev->struct_mutex);
2329                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2330                 mutex_unlock(&dev->struct_mutex);
2331         }
2332
2333         /* Let userspace switch the overlay on again. In most cases userspace
2334          * has to recompute where to put it anyway.
2335          */
2336 }
2337
2338 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2339 {
2340         struct drm_device *dev = crtc->dev;
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343         int pipe = intel_crtc->pipe;
2344         int plane = intel_crtc->plane;
2345         u32 reg, temp;
2346
2347         if (intel_crtc->active)
2348                 return;
2349
2350         intel_crtc->active = true;
2351         intel_update_watermarks(dev);
2352
2353         /* Enable the DPLL */
2354         reg = DPLL(pipe);
2355         temp = I915_READ(reg);
2356         if ((temp & DPLL_VCO_ENABLE) == 0) {
2357                 I915_WRITE(reg, temp);
2358
2359                 /* Wait for the clocks to stabilize. */
2360                 POSTING_READ(reg);
2361                 udelay(150);
2362
2363                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2364
2365                 /* Wait for the clocks to stabilize. */
2366                 POSTING_READ(reg);
2367                 udelay(150);
2368
2369                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2370
2371                 /* Wait for the clocks to stabilize. */
2372                 POSTING_READ(reg);
2373                 udelay(150);
2374         }
2375
2376         /* Enable the pipe */
2377         reg = PIPECONF(pipe);
2378         temp = I915_READ(reg);
2379         if ((temp & PIPECONF_ENABLE) == 0)
2380                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2381
2382         /* Enable the plane */
2383         reg = DSPCNTR(plane);
2384         temp = I915_READ(reg);
2385         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2386                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2387                 intel_flush_display_plane(dev, plane);
2388         }
2389
2390         intel_crtc_load_lut(crtc);
2391         intel_update_fbc(dev);
2392
2393         /* Give the overlay scaler a chance to enable if it's on this pipe */
2394         intel_crtc_dpms_overlay(intel_crtc, true);
2395         intel_crtc_update_cursor(crtc, true);
2396 }
2397
2398 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         int plane = intel_crtc->plane;
2405         u32 reg, temp;
2406
2407         if (!intel_crtc->active)
2408                 return;
2409
2410         /* Give the overlay scaler a chance to disable if it's on this pipe */
2411         intel_crtc_wait_for_pending_flips(crtc);
2412         drm_vblank_off(dev, pipe);
2413         intel_crtc_dpms_overlay(intel_crtc, false);
2414         intel_crtc_update_cursor(crtc, false);
2415
2416         if (dev_priv->cfb_plane == plane &&
2417             dev_priv->display.disable_fbc)
2418                 dev_priv->display.disable_fbc(dev);
2419
2420         /* Disable display plane */
2421         reg = DSPCNTR(plane);
2422         temp = I915_READ(reg);
2423         if (temp & DISPLAY_PLANE_ENABLE) {
2424                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2425                 /* Flush the plane changes */
2426                 intel_flush_display_plane(dev, plane);
2427
2428                 /* Wait for vblank for the disable to take effect */
2429                 if (IS_GEN2(dev))
2430                         intel_wait_for_vblank(dev, pipe);
2431         }
2432
2433         /* Don't disable pipe A or pipe A PLLs if needed */
2434         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2435                 goto done;
2436
2437         /* Next, disable display pipes */
2438         reg = PIPECONF(pipe);
2439         temp = I915_READ(reg);
2440         if (temp & PIPECONF_ENABLE) {
2441                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2442
2443                 /* Wait for the pipe to turn off */
2444                 POSTING_READ(reg);
2445                 intel_wait_for_pipe_off(dev, pipe);
2446         }
2447
2448         reg = DPLL(pipe);
2449         temp = I915_READ(reg);
2450         if (temp & DPLL_VCO_ENABLE) {
2451                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2452
2453                 /* Wait for the clocks to turn off. */
2454                 POSTING_READ(reg);
2455                 udelay(150);
2456         }
2457
2458 done:
2459         intel_crtc->active = false;
2460         intel_update_fbc(dev);
2461         intel_update_watermarks(dev);
2462         intel_clear_scanline_wait(dev);
2463 }
2464
2465 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2466 {
2467         /* XXX: When our outputs are all unaware of DPMS modes other than off
2468          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2469          */
2470         switch (mode) {
2471         case DRM_MODE_DPMS_ON:
2472         case DRM_MODE_DPMS_STANDBY:
2473         case DRM_MODE_DPMS_SUSPEND:
2474                 i9xx_crtc_enable(crtc);
2475                 break;
2476         case DRM_MODE_DPMS_OFF:
2477                 i9xx_crtc_disable(crtc);
2478                 break;
2479         }
2480 }
2481
2482 /**
2483  * Sets the power management mode of the pipe and plane.
2484  */
2485 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2486 {
2487         struct drm_device *dev = crtc->dev;
2488         struct drm_i915_private *dev_priv = dev->dev_private;
2489         struct drm_i915_master_private *master_priv;
2490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2491         int pipe = intel_crtc->pipe;
2492         bool enabled;
2493
2494         if (intel_crtc->dpms_mode == mode)
2495                 return;
2496
2497         intel_crtc->dpms_mode = mode;
2498
2499         dev_priv->display.dpms(crtc, mode);
2500
2501         if (!dev->primary->master)
2502                 return;
2503
2504         master_priv = dev->primary->master->driver_priv;
2505         if (!master_priv->sarea_priv)
2506                 return;
2507
2508         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2509
2510         switch (pipe) {
2511         case 0:
2512                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2513                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2514                 break;
2515         case 1:
2516                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2517                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2518                 break;
2519         default:
2520                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2521                 break;
2522         }
2523 }
2524
2525 static void intel_crtc_disable(struct drm_crtc *crtc)
2526 {
2527         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2528         struct drm_device *dev = crtc->dev;
2529
2530         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2531
2532         if (crtc->fb) {
2533                 mutex_lock(&dev->struct_mutex);
2534                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2535                 mutex_unlock(&dev->struct_mutex);
2536         }
2537 }
2538
2539 /* Prepare for a mode set.
2540  *
2541  * Note we could be a lot smarter here.  We need to figure out which outputs
2542  * will be enabled, which disabled (in short, how the config will changes)
2543  * and perform the minimum necessary steps to accomplish that, e.g. updating
2544  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2545  * panel fitting is in the proper state, etc.
2546  */
2547 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2548 {
2549         i9xx_crtc_disable(crtc);
2550 }
2551
2552 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2553 {
2554         i9xx_crtc_enable(crtc);
2555 }
2556
2557 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2558 {
2559         ironlake_crtc_disable(crtc);
2560 }
2561
2562 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2563 {
2564         ironlake_crtc_enable(crtc);
2565 }
2566
2567 void intel_encoder_prepare (struct drm_encoder *encoder)
2568 {
2569         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2570         /* lvds has its own version of prepare see intel_lvds_prepare */
2571         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2572 }
2573
2574 void intel_encoder_commit (struct drm_encoder *encoder)
2575 {
2576         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2577         /* lvds has its own version of commit see intel_lvds_commit */
2578         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2579 }
2580
2581 void intel_encoder_destroy(struct drm_encoder *encoder)
2582 {
2583         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2584
2585         drm_encoder_cleanup(encoder);
2586         kfree(intel_encoder);
2587 }
2588
2589 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2590                                   struct drm_display_mode *mode,
2591                                   struct drm_display_mode *adjusted_mode)
2592 {
2593         struct drm_device *dev = crtc->dev;
2594
2595         if (HAS_PCH_SPLIT(dev)) {
2596                 /* FDI link clock is fixed at 2.7G */
2597                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2598                         return false;
2599         }
2600
2601         /* XXX some encoders set the crtcinfo, others don't.
2602          * Obviously we need some form of conflict resolution here...
2603          */
2604         if (adjusted_mode->crtc_htotal == 0)
2605                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2606
2607         return true;
2608 }
2609
2610 static int i945_get_display_clock_speed(struct drm_device *dev)
2611 {
2612         return 400000;
2613 }
2614
2615 static int i915_get_display_clock_speed(struct drm_device *dev)
2616 {
2617         return 333000;
2618 }
2619
2620 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2621 {
2622         return 200000;
2623 }
2624
2625 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2626 {
2627         u16 gcfgc = 0;
2628
2629         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2630
2631         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2632                 return 133000;
2633         else {
2634                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2635                 case GC_DISPLAY_CLOCK_333_MHZ:
2636                         return 333000;
2637                 default:
2638                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2639                         return 190000;
2640                 }
2641         }
2642 }
2643
2644 static int i865_get_display_clock_speed(struct drm_device *dev)
2645 {
2646         return 266000;
2647 }
2648
2649 static int i855_get_display_clock_speed(struct drm_device *dev)
2650 {
2651         u16 hpllcc = 0;
2652         /* Assume that the hardware is in the high speed state.  This
2653          * should be the default.
2654          */
2655         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2656         case GC_CLOCK_133_200:
2657         case GC_CLOCK_100_200:
2658                 return 200000;
2659         case GC_CLOCK_166_250:
2660                 return 250000;
2661         case GC_CLOCK_100_133:
2662                 return 133000;
2663         }
2664
2665         /* Shouldn't happen */
2666         return 0;
2667 }
2668
2669 static int i830_get_display_clock_speed(struct drm_device *dev)
2670 {
2671         return 133000;
2672 }
2673
2674 struct fdi_m_n {
2675         u32        tu;
2676         u32        gmch_m;
2677         u32        gmch_n;
2678         u32        link_m;
2679         u32        link_n;
2680 };
2681
2682 static void
2683 fdi_reduce_ratio(u32 *num, u32 *den)
2684 {
2685         while (*num > 0xffffff || *den > 0xffffff) {
2686                 *num >>= 1;
2687                 *den >>= 1;
2688         }
2689 }
2690
2691 #define DATA_N 0x800000
2692 #define LINK_N 0x80000
2693
2694 static void
2695 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2696                      int link_clock, struct fdi_m_n *m_n)
2697 {
2698         u64 temp;
2699
2700         m_n->tu = 64; /* default size */
2701
2702         temp = (u64) DATA_N * pixel_clock;
2703         temp = div_u64(temp, link_clock);
2704         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2705         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2706         m_n->gmch_n = DATA_N;
2707         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2708
2709         temp = (u64) LINK_N * pixel_clock;
2710         m_n->link_m = div_u64(temp, link_clock);
2711         m_n->link_n = LINK_N;
2712         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2713 }
2714
2715
2716 struct intel_watermark_params {
2717         unsigned long fifo_size;
2718         unsigned long max_wm;
2719         unsigned long default_wm;
2720         unsigned long guard_size;
2721         unsigned long cacheline_size;
2722 };
2723
2724 /* Pineview has different values for various configs */
2725 static struct intel_watermark_params pineview_display_wm = {
2726         PINEVIEW_DISPLAY_FIFO,
2727         PINEVIEW_MAX_WM,
2728         PINEVIEW_DFT_WM,
2729         PINEVIEW_GUARD_WM,
2730         PINEVIEW_FIFO_LINE_SIZE
2731 };
2732 static struct intel_watermark_params pineview_display_hplloff_wm = {
2733         PINEVIEW_DISPLAY_FIFO,
2734         PINEVIEW_MAX_WM,
2735         PINEVIEW_DFT_HPLLOFF_WM,
2736         PINEVIEW_GUARD_WM,
2737         PINEVIEW_FIFO_LINE_SIZE
2738 };
2739 static struct intel_watermark_params pineview_cursor_wm = {
2740         PINEVIEW_CURSOR_FIFO,
2741         PINEVIEW_CURSOR_MAX_WM,
2742         PINEVIEW_CURSOR_DFT_WM,
2743         PINEVIEW_CURSOR_GUARD_WM,
2744         PINEVIEW_FIFO_LINE_SIZE,
2745 };
2746 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2747         PINEVIEW_CURSOR_FIFO,
2748         PINEVIEW_CURSOR_MAX_WM,
2749         PINEVIEW_CURSOR_DFT_WM,
2750         PINEVIEW_CURSOR_GUARD_WM,
2751         PINEVIEW_FIFO_LINE_SIZE
2752 };
2753 static struct intel_watermark_params g4x_wm_info = {
2754         G4X_FIFO_SIZE,
2755         G4X_MAX_WM,
2756         G4X_MAX_WM,
2757         2,
2758         G4X_FIFO_LINE_SIZE,
2759 };
2760 static struct intel_watermark_params g4x_cursor_wm_info = {
2761         I965_CURSOR_FIFO,
2762         I965_CURSOR_MAX_WM,
2763         I965_CURSOR_DFT_WM,
2764         2,
2765         G4X_FIFO_LINE_SIZE,
2766 };
2767 static struct intel_watermark_params i965_cursor_wm_info = {
2768         I965_CURSOR_FIFO,
2769         I965_CURSOR_MAX_WM,
2770         I965_CURSOR_DFT_WM,
2771         2,
2772         I915_FIFO_LINE_SIZE,
2773 };
2774 static struct intel_watermark_params i945_wm_info = {
2775         I945_FIFO_SIZE,
2776         I915_MAX_WM,
2777         1,
2778         2,
2779         I915_FIFO_LINE_SIZE
2780 };
2781 static struct intel_watermark_params i915_wm_info = {
2782         I915_FIFO_SIZE,
2783         I915_MAX_WM,
2784         1,
2785         2,
2786         I915_FIFO_LINE_SIZE
2787 };
2788 static struct intel_watermark_params i855_wm_info = {
2789         I855GM_FIFO_SIZE,
2790         I915_MAX_WM,
2791         1,
2792         2,
2793         I830_FIFO_LINE_SIZE
2794 };
2795 static struct intel_watermark_params i830_wm_info = {
2796         I830_FIFO_SIZE,
2797         I915_MAX_WM,
2798         1,
2799         2,
2800         I830_FIFO_LINE_SIZE
2801 };
2802
2803 static struct intel_watermark_params ironlake_display_wm_info = {
2804         ILK_DISPLAY_FIFO,
2805         ILK_DISPLAY_MAXWM,
2806         ILK_DISPLAY_DFTWM,
2807         2,
2808         ILK_FIFO_LINE_SIZE
2809 };
2810
2811 static struct intel_watermark_params ironlake_cursor_wm_info = {
2812         ILK_CURSOR_FIFO,
2813         ILK_CURSOR_MAXWM,
2814         ILK_CURSOR_DFTWM,
2815         2,
2816         ILK_FIFO_LINE_SIZE
2817 };
2818
2819 static struct intel_watermark_params ironlake_display_srwm_info = {
2820         ILK_DISPLAY_SR_FIFO,
2821         ILK_DISPLAY_MAX_SRWM,
2822         ILK_DISPLAY_DFT_SRWM,
2823         2,
2824         ILK_FIFO_LINE_SIZE
2825 };
2826
2827 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2828         ILK_CURSOR_SR_FIFO,
2829         ILK_CURSOR_MAX_SRWM,
2830         ILK_CURSOR_DFT_SRWM,
2831         2,
2832         ILK_FIFO_LINE_SIZE
2833 };
2834
2835 /**
2836  * intel_calculate_wm - calculate watermark level
2837  * @clock_in_khz: pixel clock
2838  * @wm: chip FIFO params
2839  * @pixel_size: display pixel size
2840  * @latency_ns: memory latency for the platform
2841  *
2842  * Calculate the watermark level (the level at which the display plane will
2843  * start fetching from memory again).  Each chip has a different display
2844  * FIFO size and allocation, so the caller needs to figure that out and pass
2845  * in the correct intel_watermark_params structure.
2846  *
2847  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2848  * on the pixel size.  When it reaches the watermark level, it'll start
2849  * fetching FIFO line sized based chunks from memory until the FIFO fills
2850  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2851  * will occur, and a display engine hang could result.
2852  */
2853 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2854                                         struct intel_watermark_params *wm,
2855                                         int pixel_size,
2856                                         unsigned long latency_ns)
2857 {
2858         long entries_required, wm_size;
2859
2860         /*
2861          * Note: we need to make sure we don't overflow for various clock &
2862          * latency values.
2863          * clocks go from a few thousand to several hundred thousand.
2864          * latency is usually a few thousand
2865          */
2866         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2867                 1000;
2868         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2869
2870         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2871
2872         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2873
2874         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2875
2876         /* Don't promote wm_size to unsigned... */
2877         if (wm_size > (long)wm->max_wm)
2878                 wm_size = wm->max_wm;
2879         if (wm_size <= 0)
2880                 wm_size = wm->default_wm;
2881         return wm_size;
2882 }
2883
2884 struct cxsr_latency {
2885         int is_desktop;
2886         int is_ddr3;
2887         unsigned long fsb_freq;
2888         unsigned long mem_freq;
2889         unsigned long display_sr;
2890         unsigned long display_hpll_disable;
2891         unsigned long cursor_sr;
2892         unsigned long cursor_hpll_disable;
2893 };
2894
2895 static const struct cxsr_latency cxsr_latency_table[] = {
2896         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2897         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2898         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2899         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2900         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2901
2902         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2903         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2904         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2905         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2906         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2907
2908         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2909         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2910         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2911         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2912         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2913
2914         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2915         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2916         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2917         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2918         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2919
2920         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2921         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2922         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2923         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2924         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2925
2926         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2927         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2928         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2929         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2930         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2931 };
2932
2933 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2934                                                          int is_ddr3,
2935                                                          int fsb,
2936                                                          int mem)
2937 {
2938         const struct cxsr_latency *latency;
2939         int i;
2940
2941         if (fsb == 0 || mem == 0)
2942                 return NULL;
2943
2944         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2945                 latency = &cxsr_latency_table[i];
2946                 if (is_desktop == latency->is_desktop &&
2947                     is_ddr3 == latency->is_ddr3 &&
2948                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2949                         return latency;
2950         }
2951
2952         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2953
2954         return NULL;
2955 }
2956
2957 static void pineview_disable_cxsr(struct drm_device *dev)
2958 {
2959         struct drm_i915_private *dev_priv = dev->dev_private;
2960
2961         /* deactivate cxsr */
2962         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2963 }
2964
2965 /*
2966  * Latency for FIFO fetches is dependent on several factors:
2967  *   - memory configuration (speed, channels)
2968  *   - chipset
2969  *   - current MCH state
2970  * It can be fairly high in some situations, so here we assume a fairly
2971  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2972  * set this value too high, the FIFO will fetch frequently to stay full)
2973  * and power consumption (set it too low to save power and we might see
2974  * FIFO underruns and display "flicker").
2975  *
2976  * A value of 5us seems to be a good balance; safe for very low end
2977  * platforms but not overly aggressive on lower latency configs.
2978  */
2979 static const int latency_ns = 5000;
2980
2981 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2982 {
2983         struct drm_i915_private *dev_priv = dev->dev_private;
2984         uint32_t dsparb = I915_READ(DSPARB);
2985         int size;
2986
2987         size = dsparb & 0x7f;
2988         if (plane)
2989                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2990
2991         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2992                       plane ? "B" : "A", size);
2993
2994         return size;
2995 }
2996
2997 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2998 {
2999         struct drm_i915_private *dev_priv = dev->dev_private;
3000         uint32_t dsparb = I915_READ(DSPARB);
3001         int size;
3002
3003         size = dsparb & 0x1ff;
3004         if (plane)
3005                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3006         size >>= 1; /* Convert to cachelines */
3007
3008         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3009                       plane ? "B" : "A", size);
3010
3011         return size;
3012 }
3013
3014 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3015 {
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         uint32_t dsparb = I915_READ(DSPARB);
3018         int size;
3019
3020         size = dsparb & 0x7f;
3021         size >>= 2; /* Convert to cachelines */
3022
3023         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3024                       plane ? "B" : "A",
3025                       size);
3026
3027         return size;
3028 }
3029
3030 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3031 {
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033         uint32_t dsparb = I915_READ(DSPARB);
3034         int size;
3035
3036         size = dsparb & 0x7f;
3037         size >>= 1; /* Convert to cachelines */
3038
3039         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3040                       plane ? "B" : "A", size);
3041
3042         return size;
3043 }
3044
3045 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3046                                int planeb_clock, int sr_hdisplay, int unused,
3047                                int pixel_size)
3048 {
3049         struct drm_i915_private *dev_priv = dev->dev_private;
3050         const struct cxsr_latency *latency;
3051         u32 reg;
3052         unsigned long wm;
3053         int sr_clock;
3054
3055         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3056                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3057         if (!latency) {
3058                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3059                 pineview_disable_cxsr(dev);
3060                 return;
3061         }
3062
3063         if (!planea_clock || !planeb_clock) {
3064                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3065
3066                 /* Display SR */
3067                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3068                                         pixel_size, latency->display_sr);
3069                 reg = I915_READ(DSPFW1);
3070                 reg &= ~DSPFW_SR_MASK;
3071                 reg |= wm << DSPFW_SR_SHIFT;
3072                 I915_WRITE(DSPFW1, reg);
3073                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3074
3075                 /* cursor SR */
3076                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3077                                         pixel_size, latency->cursor_sr);
3078                 reg = I915_READ(DSPFW3);
3079                 reg &= ~DSPFW_CURSOR_SR_MASK;
3080                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3081                 I915_WRITE(DSPFW3, reg);
3082
3083                 /* Display HPLL off SR */
3084                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3085                                         pixel_size, latency->display_hpll_disable);
3086                 reg = I915_READ(DSPFW3);
3087                 reg &= ~DSPFW_HPLL_SR_MASK;
3088                 reg |= wm & DSPFW_HPLL_SR_MASK;
3089                 I915_WRITE(DSPFW3, reg);
3090
3091                 /* cursor HPLL off SR */
3092                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3093                                         pixel_size, latency->cursor_hpll_disable);
3094                 reg = I915_READ(DSPFW3);
3095                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3096                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3097                 I915_WRITE(DSPFW3, reg);
3098                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3099
3100                 /* activate cxsr */
3101                 I915_WRITE(DSPFW3,
3102                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3103                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3104         } else {
3105                 pineview_disable_cxsr(dev);
3106                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3107         }
3108 }
3109
3110 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3111                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3112                           int pixel_size)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         int total_size, cacheline_size;
3116         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3117         struct intel_watermark_params planea_params, planeb_params;
3118         unsigned long line_time_us;
3119         int sr_clock, sr_entries = 0, entries_required;
3120
3121         /* Create copies of the base settings for each pipe */
3122         planea_params = planeb_params = g4x_wm_info;
3123
3124         /* Grab a couple of global values before we overwrite them */
3125         total_size = planea_params.fifo_size;
3126         cacheline_size = planea_params.cacheline_size;
3127
3128         /*
3129          * Note: we need to make sure we don't overflow for various clock &
3130          * latency values.
3131          * clocks go from a few thousand to several hundred thousand.
3132          * latency is usually a few thousand
3133          */
3134         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3135                 1000;
3136         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3137         planea_wm = entries_required + planea_params.guard_size;
3138
3139         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3140                 1000;
3141         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3142         planeb_wm = entries_required + planeb_params.guard_size;
3143
3144         cursora_wm = cursorb_wm = 16;
3145         cursor_sr = 32;
3146
3147         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3148
3149         /* Calc sr entries for one plane configs */
3150         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3151                 /* self-refresh has much higher latency */
3152                 static const int sr_latency_ns = 12000;
3153
3154                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3155                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3156
3157                 /* Use ns/us then divide to preserve precision */
3158                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3159                         pixel_size * sr_hdisplay;
3160                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3161
3162                 entries_required = (((sr_latency_ns / line_time_us) +
3163                                      1000) / 1000) * pixel_size * 64;
3164                 entries_required = DIV_ROUND_UP(entries_required,
3165                                                 g4x_cursor_wm_info.cacheline_size);
3166                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3167
3168                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3169                         cursor_sr = g4x_cursor_wm_info.max_wm;
3170                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3171                               "cursor %d\n", sr_entries, cursor_sr);
3172
3173                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3174         } else {
3175                 /* Turn off self refresh if both pipes are enabled */
3176                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3177                            & ~FW_BLC_SELF_EN);
3178         }
3179
3180         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3181                   planea_wm, planeb_wm, sr_entries);
3182
3183         planea_wm &= 0x3f;
3184         planeb_wm &= 0x3f;
3185
3186         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3187                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3188                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3189         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3190                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3191         /* HPLL off in SR has some issues on G4x... disable it */
3192         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3193                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3194 }
3195
3196 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3197                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3198                            int pixel_size)
3199 {
3200         struct drm_i915_private *dev_priv = dev->dev_private;
3201         unsigned long line_time_us;
3202         int sr_clock, sr_entries, srwm = 1;
3203         int cursor_sr = 16;
3204
3205         /* Calc sr entries for one plane configs */
3206         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3207                 /* self-refresh has much higher latency */
3208                 static const int sr_latency_ns = 12000;
3209
3210                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3211                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3212
3213                 /* Use ns/us then divide to preserve precision */
3214                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3215                         pixel_size * sr_hdisplay;
3216                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3217                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3218                 srwm = I965_FIFO_SIZE - sr_entries;
3219                 if (srwm < 0)
3220                         srwm = 1;
3221                 srwm &= 0x1ff;
3222
3223                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3224                         pixel_size * 64;
3225                 sr_entries = DIV_ROUND_UP(sr_entries,
3226                                           i965_cursor_wm_info.cacheline_size);
3227                 cursor_sr = i965_cursor_wm_info.fifo_size -
3228                         (sr_entries + i965_cursor_wm_info.guard_size);
3229
3230                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3231                         cursor_sr = i965_cursor_wm_info.max_wm;
3232
3233                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3234                               "cursor %d\n", srwm, cursor_sr);
3235
3236                 if (IS_CRESTLINE(dev))
3237                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3238         } else {
3239                 /* Turn off self refresh if both pipes are enabled */
3240                 if (IS_CRESTLINE(dev))
3241                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3242                                    & ~FW_BLC_SELF_EN);
3243         }
3244
3245         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3246                       srwm);
3247
3248         /* 965 has limitations... */
3249         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3250                    (8 << 0));
3251         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3252         /* update cursor SR watermark */
3253         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3254 }
3255
3256 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3257                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3258                            int pixel_size)
3259 {
3260         struct drm_i915_private *dev_priv = dev->dev_private;
3261         uint32_t fwater_lo;
3262         uint32_t fwater_hi;
3263         int total_size, cacheline_size, cwm, srwm = 1;
3264         int planea_wm, planeb_wm;
3265         struct intel_watermark_params planea_params, planeb_params;
3266         unsigned long line_time_us;
3267         int sr_clock, sr_entries = 0;
3268
3269         /* Create copies of the base settings for each pipe */
3270         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3271                 planea_params = planeb_params = i945_wm_info;
3272         else if (!IS_GEN2(dev))
3273                 planea_params = planeb_params = i915_wm_info;
3274         else
3275                 planea_params = planeb_params = i855_wm_info;
3276
3277         /* Grab a couple of global values before we overwrite them */
3278         total_size = planea_params.fifo_size;
3279         cacheline_size = planea_params.cacheline_size;
3280
3281         /* Update per-plane FIFO sizes */
3282         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3283         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3284
3285         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3286                                        pixel_size, latency_ns);
3287         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3288                                        pixel_size, latency_ns);
3289         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3290
3291         /*
3292          * Overlay gets an aggressive default since video jitter is bad.
3293          */
3294         cwm = 2;
3295
3296         /* Calc sr entries for one plane configs */
3297         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3298             (!planea_clock || !planeb_clock)) {
3299                 /* self-refresh has much higher latency */
3300                 static const int sr_latency_ns = 6000;
3301
3302                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3303                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3304
3305                 /* Use ns/us then divide to preserve precision */
3306                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3307                         pixel_size * sr_hdisplay;
3308                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3309                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3310                 srwm = total_size - sr_entries;
3311                 if (srwm < 0)
3312                         srwm = 1;
3313
3314                 if (IS_I945G(dev) || IS_I945GM(dev))
3315                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3316                 else if (IS_I915GM(dev)) {
3317                         /* 915M has a smaller SRWM field */
3318                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3319                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3320                 }
3321         } else {
3322                 /* Turn off self refresh if both pipes are enabled */
3323                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3324                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3325                                    & ~FW_BLC_SELF_EN);
3326                 } else if (IS_I915GM(dev)) {
3327                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3328                 }
3329         }
3330
3331         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3332                       planea_wm, planeb_wm, cwm, srwm);
3333
3334         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3335         fwater_hi = (cwm & 0x1f);
3336
3337         /* Set request length to 8 cachelines per fetch */
3338         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3339         fwater_hi = fwater_hi | (1 << 8);
3340
3341         I915_WRITE(FW_BLC, fwater_lo);
3342         I915_WRITE(FW_BLC2, fwater_hi);
3343 }
3344
3345 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3346                            int unused2, int unused3, int pixel_size)
3347 {
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3350         int planea_wm;
3351
3352         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3353
3354         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3355                                        pixel_size, latency_ns);
3356         fwater_lo |= (3<<8) | planea_wm;
3357
3358         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3359
3360         I915_WRITE(FW_BLC, fwater_lo);
3361 }
3362
3363 #define ILK_LP0_PLANE_LATENCY           700
3364 #define ILK_LP0_CURSOR_LATENCY          1300
3365
3366 static bool ironlake_compute_wm0(struct drm_device *dev,
3367                                  int pipe,
3368                                  int *plane_wm,
3369                                  int *cursor_wm)
3370 {
3371         struct drm_crtc *crtc;
3372         int htotal, hdisplay, clock, pixel_size = 0;
3373         int line_time_us, line_count, entries;
3374
3375         crtc = intel_get_crtc_for_pipe(dev, pipe);
3376         if (crtc->fb == NULL || !crtc->enabled)
3377                 return false;
3378
3379         htotal = crtc->mode.htotal;
3380         hdisplay = crtc->mode.hdisplay;
3381         clock = crtc->mode.clock;
3382         pixel_size = crtc->fb->bits_per_pixel / 8;
3383
3384         /* Use the small buffer method to calculate plane watermark */
3385         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3386         entries = DIV_ROUND_UP(entries,
3387                                ironlake_display_wm_info.cacheline_size);
3388         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3389         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3390                 *plane_wm = ironlake_display_wm_info.max_wm;
3391
3392         /* Use the large buffer method to calculate cursor watermark */
3393         line_time_us = ((htotal * 1000) / clock);
3394         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3395         entries = line_count * 64 * pixel_size;
3396         entries = DIV_ROUND_UP(entries,
3397                                ironlake_cursor_wm_info.cacheline_size);
3398         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3399         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3400                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3401
3402         return true;
3403 }
3404
3405 static void ironlake_update_wm(struct drm_device *dev,
3406                                int planea_clock, int planeb_clock,
3407                                int sr_hdisplay, int sr_htotal,
3408                                int pixel_size)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         int plane_wm, cursor_wm, enabled;
3412         int tmp;
3413
3414         enabled = 0;
3415         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3416                 I915_WRITE(WM0_PIPEA_ILK,
3417                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3418                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3419                               " plane %d, " "cursor: %d\n",
3420                               plane_wm, cursor_wm);
3421                 enabled++;
3422         }
3423
3424         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3425                 I915_WRITE(WM0_PIPEB_ILK,
3426                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3427                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3428                               " plane %d, cursor: %d\n",
3429                               plane_wm, cursor_wm);
3430                 enabled++;
3431         }
3432
3433         /*
3434          * Calculate and update the self-refresh watermark only when one
3435          * display plane is used.
3436          */
3437         tmp = 0;
3438         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3439                 unsigned long line_time_us;
3440                 int small, large, plane_fbc;
3441                 int sr_clock, entries;
3442                 int line_count, line_size;
3443                 /* Read the self-refresh latency. The unit is 0.5us */
3444                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3445
3446                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3447                 line_time_us = (sr_htotal * 1000) / sr_clock;
3448
3449                 /* Use ns/us then divide to preserve precision */
3450                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3451                         / 1000;
3452                 line_size = sr_hdisplay * pixel_size;
3453
3454                 /* Use the minimum of the small and large buffer method for primary */
3455                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3456                 large = line_count * line_size;
3457
3458                 entries = DIV_ROUND_UP(min(small, large),
3459                                        ironlake_display_srwm_info.cacheline_size);
3460
3461                 plane_fbc = entries * 64;
3462                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3463
3464                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3465                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3466                         plane_wm = ironlake_display_srwm_info.max_wm;
3467
3468                 /* calculate the self-refresh watermark for display cursor */
3469                 entries = line_count * pixel_size * 64;
3470                 entries = DIV_ROUND_UP(entries,
3471                                        ironlake_cursor_srwm_info.cacheline_size);
3472
3473                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3474                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3475                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3476
3477                 /* configure watermark and enable self-refresh */
3478                 tmp = (WM1_LP_SR_EN |
3479                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3480                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3481                        (plane_wm << WM1_LP_SR_SHIFT) |
3482                        cursor_wm);
3483                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3484                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3485         }
3486         I915_WRITE(WM1_LP_ILK, tmp);
3487         /* XXX setup WM2 and WM3 */
3488 }
3489
3490 /**
3491  * intel_update_watermarks - update FIFO watermark values based on current modes
3492  *
3493  * Calculate watermark values for the various WM regs based on current mode
3494  * and plane configuration.
3495  *
3496  * There are several cases to deal with here:
3497  *   - normal (i.e. non-self-refresh)
3498  *   - self-refresh (SR) mode
3499  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3500  *   - lines are small relative to FIFO size (buffer can hold more than 2
3501  *     lines), so need to account for TLB latency
3502  *
3503  *   The normal calculation is:
3504  *     watermark = dotclock * bytes per pixel * latency
3505  *   where latency is platform & configuration dependent (we assume pessimal
3506  *   values here).
3507  *
3508  *   The SR calculation is:
3509  *     watermark = (trunc(latency/line time)+1) * surface width *
3510  *       bytes per pixel
3511  *   where
3512  *     line time = htotal / dotclock
3513  *     surface width = hdisplay for normal plane and 64 for cursor
3514  *   and latency is assumed to be high, as above.
3515  *
3516  * The final value programmed to the register should always be rounded up,
3517  * and include an extra 2 entries to account for clock crossings.
3518  *
3519  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3520  * to set the non-SR watermarks to 8.
3521  */
3522 static void intel_update_watermarks(struct drm_device *dev)
3523 {
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         struct drm_crtc *crtc;
3526         int sr_hdisplay = 0;
3527         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3528         int enabled = 0, pixel_size = 0;
3529         int sr_htotal = 0;
3530
3531         if (!dev_priv->display.update_wm)
3532                 return;
3533
3534         /* Get the clock config from both planes */
3535         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3536                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3537                 if (intel_crtc->active) {
3538                         enabled++;
3539                         if (intel_crtc->plane == 0) {
3540                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3541                                               intel_crtc->pipe, crtc->mode.clock);
3542                                 planea_clock = crtc->mode.clock;
3543                         } else {
3544                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3545                                               intel_crtc->pipe, crtc->mode.clock);
3546                                 planeb_clock = crtc->mode.clock;
3547                         }
3548                         sr_hdisplay = crtc->mode.hdisplay;
3549                         sr_clock = crtc->mode.clock;
3550                         sr_htotal = crtc->mode.htotal;
3551                         if (crtc->fb)
3552                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3553                         else
3554                                 pixel_size = 4; /* by default */
3555                 }
3556         }
3557
3558         if (enabled <= 0)
3559                 return;
3560
3561         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3562                                     sr_hdisplay, sr_htotal, pixel_size);
3563 }
3564
3565 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3566                                struct drm_display_mode *mode,
3567                                struct drm_display_mode *adjusted_mode,
3568                                int x, int y,
3569                                struct drm_framebuffer *old_fb)
3570 {
3571         struct drm_device *dev = crtc->dev;
3572         struct drm_i915_private *dev_priv = dev->dev_private;
3573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3574         int pipe = intel_crtc->pipe;
3575         int plane = intel_crtc->plane;
3576         u32 fp_reg, dpll_reg;
3577         int refclk, num_connectors = 0;
3578         intel_clock_t clock, reduced_clock;
3579         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3580         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3581         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3582         struct intel_encoder *has_edp_encoder = NULL;
3583         struct drm_mode_config *mode_config = &dev->mode_config;
3584         struct intel_encoder *encoder;
3585         const intel_limit_t *limit;
3586         int ret;
3587         struct fdi_m_n m_n = {0};
3588         u32 reg, temp;
3589         int target_clock;
3590
3591         drm_vblank_pre_modeset(dev, pipe);
3592
3593         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3594                 if (encoder->base.crtc != crtc)
3595                         continue;
3596
3597                 switch (encoder->type) {
3598                 case INTEL_OUTPUT_LVDS:
3599                         is_lvds = true;
3600                         break;
3601                 case INTEL_OUTPUT_SDVO:
3602                 case INTEL_OUTPUT_HDMI:
3603                         is_sdvo = true;
3604                         if (encoder->needs_tv_clock)
3605                                 is_tv = true;
3606                         break;
3607                 case INTEL_OUTPUT_DVO:
3608                         is_dvo = true;
3609                         break;
3610                 case INTEL_OUTPUT_TVOUT:
3611                         is_tv = true;
3612                         break;
3613                 case INTEL_OUTPUT_ANALOG:
3614                         is_crt = true;
3615                         break;
3616                 case INTEL_OUTPUT_DISPLAYPORT:
3617                         is_dp = true;
3618                         break;
3619                 case INTEL_OUTPUT_EDP:
3620                         has_edp_encoder = encoder;
3621                         break;
3622                 }
3623
3624                 num_connectors++;
3625         }
3626
3627         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3628                 refclk = dev_priv->lvds_ssc_freq * 1000;
3629                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3630                               refclk / 1000);
3631         } else if (!IS_GEN2(dev)) {
3632                 refclk = 96000;
3633                 if (HAS_PCH_SPLIT(dev) &&
3634                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3635                         refclk = 120000; /* 120Mhz refclk */
3636         } else {
3637                 refclk = 48000;
3638         }
3639
3640         /*
3641          * Returns a set of divisors for the desired target clock with the given
3642          * refclk, or FALSE.  The returned values represent the clock equation:
3643          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3644          */
3645         limit = intel_limit(crtc);
3646         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3647         if (!ok) {
3648                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3649                 drm_vblank_post_modeset(dev, pipe);
3650                 return -EINVAL;
3651         }
3652
3653         /* Ensure that the cursor is valid for the new mode before changing... */
3654         intel_crtc_update_cursor(crtc, true);
3655
3656         if (is_lvds && dev_priv->lvds_downclock_avail) {
3657                 has_reduced_clock = limit->find_pll(limit, crtc,
3658                                                     dev_priv->lvds_downclock,
3659                                                     refclk,
3660                                                     &reduced_clock);
3661                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3662                         /*
3663                          * If the different P is found, it means that we can't
3664                          * switch the display clock by using the FP0/FP1.
3665                          * In such case we will disable the LVDS downclock
3666                          * feature.
3667                          */
3668                         DRM_DEBUG_KMS("Different P is found for "
3669                                       "LVDS clock/downclock\n");
3670                         has_reduced_clock = 0;
3671                 }
3672         }
3673         /* SDVO TV has fixed PLL values depend on its clock range,
3674            this mirrors vbios setting. */
3675         if (is_sdvo && is_tv) {
3676                 if (adjusted_mode->clock >= 100000
3677                     && adjusted_mode->clock < 140500) {
3678                         clock.p1 = 2;
3679                         clock.p2 = 10;
3680                         clock.n = 3;
3681                         clock.m1 = 16;
3682                         clock.m2 = 8;
3683                 } else if (adjusted_mode->clock >= 140500
3684                            && adjusted_mode->clock <= 200000) {
3685                         clock.p1 = 1;
3686                         clock.p2 = 10;
3687                         clock.n = 6;
3688                         clock.m1 = 12;
3689                         clock.m2 = 8;
3690                 }
3691         }
3692
3693         /* FDI link */
3694         if (HAS_PCH_SPLIT(dev)) {
3695                 int lane = 0, link_bw, bpp;
3696                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3697                    according to current link config */
3698                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3699                         target_clock = mode->clock;
3700                         intel_edp_link_config(has_edp_encoder,
3701                                               &lane, &link_bw);
3702                 } else {
3703                         /* [e]DP over FDI requires target mode clock
3704                            instead of link clock */
3705                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3706                                 target_clock = mode->clock;
3707                         else
3708                                 target_clock = adjusted_mode->clock;
3709
3710                         /* FDI is a binary signal running at ~2.7GHz, encoding
3711                          * each output octet as 10 bits. The actual frequency
3712                          * is stored as a divider into a 100MHz clock, and the
3713                          * mode pixel clock is stored in units of 1KHz.
3714                          * Hence the bw of each lane in terms of the mode signal
3715                          * is:
3716                          */
3717                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3718                 }
3719
3720                 /* determine panel color depth */
3721                 temp = I915_READ(PIPECONF(pipe));
3722                 temp &= ~PIPE_BPC_MASK;
3723                 if (is_lvds) {
3724                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3725                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3726                                 temp |= PIPE_8BPC;
3727                         else
3728                                 temp |= PIPE_6BPC;
3729                 } else if (has_edp_encoder) {
3730                         switch (dev_priv->edp.bpp/3) {
3731                         case 8:
3732                                 temp |= PIPE_8BPC;
3733                                 break;
3734                         case 10:
3735                                 temp |= PIPE_10BPC;
3736                                 break;
3737                         case 6:
3738                                 temp |= PIPE_6BPC;
3739                                 break;
3740                         case 12:
3741                                 temp |= PIPE_12BPC;
3742                                 break;
3743                         }
3744                 } else
3745                         temp |= PIPE_8BPC;
3746                 I915_WRITE(PIPECONF(pipe), temp);
3747
3748                 switch (temp & PIPE_BPC_MASK) {
3749                 case PIPE_8BPC:
3750                         bpp = 24;
3751                         break;
3752                 case PIPE_10BPC:
3753                         bpp = 30;
3754                         break;
3755                 case PIPE_6BPC:
3756                         bpp = 18;
3757                         break;
3758                 case PIPE_12BPC:
3759                         bpp = 36;
3760                         break;
3761                 default:
3762                         DRM_ERROR("unknown pipe bpc value\n");
3763                         bpp = 24;
3764                 }
3765
3766                 if (!lane) {
3767                         /*
3768                          * Account for spread spectrum to avoid
3769                          * oversubscribing the link. Max center spread
3770                          * is 2.5%; use 5% for safety's sake.
3771                          */
3772                         u32 bps = target_clock * bpp * 21 / 20;
3773                         lane = bps / (link_bw * 8) + 1;
3774                 }
3775
3776                 intel_crtc->fdi_lanes = lane;
3777
3778                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3779         }
3780
3781         /* Ironlake: try to setup display ref clock before DPLL
3782          * enabling. This is only under driver's control after
3783          * PCH B stepping, previous chipset stepping should be
3784          * ignoring this setting.
3785          */
3786         if (HAS_PCH_SPLIT(dev)) {
3787                 temp = I915_READ(PCH_DREF_CONTROL);
3788                 /* Always enable nonspread source */
3789                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3790                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3791                 temp &= ~DREF_SSC_SOURCE_MASK;
3792                 temp |= DREF_SSC_SOURCE_ENABLE;
3793                 I915_WRITE(PCH_DREF_CONTROL, temp);
3794
3795                 POSTING_READ(PCH_DREF_CONTROL);
3796                 udelay(200);
3797
3798                 if (has_edp_encoder) {
3799                         if (dev_priv->lvds_use_ssc) {
3800                                 temp |= DREF_SSC1_ENABLE;
3801                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3802
3803                                 POSTING_READ(PCH_DREF_CONTROL);
3804                                 udelay(200);
3805                         }
3806                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3807
3808                         /* Enable CPU source on CPU attached eDP */
3809                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3810                                 if (dev_priv->lvds_use_ssc)
3811                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3812                                 else
3813                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3814                         } else {
3815                                 /* Enable SSC on PCH eDP if needed */
3816                                 if (dev_priv->lvds_use_ssc) {
3817                                         DRM_ERROR("enabling SSC on PCH\n");
3818                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3819                                 }
3820                         }
3821                         I915_WRITE(PCH_DREF_CONTROL, temp);
3822                         POSTING_READ(PCH_DREF_CONTROL);
3823                         udelay(200);
3824                 }
3825         }
3826
3827         if (IS_PINEVIEW(dev)) {
3828                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3829                 if (has_reduced_clock)
3830                         fp2 = (1 << reduced_clock.n) << 16 |
3831                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3832         } else {
3833                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3834                 if (has_reduced_clock)
3835                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3836                                 reduced_clock.m2;
3837         }
3838
3839         dpll = 0;
3840         if (!HAS_PCH_SPLIT(dev))
3841                 dpll = DPLL_VGA_MODE_DIS;
3842
3843         if (!IS_GEN2(dev)) {
3844                 if (is_lvds)
3845                         dpll |= DPLLB_MODE_LVDS;
3846                 else
3847                         dpll |= DPLLB_MODE_DAC_SERIAL;
3848                 if (is_sdvo) {
3849                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3850                         if (pixel_multiplier > 1) {
3851                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3852                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3853                                 else if (HAS_PCH_SPLIT(dev))
3854                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3855                         }
3856                         dpll |= DPLL_DVO_HIGH_SPEED;
3857                 }
3858                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3859                         dpll |= DPLL_DVO_HIGH_SPEED;
3860
3861                 /* compute bitmask from p1 value */
3862                 if (IS_PINEVIEW(dev))
3863                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3864                 else {
3865                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3866                         /* also FPA1 */
3867                         if (HAS_PCH_SPLIT(dev))
3868                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3869                         if (IS_G4X(dev) && has_reduced_clock)
3870                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3871                 }
3872                 switch (clock.p2) {
3873                 case 5:
3874                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3875                         break;
3876                 case 7:
3877                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3878                         break;
3879                 case 10:
3880                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3881                         break;
3882                 case 14:
3883                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3884                         break;
3885                 }
3886                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3887                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3888         } else {
3889                 if (is_lvds) {
3890                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3891                 } else {
3892                         if (clock.p1 == 2)
3893                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3894                         else
3895                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3896                         if (clock.p2 == 4)
3897                                 dpll |= PLL_P2_DIVIDE_BY_4;
3898                 }
3899         }
3900
3901         if (is_sdvo && is_tv)
3902                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3903         else if (is_tv)
3904                 /* XXX: just matching BIOS for now */
3905                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3906                 dpll |= 3;
3907         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3908                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3909         else
3910                 dpll |= PLL_REF_INPUT_DREFCLK;
3911
3912         /* setup pipeconf */
3913         pipeconf = I915_READ(PIPECONF(pipe));
3914
3915         /* Set up the display plane register */
3916         dspcntr = DISPPLANE_GAMMA_ENABLE;
3917
3918         /* Ironlake's plane is forced to pipe, bit 24 is to
3919            enable color space conversion */
3920         if (!HAS_PCH_SPLIT(dev)) {
3921                 if (pipe == 0)
3922                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3923                 else
3924                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3925         }
3926
3927         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3928                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3929                  * core speed.
3930                  *
3931                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3932                  * pipe == 0 check?
3933                  */
3934                 if (mode->clock >
3935                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3936                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3937                 else
3938                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3939         }
3940
3941         dspcntr |= DISPLAY_PLANE_ENABLE;
3942         pipeconf |= PIPECONF_ENABLE;
3943         dpll |= DPLL_VCO_ENABLE;
3944
3945         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3946         drm_mode_debug_printmodeline(mode);
3947
3948         /* assign to Ironlake registers */
3949         if (HAS_PCH_SPLIT(dev)) {
3950                 fp_reg = PCH_FP0(pipe);
3951                 dpll_reg = PCH_DPLL(pipe);
3952         } else {
3953                 fp_reg = FP0(pipe);
3954                 dpll_reg = DPLL(pipe);
3955         }
3956
3957         /* PCH eDP needs FDI, but CPU eDP does not */
3958         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3959                 I915_WRITE(fp_reg, fp);
3960                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3961
3962                 POSTING_READ(dpll_reg);
3963                 udelay(150);
3964         }
3965
3966         /* enable transcoder DPLL */
3967         if (HAS_PCH_CPT(dev)) {
3968                 temp = I915_READ(PCH_DPLL_SEL);
3969                 if (pipe == 0)
3970                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3971                 else
3972                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3973                 I915_WRITE(PCH_DPLL_SEL, temp);
3974
3975                 POSTING_READ(PCH_DPLL_SEL);
3976                 udelay(150);
3977         }
3978
3979         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3980          * This is an exception to the general rule that mode_set doesn't turn
3981          * things on.
3982          */
3983         if (is_lvds) {
3984                 reg = LVDS;
3985                 if (HAS_PCH_SPLIT(dev))
3986                         reg = PCH_LVDS;
3987
3988                 temp = I915_READ(reg);
3989                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3990                 if (pipe == 1) {
3991                         if (HAS_PCH_CPT(dev))
3992                                 temp |= PORT_TRANS_B_SEL_CPT;
3993                         else
3994                                 temp |= LVDS_PIPEB_SELECT;
3995                 } else {
3996                         if (HAS_PCH_CPT(dev))
3997                                 temp &= ~PORT_TRANS_SEL_MASK;
3998                         else
3999                                 temp &= ~LVDS_PIPEB_SELECT;
4000                 }
4001                 /* set the corresponsding LVDS_BORDER bit */
4002                 temp |= dev_priv->lvds_border_bits;
4003                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4004                  * set the DPLLs for dual-channel mode or not.
4005                  */
4006                 if (clock.p2 == 7)
4007                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4008                 else
4009                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4010
4011                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4012                  * appropriately here, but we need to look more thoroughly into how
4013                  * panels behave in the two modes.
4014                  */
4015                 /* set the dithering flag on non-PCH LVDS as needed */
4016                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4017                         if (dev_priv->lvds_dither)
4018                                 temp |= LVDS_ENABLE_DITHER;
4019                         else
4020                                 temp &= ~LVDS_ENABLE_DITHER;
4021                 }
4022                 I915_WRITE(reg, temp);
4023         }
4024
4025         /* set the dithering flag and clear for anything other than a panel. */
4026         if (HAS_PCH_SPLIT(dev)) {
4027                 pipeconf &= ~PIPECONF_DITHER_EN;
4028                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4029                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4030                         pipeconf |= PIPECONF_DITHER_EN;
4031                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4032                 }
4033         }
4034
4035         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4036                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4037         } else if (HAS_PCH_SPLIT(dev)) {
4038                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4039                 if (pipe == 0) {
4040                         I915_WRITE(TRANSA_DATA_M1, 0);
4041                         I915_WRITE(TRANSA_DATA_N1, 0);
4042                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4043                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4044                 } else {
4045                         I915_WRITE(TRANSB_DATA_M1, 0);
4046                         I915_WRITE(TRANSB_DATA_N1, 0);
4047                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4048                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4049                 }
4050         }
4051
4052         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4053                 I915_WRITE(fp_reg, fp);
4054                 I915_WRITE(dpll_reg, dpll);
4055
4056                 /* Wait for the clocks to stabilize. */
4057                 POSTING_READ(dpll_reg);
4058                 udelay(150);
4059
4060                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4061                         temp = 0;
4062                         if (is_sdvo) {
4063                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4064                                 if (temp > 1)
4065                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4066                                 else
4067                                         temp = 0;
4068                         }
4069                         I915_WRITE(DPLL_MD(pipe), temp);
4070                 } else {
4071                         /* write it again -- the BIOS does, after all */
4072                         I915_WRITE(dpll_reg, dpll);
4073                 }
4074
4075                 /* Wait for the clocks to stabilize. */
4076                 POSTING_READ(dpll_reg);
4077                 udelay(150);
4078         }
4079
4080         intel_crtc->lowfreq_avail = false;
4081         if (is_lvds && has_reduced_clock && i915_powersave) {
4082                 I915_WRITE(fp_reg + 4, fp2);
4083                 intel_crtc->lowfreq_avail = true;
4084                 if (HAS_PIPE_CXSR(dev)) {
4085                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4086                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4087                 }
4088         } else {
4089                 I915_WRITE(fp_reg + 4, fp);
4090                 if (HAS_PIPE_CXSR(dev)) {
4091                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4092                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4093                 }
4094         }
4095
4096         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4097                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4098                 /* the chip adds 2 halflines automatically */
4099                 adjusted_mode->crtc_vdisplay -= 1;
4100                 adjusted_mode->crtc_vtotal -= 1;
4101                 adjusted_mode->crtc_vblank_start -= 1;
4102                 adjusted_mode->crtc_vblank_end -= 1;
4103                 adjusted_mode->crtc_vsync_end -= 1;
4104                 adjusted_mode->crtc_vsync_start -= 1;
4105         } else
4106                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4107
4108         I915_WRITE(HTOTAL(pipe),
4109                    (adjusted_mode->crtc_hdisplay - 1) |
4110                    ((adjusted_mode->crtc_htotal - 1) << 16));
4111         I915_WRITE(HBLANK(pipe),
4112                    (adjusted_mode->crtc_hblank_start - 1) |
4113                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4114         I915_WRITE(HSYNC(pipe),
4115                    (adjusted_mode->crtc_hsync_start - 1) |
4116                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4117
4118         I915_WRITE(VTOTAL(pipe),
4119                    (adjusted_mode->crtc_vdisplay - 1) |
4120                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4121         I915_WRITE(VBLANK(pipe),
4122                    (adjusted_mode->crtc_vblank_start - 1) |
4123                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4124         I915_WRITE(VSYNC(pipe),
4125                    (adjusted_mode->crtc_vsync_start - 1) |
4126                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4127
4128         /* pipesrc and dspsize control the size that is scaled from,
4129          * which should always be the user's requested size.
4130          */
4131         if (!HAS_PCH_SPLIT(dev)) {
4132                 I915_WRITE(DSPSIZE(plane),
4133                            ((mode->vdisplay - 1) << 16) |
4134                            (mode->hdisplay - 1));
4135                 I915_WRITE(DSPPOS(plane), 0);
4136         }
4137         I915_WRITE(PIPESRC(pipe),
4138                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4139
4140         if (HAS_PCH_SPLIT(dev)) {
4141                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4142                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4143                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4144                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4145
4146                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4147                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4148                 }
4149         }
4150
4151         I915_WRITE(PIPECONF(pipe), pipeconf);
4152         POSTING_READ(PIPECONF(pipe));
4153
4154         intel_wait_for_vblank(dev, pipe);
4155
4156         if (IS_GEN5(dev)) {
4157                 /* enable address swizzle for tiling buffer */
4158                 temp = I915_READ(DISP_ARB_CTL);
4159                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4160         }
4161
4162         I915_WRITE(DSPCNTR(plane), dspcntr);
4163
4164         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4165
4166         intel_update_watermarks(dev);
4167
4168         drm_vblank_post_modeset(dev, pipe);
4169
4170         return ret;
4171 }
4172
4173 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4174 void intel_crtc_load_lut(struct drm_crtc *crtc)
4175 {
4176         struct drm_device *dev = crtc->dev;
4177         struct drm_i915_private *dev_priv = dev->dev_private;
4178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4180         int i;
4181
4182         /* The clocks have to be on to load the palette. */
4183         if (!crtc->enabled)
4184                 return;
4185
4186         /* use legacy palette for Ironlake */
4187         if (HAS_PCH_SPLIT(dev))
4188                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4189                                                    LGC_PALETTE_B;
4190
4191         for (i = 0; i < 256; i++) {
4192                 I915_WRITE(palreg + 4 * i,
4193                            (intel_crtc->lut_r[i] << 16) |
4194                            (intel_crtc->lut_g[i] << 8) |
4195                            intel_crtc->lut_b[i]);
4196         }
4197 }
4198
4199 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4200 {
4201         struct drm_device *dev = crtc->dev;
4202         struct drm_i915_private *dev_priv = dev->dev_private;
4203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204         bool visible = base != 0;
4205         u32 cntl;
4206
4207         if (intel_crtc->cursor_visible == visible)
4208                 return;
4209
4210         cntl = I915_READ(CURACNTR);
4211         if (visible) {
4212                 /* On these chipsets we can only modify the base whilst
4213                  * the cursor is disabled.
4214                  */
4215                 I915_WRITE(CURABASE, base);
4216
4217                 cntl &= ~(CURSOR_FORMAT_MASK);
4218                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4219                 cntl |= CURSOR_ENABLE |
4220                         CURSOR_GAMMA_ENABLE |
4221                         CURSOR_FORMAT_ARGB;
4222         } else
4223                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4224         I915_WRITE(CURACNTR, cntl);
4225
4226         intel_crtc->cursor_visible = visible;
4227 }
4228
4229 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4230 {
4231         struct drm_device *dev = crtc->dev;
4232         struct drm_i915_private *dev_priv = dev->dev_private;
4233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4234         int pipe = intel_crtc->pipe;
4235         bool visible = base != 0;
4236
4237         if (intel_crtc->cursor_visible != visible) {
4238                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4239                 if (base) {
4240                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4241                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4242                         cntl |= pipe << 28; /* Connect to correct pipe */
4243                 } else {
4244                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4245                         cntl |= CURSOR_MODE_DISABLE;
4246                 }
4247                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4248
4249                 intel_crtc->cursor_visible = visible;
4250         }
4251         /* and commit changes on next vblank */
4252         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4253 }
4254
4255 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4256 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4257                                      bool on)
4258 {
4259         struct drm_device *dev = crtc->dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4262         int pipe = intel_crtc->pipe;
4263         int x = intel_crtc->cursor_x;
4264         int y = intel_crtc->cursor_y;
4265         u32 base, pos;
4266         bool visible;
4267
4268         pos = 0;
4269
4270         if (on && crtc->enabled && crtc->fb) {
4271                 base = intel_crtc->cursor_addr;
4272                 if (x > (int) crtc->fb->width)
4273                         base = 0;
4274
4275                 if (y > (int) crtc->fb->height)
4276                         base = 0;
4277         } else
4278                 base = 0;
4279
4280         if (x < 0) {
4281                 if (x + intel_crtc->cursor_width < 0)
4282                         base = 0;
4283
4284                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4285                 x = -x;
4286         }
4287         pos |= x << CURSOR_X_SHIFT;
4288
4289         if (y < 0) {
4290                 if (y + intel_crtc->cursor_height < 0)
4291                         base = 0;
4292
4293                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4294                 y = -y;
4295         }
4296         pos |= y << CURSOR_Y_SHIFT;
4297
4298         visible = base != 0;
4299         if (!visible && !intel_crtc->cursor_visible)
4300                 return;
4301
4302         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4303         if (IS_845G(dev) || IS_I865G(dev))
4304                 i845_update_cursor(crtc, base);
4305         else
4306                 i9xx_update_cursor(crtc, base);
4307
4308         if (visible)
4309                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4310 }
4311
4312 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4313                                  struct drm_file *file_priv,
4314                                  uint32_t handle,
4315                                  uint32_t width, uint32_t height)
4316 {
4317         struct drm_device *dev = crtc->dev;
4318         struct drm_i915_private *dev_priv = dev->dev_private;
4319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320         struct drm_gem_object *bo;
4321         struct drm_i915_gem_object *obj_priv;
4322         uint32_t addr;
4323         int ret;
4324
4325         DRM_DEBUG_KMS("\n");
4326
4327         /* if we want to turn off the cursor ignore width and height */
4328         if (!handle) {
4329                 DRM_DEBUG_KMS("cursor off\n");
4330                 addr = 0;
4331                 bo = NULL;
4332                 mutex_lock(&dev->struct_mutex);
4333                 goto finish;
4334         }
4335
4336         /* Currently we only support 64x64 cursors */
4337         if (width != 64 || height != 64) {
4338                 DRM_ERROR("we currently only support 64x64 cursors\n");
4339                 return -EINVAL;
4340         }
4341
4342         bo = drm_gem_object_lookup(dev, file_priv, handle);
4343         if (!bo)
4344                 return -ENOENT;
4345
4346         obj_priv = to_intel_bo(bo);
4347
4348         if (bo->size < width * height * 4) {
4349                 DRM_ERROR("buffer is to small\n");
4350                 ret = -ENOMEM;
4351                 goto fail;
4352         }
4353
4354         /* we only need to pin inside GTT if cursor is non-phy */
4355         mutex_lock(&dev->struct_mutex);
4356         if (!dev_priv->info->cursor_needs_physical) {
4357                 ret = i915_gem_object_pin(bo, PAGE_SIZE, true, false);
4358                 if (ret) {
4359                         DRM_ERROR("failed to pin cursor bo\n");
4360                         goto fail_locked;
4361                 }
4362
4363                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4364                 if (ret) {
4365                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4366                         goto fail_unpin;
4367                 }
4368
4369                 addr = obj_priv->gtt_offset;
4370         } else {
4371                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4372                 ret = i915_gem_attach_phys_object(dev, bo,
4373                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4374                                                   align);
4375                 if (ret) {
4376                         DRM_ERROR("failed to attach phys object\n");
4377                         goto fail_locked;
4378                 }
4379                 addr = obj_priv->phys_obj->handle->busaddr;
4380         }
4381
4382         if (IS_GEN2(dev))
4383                 I915_WRITE(CURSIZE, (height << 12) | width);
4384
4385  finish:
4386         if (intel_crtc->cursor_bo) {
4387                 if (dev_priv->info->cursor_needs_physical) {
4388                         if (intel_crtc->cursor_bo != bo)
4389                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4390                 } else
4391                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4392                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4393         }
4394
4395         mutex_unlock(&dev->struct_mutex);
4396
4397         intel_crtc->cursor_addr = addr;
4398         intel_crtc->cursor_bo = bo;
4399         intel_crtc->cursor_width = width;
4400         intel_crtc->cursor_height = height;
4401
4402         intel_crtc_update_cursor(crtc, true);
4403
4404         return 0;
4405 fail_unpin:
4406         i915_gem_object_unpin(bo);
4407 fail_locked:
4408         mutex_unlock(&dev->struct_mutex);
4409 fail:
4410         drm_gem_object_unreference_unlocked(bo);
4411         return ret;
4412 }
4413
4414 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4415 {
4416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417
4418         intel_crtc->cursor_x = x;
4419         intel_crtc->cursor_y = y;
4420
4421         intel_crtc_update_cursor(crtc, true);
4422
4423         return 0;
4424 }
4425
4426 /** Sets the color ramps on behalf of RandR */
4427 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4428                                  u16 blue, int regno)
4429 {
4430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4431
4432         intel_crtc->lut_r[regno] = red >> 8;
4433         intel_crtc->lut_g[regno] = green >> 8;
4434         intel_crtc->lut_b[regno] = blue >> 8;
4435 }
4436
4437 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4438                              u16 *blue, int regno)
4439 {
4440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4441
4442         *red = intel_crtc->lut_r[regno] << 8;
4443         *green = intel_crtc->lut_g[regno] << 8;
4444         *blue = intel_crtc->lut_b[regno] << 8;
4445 }
4446
4447 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4448                                  u16 *blue, uint32_t start, uint32_t size)
4449 {
4450         int end = (start + size > 256) ? 256 : start + size, i;
4451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4452
4453         for (i = start; i < end; i++) {
4454                 intel_crtc->lut_r[i] = red[i] >> 8;
4455                 intel_crtc->lut_g[i] = green[i] >> 8;
4456                 intel_crtc->lut_b[i] = blue[i] >> 8;
4457         }
4458
4459         intel_crtc_load_lut(crtc);
4460 }
4461
4462 /**
4463  * Get a pipe with a simple mode set on it for doing load-based monitor
4464  * detection.
4465  *
4466  * It will be up to the load-detect code to adjust the pipe as appropriate for
4467  * its requirements.  The pipe will be connected to no other encoders.
4468  *
4469  * Currently this code will only succeed if there is a pipe with no encoders
4470  * configured for it.  In the future, it could choose to temporarily disable
4471  * some outputs to free up a pipe for its use.
4472  *
4473  * \return crtc, or NULL if no pipes are available.
4474  */
4475
4476 /* VESA 640x480x72Hz mode to set on the pipe */
4477 static struct drm_display_mode load_detect_mode = {
4478         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4479                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4480 };
4481
4482 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4483                                             struct drm_connector *connector,
4484                                             struct drm_display_mode *mode,
4485                                             int *dpms_mode)
4486 {
4487         struct intel_crtc *intel_crtc;
4488         struct drm_crtc *possible_crtc;
4489         struct drm_crtc *supported_crtc =NULL;
4490         struct drm_encoder *encoder = &intel_encoder->base;
4491         struct drm_crtc *crtc = NULL;
4492         struct drm_device *dev = encoder->dev;
4493         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4494         struct drm_crtc_helper_funcs *crtc_funcs;
4495         int i = -1;
4496
4497         /*
4498          * Algorithm gets a little messy:
4499          *   - if the connector already has an assigned crtc, use it (but make
4500          *     sure it's on first)
4501          *   - try to find the first unused crtc that can drive this connector,
4502          *     and use that if we find one
4503          *   - if there are no unused crtcs available, try to use the first
4504          *     one we found that supports the connector
4505          */
4506
4507         /* See if we already have a CRTC for this connector */
4508         if (encoder->crtc) {
4509                 crtc = encoder->crtc;
4510                 /* Make sure the crtc and connector are running */
4511                 intel_crtc = to_intel_crtc(crtc);
4512                 *dpms_mode = intel_crtc->dpms_mode;
4513                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4514                         crtc_funcs = crtc->helper_private;
4515                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4516                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4517                 }
4518                 return crtc;
4519         }
4520
4521         /* Find an unused one (if possible) */
4522         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4523                 i++;
4524                 if (!(encoder->possible_crtcs & (1 << i)))
4525                         continue;
4526                 if (!possible_crtc->enabled) {
4527                         crtc = possible_crtc;
4528                         break;
4529                 }
4530                 if (!supported_crtc)
4531                         supported_crtc = possible_crtc;
4532         }
4533
4534         /*
4535          * If we didn't find an unused CRTC, don't use any.
4536          */
4537         if (!crtc) {
4538                 return NULL;
4539         }
4540
4541         encoder->crtc = crtc;
4542         connector->encoder = encoder;
4543         intel_encoder->load_detect_temp = true;
4544
4545         intel_crtc = to_intel_crtc(crtc);
4546         *dpms_mode = intel_crtc->dpms_mode;
4547
4548         if (!crtc->enabled) {
4549                 if (!mode)
4550                         mode = &load_detect_mode;
4551                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4552         } else {
4553                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4554                         crtc_funcs = crtc->helper_private;
4555                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4556                 }
4557
4558                 /* Add this connector to the crtc */
4559                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4560                 encoder_funcs->commit(encoder);
4561         }
4562         /* let the connector get through one full cycle before testing */
4563         intel_wait_for_vblank(dev, intel_crtc->pipe);
4564
4565         return crtc;
4566 }
4567
4568 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4569                                     struct drm_connector *connector, int dpms_mode)
4570 {
4571         struct drm_encoder *encoder = &intel_encoder->base;
4572         struct drm_device *dev = encoder->dev;
4573         struct drm_crtc *crtc = encoder->crtc;
4574         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4575         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4576
4577         if (intel_encoder->load_detect_temp) {
4578                 encoder->crtc = NULL;
4579                 connector->encoder = NULL;
4580                 intel_encoder->load_detect_temp = false;
4581                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4582                 drm_helper_disable_unused_functions(dev);
4583         }
4584
4585         /* Switch crtc and encoder back off if necessary */
4586         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4587                 if (encoder->crtc == crtc)
4588                         encoder_funcs->dpms(encoder, dpms_mode);
4589                 crtc_funcs->dpms(crtc, dpms_mode);
4590         }
4591 }
4592
4593 /* Returns the clock of the currently programmed mode of the given pipe. */
4594 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4595 {
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         int pipe = intel_crtc->pipe;
4599         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4600         u32 fp;
4601         intel_clock_t clock;
4602
4603         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4604                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4605         else
4606                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4607
4608         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4609         if (IS_PINEVIEW(dev)) {
4610                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4611                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4612         } else {
4613                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4614                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4615         }
4616
4617         if (!IS_GEN2(dev)) {
4618                 if (IS_PINEVIEW(dev))
4619                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4620                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4621                 else
4622                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4623                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4624
4625                 switch (dpll & DPLL_MODE_MASK) {
4626                 case DPLLB_MODE_DAC_SERIAL:
4627                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4628                                 5 : 10;
4629                         break;
4630                 case DPLLB_MODE_LVDS:
4631                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4632                                 7 : 14;
4633                         break;
4634                 default:
4635                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4636                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4637                         return 0;
4638                 }
4639
4640                 /* XXX: Handle the 100Mhz refclk */
4641                 intel_clock(dev, 96000, &clock);
4642         } else {
4643                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4644
4645                 if (is_lvds) {
4646                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4647                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4648                         clock.p2 = 14;
4649
4650                         if ((dpll & PLL_REF_INPUT_MASK) ==
4651                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4652                                 /* XXX: might not be 66MHz */
4653                                 intel_clock(dev, 66000, &clock);
4654                         } else
4655                                 intel_clock(dev, 48000, &clock);
4656                 } else {
4657                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4658                                 clock.p1 = 2;
4659                         else {
4660                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4661                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4662                         }
4663                         if (dpll & PLL_P2_DIVIDE_BY_4)
4664                                 clock.p2 = 4;
4665                         else
4666                                 clock.p2 = 2;
4667
4668                         intel_clock(dev, 48000, &clock);
4669                 }
4670         }
4671
4672         /* XXX: It would be nice to validate the clocks, but we can't reuse
4673          * i830PllIsValid() because it relies on the xf86_config connector
4674          * configuration being accurate, which it isn't necessarily.
4675          */
4676
4677         return clock.dot;
4678 }
4679
4680 /** Returns the currently programmed mode of the given pipe. */
4681 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4682                                              struct drm_crtc *crtc)
4683 {
4684         struct drm_i915_private *dev_priv = dev->dev_private;
4685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4686         int pipe = intel_crtc->pipe;
4687         struct drm_display_mode *mode;
4688         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4689         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4690         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4691         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4692
4693         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4694         if (!mode)
4695                 return NULL;
4696
4697         mode->clock = intel_crtc_clock_get(dev, crtc);
4698         mode->hdisplay = (htot & 0xffff) + 1;
4699         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4700         mode->hsync_start = (hsync & 0xffff) + 1;
4701         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4702         mode->vdisplay = (vtot & 0xffff) + 1;
4703         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4704         mode->vsync_start = (vsync & 0xffff) + 1;
4705         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4706
4707         drm_mode_set_name(mode);
4708         drm_mode_set_crtcinfo(mode, 0);
4709
4710         return mode;
4711 }
4712
4713 #define GPU_IDLE_TIMEOUT 500 /* ms */
4714
4715 /* When this timer fires, we've been idle for awhile */
4716 static void intel_gpu_idle_timer(unsigned long arg)
4717 {
4718         struct drm_device *dev = (struct drm_device *)arg;
4719         drm_i915_private_t *dev_priv = dev->dev_private;
4720
4721         dev_priv->busy = false;
4722
4723         queue_work(dev_priv->wq, &dev_priv->idle_work);
4724 }
4725
4726 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4727
4728 static void intel_crtc_idle_timer(unsigned long arg)
4729 {
4730         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4731         struct drm_crtc *crtc = &intel_crtc->base;
4732         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4733
4734         intel_crtc->busy = false;
4735
4736         queue_work(dev_priv->wq, &dev_priv->idle_work);
4737 }
4738
4739 static void intel_increase_pllclock(struct drm_crtc *crtc)
4740 {
4741         struct drm_device *dev = crtc->dev;
4742         drm_i915_private_t *dev_priv = dev->dev_private;
4743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744         int pipe = intel_crtc->pipe;
4745         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4746         int dpll = I915_READ(dpll_reg);
4747
4748         if (HAS_PCH_SPLIT(dev))
4749                 return;
4750
4751         if (!dev_priv->lvds_downclock_avail)
4752                 return;
4753
4754         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4755                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4756
4757                 /* Unlock panel regs */
4758                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4759                            PANEL_UNLOCK_REGS);
4760
4761                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4762                 I915_WRITE(dpll_reg, dpll);
4763                 dpll = I915_READ(dpll_reg);
4764                 intel_wait_for_vblank(dev, pipe);
4765                 dpll = I915_READ(dpll_reg);
4766                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4767                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4768
4769                 /* ...and lock them again */
4770                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4771         }
4772
4773         /* Schedule downclock */
4774         mod_timer(&intel_crtc->idle_timer, jiffies +
4775                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4776 }
4777
4778 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4779 {
4780         struct drm_device *dev = crtc->dev;
4781         drm_i915_private_t *dev_priv = dev->dev_private;
4782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783         int pipe = intel_crtc->pipe;
4784         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4785         int dpll = I915_READ(dpll_reg);
4786
4787         if (HAS_PCH_SPLIT(dev))
4788                 return;
4789
4790         if (!dev_priv->lvds_downclock_avail)
4791                 return;
4792
4793         /*
4794          * Since this is called by a timer, we should never get here in
4795          * the manual case.
4796          */
4797         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4798                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4799
4800                 /* Unlock panel regs */
4801                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4802                            PANEL_UNLOCK_REGS);
4803
4804                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4805                 I915_WRITE(dpll_reg, dpll);
4806                 dpll = I915_READ(dpll_reg);
4807                 intel_wait_for_vblank(dev, pipe);
4808                 dpll = I915_READ(dpll_reg);
4809                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4810                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4811
4812                 /* ...and lock them again */
4813                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4814         }
4815
4816 }
4817
4818 /**
4819  * intel_idle_update - adjust clocks for idleness
4820  * @work: work struct
4821  *
4822  * Either the GPU or display (or both) went idle.  Check the busy status
4823  * here and adjust the CRTC and GPU clocks as necessary.
4824  */
4825 static void intel_idle_update(struct work_struct *work)
4826 {
4827         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4828                                                     idle_work);
4829         struct drm_device *dev = dev_priv->dev;
4830         struct drm_crtc *crtc;
4831         struct intel_crtc *intel_crtc;
4832         int enabled = 0;
4833
4834         if (!i915_powersave)
4835                 return;
4836
4837         mutex_lock(&dev->struct_mutex);
4838
4839         i915_update_gfx_val(dev_priv);
4840
4841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4842                 /* Skip inactive CRTCs */
4843                 if (!crtc->fb)
4844                         continue;
4845
4846                 enabled++;
4847                 intel_crtc = to_intel_crtc(crtc);
4848                 if (!intel_crtc->busy)
4849                         intel_decrease_pllclock(crtc);
4850         }
4851
4852         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4853                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4854                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4855         }
4856
4857         mutex_unlock(&dev->struct_mutex);
4858 }
4859
4860 /**
4861  * intel_mark_busy - mark the GPU and possibly the display busy
4862  * @dev: drm device
4863  * @obj: object we're operating on
4864  *
4865  * Callers can use this function to indicate that the GPU is busy processing
4866  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4867  * buffer), we'll also mark the display as busy, so we know to increase its
4868  * clock frequency.
4869  */
4870 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4871 {
4872         drm_i915_private_t *dev_priv = dev->dev_private;
4873         struct drm_crtc *crtc = NULL;
4874         struct intel_framebuffer *intel_fb;
4875         struct intel_crtc *intel_crtc;
4876
4877         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4878                 return;
4879
4880         if (!dev_priv->busy) {
4881                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4882                         u32 fw_blc_self;
4883
4884                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4885                         fw_blc_self = I915_READ(FW_BLC_SELF);
4886                         fw_blc_self &= ~FW_BLC_SELF_EN;
4887                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4888                 }
4889                 dev_priv->busy = true;
4890         } else
4891                 mod_timer(&dev_priv->idle_timer, jiffies +
4892                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4893
4894         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4895                 if (!crtc->fb)
4896                         continue;
4897
4898                 intel_crtc = to_intel_crtc(crtc);
4899                 intel_fb = to_intel_framebuffer(crtc->fb);
4900                 if (intel_fb->obj == obj) {
4901                         if (!intel_crtc->busy) {
4902                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4903                                         u32 fw_blc_self;
4904
4905                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4906                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4907                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4908                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4909                                 }
4910                                 /* Non-busy -> busy, upclock */
4911                                 intel_increase_pllclock(crtc);
4912                                 intel_crtc->busy = true;
4913                         } else {
4914                                 /* Busy -> busy, put off timer */
4915                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4916                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4917                         }
4918                 }
4919         }
4920 }
4921
4922 static void intel_crtc_destroy(struct drm_crtc *crtc)
4923 {
4924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4925         struct drm_device *dev = crtc->dev;
4926         struct intel_unpin_work *work;
4927         unsigned long flags;
4928
4929         spin_lock_irqsave(&dev->event_lock, flags);
4930         work = intel_crtc->unpin_work;
4931         intel_crtc->unpin_work = NULL;
4932         spin_unlock_irqrestore(&dev->event_lock, flags);
4933
4934         if (work) {
4935                 cancel_work_sync(&work->work);
4936                 kfree(work);
4937         }
4938
4939         drm_crtc_cleanup(crtc);
4940
4941         kfree(intel_crtc);
4942 }
4943
4944 static void intel_unpin_work_fn(struct work_struct *__work)
4945 {
4946         struct intel_unpin_work *work =
4947                 container_of(__work, struct intel_unpin_work, work);
4948
4949         mutex_lock(&work->dev->struct_mutex);
4950         i915_gem_object_unpin(work->old_fb_obj);
4951         drm_gem_object_unreference(work->pending_flip_obj);
4952         drm_gem_object_unreference(work->old_fb_obj);
4953         mutex_unlock(&work->dev->struct_mutex);
4954         kfree(work);
4955 }
4956
4957 static void do_intel_finish_page_flip(struct drm_device *dev,
4958                                       struct drm_crtc *crtc)
4959 {
4960         drm_i915_private_t *dev_priv = dev->dev_private;
4961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962         struct intel_unpin_work *work;
4963         struct drm_i915_gem_object *obj_priv;
4964         struct drm_pending_vblank_event *e;
4965         struct timeval now;
4966         unsigned long flags;
4967
4968         /* Ignore early vblank irqs */
4969         if (intel_crtc == NULL)
4970                 return;
4971
4972         spin_lock_irqsave(&dev->event_lock, flags);
4973         work = intel_crtc->unpin_work;
4974         if (work == NULL || !work->pending) {
4975                 spin_unlock_irqrestore(&dev->event_lock, flags);
4976                 return;
4977         }
4978
4979         intel_crtc->unpin_work = NULL;
4980         drm_vblank_put(dev, intel_crtc->pipe);
4981
4982         if (work->event) {
4983                 e = work->event;
4984                 do_gettimeofday(&now);
4985                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4986                 e->event.tv_sec = now.tv_sec;
4987                 e->event.tv_usec = now.tv_usec;
4988                 list_add_tail(&e->base.link,
4989                               &e->base.file_priv->event_list);
4990                 wake_up_interruptible(&e->base.file_priv->event_wait);
4991         }
4992
4993         spin_unlock_irqrestore(&dev->event_lock, flags);
4994
4995         obj_priv = to_intel_bo(work->old_fb_obj);
4996         atomic_clear_mask(1 << intel_crtc->plane,
4997                           &obj_priv->pending_flip.counter);
4998         if (atomic_read(&obj_priv->pending_flip) == 0)
4999                 wake_up(&dev_priv->pending_flip_queue);
5000         schedule_work(&work->work);
5001
5002         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5003 }
5004
5005 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5006 {
5007         drm_i915_private_t *dev_priv = dev->dev_private;
5008         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5009
5010         do_intel_finish_page_flip(dev, crtc);
5011 }
5012
5013 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5014 {
5015         drm_i915_private_t *dev_priv = dev->dev_private;
5016         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5017
5018         do_intel_finish_page_flip(dev, crtc);
5019 }
5020
5021 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5022 {
5023         drm_i915_private_t *dev_priv = dev->dev_private;
5024         struct intel_crtc *intel_crtc =
5025                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5026         unsigned long flags;
5027
5028         spin_lock_irqsave(&dev->event_lock, flags);
5029         if (intel_crtc->unpin_work) {
5030                 if ((++intel_crtc->unpin_work->pending) > 1)
5031                         DRM_ERROR("Prepared flip multiple times\n");
5032         } else {
5033                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5034         }
5035         spin_unlock_irqrestore(&dev->event_lock, flags);
5036 }
5037
5038 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5039                                 struct drm_framebuffer *fb,
5040                                 struct drm_pending_vblank_event *event)
5041 {
5042         struct drm_device *dev = crtc->dev;
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         struct intel_framebuffer *intel_fb;
5045         struct drm_i915_gem_object *obj_priv;
5046         struct drm_gem_object *obj;
5047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048         struct intel_unpin_work *work;
5049         unsigned long flags, offset;
5050         int pipe = intel_crtc->pipe;
5051         u32 pf, pipesrc;
5052         int ret;
5053
5054         work = kzalloc(sizeof *work, GFP_KERNEL);
5055         if (work == NULL)
5056                 return -ENOMEM;
5057
5058         work->event = event;
5059         work->dev = crtc->dev;
5060         intel_fb = to_intel_framebuffer(crtc->fb);
5061         work->old_fb_obj = intel_fb->obj;
5062         INIT_WORK(&work->work, intel_unpin_work_fn);
5063
5064         /* We borrow the event spin lock for protecting unpin_work */
5065         spin_lock_irqsave(&dev->event_lock, flags);
5066         if (intel_crtc->unpin_work) {
5067                 spin_unlock_irqrestore(&dev->event_lock, flags);
5068                 kfree(work);
5069
5070                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5071                 return -EBUSY;
5072         }
5073         intel_crtc->unpin_work = work;
5074         spin_unlock_irqrestore(&dev->event_lock, flags);
5075
5076         intel_fb = to_intel_framebuffer(fb);
5077         obj = intel_fb->obj;
5078
5079         mutex_lock(&dev->struct_mutex);
5080         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5081         if (ret)
5082                 goto cleanup_work;
5083
5084         /* Reference the objects for the scheduled work. */
5085         drm_gem_object_reference(work->old_fb_obj);
5086         drm_gem_object_reference(obj);
5087
5088         crtc->fb = fb;
5089
5090         ret = drm_vblank_get(dev, intel_crtc->pipe);
5091         if (ret)
5092                 goto cleanup_objs;
5093
5094         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5095                 u32 flip_mask;
5096
5097                 /* Can't queue multiple flips, so wait for the previous
5098                  * one to finish before executing the next.
5099                  */
5100                 ret = BEGIN_LP_RING(2);
5101                 if (ret)
5102                         goto cleanup_objs;
5103
5104                 if (intel_crtc->plane)
5105                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5106                 else
5107                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5108                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5109                 OUT_RING(MI_NOOP);
5110                 ADVANCE_LP_RING();
5111         }
5112
5113         work->pending_flip_obj = obj;
5114         obj_priv = to_intel_bo(obj);
5115
5116         work->enable_stall_check = true;
5117
5118         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5119         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5120
5121         ret = BEGIN_LP_RING(4);
5122         if (ret)
5123                 goto cleanup_objs;
5124
5125         /* Block clients from rendering to the new back buffer until
5126          * the flip occurs and the object is no longer visible.
5127          */
5128         atomic_add(1 << intel_crtc->plane,
5129                    &to_intel_bo(work->old_fb_obj)->pending_flip);
5130
5131         switch (INTEL_INFO(dev)->gen) {
5132         case 2:
5133                 OUT_RING(MI_DISPLAY_FLIP |
5134                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5135                 OUT_RING(fb->pitch);
5136                 OUT_RING(obj_priv->gtt_offset + offset);
5137                 OUT_RING(MI_NOOP);
5138                 break;
5139
5140         case 3:
5141                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5142                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5143                 OUT_RING(fb->pitch);
5144                 OUT_RING(obj_priv->gtt_offset + offset);
5145                 OUT_RING(MI_NOOP);
5146                 break;
5147
5148         case 4:
5149         case 5:
5150                 /* i965+ uses the linear or tiled offsets from the
5151                  * Display Registers (which do not change across a page-flip)
5152                  * so we need only reprogram the base address.
5153                  */
5154                 OUT_RING(MI_DISPLAY_FLIP |
5155                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5156                 OUT_RING(fb->pitch);
5157                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5158
5159                 /* XXX Enabling the panel-fitter across page-flip is so far
5160                  * untested on non-native modes, so ignore it for now.
5161                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5162                  */
5163                 pf = 0;
5164                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5165                 OUT_RING(pf | pipesrc);
5166                 break;
5167
5168         case 6:
5169                 OUT_RING(MI_DISPLAY_FLIP |
5170                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5171                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5172                 OUT_RING(obj_priv->gtt_offset);
5173
5174                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5175                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5176                 OUT_RING(pf | pipesrc);
5177                 break;
5178         }
5179         ADVANCE_LP_RING();
5180
5181         mutex_unlock(&dev->struct_mutex);
5182
5183         trace_i915_flip_request(intel_crtc->plane, obj);
5184
5185         return 0;
5186
5187 cleanup_objs:
5188         drm_gem_object_unreference(work->old_fb_obj);
5189         drm_gem_object_unreference(obj);
5190 cleanup_work:
5191         mutex_unlock(&dev->struct_mutex);
5192
5193         spin_lock_irqsave(&dev->event_lock, flags);
5194         intel_crtc->unpin_work = NULL;
5195         spin_unlock_irqrestore(&dev->event_lock, flags);
5196
5197         kfree(work);
5198
5199         return ret;
5200 }
5201
5202 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5203         .dpms = intel_crtc_dpms,
5204         .mode_fixup = intel_crtc_mode_fixup,
5205         .mode_set = intel_crtc_mode_set,
5206         .mode_set_base = intel_pipe_set_base,
5207         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5208         .load_lut = intel_crtc_load_lut,
5209         .disable = intel_crtc_disable,
5210 };
5211
5212 static const struct drm_crtc_funcs intel_crtc_funcs = {
5213         .cursor_set = intel_crtc_cursor_set,
5214         .cursor_move = intel_crtc_cursor_move,
5215         .gamma_set = intel_crtc_gamma_set,
5216         .set_config = drm_crtc_helper_set_config,
5217         .destroy = intel_crtc_destroy,
5218         .page_flip = intel_crtc_page_flip,
5219 };
5220
5221
5222 static void intel_crtc_init(struct drm_device *dev, int pipe)
5223 {
5224         drm_i915_private_t *dev_priv = dev->dev_private;
5225         struct intel_crtc *intel_crtc;
5226         int i;
5227
5228         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5229         if (intel_crtc == NULL)
5230                 return;
5231
5232         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5233
5234         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5235         for (i = 0; i < 256; i++) {
5236                 intel_crtc->lut_r[i] = i;
5237                 intel_crtc->lut_g[i] = i;
5238                 intel_crtc->lut_b[i] = i;
5239         }
5240
5241         /* Swap pipes & planes for FBC on pre-965 */
5242         intel_crtc->pipe = pipe;
5243         intel_crtc->plane = pipe;
5244         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5245                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5246                 intel_crtc->plane = !pipe;
5247         }
5248
5249         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5250                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5251         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5252         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5253
5254         intel_crtc->cursor_addr = 0;
5255         intel_crtc->dpms_mode = -1;
5256         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5257
5258         if (HAS_PCH_SPLIT(dev)) {
5259                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5260                 intel_helper_funcs.commit = ironlake_crtc_commit;
5261         } else {
5262                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5263                 intel_helper_funcs.commit = i9xx_crtc_commit;
5264         }
5265
5266         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5267
5268         intel_crtc->busy = false;
5269
5270         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5271                     (unsigned long)intel_crtc);
5272 }
5273
5274 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5275                                 struct drm_file *file_priv)
5276 {
5277         drm_i915_private_t *dev_priv = dev->dev_private;
5278         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5279         struct drm_mode_object *drmmode_obj;
5280         struct intel_crtc *crtc;
5281
5282         if (!dev_priv) {
5283                 DRM_ERROR("called with no initialization\n");
5284                 return -EINVAL;
5285         }
5286
5287         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5288                         DRM_MODE_OBJECT_CRTC);
5289
5290         if (!drmmode_obj) {
5291                 DRM_ERROR("no such CRTC id\n");
5292                 return -EINVAL;
5293         }
5294
5295         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5296         pipe_from_crtc_id->pipe = crtc->pipe;
5297
5298         return 0;
5299 }
5300
5301 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5302 {
5303         struct intel_encoder *encoder;
5304         int index_mask = 0;
5305         int entry = 0;
5306
5307         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5308                 if (type_mask & encoder->clone_mask)
5309                         index_mask |= (1 << entry);
5310                 entry++;
5311         }
5312
5313         return index_mask;
5314 }
5315
5316 static void intel_setup_outputs(struct drm_device *dev)
5317 {
5318         struct drm_i915_private *dev_priv = dev->dev_private;
5319         struct intel_encoder *encoder;
5320         bool dpd_is_edp = false;
5321
5322         if (IS_MOBILE(dev) && !IS_I830(dev))
5323                 intel_lvds_init(dev);
5324
5325         if (HAS_PCH_SPLIT(dev)) {
5326                 dpd_is_edp = intel_dpd_is_edp(dev);
5327
5328                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5329                         intel_dp_init(dev, DP_A);
5330
5331                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5332                         intel_dp_init(dev, PCH_DP_D);
5333         }
5334
5335         intel_crt_init(dev);
5336
5337         if (HAS_PCH_SPLIT(dev)) {
5338                 int found;
5339
5340                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5341                         /* PCH SDVOB multiplex with HDMIB */
5342                         found = intel_sdvo_init(dev, PCH_SDVOB);
5343                         if (!found)
5344                                 intel_hdmi_init(dev, HDMIB);
5345                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5346                                 intel_dp_init(dev, PCH_DP_B);
5347                 }
5348
5349                 if (I915_READ(HDMIC) & PORT_DETECTED)
5350                         intel_hdmi_init(dev, HDMIC);
5351
5352                 if (I915_READ(HDMID) & PORT_DETECTED)
5353                         intel_hdmi_init(dev, HDMID);
5354
5355                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5356                         intel_dp_init(dev, PCH_DP_C);
5357
5358                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5359                         intel_dp_init(dev, PCH_DP_D);
5360
5361         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5362                 bool found = false;
5363
5364                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5365                         DRM_DEBUG_KMS("probing SDVOB\n");
5366                         found = intel_sdvo_init(dev, SDVOB);
5367                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5368                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5369                                 intel_hdmi_init(dev, SDVOB);
5370                         }
5371
5372                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5373                                 DRM_DEBUG_KMS("probing DP_B\n");
5374                                 intel_dp_init(dev, DP_B);
5375                         }
5376                 }
5377
5378                 /* Before G4X SDVOC doesn't have its own detect register */
5379
5380                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5381                         DRM_DEBUG_KMS("probing SDVOC\n");
5382                         found = intel_sdvo_init(dev, SDVOC);
5383                 }
5384
5385                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5386
5387                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5388                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5389                                 intel_hdmi_init(dev, SDVOC);
5390                         }
5391                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5392                                 DRM_DEBUG_KMS("probing DP_C\n");
5393                                 intel_dp_init(dev, DP_C);
5394                         }
5395                 }
5396
5397                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5398                     (I915_READ(DP_D) & DP_DETECTED)) {
5399                         DRM_DEBUG_KMS("probing DP_D\n");
5400                         intel_dp_init(dev, DP_D);
5401                 }
5402         } else if (IS_GEN2(dev))
5403                 intel_dvo_init(dev);
5404
5405         if (SUPPORTS_TV(dev))
5406                 intel_tv_init(dev);
5407
5408         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5409                 encoder->base.possible_crtcs = encoder->crtc_mask;
5410                 encoder->base.possible_clones =
5411                         intel_encoder_clones(dev, encoder->clone_mask);
5412         }
5413 }
5414
5415 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5416 {
5417         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5418
5419         drm_framebuffer_cleanup(fb);
5420         drm_gem_object_unreference_unlocked(intel_fb->obj);
5421
5422         kfree(intel_fb);
5423 }
5424
5425 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5426                                                 struct drm_file *file_priv,
5427                                                 unsigned int *handle)
5428 {
5429         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5430         struct drm_gem_object *object = intel_fb->obj;
5431
5432         return drm_gem_handle_create(file_priv, object, handle);
5433 }
5434
5435 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5436         .destroy = intel_user_framebuffer_destroy,
5437         .create_handle = intel_user_framebuffer_create_handle,
5438 };
5439
5440 int intel_framebuffer_init(struct drm_device *dev,
5441                            struct intel_framebuffer *intel_fb,
5442                            struct drm_mode_fb_cmd *mode_cmd,
5443                            struct drm_gem_object *obj)
5444 {
5445         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5446         int ret;
5447
5448         if (obj_priv->tiling_mode == I915_TILING_Y)
5449                 return -EINVAL;
5450
5451         if (mode_cmd->pitch & 63)
5452                 return -EINVAL;
5453
5454         switch (mode_cmd->bpp) {
5455         case 8:
5456         case 16:
5457         case 24:
5458         case 32:
5459                 break;
5460         default:
5461                 return -EINVAL;
5462         }
5463
5464         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5465         if (ret) {
5466                 DRM_ERROR("framebuffer init failed %d\n", ret);
5467                 return ret;
5468         }
5469
5470         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5471         intel_fb->obj = obj;
5472         return 0;
5473 }
5474
5475 static struct drm_framebuffer *
5476 intel_user_framebuffer_create(struct drm_device *dev,
5477                               struct drm_file *filp,
5478                               struct drm_mode_fb_cmd *mode_cmd)
5479 {
5480         struct drm_gem_object *obj;
5481         struct intel_framebuffer *intel_fb;
5482         int ret;
5483
5484         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5485         if (!obj)
5486                 return ERR_PTR(-ENOENT);
5487
5488         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5489         if (!intel_fb)
5490                 return ERR_PTR(-ENOMEM);
5491
5492         ret = intel_framebuffer_init(dev, intel_fb,
5493                                      mode_cmd, obj);
5494         if (ret) {
5495                 drm_gem_object_unreference_unlocked(obj);
5496                 kfree(intel_fb);
5497                 return ERR_PTR(ret);
5498         }
5499
5500         return &intel_fb->base;
5501 }
5502
5503 static const struct drm_mode_config_funcs intel_mode_funcs = {
5504         .fb_create = intel_user_framebuffer_create,
5505         .output_poll_changed = intel_fb_output_poll_changed,
5506 };
5507
5508 static struct drm_gem_object *
5509 intel_alloc_context_page(struct drm_device *dev)
5510 {
5511         struct drm_gem_object *ctx;
5512         int ret;
5513
5514         ctx = i915_gem_alloc_object(dev, 4096);
5515         if (!ctx) {
5516                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5517                 return NULL;
5518         }
5519
5520         mutex_lock(&dev->struct_mutex);
5521         ret = i915_gem_object_pin(ctx, 4096, false, false);
5522         if (ret) {
5523                 DRM_ERROR("failed to pin power context: %d\n", ret);
5524                 goto err_unref;
5525         }
5526
5527         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5528         if (ret) {
5529                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5530                 goto err_unpin;
5531         }
5532         mutex_unlock(&dev->struct_mutex);
5533
5534         return ctx;
5535
5536 err_unpin:
5537         i915_gem_object_unpin(ctx);
5538 err_unref:
5539         drm_gem_object_unreference(ctx);
5540         mutex_unlock(&dev->struct_mutex);
5541         return NULL;
5542 }
5543
5544 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5545 {
5546         struct drm_i915_private *dev_priv = dev->dev_private;
5547         u16 rgvswctl;
5548
5549         rgvswctl = I915_READ16(MEMSWCTL);
5550         if (rgvswctl & MEMCTL_CMD_STS) {
5551                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5552                 return false; /* still busy with another command */
5553         }
5554
5555         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5556                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5557         I915_WRITE16(MEMSWCTL, rgvswctl);
5558         POSTING_READ16(MEMSWCTL);
5559
5560         rgvswctl |= MEMCTL_CMD_STS;
5561         I915_WRITE16(MEMSWCTL, rgvswctl);
5562
5563         return true;
5564 }
5565
5566 void ironlake_enable_drps(struct drm_device *dev)
5567 {
5568         struct drm_i915_private *dev_priv = dev->dev_private;
5569         u32 rgvmodectl = I915_READ(MEMMODECTL);
5570         u8 fmax, fmin, fstart, vstart;
5571
5572         /* Enable temp reporting */
5573         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5574         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5575
5576         /* 100ms RC evaluation intervals */
5577         I915_WRITE(RCUPEI, 100000);
5578         I915_WRITE(RCDNEI, 100000);
5579
5580         /* Set max/min thresholds to 90ms and 80ms respectively */
5581         I915_WRITE(RCBMAXAVG, 90000);
5582         I915_WRITE(RCBMINAVG, 80000);
5583
5584         I915_WRITE(MEMIHYST, 1);
5585
5586         /* Set up min, max, and cur for interrupt handling */
5587         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5588         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5589         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5590                 MEMMODE_FSTART_SHIFT;
5591
5592         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5593                 PXVFREQ_PX_SHIFT;
5594
5595         dev_priv->fmax = fmax; /* IPS callback will increase this */
5596         dev_priv->fstart = fstart;
5597
5598         dev_priv->max_delay = fstart;
5599         dev_priv->min_delay = fmin;
5600         dev_priv->cur_delay = fstart;
5601
5602         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5603                          fmax, fmin, fstart);
5604
5605         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5606
5607         /*
5608          * Interrupts will be enabled in ironlake_irq_postinstall
5609          */
5610
5611         I915_WRITE(VIDSTART, vstart);
5612         POSTING_READ(VIDSTART);
5613
5614         rgvmodectl |= MEMMODE_SWMODE_EN;
5615         I915_WRITE(MEMMODECTL, rgvmodectl);
5616
5617         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5618                 DRM_ERROR("stuck trying to change perf mode\n");
5619         msleep(1);
5620
5621         ironlake_set_drps(dev, fstart);
5622
5623         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5624                 I915_READ(0x112e0);
5625         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5626         dev_priv->last_count2 = I915_READ(0x112f4);
5627         getrawmonotonic(&dev_priv->last_time2);
5628 }
5629
5630 void ironlake_disable_drps(struct drm_device *dev)
5631 {
5632         struct drm_i915_private *dev_priv = dev->dev_private;
5633         u16 rgvswctl = I915_READ16(MEMSWCTL);
5634
5635         /* Ack interrupts, disable EFC interrupt */
5636         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5637         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5638         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5639         I915_WRITE(DEIIR, DE_PCU_EVENT);
5640         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5641
5642         /* Go back to the starting frequency */
5643         ironlake_set_drps(dev, dev_priv->fstart);
5644         msleep(1);
5645         rgvswctl |= MEMCTL_CMD_STS;
5646         I915_WRITE(MEMSWCTL, rgvswctl);
5647         msleep(1);
5648
5649 }
5650
5651 static unsigned long intel_pxfreq(u32 vidfreq)
5652 {
5653         unsigned long freq;
5654         int div = (vidfreq & 0x3f0000) >> 16;
5655         int post = (vidfreq & 0x3000) >> 12;
5656         int pre = (vidfreq & 0x7);
5657
5658         if (!pre)
5659                 return 0;
5660
5661         freq = ((div * 133333) / ((1<<post) * pre));
5662
5663         return freq;
5664 }
5665
5666 void intel_init_emon(struct drm_device *dev)
5667 {
5668         struct drm_i915_private *dev_priv = dev->dev_private;
5669         u32 lcfuse;
5670         u8 pxw[16];
5671         int i;
5672
5673         /* Disable to program */
5674         I915_WRITE(ECR, 0);
5675         POSTING_READ(ECR);
5676
5677         /* Program energy weights for various events */
5678         I915_WRITE(SDEW, 0x15040d00);
5679         I915_WRITE(CSIEW0, 0x007f0000);
5680         I915_WRITE(CSIEW1, 0x1e220004);
5681         I915_WRITE(CSIEW2, 0x04000004);
5682
5683         for (i = 0; i < 5; i++)
5684                 I915_WRITE(PEW + (i * 4), 0);
5685         for (i = 0; i < 3; i++)
5686                 I915_WRITE(DEW + (i * 4), 0);
5687
5688         /* Program P-state weights to account for frequency power adjustment */
5689         for (i = 0; i < 16; i++) {
5690                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5691                 unsigned long freq = intel_pxfreq(pxvidfreq);
5692                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5693                         PXVFREQ_PX_SHIFT;
5694                 unsigned long val;
5695
5696                 val = vid * vid;
5697                 val *= (freq / 1000);
5698                 val *= 255;
5699                 val /= (127*127*900);
5700                 if (val > 0xff)
5701                         DRM_ERROR("bad pxval: %ld\n", val);
5702                 pxw[i] = val;
5703         }
5704         /* Render standby states get 0 weight */
5705         pxw[14] = 0;
5706         pxw[15] = 0;
5707
5708         for (i = 0; i < 4; i++) {
5709                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5710                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5711                 I915_WRITE(PXW + (i * 4), val);
5712         }
5713
5714         /* Adjust magic regs to magic values (more experimental results) */
5715         I915_WRITE(OGW0, 0);
5716         I915_WRITE(OGW1, 0);
5717         I915_WRITE(EG0, 0x00007f00);
5718         I915_WRITE(EG1, 0x0000000e);
5719         I915_WRITE(EG2, 0x000e0000);
5720         I915_WRITE(EG3, 0x68000300);
5721         I915_WRITE(EG4, 0x42000000);
5722         I915_WRITE(EG5, 0x00140031);
5723         I915_WRITE(EG6, 0);
5724         I915_WRITE(EG7, 0);
5725
5726         for (i = 0; i < 8; i++)
5727                 I915_WRITE(PXWL + (i * 4), 0);
5728
5729         /* Enable PMON + select events */
5730         I915_WRITE(ECR, 0x80000019);
5731
5732         lcfuse = I915_READ(LCFUSE02);
5733
5734         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5735 }
5736
5737 void intel_init_clock_gating(struct drm_device *dev)
5738 {
5739         struct drm_i915_private *dev_priv = dev->dev_private;
5740
5741         /*
5742          * Disable clock gating reported to work incorrectly according to the
5743          * specs, but enable as much else as we can.
5744          */
5745         if (HAS_PCH_SPLIT(dev)) {
5746                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5747
5748                 if (IS_GEN5(dev)) {
5749                         /* Required for FBC */
5750                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5751                         /* Required for CxSR */
5752                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5753
5754                         I915_WRITE(PCH_3DCGDIS0,
5755                                    MARIUNIT_CLOCK_GATE_DISABLE |
5756                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5757                 }
5758
5759                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5760
5761                 /*
5762                  * On Ibex Peak and Cougar Point, we need to disable clock
5763                  * gating for the panel power sequencer or it will fail to
5764                  * start up when no ports are active.
5765                  */
5766                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5767
5768                 /*
5769                  * According to the spec the following bits should be set in
5770                  * order to enable memory self-refresh
5771                  * The bit 22/21 of 0x42004
5772                  * The bit 5 of 0x42020
5773                  * The bit 15 of 0x45000
5774                  */
5775                 if (IS_GEN5(dev)) {
5776                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5777                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5778                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5779                         I915_WRITE(ILK_DSPCLK_GATE,
5780                                         (I915_READ(ILK_DSPCLK_GATE) |
5781                                                 ILK_DPARB_CLK_GATE));
5782                         I915_WRITE(DISP_ARB_CTL,
5783                                         (I915_READ(DISP_ARB_CTL) |
5784                                                 DISP_FBC_WM_DIS));
5785                 I915_WRITE(WM3_LP_ILK, 0);
5786                 I915_WRITE(WM2_LP_ILK, 0);
5787                 I915_WRITE(WM1_LP_ILK, 0);
5788                 }
5789                 /*
5790                  * Based on the document from hardware guys the following bits
5791                  * should be set unconditionally in order to enable FBC.
5792                  * The bit 22 of 0x42000
5793                  * The bit 22 of 0x42004
5794                  * The bit 7,8,9 of 0x42020.
5795                  */
5796                 if (IS_IRONLAKE_M(dev)) {
5797                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5798                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5799                                    ILK_FBCQ_DIS);
5800                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5801                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5802                                    ILK_DPARB_GATE);
5803                         I915_WRITE(ILK_DSPCLK_GATE,
5804                                    I915_READ(ILK_DSPCLK_GATE) |
5805                                    ILK_DPFC_DIS1 |
5806                                    ILK_DPFC_DIS2 |
5807                                    ILK_CLK_FBC);
5808                 }
5809                 return;
5810         } else if (IS_G4X(dev)) {
5811                 uint32_t dspclk_gate;
5812                 I915_WRITE(RENCLK_GATE_D1, 0);
5813                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5814                        GS_UNIT_CLOCK_GATE_DISABLE |
5815                        CL_UNIT_CLOCK_GATE_DISABLE);
5816                 I915_WRITE(RAMCLK_GATE_D, 0);
5817                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5818                         OVRUNIT_CLOCK_GATE_DISABLE |
5819                         OVCUNIT_CLOCK_GATE_DISABLE;
5820                 if (IS_GM45(dev))
5821                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5822                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5823         } else if (IS_CRESTLINE(dev)) {
5824                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5825                 I915_WRITE(RENCLK_GATE_D2, 0);
5826                 I915_WRITE(DSPCLK_GATE_D, 0);
5827                 I915_WRITE(RAMCLK_GATE_D, 0);
5828                 I915_WRITE16(DEUC, 0);
5829         } else if (IS_BROADWATER(dev)) {
5830                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5831                        I965_RCC_CLOCK_GATE_DISABLE |
5832                        I965_RCPB_CLOCK_GATE_DISABLE |
5833                        I965_ISC_CLOCK_GATE_DISABLE |
5834                        I965_FBC_CLOCK_GATE_DISABLE);
5835                 I915_WRITE(RENCLK_GATE_D2, 0);
5836         } else if (IS_GEN3(dev)) {
5837                 u32 dstate = I915_READ(D_STATE);
5838
5839                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5840                         DSTATE_DOT_CLOCK_GATING;
5841                 I915_WRITE(D_STATE, dstate);
5842         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5843                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5844         } else if (IS_I830(dev)) {
5845                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5846         }
5847
5848         /*
5849          * GPU can automatically power down the render unit if given a page
5850          * to save state.
5851          */
5852         if (IS_IRONLAKE_M(dev)) {
5853                 if (dev_priv->renderctx == NULL)
5854                         dev_priv->renderctx = intel_alloc_context_page(dev);
5855                 if (dev_priv->renderctx) {
5856                         struct drm_i915_gem_object *obj_priv;
5857                         obj_priv = to_intel_bo(dev_priv->renderctx);
5858                         if (obj_priv) {
5859                                 if (BEGIN_LP_RING(4) == 0) {
5860                                         OUT_RING(MI_SET_CONTEXT);
5861                                         OUT_RING(obj_priv->gtt_offset |
5862                                                  MI_MM_SPACE_GTT |
5863                                                  MI_SAVE_EXT_STATE_EN |
5864                                                  MI_RESTORE_EXT_STATE_EN |
5865                                                  MI_RESTORE_INHIBIT);
5866                                         OUT_RING(MI_NOOP);
5867                                         OUT_RING(MI_FLUSH);
5868                                         ADVANCE_LP_RING();
5869                                 }
5870                         }
5871                 } else
5872                         DRM_DEBUG_KMS("Failed to allocate render context."
5873                                        "Disable RC6\n");
5874         }
5875
5876         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5877                 struct drm_i915_gem_object *obj_priv = NULL;
5878
5879                 if (dev_priv->pwrctx) {
5880                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5881                 } else {
5882                         struct drm_gem_object *pwrctx;
5883
5884                         pwrctx = intel_alloc_context_page(dev);
5885                         if (pwrctx) {
5886                                 dev_priv->pwrctx = pwrctx;
5887                                 obj_priv = to_intel_bo(pwrctx);
5888                         }
5889                 }
5890
5891                 if (obj_priv) {
5892                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5893                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5894                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5895                 }
5896         }
5897 }
5898
5899 /* Set up chip specific display functions */
5900 static void intel_init_display(struct drm_device *dev)
5901 {
5902         struct drm_i915_private *dev_priv = dev->dev_private;
5903
5904         /* We always want a DPMS function */
5905         if (HAS_PCH_SPLIT(dev))
5906                 dev_priv->display.dpms = ironlake_crtc_dpms;
5907         else
5908                 dev_priv->display.dpms = i9xx_crtc_dpms;
5909
5910         if (I915_HAS_FBC(dev)) {
5911                 if (IS_IRONLAKE_M(dev)) {
5912                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5913                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5914                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5915                 } else if (IS_GM45(dev)) {
5916                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5917                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5918                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5919                 } else if (IS_CRESTLINE(dev)) {
5920                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5921                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5922                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5923                 }
5924                 /* 855GM needs testing */
5925         }
5926
5927         /* Returns the core display clock speed */
5928         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5929                 dev_priv->display.get_display_clock_speed =
5930                         i945_get_display_clock_speed;
5931         else if (IS_I915G(dev))
5932                 dev_priv->display.get_display_clock_speed =
5933                         i915_get_display_clock_speed;
5934         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5935                 dev_priv->display.get_display_clock_speed =
5936                         i9xx_misc_get_display_clock_speed;
5937         else if (IS_I915GM(dev))
5938                 dev_priv->display.get_display_clock_speed =
5939                         i915gm_get_display_clock_speed;
5940         else if (IS_I865G(dev))
5941                 dev_priv->display.get_display_clock_speed =
5942                         i865_get_display_clock_speed;
5943         else if (IS_I85X(dev))
5944                 dev_priv->display.get_display_clock_speed =
5945                         i855_get_display_clock_speed;
5946         else /* 852, 830 */
5947                 dev_priv->display.get_display_clock_speed =
5948                         i830_get_display_clock_speed;
5949
5950         /* For FIFO watermark updates */
5951         if (HAS_PCH_SPLIT(dev)) {
5952                 if (IS_GEN5(dev)) {
5953                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5954                                 dev_priv->display.update_wm = ironlake_update_wm;
5955                         else {
5956                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5957                                               "Disable CxSR\n");
5958                                 dev_priv->display.update_wm = NULL;
5959                         }
5960                 } else
5961                         dev_priv->display.update_wm = NULL;
5962         } else if (IS_PINEVIEW(dev)) {
5963                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5964                                             dev_priv->is_ddr3,
5965                                             dev_priv->fsb_freq,
5966                                             dev_priv->mem_freq)) {
5967                         DRM_INFO("failed to find known CxSR latency "
5968                                  "(found ddr%s fsb freq %d, mem freq %d), "
5969                                  "disabling CxSR\n",
5970                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5971                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5972                         /* Disable CxSR and never update its watermark again */
5973                         pineview_disable_cxsr(dev);
5974                         dev_priv->display.update_wm = NULL;
5975                 } else
5976                         dev_priv->display.update_wm = pineview_update_wm;
5977         } else if (IS_G4X(dev))
5978                 dev_priv->display.update_wm = g4x_update_wm;
5979         else if (IS_GEN4(dev))
5980                 dev_priv->display.update_wm = i965_update_wm;
5981         else if (IS_GEN3(dev)) {
5982                 dev_priv->display.update_wm = i9xx_update_wm;
5983                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5984         } else if (IS_I85X(dev)) {
5985                 dev_priv->display.update_wm = i9xx_update_wm;
5986                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5987         } else {
5988                 dev_priv->display.update_wm = i830_update_wm;
5989                 if (IS_845G(dev))
5990                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5991                 else
5992                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5993         }
5994 }
5995
5996 /*
5997  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5998  * resume, or other times.  This quirk makes sure that's the case for
5999  * affected systems.
6000  */
6001 static void quirk_pipea_force (struct drm_device *dev)
6002 {
6003         struct drm_i915_private *dev_priv = dev->dev_private;
6004
6005         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6006         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6007 }
6008
6009 struct intel_quirk {
6010         int device;
6011         int subsystem_vendor;
6012         int subsystem_device;
6013         void (*hook)(struct drm_device *dev);
6014 };
6015
6016 struct intel_quirk intel_quirks[] = {
6017         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6018         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6019         /* HP Mini needs pipe A force quirk (LP: #322104) */
6020         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6021
6022         /* Thinkpad R31 needs pipe A force quirk */
6023         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6024         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6025         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6026
6027         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6028         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6029         /* ThinkPad X40 needs pipe A force quirk */
6030
6031         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6032         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6033
6034         /* 855 & before need to leave pipe A & dpll A up */
6035         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6036         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6037 };
6038
6039 static void intel_init_quirks(struct drm_device *dev)
6040 {
6041         struct pci_dev *d = dev->pdev;
6042         int i;
6043
6044         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6045                 struct intel_quirk *q = &intel_quirks[i];
6046
6047                 if (d->device == q->device &&
6048                     (d->subsystem_vendor == q->subsystem_vendor ||
6049                      q->subsystem_vendor == PCI_ANY_ID) &&
6050                     (d->subsystem_device == q->subsystem_device ||
6051                      q->subsystem_device == PCI_ANY_ID))
6052                         q->hook(dev);
6053         }
6054 }
6055
6056 /* Disable the VGA plane that we never use */
6057 static void i915_disable_vga(struct drm_device *dev)
6058 {
6059         struct drm_i915_private *dev_priv = dev->dev_private;
6060         u8 sr1;
6061         u32 vga_reg;
6062
6063         if (HAS_PCH_SPLIT(dev))
6064                 vga_reg = CPU_VGACNTRL;
6065         else
6066                 vga_reg = VGACNTRL;
6067
6068         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6069         outb(1, VGA_SR_INDEX);
6070         sr1 = inb(VGA_SR_DATA);
6071         outb(sr1 | 1<<5, VGA_SR_DATA);
6072         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6073         udelay(300);
6074
6075         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6076         POSTING_READ(vga_reg);
6077 }
6078
6079 void intel_modeset_init(struct drm_device *dev)
6080 {
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082         int i;
6083
6084         drm_mode_config_init(dev);
6085
6086         dev->mode_config.min_width = 0;
6087         dev->mode_config.min_height = 0;
6088
6089         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6090
6091         intel_init_quirks(dev);
6092
6093         intel_init_display(dev);
6094
6095         if (IS_GEN2(dev)) {
6096                 dev->mode_config.max_width = 2048;
6097                 dev->mode_config.max_height = 2048;
6098         } else if (IS_GEN3(dev)) {
6099                 dev->mode_config.max_width = 4096;
6100                 dev->mode_config.max_height = 4096;
6101         } else {
6102                 dev->mode_config.max_width = 8192;
6103                 dev->mode_config.max_height = 8192;
6104         }
6105
6106         /* set memory base */
6107         if (IS_GEN2(dev))
6108                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6109         else
6110                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6111
6112         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6113                 dev_priv->num_pipe = 2;
6114         else
6115                 dev_priv->num_pipe = 1;
6116         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6117                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6118
6119         for (i = 0; i < dev_priv->num_pipe; i++) {
6120                 intel_crtc_init(dev, i);
6121         }
6122
6123         intel_setup_outputs(dev);
6124
6125         intel_init_clock_gating(dev);
6126
6127         /* Just disable it once at startup */
6128         i915_disable_vga(dev);
6129
6130         if (IS_IRONLAKE_M(dev)) {
6131                 ironlake_enable_drps(dev);
6132                 intel_init_emon(dev);
6133         }
6134
6135         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6136         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6137                     (unsigned long)dev);
6138
6139         intel_setup_overlay(dev);
6140 }
6141
6142 void intel_modeset_cleanup(struct drm_device *dev)
6143 {
6144         struct drm_i915_private *dev_priv = dev->dev_private;
6145         struct drm_crtc *crtc;
6146         struct intel_crtc *intel_crtc;
6147
6148         drm_kms_helper_poll_fini(dev);
6149         mutex_lock(&dev->struct_mutex);
6150
6151         intel_unregister_dsm_handler();
6152
6153
6154         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6155                 /* Skip inactive CRTCs */
6156                 if (!crtc->fb)
6157                         continue;
6158
6159                 intel_crtc = to_intel_crtc(crtc);
6160                 intel_increase_pllclock(crtc);
6161         }
6162
6163         if (dev_priv->display.disable_fbc)
6164                 dev_priv->display.disable_fbc(dev);
6165
6166         if (dev_priv->renderctx) {
6167                 struct drm_i915_gem_object *obj_priv;
6168
6169                 obj_priv = to_intel_bo(dev_priv->renderctx);
6170                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6171                 I915_READ(CCID);
6172                 i915_gem_object_unpin(dev_priv->renderctx);
6173                 drm_gem_object_unreference(dev_priv->renderctx);
6174         }
6175
6176         if (dev_priv->pwrctx) {
6177                 struct drm_i915_gem_object *obj_priv;
6178
6179                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6180                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6181                 I915_READ(PWRCTXA);
6182                 i915_gem_object_unpin(dev_priv->pwrctx);
6183                 drm_gem_object_unreference(dev_priv->pwrctx);
6184         }
6185
6186         if (IS_IRONLAKE_M(dev))
6187                 ironlake_disable_drps(dev);
6188
6189         mutex_unlock(&dev->struct_mutex);
6190
6191         /* Disable the irq before mode object teardown, for the irq might
6192          * enqueue unpin/hotplug work. */
6193         drm_irq_uninstall(dev);
6194         cancel_work_sync(&dev_priv->hotplug_work);
6195
6196         /* Shut off idle work before the crtcs get freed. */
6197         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6198                 intel_crtc = to_intel_crtc(crtc);
6199                 del_timer_sync(&intel_crtc->idle_timer);
6200         }
6201         del_timer_sync(&dev_priv->idle_timer);
6202         cancel_work_sync(&dev_priv->idle_work);
6203
6204         drm_mode_config_cleanup(dev);
6205 }
6206
6207 /*
6208  * Return which encoder is currently attached for connector.
6209  */
6210 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6211 {
6212         return &intel_attached_encoder(connector)->base;
6213 }
6214
6215 void intel_connector_attach_encoder(struct intel_connector *connector,
6216                                     struct intel_encoder *encoder)
6217 {
6218         connector->encoder = encoder;
6219         drm_mode_connector_attach_encoder(&connector->base,
6220                                           &encoder->base);
6221 }
6222
6223 /*
6224  * set vga decode state - true == enable VGA decode
6225  */
6226 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6227 {
6228         struct drm_i915_private *dev_priv = dev->dev_private;
6229         u16 gmch_ctrl;
6230
6231         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6232         if (state)
6233                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6234         else
6235                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6236         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6237         return 0;
6238 }