drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1062                            enum pipe pipe, int reg)
1063 {
1064         u32 val = I915_READ(reg);
1065         if (DP_PIPE_ENABLED(val, pipe))
1066                 I915_WRITE(reg, val & ~DP_PORT_EN);
1067 }
1068
1069 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1070                              enum pipe pipe, int reg)
1071 {
1072         u32 val = I915_READ(reg);
1073         if (HDMI_PIPE_ENABLED(val, pipe))
1074                 I915_WRITE(reg, val & ~PORT_ENABLE);
1075 }
1076
1077 /* Disable any ports connected to this transcoder */
1078 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1079                                     enum pipe pipe)
1080 {
1081         u32 reg, val;
1082
1083         val = I915_READ(PCH_PP_CONTROL);
1084         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1085
1086         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1087         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1088         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1089
1090         reg = PCH_ADPA;
1091         val = I915_READ(reg);
1092         if (ADPA_PIPE_ENABLED(val, pipe))
1093                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1094
1095         reg = PCH_LVDS;
1096         val = I915_READ(reg);
1097         if (LVDS_PIPE_ENABLED(val, pipe)) {
1098                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1099                 POSTING_READ(reg);
1100                 udelay(100);
1101         }
1102
1103         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1104         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1105         disable_pch_hdmi(dev_priv, pipe, HDMID);
1106 }
1107
1108 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1109 {
1110         struct drm_device *dev = crtc->dev;
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         struct drm_framebuffer *fb = crtc->fb;
1113         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1114         struct drm_i915_gem_object *obj = intel_fb->obj;
1115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1116         int plane, i;
1117         u32 fbc_ctl, fbc_ctl2;
1118
1119         if (fb->pitch == dev_priv->cfb_pitch &&
1120             obj->fence_reg == dev_priv->cfb_fence &&
1121             intel_crtc->plane == dev_priv->cfb_plane &&
1122             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1123                 return;
1124
1125         i8xx_disable_fbc(dev);
1126
1127         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1128
1129         if (fb->pitch < dev_priv->cfb_pitch)
1130                 dev_priv->cfb_pitch = fb->pitch;
1131
1132         /* FBC_CTL wants 64B units */
1133         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1134         dev_priv->cfb_fence = obj->fence_reg;
1135         dev_priv->cfb_plane = intel_crtc->plane;
1136         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1137
1138         /* Clear old tags */
1139         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1140                 I915_WRITE(FBC_TAG + (i * 4), 0);
1141
1142         /* Set it up... */
1143         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1144         if (obj->tiling_mode != I915_TILING_NONE)
1145                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1146         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1147         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1148
1149         /* enable it... */
1150         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1151         if (IS_I945GM(dev))
1152                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1153         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1154         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1155         if (obj->tiling_mode != I915_TILING_NONE)
1156                 fbc_ctl |= dev_priv->cfb_fence;
1157         I915_WRITE(FBC_CONTROL, fbc_ctl);
1158
1159         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1160                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1161 }
1162
1163 void i8xx_disable_fbc(struct drm_device *dev)
1164 {
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         u32 fbc_ctl;
1167
1168         /* Disable compression */
1169         fbc_ctl = I915_READ(FBC_CONTROL);
1170         if ((fbc_ctl & FBC_CTL_EN) == 0)
1171                 return;
1172
1173         fbc_ctl &= ~FBC_CTL_EN;
1174         I915_WRITE(FBC_CONTROL, fbc_ctl);
1175
1176         /* Wait for compressing bit to clear */
1177         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1178                 DRM_DEBUG_KMS("FBC idle timed out\n");
1179                 return;
1180         }
1181
1182         DRM_DEBUG_KMS("disabled FBC\n");
1183 }
1184
1185 static bool i8xx_fbc_enabled(struct drm_device *dev)
1186 {
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188
1189         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1190 }
1191
1192 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1193 {
1194         struct drm_device *dev = crtc->dev;
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         struct drm_framebuffer *fb = crtc->fb;
1197         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1198         struct drm_i915_gem_object *obj = intel_fb->obj;
1199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1201         unsigned long stall_watermark = 200;
1202         u32 dpfc_ctl;
1203
1204         dpfc_ctl = I915_READ(DPFC_CONTROL);
1205         if (dpfc_ctl & DPFC_CTL_EN) {
1206                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1207                     dev_priv->cfb_fence == obj->fence_reg &&
1208                     dev_priv->cfb_plane == intel_crtc->plane &&
1209                     dev_priv->cfb_y == crtc->y)
1210                         return;
1211
1212                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1213                 POSTING_READ(DPFC_CONTROL);
1214                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1215         }
1216
1217         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1218         dev_priv->cfb_fence = obj->fence_reg;
1219         dev_priv->cfb_plane = intel_crtc->plane;
1220         dev_priv->cfb_y = crtc->y;
1221
1222         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1223         if (obj->tiling_mode != I915_TILING_NONE) {
1224                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1225                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1226         } else {
1227                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1228         }
1229
1230         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1231                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1232                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1233         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1234
1235         /* enable it... */
1236         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1237
1238         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1239 }
1240
1241 void g4x_disable_fbc(struct drm_device *dev)
1242 {
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244         u32 dpfc_ctl;
1245
1246         /* Disable compression */
1247         dpfc_ctl = I915_READ(DPFC_CONTROL);
1248         if (dpfc_ctl & DPFC_CTL_EN) {
1249                 dpfc_ctl &= ~DPFC_CTL_EN;
1250                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1251
1252                 DRM_DEBUG_KMS("disabled FBC\n");
1253         }
1254 }
1255
1256 static bool g4x_fbc_enabled(struct drm_device *dev)
1257 {
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259
1260         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1261 }
1262
1263 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1264 {
1265         struct drm_i915_private *dev_priv = dev->dev_private;
1266         u32 blt_ecoskpd;
1267
1268         /* Make sure blitter notifies FBC of writes */
1269         __gen6_gt_force_wake_get(dev_priv);
1270         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1271         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1272                 GEN6_BLITTER_LOCK_SHIFT;
1273         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1274         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1275         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1276         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1277                          GEN6_BLITTER_LOCK_SHIFT);
1278         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1279         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1280         __gen6_gt_force_wake_put(dev_priv);
1281 }
1282
1283 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1284 {
1285         struct drm_device *dev = crtc->dev;
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         struct drm_framebuffer *fb = crtc->fb;
1288         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1289         struct drm_i915_gem_object *obj = intel_fb->obj;
1290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1291         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1292         unsigned long stall_watermark = 200;
1293         u32 dpfc_ctl;
1294
1295         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1296         if (dpfc_ctl & DPFC_CTL_EN) {
1297                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1298                     dev_priv->cfb_fence == obj->fence_reg &&
1299                     dev_priv->cfb_plane == intel_crtc->plane &&
1300                     dev_priv->cfb_offset == obj->gtt_offset &&
1301                     dev_priv->cfb_y == crtc->y)
1302                         return;
1303
1304                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1305                 POSTING_READ(ILK_DPFC_CONTROL);
1306                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1307         }
1308
1309         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1310         dev_priv->cfb_fence = obj->fence_reg;
1311         dev_priv->cfb_plane = intel_crtc->plane;
1312         dev_priv->cfb_offset = obj->gtt_offset;
1313         dev_priv->cfb_y = crtc->y;
1314
1315         dpfc_ctl &= DPFC_RESERVED;
1316         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1317         if (obj->tiling_mode != I915_TILING_NONE) {
1318                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1319                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1320         } else {
1321                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1322         }
1323
1324         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1325                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1326                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1327         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1328         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1329         /* enable it... */
1330         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1331
1332         if (IS_GEN6(dev)) {
1333                 I915_WRITE(SNB_DPFC_CTL_SA,
1334                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1335                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1336                 sandybridge_blit_fbc_update(dev);
1337         }
1338
1339         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1340 }
1341
1342 void ironlake_disable_fbc(struct drm_device *dev)
1343 {
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         u32 dpfc_ctl;
1346
1347         /* Disable compression */
1348         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1349         if (dpfc_ctl & DPFC_CTL_EN) {
1350                 dpfc_ctl &= ~DPFC_CTL_EN;
1351                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1352
1353                 DRM_DEBUG_KMS("disabled FBC\n");
1354         }
1355 }
1356
1357 static bool ironlake_fbc_enabled(struct drm_device *dev)
1358 {
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1362 }
1363
1364 bool intel_fbc_enabled(struct drm_device *dev)
1365 {
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367
1368         if (!dev_priv->display.fbc_enabled)
1369                 return false;
1370
1371         return dev_priv->display.fbc_enabled(dev);
1372 }
1373
1374 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1375 {
1376         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1377
1378         if (!dev_priv->display.enable_fbc)
1379                 return;
1380
1381         dev_priv->display.enable_fbc(crtc, interval);
1382 }
1383
1384 void intel_disable_fbc(struct drm_device *dev)
1385 {
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387
1388         if (!dev_priv->display.disable_fbc)
1389                 return;
1390
1391         dev_priv->display.disable_fbc(dev);
1392 }
1393
1394 /**
1395  * intel_update_fbc - enable/disable FBC as needed
1396  * @dev: the drm_device
1397  *
1398  * Set up the framebuffer compression hardware at mode set time.  We
1399  * enable it if possible:
1400  *   - plane A only (on pre-965)
1401  *   - no pixel mulitply/line duplication
1402  *   - no alpha buffer discard
1403  *   - no dual wide
1404  *   - framebuffer <= 2048 in width, 1536 in height
1405  *
1406  * We can't assume that any compression will take place (worst case),
1407  * so the compressed buffer has to be the same size as the uncompressed
1408  * one.  It also must reside (along with the line length buffer) in
1409  * stolen memory.
1410  *
1411  * We need to enable/disable FBC on a global basis.
1412  */
1413 static void intel_update_fbc(struct drm_device *dev)
1414 {
1415         struct drm_i915_private *dev_priv = dev->dev_private;
1416         struct drm_crtc *crtc = NULL, *tmp_crtc;
1417         struct intel_crtc *intel_crtc;
1418         struct drm_framebuffer *fb;
1419         struct intel_framebuffer *intel_fb;
1420         struct drm_i915_gem_object *obj;
1421
1422         DRM_DEBUG_KMS("\n");
1423
1424         if (!i915_powersave)
1425                 return;
1426
1427         if (!I915_HAS_FBC(dev))
1428                 return;
1429
1430         /*
1431          * If FBC is already on, we just have to verify that we can
1432          * keep it that way...
1433          * Need to disable if:
1434          *   - more than one pipe is active
1435          *   - changing FBC params (stride, fence, mode)
1436          *   - new fb is too large to fit in compressed buffer
1437          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1438          */
1439         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1440                 if (tmp_crtc->enabled) {
1441                         if (crtc) {
1442                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1443                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1444                                 goto out_disable;
1445                         }
1446                         crtc = tmp_crtc;
1447                 }
1448         }
1449
1450         if (!crtc || crtc->fb == NULL) {
1451                 DRM_DEBUG_KMS("no output, disabling\n");
1452                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1453                 goto out_disable;
1454         }
1455
1456         intel_crtc = to_intel_crtc(crtc);
1457         fb = crtc->fb;
1458         intel_fb = to_intel_framebuffer(fb);
1459         obj = intel_fb->obj;
1460
1461         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1462                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1463                               "compression\n");
1464                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1465                 goto out_disable;
1466         }
1467         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1468             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1469                 DRM_DEBUG_KMS("mode incompatible with compression, "
1470                               "disabling\n");
1471                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1472                 goto out_disable;
1473         }
1474         if ((crtc->mode.hdisplay > 2048) ||
1475             (crtc->mode.vdisplay > 1536)) {
1476                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1477                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1478                 goto out_disable;
1479         }
1480         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1481                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1482                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1483                 goto out_disable;
1484         }
1485         if (obj->tiling_mode != I915_TILING_X) {
1486                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1487                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1488                 goto out_disable;
1489         }
1490
1491         /* If the kernel debugger is active, always disable compression */
1492         if (in_dbg_master())
1493                 goto out_disable;
1494
1495         intel_enable_fbc(crtc, 500);
1496         return;
1497
1498 out_disable:
1499         /* Multiple disables should be harmless */
1500         if (intel_fbc_enabled(dev)) {
1501                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1502                 intel_disable_fbc(dev);
1503         }
1504 }
1505
1506 int
1507 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1508                            struct drm_i915_gem_object *obj,
1509                            struct intel_ring_buffer *pipelined)
1510 {
1511         u32 alignment;
1512         int ret;
1513
1514         switch (obj->tiling_mode) {
1515         case I915_TILING_NONE:
1516                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1517                         alignment = 128 * 1024;
1518                 else if (INTEL_INFO(dev)->gen >= 4)
1519                         alignment = 4 * 1024;
1520                 else
1521                         alignment = 64 * 1024;
1522                 break;
1523         case I915_TILING_X:
1524                 /* pin() will align the object as required by fence */
1525                 alignment = 0;
1526                 break;
1527         case I915_TILING_Y:
1528                 /* FIXME: Is this true? */
1529                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1530                 return -EINVAL;
1531         default:
1532                 BUG();
1533         }
1534
1535         ret = i915_gem_object_pin(obj, alignment, true);
1536         if (ret)
1537                 return ret;
1538
1539         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1540         if (ret)
1541                 goto err_unpin;
1542
1543         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1544          * fence, whereas 965+ only requires a fence if using
1545          * framebuffer compression.  For simplicity, we always install
1546          * a fence as the cost is not that onerous.
1547          */
1548         if (obj->tiling_mode != I915_TILING_NONE) {
1549                 ret = i915_gem_object_get_fence(obj, pipelined, false);
1550                 if (ret)
1551                         goto err_unpin;
1552         }
1553
1554         return 0;
1555
1556 err_unpin:
1557         i915_gem_object_unpin(obj);
1558         return ret;
1559 }
1560
1561 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1562 static int
1563 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1564                            int x, int y, enum mode_set_atomic state)
1565 {
1566         struct drm_device *dev = crtc->dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1569         struct intel_framebuffer *intel_fb;
1570         struct drm_i915_gem_object *obj;
1571         int plane = intel_crtc->plane;
1572         unsigned long Start, Offset;
1573         u32 dspcntr;
1574         u32 reg;
1575
1576         switch (plane) {
1577         case 0:
1578         case 1:
1579                 break;
1580         default:
1581                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1582                 return -EINVAL;
1583         }
1584
1585         intel_fb = to_intel_framebuffer(fb);
1586         obj = intel_fb->obj;
1587
1588         reg = DSPCNTR(plane);
1589         dspcntr = I915_READ(reg);
1590         /* Mask out pixel format bits in case we change it */
1591         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1592         switch (fb->bits_per_pixel) {
1593         case 8:
1594                 dspcntr |= DISPPLANE_8BPP;
1595                 break;
1596         case 16:
1597                 if (fb->depth == 15)
1598                         dspcntr |= DISPPLANE_15_16BPP;
1599                 else
1600                         dspcntr |= DISPPLANE_16BPP;
1601                 break;
1602         case 24:
1603         case 32:
1604                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1605                 break;
1606         default:
1607                 DRM_ERROR("Unknown color depth\n");
1608                 return -EINVAL;
1609         }
1610         if (INTEL_INFO(dev)->gen >= 4) {
1611                 if (obj->tiling_mode != I915_TILING_NONE)
1612                         dspcntr |= DISPPLANE_TILED;
1613                 else
1614                         dspcntr &= ~DISPPLANE_TILED;
1615         }
1616
1617         if (HAS_PCH_SPLIT(dev))
1618                 /* must disable */
1619                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1620
1621         I915_WRITE(reg, dspcntr);
1622
1623         Start = obj->gtt_offset;
1624         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1625
1626         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1627                       Start, Offset, x, y, fb->pitch);
1628         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DSPSURF(plane), Start);
1631                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1632                 I915_WRITE(DSPADDR(plane), Offset);
1633         } else
1634                 I915_WRITE(DSPADDR(plane), Start + Offset);
1635         POSTING_READ(reg);
1636
1637         intel_update_fbc(dev);
1638         intel_increase_pllclock(crtc);
1639
1640         return 0;
1641 }
1642
1643 static int
1644 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1645                     struct drm_framebuffer *old_fb)
1646 {
1647         struct drm_device *dev = crtc->dev;
1648         struct drm_i915_master_private *master_priv;
1649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1650         int ret;
1651
1652         /* no fb bound */
1653         if (!crtc->fb) {
1654                 DRM_DEBUG_KMS("No FB bound\n");
1655                 return 0;
1656         }
1657
1658         switch (intel_crtc->plane) {
1659         case 0:
1660         case 1:
1661                 break;
1662         default:
1663                 return -EINVAL;
1664         }
1665
1666         mutex_lock(&dev->struct_mutex);
1667         ret = intel_pin_and_fence_fb_obj(dev,
1668                                          to_intel_framebuffer(crtc->fb)->obj,
1669                                          NULL);
1670         if (ret != 0) {
1671                 mutex_unlock(&dev->struct_mutex);
1672                 return ret;
1673         }
1674
1675         if (old_fb) {
1676                 struct drm_i915_private *dev_priv = dev->dev_private;
1677                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1678
1679                 wait_event(dev_priv->pending_flip_queue,
1680                            atomic_read(&dev_priv->mm.wedged) ||
1681                            atomic_read(&obj->pending_flip) == 0);
1682
1683                 /* Big Hammer, we also need to ensure that any pending
1684                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1685                  * current scanout is retired before unpinning the old
1686                  * framebuffer.
1687                  *
1688                  * This should only fail upon a hung GPU, in which case we
1689                  * can safely continue.
1690                  */
1691                 ret = i915_gem_object_flush_gpu(obj, false);
1692                 (void) ret;
1693         }
1694
1695         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1696                                          LEAVE_ATOMIC_MODE_SET);
1697         if (ret) {
1698                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1699                 mutex_unlock(&dev->struct_mutex);
1700                 return ret;
1701         }
1702
1703         if (old_fb) {
1704                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1705                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1706         }
1707
1708         mutex_unlock(&dev->struct_mutex);
1709
1710         if (!dev->primary->master)
1711                 return 0;
1712
1713         master_priv = dev->primary->master->driver_priv;
1714         if (!master_priv->sarea_priv)
1715                 return 0;
1716
1717         if (intel_crtc->pipe) {
1718                 master_priv->sarea_priv->pipeB_x = x;
1719                 master_priv->sarea_priv->pipeB_y = y;
1720         } else {
1721                 master_priv->sarea_priv->pipeA_x = x;
1722                 master_priv->sarea_priv->pipeA_y = y;
1723         }
1724
1725         return 0;
1726 }
1727
1728 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1729 {
1730         struct drm_device *dev = crtc->dev;
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         u32 dpa_ctl;
1733
1734         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1735         dpa_ctl = I915_READ(DP_A);
1736         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1737
1738         if (clock < 200000) {
1739                 u32 temp;
1740                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1741                 /* workaround for 160Mhz:
1742                    1) program 0x4600c bits 15:0 = 0x8124
1743                    2) program 0x46010 bit 0 = 1
1744                    3) program 0x46034 bit 24 = 1
1745                    4) program 0x64000 bit 14 = 1
1746                    */
1747                 temp = I915_READ(0x4600c);
1748                 temp &= 0xffff0000;
1749                 I915_WRITE(0x4600c, temp | 0x8124);
1750
1751                 temp = I915_READ(0x46010);
1752                 I915_WRITE(0x46010, temp | 1);
1753
1754                 temp = I915_READ(0x46034);
1755                 I915_WRITE(0x46034, temp | (1 << 24));
1756         } else {
1757                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1758         }
1759         I915_WRITE(DP_A, dpa_ctl);
1760
1761         POSTING_READ(DP_A);
1762         udelay(500);
1763 }
1764
1765 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1766 {
1767         struct drm_device *dev = crtc->dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1770         int pipe = intel_crtc->pipe;
1771         u32 reg, temp;
1772
1773         /* enable normal train */
1774         reg = FDI_TX_CTL(pipe);
1775         temp = I915_READ(reg);
1776         temp &= ~FDI_LINK_TRAIN_NONE;
1777         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1778         I915_WRITE(reg, temp);
1779
1780         reg = FDI_RX_CTL(pipe);
1781         temp = I915_READ(reg);
1782         if (HAS_PCH_CPT(dev)) {
1783                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1784                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1785         } else {
1786                 temp &= ~FDI_LINK_TRAIN_NONE;
1787                 temp |= FDI_LINK_TRAIN_NONE;
1788         }
1789         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1790
1791         /* wait one idle pattern time */
1792         POSTING_READ(reg);
1793         udelay(1000);
1794 }
1795
1796 /* The FDI link training functions for ILK/Ibexpeak. */
1797 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1798 {
1799         struct drm_device *dev = crtc->dev;
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1802         int pipe = intel_crtc->pipe;
1803         u32 reg, temp, tries;
1804
1805         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1806            for train result */
1807         reg = FDI_RX_IMR(pipe);
1808         temp = I915_READ(reg);
1809         temp &= ~FDI_RX_SYMBOL_LOCK;
1810         temp &= ~FDI_RX_BIT_LOCK;
1811         I915_WRITE(reg, temp);
1812         I915_READ(reg);
1813         udelay(150);
1814
1815         /* enable CPU FDI TX and PCH FDI RX */
1816         reg = FDI_TX_CTL(pipe);
1817         temp = I915_READ(reg);
1818         temp &= ~(7 << 19);
1819         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1820         temp &= ~FDI_LINK_TRAIN_NONE;
1821         temp |= FDI_LINK_TRAIN_PATTERN_1;
1822         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1823
1824         reg = FDI_RX_CTL(pipe);
1825         temp = I915_READ(reg);
1826         temp &= ~FDI_LINK_TRAIN_NONE;
1827         temp |= FDI_LINK_TRAIN_PATTERN_1;
1828         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1829
1830         POSTING_READ(reg);
1831         udelay(150);
1832
1833         /* Ironlake workaround, enable clock pointer after FDI enable*/
1834         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1835
1836         reg = FDI_RX_IIR(pipe);
1837         for (tries = 0; tries < 5; tries++) {
1838                 temp = I915_READ(reg);
1839                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1840
1841                 if ((temp & FDI_RX_BIT_LOCK)) {
1842                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1843                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1844                         break;
1845                 }
1846         }
1847         if (tries == 5)
1848                 DRM_ERROR("FDI train 1 fail!\n");
1849
1850         /* Train 2 */
1851         reg = FDI_TX_CTL(pipe);
1852         temp = I915_READ(reg);
1853         temp &= ~FDI_LINK_TRAIN_NONE;
1854         temp |= FDI_LINK_TRAIN_PATTERN_2;
1855         I915_WRITE(reg, temp);
1856
1857         reg = FDI_RX_CTL(pipe);
1858         temp = I915_READ(reg);
1859         temp &= ~FDI_LINK_TRAIN_NONE;
1860         temp |= FDI_LINK_TRAIN_PATTERN_2;
1861         I915_WRITE(reg, temp);
1862
1863         POSTING_READ(reg);
1864         udelay(150);
1865
1866         reg = FDI_RX_IIR(pipe);
1867         for (tries = 0; tries < 5; tries++) {
1868                 temp = I915_READ(reg);
1869                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1870
1871                 if (temp & FDI_RX_SYMBOL_LOCK) {
1872                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1873                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1874                         break;
1875                 }
1876         }
1877         if (tries == 5)
1878                 DRM_ERROR("FDI train 2 fail!\n");
1879
1880         DRM_DEBUG_KMS("FDI train done\n");
1881
1882 }
1883
1884 static const int const snb_b_fdi_train_param [] = {
1885         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1886         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1887         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1888         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1889 };
1890
1891 /* The FDI link training functions for SNB/Cougarpoint. */
1892 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1897         int pipe = intel_crtc->pipe;
1898         u32 reg, temp, i;
1899
1900         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1901            for train result */
1902         reg = FDI_RX_IMR(pipe);
1903         temp = I915_READ(reg);
1904         temp &= ~FDI_RX_SYMBOL_LOCK;
1905         temp &= ~FDI_RX_BIT_LOCK;
1906         I915_WRITE(reg, temp);
1907
1908         POSTING_READ(reg);
1909         udelay(150);
1910
1911         /* enable CPU FDI TX and PCH FDI RX */
1912         reg = FDI_TX_CTL(pipe);
1913         temp = I915_READ(reg);
1914         temp &= ~(7 << 19);
1915         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1916         temp &= ~FDI_LINK_TRAIN_NONE;
1917         temp |= FDI_LINK_TRAIN_PATTERN_1;
1918         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1919         /* SNB-B */
1920         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1921         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1922
1923         reg = FDI_RX_CTL(pipe);
1924         temp = I915_READ(reg);
1925         if (HAS_PCH_CPT(dev)) {
1926                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1927                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1928         } else {
1929                 temp &= ~FDI_LINK_TRAIN_NONE;
1930                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1931         }
1932         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1933
1934         POSTING_READ(reg);
1935         udelay(150);
1936
1937         for (i = 0; i < 4; i++ ) {
1938                 reg = FDI_TX_CTL(pipe);
1939                 temp = I915_READ(reg);
1940                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1941                 temp |= snb_b_fdi_train_param[i];
1942                 I915_WRITE(reg, temp);
1943
1944                 POSTING_READ(reg);
1945                 udelay(500);
1946
1947                 reg = FDI_RX_IIR(pipe);
1948                 temp = I915_READ(reg);
1949                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1950
1951                 if (temp & FDI_RX_BIT_LOCK) {
1952                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1953                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1954                         break;
1955                 }
1956         }
1957         if (i == 4)
1958                 DRM_ERROR("FDI train 1 fail!\n");
1959
1960         /* Train 2 */
1961         reg = FDI_TX_CTL(pipe);
1962         temp = I915_READ(reg);
1963         temp &= ~FDI_LINK_TRAIN_NONE;
1964         temp |= FDI_LINK_TRAIN_PATTERN_2;
1965         if (IS_GEN6(dev)) {
1966                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1967                 /* SNB-B */
1968                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1969         }
1970         I915_WRITE(reg, temp);
1971
1972         reg = FDI_RX_CTL(pipe);
1973         temp = I915_READ(reg);
1974         if (HAS_PCH_CPT(dev)) {
1975                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1976                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1977         } else {
1978                 temp &= ~FDI_LINK_TRAIN_NONE;
1979                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1980         }
1981         I915_WRITE(reg, temp);
1982
1983         POSTING_READ(reg);
1984         udelay(150);
1985
1986         for (i = 0; i < 4; i++ ) {
1987                 reg = FDI_TX_CTL(pipe);
1988                 temp = I915_READ(reg);
1989                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1990                 temp |= snb_b_fdi_train_param[i];
1991                 I915_WRITE(reg, temp);
1992
1993                 POSTING_READ(reg);
1994                 udelay(500);
1995
1996                 reg = FDI_RX_IIR(pipe);
1997                 temp = I915_READ(reg);
1998                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1999
2000                 if (temp & FDI_RX_SYMBOL_LOCK) {
2001                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2002                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2003                         break;
2004                 }
2005         }
2006         if (i == 4)
2007                 DRM_ERROR("FDI train 2 fail!\n");
2008
2009         DRM_DEBUG_KMS("FDI train done.\n");
2010 }
2011
2012 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2013 {
2014         struct drm_device *dev = crtc->dev;
2015         struct drm_i915_private *dev_priv = dev->dev_private;
2016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2017         int pipe = intel_crtc->pipe;
2018         u32 reg, temp;
2019
2020         /* Write the TU size bits so error detection works */
2021         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2022                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2023
2024         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2025         reg = FDI_RX_CTL(pipe);
2026         temp = I915_READ(reg);
2027         temp &= ~((0x7 << 19) | (0x7 << 16));
2028         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2029         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2030         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2031
2032         POSTING_READ(reg);
2033         udelay(200);
2034
2035         /* Switch from Rawclk to PCDclk */
2036         temp = I915_READ(reg);
2037         I915_WRITE(reg, temp | FDI_PCDCLK);
2038
2039         POSTING_READ(reg);
2040         udelay(200);
2041
2042         /* Enable CPU FDI TX PLL, always on for Ironlake */
2043         reg = FDI_TX_CTL(pipe);
2044         temp = I915_READ(reg);
2045         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2046                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2047
2048                 POSTING_READ(reg);
2049                 udelay(100);
2050         }
2051 }
2052
2053 static void intel_flush_display_plane(struct drm_device *dev,
2054                                       int plane)
2055 {
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057         u32 reg = DSPADDR(plane);
2058         I915_WRITE(reg, I915_READ(reg));
2059 }
2060
2061 /*
2062  * When we disable a pipe, we need to clear any pending scanline wait events
2063  * to avoid hanging the ring, which we assume we are waiting on.
2064  */
2065 static void intel_clear_scanline_wait(struct drm_device *dev)
2066 {
2067         struct drm_i915_private *dev_priv = dev->dev_private;
2068         struct intel_ring_buffer *ring;
2069         u32 tmp;
2070
2071         if (IS_GEN2(dev))
2072                 /* Can't break the hang on i8xx */
2073                 return;
2074
2075         ring = LP_RING(dev_priv);
2076         tmp = I915_READ_CTL(ring);
2077         if (tmp & RING_WAIT)
2078                 I915_WRITE_CTL(ring, tmp);
2079 }
2080
2081 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2082 {
2083         struct drm_i915_gem_object *obj;
2084         struct drm_i915_private *dev_priv;
2085
2086         if (crtc->fb == NULL)
2087                 return;
2088
2089         obj = to_intel_framebuffer(crtc->fb)->obj;
2090         dev_priv = crtc->dev->dev_private;
2091         wait_event(dev_priv->pending_flip_queue,
2092                    atomic_read(&obj->pending_flip) == 0);
2093 }
2094
2095 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2096 {
2097         struct drm_device *dev = crtc->dev;
2098         struct drm_mode_config *mode_config = &dev->mode_config;
2099         struct intel_encoder *encoder;
2100
2101         /*
2102          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2103          * must be driven by its own crtc; no sharing is possible.
2104          */
2105         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2106                 if (encoder->base.crtc != crtc)
2107                         continue;
2108
2109                 switch (encoder->type) {
2110                 case INTEL_OUTPUT_EDP:
2111                         if (!intel_encoder_is_pch_edp(&encoder->base))
2112                                 return false;
2113                         continue;
2114                 }
2115         }
2116
2117         return true;
2118 }
2119
2120 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2121 {
2122         struct drm_device *dev = crtc->dev;
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2125         int pipe = intel_crtc->pipe;
2126         int plane = intel_crtc->plane;
2127         u32 reg, temp;
2128         bool is_pch_port = false;
2129
2130         if (intel_crtc->active)
2131                 return;
2132
2133         intel_crtc->active = true;
2134         intel_update_watermarks(dev);
2135
2136         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2137                 temp = I915_READ(PCH_LVDS);
2138                 if ((temp & LVDS_PORT_EN) == 0)
2139                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2140         }
2141
2142         is_pch_port = intel_crtc_driving_pch(crtc);
2143
2144         if (is_pch_port)
2145                 ironlake_fdi_enable(crtc);
2146         else {
2147                 /* disable CPU FDI tx and PCH FDI rx */
2148                 reg = FDI_TX_CTL(pipe);
2149                 temp = I915_READ(reg);
2150                 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2151                 POSTING_READ(reg);
2152
2153                 reg = FDI_RX_CTL(pipe);
2154                 temp = I915_READ(reg);
2155                 temp &= ~(0x7 << 16);
2156                 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2157                 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2158
2159                 POSTING_READ(reg);
2160                 udelay(100);
2161
2162                 /* Ironlake workaround, disable clock pointer after downing FDI */
2163                 if (HAS_PCH_IBX(dev))
2164                         I915_WRITE(FDI_RX_CHICKEN(pipe),
2165                                    I915_READ(FDI_RX_CHICKEN(pipe) &
2166                                              ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2167
2168                 /* still set train pattern 1 */
2169                 reg = FDI_TX_CTL(pipe);
2170                 temp = I915_READ(reg);
2171                 temp &= ~FDI_LINK_TRAIN_NONE;
2172                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2173                 I915_WRITE(reg, temp);
2174
2175                 reg = FDI_RX_CTL(pipe);
2176                 temp = I915_READ(reg);
2177                 if (HAS_PCH_CPT(dev)) {
2178                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2179                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2180                 } else {
2181                         temp &= ~FDI_LINK_TRAIN_NONE;
2182                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2183                 }
2184                 /* BPC in FDI rx is consistent with that in PIPECONF */
2185                 temp &= ~(0x07 << 16);
2186                 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2187                 I915_WRITE(reg, temp);
2188
2189                 POSTING_READ(reg);
2190                 udelay(100);
2191         }
2192
2193         /* Enable panel fitting for LVDS */
2194         if (dev_priv->pch_pf_size &&
2195             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2196                 /* Force use of hard-coded filter coefficients
2197                  * as some pre-programmed values are broken,
2198                  * e.g. x201.
2199                  */
2200                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2201                            PF_ENABLE | PF_FILTER_MED_3x3);
2202                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2203                            dev_priv->pch_pf_pos);
2204                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2205                            dev_priv->pch_pf_size);
2206         }
2207
2208         /* Enable CPU pipe */
2209         reg = PIPECONF(pipe);
2210         temp = I915_READ(reg);
2211         if ((temp & PIPECONF_ENABLE) == 0) {
2212                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2213                 POSTING_READ(reg);
2214                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2215         }
2216
2217         /* configure and enable CPU plane */
2218         reg = DSPCNTR(plane);
2219         temp = I915_READ(reg);
2220         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2221                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2222                 intel_flush_display_plane(dev, plane);
2223         }
2224
2225         /* Skip the PCH stuff if possible */
2226         if (!is_pch_port)
2227                 goto done;
2228
2229         /* For PCH output, training FDI link */
2230         if (IS_GEN6(dev))
2231                 gen6_fdi_link_train(crtc);
2232         else
2233                 ironlake_fdi_link_train(crtc);
2234
2235         /* enable PCH DPLL */
2236         reg = PCH_DPLL(pipe);
2237         temp = I915_READ(reg);
2238         if ((temp & DPLL_VCO_ENABLE) == 0) {
2239                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2240                 POSTING_READ(reg);
2241                 udelay(200);
2242         }
2243
2244         if (HAS_PCH_CPT(dev)) {
2245                 /* Be sure PCH DPLL SEL is set */
2246                 temp = I915_READ(PCH_DPLL_SEL);
2247                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2248                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2249                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2250                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2251                 I915_WRITE(PCH_DPLL_SEL, temp);
2252         }
2253
2254         /* set transcoder timing */
2255         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2256         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2257         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2258
2259         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2260         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2261         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2262
2263         intel_fdi_normal_train(crtc);
2264
2265         /* For PCH DP, enable TRANS_DP_CTL */
2266         if (HAS_PCH_CPT(dev) &&
2267             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2268                 reg = TRANS_DP_CTL(pipe);
2269                 temp = I915_READ(reg);
2270                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2271                           TRANS_DP_SYNC_MASK |
2272                           TRANS_DP_BPC_MASK);
2273                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2274                          TRANS_DP_ENH_FRAMING);
2275                 temp |= TRANS_DP_8BPC;
2276
2277                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2278                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2279                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2280                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2281
2282                 switch (intel_trans_dp_port_sel(crtc)) {
2283                 case PCH_DP_B:
2284                         temp |= TRANS_DP_PORT_SEL_B;
2285                         break;
2286                 case PCH_DP_C:
2287                         temp |= TRANS_DP_PORT_SEL_C;
2288                         break;
2289                 case PCH_DP_D:
2290                         temp |= TRANS_DP_PORT_SEL_D;
2291                         break;
2292                 default:
2293                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2294                         temp |= TRANS_DP_PORT_SEL_B;
2295                         break;
2296                 }
2297
2298                 I915_WRITE(reg, temp);
2299         }
2300
2301         /* enable PCH transcoder */
2302         reg = TRANSCONF(pipe);
2303         temp = I915_READ(reg);
2304         /*
2305          * make the BPC in transcoder be consistent with
2306          * that in pipeconf reg.
2307          */
2308         temp &= ~PIPE_BPC_MASK;
2309         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2310         I915_WRITE(reg, temp | TRANS_ENABLE);
2311         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2312                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2313 done:
2314         intel_crtc_load_lut(crtc);
2315         intel_update_fbc(dev);
2316         intel_crtc_update_cursor(crtc, true);
2317 }
2318
2319 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2320 {
2321         struct drm_device *dev = crtc->dev;
2322         struct drm_i915_private *dev_priv = dev->dev_private;
2323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324         int pipe = intel_crtc->pipe;
2325         int plane = intel_crtc->plane;
2326         u32 reg, temp;
2327
2328         if (!intel_crtc->active)
2329                 return;
2330
2331         intel_crtc_wait_for_pending_flips(crtc);
2332         drm_vblank_off(dev, pipe);
2333         intel_crtc_update_cursor(crtc, false);
2334
2335         /* Disable display plane */
2336         reg = DSPCNTR(plane);
2337         temp = I915_READ(reg);
2338         if (temp & DISPLAY_PLANE_ENABLE) {
2339                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2340                 intel_flush_display_plane(dev, plane);
2341         }
2342
2343         if (dev_priv->cfb_plane == plane &&
2344             dev_priv->display.disable_fbc)
2345                 dev_priv->display.disable_fbc(dev);
2346
2347         /* disable cpu pipe, disable after all planes disabled */
2348         reg = PIPECONF(pipe);
2349         temp = I915_READ(reg);
2350         if (temp & PIPECONF_ENABLE) {
2351                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2352                 POSTING_READ(reg);
2353                 /* wait for cpu pipe off, pipe state */
2354                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2355         }
2356
2357         /* Disable PF */
2358         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2359         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2360
2361         /* disable CPU FDI tx and PCH FDI rx */
2362         reg = FDI_TX_CTL(pipe);
2363         temp = I915_READ(reg);
2364         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2365         POSTING_READ(reg);
2366
2367         reg = FDI_RX_CTL(pipe);
2368         temp = I915_READ(reg);
2369         temp &= ~(0x7 << 16);
2370         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2371         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2372
2373         POSTING_READ(reg);
2374         udelay(100);
2375
2376         /* Ironlake workaround, disable clock pointer after downing FDI */
2377         if (HAS_PCH_IBX(dev))
2378                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2379                            I915_READ(FDI_RX_CHICKEN(pipe) &
2380                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2381
2382         /* still set train pattern 1 */
2383         reg = FDI_TX_CTL(pipe);
2384         temp = I915_READ(reg);
2385         temp &= ~FDI_LINK_TRAIN_NONE;
2386         temp |= FDI_LINK_TRAIN_PATTERN_1;
2387         I915_WRITE(reg, temp);
2388
2389         reg = FDI_RX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         if (HAS_PCH_CPT(dev)) {
2392                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2393                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2394         } else {
2395                 temp &= ~FDI_LINK_TRAIN_NONE;
2396                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2397         }
2398         /* BPC in FDI rx is consistent with that in PIPECONF */
2399         temp &= ~(0x07 << 16);
2400         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2401         I915_WRITE(reg, temp);
2402
2403         POSTING_READ(reg);
2404         udelay(100);
2405
2406         /* This is a horrible layering violation; we should be doing this in
2407          * the connector/encoder ->prepare instead, but we don't always have
2408          * enough information there about the config to know whether it will
2409          * actually be necessary or just cause undesired flicker.
2410          */
2411         intel_disable_pch_ports(dev_priv, pipe);
2412
2413         /* disable PCH transcoder */
2414         reg = TRANSCONF(plane);
2415         temp = I915_READ(reg);
2416         if (temp & TRANS_ENABLE) {
2417                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2418                 /* wait for PCH transcoder off, transcoder state */
2419                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2420                         DRM_ERROR("failed to disable transcoder\n");
2421         }
2422
2423         if (HAS_PCH_CPT(dev)) {
2424                 /* disable TRANS_DP_CTL */
2425                 reg = TRANS_DP_CTL(pipe);
2426                 temp = I915_READ(reg);
2427                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2428                 I915_WRITE(reg, temp);
2429
2430                 /* disable DPLL_SEL */
2431                 temp = I915_READ(PCH_DPLL_SEL);
2432                 if (pipe == 0)
2433                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2434                 else
2435                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2436                 I915_WRITE(PCH_DPLL_SEL, temp);
2437         }
2438
2439         /* disable PCH DPLL */
2440         reg = PCH_DPLL(pipe);
2441         temp = I915_READ(reg);
2442         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2443
2444         /* Switch from PCDclk to Rawclk */
2445         reg = FDI_RX_CTL(pipe);
2446         temp = I915_READ(reg);
2447         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2448
2449         /* Disable CPU FDI TX PLL */
2450         reg = FDI_TX_CTL(pipe);
2451         temp = I915_READ(reg);
2452         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2453
2454         POSTING_READ(reg);
2455         udelay(100);
2456
2457         reg = FDI_RX_CTL(pipe);
2458         temp = I915_READ(reg);
2459         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2460
2461         /* Wait for the clocks to turn off. */
2462         POSTING_READ(reg);
2463         udelay(100);
2464
2465         intel_crtc->active = false;
2466         intel_update_watermarks(dev);
2467         intel_update_fbc(dev);
2468         intel_clear_scanline_wait(dev);
2469 }
2470
2471 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2472 {
2473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2474         int pipe = intel_crtc->pipe;
2475         int plane = intel_crtc->plane;
2476
2477         /* XXX: When our outputs are all unaware of DPMS modes other than off
2478          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2479          */
2480         switch (mode) {
2481         case DRM_MODE_DPMS_ON:
2482         case DRM_MODE_DPMS_STANDBY:
2483         case DRM_MODE_DPMS_SUSPEND:
2484                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2485                 ironlake_crtc_enable(crtc);
2486                 break;
2487
2488         case DRM_MODE_DPMS_OFF:
2489                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2490                 ironlake_crtc_disable(crtc);
2491                 break;
2492         }
2493 }
2494
2495 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2496 {
2497         if (!enable && intel_crtc->overlay) {
2498                 struct drm_device *dev = intel_crtc->base.dev;
2499
2500                 mutex_lock(&dev->struct_mutex);
2501                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2502                 mutex_unlock(&dev->struct_mutex);
2503         }
2504
2505         /* Let userspace switch the overlay on again. In most cases userspace
2506          * has to recompute where to put it anyway.
2507          */
2508 }
2509
2510 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2511 {
2512         struct drm_device *dev = crtc->dev;
2513         struct drm_i915_private *dev_priv = dev->dev_private;
2514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2515         int pipe = intel_crtc->pipe;
2516         int plane = intel_crtc->plane;
2517         u32 reg, temp;
2518
2519         if (intel_crtc->active)
2520                 return;
2521
2522         intel_crtc->active = true;
2523         intel_update_watermarks(dev);
2524
2525         /* Enable the DPLL */
2526         reg = DPLL(pipe);
2527         temp = I915_READ(reg);
2528         if ((temp & DPLL_VCO_ENABLE) == 0) {
2529                 I915_WRITE(reg, temp);
2530
2531                 /* Wait for the clocks to stabilize. */
2532                 POSTING_READ(reg);
2533                 udelay(150);
2534
2535                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2536
2537                 /* Wait for the clocks to stabilize. */
2538                 POSTING_READ(reg);
2539                 udelay(150);
2540
2541                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2542
2543                 /* Wait for the clocks to stabilize. */
2544                 POSTING_READ(reg);
2545                 udelay(150);
2546         }
2547
2548         /* Enable the pipe */
2549         reg = PIPECONF(pipe);
2550         temp = I915_READ(reg);
2551         if ((temp & PIPECONF_ENABLE) == 0)
2552                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2553
2554         /* Enable the plane */
2555         reg = DSPCNTR(plane);
2556         temp = I915_READ(reg);
2557         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2558                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2559                 intel_flush_display_plane(dev, plane);
2560         }
2561
2562         intel_crtc_load_lut(crtc);
2563         intel_update_fbc(dev);
2564
2565         /* Give the overlay scaler a chance to enable if it's on this pipe */
2566         intel_crtc_dpms_overlay(intel_crtc, true);
2567         intel_crtc_update_cursor(crtc, true);
2568 }
2569
2570 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2571 {
2572         struct drm_device *dev = crtc->dev;
2573         struct drm_i915_private *dev_priv = dev->dev_private;
2574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2575         int pipe = intel_crtc->pipe;
2576         int plane = intel_crtc->plane;
2577         u32 reg, temp;
2578
2579         if (!intel_crtc->active)
2580                 return;
2581
2582         /* Give the overlay scaler a chance to disable if it's on this pipe */
2583         intel_crtc_wait_for_pending_flips(crtc);
2584         drm_vblank_off(dev, pipe);
2585         intel_crtc_dpms_overlay(intel_crtc, false);
2586         intel_crtc_update_cursor(crtc, false);
2587
2588         if (dev_priv->cfb_plane == plane &&
2589             dev_priv->display.disable_fbc)
2590                 dev_priv->display.disable_fbc(dev);
2591
2592         /* Disable display plane */
2593         reg = DSPCNTR(plane);
2594         temp = I915_READ(reg);
2595         if (temp & DISPLAY_PLANE_ENABLE) {
2596                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2597                 /* Flush the plane changes */
2598                 intel_flush_display_plane(dev, plane);
2599
2600                 /* Wait for vblank for the disable to take effect */
2601                 if (IS_GEN2(dev))
2602                         intel_wait_for_vblank(dev, pipe);
2603         }
2604
2605         /* Don't disable pipe A or pipe A PLLs if needed */
2606         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2607                 goto done;
2608
2609         /* Next, disable display pipes */
2610         reg = PIPECONF(pipe);
2611         temp = I915_READ(reg);
2612         if (temp & PIPECONF_ENABLE) {
2613                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2614
2615                 /* Wait for the pipe to turn off */
2616                 POSTING_READ(reg);
2617                 intel_wait_for_pipe_off(dev, pipe);
2618         }
2619
2620         reg = DPLL(pipe);
2621         temp = I915_READ(reg);
2622         if (temp & DPLL_VCO_ENABLE) {
2623                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2624
2625                 /* Wait for the clocks to turn off. */
2626                 POSTING_READ(reg);
2627                 udelay(150);
2628         }
2629
2630 done:
2631         intel_crtc->active = false;
2632         intel_update_fbc(dev);
2633         intel_update_watermarks(dev);
2634         intel_clear_scanline_wait(dev);
2635 }
2636
2637 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2638 {
2639         /* XXX: When our outputs are all unaware of DPMS modes other than off
2640          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2641          */
2642         switch (mode) {
2643         case DRM_MODE_DPMS_ON:
2644         case DRM_MODE_DPMS_STANDBY:
2645         case DRM_MODE_DPMS_SUSPEND:
2646                 i9xx_crtc_enable(crtc);
2647                 break;
2648         case DRM_MODE_DPMS_OFF:
2649                 i9xx_crtc_disable(crtc);
2650                 break;
2651         }
2652 }
2653
2654 /**
2655  * Sets the power management mode of the pipe and plane.
2656  */
2657 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2658 {
2659         struct drm_device *dev = crtc->dev;
2660         struct drm_i915_private *dev_priv = dev->dev_private;
2661         struct drm_i915_master_private *master_priv;
2662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2663         int pipe = intel_crtc->pipe;
2664         bool enabled;
2665
2666         if (intel_crtc->dpms_mode == mode)
2667                 return;
2668
2669         intel_crtc->dpms_mode = mode;
2670
2671         dev_priv->display.dpms(crtc, mode);
2672
2673         if (!dev->primary->master)
2674                 return;
2675
2676         master_priv = dev->primary->master->driver_priv;
2677         if (!master_priv->sarea_priv)
2678                 return;
2679
2680         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2681
2682         switch (pipe) {
2683         case 0:
2684                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2685                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2686                 break;
2687         case 1:
2688                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2689                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2690                 break;
2691         default:
2692                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2693                 break;
2694         }
2695 }
2696
2697 static void intel_crtc_disable(struct drm_crtc *crtc)
2698 {
2699         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2700         struct drm_device *dev = crtc->dev;
2701
2702         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2703
2704         if (crtc->fb) {
2705                 mutex_lock(&dev->struct_mutex);
2706                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2707                 mutex_unlock(&dev->struct_mutex);
2708         }
2709 }
2710
2711 /* Prepare for a mode set.
2712  *
2713  * Note we could be a lot smarter here.  We need to figure out which outputs
2714  * will be enabled, which disabled (in short, how the config will changes)
2715  * and perform the minimum necessary steps to accomplish that, e.g. updating
2716  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2717  * panel fitting is in the proper state, etc.
2718  */
2719 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2720 {
2721         i9xx_crtc_disable(crtc);
2722 }
2723
2724 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2725 {
2726         i9xx_crtc_enable(crtc);
2727 }
2728
2729 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2730 {
2731         ironlake_crtc_disable(crtc);
2732 }
2733
2734 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2735 {
2736         ironlake_crtc_enable(crtc);
2737 }
2738
2739 void intel_encoder_prepare (struct drm_encoder *encoder)
2740 {
2741         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2742         /* lvds has its own version of prepare see intel_lvds_prepare */
2743         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2744 }
2745
2746 void intel_encoder_commit (struct drm_encoder *encoder)
2747 {
2748         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2749         /* lvds has its own version of commit see intel_lvds_commit */
2750         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2751 }
2752
2753 void intel_encoder_destroy(struct drm_encoder *encoder)
2754 {
2755         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2756
2757         drm_encoder_cleanup(encoder);
2758         kfree(intel_encoder);
2759 }
2760
2761 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2762                                   struct drm_display_mode *mode,
2763                                   struct drm_display_mode *adjusted_mode)
2764 {
2765         struct drm_device *dev = crtc->dev;
2766
2767         if (HAS_PCH_SPLIT(dev)) {
2768                 /* FDI link clock is fixed at 2.7G */
2769                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2770                         return false;
2771         }
2772
2773         /* XXX some encoders set the crtcinfo, others don't.
2774          * Obviously we need some form of conflict resolution here...
2775          */
2776         if (adjusted_mode->crtc_htotal == 0)
2777                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2778
2779         return true;
2780 }
2781
2782 static int i945_get_display_clock_speed(struct drm_device *dev)
2783 {
2784         return 400000;
2785 }
2786
2787 static int i915_get_display_clock_speed(struct drm_device *dev)
2788 {
2789         return 333000;
2790 }
2791
2792 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2793 {
2794         return 200000;
2795 }
2796
2797 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2798 {
2799         u16 gcfgc = 0;
2800
2801         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2802
2803         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2804                 return 133000;
2805         else {
2806                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2807                 case GC_DISPLAY_CLOCK_333_MHZ:
2808                         return 333000;
2809                 default:
2810                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2811                         return 190000;
2812                 }
2813         }
2814 }
2815
2816 static int i865_get_display_clock_speed(struct drm_device *dev)
2817 {
2818         return 266000;
2819 }
2820
2821 static int i855_get_display_clock_speed(struct drm_device *dev)
2822 {
2823         u16 hpllcc = 0;
2824         /* Assume that the hardware is in the high speed state.  This
2825          * should be the default.
2826          */
2827         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2828         case GC_CLOCK_133_200:
2829         case GC_CLOCK_100_200:
2830                 return 200000;
2831         case GC_CLOCK_166_250:
2832                 return 250000;
2833         case GC_CLOCK_100_133:
2834                 return 133000;
2835         }
2836
2837         /* Shouldn't happen */
2838         return 0;
2839 }
2840
2841 static int i830_get_display_clock_speed(struct drm_device *dev)
2842 {
2843         return 133000;
2844 }
2845
2846 struct fdi_m_n {
2847         u32        tu;
2848         u32        gmch_m;
2849         u32        gmch_n;
2850         u32        link_m;
2851         u32        link_n;
2852 };
2853
2854 static void
2855 fdi_reduce_ratio(u32 *num, u32 *den)
2856 {
2857         while (*num > 0xffffff || *den > 0xffffff) {
2858                 *num >>= 1;
2859                 *den >>= 1;
2860         }
2861 }
2862
2863 static void
2864 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2865                      int link_clock, struct fdi_m_n *m_n)
2866 {
2867         m_n->tu = 64; /* default size */
2868
2869         /* BUG_ON(pixel_clock > INT_MAX / 36); */
2870         m_n->gmch_m = bits_per_pixel * pixel_clock;
2871         m_n->gmch_n = link_clock * nlanes * 8;
2872         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2873
2874         m_n->link_m = pixel_clock;
2875         m_n->link_n = link_clock;
2876         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2877 }
2878
2879
2880 struct intel_watermark_params {
2881         unsigned long fifo_size;
2882         unsigned long max_wm;
2883         unsigned long default_wm;
2884         unsigned long guard_size;
2885         unsigned long cacheline_size;
2886 };
2887
2888 /* Pineview has different values for various configs */
2889 static struct intel_watermark_params pineview_display_wm = {
2890         PINEVIEW_DISPLAY_FIFO,
2891         PINEVIEW_MAX_WM,
2892         PINEVIEW_DFT_WM,
2893         PINEVIEW_GUARD_WM,
2894         PINEVIEW_FIFO_LINE_SIZE
2895 };
2896 static struct intel_watermark_params pineview_display_hplloff_wm = {
2897         PINEVIEW_DISPLAY_FIFO,
2898         PINEVIEW_MAX_WM,
2899         PINEVIEW_DFT_HPLLOFF_WM,
2900         PINEVIEW_GUARD_WM,
2901         PINEVIEW_FIFO_LINE_SIZE
2902 };
2903 static struct intel_watermark_params pineview_cursor_wm = {
2904         PINEVIEW_CURSOR_FIFO,
2905         PINEVIEW_CURSOR_MAX_WM,
2906         PINEVIEW_CURSOR_DFT_WM,
2907         PINEVIEW_CURSOR_GUARD_WM,
2908         PINEVIEW_FIFO_LINE_SIZE,
2909 };
2910 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2911         PINEVIEW_CURSOR_FIFO,
2912         PINEVIEW_CURSOR_MAX_WM,
2913         PINEVIEW_CURSOR_DFT_WM,
2914         PINEVIEW_CURSOR_GUARD_WM,
2915         PINEVIEW_FIFO_LINE_SIZE
2916 };
2917 static struct intel_watermark_params g4x_wm_info = {
2918         G4X_FIFO_SIZE,
2919         G4X_MAX_WM,
2920         G4X_MAX_WM,
2921         2,
2922         G4X_FIFO_LINE_SIZE,
2923 };
2924 static struct intel_watermark_params g4x_cursor_wm_info = {
2925         I965_CURSOR_FIFO,
2926         I965_CURSOR_MAX_WM,
2927         I965_CURSOR_DFT_WM,
2928         2,
2929         G4X_FIFO_LINE_SIZE,
2930 };
2931 static struct intel_watermark_params i965_cursor_wm_info = {
2932         I965_CURSOR_FIFO,
2933         I965_CURSOR_MAX_WM,
2934         I965_CURSOR_DFT_WM,
2935         2,
2936         I915_FIFO_LINE_SIZE,
2937 };
2938 static struct intel_watermark_params i945_wm_info = {
2939         I945_FIFO_SIZE,
2940         I915_MAX_WM,
2941         1,
2942         2,
2943         I915_FIFO_LINE_SIZE
2944 };
2945 static struct intel_watermark_params i915_wm_info = {
2946         I915_FIFO_SIZE,
2947         I915_MAX_WM,
2948         1,
2949         2,
2950         I915_FIFO_LINE_SIZE
2951 };
2952 static struct intel_watermark_params i855_wm_info = {
2953         I855GM_FIFO_SIZE,
2954         I915_MAX_WM,
2955         1,
2956         2,
2957         I830_FIFO_LINE_SIZE
2958 };
2959 static struct intel_watermark_params i830_wm_info = {
2960         I830_FIFO_SIZE,
2961         I915_MAX_WM,
2962         1,
2963         2,
2964         I830_FIFO_LINE_SIZE
2965 };
2966
2967 static struct intel_watermark_params ironlake_display_wm_info = {
2968         ILK_DISPLAY_FIFO,
2969         ILK_DISPLAY_MAXWM,
2970         ILK_DISPLAY_DFTWM,
2971         2,
2972         ILK_FIFO_LINE_SIZE
2973 };
2974
2975 static struct intel_watermark_params ironlake_cursor_wm_info = {
2976         ILK_CURSOR_FIFO,
2977         ILK_CURSOR_MAXWM,
2978         ILK_CURSOR_DFTWM,
2979         2,
2980         ILK_FIFO_LINE_SIZE
2981 };
2982
2983 static struct intel_watermark_params ironlake_display_srwm_info = {
2984         ILK_DISPLAY_SR_FIFO,
2985         ILK_DISPLAY_MAX_SRWM,
2986         ILK_DISPLAY_DFT_SRWM,
2987         2,
2988         ILK_FIFO_LINE_SIZE
2989 };
2990
2991 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2992         ILK_CURSOR_SR_FIFO,
2993         ILK_CURSOR_MAX_SRWM,
2994         ILK_CURSOR_DFT_SRWM,
2995         2,
2996         ILK_FIFO_LINE_SIZE
2997 };
2998
2999 static struct intel_watermark_params sandybridge_display_wm_info = {
3000         SNB_DISPLAY_FIFO,
3001         SNB_DISPLAY_MAXWM,
3002         SNB_DISPLAY_DFTWM,
3003         2,
3004         SNB_FIFO_LINE_SIZE
3005 };
3006
3007 static struct intel_watermark_params sandybridge_cursor_wm_info = {
3008         SNB_CURSOR_FIFO,
3009         SNB_CURSOR_MAXWM,
3010         SNB_CURSOR_DFTWM,
3011         2,
3012         SNB_FIFO_LINE_SIZE
3013 };
3014
3015 static struct intel_watermark_params sandybridge_display_srwm_info = {
3016         SNB_DISPLAY_SR_FIFO,
3017         SNB_DISPLAY_MAX_SRWM,
3018         SNB_DISPLAY_DFT_SRWM,
3019         2,
3020         SNB_FIFO_LINE_SIZE
3021 };
3022
3023 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
3024         SNB_CURSOR_SR_FIFO,
3025         SNB_CURSOR_MAX_SRWM,
3026         SNB_CURSOR_DFT_SRWM,
3027         2,
3028         SNB_FIFO_LINE_SIZE
3029 };
3030
3031
3032 /**
3033  * intel_calculate_wm - calculate watermark level
3034  * @clock_in_khz: pixel clock
3035  * @wm: chip FIFO params
3036  * @pixel_size: display pixel size
3037  * @latency_ns: memory latency for the platform
3038  *
3039  * Calculate the watermark level (the level at which the display plane will
3040  * start fetching from memory again).  Each chip has a different display
3041  * FIFO size and allocation, so the caller needs to figure that out and pass
3042  * in the correct intel_watermark_params structure.
3043  *
3044  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3045  * on the pixel size.  When it reaches the watermark level, it'll start
3046  * fetching FIFO line sized based chunks from memory until the FIFO fills
3047  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3048  * will occur, and a display engine hang could result.
3049  */
3050 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3051                                         struct intel_watermark_params *wm,
3052                                         int pixel_size,
3053                                         unsigned long latency_ns)
3054 {
3055         long entries_required, wm_size;
3056
3057         /*
3058          * Note: we need to make sure we don't overflow for various clock &
3059          * latency values.
3060          * clocks go from a few thousand to several hundred thousand.
3061          * latency is usually a few thousand
3062          */
3063         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3064                 1000;
3065         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3066
3067         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3068
3069         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
3070
3071         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3072
3073         /* Don't promote wm_size to unsigned... */
3074         if (wm_size > (long)wm->max_wm)
3075                 wm_size = wm->max_wm;
3076         if (wm_size <= 0)
3077                 wm_size = wm->default_wm;
3078         return wm_size;
3079 }
3080
3081 struct cxsr_latency {
3082         int is_desktop;
3083         int is_ddr3;
3084         unsigned long fsb_freq;
3085         unsigned long mem_freq;
3086         unsigned long display_sr;
3087         unsigned long display_hpll_disable;
3088         unsigned long cursor_sr;
3089         unsigned long cursor_hpll_disable;
3090 };
3091
3092 static const struct cxsr_latency cxsr_latency_table[] = {
3093         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3094         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3095         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3096         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3097         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3098
3099         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3100         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3101         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3102         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3103         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3104
3105         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3106         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3107         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3108         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3109         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3110
3111         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3112         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3113         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3114         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3115         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3116
3117         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3118         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3119         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3120         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3121         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3122
3123         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3124         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3125         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3126         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3127         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3128 };
3129
3130 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3131                                                          int is_ddr3,
3132                                                          int fsb,
3133                                                          int mem)
3134 {
3135         const struct cxsr_latency *latency;
3136         int i;
3137
3138         if (fsb == 0 || mem == 0)
3139                 return NULL;
3140
3141         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3142                 latency = &cxsr_latency_table[i];
3143                 if (is_desktop == latency->is_desktop &&
3144                     is_ddr3 == latency->is_ddr3 &&
3145                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3146                         return latency;
3147         }
3148
3149         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3150
3151         return NULL;
3152 }
3153
3154 static void pineview_disable_cxsr(struct drm_device *dev)
3155 {
3156         struct drm_i915_private *dev_priv = dev->dev_private;
3157
3158         /* deactivate cxsr */
3159         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3160 }
3161
3162 /*
3163  * Latency for FIFO fetches is dependent on several factors:
3164  *   - memory configuration (speed, channels)
3165  *   - chipset
3166  *   - current MCH state
3167  * It can be fairly high in some situations, so here we assume a fairly
3168  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3169  * set this value too high, the FIFO will fetch frequently to stay full)
3170  * and power consumption (set it too low to save power and we might see
3171  * FIFO underruns and display "flicker").
3172  *
3173  * A value of 5us seems to be a good balance; safe for very low end
3174  * platforms but not overly aggressive on lower latency configs.
3175  */
3176 static const int latency_ns = 5000;
3177
3178 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3179 {
3180         struct drm_i915_private *dev_priv = dev->dev_private;
3181         uint32_t dsparb = I915_READ(DSPARB);
3182         int size;
3183
3184         size = dsparb & 0x7f;
3185         if (plane)
3186                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3187
3188         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3189                       plane ? "B" : "A", size);
3190
3191         return size;
3192 }
3193
3194 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3195 {
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         uint32_t dsparb = I915_READ(DSPARB);
3198         int size;
3199
3200         size = dsparb & 0x1ff;
3201         if (plane)
3202                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3203         size >>= 1; /* Convert to cachelines */
3204
3205         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3206                       plane ? "B" : "A", size);
3207
3208         return size;
3209 }
3210
3211 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3212 {
3213         struct drm_i915_private *dev_priv = dev->dev_private;
3214         uint32_t dsparb = I915_READ(DSPARB);
3215         int size;
3216
3217         size = dsparb & 0x7f;
3218         size >>= 2; /* Convert to cachelines */
3219
3220         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3221                       plane ? "B" : "A",
3222                       size);
3223
3224         return size;
3225 }
3226
3227 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3228 {
3229         struct drm_i915_private *dev_priv = dev->dev_private;
3230         uint32_t dsparb = I915_READ(DSPARB);
3231         int size;
3232
3233         size = dsparb & 0x7f;
3234         size >>= 1; /* Convert to cachelines */
3235
3236         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3237                       plane ? "B" : "A", size);
3238
3239         return size;
3240 }
3241
3242 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3243                                int planeb_clock, int sr_hdisplay, int unused,
3244                                int pixel_size)
3245 {
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         const struct cxsr_latency *latency;
3248         u32 reg;
3249         unsigned long wm;
3250         int sr_clock;
3251
3252         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3253                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3254         if (!latency) {
3255                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3256                 pineview_disable_cxsr(dev);
3257                 return;
3258         }
3259
3260         if (!planea_clock || !planeb_clock) {
3261                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3262
3263                 /* Display SR */
3264                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3265                                         pixel_size, latency->display_sr);
3266                 reg = I915_READ(DSPFW1);
3267                 reg &= ~DSPFW_SR_MASK;
3268                 reg |= wm << DSPFW_SR_SHIFT;
3269                 I915_WRITE(DSPFW1, reg);
3270                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3271
3272                 /* cursor SR */
3273                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3274                                         pixel_size, latency->cursor_sr);
3275                 reg = I915_READ(DSPFW3);
3276                 reg &= ~DSPFW_CURSOR_SR_MASK;
3277                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3278                 I915_WRITE(DSPFW3, reg);
3279
3280                 /* Display HPLL off SR */
3281                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3282                                         pixel_size, latency->display_hpll_disable);
3283                 reg = I915_READ(DSPFW3);
3284                 reg &= ~DSPFW_HPLL_SR_MASK;
3285                 reg |= wm & DSPFW_HPLL_SR_MASK;
3286                 I915_WRITE(DSPFW3, reg);
3287
3288                 /* cursor HPLL off SR */
3289                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3290                                         pixel_size, latency->cursor_hpll_disable);
3291                 reg = I915_READ(DSPFW3);
3292                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3293                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3294                 I915_WRITE(DSPFW3, reg);
3295                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3296
3297                 /* activate cxsr */
3298                 I915_WRITE(DSPFW3,
3299                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3300                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3301         } else {
3302                 pineview_disable_cxsr(dev);
3303                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3304         }
3305 }
3306
3307 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3308                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3309                           int pixel_size)
3310 {
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         int total_size, cacheline_size;
3313         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3314         struct intel_watermark_params planea_params, planeb_params;
3315         unsigned long line_time_us;
3316         int sr_clock, sr_entries = 0, entries_required;
3317
3318         /* Create copies of the base settings for each pipe */
3319         planea_params = planeb_params = g4x_wm_info;
3320
3321         /* Grab a couple of global values before we overwrite them */
3322         total_size = planea_params.fifo_size;
3323         cacheline_size = planea_params.cacheline_size;
3324
3325         /*
3326          * Note: we need to make sure we don't overflow for various clock &
3327          * latency values.
3328          * clocks go from a few thousand to several hundred thousand.
3329          * latency is usually a few thousand
3330          */
3331         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3332                 1000;
3333         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3334         planea_wm = entries_required + planea_params.guard_size;
3335
3336         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3337                 1000;
3338         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3339         planeb_wm = entries_required + planeb_params.guard_size;
3340
3341         cursora_wm = cursorb_wm = 16;
3342         cursor_sr = 32;
3343
3344         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3345
3346         /* Calc sr entries for one plane configs */
3347         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3348                 /* self-refresh has much higher latency */
3349                 static const int sr_latency_ns = 12000;
3350
3351                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3352                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3353
3354                 /* Use ns/us then divide to preserve precision */
3355                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3356                         pixel_size * sr_hdisplay;
3357                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3358
3359                 entries_required = (((sr_latency_ns / line_time_us) +
3360                                      1000) / 1000) * pixel_size * 64;
3361                 entries_required = DIV_ROUND_UP(entries_required,
3362                                                 g4x_cursor_wm_info.cacheline_size);
3363                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3364
3365                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3366                         cursor_sr = g4x_cursor_wm_info.max_wm;
3367                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3368                               "cursor %d\n", sr_entries, cursor_sr);
3369
3370                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3371         } else {
3372                 /* Turn off self refresh if both pipes are enabled */
3373                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3374                            & ~FW_BLC_SELF_EN);
3375         }
3376
3377         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3378                   planea_wm, planeb_wm, sr_entries);
3379
3380         planea_wm &= 0x3f;
3381         planeb_wm &= 0x3f;
3382
3383         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3384                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3385                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3386         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3387                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3388         /* HPLL off in SR has some issues on G4x... disable it */
3389         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3390                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3391 }
3392
3393 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3394                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3395                            int pixel_size)
3396 {
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         unsigned long line_time_us;
3399         int sr_clock, sr_entries, srwm = 1;
3400         int cursor_sr = 16;
3401
3402         /* Calc sr entries for one plane configs */
3403         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3404                 /* self-refresh has much higher latency */
3405                 static const int sr_latency_ns = 12000;
3406
3407                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3408                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3409
3410                 /* Use ns/us then divide to preserve precision */
3411                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3412                         pixel_size * sr_hdisplay;
3413                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3414                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3415                 srwm = I965_FIFO_SIZE - sr_entries;
3416                 if (srwm < 0)
3417                         srwm = 1;
3418                 srwm &= 0x1ff;
3419
3420                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3421                         pixel_size * 64;
3422                 sr_entries = DIV_ROUND_UP(sr_entries,
3423                                           i965_cursor_wm_info.cacheline_size);
3424                 cursor_sr = i965_cursor_wm_info.fifo_size -
3425                         (sr_entries + i965_cursor_wm_info.guard_size);
3426
3427                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3428                         cursor_sr = i965_cursor_wm_info.max_wm;
3429
3430                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3431                               "cursor %d\n", srwm, cursor_sr);
3432
3433                 if (IS_CRESTLINE(dev))
3434                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3435         } else {
3436                 /* Turn off self refresh if both pipes are enabled */
3437                 if (IS_CRESTLINE(dev))
3438                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3439                                    & ~FW_BLC_SELF_EN);
3440         }
3441
3442         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3443                       srwm);
3444
3445         /* 965 has limitations... */
3446         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3447                    (8 << 0));
3448         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3449         /* update cursor SR watermark */
3450         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3451 }
3452
3453 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3454                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3455                            int pixel_size)
3456 {
3457         struct drm_i915_private *dev_priv = dev->dev_private;
3458         uint32_t fwater_lo;
3459         uint32_t fwater_hi;
3460         int total_size, cacheline_size, cwm, srwm = 1;
3461         int planea_wm, planeb_wm;
3462         struct intel_watermark_params planea_params, planeb_params;
3463         unsigned long line_time_us;
3464         int sr_clock, sr_entries = 0;
3465
3466         /* Create copies of the base settings for each pipe */
3467         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3468                 planea_params = planeb_params = i945_wm_info;
3469         else if (!IS_GEN2(dev))
3470                 planea_params = planeb_params = i915_wm_info;
3471         else
3472                 planea_params = planeb_params = i855_wm_info;
3473
3474         /* Grab a couple of global values before we overwrite them */
3475         total_size = planea_params.fifo_size;
3476         cacheline_size = planea_params.cacheline_size;
3477
3478         /* Update per-plane FIFO sizes */
3479         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3480         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3481
3482         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3483                                        pixel_size, latency_ns);
3484         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3485                                        pixel_size, latency_ns);
3486         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3487
3488         /*
3489          * Overlay gets an aggressive default since video jitter is bad.
3490          */
3491         cwm = 2;
3492
3493         /* Calc sr entries for one plane configs */
3494         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3495             (!planea_clock || !planeb_clock)) {
3496                 /* self-refresh has much higher latency */
3497                 static const int sr_latency_ns = 6000;
3498
3499                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3500                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3501
3502                 /* Use ns/us then divide to preserve precision */
3503                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3504                         pixel_size * sr_hdisplay;
3505                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3506                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3507                 srwm = total_size - sr_entries;
3508                 if (srwm < 0)
3509                         srwm = 1;
3510
3511                 if (IS_I945G(dev) || IS_I945GM(dev))
3512                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3513                 else if (IS_I915GM(dev)) {
3514                         /* 915M has a smaller SRWM field */
3515                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3516                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3517                 }
3518         } else {
3519                 /* Turn off self refresh if both pipes are enabled */
3520                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3521                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3522                                    & ~FW_BLC_SELF_EN);
3523                 } else if (IS_I915GM(dev)) {
3524                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3525                 }
3526         }
3527
3528         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3529                       planea_wm, planeb_wm, cwm, srwm);
3530
3531         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3532         fwater_hi = (cwm & 0x1f);
3533
3534         /* Set request length to 8 cachelines per fetch */
3535         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3536         fwater_hi = fwater_hi | (1 << 8);
3537
3538         I915_WRITE(FW_BLC, fwater_lo);
3539         I915_WRITE(FW_BLC2, fwater_hi);
3540 }
3541
3542 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3543                            int unused2, int unused3, int pixel_size)
3544 {
3545         struct drm_i915_private *dev_priv = dev->dev_private;
3546         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3547         int planea_wm;
3548
3549         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3550
3551         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3552                                        pixel_size, latency_ns);
3553         fwater_lo |= (3<<8) | planea_wm;
3554
3555         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3556
3557         I915_WRITE(FW_BLC, fwater_lo);
3558 }
3559
3560 #define ILK_LP0_PLANE_LATENCY           700
3561 #define ILK_LP0_CURSOR_LATENCY          1300
3562
3563 static bool ironlake_compute_wm0(struct drm_device *dev,
3564                                  int pipe,
3565                                  const struct intel_watermark_params *display,
3566                                  int display_latency_ns,
3567                                  const struct intel_watermark_params *cursor,
3568                                  int cursor_latency_ns,
3569                                  int *plane_wm,
3570                                  int *cursor_wm)
3571 {
3572         struct drm_crtc *crtc;
3573         int htotal, hdisplay, clock, pixel_size;
3574         int line_time_us, line_count;
3575         int entries, tlb_miss;
3576
3577         crtc = intel_get_crtc_for_pipe(dev, pipe);
3578         if (crtc->fb == NULL || !crtc->enabled)
3579                 return false;
3580
3581         htotal = crtc->mode.htotal;
3582         hdisplay = crtc->mode.hdisplay;
3583         clock = crtc->mode.clock;
3584         pixel_size = crtc->fb->bits_per_pixel / 8;
3585
3586         /* Use the small buffer method to calculate plane watermark */
3587         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3588         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3589         if (tlb_miss > 0)
3590                 entries += tlb_miss;
3591         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3592         *plane_wm = entries + display->guard_size;
3593         if (*plane_wm > (int)display->max_wm)
3594                 *plane_wm = display->max_wm;
3595
3596         /* Use the large buffer method to calculate cursor watermark */
3597         line_time_us = ((htotal * 1000) / clock);
3598         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3599         entries = line_count * 64 * pixel_size;
3600         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3601         if (tlb_miss > 0)
3602                 entries += tlb_miss;
3603         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3604         *cursor_wm = entries + cursor->guard_size;
3605         if (*cursor_wm > (int)cursor->max_wm)
3606                 *cursor_wm = (int)cursor->max_wm;
3607
3608         return true;
3609 }
3610
3611 /*
3612  * Check the wm result.
3613  *
3614  * If any calculated watermark values is larger than the maximum value that
3615  * can be programmed into the associated watermark register, that watermark
3616  * must be disabled.
3617  */
3618 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3619                                 int fbc_wm, int display_wm, int cursor_wm,
3620                                 const struct intel_watermark_params *display,
3621                                 const struct intel_watermark_params *cursor)
3622 {
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624
3625         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3626                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3627
3628         if (fbc_wm > SNB_FBC_MAX_SRWM) {
3629                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3630                               fbc_wm, SNB_FBC_MAX_SRWM, level);
3631
3632                 /* fbc has it's own way to disable FBC WM */
3633                 I915_WRITE(DISP_ARB_CTL,
3634                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3635                 return false;
3636         }
3637
3638         if (display_wm > display->max_wm) {
3639                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3640                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
3641                 return false;
3642         }
3643
3644         if (cursor_wm > cursor->max_wm) {
3645                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3646                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3647                 return false;
3648         }
3649
3650         if (!(fbc_wm || display_wm || cursor_wm)) {
3651                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3652                 return false;
3653         }
3654
3655         return true;
3656 }
3657
3658 /*
3659  * Compute watermark values of WM[1-3],
3660  */
3661 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3662                                   int hdisplay, int htotal,
3663                                   int pixel_size, int clock, int latency_ns,
3664                                   const struct intel_watermark_params *display,
3665                                   const struct intel_watermark_params *cursor,
3666                                   int *fbc_wm, int *display_wm, int *cursor_wm)
3667 {
3668
3669         unsigned long line_time_us;
3670         int line_count, line_size;
3671         int small, large;
3672         int entries;
3673
3674         if (!latency_ns) {
3675                 *fbc_wm = *display_wm = *cursor_wm = 0;
3676                 return false;
3677         }
3678
3679         line_time_us = (htotal * 1000) / clock;
3680         line_count = (latency_ns / line_time_us + 1000) / 1000;
3681         line_size = hdisplay * pixel_size;
3682
3683         /* Use the minimum of the small and large buffer method for primary */
3684         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3685         large = line_count * line_size;
3686
3687         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3688         *display_wm = entries + display->guard_size;
3689
3690         /*
3691          * Spec says:
3692          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3693          */
3694         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3695
3696         /* calculate the self-refresh watermark for display cursor */
3697         entries = line_count * pixel_size * 64;
3698         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3699         *cursor_wm = entries + cursor->guard_size;
3700
3701         return ironlake_check_srwm(dev, level,
3702                                    *fbc_wm, *display_wm, *cursor_wm,
3703                                    display, cursor);
3704 }
3705
3706 static void ironlake_update_wm(struct drm_device *dev,
3707                                int planea_clock, int planeb_clock,
3708                                int hdisplay, int htotal,
3709                                int pixel_size)
3710 {
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712         int fbc_wm, plane_wm, cursor_wm, enabled;
3713         int clock;
3714
3715         enabled = 0;
3716         if (ironlake_compute_wm0(dev, 0,
3717                                  &ironlake_display_wm_info,
3718                                  ILK_LP0_PLANE_LATENCY,
3719                                  &ironlake_cursor_wm_info,
3720                                  ILK_LP0_CURSOR_LATENCY,
3721                                  &plane_wm, &cursor_wm)) {
3722                 I915_WRITE(WM0_PIPEA_ILK,
3723                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3724                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3725                               " plane %d, " "cursor: %d\n",
3726                               plane_wm, cursor_wm);
3727                 enabled++;
3728         }
3729
3730         if (ironlake_compute_wm0(dev, 1,
3731                                  &ironlake_display_wm_info,
3732                                  ILK_LP0_PLANE_LATENCY,
3733                                  &ironlake_cursor_wm_info,
3734                                  ILK_LP0_CURSOR_LATENCY,
3735                                  &plane_wm, &cursor_wm)) {
3736                 I915_WRITE(WM0_PIPEB_ILK,
3737                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3738                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3739                               " plane %d, cursor: %d\n",
3740                               plane_wm, cursor_wm);
3741                 enabled++;
3742         }
3743
3744         /*
3745          * Calculate and update the self-refresh watermark only when one
3746          * display plane is used.
3747          */
3748         I915_WRITE(WM3_LP_ILK, 0);
3749         I915_WRITE(WM2_LP_ILK, 0);
3750         I915_WRITE(WM1_LP_ILK, 0);
3751
3752         if (enabled != 1)
3753                 return;
3754
3755         clock = planea_clock ? planea_clock : planeb_clock;
3756
3757         /* WM1 */
3758         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3759                                    clock, ILK_READ_WM1_LATENCY() * 500,
3760                                    &ironlake_display_srwm_info,
3761                                    &ironlake_cursor_srwm_info,
3762                                    &fbc_wm, &plane_wm, &cursor_wm))
3763                 return;
3764
3765         I915_WRITE(WM1_LP_ILK,
3766                    WM1_LP_SR_EN |
3767                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3768                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3769                    (plane_wm << WM1_LP_SR_SHIFT) |
3770                    cursor_wm);
3771
3772         /* WM2 */
3773         if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
3774                                    clock, ILK_READ_WM2_LATENCY() * 500,
3775                                    &ironlake_display_srwm_info,
3776                                    &ironlake_cursor_srwm_info,
3777                                    &fbc_wm, &plane_wm, &cursor_wm))
3778                 return;
3779
3780         I915_WRITE(WM2_LP_ILK,
3781                    WM2_LP_EN |
3782                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3783                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3784                    (plane_wm << WM1_LP_SR_SHIFT) |
3785                    cursor_wm);
3786
3787         /*
3788          * WM3 is unsupported on ILK, probably because we don't have latency
3789          * data for that power state
3790          */
3791 }
3792
3793 static void sandybridge_update_wm(struct drm_device *dev,
3794                                int planea_clock, int planeb_clock,
3795                                int hdisplay, int htotal,
3796                                int pixel_size)
3797 {
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
3800         int fbc_wm, plane_wm, cursor_wm, enabled;
3801         int clock;
3802
3803         enabled = 0;
3804         if (ironlake_compute_wm0(dev, 0,
3805                                  &sandybridge_display_wm_info, latency,
3806                                  &sandybridge_cursor_wm_info, latency,
3807                                  &plane_wm, &cursor_wm)) {
3808                 I915_WRITE(WM0_PIPEA_ILK,
3809                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3810                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3811                               " plane %d, " "cursor: %d\n",
3812                               plane_wm, cursor_wm);
3813                 enabled++;
3814         }
3815
3816         if (ironlake_compute_wm0(dev, 1,
3817                                  &sandybridge_display_wm_info, latency,
3818                                  &sandybridge_cursor_wm_info, latency,
3819                                  &plane_wm, &cursor_wm)) {
3820                 I915_WRITE(WM0_PIPEB_ILK,
3821                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3822                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3823                               " plane %d, cursor: %d\n",
3824                               plane_wm, cursor_wm);
3825                 enabled++;
3826         }
3827
3828         /*
3829          * Calculate and update the self-refresh watermark only when one
3830          * display plane is used.
3831          *
3832          * SNB support 3 levels of watermark.
3833          *
3834          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3835          * and disabled in the descending order
3836          *
3837          */
3838         I915_WRITE(WM3_LP_ILK, 0);
3839         I915_WRITE(WM2_LP_ILK, 0);
3840         I915_WRITE(WM1_LP_ILK, 0);
3841
3842         if (enabled != 1)
3843                 return;
3844
3845         clock = planea_clock ? planea_clock : planeb_clock;
3846
3847         /* WM1 */
3848         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3849                                    clock, SNB_READ_WM1_LATENCY() * 500,
3850                                    &sandybridge_display_srwm_info,
3851                                    &sandybridge_cursor_srwm_info,
3852                                    &fbc_wm, &plane_wm, &cursor_wm))
3853                 return;
3854
3855         I915_WRITE(WM1_LP_ILK,
3856                    WM1_LP_SR_EN |
3857                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3858                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3859                    (plane_wm << WM1_LP_SR_SHIFT) |
3860                    cursor_wm);
3861
3862         /* WM2 */
3863         if (!ironlake_compute_srwm(dev, 2,
3864                                    hdisplay, htotal, pixel_size,
3865                                    clock, SNB_READ_WM2_LATENCY() * 500,
3866                                    &sandybridge_display_srwm_info,
3867                                    &sandybridge_cursor_srwm_info,
3868                                    &fbc_wm, &plane_wm, &cursor_wm))
3869                 return;
3870
3871         I915_WRITE(WM2_LP_ILK,
3872                    WM2_LP_EN |
3873                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3874                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3875                    (plane_wm << WM1_LP_SR_SHIFT) |
3876                    cursor_wm);
3877
3878         /* WM3 */
3879         if (!ironlake_compute_srwm(dev, 3,
3880                                    hdisplay, htotal, pixel_size,
3881                                    clock, SNB_READ_WM3_LATENCY() * 500,
3882                                    &sandybridge_display_srwm_info,
3883                                    &sandybridge_cursor_srwm_info,
3884                                    &fbc_wm, &plane_wm, &cursor_wm))
3885                 return;
3886
3887         I915_WRITE(WM3_LP_ILK,
3888                    WM3_LP_EN |
3889                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3890                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3891                    (plane_wm << WM1_LP_SR_SHIFT) |
3892                    cursor_wm);
3893 }
3894
3895 /**
3896  * intel_update_watermarks - update FIFO watermark values based on current modes
3897  *
3898  * Calculate watermark values for the various WM regs based on current mode
3899  * and plane configuration.
3900  *
3901  * There are several cases to deal with here:
3902  *   - normal (i.e. non-self-refresh)
3903  *   - self-refresh (SR) mode
3904  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3905  *   - lines are small relative to FIFO size (buffer can hold more than 2
3906  *     lines), so need to account for TLB latency
3907  *
3908  *   The normal calculation is:
3909  *     watermark = dotclock * bytes per pixel * latency
3910  *   where latency is platform & configuration dependent (we assume pessimal
3911  *   values here).
3912  *
3913  *   The SR calculation is:
3914  *     watermark = (trunc(latency/line time)+1) * surface width *
3915  *       bytes per pixel
3916  *   where
3917  *     line time = htotal / dotclock
3918  *     surface width = hdisplay for normal plane and 64 for cursor
3919  *   and latency is assumed to be high, as above.
3920  *
3921  * The final value programmed to the register should always be rounded up,
3922  * and include an extra 2 entries to account for clock crossings.
3923  *
3924  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3925  * to set the non-SR watermarks to 8.
3926  */
3927 static void intel_update_watermarks(struct drm_device *dev)
3928 {
3929         struct drm_i915_private *dev_priv = dev->dev_private;
3930         struct drm_crtc *crtc;
3931         int sr_hdisplay = 0;
3932         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3933         int enabled = 0, pixel_size = 0;
3934         int sr_htotal = 0;
3935
3936         if (!dev_priv->display.update_wm)
3937                 return;
3938
3939         /* Get the clock config from both planes */
3940         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3941                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942                 if (intel_crtc->active) {
3943                         enabled++;
3944                         if (intel_crtc->plane == 0) {
3945                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3946                                               intel_crtc->pipe, crtc->mode.clock);
3947                                 planea_clock = crtc->mode.clock;
3948                         } else {
3949                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3950                                               intel_crtc->pipe, crtc->mode.clock);
3951                                 planeb_clock = crtc->mode.clock;
3952                         }
3953                         sr_hdisplay = crtc->mode.hdisplay;
3954                         sr_clock = crtc->mode.clock;
3955                         sr_htotal = crtc->mode.htotal;
3956                         if (crtc->fb)
3957                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3958                         else
3959                                 pixel_size = 4; /* by default */
3960                 }
3961         }
3962
3963         if (enabled <= 0)
3964                 return;
3965
3966         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3967                                     sr_hdisplay, sr_htotal, pixel_size);
3968 }
3969
3970 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3971 {
3972         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
3973 }
3974
3975 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3976                                struct drm_display_mode *mode,
3977                                struct drm_display_mode *adjusted_mode,
3978                                int x, int y,
3979                                struct drm_framebuffer *old_fb)
3980 {
3981         struct drm_device *dev = crtc->dev;
3982         struct drm_i915_private *dev_priv = dev->dev_private;
3983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3984         int pipe = intel_crtc->pipe;
3985         int plane = intel_crtc->plane;
3986         u32 fp_reg, dpll_reg;
3987         int refclk, num_connectors = 0;
3988         intel_clock_t clock, reduced_clock;
3989         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3990         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3991         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3992         struct intel_encoder *has_edp_encoder = NULL;
3993         struct drm_mode_config *mode_config = &dev->mode_config;
3994         struct intel_encoder *encoder;
3995         const intel_limit_t *limit;
3996         int ret;
3997         struct fdi_m_n m_n = {0};
3998         u32 reg, temp;
3999         int target_clock;
4000
4001         drm_vblank_pre_modeset(dev, pipe);
4002
4003         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4004                 if (encoder->base.crtc != crtc)
4005                         continue;
4006
4007                 switch (encoder->type) {
4008                 case INTEL_OUTPUT_LVDS:
4009                         is_lvds = true;
4010                         break;
4011                 case INTEL_OUTPUT_SDVO:
4012                 case INTEL_OUTPUT_HDMI:
4013                         is_sdvo = true;
4014                         if (encoder->needs_tv_clock)
4015                                 is_tv = true;
4016                         break;
4017                 case INTEL_OUTPUT_DVO:
4018                         is_dvo = true;
4019                         break;
4020                 case INTEL_OUTPUT_TVOUT:
4021                         is_tv = true;
4022                         break;
4023                 case INTEL_OUTPUT_ANALOG:
4024                         is_crt = true;
4025                         break;
4026                 case INTEL_OUTPUT_DISPLAYPORT:
4027                         is_dp = true;
4028                         break;
4029                 case INTEL_OUTPUT_EDP:
4030                         has_edp_encoder = encoder;
4031                         break;
4032                 }
4033
4034                 num_connectors++;
4035         }
4036
4037         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4038                 refclk = dev_priv->lvds_ssc_freq * 1000;
4039                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4040                               refclk / 1000);
4041         } else if (!IS_GEN2(dev)) {
4042                 refclk = 96000;
4043                 if (HAS_PCH_SPLIT(dev) &&
4044                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4045                         refclk = 120000; /* 120Mhz refclk */
4046         } else {
4047                 refclk = 48000;
4048         }
4049
4050         /*
4051          * Returns a set of divisors for the desired target clock with the given
4052          * refclk, or FALSE.  The returned values represent the clock equation:
4053          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4054          */
4055         limit = intel_limit(crtc, refclk);
4056         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4057         if (!ok) {
4058                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4059                 drm_vblank_post_modeset(dev, pipe);
4060                 return -EINVAL;
4061         }
4062
4063         /* Ensure that the cursor is valid for the new mode before changing... */
4064         intel_crtc_update_cursor(crtc, true);
4065
4066         if (is_lvds && dev_priv->lvds_downclock_avail) {
4067                 has_reduced_clock = limit->find_pll(limit, crtc,
4068                                                     dev_priv->lvds_downclock,
4069                                                     refclk,
4070                                                     &reduced_clock);
4071                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4072                         /*
4073                          * If the different P is found, it means that we can't
4074                          * switch the display clock by using the FP0/FP1.
4075                          * In such case we will disable the LVDS downclock
4076                          * feature.
4077                          */
4078                         DRM_DEBUG_KMS("Different P is found for "
4079                                       "LVDS clock/downclock\n");
4080                         has_reduced_clock = 0;
4081                 }
4082         }
4083         /* SDVO TV has fixed PLL values depend on its clock range,
4084            this mirrors vbios setting. */
4085         if (is_sdvo && is_tv) {
4086                 if (adjusted_mode->clock >= 100000
4087                     && adjusted_mode->clock < 140500) {
4088                         clock.p1 = 2;
4089                         clock.p2 = 10;
4090                         clock.n = 3;
4091                         clock.m1 = 16;
4092                         clock.m2 = 8;
4093                 } else if (adjusted_mode->clock >= 140500
4094                            && adjusted_mode->clock <= 200000) {
4095                         clock.p1 = 1;
4096                         clock.p2 = 10;
4097                         clock.n = 6;
4098                         clock.m1 = 12;
4099                         clock.m2 = 8;
4100                 }
4101         }
4102
4103         /* FDI link */
4104         if (HAS_PCH_SPLIT(dev)) {
4105                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4106                 int lane = 0, link_bw, bpp;
4107                 /* CPU eDP doesn't require FDI link, so just set DP M/N
4108                    according to current link config */
4109                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4110                         target_clock = mode->clock;
4111                         intel_edp_link_config(has_edp_encoder,
4112                                               &lane, &link_bw);
4113                 } else {
4114                         /* [e]DP over FDI requires target mode clock
4115                            instead of link clock */
4116                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4117                                 target_clock = mode->clock;
4118                         else
4119                                 target_clock = adjusted_mode->clock;
4120
4121                         /* FDI is a binary signal running at ~2.7GHz, encoding
4122                          * each output octet as 10 bits. The actual frequency
4123                          * is stored as a divider into a 100MHz clock, and the
4124                          * mode pixel clock is stored in units of 1KHz.
4125                          * Hence the bw of each lane in terms of the mode signal
4126                          * is:
4127                          */
4128                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4129                 }
4130
4131                 /* determine panel color depth */
4132                 temp = I915_READ(PIPECONF(pipe));
4133                 temp &= ~PIPE_BPC_MASK;
4134                 if (is_lvds) {
4135                         /* the BPC will be 6 if it is 18-bit LVDS panel */
4136                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4137                                 temp |= PIPE_8BPC;
4138                         else
4139                                 temp |= PIPE_6BPC;
4140                 } else if (has_edp_encoder) {
4141                         switch (dev_priv->edp.bpp/3) {
4142                         case 8:
4143                                 temp |= PIPE_8BPC;
4144                                 break;
4145                         case 10:
4146                                 temp |= PIPE_10BPC;
4147                                 break;
4148                         case 6:
4149                                 temp |= PIPE_6BPC;
4150                                 break;
4151                         case 12:
4152                                 temp |= PIPE_12BPC;
4153                                 break;
4154                         }
4155                 } else
4156                         temp |= PIPE_8BPC;
4157                 I915_WRITE(PIPECONF(pipe), temp);
4158
4159                 switch (temp & PIPE_BPC_MASK) {
4160                 case PIPE_8BPC:
4161                         bpp = 24;
4162                         break;
4163                 case PIPE_10BPC:
4164                         bpp = 30;
4165                         break;
4166                 case PIPE_6BPC:
4167                         bpp = 18;
4168                         break;
4169                 case PIPE_12BPC:
4170                         bpp = 36;
4171                         break;
4172                 default:
4173                         DRM_ERROR("unknown pipe bpc value\n");
4174                         bpp = 24;
4175                 }
4176
4177                 if (!lane) {
4178                         /*
4179                          * Account for spread spectrum to avoid
4180                          * oversubscribing the link. Max center spread
4181                          * is 2.5%; use 5% for safety's sake.
4182                          */
4183                         u32 bps = target_clock * bpp * 21 / 20;
4184                         lane = bps / (link_bw * 8) + 1;
4185                 }
4186
4187                 intel_crtc->fdi_lanes = lane;
4188
4189                 if (pixel_multiplier > 1)
4190                         link_bw *= pixel_multiplier;
4191                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4192         }
4193
4194         /* Ironlake: try to setup display ref clock before DPLL
4195          * enabling. This is only under driver's control after
4196          * PCH B stepping, previous chipset stepping should be
4197          * ignoring this setting.
4198          */
4199         if (HAS_PCH_SPLIT(dev)) {
4200                 temp = I915_READ(PCH_DREF_CONTROL);
4201                 /* Always enable nonspread source */
4202                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4203                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4204                 temp &= ~DREF_SSC_SOURCE_MASK;
4205                 temp |= DREF_SSC_SOURCE_ENABLE;
4206                 I915_WRITE(PCH_DREF_CONTROL, temp);
4207
4208                 POSTING_READ(PCH_DREF_CONTROL);
4209                 udelay(200);
4210
4211                 if (has_edp_encoder) {
4212                         if (intel_panel_use_ssc(dev_priv)) {
4213                                 temp |= DREF_SSC1_ENABLE;
4214                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4215
4216                                 POSTING_READ(PCH_DREF_CONTROL);
4217                                 udelay(200);
4218                         }
4219                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4220
4221                         /* Enable CPU source on CPU attached eDP */
4222                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4223                                 if (intel_panel_use_ssc(dev_priv))
4224                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4225                                 else
4226                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4227                         } else {
4228                                 /* Enable SSC on PCH eDP if needed */
4229                                 if (intel_panel_use_ssc(dev_priv)) {
4230                                         DRM_ERROR("enabling SSC on PCH\n");
4231                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4232                                 }
4233                         }
4234                         I915_WRITE(PCH_DREF_CONTROL, temp);
4235                         POSTING_READ(PCH_DREF_CONTROL);
4236                         udelay(200);
4237                 }
4238         }
4239
4240         if (IS_PINEVIEW(dev)) {
4241                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4242                 if (has_reduced_clock)
4243                         fp2 = (1 << reduced_clock.n) << 16 |
4244                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4245         } else {
4246                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4247                 if (has_reduced_clock)
4248                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4249                                 reduced_clock.m2;
4250         }
4251
4252         /* Enable autotuning of the PLL clock (if permissible) */
4253         if (HAS_PCH_SPLIT(dev)) {
4254                 int factor = 21;
4255
4256                 if (is_lvds) {
4257                         if ((intel_panel_use_ssc(dev_priv) &&
4258                              dev_priv->lvds_ssc_freq == 100) ||
4259                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4260                                 factor = 25;
4261                 } else if (is_sdvo && is_tv)
4262                         factor = 20;
4263
4264                 if (clock.m1 < factor * clock.n)
4265                         fp |= FP_CB_TUNE;
4266         }
4267
4268         dpll = 0;
4269         if (!HAS_PCH_SPLIT(dev))
4270                 dpll = DPLL_VGA_MODE_DIS;
4271
4272         if (!IS_GEN2(dev)) {
4273                 if (is_lvds)
4274                         dpll |= DPLLB_MODE_LVDS;
4275                 else
4276                         dpll |= DPLLB_MODE_DAC_SERIAL;
4277                 if (is_sdvo) {
4278                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4279                         if (pixel_multiplier > 1) {
4280                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4281                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4282                                 else if (HAS_PCH_SPLIT(dev))
4283                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4284                         }
4285                         dpll |= DPLL_DVO_HIGH_SPEED;
4286                 }
4287                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4288                         dpll |= DPLL_DVO_HIGH_SPEED;
4289
4290                 /* compute bitmask from p1 value */
4291                 if (IS_PINEVIEW(dev))
4292                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4293                 else {
4294                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4295                         /* also FPA1 */
4296                         if (HAS_PCH_SPLIT(dev))
4297                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4298                         if (IS_G4X(dev) && has_reduced_clock)
4299                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4300                 }
4301                 switch (clock.p2) {
4302                 case 5:
4303                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4304                         break;
4305                 case 7:
4306                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4307                         break;
4308                 case 10:
4309                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4310                         break;
4311                 case 14:
4312                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4313                         break;
4314                 }
4315                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4316                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4317         } else {
4318                 if (is_lvds) {
4319                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4320                 } else {
4321                         if (clock.p1 == 2)
4322                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4323                         else
4324                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4325                         if (clock.p2 == 4)
4326                                 dpll |= PLL_P2_DIVIDE_BY_4;
4327                 }
4328         }
4329
4330         if (is_sdvo && is_tv)
4331                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4332         else if (is_tv)
4333                 /* XXX: just matching BIOS for now */
4334                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4335                 dpll |= 3;
4336         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4337                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4338         else
4339                 dpll |= PLL_REF_INPUT_DREFCLK;
4340
4341         /* setup pipeconf */
4342         pipeconf = I915_READ(PIPECONF(pipe));
4343
4344         /* Set up the display plane register */
4345         dspcntr = DISPPLANE_GAMMA_ENABLE;
4346
4347         /* Ironlake's plane is forced to pipe, bit 24 is to
4348            enable color space conversion */
4349         if (!HAS_PCH_SPLIT(dev)) {
4350                 if (pipe == 0)
4351                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4352                 else
4353                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4354         }
4355
4356         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4357                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4358                  * core speed.
4359                  *
4360                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4361                  * pipe == 0 check?
4362                  */
4363                 if (mode->clock >
4364                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4365                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4366                 else
4367                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4368         }
4369
4370         dspcntr |= DISPLAY_PLANE_ENABLE;
4371         pipeconf |= PIPECONF_ENABLE;
4372         dpll |= DPLL_VCO_ENABLE;
4373
4374         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4375         drm_mode_debug_printmodeline(mode);
4376
4377         /* assign to Ironlake registers */
4378         if (HAS_PCH_SPLIT(dev)) {
4379                 fp_reg = PCH_FP0(pipe);
4380                 dpll_reg = PCH_DPLL(pipe);
4381         } else {
4382                 fp_reg = FP0(pipe);
4383                 dpll_reg = DPLL(pipe);
4384         }
4385
4386         /* PCH eDP needs FDI, but CPU eDP does not */
4387         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4388                 I915_WRITE(fp_reg, fp);
4389                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4390
4391                 POSTING_READ(dpll_reg);
4392                 udelay(150);
4393         }
4394
4395         /* enable transcoder DPLL */
4396         if (HAS_PCH_CPT(dev)) {
4397                 temp = I915_READ(PCH_DPLL_SEL);
4398                 if (pipe == 0)
4399                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4400                 else
4401                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4402                 I915_WRITE(PCH_DPLL_SEL, temp);
4403
4404                 POSTING_READ(PCH_DPLL_SEL);
4405                 udelay(150);
4406         }
4407
4408         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4409          * This is an exception to the general rule that mode_set doesn't turn
4410          * things on.
4411          */
4412         if (is_lvds) {
4413                 reg = LVDS;
4414                 if (HAS_PCH_SPLIT(dev))
4415                         reg = PCH_LVDS;
4416
4417                 temp = I915_READ(reg);
4418                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4419                 if (pipe == 1) {
4420                         if (HAS_PCH_CPT(dev))
4421                                 temp |= PORT_TRANS_B_SEL_CPT;
4422                         else
4423                                 temp |= LVDS_PIPEB_SELECT;
4424                 } else {
4425                         if (HAS_PCH_CPT(dev))
4426                                 temp &= ~PORT_TRANS_SEL_MASK;
4427                         else
4428                                 temp &= ~LVDS_PIPEB_SELECT;
4429                 }
4430                 /* set the corresponsding LVDS_BORDER bit */
4431                 temp |= dev_priv->lvds_border_bits;
4432                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4433                  * set the DPLLs for dual-channel mode or not.
4434                  */
4435                 if (clock.p2 == 7)
4436                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4437                 else
4438                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4439
4440                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4441                  * appropriately here, but we need to look more thoroughly into how
4442                  * panels behave in the two modes.
4443                  */
4444                 /* set the dithering flag on non-PCH LVDS as needed */
4445                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4446                         if (dev_priv->lvds_dither)
4447                                 temp |= LVDS_ENABLE_DITHER;
4448                         else
4449                                 temp &= ~LVDS_ENABLE_DITHER;
4450                 }
4451                 I915_WRITE(reg, temp);
4452         }
4453
4454         /* set the dithering flag and clear for anything other than a panel. */
4455         if (HAS_PCH_SPLIT(dev)) {
4456                 pipeconf &= ~PIPECONF_DITHER_EN;
4457                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4458                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4459                         pipeconf |= PIPECONF_DITHER_EN;
4460                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4461                 }
4462         }
4463
4464         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4465                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4466         } else if (HAS_PCH_SPLIT(dev)) {
4467                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4468                 if (pipe == 0) {
4469                         I915_WRITE(TRANSA_DATA_M1, 0);
4470                         I915_WRITE(TRANSA_DATA_N1, 0);
4471                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4472                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4473                 } else {
4474                         I915_WRITE(TRANSB_DATA_M1, 0);
4475                         I915_WRITE(TRANSB_DATA_N1, 0);
4476                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4477                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4478                 }
4479         }
4480
4481         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4482                 I915_WRITE(dpll_reg, dpll);
4483
4484                 /* Wait for the clocks to stabilize. */
4485                 POSTING_READ(dpll_reg);
4486                 udelay(150);
4487
4488                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4489                         temp = 0;
4490                         if (is_sdvo) {
4491                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4492                                 if (temp > 1)
4493                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4494                                 else
4495                                         temp = 0;
4496                         }
4497                         I915_WRITE(DPLL_MD(pipe), temp);
4498                 } else {
4499                         /* The pixel multiplier can only be updated once the
4500                          * DPLL is enabled and the clocks are stable.
4501                          *
4502                          * So write it again.
4503                          */
4504                         I915_WRITE(dpll_reg, dpll);
4505                 }
4506         }
4507
4508         intel_crtc->lowfreq_avail = false;
4509         if (is_lvds && has_reduced_clock && i915_powersave) {
4510                 I915_WRITE(fp_reg + 4, fp2);
4511                 intel_crtc->lowfreq_avail = true;
4512                 if (HAS_PIPE_CXSR(dev)) {
4513                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4514                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4515                 }
4516         } else {
4517                 I915_WRITE(fp_reg + 4, fp);
4518                 if (HAS_PIPE_CXSR(dev)) {
4519                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4520                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4521                 }
4522         }
4523
4524         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4525                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4526                 /* the chip adds 2 halflines automatically */
4527                 adjusted_mode->crtc_vdisplay -= 1;
4528                 adjusted_mode->crtc_vtotal -= 1;
4529                 adjusted_mode->crtc_vblank_start -= 1;
4530                 adjusted_mode->crtc_vblank_end -= 1;
4531                 adjusted_mode->crtc_vsync_end -= 1;
4532                 adjusted_mode->crtc_vsync_start -= 1;
4533         } else
4534                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4535
4536         I915_WRITE(HTOTAL(pipe),
4537                    (adjusted_mode->crtc_hdisplay - 1) |
4538                    ((adjusted_mode->crtc_htotal - 1) << 16));
4539         I915_WRITE(HBLANK(pipe),
4540                    (adjusted_mode->crtc_hblank_start - 1) |
4541                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4542         I915_WRITE(HSYNC(pipe),
4543                    (adjusted_mode->crtc_hsync_start - 1) |
4544                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4545
4546         I915_WRITE(VTOTAL(pipe),
4547                    (adjusted_mode->crtc_vdisplay - 1) |
4548                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4549         I915_WRITE(VBLANK(pipe),
4550                    (adjusted_mode->crtc_vblank_start - 1) |
4551                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4552         I915_WRITE(VSYNC(pipe),
4553                    (adjusted_mode->crtc_vsync_start - 1) |
4554                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4555
4556         /* pipesrc and dspsize control the size that is scaled from,
4557          * which should always be the user's requested size.
4558          */
4559         if (!HAS_PCH_SPLIT(dev)) {
4560                 I915_WRITE(DSPSIZE(plane),
4561                            ((mode->vdisplay - 1) << 16) |
4562                            (mode->hdisplay - 1));
4563                 I915_WRITE(DSPPOS(plane), 0);
4564         }
4565         I915_WRITE(PIPESRC(pipe),
4566                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4567
4568         if (HAS_PCH_SPLIT(dev)) {
4569                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4570                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4571                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4572                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4573
4574                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4575                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4576                 }
4577         }
4578
4579         I915_WRITE(PIPECONF(pipe), pipeconf);
4580         POSTING_READ(PIPECONF(pipe));
4581
4582         intel_wait_for_vblank(dev, pipe);
4583
4584         if (IS_GEN5(dev)) {
4585                 /* enable address swizzle for tiling buffer */
4586                 temp = I915_READ(DISP_ARB_CTL);
4587                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4588         }
4589
4590         I915_WRITE(DSPCNTR(plane), dspcntr);
4591
4592         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4593
4594         intel_update_watermarks(dev);
4595
4596         drm_vblank_post_modeset(dev, pipe);
4597
4598         return ret;
4599 }
4600
4601 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4602 void intel_crtc_load_lut(struct drm_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->dev;
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4607         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4608         int i;
4609
4610         /* The clocks have to be on to load the palette. */
4611         if (!crtc->enabled)
4612                 return;
4613
4614         /* use legacy palette for Ironlake */
4615         if (HAS_PCH_SPLIT(dev))
4616                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4617                                                    LGC_PALETTE_B;
4618
4619         for (i = 0; i < 256; i++) {
4620                 I915_WRITE(palreg + 4 * i,
4621                            (intel_crtc->lut_r[i] << 16) |
4622                            (intel_crtc->lut_g[i] << 8) |
4623                            intel_crtc->lut_b[i]);
4624         }
4625 }
4626
4627 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4628 {
4629         struct drm_device *dev = crtc->dev;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632         bool visible = base != 0;
4633         u32 cntl;
4634
4635         if (intel_crtc->cursor_visible == visible)
4636                 return;
4637
4638         cntl = I915_READ(CURACNTR);
4639         if (visible) {
4640                 /* On these chipsets we can only modify the base whilst
4641                  * the cursor is disabled.
4642                  */
4643                 I915_WRITE(CURABASE, base);
4644
4645                 cntl &= ~(CURSOR_FORMAT_MASK);
4646                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4647                 cntl |= CURSOR_ENABLE |
4648                         CURSOR_GAMMA_ENABLE |
4649                         CURSOR_FORMAT_ARGB;
4650         } else
4651                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4652         I915_WRITE(CURACNTR, cntl);
4653
4654         intel_crtc->cursor_visible = visible;
4655 }
4656
4657 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4658 {
4659         struct drm_device *dev = crtc->dev;
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662         int pipe = intel_crtc->pipe;
4663         bool visible = base != 0;
4664
4665         if (intel_crtc->cursor_visible != visible) {
4666                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4667                 if (base) {
4668                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4669                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4670                         cntl |= pipe << 28; /* Connect to correct pipe */
4671                 } else {
4672                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4673                         cntl |= CURSOR_MODE_DISABLE;
4674                 }
4675                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4676
4677                 intel_crtc->cursor_visible = visible;
4678         }
4679         /* and commit changes on next vblank */
4680         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4681 }
4682
4683 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4684 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4685                                      bool on)
4686 {
4687         struct drm_device *dev = crtc->dev;
4688         struct drm_i915_private *dev_priv = dev->dev_private;
4689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4690         int pipe = intel_crtc->pipe;
4691         int x = intel_crtc->cursor_x;
4692         int y = intel_crtc->cursor_y;
4693         u32 base, pos;
4694         bool visible;
4695
4696         pos = 0;
4697
4698         if (on && crtc->enabled && crtc->fb) {
4699                 base = intel_crtc->cursor_addr;
4700                 if (x > (int) crtc->fb->width)
4701                         base = 0;
4702
4703                 if (y > (int) crtc->fb->height)
4704                         base = 0;
4705         } else
4706                 base = 0;
4707
4708         if (x < 0) {
4709                 if (x + intel_crtc->cursor_width < 0)
4710                         base = 0;
4711
4712                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4713                 x = -x;
4714         }
4715         pos |= x << CURSOR_X_SHIFT;
4716
4717         if (y < 0) {
4718                 if (y + intel_crtc->cursor_height < 0)
4719                         base = 0;
4720
4721                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4722                 y = -y;
4723         }
4724         pos |= y << CURSOR_Y_SHIFT;
4725
4726         visible = base != 0;
4727         if (!visible && !intel_crtc->cursor_visible)
4728                 return;
4729
4730         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4731         if (IS_845G(dev) || IS_I865G(dev))
4732                 i845_update_cursor(crtc, base);
4733         else
4734                 i9xx_update_cursor(crtc, base);
4735
4736         if (visible)
4737                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4738 }
4739
4740 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4741                                  struct drm_file *file,
4742                                  uint32_t handle,
4743                                  uint32_t width, uint32_t height)
4744 {
4745         struct drm_device *dev = crtc->dev;
4746         struct drm_i915_private *dev_priv = dev->dev_private;
4747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4748         struct drm_i915_gem_object *obj;
4749         uint32_t addr;
4750         int ret;
4751
4752         DRM_DEBUG_KMS("\n");
4753
4754         /* if we want to turn off the cursor ignore width and height */
4755         if (!handle) {
4756                 DRM_DEBUG_KMS("cursor off\n");
4757                 addr = 0;
4758                 obj = NULL;
4759                 mutex_lock(&dev->struct_mutex);
4760                 goto finish;
4761         }
4762
4763         /* Currently we only support 64x64 cursors */
4764         if (width != 64 || height != 64) {
4765                 DRM_ERROR("we currently only support 64x64 cursors\n");
4766                 return -EINVAL;
4767         }
4768
4769         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4770         if (!obj)
4771                 return -ENOENT;
4772
4773         if (obj->base.size < width * height * 4) {
4774                 DRM_ERROR("buffer is to small\n");
4775                 ret = -ENOMEM;
4776                 goto fail;
4777         }
4778
4779         /* we only need to pin inside GTT if cursor is non-phy */
4780         mutex_lock(&dev->struct_mutex);
4781         if (!dev_priv->info->cursor_needs_physical) {
4782                 if (obj->tiling_mode) {
4783                         DRM_ERROR("cursor cannot be tiled\n");
4784                         ret = -EINVAL;
4785                         goto fail_locked;
4786                 }
4787
4788                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4789                 if (ret) {
4790                         DRM_ERROR("failed to pin cursor bo\n");
4791                         goto fail_locked;
4792                 }
4793
4794                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4795                 if (ret) {
4796                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4797                         goto fail_unpin;
4798                 }
4799
4800                 ret = i915_gem_object_put_fence(obj);
4801                 if (ret) {
4802                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4803                         goto fail_unpin;
4804                 }
4805
4806                 addr = obj->gtt_offset;
4807         } else {
4808                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4809                 ret = i915_gem_attach_phys_object(dev, obj,
4810                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4811                                                   align);
4812                 if (ret) {
4813                         DRM_ERROR("failed to attach phys object\n");
4814                         goto fail_locked;
4815                 }
4816                 addr = obj->phys_obj->handle->busaddr;
4817         }
4818
4819         if (IS_GEN2(dev))
4820                 I915_WRITE(CURSIZE, (height << 12) | width);
4821
4822  finish:
4823         if (intel_crtc->cursor_bo) {
4824                 if (dev_priv->info->cursor_needs_physical) {
4825                         if (intel_crtc->cursor_bo != obj)
4826                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4827                 } else
4828                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4829                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4830         }
4831
4832         mutex_unlock(&dev->struct_mutex);
4833
4834         intel_crtc->cursor_addr = addr;
4835         intel_crtc->cursor_bo = obj;
4836         intel_crtc->cursor_width = width;
4837         intel_crtc->cursor_height = height;
4838
4839         intel_crtc_update_cursor(crtc, true);
4840
4841         return 0;
4842 fail_unpin:
4843         i915_gem_object_unpin(obj);
4844 fail_locked:
4845         mutex_unlock(&dev->struct_mutex);
4846 fail:
4847         drm_gem_object_unreference_unlocked(&obj->base);
4848         return ret;
4849 }
4850
4851 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4852 {
4853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854
4855         intel_crtc->cursor_x = x;
4856         intel_crtc->cursor_y = y;
4857
4858         intel_crtc_update_cursor(crtc, true);
4859
4860         return 0;
4861 }
4862
4863 /** Sets the color ramps on behalf of RandR */
4864 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4865                                  u16 blue, int regno)
4866 {
4867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4868
4869         intel_crtc->lut_r[regno] = red >> 8;
4870         intel_crtc->lut_g[regno] = green >> 8;
4871         intel_crtc->lut_b[regno] = blue >> 8;
4872 }
4873
4874 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4875                              u16 *blue, int regno)
4876 {
4877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878
4879         *red = intel_crtc->lut_r[regno] << 8;
4880         *green = intel_crtc->lut_g[regno] << 8;
4881         *blue = intel_crtc->lut_b[regno] << 8;
4882 }
4883
4884 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4885                                  u16 *blue, uint32_t start, uint32_t size)
4886 {
4887         int end = (start + size > 256) ? 256 : start + size, i;
4888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4889
4890         for (i = start; i < end; i++) {
4891                 intel_crtc->lut_r[i] = red[i] >> 8;
4892                 intel_crtc->lut_g[i] = green[i] >> 8;
4893                 intel_crtc->lut_b[i] = blue[i] >> 8;
4894         }
4895
4896         intel_crtc_load_lut(crtc);
4897 }
4898
4899 /**
4900  * Get a pipe with a simple mode set on it for doing load-based monitor
4901  * detection.
4902  *
4903  * It will be up to the load-detect code to adjust the pipe as appropriate for
4904  * its requirements.  The pipe will be connected to no other encoders.
4905  *
4906  * Currently this code will only succeed if there is a pipe with no encoders
4907  * configured for it.  In the future, it could choose to temporarily disable
4908  * some outputs to free up a pipe for its use.
4909  *
4910  * \return crtc, or NULL if no pipes are available.
4911  */
4912
4913 /* VESA 640x480x72Hz mode to set on the pipe */
4914 static struct drm_display_mode load_detect_mode = {
4915         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4916                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4917 };
4918
4919 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4920                                             struct drm_connector *connector,
4921                                             struct drm_display_mode *mode,
4922                                             int *dpms_mode)
4923 {
4924         struct intel_crtc *intel_crtc;
4925         struct drm_crtc *possible_crtc;
4926         struct drm_crtc *supported_crtc =NULL;
4927         struct drm_encoder *encoder = &intel_encoder->base;
4928         struct drm_crtc *crtc = NULL;
4929         struct drm_device *dev = encoder->dev;
4930         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4931         struct drm_crtc_helper_funcs *crtc_funcs;
4932         int i = -1;
4933
4934         /*
4935          * Algorithm gets a little messy:
4936          *   - if the connector already has an assigned crtc, use it (but make
4937          *     sure it's on first)
4938          *   - try to find the first unused crtc that can drive this connector,
4939          *     and use that if we find one
4940          *   - if there are no unused crtcs available, try to use the first
4941          *     one we found that supports the connector
4942          */
4943
4944         /* See if we already have a CRTC for this connector */
4945         if (encoder->crtc) {
4946                 crtc = encoder->crtc;
4947                 /* Make sure the crtc and connector are running */
4948                 intel_crtc = to_intel_crtc(crtc);
4949                 *dpms_mode = intel_crtc->dpms_mode;
4950                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4951                         crtc_funcs = crtc->helper_private;
4952                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4953                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4954                 }
4955                 return crtc;
4956         }
4957
4958         /* Find an unused one (if possible) */
4959         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4960                 i++;
4961                 if (!(encoder->possible_crtcs & (1 << i)))
4962                         continue;
4963                 if (!possible_crtc->enabled) {
4964                         crtc = possible_crtc;
4965                         break;
4966                 }
4967                 if (!supported_crtc)
4968                         supported_crtc = possible_crtc;
4969         }
4970
4971         /*
4972          * If we didn't find an unused CRTC, don't use any.
4973          */
4974         if (!crtc) {
4975                 return NULL;
4976         }
4977
4978         encoder->crtc = crtc;
4979         connector->encoder = encoder;
4980         intel_encoder->load_detect_temp = true;
4981
4982         intel_crtc = to_intel_crtc(crtc);
4983         *dpms_mode = intel_crtc->dpms_mode;
4984
4985         if (!crtc->enabled) {
4986                 if (!mode)
4987                         mode = &load_detect_mode;
4988                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4989         } else {
4990                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4991                         crtc_funcs = crtc->helper_private;
4992                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4993                 }
4994
4995                 /* Add this connector to the crtc */
4996                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4997                 encoder_funcs->commit(encoder);
4998         }
4999         /* let the connector get through one full cycle before testing */
5000         intel_wait_for_vblank(dev, intel_crtc->pipe);
5001
5002         return crtc;
5003 }
5004
5005 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5006                                     struct drm_connector *connector, int dpms_mode)
5007 {
5008         struct drm_encoder *encoder = &intel_encoder->base;
5009         struct drm_device *dev = encoder->dev;
5010         struct drm_crtc *crtc = encoder->crtc;
5011         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5012         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5013
5014         if (intel_encoder->load_detect_temp) {
5015                 encoder->crtc = NULL;
5016                 connector->encoder = NULL;
5017                 intel_encoder->load_detect_temp = false;
5018                 crtc->enabled = drm_helper_crtc_in_use(crtc);
5019                 drm_helper_disable_unused_functions(dev);
5020         }
5021
5022         /* Switch crtc and encoder back off if necessary */
5023         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5024                 if (encoder->crtc == crtc)
5025                         encoder_funcs->dpms(encoder, dpms_mode);
5026                 crtc_funcs->dpms(crtc, dpms_mode);
5027         }
5028 }
5029
5030 /* Returns the clock of the currently programmed mode of the given pipe. */
5031 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5032 {
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5035         int pipe = intel_crtc->pipe;
5036         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
5037         u32 fp;
5038         intel_clock_t clock;
5039
5040         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5041                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
5042         else
5043                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
5044
5045         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5046         if (IS_PINEVIEW(dev)) {
5047                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5048                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5049         } else {
5050                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5051                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5052         }
5053
5054         if (!IS_GEN2(dev)) {
5055                 if (IS_PINEVIEW(dev))
5056                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5057                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5058                 else
5059                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5060                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5061
5062                 switch (dpll & DPLL_MODE_MASK) {
5063                 case DPLLB_MODE_DAC_SERIAL:
5064                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5065                                 5 : 10;
5066                         break;
5067                 case DPLLB_MODE_LVDS:
5068                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5069                                 7 : 14;
5070                         break;
5071                 default:
5072                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5073                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5074                         return 0;
5075                 }
5076
5077                 /* XXX: Handle the 100Mhz refclk */
5078                 intel_clock(dev, 96000, &clock);
5079         } else {
5080                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5081
5082                 if (is_lvds) {
5083                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5084                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5085                         clock.p2 = 14;
5086
5087                         if ((dpll & PLL_REF_INPUT_MASK) ==
5088                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5089                                 /* XXX: might not be 66MHz */
5090                                 intel_clock(dev, 66000, &clock);
5091                         } else
5092                                 intel_clock(dev, 48000, &clock);
5093                 } else {
5094                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5095                                 clock.p1 = 2;
5096                         else {
5097                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5098                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5099                         }
5100                         if (dpll & PLL_P2_DIVIDE_BY_4)
5101                                 clock.p2 = 4;
5102                         else
5103                                 clock.p2 = 2;
5104
5105                         intel_clock(dev, 48000, &clock);
5106                 }
5107         }
5108
5109         /* XXX: It would be nice to validate the clocks, but we can't reuse
5110          * i830PllIsValid() because it relies on the xf86_config connector
5111          * configuration being accurate, which it isn't necessarily.
5112          */
5113
5114         return clock.dot;
5115 }
5116
5117 /** Returns the currently programmed mode of the given pipe. */
5118 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5119                                              struct drm_crtc *crtc)
5120 {
5121         struct drm_i915_private *dev_priv = dev->dev_private;
5122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5123         int pipe = intel_crtc->pipe;
5124         struct drm_display_mode *mode;
5125         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5126         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5127         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5128         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5129
5130         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5131         if (!mode)
5132                 return NULL;
5133
5134         mode->clock = intel_crtc_clock_get(dev, crtc);
5135         mode->hdisplay = (htot & 0xffff) + 1;
5136         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5137         mode->hsync_start = (hsync & 0xffff) + 1;
5138         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5139         mode->vdisplay = (vtot & 0xffff) + 1;
5140         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5141         mode->vsync_start = (vsync & 0xffff) + 1;
5142         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5143
5144         drm_mode_set_name(mode);
5145         drm_mode_set_crtcinfo(mode, 0);
5146
5147         return mode;
5148 }
5149
5150 #define GPU_IDLE_TIMEOUT 500 /* ms */
5151
5152 /* When this timer fires, we've been idle for awhile */
5153 static void intel_gpu_idle_timer(unsigned long arg)
5154 {
5155         struct drm_device *dev = (struct drm_device *)arg;
5156         drm_i915_private_t *dev_priv = dev->dev_private;
5157
5158         if (!list_empty(&dev_priv->mm.active_list)) {
5159                 /* Still processing requests, so just re-arm the timer. */
5160                 mod_timer(&dev_priv->idle_timer, jiffies +
5161                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5162                 return;
5163         }
5164
5165         dev_priv->busy = false;
5166         queue_work(dev_priv->wq, &dev_priv->idle_work);
5167 }
5168
5169 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5170
5171 static void intel_crtc_idle_timer(unsigned long arg)
5172 {
5173         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5174         struct drm_crtc *crtc = &intel_crtc->base;
5175         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5176         struct intel_framebuffer *intel_fb;
5177
5178         intel_fb = to_intel_framebuffer(crtc->fb);
5179         if (intel_fb && intel_fb->obj->active) {
5180                 /* The framebuffer is still being accessed by the GPU. */
5181                 mod_timer(&intel_crtc->idle_timer, jiffies +
5182                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5183                 return;
5184         }
5185
5186         intel_crtc->busy = false;
5187         queue_work(dev_priv->wq, &dev_priv->idle_work);
5188 }
5189
5190 static void intel_increase_pllclock(struct drm_crtc *crtc)
5191 {
5192         struct drm_device *dev = crtc->dev;
5193         drm_i915_private_t *dev_priv = dev->dev_private;
5194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5195         int pipe = intel_crtc->pipe;
5196         int dpll_reg = DPLL(pipe);
5197         int dpll;
5198
5199         if (HAS_PCH_SPLIT(dev))
5200                 return;
5201
5202         if (!dev_priv->lvds_downclock_avail)
5203                 return;
5204
5205         dpll = I915_READ(dpll_reg);
5206         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5207                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5208
5209                 /* Unlock panel regs */
5210                 I915_WRITE(PP_CONTROL,
5211                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5212
5213                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5214                 I915_WRITE(dpll_reg, dpll);
5215                 POSTING_READ(dpll_reg);
5216                 intel_wait_for_vblank(dev, pipe);
5217
5218                 dpll = I915_READ(dpll_reg);
5219                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5220                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5221
5222                 /* ...and lock them again */
5223                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5224         }
5225
5226         /* Schedule downclock */
5227         mod_timer(&intel_crtc->idle_timer, jiffies +
5228                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5229 }
5230
5231 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5232 {
5233         struct drm_device *dev = crtc->dev;
5234         drm_i915_private_t *dev_priv = dev->dev_private;
5235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236         int pipe = intel_crtc->pipe;
5237         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5238         int dpll = I915_READ(dpll_reg);
5239
5240         if (HAS_PCH_SPLIT(dev))
5241                 return;
5242
5243         if (!dev_priv->lvds_downclock_avail)
5244                 return;
5245
5246         /*
5247          * Since this is called by a timer, we should never get here in
5248          * the manual case.
5249          */
5250         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5251                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5252
5253                 /* Unlock panel regs */
5254                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5255                            PANEL_UNLOCK_REGS);
5256
5257                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5258                 I915_WRITE(dpll_reg, dpll);
5259                 dpll = I915_READ(dpll_reg);
5260                 intel_wait_for_vblank(dev, pipe);
5261                 dpll = I915_READ(dpll_reg);
5262                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5263                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5264
5265                 /* ...and lock them again */
5266                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5267         }
5268
5269 }
5270
5271 /**
5272  * intel_idle_update - adjust clocks for idleness
5273  * @work: work struct
5274  *
5275  * Either the GPU or display (or both) went idle.  Check the busy status
5276  * here and adjust the CRTC and GPU clocks as necessary.
5277  */
5278 static void intel_idle_update(struct work_struct *work)
5279 {
5280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5281                                                     idle_work);
5282         struct drm_device *dev = dev_priv->dev;
5283         struct drm_crtc *crtc;
5284         struct intel_crtc *intel_crtc;
5285         int enabled = 0;
5286
5287         if (!i915_powersave)
5288                 return;
5289
5290         mutex_lock(&dev->struct_mutex);
5291
5292         i915_update_gfx_val(dev_priv);
5293
5294         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5295                 /* Skip inactive CRTCs */
5296                 if (!crtc->fb)
5297                         continue;
5298
5299                 enabled++;
5300                 intel_crtc = to_intel_crtc(crtc);
5301                 if (!intel_crtc->busy)
5302                         intel_decrease_pllclock(crtc);
5303         }
5304
5305         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5306                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5307                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5308         }
5309
5310         mutex_unlock(&dev->struct_mutex);
5311 }
5312
5313 /**
5314  * intel_mark_busy - mark the GPU and possibly the display busy
5315  * @dev: drm device
5316  * @obj: object we're operating on
5317  *
5318  * Callers can use this function to indicate that the GPU is busy processing
5319  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5320  * buffer), we'll also mark the display as busy, so we know to increase its
5321  * clock frequency.
5322  */
5323 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5324 {
5325         drm_i915_private_t *dev_priv = dev->dev_private;
5326         struct drm_crtc *crtc = NULL;
5327         struct intel_framebuffer *intel_fb;
5328         struct intel_crtc *intel_crtc;
5329
5330         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5331                 return;
5332
5333         if (!dev_priv->busy) {
5334                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5335                         u32 fw_blc_self;
5336
5337                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5338                         fw_blc_self = I915_READ(FW_BLC_SELF);
5339                         fw_blc_self &= ~FW_BLC_SELF_EN;
5340                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5341                 }
5342                 dev_priv->busy = true;
5343         } else
5344                 mod_timer(&dev_priv->idle_timer, jiffies +
5345                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5346
5347         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5348                 if (!crtc->fb)
5349                         continue;
5350
5351                 intel_crtc = to_intel_crtc(crtc);
5352                 intel_fb = to_intel_framebuffer(crtc->fb);
5353                 if (intel_fb->obj == obj) {
5354                         if (!intel_crtc->busy) {
5355                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5356                                         u32 fw_blc_self;
5357
5358                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5359                                         fw_blc_self = I915_READ(FW_BLC_SELF);
5360                                         fw_blc_self &= ~FW_BLC_SELF_EN;
5361                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5362                                 }
5363                                 /* Non-busy -> busy, upclock */
5364                                 intel_increase_pllclock(crtc);
5365                                 intel_crtc->busy = true;
5366                         } else {
5367                                 /* Busy -> busy, put off timer */
5368                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5369                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5370                         }
5371                 }
5372         }
5373 }
5374
5375 static void intel_crtc_destroy(struct drm_crtc *crtc)
5376 {
5377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378         struct drm_device *dev = crtc->dev;
5379         struct intel_unpin_work *work;
5380         unsigned long flags;
5381
5382         spin_lock_irqsave(&dev->event_lock, flags);
5383         work = intel_crtc->unpin_work;
5384         intel_crtc->unpin_work = NULL;
5385         spin_unlock_irqrestore(&dev->event_lock, flags);
5386
5387         if (work) {
5388                 cancel_work_sync(&work->work);
5389                 kfree(work);
5390         }
5391
5392         drm_crtc_cleanup(crtc);
5393
5394         kfree(intel_crtc);
5395 }
5396
5397 static void intel_unpin_work_fn(struct work_struct *__work)
5398 {
5399         struct intel_unpin_work *work =
5400                 container_of(__work, struct intel_unpin_work, work);
5401
5402         mutex_lock(&work->dev->struct_mutex);
5403         i915_gem_object_unpin(work->old_fb_obj);
5404         drm_gem_object_unreference(&work->pending_flip_obj->base);
5405         drm_gem_object_unreference(&work->old_fb_obj->base);
5406
5407         mutex_unlock(&work->dev->struct_mutex);
5408         kfree(work);
5409 }
5410
5411 static void do_intel_finish_page_flip(struct drm_device *dev,
5412                                       struct drm_crtc *crtc)
5413 {
5414         drm_i915_private_t *dev_priv = dev->dev_private;
5415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5416         struct intel_unpin_work *work;
5417         struct drm_i915_gem_object *obj;
5418         struct drm_pending_vblank_event *e;
5419         struct timeval tnow, tvbl;
5420         unsigned long flags;
5421
5422         /* Ignore early vblank irqs */
5423         if (intel_crtc == NULL)
5424                 return;
5425
5426         do_gettimeofday(&tnow);
5427
5428         spin_lock_irqsave(&dev->event_lock, flags);
5429         work = intel_crtc->unpin_work;
5430         if (work == NULL || !work->pending) {
5431                 spin_unlock_irqrestore(&dev->event_lock, flags);
5432                 return;
5433         }
5434
5435         intel_crtc->unpin_work = NULL;
5436
5437         if (work->event) {
5438                 e = work->event;
5439                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5440
5441                 /* Called before vblank count and timestamps have
5442                  * been updated for the vblank interval of flip
5443                  * completion? Need to increment vblank count and
5444                  * add one videorefresh duration to returned timestamp
5445                  * to account for this. We assume this happened if we
5446                  * get called over 0.9 frame durations after the last
5447                  * timestamped vblank.
5448                  *
5449                  * This calculation can not be used with vrefresh rates
5450                  * below 5Hz (10Hz to be on the safe side) without
5451                  * promoting to 64 integers.
5452                  */
5453                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5454                     9 * crtc->framedur_ns) {
5455                         e->event.sequence++;
5456                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5457                                              crtc->framedur_ns);
5458                 }
5459
5460                 e->event.tv_sec = tvbl.tv_sec;
5461                 e->event.tv_usec = tvbl.tv_usec;
5462
5463                 list_add_tail(&e->base.link,
5464                               &e->base.file_priv->event_list);
5465                 wake_up_interruptible(&e->base.file_priv->event_wait);
5466         }
5467
5468         drm_vblank_put(dev, intel_crtc->pipe);
5469
5470         spin_unlock_irqrestore(&dev->event_lock, flags);
5471
5472         obj = work->old_fb_obj;
5473
5474         atomic_clear_mask(1 << intel_crtc->plane,
5475                           &obj->pending_flip.counter);
5476         if (atomic_read(&obj->pending_flip) == 0)
5477                 wake_up(&dev_priv->pending_flip_queue);
5478
5479         schedule_work(&work->work);
5480
5481         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5482 }
5483
5484 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5485 {
5486         drm_i915_private_t *dev_priv = dev->dev_private;
5487         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5488
5489         do_intel_finish_page_flip(dev, crtc);
5490 }
5491
5492 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5493 {
5494         drm_i915_private_t *dev_priv = dev->dev_private;
5495         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5496
5497         do_intel_finish_page_flip(dev, crtc);
5498 }
5499
5500 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5501 {
5502         drm_i915_private_t *dev_priv = dev->dev_private;
5503         struct intel_crtc *intel_crtc =
5504                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5505         unsigned long flags;
5506
5507         spin_lock_irqsave(&dev->event_lock, flags);
5508         if (intel_crtc->unpin_work) {
5509                 if ((++intel_crtc->unpin_work->pending) > 1)
5510                         DRM_ERROR("Prepared flip multiple times\n");
5511         } else {
5512                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5513         }
5514         spin_unlock_irqrestore(&dev->event_lock, flags);
5515 }
5516
5517 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5518                                 struct drm_framebuffer *fb,
5519                                 struct drm_pending_vblank_event *event)
5520 {
5521         struct drm_device *dev = crtc->dev;
5522         struct drm_i915_private *dev_priv = dev->dev_private;
5523         struct intel_framebuffer *intel_fb;
5524         struct drm_i915_gem_object *obj;
5525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5526         struct intel_unpin_work *work;
5527         unsigned long flags, offset;
5528         int pipe = intel_crtc->pipe;
5529         u32 pf, pipesrc;
5530         int ret;
5531
5532         work = kzalloc(sizeof *work, GFP_KERNEL);
5533         if (work == NULL)
5534                 return -ENOMEM;
5535
5536         work->event = event;
5537         work->dev = crtc->dev;
5538         intel_fb = to_intel_framebuffer(crtc->fb);
5539         work->old_fb_obj = intel_fb->obj;
5540         INIT_WORK(&work->work, intel_unpin_work_fn);
5541
5542         /* We borrow the event spin lock for protecting unpin_work */
5543         spin_lock_irqsave(&dev->event_lock, flags);
5544         if (intel_crtc->unpin_work) {
5545                 spin_unlock_irqrestore(&dev->event_lock, flags);
5546                 kfree(work);
5547
5548                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5549                 return -EBUSY;
5550         }
5551         intel_crtc->unpin_work = work;
5552         spin_unlock_irqrestore(&dev->event_lock, flags);
5553
5554         intel_fb = to_intel_framebuffer(fb);
5555         obj = intel_fb->obj;
5556
5557         mutex_lock(&dev->struct_mutex);
5558         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5559         if (ret)
5560                 goto cleanup_work;
5561
5562         /* Reference the objects for the scheduled work. */
5563         drm_gem_object_reference(&work->old_fb_obj->base);
5564         drm_gem_object_reference(&obj->base);
5565
5566         crtc->fb = fb;
5567
5568         ret = drm_vblank_get(dev, intel_crtc->pipe);
5569         if (ret)
5570                 goto cleanup_objs;
5571
5572         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5573                 u32 flip_mask;
5574
5575                 /* Can't queue multiple flips, so wait for the previous
5576                  * one to finish before executing the next.
5577                  */
5578                 ret = BEGIN_LP_RING(2);
5579                 if (ret)
5580                         goto cleanup_objs;
5581
5582                 if (intel_crtc->plane)
5583                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5584                 else
5585                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5586                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5587                 OUT_RING(MI_NOOP);
5588                 ADVANCE_LP_RING();
5589         }
5590
5591         work->pending_flip_obj = obj;
5592
5593         work->enable_stall_check = true;
5594
5595         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5596         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5597
5598         ret = BEGIN_LP_RING(4);
5599         if (ret)
5600                 goto cleanup_objs;
5601
5602         /* Block clients from rendering to the new back buffer until
5603          * the flip occurs and the object is no longer visible.
5604          */
5605         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5606
5607         switch (INTEL_INFO(dev)->gen) {
5608         case 2:
5609                 OUT_RING(MI_DISPLAY_FLIP |
5610                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5611                 OUT_RING(fb->pitch);
5612                 OUT_RING(obj->gtt_offset + offset);
5613                 OUT_RING(MI_NOOP);
5614                 break;
5615
5616         case 3:
5617                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5618                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5619                 OUT_RING(fb->pitch);
5620                 OUT_RING(obj->gtt_offset + offset);
5621                 OUT_RING(MI_NOOP);
5622                 break;
5623
5624         case 4:
5625         case 5:
5626                 /* i965+ uses the linear or tiled offsets from the
5627                  * Display Registers (which do not change across a page-flip)
5628                  * so we need only reprogram the base address.
5629                  */
5630                 OUT_RING(MI_DISPLAY_FLIP |
5631                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5632                 OUT_RING(fb->pitch);
5633                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5634
5635                 /* XXX Enabling the panel-fitter across page-flip is so far
5636                  * untested on non-native modes, so ignore it for now.
5637                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5638                  */
5639                 pf = 0;
5640                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5641                 OUT_RING(pf | pipesrc);
5642                 break;
5643
5644         case 6:
5645                 OUT_RING(MI_DISPLAY_FLIP |
5646                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5647                 OUT_RING(fb->pitch | obj->tiling_mode);
5648                 OUT_RING(obj->gtt_offset);
5649
5650                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5651                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5652                 OUT_RING(pf | pipesrc);
5653                 break;
5654         }
5655         ADVANCE_LP_RING();
5656
5657         mutex_unlock(&dev->struct_mutex);
5658
5659         trace_i915_flip_request(intel_crtc->plane, obj);
5660
5661         return 0;
5662
5663 cleanup_objs:
5664         drm_gem_object_unreference(&work->old_fb_obj->base);
5665         drm_gem_object_unreference(&obj->base);
5666 cleanup_work:
5667         mutex_unlock(&dev->struct_mutex);
5668
5669         spin_lock_irqsave(&dev->event_lock, flags);
5670         intel_crtc->unpin_work = NULL;
5671         spin_unlock_irqrestore(&dev->event_lock, flags);
5672
5673         kfree(work);
5674
5675         return ret;
5676 }
5677
5678 static void intel_sanitize_modesetting(struct drm_device *dev,
5679                                        int pipe, int plane)
5680 {
5681         struct drm_i915_private *dev_priv = dev->dev_private;
5682         u32 reg, val;
5683
5684         if (HAS_PCH_SPLIT(dev))
5685                 return;
5686
5687         /* Who knows what state these registers were left in by the BIOS or
5688          * grub?
5689          *
5690          * If we leave the registers in a conflicting state (e.g. with the
5691          * display plane reading from the other pipe than the one we intend
5692          * to use) then when we attempt to teardown the active mode, we will
5693          * not disable the pipes and planes in the correct order -- leaving
5694          * a plane reading from a disabled pipe and possibly leading to
5695          * undefined behaviour.
5696          */
5697
5698         reg = DSPCNTR(plane);
5699         val = I915_READ(reg);
5700
5701         if ((val & DISPLAY_PLANE_ENABLE) == 0)
5702                 return;
5703         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5704                 return;
5705
5706         /* This display plane is active and attached to the other CPU pipe. */
5707         pipe = !pipe;
5708
5709         /* Disable the plane and wait for it to stop reading from the pipe. */
5710         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5711         intel_flush_display_plane(dev, plane);
5712
5713         if (IS_GEN2(dev))
5714                 intel_wait_for_vblank(dev, pipe);
5715
5716         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5717                 return;
5718
5719         /* Switch off the pipe. */
5720         reg = PIPECONF(pipe);
5721         val = I915_READ(reg);
5722         if (val & PIPECONF_ENABLE) {
5723                 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5724                 intel_wait_for_pipe_off(dev, pipe);
5725         }
5726 }
5727
5728 static void intel_crtc_reset(struct drm_crtc *crtc)
5729 {
5730         struct drm_device *dev = crtc->dev;
5731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5732
5733         /* Reset flags back to the 'unknown' status so that they
5734          * will be correctly set on the initial modeset.
5735          */
5736         intel_crtc->dpms_mode = -1;
5737
5738         /* We need to fix up any BIOS configuration that conflicts with
5739          * our expectations.
5740          */
5741         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5742 }
5743
5744 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5745         .dpms = intel_crtc_dpms,
5746         .mode_fixup = intel_crtc_mode_fixup,
5747         .mode_set = intel_crtc_mode_set,
5748         .mode_set_base = intel_pipe_set_base,
5749         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5750         .load_lut = intel_crtc_load_lut,
5751         .disable = intel_crtc_disable,
5752 };
5753
5754 static const struct drm_crtc_funcs intel_crtc_funcs = {
5755         .reset = intel_crtc_reset,
5756         .cursor_set = intel_crtc_cursor_set,
5757         .cursor_move = intel_crtc_cursor_move,
5758         .gamma_set = intel_crtc_gamma_set,
5759         .set_config = drm_crtc_helper_set_config,
5760         .destroy = intel_crtc_destroy,
5761         .page_flip = intel_crtc_page_flip,
5762 };
5763
5764 static void intel_crtc_init(struct drm_device *dev, int pipe)
5765 {
5766         drm_i915_private_t *dev_priv = dev->dev_private;
5767         struct intel_crtc *intel_crtc;
5768         int i;
5769
5770         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5771         if (intel_crtc == NULL)
5772                 return;
5773
5774         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5775
5776         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5777         for (i = 0; i < 256; i++) {
5778                 intel_crtc->lut_r[i] = i;
5779                 intel_crtc->lut_g[i] = i;
5780                 intel_crtc->lut_b[i] = i;
5781         }
5782
5783         /* Swap pipes & planes for FBC on pre-965 */
5784         intel_crtc->pipe = pipe;
5785         intel_crtc->plane = pipe;
5786         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5787                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5788                 intel_crtc->plane = !pipe;
5789         }
5790
5791         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5792                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5793         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5794         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5795
5796         intel_crtc_reset(&intel_crtc->base);
5797         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5798
5799         if (HAS_PCH_SPLIT(dev)) {
5800                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5801                 intel_helper_funcs.commit = ironlake_crtc_commit;
5802         } else {
5803                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5804                 intel_helper_funcs.commit = i9xx_crtc_commit;
5805         }
5806
5807         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5808
5809         intel_crtc->busy = false;
5810
5811         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5812                     (unsigned long)intel_crtc);
5813 }
5814
5815 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5816                                 struct drm_file *file)
5817 {
5818         drm_i915_private_t *dev_priv = dev->dev_private;
5819         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5820         struct drm_mode_object *drmmode_obj;
5821         struct intel_crtc *crtc;
5822
5823         if (!dev_priv) {
5824                 DRM_ERROR("called with no initialization\n");
5825                 return -EINVAL;
5826         }
5827
5828         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5829                         DRM_MODE_OBJECT_CRTC);
5830
5831         if (!drmmode_obj) {
5832                 DRM_ERROR("no such CRTC id\n");
5833                 return -EINVAL;
5834         }
5835
5836         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5837         pipe_from_crtc_id->pipe = crtc->pipe;
5838
5839         return 0;
5840 }
5841
5842 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5843 {
5844         struct intel_encoder *encoder;
5845         int index_mask = 0;
5846         int entry = 0;
5847
5848         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5849                 if (type_mask & encoder->clone_mask)
5850                         index_mask |= (1 << entry);
5851                 entry++;
5852         }
5853
5854         return index_mask;
5855 }
5856
5857 static bool has_edp_a(struct drm_device *dev)
5858 {
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860
5861         if (!IS_MOBILE(dev))
5862                 return false;
5863
5864         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5865                 return false;
5866
5867         if (IS_GEN5(dev) &&
5868             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5869                 return false;
5870
5871         return true;
5872 }
5873
5874 static void intel_setup_outputs(struct drm_device *dev)
5875 {
5876         struct drm_i915_private *dev_priv = dev->dev_private;
5877         struct intel_encoder *encoder;
5878         bool dpd_is_edp = false;
5879         bool has_lvds = false;
5880
5881         if (IS_MOBILE(dev) && !IS_I830(dev))
5882                 has_lvds = intel_lvds_init(dev);
5883         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5884                 /* disable the panel fitter on everything but LVDS */
5885                 I915_WRITE(PFIT_CONTROL, 0);
5886         }
5887
5888         if (HAS_PCH_SPLIT(dev)) {
5889                 dpd_is_edp = intel_dpd_is_edp(dev);
5890
5891                 if (has_edp_a(dev))
5892                         intel_dp_init(dev, DP_A);
5893
5894                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5895                         intel_dp_init(dev, PCH_DP_D);
5896         }
5897
5898         intel_crt_init(dev);
5899
5900         if (HAS_PCH_SPLIT(dev)) {
5901                 int found;
5902
5903                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5904                         /* PCH SDVOB multiplex with HDMIB */
5905                         found = intel_sdvo_init(dev, PCH_SDVOB);
5906                         if (!found)
5907                                 intel_hdmi_init(dev, HDMIB);
5908                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5909                                 intel_dp_init(dev, PCH_DP_B);
5910                 }
5911
5912                 if (I915_READ(HDMIC) & PORT_DETECTED)
5913                         intel_hdmi_init(dev, HDMIC);
5914
5915                 if (I915_READ(HDMID) & PORT_DETECTED)
5916                         intel_hdmi_init(dev, HDMID);
5917
5918                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5919                         intel_dp_init(dev, PCH_DP_C);
5920
5921                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5922                         intel_dp_init(dev, PCH_DP_D);
5923
5924         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5925                 bool found = false;
5926
5927                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5928                         DRM_DEBUG_KMS("probing SDVOB\n");
5929                         found = intel_sdvo_init(dev, SDVOB);
5930                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5931                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5932                                 intel_hdmi_init(dev, SDVOB);
5933                         }
5934
5935                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5936                                 DRM_DEBUG_KMS("probing DP_B\n");
5937                                 intel_dp_init(dev, DP_B);
5938                         }
5939                 }
5940
5941                 /* Before G4X SDVOC doesn't have its own detect register */
5942
5943                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5944                         DRM_DEBUG_KMS("probing SDVOC\n");
5945                         found = intel_sdvo_init(dev, SDVOC);
5946                 }
5947
5948                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5949
5950                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5951                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5952                                 intel_hdmi_init(dev, SDVOC);
5953                         }
5954                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5955                                 DRM_DEBUG_KMS("probing DP_C\n");
5956                                 intel_dp_init(dev, DP_C);
5957                         }
5958                 }
5959
5960                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5961                     (I915_READ(DP_D) & DP_DETECTED)) {
5962                         DRM_DEBUG_KMS("probing DP_D\n");
5963                         intel_dp_init(dev, DP_D);
5964                 }
5965         } else if (IS_GEN2(dev))
5966                 intel_dvo_init(dev);
5967
5968         if (SUPPORTS_TV(dev))
5969                 intel_tv_init(dev);
5970
5971         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5972                 encoder->base.possible_crtcs = encoder->crtc_mask;
5973                 encoder->base.possible_clones =
5974                         intel_encoder_clones(dev, encoder->clone_mask);
5975         }
5976
5977         intel_panel_setup_backlight(dev);
5978 }
5979
5980 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5981 {
5982         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5983
5984         drm_framebuffer_cleanup(fb);
5985         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5986
5987         kfree(intel_fb);
5988 }
5989
5990 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5991                                                 struct drm_file *file,
5992                                                 unsigned int *handle)
5993 {
5994         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5995         struct drm_i915_gem_object *obj = intel_fb->obj;
5996
5997         return drm_gem_handle_create(file, &obj->base, handle);
5998 }
5999
6000 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6001         .destroy = intel_user_framebuffer_destroy,
6002         .create_handle = intel_user_framebuffer_create_handle,
6003 };
6004
6005 int intel_framebuffer_init(struct drm_device *dev,
6006                            struct intel_framebuffer *intel_fb,
6007                            struct drm_mode_fb_cmd *mode_cmd,
6008                            struct drm_i915_gem_object *obj)
6009 {
6010         int ret;
6011
6012         if (obj->tiling_mode == I915_TILING_Y)
6013                 return -EINVAL;
6014
6015         if (mode_cmd->pitch & 63)
6016                 return -EINVAL;
6017
6018         switch (mode_cmd->bpp) {
6019         case 8:
6020         case 16:
6021         case 24:
6022         case 32:
6023                 break;
6024         default:
6025                 return -EINVAL;
6026         }
6027
6028         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6029         if (ret) {
6030                 DRM_ERROR("framebuffer init failed %d\n", ret);
6031                 return ret;
6032         }
6033
6034         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6035         intel_fb->obj = obj;
6036         return 0;
6037 }
6038
6039 static struct drm_framebuffer *
6040 intel_user_framebuffer_create(struct drm_device *dev,
6041                               struct drm_file *filp,
6042                               struct drm_mode_fb_cmd *mode_cmd)
6043 {
6044         struct drm_i915_gem_object *obj;
6045         struct intel_framebuffer *intel_fb;
6046         int ret;
6047
6048         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6049         if (!obj)
6050                 return ERR_PTR(-ENOENT);
6051
6052         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6053         if (!intel_fb) {
6054                 drm_gem_object_unreference_unlocked(&obj->base);
6055                 return ERR_PTR(-ENOMEM);
6056         }
6057
6058         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6059         if (ret) {
6060                 drm_gem_object_unreference_unlocked(&obj->base);
6061                 kfree(intel_fb);
6062                 return ERR_PTR(ret);
6063         }
6064
6065         return &intel_fb->base;
6066 }
6067
6068 static const struct drm_mode_config_funcs intel_mode_funcs = {
6069         .fb_create = intel_user_framebuffer_create,
6070         .output_poll_changed = intel_fb_output_poll_changed,
6071 };
6072
6073 static struct drm_i915_gem_object *
6074 intel_alloc_context_page(struct drm_device *dev)
6075 {
6076         struct drm_i915_gem_object *ctx;
6077         int ret;
6078
6079         ctx = i915_gem_alloc_object(dev, 4096);
6080         if (!ctx) {
6081                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6082                 return NULL;
6083         }
6084
6085         mutex_lock(&dev->struct_mutex);
6086         ret = i915_gem_object_pin(ctx, 4096, true);
6087         if (ret) {
6088                 DRM_ERROR("failed to pin power context: %d\n", ret);
6089                 goto err_unref;
6090         }
6091
6092         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6093         if (ret) {
6094                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6095                 goto err_unpin;
6096         }
6097         mutex_unlock(&dev->struct_mutex);
6098
6099         return ctx;
6100
6101 err_unpin:
6102         i915_gem_object_unpin(ctx);
6103 err_unref:
6104         drm_gem_object_unreference(&ctx->base);
6105         mutex_unlock(&dev->struct_mutex);
6106         return NULL;
6107 }
6108
6109 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6110 {
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112         u16 rgvswctl;
6113
6114         rgvswctl = I915_READ16(MEMSWCTL);
6115         if (rgvswctl & MEMCTL_CMD_STS) {
6116                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6117                 return false; /* still busy with another command */
6118         }
6119
6120         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6121                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6122         I915_WRITE16(MEMSWCTL, rgvswctl);
6123         POSTING_READ16(MEMSWCTL);
6124
6125         rgvswctl |= MEMCTL_CMD_STS;
6126         I915_WRITE16(MEMSWCTL, rgvswctl);
6127
6128         return true;
6129 }
6130
6131 void ironlake_enable_drps(struct drm_device *dev)
6132 {
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134         u32 rgvmodectl = I915_READ(MEMMODECTL);
6135         u8 fmax, fmin, fstart, vstart;
6136
6137         /* Enable temp reporting */
6138         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6139         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6140
6141         /* 100ms RC evaluation intervals */
6142         I915_WRITE(RCUPEI, 100000);
6143         I915_WRITE(RCDNEI, 100000);
6144
6145         /* Set max/min thresholds to 90ms and 80ms respectively */
6146         I915_WRITE(RCBMAXAVG, 90000);
6147         I915_WRITE(RCBMINAVG, 80000);
6148
6149         I915_WRITE(MEMIHYST, 1);
6150
6151         /* Set up min, max, and cur for interrupt handling */
6152         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6153         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6154         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6155                 MEMMODE_FSTART_SHIFT;
6156
6157         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6158                 PXVFREQ_PX_SHIFT;
6159
6160         dev_priv->fmax = fmax; /* IPS callback will increase this */
6161         dev_priv->fstart = fstart;
6162
6163         dev_priv->max_delay = fstart;
6164         dev_priv->min_delay = fmin;
6165         dev_priv->cur_delay = fstart;
6166
6167         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6168                          fmax, fmin, fstart);
6169
6170         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6171
6172         /*
6173          * Interrupts will be enabled in ironlake_irq_postinstall
6174          */
6175
6176         I915_WRITE(VIDSTART, vstart);
6177         POSTING_READ(VIDSTART);
6178
6179         rgvmodectl |= MEMMODE_SWMODE_EN;
6180         I915_WRITE(MEMMODECTL, rgvmodectl);
6181
6182         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6183                 DRM_ERROR("stuck trying to change perf mode\n");
6184         msleep(1);
6185
6186         ironlake_set_drps(dev, fstart);
6187
6188         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6189                 I915_READ(0x112e0);
6190         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6191         dev_priv->last_count2 = I915_READ(0x112f4);
6192         getrawmonotonic(&dev_priv->last_time2);
6193 }
6194
6195 void ironlake_disable_drps(struct drm_device *dev)
6196 {
6197         struct drm_i915_private *dev_priv = dev->dev_private;
6198         u16 rgvswctl = I915_READ16(MEMSWCTL);
6199
6200         /* Ack interrupts, disable EFC interrupt */
6201         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6202         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6203         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6204         I915_WRITE(DEIIR, DE_PCU_EVENT);
6205         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6206
6207         /* Go back to the starting frequency */
6208         ironlake_set_drps(dev, dev_priv->fstart);
6209         msleep(1);
6210         rgvswctl |= MEMCTL_CMD_STS;
6211         I915_WRITE(MEMSWCTL, rgvswctl);
6212         msleep(1);
6213
6214 }
6215
6216 void gen6_set_rps(struct drm_device *dev, u8 val)
6217 {
6218         struct drm_i915_private *dev_priv = dev->dev_private;
6219         u32 swreq;
6220
6221         swreq = (val & 0x3ff) << 25;
6222         I915_WRITE(GEN6_RPNSWREQ, swreq);
6223 }
6224
6225 void gen6_disable_rps(struct drm_device *dev)
6226 {
6227         struct drm_i915_private *dev_priv = dev->dev_private;
6228
6229         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6230         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6231         I915_WRITE(GEN6_PMIER, 0);
6232         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6233 }
6234
6235 static unsigned long intel_pxfreq(u32 vidfreq)
6236 {
6237         unsigned long freq;
6238         int div = (vidfreq & 0x3f0000) >> 16;
6239         int post = (vidfreq & 0x3000) >> 12;
6240         int pre = (vidfreq & 0x7);
6241
6242         if (!pre)
6243                 return 0;
6244
6245         freq = ((div * 133333) / ((1<<post) * pre));
6246
6247         return freq;
6248 }
6249
6250 void intel_init_emon(struct drm_device *dev)
6251 {
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         u32 lcfuse;
6254         u8 pxw[16];
6255         int i;
6256
6257         /* Disable to program */
6258         I915_WRITE(ECR, 0);
6259         POSTING_READ(ECR);
6260
6261         /* Program energy weights for various events */
6262         I915_WRITE(SDEW, 0x15040d00);
6263         I915_WRITE(CSIEW0, 0x007f0000);
6264         I915_WRITE(CSIEW1, 0x1e220004);
6265         I915_WRITE(CSIEW2, 0x04000004);
6266
6267         for (i = 0; i < 5; i++)
6268                 I915_WRITE(PEW + (i * 4), 0);
6269         for (i = 0; i < 3; i++)
6270                 I915_WRITE(DEW + (i * 4), 0);
6271
6272         /* Program P-state weights to account for frequency power adjustment */
6273         for (i = 0; i < 16; i++) {
6274                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6275                 unsigned long freq = intel_pxfreq(pxvidfreq);
6276                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6277                         PXVFREQ_PX_SHIFT;
6278                 unsigned long val;
6279
6280                 val = vid * vid;
6281                 val *= (freq / 1000);
6282                 val *= 255;
6283                 val /= (127*127*900);
6284                 if (val > 0xff)
6285                         DRM_ERROR("bad pxval: %ld\n", val);
6286                 pxw[i] = val;
6287         }
6288         /* Render standby states get 0 weight */
6289         pxw[14] = 0;
6290         pxw[15] = 0;
6291
6292         for (i = 0; i < 4; i++) {
6293                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6294                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6295                 I915_WRITE(PXW + (i * 4), val);
6296         }
6297
6298         /* Adjust magic regs to magic values (more experimental results) */
6299         I915_WRITE(OGW0, 0);
6300         I915_WRITE(OGW1, 0);
6301         I915_WRITE(EG0, 0x00007f00);
6302         I915_WRITE(EG1, 0x0000000e);
6303         I915_WRITE(EG2, 0x000e0000);
6304         I915_WRITE(EG3, 0x68000300);
6305         I915_WRITE(EG4, 0x42000000);
6306         I915_WRITE(EG5, 0x00140031);
6307         I915_WRITE(EG6, 0);
6308         I915_WRITE(EG7, 0);
6309
6310         for (i = 0; i < 8; i++)
6311                 I915_WRITE(PXWL + (i * 4), 0);
6312
6313         /* Enable PMON + select events */
6314         I915_WRITE(ECR, 0x80000019);
6315
6316         lcfuse = I915_READ(LCFUSE02);
6317
6318         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6319 }
6320
6321 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6322 {
6323         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6324         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6325         u32 pcu_mbox;
6326         int cur_freq, min_freq, max_freq;
6327         int i;
6328
6329         /* Here begins a magic sequence of register writes to enable
6330          * auto-downclocking.
6331          *
6332          * Perhaps there might be some value in exposing these to
6333          * userspace...
6334          */
6335         I915_WRITE(GEN6_RC_STATE, 0);
6336         __gen6_gt_force_wake_get(dev_priv);
6337
6338         /* disable the counters and set deterministic thresholds */
6339         I915_WRITE(GEN6_RC_CONTROL, 0);
6340
6341         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6342         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6343         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6344         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6345         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6346
6347         for (i = 0; i < I915_NUM_RINGS; i++)
6348                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6349
6350         I915_WRITE(GEN6_RC_SLEEP, 0);
6351         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6352         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6353         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6354         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6355
6356         I915_WRITE(GEN6_RC_CONTROL,
6357                    GEN6_RC_CTL_RC6p_ENABLE |
6358                    GEN6_RC_CTL_RC6_ENABLE |
6359                    GEN6_RC_CTL_EI_MODE(1) |
6360                    GEN6_RC_CTL_HW_ENABLE);
6361
6362         I915_WRITE(GEN6_RPNSWREQ,
6363                    GEN6_FREQUENCY(10) |
6364                    GEN6_OFFSET(0) |
6365                    GEN6_AGGRESSIVE_TURBO);
6366         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6367                    GEN6_FREQUENCY(12));
6368
6369         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6370         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6371                    18 << 24 |
6372                    6 << 16);
6373         I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6374         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6375         I915_WRITE(GEN6_RP_UP_EI, 100000);
6376         I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6377         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6378         I915_WRITE(GEN6_RP_CONTROL,
6379                    GEN6_RP_MEDIA_TURBO |
6380                    GEN6_RP_USE_NORMAL_FREQ |
6381                    GEN6_RP_MEDIA_IS_GFX |
6382                    GEN6_RP_ENABLE |
6383                    GEN6_RP_UP_BUSY_MAX |
6384                    GEN6_RP_DOWN_BUSY_MIN);
6385
6386         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6387                      500))
6388                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6389
6390         I915_WRITE(GEN6_PCODE_DATA, 0);
6391         I915_WRITE(GEN6_PCODE_MAILBOX,
6392                    GEN6_PCODE_READY |
6393                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6394         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6395                      500))
6396                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6397
6398         min_freq = (rp_state_cap & 0xff0000) >> 16;
6399         max_freq = rp_state_cap & 0xff;
6400         cur_freq = (gt_perf_status & 0xff00) >> 8;
6401
6402         /* Check for overclock support */
6403         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6404                      500))
6405                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6406         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6407         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6408         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6409                      500))
6410                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6411         if (pcu_mbox & (1<<31)) { /* OC supported */
6412                 max_freq = pcu_mbox & 0xff;
6413                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6414         }
6415
6416         /* In units of 100MHz */
6417         dev_priv->max_delay = max_freq;
6418         dev_priv->min_delay = min_freq;
6419         dev_priv->cur_delay = cur_freq;
6420
6421         /* requires MSI enabled */
6422         I915_WRITE(GEN6_PMIER,
6423                    GEN6_PM_MBOX_EVENT |
6424                    GEN6_PM_THERMAL_EVENT |
6425                    GEN6_PM_RP_DOWN_TIMEOUT |
6426                    GEN6_PM_RP_UP_THRESHOLD |
6427                    GEN6_PM_RP_DOWN_THRESHOLD |
6428                    GEN6_PM_RP_UP_EI_EXPIRED |
6429                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6430         I915_WRITE(GEN6_PMIMR, 0);
6431         /* enable all PM interrupts */
6432         I915_WRITE(GEN6_PMINTRMSK, 0);
6433
6434         __gen6_gt_force_wake_put(dev_priv);
6435 }
6436
6437 void intel_enable_clock_gating(struct drm_device *dev)
6438 {
6439         struct drm_i915_private *dev_priv = dev->dev_private;
6440
6441         /*
6442          * Disable clock gating reported to work incorrectly according to the
6443          * specs, but enable as much else as we can.
6444          */
6445         if (HAS_PCH_SPLIT(dev)) {
6446                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6447
6448                 if (IS_GEN5(dev)) {
6449                         /* Required for FBC */
6450                         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6451                                 DPFCRUNIT_CLOCK_GATE_DISABLE |
6452                                 DPFDUNIT_CLOCK_GATE_DISABLE;
6453                         /* Required for CxSR */
6454                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6455
6456                         I915_WRITE(PCH_3DCGDIS0,
6457                                    MARIUNIT_CLOCK_GATE_DISABLE |
6458                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6459                         I915_WRITE(PCH_3DCGDIS1,
6460                                    VFMUNIT_CLOCK_GATE_DISABLE);
6461                 }
6462
6463                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6464
6465                 /*
6466                  * On Ibex Peak and Cougar Point, we need to disable clock
6467                  * gating for the panel power sequencer or it will fail to
6468                  * start up when no ports are active.
6469                  */
6470                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6471
6472                 /*
6473                  * According to the spec the following bits should be set in
6474                  * order to enable memory self-refresh
6475                  * The bit 22/21 of 0x42004
6476                  * The bit 5 of 0x42020
6477                  * The bit 15 of 0x45000
6478                  */
6479                 if (IS_GEN5(dev)) {
6480                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6481                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
6482                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6483                         I915_WRITE(ILK_DSPCLK_GATE,
6484                                         (I915_READ(ILK_DSPCLK_GATE) |
6485                                                 ILK_DPARB_CLK_GATE));
6486                         I915_WRITE(DISP_ARB_CTL,
6487                                         (I915_READ(DISP_ARB_CTL) |
6488                                                 DISP_FBC_WM_DIS));
6489                         I915_WRITE(WM3_LP_ILK, 0);
6490                         I915_WRITE(WM2_LP_ILK, 0);
6491                         I915_WRITE(WM1_LP_ILK, 0);
6492                 }
6493                 /*
6494                  * Based on the document from hardware guys the following bits
6495                  * should be set unconditionally in order to enable FBC.
6496                  * The bit 22 of 0x42000
6497                  * The bit 22 of 0x42004
6498                  * The bit 7,8,9 of 0x42020.
6499                  */
6500                 if (IS_IRONLAKE_M(dev)) {
6501                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6502                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6503                                    ILK_FBCQ_DIS);
6504                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6505                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6506                                    ILK_DPARB_GATE);
6507                         I915_WRITE(ILK_DSPCLK_GATE,
6508                                    I915_READ(ILK_DSPCLK_GATE) |
6509                                    ILK_DPFC_DIS1 |
6510                                    ILK_DPFC_DIS2 |
6511                                    ILK_CLK_FBC);
6512                 }
6513
6514                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6515                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6516                            ILK_ELPIN_409_SELECT);
6517
6518                 if (IS_GEN5(dev)) {
6519                         I915_WRITE(_3D_CHICKEN2,
6520                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6521                                    _3D_CHICKEN2_WM_READ_PIPELINED);
6522                 }
6523
6524                 if (IS_GEN6(dev)) {
6525                         I915_WRITE(WM3_LP_ILK, 0);
6526                         I915_WRITE(WM2_LP_ILK, 0);
6527                         I915_WRITE(WM1_LP_ILK, 0);
6528
6529                         /*
6530                          * According to the spec the following bits should be
6531                          * set in order to enable memory self-refresh and fbc:
6532                          * The bit21 and bit22 of 0x42000
6533                          * The bit21 and bit22 of 0x42004
6534                          * The bit5 and bit7 of 0x42020
6535                          * The bit14 of 0x70180
6536                          * The bit14 of 0x71180
6537                          */
6538                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6539                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6540                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6541                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6542                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6543                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6544                         I915_WRITE(ILK_DSPCLK_GATE,
6545                                    I915_READ(ILK_DSPCLK_GATE) |
6546                                    ILK_DPARB_CLK_GATE  |
6547                                    ILK_DPFD_CLK_GATE);
6548
6549                         I915_WRITE(DSPACNTR,
6550                                    I915_READ(DSPACNTR) |
6551                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6552                         I915_WRITE(DSPBCNTR,
6553                                    I915_READ(DSPBCNTR) |
6554                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6555                 }
6556         } else if (IS_G4X(dev)) {
6557                 uint32_t dspclk_gate;
6558                 I915_WRITE(RENCLK_GATE_D1, 0);
6559                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6560                        GS_UNIT_CLOCK_GATE_DISABLE |
6561                        CL_UNIT_CLOCK_GATE_DISABLE);
6562                 I915_WRITE(RAMCLK_GATE_D, 0);
6563                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6564                         OVRUNIT_CLOCK_GATE_DISABLE |
6565                         OVCUNIT_CLOCK_GATE_DISABLE;
6566                 if (IS_GM45(dev))
6567                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6568                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6569         } else if (IS_CRESTLINE(dev)) {
6570                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6571                 I915_WRITE(RENCLK_GATE_D2, 0);
6572                 I915_WRITE(DSPCLK_GATE_D, 0);
6573                 I915_WRITE(RAMCLK_GATE_D, 0);
6574                 I915_WRITE16(DEUC, 0);
6575         } else if (IS_BROADWATER(dev)) {
6576                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6577                        I965_RCC_CLOCK_GATE_DISABLE |
6578                        I965_RCPB_CLOCK_GATE_DISABLE |
6579                        I965_ISC_CLOCK_GATE_DISABLE |
6580                        I965_FBC_CLOCK_GATE_DISABLE);
6581                 I915_WRITE(RENCLK_GATE_D2, 0);
6582         } else if (IS_GEN3(dev)) {
6583                 u32 dstate = I915_READ(D_STATE);
6584
6585                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6586                         DSTATE_DOT_CLOCK_GATING;
6587                 I915_WRITE(D_STATE, dstate);
6588         } else if (IS_I85X(dev) || IS_I865G(dev)) {
6589                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6590         } else if (IS_I830(dev)) {
6591                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6592         }
6593 }
6594
6595 static void ironlake_teardown_rc6(struct drm_device *dev)
6596 {
6597         struct drm_i915_private *dev_priv = dev->dev_private;
6598
6599         if (dev_priv->renderctx) {
6600                 i915_gem_object_unpin(dev_priv->renderctx);
6601                 drm_gem_object_unreference(&dev_priv->renderctx->base);
6602                 dev_priv->renderctx = NULL;
6603         }
6604
6605         if (dev_priv->pwrctx) {
6606                 i915_gem_object_unpin(dev_priv->pwrctx);
6607                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
6608                 dev_priv->pwrctx = NULL;
6609         }
6610 }
6611
6612 static void ironlake_disable_rc6(struct drm_device *dev)
6613 {
6614         struct drm_i915_private *dev_priv = dev->dev_private;
6615
6616         if (I915_READ(PWRCTXA)) {
6617                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6618                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6619                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6620                          50);
6621
6622                 I915_WRITE(PWRCTXA, 0);
6623                 POSTING_READ(PWRCTXA);
6624
6625                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6626                 POSTING_READ(RSTDBYCTL);
6627         }
6628
6629         ironlake_teardown_rc6(dev);
6630 }
6631
6632 static int ironlake_setup_rc6(struct drm_device *dev)
6633 {
6634         struct drm_i915_private *dev_priv = dev->dev_private;
6635
6636         if (dev_priv->renderctx == NULL)
6637                 dev_priv->renderctx = intel_alloc_context_page(dev);
6638         if (!dev_priv->renderctx)
6639                 return -ENOMEM;
6640
6641         if (dev_priv->pwrctx == NULL)
6642                 dev_priv->pwrctx = intel_alloc_context_page(dev);
6643         if (!dev_priv->pwrctx) {
6644                 ironlake_teardown_rc6(dev);
6645                 return -ENOMEM;
6646         }
6647
6648         return 0;
6649 }
6650
6651 void ironlake_enable_rc6(struct drm_device *dev)
6652 {
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         int ret;
6655
6656         /* rc6 disabled by default due to repeated reports of hanging during
6657          * boot and resume.
6658          */
6659         if (!i915_enable_rc6)
6660                 return;
6661
6662         ret = ironlake_setup_rc6(dev);
6663         if (ret)
6664                 return;
6665
6666         /*
6667          * GPU can automatically power down the render unit if given a page
6668          * to save state.
6669          */
6670         ret = BEGIN_LP_RING(6);
6671         if (ret) {
6672                 ironlake_teardown_rc6(dev);
6673                 return;
6674         }
6675
6676         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6677         OUT_RING(MI_SET_CONTEXT);
6678         OUT_RING(dev_priv->renderctx->gtt_offset |
6679                  MI_MM_SPACE_GTT |
6680                  MI_SAVE_EXT_STATE_EN |
6681                  MI_RESTORE_EXT_STATE_EN |
6682                  MI_RESTORE_INHIBIT);
6683         OUT_RING(MI_SUSPEND_FLUSH);
6684         OUT_RING(MI_NOOP);
6685         OUT_RING(MI_FLUSH);
6686         ADVANCE_LP_RING();
6687
6688         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6689         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6690 }
6691
6692
6693 /* Set up chip specific display functions */
6694 static void intel_init_display(struct drm_device *dev)
6695 {
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697
6698         /* We always want a DPMS function */
6699         if (HAS_PCH_SPLIT(dev))
6700                 dev_priv->display.dpms = ironlake_crtc_dpms;
6701         else
6702                 dev_priv->display.dpms = i9xx_crtc_dpms;
6703
6704         if (I915_HAS_FBC(dev)) {
6705                 if (HAS_PCH_SPLIT(dev)) {
6706                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6707                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6708                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6709                 } else if (IS_GM45(dev)) {
6710                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6711                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6712                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6713                 } else if (IS_CRESTLINE(dev)) {
6714                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6715                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6716                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6717                 }
6718                 /* 855GM needs testing */
6719         }
6720
6721         /* Returns the core display clock speed */
6722         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6723                 dev_priv->display.get_display_clock_speed =
6724                         i945_get_display_clock_speed;
6725         else if (IS_I915G(dev))
6726                 dev_priv->display.get_display_clock_speed =
6727                         i915_get_display_clock_speed;
6728         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6729                 dev_priv->display.get_display_clock_speed =
6730                         i9xx_misc_get_display_clock_speed;
6731         else if (IS_I915GM(dev))
6732                 dev_priv->display.get_display_clock_speed =
6733                         i915gm_get_display_clock_speed;
6734         else if (IS_I865G(dev))
6735                 dev_priv->display.get_display_clock_speed =
6736                         i865_get_display_clock_speed;
6737         else if (IS_I85X(dev))
6738                 dev_priv->display.get_display_clock_speed =
6739                         i855_get_display_clock_speed;
6740         else /* 852, 830 */
6741                 dev_priv->display.get_display_clock_speed =
6742                         i830_get_display_clock_speed;
6743
6744         /* For FIFO watermark updates */
6745         if (HAS_PCH_SPLIT(dev)) {
6746                 if (IS_GEN5(dev)) {
6747                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6748                                 dev_priv->display.update_wm = ironlake_update_wm;
6749                         else {
6750                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6751                                               "Disable CxSR\n");
6752                                 dev_priv->display.update_wm = NULL;
6753                         }
6754                 } else if (IS_GEN6(dev)) {
6755                         if (SNB_READ_WM0_LATENCY()) {
6756                                 dev_priv->display.update_wm = sandybridge_update_wm;
6757                         } else {
6758                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6759                                               "Disable CxSR\n");
6760                                 dev_priv->display.update_wm = NULL;
6761                         }
6762                 } else
6763                         dev_priv->display.update_wm = NULL;
6764         } else if (IS_PINEVIEW(dev)) {
6765                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6766                                             dev_priv->is_ddr3,
6767                                             dev_priv->fsb_freq,
6768                                             dev_priv->mem_freq)) {
6769                         DRM_INFO("failed to find known CxSR latency "
6770                                  "(found ddr%s fsb freq %d, mem freq %d), "
6771                                  "disabling CxSR\n",
6772                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6773                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6774                         /* Disable CxSR and never update its watermark again */
6775                         pineview_disable_cxsr(dev);
6776                         dev_priv->display.update_wm = NULL;
6777                 } else
6778                         dev_priv->display.update_wm = pineview_update_wm;
6779         } else if (IS_G4X(dev))
6780                 dev_priv->display.update_wm = g4x_update_wm;
6781         else if (IS_GEN4(dev))
6782                 dev_priv->display.update_wm = i965_update_wm;
6783         else if (IS_GEN3(dev)) {
6784                 dev_priv->display.update_wm = i9xx_update_wm;
6785                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6786         } else if (IS_I85X(dev)) {
6787                 dev_priv->display.update_wm = i9xx_update_wm;
6788                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6789         } else {
6790                 dev_priv->display.update_wm = i830_update_wm;
6791                 if (IS_845G(dev))
6792                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6793                 else
6794                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6795         }
6796 }
6797
6798 /*
6799  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6800  * resume, or other times.  This quirk makes sure that's the case for
6801  * affected systems.
6802  */
6803 static void quirk_pipea_force (struct drm_device *dev)
6804 {
6805         struct drm_i915_private *dev_priv = dev->dev_private;
6806
6807         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6808         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6809 }
6810
6811 struct intel_quirk {
6812         int device;
6813         int subsystem_vendor;
6814         int subsystem_device;
6815         void (*hook)(struct drm_device *dev);
6816 };
6817
6818 struct intel_quirk intel_quirks[] = {
6819         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6820         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6821         /* HP Mini needs pipe A force quirk (LP: #322104) */
6822         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6823
6824         /* Thinkpad R31 needs pipe A force quirk */
6825         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6826         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6827         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6828
6829         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6830         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6831         /* ThinkPad X40 needs pipe A force quirk */
6832
6833         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6834         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6835
6836         /* 855 & before need to leave pipe A & dpll A up */
6837         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6838         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6839 };
6840
6841 static void intel_init_quirks(struct drm_device *dev)
6842 {
6843         struct pci_dev *d = dev->pdev;
6844         int i;
6845
6846         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6847                 struct intel_quirk *q = &intel_quirks[i];
6848
6849                 if (d->device == q->device &&
6850                     (d->subsystem_vendor == q->subsystem_vendor ||
6851                      q->subsystem_vendor == PCI_ANY_ID) &&
6852                     (d->subsystem_device == q->subsystem_device ||
6853                      q->subsystem_device == PCI_ANY_ID))
6854                         q->hook(dev);
6855         }
6856 }
6857
6858 /* Disable the VGA plane that we never use */
6859 static void i915_disable_vga(struct drm_device *dev)
6860 {
6861         struct drm_i915_private *dev_priv = dev->dev_private;
6862         u8 sr1;
6863         u32 vga_reg;
6864
6865         if (HAS_PCH_SPLIT(dev))
6866                 vga_reg = CPU_VGACNTRL;
6867         else
6868                 vga_reg = VGACNTRL;
6869
6870         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6871         outb(1, VGA_SR_INDEX);
6872         sr1 = inb(VGA_SR_DATA);
6873         outb(sr1 | 1<<5, VGA_SR_DATA);
6874         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6875         udelay(300);
6876
6877         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6878         POSTING_READ(vga_reg);
6879 }
6880
6881 void intel_modeset_init(struct drm_device *dev)
6882 {
6883         struct drm_i915_private *dev_priv = dev->dev_private;
6884         int i;
6885
6886         drm_mode_config_init(dev);
6887
6888         dev->mode_config.min_width = 0;
6889         dev->mode_config.min_height = 0;
6890
6891         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6892
6893         intel_init_quirks(dev);
6894
6895         intel_init_display(dev);
6896
6897         if (IS_GEN2(dev)) {
6898                 dev->mode_config.max_width = 2048;
6899                 dev->mode_config.max_height = 2048;
6900         } else if (IS_GEN3(dev)) {
6901                 dev->mode_config.max_width = 4096;
6902                 dev->mode_config.max_height = 4096;
6903         } else {
6904                 dev->mode_config.max_width = 8192;
6905                 dev->mode_config.max_height = 8192;
6906         }
6907         dev->mode_config.fb_base = dev->agp->base;
6908
6909         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6910                 dev_priv->num_pipe = 2;
6911         else
6912                 dev_priv->num_pipe = 1;
6913         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6914                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6915
6916         for (i = 0; i < dev_priv->num_pipe; i++) {
6917                 intel_crtc_init(dev, i);
6918         }
6919
6920         intel_setup_outputs(dev);
6921
6922         intel_enable_clock_gating(dev);
6923
6924         /* Just disable it once at startup */
6925         i915_disable_vga(dev);
6926
6927         if (IS_IRONLAKE_M(dev)) {
6928                 ironlake_enable_drps(dev);
6929                 intel_init_emon(dev);
6930         }
6931
6932         if (IS_GEN6(dev))
6933                 gen6_enable_rps(dev_priv);
6934
6935         if (IS_IRONLAKE_M(dev))
6936                 ironlake_enable_rc6(dev);
6937
6938         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6939         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6940                     (unsigned long)dev);
6941
6942         intel_setup_overlay(dev);
6943 }
6944
6945 void intel_modeset_cleanup(struct drm_device *dev)
6946 {
6947         struct drm_i915_private *dev_priv = dev->dev_private;
6948         struct drm_crtc *crtc;
6949         struct intel_crtc *intel_crtc;
6950
6951         drm_kms_helper_poll_fini(dev);
6952         mutex_lock(&dev->struct_mutex);
6953
6954         intel_unregister_dsm_handler();
6955
6956
6957         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6958                 /* Skip inactive CRTCs */
6959                 if (!crtc->fb)
6960                         continue;
6961
6962                 intel_crtc = to_intel_crtc(crtc);
6963                 intel_increase_pllclock(crtc);
6964         }
6965
6966         if (dev_priv->display.disable_fbc)
6967                 dev_priv->display.disable_fbc(dev);
6968
6969         if (IS_IRONLAKE_M(dev))
6970                 ironlake_disable_drps(dev);
6971         if (IS_GEN6(dev))
6972                 gen6_disable_rps(dev);
6973
6974         if (IS_IRONLAKE_M(dev))
6975                 ironlake_disable_rc6(dev);
6976
6977         mutex_unlock(&dev->struct_mutex);
6978
6979         /* Disable the irq before mode object teardown, for the irq might
6980          * enqueue unpin/hotplug work. */
6981         drm_irq_uninstall(dev);
6982         cancel_work_sync(&dev_priv->hotplug_work);
6983
6984         /* Shut off idle work before the crtcs get freed. */
6985         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6986                 intel_crtc = to_intel_crtc(crtc);
6987                 del_timer_sync(&intel_crtc->idle_timer);
6988         }
6989         del_timer_sync(&dev_priv->idle_timer);
6990         cancel_work_sync(&dev_priv->idle_work);
6991
6992         drm_mode_config_cleanup(dev);
6993 }
6994
6995 /*
6996  * Return which encoder is currently attached for connector.
6997  */
6998 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6999 {
7000         return &intel_attached_encoder(connector)->base;
7001 }
7002
7003 void intel_connector_attach_encoder(struct intel_connector *connector,
7004                                     struct intel_encoder *encoder)
7005 {
7006         connector->encoder = encoder;
7007         drm_mode_connector_attach_encoder(&connector->base,
7008                                           &encoder->base);
7009 }
7010
7011 /*
7012  * set vga decode state - true == enable VGA decode
7013  */
7014 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7015 {
7016         struct drm_i915_private *dev_priv = dev->dev_private;
7017         u16 gmch_ctrl;
7018
7019         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7020         if (state)
7021                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7022         else
7023                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7024         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7025         return 0;
7026 }
7027
7028 #ifdef CONFIG_DEBUG_FS
7029 #include <linux/seq_file.h>
7030
7031 struct intel_display_error_state {
7032         struct intel_cursor_error_state {
7033                 u32 control;
7034                 u32 position;
7035                 u32 base;
7036                 u32 size;
7037         } cursor[2];
7038
7039         struct intel_pipe_error_state {
7040                 u32 conf;
7041                 u32 source;
7042
7043                 u32 htotal;
7044                 u32 hblank;
7045                 u32 hsync;
7046                 u32 vtotal;
7047                 u32 vblank;
7048                 u32 vsync;
7049         } pipe[2];
7050
7051         struct intel_plane_error_state {
7052                 u32 control;
7053                 u32 stride;
7054                 u32 size;
7055                 u32 pos;
7056                 u32 addr;
7057                 u32 surface;
7058                 u32 tile_offset;
7059         } plane[2];
7060 };
7061
7062 struct intel_display_error_state *
7063 intel_display_capture_error_state(struct drm_device *dev)
7064 {
7065         drm_i915_private_t *dev_priv = dev->dev_private;
7066         struct intel_display_error_state *error;
7067         int i;
7068
7069         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7070         if (error == NULL)
7071                 return NULL;
7072
7073         for (i = 0; i < 2; i++) {
7074                 error->cursor[i].control = I915_READ(CURCNTR(i));
7075                 error->cursor[i].position = I915_READ(CURPOS(i));
7076                 error->cursor[i].base = I915_READ(CURBASE(i));
7077
7078                 error->plane[i].control = I915_READ(DSPCNTR(i));
7079                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7080                 error->plane[i].size = I915_READ(DSPSIZE(i));
7081                 error->plane[i].pos= I915_READ(DSPPOS(i));
7082                 error->plane[i].addr = I915_READ(DSPADDR(i));
7083                 if (INTEL_INFO(dev)->gen >= 4) {
7084                         error->plane[i].surface = I915_READ(DSPSURF(i));
7085                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7086                 }
7087
7088                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7089                 error->pipe[i].source = I915_READ(PIPESRC(i));
7090                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7091                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7092                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7093                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7094                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7095                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7096         }
7097
7098         return error;
7099 }
7100
7101 void
7102 intel_display_print_error_state(struct seq_file *m,
7103                                 struct drm_device *dev,
7104                                 struct intel_display_error_state *error)
7105 {
7106         int i;
7107
7108         for (i = 0; i < 2; i++) {
7109                 seq_printf(m, "Pipe [%d]:\n", i);
7110                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7111                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7112                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7113                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7114                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7115                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7116                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7117                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7118
7119                 seq_printf(m, "Plane [%d]:\n", i);
7120                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7121                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7122                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7123                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7124                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7125                 if (INTEL_INFO(dev)->gen >= 4) {
7126                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7127                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7128                 }
7129
7130                 seq_printf(m, "Cursor [%d]:\n", i);
7131                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7132                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7133                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7134         }
7135 }
7136 #endif