arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/thread_info.h>
   8 #include <linux/module.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/pgtable.h>
  12 #include <asm/msr.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/ds.h>
  15 #include <asm/bugs.h>
  16
  17 #ifdef CONFIG_X86_64
  18 #include <asm/topology.h>
  19 #include <asm/numa_64.h>
  20 #endif
  21
  22 #include "cpu.h"
  23
  24 #ifdef CONFIG_X86_LOCAL_APIC
  25 #include <asm/mpspec.h>
  26 #include <asm/apic.h>
  27 #include <mach_apic.h>
  28 #endif
  29
  30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  31 {
  32         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  33                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  34                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  35
  36 #ifdef CONFIG_X86_64
  37         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  38 #else
  39         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  40         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  41                 c->x86_cache_alignment = 128;
  42 #endif
  43
  44         /*
  45          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  46          * with P/T states and does not stop in deep C-states
  47          */
  48         if (c->x86_power & (1 << 8)) {
  49                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  50                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  51         }
  52
  53         /*
  54          * There is a known erratum on Pentium III and Core Solo
  55          * and Core Duo CPUs.
  56          * " Page with PAT set to WC while associated MTRR is UC
  57          *   may consolidate to UC "
  58          * Because of this erratum, it is better to stick with
  59          * setting WC in MTRR rather than using PAT on these CPUs.
  60          *
  61          * Enable PAT WC only on P4, Core 2 or later CPUs.
  62          */
  63         if (c->x86 == 6 && c->x86_model < 15)
  64                 clear_cpu_cap(c, X86_FEATURE_PAT);
  65 }
  66
  67 #ifdef CONFIG_X86_32
  68 /*
  69  *      Early probe support logic for ppro memory erratum #50
  70  *
  71  *      This is called before we do cpu ident work
  72  */
  73
  74 int __cpuinit ppro_with_ram_bug(void)
  75 {
  76         /* Uses data from early_cpu_detect now */
  77         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  78             boot_cpu_data.x86 == 6 &&
  79             boot_cpu_data.x86_model == 1 &&
  80             boot_cpu_data.x86_mask < 8) {
  81                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  82                 return 1;
  83         }
  84         return 0;
  85 }
  86
  87 #ifdef CONFIG_X86_F00F_BUG
  88 static void __cpuinit trap_init_f00f_bug(void)
  89 {
  90         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
  91
  92         /*
  93          * Update the IDT descriptor and reload the IDT so that
  94          * it uses the read-only mapped virtual address.
  95          */
  96         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
  97         load_idt(&idt_descr);
  98 }
  99 #endif
 100
 101 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 102 {
 103         unsigned long lo, hi;
 104
 105 #ifdef CONFIG_X86_F00F_BUG
 106         /*
 107          * All current models of Pentium and Pentium with MMX technology CPUs
 108          * have the F0 0F bug, which lets nonprivileged users lock up the system.
 109          * Note that the workaround only should be initialized once...
 110          */
 111         c->f00f_bug = 0;
 112         if (!paravirt_enabled() && c->x86 == 5) {
 113                 static int f00f_workaround_enabled;
 114
 115                 c->f00f_bug = 1;
 116                 if (!f00f_workaround_enabled) {
 117                         trap_init_f00f_bug();
 118                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 119                         f00f_workaround_enabled = 1;
 120                 }
 121         }
 122 #endif
 123
 124         /*
 125          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 126          * model 3 mask 3
 127          */
 128         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 129                 clear_cpu_cap(c, X86_FEATURE_SEP);
 130
 131         /*
 132          * P4 Xeon errata 037 workaround.
 133          * Hardware prefetcher may cause stale data to be loaded into the cache.
 134          */
 135         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 136                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 137                 if ((lo & (1<<9)) == 0) {
 138                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 139                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 140                         lo |= (1<<9);   /* Disable hw prefetching */
 141                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 142                 }
 143         }
 144
 145         /*
 146          * See if we have a good local APIC by checking for buggy Pentia,
 147          * i.e. all B steppings and the C2 stepping of P54C when using their
 148          * integrated APIC (see 11AP erratum in "Pentium Processor
 149          * Specification Update").
 150          */
 151         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 152             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 153                 set_cpu_cap(c, X86_FEATURE_11AP);
 154
 155
 156 #ifdef CONFIG_X86_INTEL_USERCOPY
 157         /*
 158          * Set up the preferred alignment for movsl bulk memory moves
 159          */
 160         switch (c->x86) {
 161         case 4:         /* 486: untested */
 162                 break;
 163         case 5:         /* Old Pentia: untested */
 164                 break;
 165         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 166                 movsl_mask.mask = 7;
 167                 break;
 168         case 15:        /* P4 is OK down to 8-byte alignment */
 169                 movsl_mask.mask = 7;
 170                 break;
 171         }
 172 #endif
 173
 174 #ifdef CONFIG_X86_NUMAQ
 175         numaq_tsc_disable();
 176 #endif
 177 }
 178 #else
 179 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 180 {
 181 }
 182 #endif
 183
 184 static void __cpuinit srat_detect_node(void)
 185 {
 186 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 187         unsigned node;
 188         int cpu = smp_processor_id();
 189         int apicid = hard_smp_processor_id();
 190
 191         /* Don't do the funky fallback heuristics the AMD version employs
 192            for now. */
 193         node = apicid_to_node[apicid];
 194         if (node == NUMA_NO_NODE || !node_online(node))
 195                 node = first_node(node_online_map);
 196         numa_set_node(cpu, node);
 197
 198         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
 199 #endif
 200 }
 201
 202 /*
 203  * find out the number of processor cores on the die
 204  */
 205 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 206 {
 207         unsigned int eax, ebx, ecx, edx;
 208
 209         if (c->cpuid_level < 4)
 210                 return 1;
 211
 212         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 213         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 214         if (eax & 0x1f)
 215                 return ((eax >> 26) + 1);
 216         else
 217                 return 1;
 218 }
 219
 220 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 221 {
 222         /* Intel VMX MSR indicated features */
 223 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 224 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 225 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 226 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 227 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 228 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 229
 230         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 231
 232         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 233         clear_cpu_cap(c, X86_FEATURE_VNMI);
 234         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 235         clear_cpu_cap(c, X86_FEATURE_EPT);
 236         clear_cpu_cap(c, X86_FEATURE_VPID);
 237
 238         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 239         msr_ctl = vmx_msr_high | vmx_msr_low;
 240         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 241                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 242         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 243                 set_cpu_cap(c, X86_FEATURE_VNMI);
 244         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 245                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 246                       vmx_msr_low, vmx_msr_high);
 247                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 248                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 249                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 250                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 251                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 252                         set_cpu_cap(c, X86_FEATURE_EPT);
 253                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 254                         set_cpu_cap(c, X86_FEATURE_VPID);
 255         }
 256 }
 257
 258 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 259 {
 260         unsigned int l2 = 0;
 261
 262         early_init_intel(c);
 263
 264         intel_workarounds(c);
 265
 266         /*
 267          * Detect the extended topology information if available. This
 268          * will reinitialise the initial_apicid which will be used
 269          * in init_intel_cacheinfo()
 270          */
 271         detect_extended_topology(c);
 272
 273         l2 = init_intel_cacheinfo(c);
 274         if (c->cpuid_level > 9) {
 275                 unsigned eax = cpuid_eax(10);
 276                 /* Check for version and the number of counters */
 277                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 278                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 279         }
 280
 281         if (cpu_has_xmm2)
 282                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 283         if (cpu_has_ds) {
 284                 unsigned int l1;
 285                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 286                 if (!(l1 & (1<<11)))
 287                         set_cpu_cap(c, X86_FEATURE_BTS);
 288                 if (!(l1 & (1<<12)))
 289                         set_cpu_cap(c, X86_FEATURE_PEBS);
 290                 ds_init_intel(c);
 291         }
 292
 293 #ifdef CONFIG_X86_64
 294         if (c->x86 == 15)
 295                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 296         if (c->x86 == 6)
 297                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 298 #else
 299         /*
 300          * Names for the Pentium II/Celeron processors
 301          * detectable only by also checking the cache size.
 302          * Dixon is NOT a Celeron.
 303          */
 304         if (c->x86 == 6) {
 305                 char *p = NULL;
 306
 307                 switch (c->x86_model) {
 308                 case 5:
 309                         if (c->x86_mask == 0) {
 310                                 if (l2 == 0)
 311                                         p = "Celeron (Covington)";
 312                                 else if (l2 == 256)
 313                                         p = "Mobile Pentium II (Dixon)";
 314                         }
 315                         break;
 316
 317                 case 6:
 318                         if (l2 == 128)
 319                                 p = "Celeron (Mendocino)";
 320                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 321                                 p = "Celeron-A";
 322                         break;
 323
 324                 case 8:
 325                         if (l2 == 128)
 326                                 p = "Celeron (Coppermine)";
 327                         break;
 328                 }
 329
 330                 if (p)
 331                         strcpy(c->x86_model_id, p);
 332         }
 333
 334         if (c->x86 == 15)
 335                 set_cpu_cap(c, X86_FEATURE_P4);
 336         if (c->x86 == 6)
 337                 set_cpu_cap(c, X86_FEATURE_P3);
 338 #endif
 339
 340         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 341                 /*
 342                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 343                  * detection.
 344                  */
 345                 c->x86_max_cores = intel_num_cpu_cores(c);
 346 #ifdef CONFIG_X86_32
 347                 detect_ht(c);
 348 #endif
 349         }
 350
 351         /* Work around errata */
 352         srat_detect_node();
 353
 354         if (cpu_has(c, X86_FEATURE_VMX))
 355                 detect_vmx_virtcap(c);
 356 }
 357
 358 #ifdef CONFIG_X86_32
 359 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 360 {
 361         /*
 362          * Intel PIII Tualatin. This comes in two flavours.
 363          * One has 256kb of cache, the other 512. We have no way
 364          * to determine which, so we use a boottime override
 365          * for the 512kb model, and assume 256 otherwise.
 366          */
 367         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 368                 size = 256;
 369         return size;
 370 }
 371 #endif
 372
 373 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
 374         .c_vendor       = "Intel",
 375         .c_ident        = { "GenuineIntel" },
 376 #ifdef CONFIG_X86_32
 377         .c_models = {
 378                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 379                   {
 380                           [0] = "486 DX-25/33",
 381                           [1] = "486 DX-50",
 382                           [2] = "486 SX",
 383                           [3] = "486 DX/2",
 384                           [4] = "486 SL",
 385                           [5] = "486 SX/2",
 386                           [7] = "486 DX/2-WB",
 387                           [8] = "486 DX/4",
 388                           [9] = "486 DX/4-WB"
 389                   }
 390                 },
 391                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 392                   {
 393                           [0] = "Pentium 60/66 A-step",
 394                           [1] = "Pentium 60/66",
 395                           [2] = "Pentium 75 - 200",
 396                           [3] = "OverDrive PODP5V83",
 397                           [4] = "Pentium MMX",
 398                           [7] = "Mobile Pentium 75 - 200",
 399                           [8] = "Mobile Pentium MMX"
 400                   }
 401                 },
 402                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 403                   {
 404                           [0] = "Pentium Pro A-step",
 405                           [1] = "Pentium Pro",
 406                           [3] = "Pentium II (Klamath)",
 407                           [4] = "Pentium II (Deschutes)",
 408                           [5] = "Pentium II (Deschutes)",
 409                           [6] = "Mobile Pentium II",
 410                           [7] = "Pentium III (Katmai)",
 411                           [8] = "Pentium III (Coppermine)",
 412                           [10] = "Pentium III (Cascades)",
 413                           [11] = "Pentium III (Tualatin)",
 414                   }
 415                 },
 416                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 417                   {
 418                           [0] = "Pentium 4 (Unknown)",
 419                           [1] = "Pentium 4 (Willamette)",
 420                           [2] = "Pentium 4 (Northwood)",
 421                           [4] = "Pentium 4 (Foster)",
 422                           [5] = "Pentium 4 (Foster)",
 423                   }
 424                 },
 425         },
 426         .c_size_cache   = intel_size_cache,
 427 #endif
 428         .c_early_init   = early_init_intel,
 429         .c_init         = init_intel,
 430         .c_x86_vendor   = X86_VENDOR_INTEL,
 431 };
 432
 433 cpu_dev_register(intel_cpu_dev);
 434