drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 350 }
 351
 352 static const intel_limit_t intel_limits_i8xx_dvo = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i8xx_lvds = {
 367         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 368         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 369         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 370         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 371         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 372         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 373         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 374         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 375         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 376                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_sdvo = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 390                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 391         .find_pll = intel_find_best_PLL,
 392 };
 393
 394 static const intel_limit_t intel_limits_i9xx_lvds = {
 395         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 396         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 397         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 398         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 399         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 400         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 401         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 402         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 403         /* The single-channel range is 25-112Mhz, and dual-channel
 404          * is 80-224Mhz.  Prefer single channel as much as possible.
 405          */
 406         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 407                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 408         .find_pll = intel_find_best_PLL,
 409 };
 410
 411     /* below parameter and function is for G4X Chipset Family*/
 412 static const intel_limit_t intel_limits_g4x_sdvo = {
 413         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 414         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 416         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 417         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 418         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 419         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 420         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 421         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 422                  .p2_slow = G4X_P2_SDVO_SLOW,
 423                  .p2_fast = G4X_P2_SDVO_FAST
 424         },
 425         .find_pll = intel_g4x_find_best_PLL,
 426 };
 427
 428 static const intel_limit_t intel_limits_g4x_hdmi = {
 429         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 430         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 431         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 432         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 433         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 434         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 435         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 436         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 437         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 438                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 439                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 440         },
 441         .find_pll = intel_g4x_find_best_PLL,
 442 };
 443
 444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 445         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 447         .vco = { .min = G4X_VCO_MIN,
 448                  .max = G4X_VCO_MAX },
 449         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 451         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 453         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 454                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 455         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 456                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 457         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 458                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 459         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 460                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 461         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 462                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 463                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 464         },
 465         .find_pll = intel_g4x_find_best_PLL,
 466 };
 467
 468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 469         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 471         .vco = { .min = G4X_VCO_MIN,
 472                  .max = G4X_VCO_MAX },
 473         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 475         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 477         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 478                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 479         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 480                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 481         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 482                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 483         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 484                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 485         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 486                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 487                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 488         },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_g4x_display_port = {
 493         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 494                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 495         .vco = { .min = G4X_VCO_MIN,
 496                  .max = G4X_VCO_MAX},
 497         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 498                  .max = G4X_N_DISPLAY_PORT_MAX },
 499         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 500                  .max = G4X_M_DISPLAY_PORT_MAX },
 501         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 502                  .max = G4X_M1_DISPLAY_PORT_MAX },
 503         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 504                  .max = G4X_M2_DISPLAY_PORT_MAX },
 505         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 506                  .max = G4X_P_DISPLAY_PORT_MAX },
 507         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 508                  .max = G4X_P1_DISPLAY_PORT_MAX},
 509         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 510                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 511                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 512         .find_pll = intel_find_pll_g4x_dp,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_sdvo = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 525                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 526         .find_pll = intel_find_best_PLL,
 527 };
 528
 529 static const intel_limit_t intel_limits_pineview_lvds = {
 530         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 531         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 532         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 533         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 534         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 535         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 536         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 537         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 538         /* Pineview only supports single-channel mode. */
 539         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 540                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 541         .find_pll = intel_find_best_PLL,
 542 };
 543
 544 static const intel_limit_t intel_limits_ironlake_dac = {
 545         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 546         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 547         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 548         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 549         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 550         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 551         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 552         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 553         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 554                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 555                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 556         .find_pll = intel_g4x_find_best_PLL,
 557 };
 558
 559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 560         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 561         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 562         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 563         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 564         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 565         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 566         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 567         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 568         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 569                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 570                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 571         .find_pll = intel_g4x_find_best_PLL,
 572 };
 573
 574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 575         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 576         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 577         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 578         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 579         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 580         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 581         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 582         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 583         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 584                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 585                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 586         .find_pll = intel_g4x_find_best_PLL,
 587 };
 588
 589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 590         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 591         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 592         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 593         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 594         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 595         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 596         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 597         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 598         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 599                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 600                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 601         .find_pll = intel_g4x_find_best_PLL,
 602 };
 603
 604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 605         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 606         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 607         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 608         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 609         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 610         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 611         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 612         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 613         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 614                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 615                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 616         .find_pll = intel_g4x_find_best_PLL,
 617 };
 618
 619 static const intel_limit_t intel_limits_ironlake_display_port = {
 620         .dot = { .min = IRONLAKE_DOT_MIN,
 621                  .max = IRONLAKE_DOT_MAX },
 622         .vco = { .min = IRONLAKE_VCO_MIN,
 623                  .max = IRONLAKE_VCO_MAX},
 624         .n   = { .min = IRONLAKE_DP_N_MIN,
 625                  .max = IRONLAKE_DP_N_MAX },
 626         .m   = { .min = IRONLAKE_DP_M_MIN,
 627                  .max = IRONLAKE_DP_M_MAX },
 628         .m1  = { .min = IRONLAKE_M1_MIN,
 629                  .max = IRONLAKE_M1_MAX },
 630         .m2  = { .min = IRONLAKE_M2_MIN,
 631                  .max = IRONLAKE_M2_MAX },
 632         .p   = { .min = IRONLAKE_DP_P_MIN,
 633                  .max = IRONLAKE_DP_P_MAX },
 634         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 635                  .max = IRONLAKE_DP_P1_MAX},
 636         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 637                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 638                  .p2_fast = IRONLAKE_DP_P2_FAST },
 639         .find_pll = intel_find_pll_ironlake_dp,
 640 };
 641
 642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         const intel_limit_t *limit;
 647         int refclk = 120;
 648
 649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 650                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 651                         refclk = 100;
 652
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 774 {
 775         const intel_limit_t *limit = intel_limit (crtc);
 776         struct drm_device *dev = crtc->dev;
 777
 778         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 779                 INTELPllInvalid ("p1 out of range\n");
 780         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 781                 INTELPllInvalid ("p out of range\n");
 782         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 783                 INTELPllInvalid ("m2 out of range\n");
 784         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 785                 INTELPllInvalid ("m1 out of range\n");
 786         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 787                 INTELPllInvalid ("m1 <= m2\n");
 788         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 789                 INTELPllInvalid ("m out of range\n");
 790         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 791                 INTELPllInvalid ("n out of range\n");
 792         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 793                 INTELPllInvalid ("vco out of range\n");
 794         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 795          * connector, etc., rather than just a single range.
 796          */
 797         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 798                 INTELPllInvalid ("dot out of range\n");
 799
 800         return true;
 801 }
 802
 803 static bool
 804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 805                     int target, int refclk, intel_clock_t *best_clock)
 806
 807 {
 808         struct drm_device *dev = crtc->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         intel_clock_t clock;
 811         int err = target;
 812
 813         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 814             (I915_READ(LVDS)) != 0) {
 815                 /*
 816                  * For LVDS, if the panel is on, just rely on its current
 817                  * settings for dual-channel.  We haven't figured out how to
 818                  * reliably set up different single/dual channel state, if we
 819                  * even can.
 820                  */
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset (best_clock, 0, sizeof (*best_clock));
 834
 835         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 836              clock.m1++) {
 837                 for (clock.m2 = limit->m2.min;
 838                      clock.m2 <= limit->m2.max; clock.m2++) {
 839                         /* m1 is always 0 in Pineview */
 840                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 841                                 break;
 842                         for (clock.n = limit->n.min;
 843                              clock.n <= limit->n.max; clock.n++) {
 844                                 for (clock.p1 = limit->p1.min;
 845                                         clock.p1 <= limit->p1.max; clock.p1++) {
 846                                         int this_err;
 847
 848                                         intel_clock(dev, refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(crtc, &clock))
 851                                                 continue;
 852
 853                                         this_err = abs(clock.dot - target);
 854                                         if (this_err < err) {
 855                                                 *best_clock = clock;
 856                                                 err = this_err;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return (err != target);
 864 }
 865
 866 static bool
 867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 868                         int target, int refclk, intel_clock_t *best_clock)
 869 {
 870         struct drm_device *dev = crtc->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         intel_clock_t clock;
 873         int max_n;
 874         bool found;
 875         /* approximately equals target * 0.00585 */
 876         int err_most = (target >> 8) + (target >> 9);
 877         found = false;
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 int lvds_reg;
 881
 882                 if (HAS_PCH_SPLIT(dev))
 883                         lvds_reg = PCH_LVDS;
 884                 else
 885                         lvds_reg = LVDS;
 886                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 887                     LVDS_CLKB_POWER_UP)
 888                         clock.p2 = limit->p2.p2_fast;
 889                 else
 890                         clock.p2 = limit->p2.p2_slow;
 891         } else {
 892                 if (target < limit->p2.dot_limit)
 893                         clock.p2 = limit->p2.p2_slow;
 894                 else
 895                         clock.p2 = limit->p2.p2_fast;
 896         }
 897
 898         memset(best_clock, 0, sizeof(*best_clock));
 899         max_n = limit->n.max;
 900         /* based on hardware requirement, prefer smaller n to precision */
 901         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 902                 /* based on hardware requirement, prefere larger m1,m2 */
 903                 for (clock.m1 = limit->m1.max;
 904                      clock.m1 >= limit->m1.min; clock.m1--) {
 905                         for (clock.m2 = limit->m2.max;
 906                              clock.m2 >= limit->m2.min; clock.m2--) {
 907                                 for (clock.p1 = limit->p1.max;
 908                                      clock.p1 >= limit->p1.min; clock.p1--) {
 909                                         int this_err;
 910
 911                                         intel_clock(dev, refclk, &clock);
 912                                         if (!intel_PLL_is_valid(crtc, &clock))
 913                                                 continue;
 914                                         this_err = abs(clock.dot - target) ;
 915                                         if (this_err < err_most) {
 916                                                 *best_clock = clock;
 917                                                 err_most = this_err;
 918                                                 max_n = clock.n;
 919                                                 found = true;
 920                                         }
 921                                 }
 922                         }
 923                 }
 924         }
 925         return found;
 926 }
 927
 928 static bool
 929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 930                            int target, int refclk, intel_clock_t *best_clock)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         intel_clock_t clock;
 934
 935         /* return directly when it is eDP */
 936         if (HAS_eDP)
 937                 return true;
 938
 939         if (target < 200000) {
 940                 clock.n = 1;
 941                 clock.p1 = 2;
 942                 clock.p2 = 10;
 943                 clock.m1 = 12;
 944                 clock.m2 = 9;
 945         } else {
 946                 clock.n = 2;
 947                 clock.p1 = 1;
 948                 clock.p2 = 10;
 949                 clock.m1 = 14;
 950                 clock.m2 = 8;
 951         }
 952         intel_clock(dev, refclk, &clock);
 953         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 954         return true;
 955 }
 956
 957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 958 static bool
 959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 960                       int target, int refclk, intel_clock_t *best_clock)
 961 {
 962         intel_clock_t clock;
 963         if (target < 200000) {
 964                 clock.p1 = 2;
 965                 clock.p2 = 10;
 966                 clock.n = 2;
 967                 clock.m1 = 23;
 968                 clock.m2 = 8;
 969         } else {
 970                 clock.p1 = 1;
 971                 clock.p2 = 10;
 972                 clock.n = 1;
 973                 clock.m1 = 14;
 974                 clock.m2 = 2;
 975         }
 976         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 977         clock.p = (clock.p1 * clock.p2);
 978         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 979         clock.vco = 0;
 980         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 981         return true;
 982 }
 983
 984 /**
 985  * intel_wait_for_vblank - wait for vblank on a given pipe
 986  * @dev: drm device
 987  * @pipe: pipe to wait for
 988  *
 989  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 990  * mode setting code.
 991  */
 992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 996
 997         /* Clear existing vblank status. Note this will clear any other
 998          * sticky status fields as well.
 999          *
1000          * This races with i915_driver_irq_handler() with the result
1001          * that either function could miss a vblank event.  Here it is not
1002          * fatal, as we will either wait upon the next vblank interrupt or
1003          * timeout.  Generally speaking intel_wait_for_vblank() is only
1004          * called during modeset at which time the GPU should be idle and
1005          * should *not* be performing page flips and thus not waiting on
1006          * vblanks...
1007          * Currently, the result of us stealing a vblank from the irq
1008          * handler is that a single frame will be skipped during swapbuffers.
1009          */
1010         I915_WRITE(pipestat_reg,
1011                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013         /* Wait for vblank interrupt bit to set */
1014         if (wait_for(I915_READ(pipestat_reg) &
1015                      PIPE_VBLANK_INTERRUPT_STATUS,
1016                      50))
1017                 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /**
1021  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1022  * @dev: drm device
1023  * @pipe: pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * So this function waits for the display line value to settle (it
1030  * usually ends up stopping at the start of the next frame).
1031  */
1032 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1036         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037         u32 last_line, line;
1038
1039         /* Wait for the display line to settle */
1040         line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1041         do {
1042                 last_line = line;
1043                 MSLEEP(5);
1044                 line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1045         } while (line != last_line && time_after(timeout, jiffies));
1046
1047         if (line != last_line)
1048                 DRM_DEBUG_KMS("vblank wait timed out\n");
1049 }
1050
1051 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1052 {
1053         struct drm_device *dev = crtc->dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         struct drm_framebuffer *fb = crtc->fb;
1056         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1057         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059         int plane, i;
1060         u32 fbc_ctl, fbc_ctl2;
1061
1062         if (fb->pitch == dev_priv->cfb_pitch &&
1063             obj_priv->fence_reg == dev_priv->cfb_fence &&
1064             intel_crtc->plane == dev_priv->cfb_plane &&
1065             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1066                 return;
1067
1068         i8xx_disable_fbc(dev);
1069
1070         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1071
1072         if (fb->pitch < dev_priv->cfb_pitch)
1073                 dev_priv->cfb_pitch = fb->pitch;
1074
1075         /* FBC_CTL wants 64B units */
1076         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1077         dev_priv->cfb_fence = obj_priv->fence_reg;
1078         dev_priv->cfb_plane = intel_crtc->plane;
1079         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1080
1081         /* Clear old tags */
1082         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1083                 I915_WRITE(FBC_TAG + (i * 4), 0);
1084
1085         /* Set it up... */
1086         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1087         if (obj_priv->tiling_mode != I915_TILING_NONE)
1088                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1089         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1090         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1091
1092         /* enable it... */
1093         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1094         if (IS_I945GM(dev))
1095                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1096         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1097         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1098         if (obj_priv->tiling_mode != I915_TILING_NONE)
1099                 fbc_ctl |= dev_priv->cfb_fence;
1100         I915_WRITE(FBC_CONTROL, fbc_ctl);
1101
1102         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1103                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1104 }
1105
1106 void i8xx_disable_fbc(struct drm_device *dev)
1107 {
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         u32 fbc_ctl;
1110
1111         /* Disable compression */
1112         fbc_ctl = I915_READ(FBC_CONTROL);
1113         if ((fbc_ctl & FBC_CTL_EN) == 0)
1114                 return;
1115
1116         fbc_ctl &= ~FBC_CTL_EN;
1117         I915_WRITE(FBC_CONTROL, fbc_ctl);
1118
1119         /* Wait for compressing bit to clear */
1120         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1121                 DRM_DEBUG_KMS("FBC idle timed out\n");
1122                 return;
1123         }
1124
1125         DRM_DEBUG_KMS("disabled FBC\n");
1126 }
1127
1128 static bool i8xx_fbc_enabled(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1133 }
1134
1135 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136 {
1137         struct drm_device *dev = crtc->dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct drm_framebuffer *fb = crtc->fb;
1140         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1141         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1143         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1144         unsigned long stall_watermark = 200;
1145         u32 dpfc_ctl;
1146
1147         dpfc_ctl = I915_READ(DPFC_CONTROL);
1148         if (dpfc_ctl & DPFC_CTL_EN) {
1149                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1150                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1151                     dev_priv->cfb_plane == intel_crtc->plane &&
1152                     dev_priv->cfb_y == crtc->y)
1153                         return;
1154
1155                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1156                 POSTING_READ(DPFC_CONTROL);
1157                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1158         }
1159
1160         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1161         dev_priv->cfb_fence = obj_priv->fence_reg;
1162         dev_priv->cfb_plane = intel_crtc->plane;
1163         dev_priv->cfb_y = crtc->y;
1164
1165         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1166         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1167                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1168                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1169         } else {
1170                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1171         }
1172
1173         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1174                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1175                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1176         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1177
1178         /* enable it... */
1179         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1180
1181         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1182 }
1183
1184 void g4x_disable_fbc(struct drm_device *dev)
1185 {
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         u32 dpfc_ctl;
1188
1189         /* Disable compression */
1190         dpfc_ctl = I915_READ(DPFC_CONTROL);
1191         if (dpfc_ctl & DPFC_CTL_EN) {
1192                 dpfc_ctl &= ~DPFC_CTL_EN;
1193                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1194
1195                 DRM_DEBUG_KMS("disabled FBC\n");
1196         }
1197 }
1198
1199 static bool g4x_fbc_enabled(struct drm_device *dev)
1200 {
1201         struct drm_i915_private *dev_priv = dev->dev_private;
1202
1203         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1204 }
1205
1206 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1207 {
1208         struct drm_device *dev = crtc->dev;
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210         struct drm_framebuffer *fb = crtc->fb;
1211         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1212         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1214         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1215         unsigned long stall_watermark = 200;
1216         u32 dpfc_ctl;
1217
1218         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1219         if (dpfc_ctl & DPFC_CTL_EN) {
1220                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1221                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1222                     dev_priv->cfb_plane == intel_crtc->plane &&
1223                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1224                     dev_priv->cfb_y == crtc->y)
1225                         return;
1226
1227                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1228                 POSTING_READ(ILK_DPFC_CONTROL);
1229                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1230         }
1231
1232         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1233         dev_priv->cfb_fence = obj_priv->fence_reg;
1234         dev_priv->cfb_plane = intel_crtc->plane;
1235         dev_priv->cfb_offset = obj_priv->gtt_offset;
1236         dev_priv->cfb_y = crtc->y;
1237
1238         dpfc_ctl &= DPFC_RESERVED;
1239         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1240         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1241                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1242                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1243         } else {
1244                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1245         }
1246
1247         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1248                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1249                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1250         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1251         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1252         /* enable it... */
1253         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1254
1255         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1256 }
1257
1258 void ironlake_disable_fbc(struct drm_device *dev)
1259 {
1260         struct drm_i915_private *dev_priv = dev->dev_private;
1261         u32 dpfc_ctl;
1262
1263         /* Disable compression */
1264         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1265         if (dpfc_ctl & DPFC_CTL_EN) {
1266                 dpfc_ctl &= ~DPFC_CTL_EN;
1267                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1268
1269                 DRM_DEBUG_KMS("disabled FBC\n");
1270         }
1271 }
1272
1273 static bool ironlake_fbc_enabled(struct drm_device *dev)
1274 {
1275         struct drm_i915_private *dev_priv = dev->dev_private;
1276
1277         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1278 }
1279
1280 bool intel_fbc_enabled(struct drm_device *dev)
1281 {
1282         struct drm_i915_private *dev_priv = dev->dev_private;
1283
1284         if (!dev_priv->display.fbc_enabled)
1285                 return false;
1286
1287         return dev_priv->display.fbc_enabled(dev);
1288 }
1289
1290 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1291 {
1292         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1293
1294         if (!dev_priv->display.enable_fbc)
1295                 return;
1296
1297         dev_priv->display.enable_fbc(crtc, interval);
1298 }
1299
1300 void intel_disable_fbc(struct drm_device *dev)
1301 {
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303
1304         if (!dev_priv->display.disable_fbc)
1305                 return;
1306
1307         dev_priv->display.disable_fbc(dev);
1308 }
1309
1310 /**
1311  * intel_update_fbc - enable/disable FBC as needed
1312  * @dev: the drm_device
1313  *
1314  * Set up the framebuffer compression hardware at mode set time.  We
1315  * enable it if possible:
1316  *   - plane A only (on pre-965)
1317  *   - no pixel mulitply/line duplication
1318  *   - no alpha buffer discard
1319  *   - no dual wide
1320  *   - framebuffer <= 2048 in width, 1536 in height
1321  *
1322  * We can't assume that any compression will take place (worst case),
1323  * so the compressed buffer has to be the same size as the uncompressed
1324  * one.  It also must reside (along with the line length buffer) in
1325  * stolen memory.
1326  *
1327  * We need to enable/disable FBC on a global basis.
1328  */
1329 static void intel_update_fbc(struct drm_device *dev)
1330 {
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         struct drm_crtc *crtc = NULL, *tmp_crtc;
1333         struct intel_crtc *intel_crtc;
1334         struct drm_framebuffer *fb;
1335         struct intel_framebuffer *intel_fb;
1336         struct drm_i915_gem_object *obj_priv;
1337
1338         DRM_DEBUG_KMS("\n");
1339
1340         if (!i915_powersave)
1341                 return;
1342
1343         if (!I915_HAS_FBC(dev))
1344                 return;
1345
1346         /*
1347          * If FBC is already on, we just have to verify that we can
1348          * keep it that way...
1349          * Need to disable if:
1350          *   - more than one pipe is active
1351          *   - changing FBC params (stride, fence, mode)
1352          *   - new fb is too large to fit in compressed buffer
1353          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1354          */
1355         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1356                 if (tmp_crtc->enabled) {
1357                         if (crtc) {
1358                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1359                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1360                                 goto out_disable;
1361                         }
1362                         crtc = tmp_crtc;
1363                 }
1364         }
1365
1366         if (!crtc || crtc->fb == NULL) {
1367                 DRM_DEBUG_KMS("no output, disabling\n");
1368                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1369                 goto out_disable;
1370         }
1371
1372         intel_crtc = to_intel_crtc(crtc);
1373         fb = crtc->fb;
1374         intel_fb = to_intel_framebuffer(fb);
1375         obj_priv = to_intel_bo(intel_fb->obj);
1376
1377         if (intel_fb->obj->size > dev_priv->cfb_size) {
1378                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1379                               "compression\n");
1380                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1381                 goto out_disable;
1382         }
1383         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1384             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1385                 DRM_DEBUG_KMS("mode incompatible with compression, "
1386                               "disabling\n");
1387                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1388                 goto out_disable;
1389         }
1390         if ((crtc->mode.hdisplay > 2048) ||
1391             (crtc->mode.vdisplay > 1536)) {
1392                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1393                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1394                 goto out_disable;
1395         }
1396         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1397                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1398                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1399                 goto out_disable;
1400         }
1401         if (obj_priv->tiling_mode != I915_TILING_X) {
1402                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1403                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1404                 goto out_disable;
1405         }
1406
1407         /* If the kernel debugger is active, always disable compression */
1408         if (in_dbg_master())
1409                 goto out_disable;
1410
1411         intel_enable_fbc(crtc, 500);
1412         return;
1413
1414 out_disable:
1415         /* Multiple disables should be harmless */
1416         if (intel_fbc_enabled(dev)) {
1417                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1418                 intel_disable_fbc(dev);
1419         }
1420 }
1421
1422 int
1423 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1424                            struct drm_gem_object *obj,
1425                            bool pipelined)
1426 {
1427         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1428         u32 alignment;
1429         int ret;
1430
1431         switch (obj_priv->tiling_mode) {
1432         case I915_TILING_NONE:
1433                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1434                         alignment = 128 * 1024;
1435                 else if (INTEL_INFO(dev)->gen >= 4)
1436                         alignment = 4 * 1024;
1437                 else
1438                         alignment = 64 * 1024;
1439                 break;
1440         case I915_TILING_X:
1441                 /* pin() will align the object as required by fence */
1442                 alignment = 0;
1443                 break;
1444         case I915_TILING_Y:
1445                 /* FIXME: Is this true? */
1446                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1447                 return -EINVAL;
1448         default:
1449                 BUG();
1450         }
1451
1452         ret = i915_gem_object_pin(obj, alignment);
1453         if (ret)
1454                 return ret;
1455
1456         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1457         if (ret)
1458                 goto err_unpin;
1459
1460         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1461          * fence, whereas 965+ only requires a fence if using
1462          * framebuffer compression.  For simplicity, we always install
1463          * a fence as the cost is not that onerous.
1464          */
1465         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1466             obj_priv->tiling_mode != I915_TILING_NONE) {
1467                 ret = i915_gem_object_get_fence_reg(obj, false);
1468                 if (ret)
1469                         goto err_unpin;
1470         }
1471
1472         return 0;
1473
1474 err_unpin:
1475         i915_gem_object_unpin(obj);
1476         return ret;
1477 }
1478
1479 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1480 static int
1481 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1482                            int x, int y)
1483 {
1484         struct drm_device *dev = crtc->dev;
1485         struct drm_i915_private *dev_priv = dev->dev_private;
1486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1487         struct intel_framebuffer *intel_fb;
1488         struct drm_i915_gem_object *obj_priv;
1489         struct drm_gem_object *obj;
1490         int plane = intel_crtc->plane;
1491         unsigned long Start, Offset;
1492         u32 dspcntr;
1493         u32 reg;
1494
1495         switch (plane) {
1496         case 0:
1497         case 1:
1498                 break;
1499         default:
1500                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1501                 return -EINVAL;
1502         }
1503
1504         intel_fb = to_intel_framebuffer(fb);
1505         obj = intel_fb->obj;
1506         obj_priv = to_intel_bo(obj);
1507
1508         reg = DSPCNTR(plane);
1509         dspcntr = I915_READ(reg);
1510         /* Mask out pixel format bits in case we change it */
1511         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1512         switch (fb->bits_per_pixel) {
1513         case 8:
1514                 dspcntr |= DISPPLANE_8BPP;
1515                 break;
1516         case 16:
1517                 if (fb->depth == 15)
1518                         dspcntr |= DISPPLANE_15_16BPP;
1519                 else
1520                         dspcntr |= DISPPLANE_16BPP;
1521                 break;
1522         case 24:
1523         case 32:
1524                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1525                 break;
1526         default:
1527                 DRM_ERROR("Unknown color depth\n");
1528                 return -EINVAL;
1529         }
1530         if (INTEL_INFO(dev)->gen >= 4) {
1531                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1532                         dspcntr |= DISPPLANE_TILED;
1533                 else
1534                         dspcntr &= ~DISPPLANE_TILED;
1535         }
1536
1537         if (HAS_PCH_SPLIT(dev))
1538                 /* must disable */
1539                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1540
1541         I915_WRITE(reg, dspcntr);
1542
1543         Start = obj_priv->gtt_offset;
1544         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1545
1546         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1547                       Start, Offset, x, y, fb->pitch);
1548         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1549         if (INTEL_INFO(dev)->gen >= 4) {
1550                 I915_WRITE(DSPSURF(plane), Start);
1551                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1552                 I915_WRITE(DSPADDR(plane), Offset);
1553         } else
1554                 I915_WRITE(DSPADDR(plane), Start + Offset);
1555         POSTING_READ(reg);
1556
1557         intel_update_fbc(dev);
1558         intel_increase_pllclock(crtc);
1559
1560         return 0;
1561 }
1562
1563 static int
1564 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1565                     struct drm_framebuffer *old_fb)
1566 {
1567         struct drm_device *dev = crtc->dev;
1568         struct drm_i915_master_private *master_priv;
1569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1570         int ret;
1571
1572         /* no fb bound */
1573         if (!crtc->fb) {
1574                 DRM_DEBUG_KMS("No FB bound\n");
1575                 return 0;
1576         }
1577
1578         switch (intel_crtc->plane) {
1579         case 0:
1580         case 1:
1581                 break;
1582         default:
1583                 return -EINVAL;
1584         }
1585
1586         mutex_lock(&dev->struct_mutex);
1587         ret = intel_pin_and_fence_fb_obj(dev,
1588                                          to_intel_framebuffer(crtc->fb)->obj,
1589                                          false);
1590         if (ret != 0) {
1591                 mutex_unlock(&dev->struct_mutex);
1592                 return ret;
1593         }
1594
1595         if (old_fb) {
1596                 struct drm_i915_private *dev_priv = dev->dev_private;
1597                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1598                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1599
1600                 wait_event(dev_priv->pending_flip_queue,
1601                            atomic_read(&obj_priv->pending_flip) == 0);
1602         }
1603
1604         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1605         if (ret) {
1606                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1607                 mutex_unlock(&dev->struct_mutex);
1608                 return ret;
1609         }
1610
1611         if (old_fb)
1612                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1613
1614         mutex_unlock(&dev->struct_mutex);
1615
1616         if (!dev->primary->master)
1617                 return 0;
1618
1619         master_priv = dev->primary->master->driver_priv;
1620         if (!master_priv->sarea_priv)
1621                 return 0;
1622
1623         if (intel_crtc->pipe) {
1624                 master_priv->sarea_priv->pipeB_x = x;
1625                 master_priv->sarea_priv->pipeB_y = y;
1626         } else {
1627                 master_priv->sarea_priv->pipeA_x = x;
1628                 master_priv->sarea_priv->pipeA_y = y;
1629         }
1630
1631         return 0;
1632 }
1633
1634 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1635 {
1636         struct drm_device *dev = crtc->dev;
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         u32 dpa_ctl;
1639
1640         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1641         dpa_ctl = I915_READ(DP_A);
1642         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1643
1644         if (clock < 200000) {
1645                 u32 temp;
1646                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1647                 /* workaround for 160Mhz:
1648                    1) program 0x4600c bits 15:0 = 0x8124
1649                    2) program 0x46010 bit 0 = 1
1650                    3) program 0x46034 bit 24 = 1
1651                    4) program 0x64000 bit 14 = 1
1652                    */
1653                 temp = I915_READ(0x4600c);
1654                 temp &= 0xffff0000;
1655                 I915_WRITE(0x4600c, temp | 0x8124);
1656
1657                 temp = I915_READ(0x46010);
1658                 I915_WRITE(0x46010, temp | 1);
1659
1660                 temp = I915_READ(0x46034);
1661                 I915_WRITE(0x46034, temp | (1 << 24));
1662         } else {
1663                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1664         }
1665         I915_WRITE(DP_A, dpa_ctl);
1666
1667         POSTING_READ(DP_A);
1668         udelay(500);
1669 }
1670
1671 /* The FDI link training functions for ILK/Ibexpeak. */
1672 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1673 {
1674         struct drm_device *dev = crtc->dev;
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1677         int pipe = intel_crtc->pipe;
1678         u32 reg, temp, tries;
1679
1680         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1681            for train result */
1682         reg = FDI_RX_IMR(pipe);
1683         temp = I915_READ(reg);
1684         temp &= ~FDI_RX_SYMBOL_LOCK;
1685         temp &= ~FDI_RX_BIT_LOCK;
1686         I915_WRITE(reg, temp);
1687         I915_READ(reg);
1688         udelay(150);
1689
1690         /* enable CPU FDI TX and PCH FDI RX */
1691         reg = FDI_TX_CTL(pipe);
1692         temp = I915_READ(reg);
1693         temp &= ~(7 << 19);
1694         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1695         temp &= ~FDI_LINK_TRAIN_NONE;
1696         temp |= FDI_LINK_TRAIN_PATTERN_1;
1697         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1698
1699         reg = FDI_RX_CTL(pipe);
1700         temp = I915_READ(reg);
1701         temp &= ~FDI_LINK_TRAIN_NONE;
1702         temp |= FDI_LINK_TRAIN_PATTERN_1;
1703         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1704
1705         POSTING_READ(reg);
1706         udelay(150);
1707
1708         reg = FDI_RX_IIR(pipe);
1709         for (tries = 0; tries < 5; tries++) {
1710                 temp = I915_READ(reg);
1711                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1712
1713                 if ((temp & FDI_RX_BIT_LOCK)) {
1714                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1715                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1716                         break;
1717                 }
1718         }
1719         if (tries == 5)
1720                 DRM_ERROR("FDI train 1 fail!\n");
1721
1722         /* Train 2 */
1723         reg = FDI_TX_CTL(pipe);
1724         temp = I915_READ(reg);
1725         temp &= ~FDI_LINK_TRAIN_NONE;
1726         temp |= FDI_LINK_TRAIN_PATTERN_2;
1727         I915_WRITE(reg, temp);
1728
1729         reg = FDI_RX_CTL(pipe);
1730         temp = I915_READ(reg);
1731         temp &= ~FDI_LINK_TRAIN_NONE;
1732         temp |= FDI_LINK_TRAIN_PATTERN_2;
1733         I915_WRITE(reg, temp);
1734
1735         POSTING_READ(reg);
1736         udelay(150);
1737
1738         reg = FDI_RX_IIR(pipe);
1739         for (tries = 0; tries < 5; tries++) {
1740                 temp = I915_READ(reg);
1741                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1742
1743                 if (temp & FDI_RX_SYMBOL_LOCK) {
1744                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1745                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1746                         break;
1747                 }
1748         }
1749         if (tries == 5)
1750                 DRM_ERROR("FDI train 2 fail!\n");
1751
1752         DRM_DEBUG_KMS("FDI train done\n");
1753 }
1754
1755 static const int const snb_b_fdi_train_param [] = {
1756         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1757         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1758         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1759         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1760 };
1761
1762 /* The FDI link training functions for SNB/Cougarpoint. */
1763 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1764 {
1765         struct drm_device *dev = crtc->dev;
1766         struct drm_i915_private *dev_priv = dev->dev_private;
1767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1768         int pipe = intel_crtc->pipe;
1769         u32 reg, temp, i;
1770
1771         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1772            for train result */
1773         reg = FDI_RX_IMR(pipe);
1774         temp = I915_READ(reg);
1775         temp &= ~FDI_RX_SYMBOL_LOCK;
1776         temp &= ~FDI_RX_BIT_LOCK;
1777         I915_WRITE(reg, temp);
1778
1779         POSTING_READ(reg);
1780         udelay(150);
1781
1782         /* enable CPU FDI TX and PCH FDI RX */
1783         reg = FDI_TX_CTL(pipe);
1784         temp = I915_READ(reg);
1785         temp &= ~(7 << 19);
1786         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1787         temp &= ~FDI_LINK_TRAIN_NONE;
1788         temp |= FDI_LINK_TRAIN_PATTERN_1;
1789         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1790         /* SNB-B */
1791         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1792         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1793
1794         reg = FDI_RX_CTL(pipe);
1795         temp = I915_READ(reg);
1796         if (HAS_PCH_CPT(dev)) {
1797                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1798                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1799         } else {
1800                 temp &= ~FDI_LINK_TRAIN_NONE;
1801                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1802         }
1803         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1804
1805         POSTING_READ(reg);
1806         udelay(150);
1807
1808         for (i = 0; i < 4; i++ ) {
1809                 reg = FDI_TX_CTL(pipe);
1810                 temp = I915_READ(reg);
1811                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1812                 temp |= snb_b_fdi_train_param[i];
1813                 I915_WRITE(reg, temp);
1814
1815                 POSTING_READ(reg);
1816                 udelay(500);
1817
1818                 reg = FDI_RX_IIR(pipe);
1819                 temp = I915_READ(reg);
1820                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1821
1822                 if (temp & FDI_RX_BIT_LOCK) {
1823                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1824                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1825                         break;
1826                 }
1827         }
1828         if (i == 4)
1829                 DRM_ERROR("FDI train 1 fail!\n");
1830
1831         /* Train 2 */
1832         reg = FDI_TX_CTL(pipe);
1833         temp = I915_READ(reg);
1834         temp &= ~FDI_LINK_TRAIN_NONE;
1835         temp |= FDI_LINK_TRAIN_PATTERN_2;
1836         if (IS_GEN6(dev)) {
1837                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1838                 /* SNB-B */
1839                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1840         }
1841         I915_WRITE(reg, temp);
1842
1843         reg = FDI_RX_CTL(pipe);
1844         temp = I915_READ(reg);
1845         if (HAS_PCH_CPT(dev)) {
1846                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1847                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1848         } else {
1849                 temp &= ~FDI_LINK_TRAIN_NONE;
1850                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1851         }
1852         I915_WRITE(reg, temp);
1853
1854         POSTING_READ(reg);
1855         udelay(150);
1856
1857         for (i = 0; i < 4; i++ ) {
1858                 reg = FDI_TX_CTL(pipe);
1859                 temp = I915_READ(reg);
1860                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1861                 temp |= snb_b_fdi_train_param[i];
1862                 I915_WRITE(reg, temp);
1863
1864                 POSTING_READ(reg);
1865                 udelay(500);
1866
1867                 reg = FDI_RX_IIR(pipe);
1868                 temp = I915_READ(reg);
1869                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1870
1871                 if (temp & FDI_RX_SYMBOL_LOCK) {
1872                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1873                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1874                         break;
1875                 }
1876         }
1877         if (i == 4)
1878                 DRM_ERROR("FDI train 2 fail!\n");
1879
1880         DRM_DEBUG_KMS("FDI train done.\n");
1881 }
1882
1883 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1884 {
1885         struct drm_device *dev = crtc->dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888         int pipe = intel_crtc->pipe;
1889         u32 reg, temp;
1890
1891         /* Write the TU size bits so error detection works */
1892         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1893                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1894
1895         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1896         reg = FDI_RX_CTL(pipe);
1897         temp = I915_READ(reg);
1898         temp &= ~((0x7 << 19) | (0x7 << 16));
1899         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1900         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1901         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1902
1903         POSTING_READ(reg);
1904         udelay(200);
1905
1906         /* Switch from Rawclk to PCDclk */
1907         temp = I915_READ(reg);
1908         I915_WRITE(reg, temp | FDI_PCDCLK);
1909
1910         POSTING_READ(reg);
1911         udelay(200);
1912
1913         /* Enable CPU FDI TX PLL, always on for Ironlake */
1914         reg = FDI_TX_CTL(pipe);
1915         temp = I915_READ(reg);
1916         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1917                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1918
1919                 POSTING_READ(reg);
1920                 udelay(100);
1921         }
1922 }
1923
1924 static void intel_flush_display_plane(struct drm_device *dev,
1925                                       int plane)
1926 {
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928         u32 reg = DSPADDR(plane);
1929         I915_WRITE(reg, I915_READ(reg));
1930 }
1931
1932 /*
1933  * When we disable a pipe, we need to clear any pending scanline wait events
1934  * to avoid hanging the ring, which we assume we are waiting on.
1935  */
1936 static void intel_clear_scanline_wait(struct drm_device *dev)
1937 {
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         u32 tmp;
1940
1941         if (IS_GEN2(dev))
1942                 /* Can't break the hang on i8xx */
1943                 return;
1944
1945         tmp = I915_READ(PRB0_CTL);
1946         if (tmp & RING_WAIT) {
1947                 I915_WRITE(PRB0_CTL, tmp);
1948                 POSTING_READ(PRB0_CTL);
1949         }
1950 }
1951
1952 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
1953 {
1954         struct drm_i915_gem_object *obj_priv;
1955         struct drm_i915_private *dev_priv;
1956
1957         if (crtc->fb == NULL)
1958                 return;
1959
1960         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
1961         dev_priv = crtc->dev->dev_private;
1962         wait_event(dev_priv->pending_flip_queue,
1963                    atomic_read(&obj_priv->pending_flip) == 0);
1964 }
1965
1966 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1967 {
1968         struct drm_device *dev = crtc->dev;
1969         struct drm_i915_private *dev_priv = dev->dev_private;
1970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1971         int pipe = intel_crtc->pipe;
1972         int plane = intel_crtc->plane;
1973         u32 reg, temp;
1974
1975         if (intel_crtc->active)
1976                 return;
1977
1978         intel_crtc->active = true;
1979         intel_update_watermarks(dev);
1980
1981         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1982                 temp = I915_READ(PCH_LVDS);
1983                 if ((temp & LVDS_PORT_EN) == 0)
1984                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1985         }
1986
1987         ironlake_fdi_enable(crtc);
1988
1989         /* Enable panel fitting for LVDS */
1990         if (dev_priv->pch_pf_size &&
1991             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1992              || HAS_eDP || intel_pch_has_edp(crtc))) {
1993                 /* Force use of hard-coded filter coefficients
1994                  * as some pre-programmed values are broken,
1995                  * e.g. x201.
1996                  */
1997                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1998                            PF_ENABLE | PF_FILTER_MED_3x3);
1999                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2000                            dev_priv->pch_pf_pos);
2001                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2002                            dev_priv->pch_pf_size);
2003         }
2004
2005         /* Enable CPU pipe */
2006         reg = PIPECONF(pipe);
2007         temp = I915_READ(reg);
2008         if ((temp & PIPECONF_ENABLE) == 0) {
2009                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2010                 POSTING_READ(reg);
2011                 udelay(100);
2012         }
2013
2014         /* configure and enable CPU plane */
2015         reg = DSPCNTR(plane);
2016         temp = I915_READ(reg);
2017         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2018                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2019                 intel_flush_display_plane(dev, plane);
2020         }
2021
2022         /* For PCH output, training FDI link */
2023         if (IS_GEN6(dev))
2024                 gen6_fdi_link_train(crtc);
2025         else
2026                 ironlake_fdi_link_train(crtc);
2027
2028         /* enable PCH DPLL */
2029         reg = PCH_DPLL(pipe);
2030         temp = I915_READ(reg);
2031         if ((temp & DPLL_VCO_ENABLE) == 0) {
2032                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2033                 POSTING_READ(reg);
2034                 udelay(200);
2035         }
2036
2037         if (HAS_PCH_CPT(dev)) {
2038                 /* Be sure PCH DPLL SEL is set */
2039                 temp = I915_READ(PCH_DPLL_SEL);
2040                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2041                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2042                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2043                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2044                 I915_WRITE(PCH_DPLL_SEL, temp);
2045         }
2046
2047         /* set transcoder timing */
2048         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2049         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2050         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2051
2052         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2053         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2054         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2055
2056         /* enable normal train */
2057         reg = FDI_TX_CTL(pipe);
2058         temp = I915_READ(reg);
2059         temp &= ~FDI_LINK_TRAIN_NONE;
2060         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2061         I915_WRITE(reg, temp);
2062
2063         reg = FDI_RX_CTL(pipe);
2064         temp = I915_READ(reg);
2065         if (HAS_PCH_CPT(dev)) {
2066                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2067                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2068         } else {
2069                 temp &= ~FDI_LINK_TRAIN_NONE;
2070                 temp |= FDI_LINK_TRAIN_NONE;
2071         }
2072         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2073
2074         /* wait one idle pattern time */
2075         POSTING_READ(reg);
2076         udelay(100);
2077
2078         /* For PCH DP, enable TRANS_DP_CTL */
2079         if (HAS_PCH_CPT(dev) &&
2080             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2081                 reg = TRANS_DP_CTL(pipe);
2082                 temp = I915_READ(reg);
2083                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2084                           TRANS_DP_SYNC_MASK);
2085                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2086                          TRANS_DP_ENH_FRAMING);
2087
2088                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2089                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2090                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2091                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2092
2093                 switch (intel_trans_dp_port_sel(crtc)) {
2094                 case PCH_DP_B:
2095                         temp |= TRANS_DP_PORT_SEL_B;
2096                         break;
2097                 case PCH_DP_C:
2098                         temp |= TRANS_DP_PORT_SEL_C;
2099                         break;
2100                 case PCH_DP_D:
2101                         temp |= TRANS_DP_PORT_SEL_D;
2102                         break;
2103                 default:
2104                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2105                         temp |= TRANS_DP_PORT_SEL_B;
2106                         break;
2107                 }
2108
2109                 I915_WRITE(reg, temp);
2110         }
2111
2112         /* enable PCH transcoder */
2113         reg = TRANSCONF(pipe);
2114         temp = I915_READ(reg);
2115         /*
2116          * make the BPC in transcoder be consistent with
2117          * that in pipeconf reg.
2118          */
2119         temp &= ~PIPE_BPC_MASK;
2120         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2121         I915_WRITE(reg, temp | TRANS_ENABLE);
2122         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2123                 DRM_ERROR("failed to enable transcoder\n");
2124
2125         intel_crtc_load_lut(crtc);
2126         intel_update_fbc(dev);
2127         intel_crtc_update_cursor(crtc, true);
2128 }
2129
2130 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2131 {
2132         struct drm_device *dev = crtc->dev;
2133         struct drm_i915_private *dev_priv = dev->dev_private;
2134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135         int pipe = intel_crtc->pipe;
2136         int plane = intel_crtc->plane;
2137         u32 reg, temp;
2138
2139         if (!intel_crtc->active)
2140                 return;
2141
2142         intel_crtc_wait_for_pending_flips(crtc);
2143         drm_vblank_off(dev, pipe);
2144         intel_crtc_update_cursor(crtc, false);
2145
2146         /* Disable display plane */
2147         reg = DSPCNTR(plane);
2148         temp = I915_READ(reg);
2149         if (temp & DISPLAY_PLANE_ENABLE) {
2150                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2151                 intel_flush_display_plane(dev, plane);
2152         }
2153
2154         if (dev_priv->cfb_plane == plane &&
2155             dev_priv->display.disable_fbc)
2156                 dev_priv->display.disable_fbc(dev);
2157
2158         /* disable cpu pipe, disable after all planes disabled */
2159         reg = PIPECONF(pipe);
2160         temp = I915_READ(reg);
2161         if (temp & PIPECONF_ENABLE) {
2162                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2163                 /* wait for cpu pipe off, pipe state */
2164                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2165                         DRM_ERROR("failed to turn off cpu pipe\n");
2166         }
2167
2168         /* Disable PF */
2169         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2170         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2171
2172         /* disable CPU FDI tx and PCH FDI rx */
2173         reg = FDI_TX_CTL(pipe);
2174         temp = I915_READ(reg);
2175         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2176         POSTING_READ(reg);
2177
2178         reg = FDI_RX_CTL(pipe);
2179         temp = I915_READ(reg);
2180         temp &= ~(0x7 << 16);
2181         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2182         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2183
2184         POSTING_READ(reg);
2185         udelay(100);
2186
2187         /* still set train pattern 1 */
2188         reg = FDI_TX_CTL(pipe);
2189         temp = I915_READ(reg);
2190         temp &= ~FDI_LINK_TRAIN_NONE;
2191         temp |= FDI_LINK_TRAIN_PATTERN_1;
2192         I915_WRITE(reg, temp);
2193
2194         reg = FDI_RX_CTL(pipe);
2195         temp = I915_READ(reg);
2196         if (HAS_PCH_CPT(dev)) {
2197                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2198                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2199         } else {
2200                 temp &= ~FDI_LINK_TRAIN_NONE;
2201                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2202         }
2203         /* BPC in FDI rx is consistent with that in PIPECONF */
2204         temp &= ~(0x07 << 16);
2205         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2206         I915_WRITE(reg, temp);
2207
2208         POSTING_READ(reg);
2209         udelay(100);
2210
2211         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2212                 temp = I915_READ(PCH_LVDS);
2213                 if (temp & LVDS_PORT_EN) {
2214                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2215                         POSTING_READ(PCH_LVDS);
2216                         udelay(100);
2217                 }
2218         }
2219
2220         /* disable PCH transcoder */
2221         reg = TRANSCONF(plane);
2222         temp = I915_READ(reg);
2223         if (temp & TRANS_ENABLE) {
2224                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2225                 /* wait for PCH transcoder off, transcoder state */
2226                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2227                         DRM_ERROR("failed to disable transcoder\n");
2228         }
2229
2230         if (HAS_PCH_CPT(dev)) {
2231                 /* disable TRANS_DP_CTL */
2232                 reg = TRANS_DP_CTL(pipe);
2233                 temp = I915_READ(reg);
2234                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2235                 I915_WRITE(reg, temp);
2236
2237                 /* disable DPLL_SEL */
2238                 temp = I915_READ(PCH_DPLL_SEL);
2239                 if (pipe == 0)
2240                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2241                 else
2242                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2243                 I915_WRITE(PCH_DPLL_SEL, temp);
2244         }
2245
2246         /* disable PCH DPLL */
2247         reg = PCH_DPLL(pipe);
2248         temp = I915_READ(reg);
2249         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2250
2251         /* Switch from PCDclk to Rawclk */
2252         reg = FDI_RX_CTL(pipe);
2253         temp = I915_READ(reg);
2254         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2255
2256         /* Disable CPU FDI TX PLL */
2257         reg = FDI_TX_CTL(pipe);
2258         temp = I915_READ(reg);
2259         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2260
2261         POSTING_READ(reg);
2262         udelay(100);
2263
2264         reg = FDI_RX_CTL(pipe);
2265         temp = I915_READ(reg);
2266         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2267
2268         /* Wait for the clocks to turn off. */
2269         POSTING_READ(reg);
2270         udelay(100);
2271
2272         intel_crtc->active = false;
2273         intel_update_watermarks(dev);
2274         intel_update_fbc(dev);
2275         intel_clear_scanline_wait(dev);
2276 }
2277
2278 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2279 {
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int pipe = intel_crtc->pipe;
2282         int plane = intel_crtc->plane;
2283
2284         /* XXX: When our outputs are all unaware of DPMS modes other than off
2285          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2286          */
2287         switch (mode) {
2288         case DRM_MODE_DPMS_ON:
2289         case DRM_MODE_DPMS_STANDBY:
2290         case DRM_MODE_DPMS_SUSPEND:
2291                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2292                 ironlake_crtc_enable(crtc);
2293                 break;
2294
2295         case DRM_MODE_DPMS_OFF:
2296                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2297                 ironlake_crtc_disable(crtc);
2298                 break;
2299         }
2300 }
2301
2302 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2303 {
2304         if (!enable && intel_crtc->overlay) {
2305                 struct drm_device *dev = intel_crtc->base.dev;
2306
2307                 mutex_lock(&dev->struct_mutex);
2308                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2309                 mutex_unlock(&dev->struct_mutex);
2310         }
2311
2312         /* Let userspace switch the overlay on again. In most cases userspace
2313          * has to recompute where to put it anyway.
2314          */
2315 }
2316
2317 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2318 {
2319         struct drm_device *dev = crtc->dev;
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2322         int pipe = intel_crtc->pipe;
2323         int plane = intel_crtc->plane;
2324         u32 reg, temp;
2325
2326         if (intel_crtc->active)
2327                 return;
2328
2329         intel_crtc->active = true;
2330         intel_update_watermarks(dev);
2331
2332         /* Enable the DPLL */
2333         reg = DPLL(pipe);
2334         temp = I915_READ(reg);
2335         if ((temp & DPLL_VCO_ENABLE) == 0) {
2336                 I915_WRITE(reg, temp);
2337
2338                 /* Wait for the clocks to stabilize. */
2339                 POSTING_READ(reg);
2340                 udelay(150);
2341
2342                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2343
2344                 /* Wait for the clocks to stabilize. */
2345                 POSTING_READ(reg);
2346                 udelay(150);
2347
2348                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2349
2350                 /* Wait for the clocks to stabilize. */
2351                 POSTING_READ(reg);
2352                 udelay(150);
2353         }
2354
2355         /* Enable the pipe */
2356         reg = PIPECONF(pipe);
2357         temp = I915_READ(reg);
2358         if ((temp & PIPECONF_ENABLE) == 0)
2359                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2360
2361         /* Enable the plane */
2362         reg = DSPCNTR(plane);
2363         temp = I915_READ(reg);
2364         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2365                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2366                 intel_flush_display_plane(dev, plane);
2367         }
2368
2369         intel_crtc_load_lut(crtc);
2370         intel_update_fbc(dev);
2371
2372         /* Give the overlay scaler a chance to enable if it's on this pipe */
2373         intel_crtc_dpms_overlay(intel_crtc, true);
2374         intel_crtc_update_cursor(crtc, true);
2375 }
2376
2377 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2378 {
2379         struct drm_device *dev = crtc->dev;
2380         struct drm_i915_private *dev_priv = dev->dev_private;
2381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382         int pipe = intel_crtc->pipe;
2383         int plane = intel_crtc->plane;
2384         u32 reg, temp;
2385
2386         if (!intel_crtc->active)
2387                 return;
2388
2389         /* Give the overlay scaler a chance to disable if it's on this pipe */
2390         intel_crtc_wait_for_pending_flips(crtc);
2391         drm_vblank_off(dev, pipe);
2392         intel_crtc_dpms_overlay(intel_crtc, false);
2393         intel_crtc_update_cursor(crtc, false);
2394
2395         if (dev_priv->cfb_plane == plane &&
2396             dev_priv->display.disable_fbc)
2397                 dev_priv->display.disable_fbc(dev);
2398
2399         /* Disable display plane */
2400         reg = DSPCNTR(plane);
2401         temp = I915_READ(reg);
2402         if (temp & DISPLAY_PLANE_ENABLE) {
2403                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2404                 /* Flush the plane changes */
2405                 intel_flush_display_plane(dev, plane);
2406
2407                 /* Wait for vblank for the disable to take effect */
2408                 if (IS_GEN2(dev))
2409                         intel_wait_for_vblank_off(dev, pipe);
2410         }
2411
2412         /* Don't disable pipe A or pipe A PLLs if needed */
2413         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2414                 goto done;
2415
2416         /* Next, disable display pipes */
2417         reg = PIPECONF(pipe);
2418         temp = I915_READ(reg);
2419         if (temp & PIPECONF_ENABLE) {
2420                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2421
2422                 /* Wait for vblank for the disable to take effect. */
2423                 POSTING_READ(reg);
2424                 intel_wait_for_vblank_off(dev, pipe);
2425         }
2426
2427         reg = DPLL(pipe);
2428         temp = I915_READ(reg);
2429         if (temp & DPLL_VCO_ENABLE) {
2430                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2431
2432                 /* Wait for the clocks to turn off. */
2433                 POSTING_READ(reg);
2434                 udelay(150);
2435         }
2436
2437 done:
2438         intel_crtc->active = false;
2439         intel_update_fbc(dev);
2440         intel_update_watermarks(dev);
2441         intel_clear_scanline_wait(dev);
2442 }
2443
2444 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2445 {
2446         /* XXX: When our outputs are all unaware of DPMS modes other than off
2447          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2448          */
2449         switch (mode) {
2450         case DRM_MODE_DPMS_ON:
2451         case DRM_MODE_DPMS_STANDBY:
2452         case DRM_MODE_DPMS_SUSPEND:
2453                 i9xx_crtc_enable(crtc);
2454                 break;
2455         case DRM_MODE_DPMS_OFF:
2456                 i9xx_crtc_disable(crtc);
2457                 break;
2458         }
2459 }
2460
2461 /**
2462  * Sets the power management mode of the pipe and plane.
2463  */
2464 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2465 {
2466         struct drm_device *dev = crtc->dev;
2467         struct drm_i915_private *dev_priv = dev->dev_private;
2468         struct drm_i915_master_private *master_priv;
2469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470         int pipe = intel_crtc->pipe;
2471         bool enabled;
2472
2473         if (intel_crtc->dpms_mode == mode)
2474                 return;
2475
2476         intel_crtc->dpms_mode = mode;
2477
2478         dev_priv->display.dpms(crtc, mode);
2479
2480         if (!dev->primary->master)
2481                 return;
2482
2483         master_priv = dev->primary->master->driver_priv;
2484         if (!master_priv->sarea_priv)
2485                 return;
2486
2487         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2488
2489         switch (pipe) {
2490         case 0:
2491                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2492                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2493                 break;
2494         case 1:
2495                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2496                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2497                 break;
2498         default:
2499                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2500                 break;
2501         }
2502 }
2503
2504 static void intel_crtc_disable(struct drm_crtc *crtc)
2505 {
2506         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2507         struct drm_device *dev = crtc->dev;
2508
2509         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2510
2511         if (crtc->fb) {
2512                 mutex_lock(&dev->struct_mutex);
2513                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2514                 mutex_unlock(&dev->struct_mutex);
2515         }
2516 }
2517
2518 /* Prepare for a mode set.
2519  *
2520  * Note we could be a lot smarter here.  We need to figure out which outputs
2521  * will be enabled, which disabled (in short, how the config will changes)
2522  * and perform the minimum necessary steps to accomplish that, e.g. updating
2523  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2524  * panel fitting is in the proper state, etc.
2525  */
2526 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2527 {
2528         i9xx_crtc_disable(crtc);
2529 }
2530
2531 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2532 {
2533         i9xx_crtc_enable(crtc);
2534 }
2535
2536 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2537 {
2538         ironlake_crtc_disable(crtc);
2539 }
2540
2541 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2542 {
2543         ironlake_crtc_enable(crtc);
2544 }
2545
2546 void intel_encoder_prepare (struct drm_encoder *encoder)
2547 {
2548         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2549         /* lvds has its own version of prepare see intel_lvds_prepare */
2550         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2551 }
2552
2553 void intel_encoder_commit (struct drm_encoder *encoder)
2554 {
2555         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2556         /* lvds has its own version of commit see intel_lvds_commit */
2557         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2558 }
2559
2560 void intel_encoder_destroy(struct drm_encoder *encoder)
2561 {
2562         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2563
2564         drm_encoder_cleanup(encoder);
2565         kfree(intel_encoder);
2566 }
2567
2568 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2569                                   struct drm_display_mode *mode,
2570                                   struct drm_display_mode *adjusted_mode)
2571 {
2572         struct drm_device *dev = crtc->dev;
2573
2574         if (HAS_PCH_SPLIT(dev)) {
2575                 /* FDI link clock is fixed at 2.7G */
2576                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2577                         return false;
2578         }
2579
2580         /* XXX some encoders set the crtcinfo, others don't.
2581          * Obviously we need some form of conflict resolution here...
2582          */
2583         if (adjusted_mode->crtc_htotal == 0)
2584                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2585
2586         return true;
2587 }
2588
2589 static int i945_get_display_clock_speed(struct drm_device *dev)
2590 {
2591         return 400000;
2592 }
2593
2594 static int i915_get_display_clock_speed(struct drm_device *dev)
2595 {
2596         return 333000;
2597 }
2598
2599 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2600 {
2601         return 200000;
2602 }
2603
2604 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2605 {
2606         u16 gcfgc = 0;
2607
2608         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2609
2610         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2611                 return 133000;
2612         else {
2613                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2614                 case GC_DISPLAY_CLOCK_333_MHZ:
2615                         return 333000;
2616                 default:
2617                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2618                         return 190000;
2619                 }
2620         }
2621 }
2622
2623 static int i865_get_display_clock_speed(struct drm_device *dev)
2624 {
2625         return 266000;
2626 }
2627
2628 static int i855_get_display_clock_speed(struct drm_device *dev)
2629 {
2630         u16 hpllcc = 0;
2631         /* Assume that the hardware is in the high speed state.  This
2632          * should be the default.
2633          */
2634         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2635         case GC_CLOCK_133_200:
2636         case GC_CLOCK_100_200:
2637                 return 200000;
2638         case GC_CLOCK_166_250:
2639                 return 250000;
2640         case GC_CLOCK_100_133:
2641                 return 133000;
2642         }
2643
2644         /* Shouldn't happen */
2645         return 0;
2646 }
2647
2648 static int i830_get_display_clock_speed(struct drm_device *dev)
2649 {
2650         return 133000;
2651 }
2652
2653 struct fdi_m_n {
2654         u32        tu;
2655         u32        gmch_m;
2656         u32        gmch_n;
2657         u32        link_m;
2658         u32        link_n;
2659 };
2660
2661 static void
2662 fdi_reduce_ratio(u32 *num, u32 *den)
2663 {
2664         while (*num > 0xffffff || *den > 0xffffff) {
2665                 *num >>= 1;
2666                 *den >>= 1;
2667         }
2668 }
2669
2670 #define DATA_N 0x800000
2671 #define LINK_N 0x80000
2672
2673 static void
2674 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2675                      int link_clock, struct fdi_m_n *m_n)
2676 {
2677         u64 temp;
2678
2679         m_n->tu = 64; /* default size */
2680
2681         temp = (u64) DATA_N * pixel_clock;
2682         temp = div_u64(temp, link_clock);
2683         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2684         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2685         m_n->gmch_n = DATA_N;
2686         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2687
2688         temp = (u64) LINK_N * pixel_clock;
2689         m_n->link_m = div_u64(temp, link_clock);
2690         m_n->link_n = LINK_N;
2691         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2692 }
2693
2694
2695 struct intel_watermark_params {
2696         unsigned long fifo_size;
2697         unsigned long max_wm;
2698         unsigned long default_wm;
2699         unsigned long guard_size;
2700         unsigned long cacheline_size;
2701 };
2702
2703 /* Pineview has different values for various configs */
2704 static struct intel_watermark_params pineview_display_wm = {
2705         PINEVIEW_DISPLAY_FIFO,
2706         PINEVIEW_MAX_WM,
2707         PINEVIEW_DFT_WM,
2708         PINEVIEW_GUARD_WM,
2709         PINEVIEW_FIFO_LINE_SIZE
2710 };
2711 static struct intel_watermark_params pineview_display_hplloff_wm = {
2712         PINEVIEW_DISPLAY_FIFO,
2713         PINEVIEW_MAX_WM,
2714         PINEVIEW_DFT_HPLLOFF_WM,
2715         PINEVIEW_GUARD_WM,
2716         PINEVIEW_FIFO_LINE_SIZE
2717 };
2718 static struct intel_watermark_params pineview_cursor_wm = {
2719         PINEVIEW_CURSOR_FIFO,
2720         PINEVIEW_CURSOR_MAX_WM,
2721         PINEVIEW_CURSOR_DFT_WM,
2722         PINEVIEW_CURSOR_GUARD_WM,
2723         PINEVIEW_FIFO_LINE_SIZE,
2724 };
2725 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2726         PINEVIEW_CURSOR_FIFO,
2727         PINEVIEW_CURSOR_MAX_WM,
2728         PINEVIEW_CURSOR_DFT_WM,
2729         PINEVIEW_CURSOR_GUARD_WM,
2730         PINEVIEW_FIFO_LINE_SIZE
2731 };
2732 static struct intel_watermark_params g4x_wm_info = {
2733         G4X_FIFO_SIZE,
2734         G4X_MAX_WM,
2735         G4X_MAX_WM,
2736         2,
2737         G4X_FIFO_LINE_SIZE,
2738 };
2739 static struct intel_watermark_params g4x_cursor_wm_info = {
2740         I965_CURSOR_FIFO,
2741         I965_CURSOR_MAX_WM,
2742         I965_CURSOR_DFT_WM,
2743         2,
2744         G4X_FIFO_LINE_SIZE,
2745 };
2746 static struct intel_watermark_params i965_cursor_wm_info = {
2747         I965_CURSOR_FIFO,
2748         I965_CURSOR_MAX_WM,
2749         I965_CURSOR_DFT_WM,
2750         2,
2751         I915_FIFO_LINE_SIZE,
2752 };
2753 static struct intel_watermark_params i945_wm_info = {
2754         I945_FIFO_SIZE,
2755         I915_MAX_WM,
2756         1,
2757         2,
2758         I915_FIFO_LINE_SIZE
2759 };
2760 static struct intel_watermark_params i915_wm_info = {
2761         I915_FIFO_SIZE,
2762         I915_MAX_WM,
2763         1,
2764         2,
2765         I915_FIFO_LINE_SIZE
2766 };
2767 static struct intel_watermark_params i855_wm_info = {
2768         I855GM_FIFO_SIZE,
2769         I915_MAX_WM,
2770         1,
2771         2,
2772         I830_FIFO_LINE_SIZE
2773 };
2774 static struct intel_watermark_params i830_wm_info = {
2775         I830_FIFO_SIZE,
2776         I915_MAX_WM,
2777         1,
2778         2,
2779         I830_FIFO_LINE_SIZE
2780 };
2781
2782 static struct intel_watermark_params ironlake_display_wm_info = {
2783         ILK_DISPLAY_FIFO,
2784         ILK_DISPLAY_MAXWM,
2785         ILK_DISPLAY_DFTWM,
2786         2,
2787         ILK_FIFO_LINE_SIZE
2788 };
2789
2790 static struct intel_watermark_params ironlake_cursor_wm_info = {
2791         ILK_CURSOR_FIFO,
2792         ILK_CURSOR_MAXWM,
2793         ILK_CURSOR_DFTWM,
2794         2,
2795         ILK_FIFO_LINE_SIZE
2796 };
2797
2798 static struct intel_watermark_params ironlake_display_srwm_info = {
2799         ILK_DISPLAY_SR_FIFO,
2800         ILK_DISPLAY_MAX_SRWM,
2801         ILK_DISPLAY_DFT_SRWM,
2802         2,
2803         ILK_FIFO_LINE_SIZE
2804 };
2805
2806 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2807         ILK_CURSOR_SR_FIFO,
2808         ILK_CURSOR_MAX_SRWM,
2809         ILK_CURSOR_DFT_SRWM,
2810         2,
2811         ILK_FIFO_LINE_SIZE
2812 };
2813
2814 /**
2815  * intel_calculate_wm - calculate watermark level
2816  * @clock_in_khz: pixel clock
2817  * @wm: chip FIFO params
2818  * @pixel_size: display pixel size
2819  * @latency_ns: memory latency for the platform
2820  *
2821  * Calculate the watermark level (the level at which the display plane will
2822  * start fetching from memory again).  Each chip has a different display
2823  * FIFO size and allocation, so the caller needs to figure that out and pass
2824  * in the correct intel_watermark_params structure.
2825  *
2826  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2827  * on the pixel size.  When it reaches the watermark level, it'll start
2828  * fetching FIFO line sized based chunks from memory until the FIFO fills
2829  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2830  * will occur, and a display engine hang could result.
2831  */
2832 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2833                                         struct intel_watermark_params *wm,
2834                                         int pixel_size,
2835                                         unsigned long latency_ns)
2836 {
2837         long entries_required, wm_size;
2838
2839         /*
2840          * Note: we need to make sure we don't overflow for various clock &
2841          * latency values.
2842          * clocks go from a few thousand to several hundred thousand.
2843          * latency is usually a few thousand
2844          */
2845         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2846                 1000;
2847         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2848
2849         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2850
2851         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2852
2853         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2854
2855         /* Don't promote wm_size to unsigned... */
2856         if (wm_size > (long)wm->max_wm)
2857                 wm_size = wm->max_wm;
2858         if (wm_size <= 0)
2859                 wm_size = wm->default_wm;
2860         return wm_size;
2861 }
2862
2863 struct cxsr_latency {
2864         int is_desktop;
2865         int is_ddr3;
2866         unsigned long fsb_freq;
2867         unsigned long mem_freq;
2868         unsigned long display_sr;
2869         unsigned long display_hpll_disable;
2870         unsigned long cursor_sr;
2871         unsigned long cursor_hpll_disable;
2872 };
2873
2874 static const struct cxsr_latency cxsr_latency_table[] = {
2875         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2876         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2877         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2878         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2879         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2880
2881         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2882         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2883         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2884         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2885         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2886
2887         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2888         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2889         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2890         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2891         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2892
2893         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2894         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2895         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2896         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2897         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2898
2899         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2900         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2901         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2902         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2903         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2904
2905         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2906         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2907         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2908         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2909         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2910 };
2911
2912 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2913                                                          int is_ddr3,
2914                                                          int fsb,
2915                                                          int mem)
2916 {
2917         const struct cxsr_latency *latency;
2918         int i;
2919
2920         if (fsb == 0 || mem == 0)
2921                 return NULL;
2922
2923         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2924                 latency = &cxsr_latency_table[i];
2925                 if (is_desktop == latency->is_desktop &&
2926                     is_ddr3 == latency->is_ddr3 &&
2927                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2928                         return latency;
2929         }
2930
2931         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2932
2933         return NULL;
2934 }
2935
2936 static void pineview_disable_cxsr(struct drm_device *dev)
2937 {
2938         struct drm_i915_private *dev_priv = dev->dev_private;
2939
2940         /* deactivate cxsr */
2941         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2942 }
2943
2944 /*
2945  * Latency for FIFO fetches is dependent on several factors:
2946  *   - memory configuration (speed, channels)
2947  *   - chipset
2948  *   - current MCH state
2949  * It can be fairly high in some situations, so here we assume a fairly
2950  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2951  * set this value too high, the FIFO will fetch frequently to stay full)
2952  * and power consumption (set it too low to save power and we might see
2953  * FIFO underruns and display "flicker").
2954  *
2955  * A value of 5us seems to be a good balance; safe for very low end
2956  * platforms but not overly aggressive on lower latency configs.
2957  */
2958 static const int latency_ns = 5000;
2959
2960 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2961 {
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         uint32_t dsparb = I915_READ(DSPARB);
2964         int size;
2965
2966         size = dsparb & 0x7f;
2967         if (plane)
2968                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2969
2970         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2971                       plane ? "B" : "A", size);
2972
2973         return size;
2974 }
2975
2976 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2977 {
2978         struct drm_i915_private *dev_priv = dev->dev_private;
2979         uint32_t dsparb = I915_READ(DSPARB);
2980         int size;
2981
2982         size = dsparb & 0x1ff;
2983         if (plane)
2984                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2985         size >>= 1; /* Convert to cachelines */
2986
2987         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2988                       plane ? "B" : "A", size);
2989
2990         return size;
2991 }
2992
2993 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         uint32_t dsparb = I915_READ(DSPARB);
2997         int size;
2998
2999         size = dsparb & 0x7f;
3000         size >>= 2; /* Convert to cachelines */
3001
3002         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3003                       plane ? "B" : "A",
3004                       size);
3005
3006         return size;
3007 }
3008
3009 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3010 {
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         uint32_t dsparb = I915_READ(DSPARB);
3013         int size;
3014
3015         size = dsparb & 0x7f;
3016         size >>= 1; /* Convert to cachelines */
3017
3018         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3019                       plane ? "B" : "A", size);
3020
3021         return size;
3022 }
3023
3024 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3025                                int planeb_clock, int sr_hdisplay, int unused,
3026                                int pixel_size)
3027 {
3028         struct drm_i915_private *dev_priv = dev->dev_private;
3029         const struct cxsr_latency *latency;
3030         u32 reg;
3031         unsigned long wm;
3032         int sr_clock;
3033
3034         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3035                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3036         if (!latency) {
3037                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3038                 pineview_disable_cxsr(dev);
3039                 return;
3040         }
3041
3042         if (!planea_clock || !planeb_clock) {
3043                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3044
3045                 /* Display SR */
3046                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3047                                         pixel_size, latency->display_sr);
3048                 reg = I915_READ(DSPFW1);
3049                 reg &= ~DSPFW_SR_MASK;
3050                 reg |= wm << DSPFW_SR_SHIFT;
3051                 I915_WRITE(DSPFW1, reg);
3052                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3053
3054                 /* cursor SR */
3055                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3056                                         pixel_size, latency->cursor_sr);
3057                 reg = I915_READ(DSPFW3);
3058                 reg &= ~DSPFW_CURSOR_SR_MASK;
3059                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3060                 I915_WRITE(DSPFW3, reg);
3061
3062                 /* Display HPLL off SR */
3063                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3064                                         pixel_size, latency->display_hpll_disable);
3065                 reg = I915_READ(DSPFW3);
3066                 reg &= ~DSPFW_HPLL_SR_MASK;
3067                 reg |= wm & DSPFW_HPLL_SR_MASK;
3068                 I915_WRITE(DSPFW3, reg);
3069
3070                 /* cursor HPLL off SR */
3071                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3072                                         pixel_size, latency->cursor_hpll_disable);
3073                 reg = I915_READ(DSPFW3);
3074                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3075                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3076                 I915_WRITE(DSPFW3, reg);
3077                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3078
3079                 /* activate cxsr */
3080                 I915_WRITE(DSPFW3,
3081                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3082                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3083         } else {
3084                 pineview_disable_cxsr(dev);
3085                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3086         }
3087 }
3088
3089 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3090                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3091                           int pixel_size)
3092 {
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094         int total_size, cacheline_size;
3095         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3096         struct intel_watermark_params planea_params, planeb_params;
3097         unsigned long line_time_us;
3098         int sr_clock, sr_entries = 0, entries_required;
3099
3100         /* Create copies of the base settings for each pipe */
3101         planea_params = planeb_params = g4x_wm_info;
3102
3103         /* Grab a couple of global values before we overwrite them */
3104         total_size = planea_params.fifo_size;
3105         cacheline_size = planea_params.cacheline_size;
3106
3107         /*
3108          * Note: we need to make sure we don't overflow for various clock &
3109          * latency values.
3110          * clocks go from a few thousand to several hundred thousand.
3111          * latency is usually a few thousand
3112          */
3113         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3114                 1000;
3115         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3116         planea_wm = entries_required + planea_params.guard_size;
3117
3118         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3119                 1000;
3120         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3121         planeb_wm = entries_required + planeb_params.guard_size;
3122
3123         cursora_wm = cursorb_wm = 16;
3124         cursor_sr = 32;
3125
3126         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3127
3128         /* Calc sr entries for one plane configs */
3129         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3130                 /* self-refresh has much higher latency */
3131                 static const int sr_latency_ns = 12000;
3132
3133                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3134                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3135
3136                 /* Use ns/us then divide to preserve precision */
3137                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3138                         pixel_size * sr_hdisplay;
3139                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3140
3141                 entries_required = (((sr_latency_ns / line_time_us) +
3142                                      1000) / 1000) * pixel_size * 64;
3143                 entries_required = DIV_ROUND_UP(entries_required,
3144                                                 g4x_cursor_wm_info.cacheline_size);
3145                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3146
3147                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3148                         cursor_sr = g4x_cursor_wm_info.max_wm;
3149                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3150                               "cursor %d\n", sr_entries, cursor_sr);
3151
3152                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3153         } else {
3154                 /* Turn off self refresh if both pipes are enabled */
3155                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3156                            & ~FW_BLC_SELF_EN);
3157         }
3158
3159         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3160                   planea_wm, planeb_wm, sr_entries);
3161
3162         planea_wm &= 0x3f;
3163         planeb_wm &= 0x3f;
3164
3165         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3166                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3167                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3168         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3169                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3170         /* HPLL off in SR has some issues on G4x... disable it */
3171         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3172                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3173 }
3174
3175 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3176                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3177                            int pixel_size)
3178 {
3179         struct drm_i915_private *dev_priv = dev->dev_private;
3180         unsigned long line_time_us;
3181         int sr_clock, sr_entries, srwm = 1;
3182         int cursor_sr = 16;
3183
3184         /* Calc sr entries for one plane configs */
3185         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3186                 /* self-refresh has much higher latency */
3187                 static const int sr_latency_ns = 12000;
3188
3189                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3190                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3191
3192                 /* Use ns/us then divide to preserve precision */
3193                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3194                         pixel_size * sr_hdisplay;
3195                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3196                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3197                 srwm = I965_FIFO_SIZE - sr_entries;
3198                 if (srwm < 0)
3199                         srwm = 1;
3200                 srwm &= 0x1ff;
3201
3202                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3203                         pixel_size * 64;
3204                 sr_entries = DIV_ROUND_UP(sr_entries,
3205                                           i965_cursor_wm_info.cacheline_size);
3206                 cursor_sr = i965_cursor_wm_info.fifo_size -
3207                         (sr_entries + i965_cursor_wm_info.guard_size);
3208
3209                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3210                         cursor_sr = i965_cursor_wm_info.max_wm;
3211
3212                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3213                               "cursor %d\n", srwm, cursor_sr);
3214
3215                 if (IS_CRESTLINE(dev))
3216                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3217         } else {
3218                 /* Turn off self refresh if both pipes are enabled */
3219                 if (IS_CRESTLINE(dev))
3220                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3221                                    & ~FW_BLC_SELF_EN);
3222         }
3223
3224         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3225                       srwm);
3226
3227         /* 965 has limitations... */
3228         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3229                    (8 << 0));
3230         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3231         /* update cursor SR watermark */
3232         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3233 }
3234
3235 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3236                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3237                            int pixel_size)
3238 {
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         uint32_t fwater_lo;
3241         uint32_t fwater_hi;
3242         int total_size, cacheline_size, cwm, srwm = 1;
3243         int planea_wm, planeb_wm;
3244         struct intel_watermark_params planea_params, planeb_params;
3245         unsigned long line_time_us;
3246         int sr_clock, sr_entries = 0;
3247
3248         /* Create copies of the base settings for each pipe */
3249         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3250                 planea_params = planeb_params = i945_wm_info;
3251         else if (!IS_GEN2(dev))
3252                 planea_params = planeb_params = i915_wm_info;
3253         else
3254                 planea_params = planeb_params = i855_wm_info;
3255
3256         /* Grab a couple of global values before we overwrite them */
3257         total_size = planea_params.fifo_size;
3258         cacheline_size = planea_params.cacheline_size;
3259
3260         /* Update per-plane FIFO sizes */
3261         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3262         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3263
3264         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3265                                        pixel_size, latency_ns);
3266         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3267                                        pixel_size, latency_ns);
3268         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3269
3270         /*
3271          * Overlay gets an aggressive default since video jitter is bad.
3272          */
3273         cwm = 2;
3274
3275         /* Calc sr entries for one plane configs */
3276         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3277             (!planea_clock || !planeb_clock)) {
3278                 /* self-refresh has much higher latency */
3279                 static const int sr_latency_ns = 6000;
3280
3281                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3282                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3283
3284                 /* Use ns/us then divide to preserve precision */
3285                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3286                         pixel_size * sr_hdisplay;
3287                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3288                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3289                 srwm = total_size - sr_entries;
3290                 if (srwm < 0)
3291                         srwm = 1;
3292
3293                 if (IS_I945G(dev) || IS_I945GM(dev))
3294                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3295                 else if (IS_I915GM(dev)) {
3296                         /* 915M has a smaller SRWM field */
3297                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3298                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3299                 }
3300         } else {
3301                 /* Turn off self refresh if both pipes are enabled */
3302                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3303                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3304                                    & ~FW_BLC_SELF_EN);
3305                 } else if (IS_I915GM(dev)) {
3306                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3307                 }
3308         }
3309
3310         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3311                       planea_wm, planeb_wm, cwm, srwm);
3312
3313         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3314         fwater_hi = (cwm & 0x1f);
3315
3316         /* Set request length to 8 cachelines per fetch */
3317         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3318         fwater_hi = fwater_hi | (1 << 8);
3319
3320         I915_WRITE(FW_BLC, fwater_lo);
3321         I915_WRITE(FW_BLC2, fwater_hi);
3322 }
3323
3324 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3325                            int unused2, int unused3, int pixel_size)
3326 {
3327         struct drm_i915_private *dev_priv = dev->dev_private;
3328         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3329         int planea_wm;
3330
3331         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3332
3333         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3334                                        pixel_size, latency_ns);
3335         fwater_lo |= (3<<8) | planea_wm;
3336
3337         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3338
3339         I915_WRITE(FW_BLC, fwater_lo);
3340 }
3341
3342 #define ILK_LP0_PLANE_LATENCY           700
3343 #define ILK_LP0_CURSOR_LATENCY          1300
3344
3345 static bool ironlake_compute_wm0(struct drm_device *dev,
3346                                  int pipe,
3347                                  int *plane_wm,
3348                                  int *cursor_wm)
3349 {
3350         struct drm_crtc *crtc;
3351         int htotal, hdisplay, clock, pixel_size = 0;
3352         int line_time_us, line_count, entries;
3353
3354         crtc = intel_get_crtc_for_pipe(dev, pipe);
3355         if (crtc->fb == NULL || !crtc->enabled)
3356                 return false;
3357
3358         htotal = crtc->mode.htotal;
3359         hdisplay = crtc->mode.hdisplay;
3360         clock = crtc->mode.clock;
3361         pixel_size = crtc->fb->bits_per_pixel / 8;
3362
3363         /* Use the small buffer method to calculate plane watermark */
3364         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3365         entries = DIV_ROUND_UP(entries,
3366                                ironlake_display_wm_info.cacheline_size);
3367         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3368         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3369                 *plane_wm = ironlake_display_wm_info.max_wm;
3370
3371         /* Use the large buffer method to calculate cursor watermark */
3372         line_time_us = ((htotal * 1000) / clock);
3373         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3374         entries = line_count * 64 * pixel_size;
3375         entries = DIV_ROUND_UP(entries,
3376                                ironlake_cursor_wm_info.cacheline_size);
3377         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3378         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3379                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3380
3381         return true;
3382 }
3383
3384 static void ironlake_update_wm(struct drm_device *dev,
3385                                int planea_clock, int planeb_clock,
3386                                int sr_hdisplay, int sr_htotal,
3387                                int pixel_size)
3388 {
3389         struct drm_i915_private *dev_priv = dev->dev_private;
3390         int plane_wm, cursor_wm, enabled;
3391         int tmp;
3392
3393         enabled = 0;
3394         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3395                 I915_WRITE(WM0_PIPEA_ILK,
3396                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3397                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3398                               " plane %d, " "cursor: %d\n",
3399                               plane_wm, cursor_wm);
3400                 enabled++;
3401         }
3402
3403         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3404                 I915_WRITE(WM0_PIPEB_ILK,
3405                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3406                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3407                               " plane %d, cursor: %d\n",
3408                               plane_wm, cursor_wm);
3409                 enabled++;
3410         }
3411
3412         /*
3413          * Calculate and update the self-refresh watermark only when one
3414          * display plane is used.
3415          */
3416         tmp = 0;
3417         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3418                 unsigned long line_time_us;
3419                 int small, large, plane_fbc;
3420                 int sr_clock, entries;
3421                 int line_count, line_size;
3422                 /* Read the self-refresh latency. The unit is 0.5us */
3423                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3424
3425                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3426                 line_time_us = (sr_htotal * 1000) / sr_clock;
3427
3428                 /* Use ns/us then divide to preserve precision */
3429                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3430                         / 1000;
3431                 line_size = sr_hdisplay * pixel_size;
3432
3433                 /* Use the minimum of the small and large buffer method for primary */
3434                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3435                 large = line_count * line_size;
3436
3437                 entries = DIV_ROUND_UP(min(small, large),
3438                                        ironlake_display_srwm_info.cacheline_size);
3439
3440                 plane_fbc = entries * 64;
3441                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3442
3443                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3444                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3445                         plane_wm = ironlake_display_srwm_info.max_wm;
3446
3447                 /* calculate the self-refresh watermark for display cursor */
3448                 entries = line_count * pixel_size * 64;
3449                 entries = DIV_ROUND_UP(entries,
3450                                        ironlake_cursor_srwm_info.cacheline_size);
3451
3452                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3453                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3454                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3455
3456                 /* configure watermark and enable self-refresh */
3457                 tmp = (WM1_LP_SR_EN |
3458                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3459                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3460                        (plane_wm << WM1_LP_SR_SHIFT) |
3461                        cursor_wm);
3462                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3463                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3464         }
3465         I915_WRITE(WM1_LP_ILK, tmp);
3466         /* XXX setup WM2 and WM3 */
3467 }
3468
3469 /**
3470  * intel_update_watermarks - update FIFO watermark values based on current modes
3471  *
3472  * Calculate watermark values for the various WM regs based on current mode
3473  * and plane configuration.
3474  *
3475  * There are several cases to deal with here:
3476  *   - normal (i.e. non-self-refresh)
3477  *   - self-refresh (SR) mode
3478  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3479  *   - lines are small relative to FIFO size (buffer can hold more than 2
3480  *     lines), so need to account for TLB latency
3481  *
3482  *   The normal calculation is:
3483  *     watermark = dotclock * bytes per pixel * latency
3484  *   where latency is platform & configuration dependent (we assume pessimal
3485  *   values here).
3486  *
3487  *   The SR calculation is:
3488  *     watermark = (trunc(latency/line time)+1) * surface width *
3489  *       bytes per pixel
3490  *   where
3491  *     line time = htotal / dotclock
3492  *     surface width = hdisplay for normal plane and 64 for cursor
3493  *   and latency is assumed to be high, as above.
3494  *
3495  * The final value programmed to the register should always be rounded up,
3496  * and include an extra 2 entries to account for clock crossings.
3497  *
3498  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3499  * to set the non-SR watermarks to 8.
3500  */
3501 static void intel_update_watermarks(struct drm_device *dev)
3502 {
3503         struct drm_i915_private *dev_priv = dev->dev_private;
3504         struct drm_crtc *crtc;
3505         int sr_hdisplay = 0;
3506         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3507         int enabled = 0, pixel_size = 0;
3508         int sr_htotal = 0;
3509
3510         if (!dev_priv->display.update_wm)
3511                 return;
3512
3513         /* Get the clock config from both planes */
3514         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3515                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516                 if (intel_crtc->active) {
3517                         enabled++;
3518                         if (intel_crtc->plane == 0) {
3519                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3520                                               intel_crtc->pipe, crtc->mode.clock);
3521                                 planea_clock = crtc->mode.clock;
3522                         } else {
3523                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3524                                               intel_crtc->pipe, crtc->mode.clock);
3525                                 planeb_clock = crtc->mode.clock;
3526                         }
3527                         sr_hdisplay = crtc->mode.hdisplay;
3528                         sr_clock = crtc->mode.clock;
3529                         sr_htotal = crtc->mode.htotal;
3530                         if (crtc->fb)
3531                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3532                         else
3533                                 pixel_size = 4; /* by default */
3534                 }
3535         }
3536
3537         if (enabled <= 0)
3538                 return;
3539
3540         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3541                                     sr_hdisplay, sr_htotal, pixel_size);
3542 }
3543
3544 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3545                                struct drm_display_mode *mode,
3546                                struct drm_display_mode *adjusted_mode,
3547                                int x, int y,
3548                                struct drm_framebuffer *old_fb)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         int pipe = intel_crtc->pipe;
3554         int plane = intel_crtc->plane;
3555         u32 fp_reg, dpll_reg;
3556         int refclk, num_connectors = 0;
3557         intel_clock_t clock, reduced_clock;
3558         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3559         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3560         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3561         struct intel_encoder *has_edp_encoder = NULL;
3562         struct drm_mode_config *mode_config = &dev->mode_config;
3563         struct intel_encoder *encoder;
3564         const intel_limit_t *limit;
3565         int ret;
3566         struct fdi_m_n m_n = {0};
3567         u32 reg, temp;
3568         int target_clock;
3569
3570         drm_vblank_pre_modeset(dev, pipe);
3571
3572         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3573                 if (encoder->base.crtc != crtc)
3574                         continue;
3575
3576                 switch (encoder->type) {
3577                 case INTEL_OUTPUT_LVDS:
3578                         is_lvds = true;
3579                         break;
3580                 case INTEL_OUTPUT_SDVO:
3581                 case INTEL_OUTPUT_HDMI:
3582                         is_sdvo = true;
3583                         if (encoder->needs_tv_clock)
3584                                 is_tv = true;
3585                         break;
3586                 case INTEL_OUTPUT_DVO:
3587                         is_dvo = true;
3588                         break;
3589                 case INTEL_OUTPUT_TVOUT:
3590                         is_tv = true;
3591                         break;
3592                 case INTEL_OUTPUT_ANALOG:
3593                         is_crt = true;
3594                         break;
3595                 case INTEL_OUTPUT_DISPLAYPORT:
3596                         is_dp = true;
3597                         break;
3598                 case INTEL_OUTPUT_EDP:
3599                         has_edp_encoder = encoder;
3600                         break;
3601                 }
3602
3603                 num_connectors++;
3604         }
3605
3606         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3607                 refclk = dev_priv->lvds_ssc_freq * 1000;
3608                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3609                               refclk / 1000);
3610         } else if (!IS_GEN2(dev)) {
3611                 refclk = 96000;
3612                 if (HAS_PCH_SPLIT(dev))
3613                         refclk = 120000; /* 120Mhz refclk */
3614         } else {
3615                 refclk = 48000;
3616         }
3617
3618         /*
3619          * Returns a set of divisors for the desired target clock with the given
3620          * refclk, or FALSE.  The returned values represent the clock equation:
3621          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3622          */
3623         limit = intel_limit(crtc);
3624         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3625         if (!ok) {
3626                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3627                 drm_vblank_post_modeset(dev, pipe);
3628                 return -EINVAL;
3629         }
3630
3631         /* Ensure that the cursor is valid for the new mode before changing... */
3632         intel_crtc_update_cursor(crtc, true);
3633
3634         if (is_lvds && dev_priv->lvds_downclock_avail) {
3635                 has_reduced_clock = limit->find_pll(limit, crtc,
3636                                                     dev_priv->lvds_downclock,
3637                                                     refclk,
3638                                                     &reduced_clock);
3639                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3640                         /*
3641                          * If the different P is found, it means that we can't
3642                          * switch the display clock by using the FP0/FP1.
3643                          * In such case we will disable the LVDS downclock
3644                          * feature.
3645                          */
3646                         DRM_DEBUG_KMS("Different P is found for "
3647                                       "LVDS clock/downclock\n");
3648                         has_reduced_clock = 0;
3649                 }
3650         }
3651         /* SDVO TV has fixed PLL values depend on its clock range,
3652            this mirrors vbios setting. */
3653         if (is_sdvo && is_tv) {
3654                 if (adjusted_mode->clock >= 100000
3655                     && adjusted_mode->clock < 140500) {
3656                         clock.p1 = 2;
3657                         clock.p2 = 10;
3658                         clock.n = 3;
3659                         clock.m1 = 16;
3660                         clock.m2 = 8;
3661                 } else if (adjusted_mode->clock >= 140500
3662                            && adjusted_mode->clock <= 200000) {
3663                         clock.p1 = 1;
3664                         clock.p2 = 10;
3665                         clock.n = 6;
3666                         clock.m1 = 12;
3667                         clock.m2 = 8;
3668                 }
3669         }
3670
3671         /* FDI link */
3672         if (HAS_PCH_SPLIT(dev)) {
3673                 int lane = 0, link_bw, bpp;
3674                 /* eDP doesn't require FDI link, so just set DP M/N
3675                    according to current link config */
3676                 if (has_edp_encoder) {
3677                         target_clock = mode->clock;
3678                         intel_edp_link_config(has_edp_encoder,
3679                                               &lane, &link_bw);
3680                 } else {
3681                         /* DP over FDI requires target mode clock
3682                            instead of link clock */
3683                         if (is_dp)
3684                                 target_clock = mode->clock;
3685                         else
3686                                 target_clock = adjusted_mode->clock;
3687
3688                         /* FDI is a binary signal running at ~2.7GHz, encoding
3689                          * each output octet as 10 bits. The actual frequency
3690                          * is stored as a divider into a 100MHz clock, and the
3691                          * mode pixel clock is stored in units of 1KHz.
3692                          * Hence the bw of each lane in terms of the mode signal
3693                          * is:
3694                          */
3695                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3696                 }
3697
3698                 /* determine panel color depth */
3699                 temp = I915_READ(PIPECONF(pipe));
3700                 temp &= ~PIPE_BPC_MASK;
3701                 if (is_lvds) {
3702                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3703                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3704                                 temp |= PIPE_8BPC;
3705                         else
3706                                 temp |= PIPE_6BPC;
3707                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3708                         switch (dev_priv->edp.bpp/3) {
3709                         case 8:
3710                                 temp |= PIPE_8BPC;
3711                                 break;
3712                         case 10:
3713                                 temp |= PIPE_10BPC;
3714                                 break;
3715                         case 6:
3716                                 temp |= PIPE_6BPC;
3717                                 break;
3718                         case 12:
3719                                 temp |= PIPE_12BPC;
3720                                 break;
3721                         }
3722                 } else
3723                         temp |= PIPE_8BPC;
3724                 I915_WRITE(PIPECONF(pipe), temp);
3725
3726                 switch (temp & PIPE_BPC_MASK) {
3727                 case PIPE_8BPC:
3728                         bpp = 24;
3729                         break;
3730                 case PIPE_10BPC:
3731                         bpp = 30;
3732                         break;
3733                 case PIPE_6BPC:
3734                         bpp = 18;
3735                         break;
3736                 case PIPE_12BPC:
3737                         bpp = 36;
3738                         break;
3739                 default:
3740                         DRM_ERROR("unknown pipe bpc value\n");
3741                         bpp = 24;
3742                 }
3743
3744                 if (!lane) {
3745                         /*
3746                          * Account for spread spectrum to avoid
3747                          * oversubscribing the link. Max center spread
3748                          * is 2.5%; use 5% for safety's sake.
3749                          */
3750                         u32 bps = target_clock * bpp * 21 / 20;
3751                         lane = bps / (link_bw * 8) + 1;
3752                 }
3753
3754                 intel_crtc->fdi_lanes = lane;
3755
3756                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3757         }
3758
3759         /* Ironlake: try to setup display ref clock before DPLL
3760          * enabling. This is only under driver's control after
3761          * PCH B stepping, previous chipset stepping should be
3762          * ignoring this setting.
3763          */
3764         if (HAS_PCH_SPLIT(dev)) {
3765                 temp = I915_READ(PCH_DREF_CONTROL);
3766                 /* Always enable nonspread source */
3767                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3768                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3769                 temp &= ~DREF_SSC_SOURCE_MASK;
3770                 temp |= DREF_SSC_SOURCE_ENABLE;
3771                 I915_WRITE(PCH_DREF_CONTROL, temp);
3772
3773                 POSTING_READ(PCH_DREF_CONTROL);
3774                 udelay(200);
3775
3776                 if (has_edp_encoder) {
3777                         if (dev_priv->lvds_use_ssc) {
3778                                 temp |= DREF_SSC1_ENABLE;
3779                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3780
3781                                 POSTING_READ(PCH_DREF_CONTROL);
3782                                 udelay(200);
3783
3784                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3785                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3786                         } else {
3787                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3788                         }
3789                         I915_WRITE(PCH_DREF_CONTROL, temp);
3790                 }
3791         }
3792
3793         if (IS_PINEVIEW(dev)) {
3794                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3795                 if (has_reduced_clock)
3796                         fp2 = (1 << reduced_clock.n) << 16 |
3797                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3798         } else {
3799                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3800                 if (has_reduced_clock)
3801                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3802                                 reduced_clock.m2;
3803         }
3804
3805         dpll = 0;
3806         if (!HAS_PCH_SPLIT(dev))
3807                 dpll = DPLL_VGA_MODE_DIS;
3808
3809         if (!IS_GEN2(dev)) {
3810                 if (is_lvds)
3811                         dpll |= DPLLB_MODE_LVDS;
3812                 else
3813                         dpll |= DPLLB_MODE_DAC_SERIAL;
3814                 if (is_sdvo) {
3815                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3816                         if (pixel_multiplier > 1) {
3817                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3818                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3819                                 else if (HAS_PCH_SPLIT(dev))
3820                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3821                         }
3822                         dpll |= DPLL_DVO_HIGH_SPEED;
3823                 }
3824                 if (is_dp)
3825                         dpll |= DPLL_DVO_HIGH_SPEED;
3826
3827                 /* compute bitmask from p1 value */
3828                 if (IS_PINEVIEW(dev))
3829                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3830                 else {
3831                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3832                         /* also FPA1 */
3833                         if (HAS_PCH_SPLIT(dev))
3834                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3835                         if (IS_G4X(dev) && has_reduced_clock)
3836                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3837                 }
3838                 switch (clock.p2) {
3839                 case 5:
3840                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3841                         break;
3842                 case 7:
3843                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3844                         break;
3845                 case 10:
3846                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3847                         break;
3848                 case 14:
3849                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3850                         break;
3851                 }
3852                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3853                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3854         } else {
3855                 if (is_lvds) {
3856                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3857                 } else {
3858                         if (clock.p1 == 2)
3859                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3860                         else
3861                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3862                         if (clock.p2 == 4)
3863                                 dpll |= PLL_P2_DIVIDE_BY_4;
3864                 }
3865         }
3866
3867         if (is_sdvo && is_tv)
3868                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3869         else if (is_tv)
3870                 /* XXX: just matching BIOS for now */
3871                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3872                 dpll |= 3;
3873         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3874                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3875         else
3876                 dpll |= PLL_REF_INPUT_DREFCLK;
3877
3878         /* setup pipeconf */
3879         pipeconf = I915_READ(PIPECONF(pipe));
3880
3881         /* Set up the display plane register */
3882         dspcntr = DISPPLANE_GAMMA_ENABLE;
3883
3884         /* Ironlake's plane is forced to pipe, bit 24 is to
3885            enable color space conversion */
3886         if (!HAS_PCH_SPLIT(dev)) {
3887                 if (pipe == 0)
3888                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3889                 else
3890                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3891         }
3892
3893         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3894                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3895                  * core speed.
3896                  *
3897                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3898                  * pipe == 0 check?
3899                  */
3900                 if (mode->clock >
3901                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3902                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3903                 else
3904                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3905         }
3906
3907         dspcntr |= DISPLAY_PLANE_ENABLE;
3908         pipeconf |= PIPECONF_ENABLE;
3909         dpll |= DPLL_VCO_ENABLE;
3910
3911         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3912         drm_mode_debug_printmodeline(mode);
3913
3914         /* assign to Ironlake registers */
3915         if (HAS_PCH_SPLIT(dev)) {
3916                 fp_reg = PCH_FP0(pipe);
3917                 dpll_reg = PCH_DPLL(pipe);
3918         } else {
3919                 fp_reg = FP0(pipe);
3920                 dpll_reg = DPLL(pipe);
3921         }
3922
3923         if (!has_edp_encoder) {
3924                 I915_WRITE(fp_reg, fp);
3925                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3926
3927                 POSTING_READ(dpll_reg);
3928                 udelay(150);
3929         }
3930
3931         /* enable transcoder DPLL */
3932         if (HAS_PCH_CPT(dev)) {
3933                 temp = I915_READ(PCH_DPLL_SEL);
3934                 if (pipe == 0)
3935                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3936                 else
3937                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3938                 I915_WRITE(PCH_DPLL_SEL, temp);
3939
3940                 POSTING_READ(PCH_DPLL_SEL);
3941                 udelay(150);
3942         }
3943
3944         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3945          * This is an exception to the general rule that mode_set doesn't turn
3946          * things on.
3947          */
3948         if (is_lvds) {
3949                 reg = LVDS;
3950                 if (HAS_PCH_SPLIT(dev))
3951                         reg = PCH_LVDS;
3952
3953                 temp = I915_READ(reg);
3954                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3955                 if (pipe == 1) {
3956                         if (HAS_PCH_CPT(dev))
3957                                 temp |= PORT_TRANS_B_SEL_CPT;
3958                         else
3959                                 temp |= LVDS_PIPEB_SELECT;
3960                 } else {
3961                         if (HAS_PCH_CPT(dev))
3962                                 temp &= ~PORT_TRANS_SEL_MASK;
3963                         else
3964                                 temp &= ~LVDS_PIPEB_SELECT;
3965                 }
3966                 /* set the corresponsding LVDS_BORDER bit */
3967                 temp |= dev_priv->lvds_border_bits;
3968                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3969                  * set the DPLLs for dual-channel mode or not.
3970                  */
3971                 if (clock.p2 == 7)
3972                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3973                 else
3974                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3975
3976                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3977                  * appropriately here, but we need to look more thoroughly into how
3978                  * panels behave in the two modes.
3979                  */
3980                 /* set the dithering flag on non-PCH LVDS as needed */
3981                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
3982                         if (dev_priv->lvds_dither)
3983                                 temp |= LVDS_ENABLE_DITHER;
3984                         else
3985                                 temp &= ~LVDS_ENABLE_DITHER;
3986                 }
3987                 I915_WRITE(reg, temp);
3988         }
3989
3990         /* set the dithering flag and clear for anything other than a panel. */
3991         if (HAS_PCH_SPLIT(dev)) {
3992                 pipeconf &= ~PIPECONF_DITHER_EN;
3993                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3994                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3995                         pipeconf |= PIPECONF_DITHER_EN;
3996                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3997                 }
3998         }
3999
4000         if (is_dp)
4001                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4002         else if (HAS_PCH_SPLIT(dev)) {
4003                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4004                 if (pipe == 0) {
4005                         I915_WRITE(TRANSA_DATA_M1, 0);
4006                         I915_WRITE(TRANSA_DATA_N1, 0);
4007                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4008                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4009                 } else {
4010                         I915_WRITE(TRANSB_DATA_M1, 0);
4011                         I915_WRITE(TRANSB_DATA_N1, 0);
4012                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4013                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4014                 }
4015         }
4016
4017         if (!has_edp_encoder) {
4018                 I915_WRITE(fp_reg, fp);
4019                 I915_WRITE(dpll_reg, dpll);
4020
4021                 /* Wait for the clocks to stabilize. */
4022                 POSTING_READ(dpll_reg);
4023                 udelay(150);
4024
4025                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4026                         temp = 0;
4027                         if (is_sdvo) {
4028                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4029                                 if (temp > 1)
4030                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4031                                 else
4032                                         temp = 0;
4033                         }
4034                         I915_WRITE(DPLL_MD(pipe), temp);
4035                 } else {
4036                         /* write it again -- the BIOS does, after all */
4037                         I915_WRITE(dpll_reg, dpll);
4038                 }
4039
4040                 /* Wait for the clocks to stabilize. */
4041                 POSTING_READ(dpll_reg);
4042                 udelay(150);
4043         }
4044
4045         intel_crtc->lowfreq_avail = false;
4046         if (is_lvds && has_reduced_clock && i915_powersave) {
4047                 I915_WRITE(fp_reg + 4, fp2);
4048                 intel_crtc->lowfreq_avail = true;
4049                 if (HAS_PIPE_CXSR(dev)) {
4050                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4051                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4052                 }
4053         } else {
4054                 I915_WRITE(fp_reg + 4, fp);
4055                 if (HAS_PIPE_CXSR(dev)) {
4056                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4057                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4058                 }
4059         }
4060
4061         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4062                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4063                 /* the chip adds 2 halflines automatically */
4064                 adjusted_mode->crtc_vdisplay -= 1;
4065                 adjusted_mode->crtc_vtotal -= 1;
4066                 adjusted_mode->crtc_vblank_start -= 1;
4067                 adjusted_mode->crtc_vblank_end -= 1;
4068                 adjusted_mode->crtc_vsync_end -= 1;
4069                 adjusted_mode->crtc_vsync_start -= 1;
4070         } else
4071                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4072
4073         I915_WRITE(HTOTAL(pipe),
4074                    (adjusted_mode->crtc_hdisplay - 1) |
4075                    ((adjusted_mode->crtc_htotal - 1) << 16));
4076         I915_WRITE(HBLANK(pipe),
4077                    (adjusted_mode->crtc_hblank_start - 1) |
4078                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4079         I915_WRITE(HSYNC(pipe),
4080                    (adjusted_mode->crtc_hsync_start - 1) |
4081                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4082
4083         I915_WRITE(VTOTAL(pipe),
4084                    (adjusted_mode->crtc_vdisplay - 1) |
4085                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4086         I915_WRITE(VBLANK(pipe),
4087                    (adjusted_mode->crtc_vblank_start - 1) |
4088                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4089         I915_WRITE(VSYNC(pipe),
4090                    (adjusted_mode->crtc_vsync_start - 1) |
4091                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4092
4093         /* pipesrc and dspsize control the size that is scaled from,
4094          * which should always be the user's requested size.
4095          */
4096         if (!HAS_PCH_SPLIT(dev)) {
4097                 I915_WRITE(DSPSIZE(plane),
4098                            ((mode->vdisplay - 1) << 16) |
4099                            (mode->hdisplay - 1));
4100                 I915_WRITE(DSPPOS(plane), 0);
4101         }
4102         I915_WRITE(PIPESRC(pipe),
4103                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4104
4105         if (HAS_PCH_SPLIT(dev)) {
4106                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4107                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4108                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4109                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4110
4111                 if (has_edp_encoder) {
4112                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4113                 } else {
4114                         /* enable FDI RX PLL too */
4115                         reg = FDI_RX_CTL(pipe);
4116                         temp = I915_READ(reg);
4117                         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4118
4119                         POSTING_READ(reg);
4120                         udelay(200);
4121
4122                         /* enable FDI TX PLL too */
4123                         reg = FDI_TX_CTL(pipe);
4124                         temp = I915_READ(reg);
4125                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4126
4127                         /* enable FDI RX PCDCLK */
4128                         reg = FDI_RX_CTL(pipe);
4129                         temp = I915_READ(reg);
4130                         I915_WRITE(reg, temp | FDI_PCDCLK);
4131
4132                         POSTING_READ(reg);
4133                         udelay(200);
4134                 }
4135         }
4136
4137         I915_WRITE(PIPECONF(pipe), pipeconf);
4138         POSTING_READ(PIPECONF(pipe));
4139
4140         intel_wait_for_vblank(dev, pipe);
4141
4142         if (IS_IRONLAKE(dev)) {
4143                 /* enable address swizzle for tiling buffer */
4144                 temp = I915_READ(DISP_ARB_CTL);
4145                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4146         }
4147
4148         I915_WRITE(DSPCNTR(plane), dspcntr);
4149
4150         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4151
4152         intel_update_watermarks(dev);
4153
4154         drm_vblank_post_modeset(dev, pipe);
4155
4156         return ret;
4157 }
4158
4159 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4160 void intel_crtc_load_lut(struct drm_crtc *crtc)
4161 {
4162         struct drm_device *dev = crtc->dev;
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4165         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4166         int i;
4167
4168         /* The clocks have to be on to load the palette. */
4169         if (!crtc->enabled)
4170                 return;
4171
4172         /* use legacy palette for Ironlake */
4173         if (HAS_PCH_SPLIT(dev))
4174                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4175                                                    LGC_PALETTE_B;
4176
4177         for (i = 0; i < 256; i++) {
4178                 I915_WRITE(palreg + 4 * i,
4179                            (intel_crtc->lut_r[i] << 16) |
4180                            (intel_crtc->lut_g[i] << 8) |
4181                            intel_crtc->lut_b[i]);
4182         }
4183 }
4184
4185 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4186 {
4187         struct drm_device *dev = crtc->dev;
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190         bool visible = base != 0;
4191         u32 cntl;
4192
4193         if (intel_crtc->cursor_visible == visible)
4194                 return;
4195
4196         cntl = I915_READ(CURACNTR);
4197         if (visible) {
4198                 /* On these chipsets we can only modify the base whilst
4199                  * the cursor is disabled.
4200                  */
4201                 I915_WRITE(CURABASE, base);
4202
4203                 cntl &= ~(CURSOR_FORMAT_MASK);
4204                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4205                 cntl |= CURSOR_ENABLE |
4206                         CURSOR_GAMMA_ENABLE |
4207                         CURSOR_FORMAT_ARGB;
4208         } else
4209                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4210         I915_WRITE(CURACNTR, cntl);
4211
4212         intel_crtc->cursor_visible = visible;
4213 }
4214
4215 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4216 {
4217         struct drm_device *dev = crtc->dev;
4218         struct drm_i915_private *dev_priv = dev->dev_private;
4219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220         int pipe = intel_crtc->pipe;
4221         bool visible = base != 0;
4222
4223         if (intel_crtc->cursor_visible != visible) {
4224                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4225                 if (base) {
4226                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4227                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4228                         cntl |= pipe << 28; /* Connect to correct pipe */
4229                 } else {
4230                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4231                         cntl |= CURSOR_MODE_DISABLE;
4232                 }
4233                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4234
4235                 intel_crtc->cursor_visible = visible;
4236         }
4237         /* and commit changes on next vblank */
4238         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4239 }
4240
4241 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4242 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4243                                      bool on)
4244 {
4245         struct drm_device *dev = crtc->dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248         int pipe = intel_crtc->pipe;
4249         int x = intel_crtc->cursor_x;
4250         int y = intel_crtc->cursor_y;
4251         u32 base, pos;
4252         bool visible;
4253
4254         pos = 0;
4255
4256         if (on && crtc->enabled && crtc->fb) {
4257                 base = intel_crtc->cursor_addr;
4258                 if (x > (int) crtc->fb->width)
4259                         base = 0;
4260
4261                 if (y > (int) crtc->fb->height)
4262                         base = 0;
4263         } else
4264                 base = 0;
4265
4266         if (x < 0) {
4267                 if (x + intel_crtc->cursor_width < 0)
4268                         base = 0;
4269
4270                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4271                 x = -x;
4272         }
4273         pos |= x << CURSOR_X_SHIFT;
4274
4275         if (y < 0) {
4276                 if (y + intel_crtc->cursor_height < 0)
4277                         base = 0;
4278
4279                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4280                 y = -y;
4281         }
4282         pos |= y << CURSOR_Y_SHIFT;
4283
4284         visible = base != 0;
4285         if (!visible && !intel_crtc->cursor_visible)
4286                 return;
4287
4288         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4289         if (IS_845G(dev) || IS_I865G(dev))
4290                 i845_update_cursor(crtc, base);
4291         else
4292                 i9xx_update_cursor(crtc, base);
4293
4294         if (visible)
4295                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4296 }
4297
4298 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4299                                  struct drm_file *file_priv,
4300                                  uint32_t handle,
4301                                  uint32_t width, uint32_t height)
4302 {
4303         struct drm_device *dev = crtc->dev;
4304         struct drm_i915_private *dev_priv = dev->dev_private;
4305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4306         struct drm_gem_object *bo;
4307         struct drm_i915_gem_object *obj_priv;
4308         uint32_t addr;
4309         int ret;
4310
4311         DRM_DEBUG_KMS("\n");
4312
4313         /* if we want to turn off the cursor ignore width and height */
4314         if (!handle) {
4315                 DRM_DEBUG_KMS("cursor off\n");
4316                 addr = 0;
4317                 bo = NULL;
4318                 mutex_lock(&dev->struct_mutex);
4319                 goto finish;
4320         }
4321
4322         /* Currently we only support 64x64 cursors */
4323         if (width != 64 || height != 64) {
4324                 DRM_ERROR("we currently only support 64x64 cursors\n");
4325                 return -EINVAL;
4326         }
4327
4328         bo = drm_gem_object_lookup(dev, file_priv, handle);
4329         if (!bo)
4330                 return -ENOENT;
4331
4332         obj_priv = to_intel_bo(bo);
4333
4334         if (bo->size < width * height * 4) {
4335                 DRM_ERROR("buffer is to small\n");
4336                 ret = -ENOMEM;
4337                 goto fail;
4338         }
4339
4340         /* we only need to pin inside GTT if cursor is non-phy */
4341         mutex_lock(&dev->struct_mutex);
4342         if (!dev_priv->info->cursor_needs_physical) {
4343                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4344                 if (ret) {
4345                         DRM_ERROR("failed to pin cursor bo\n");
4346                         goto fail_locked;
4347                 }
4348
4349                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4350                 if (ret) {
4351                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4352                         goto fail_unpin;
4353                 }
4354
4355                 addr = obj_priv->gtt_offset;
4356         } else {
4357                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4358                 ret = i915_gem_attach_phys_object(dev, bo,
4359                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4360                                                   align);
4361                 if (ret) {
4362                         DRM_ERROR("failed to attach phys object\n");
4363                         goto fail_locked;
4364                 }
4365                 addr = obj_priv->phys_obj->handle->busaddr;
4366         }
4367
4368         if (IS_GEN2(dev))
4369                 I915_WRITE(CURSIZE, (height << 12) | width);
4370
4371  finish:
4372         if (intel_crtc->cursor_bo) {
4373                 if (dev_priv->info->cursor_needs_physical) {
4374                         if (intel_crtc->cursor_bo != bo)
4375                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4376                 } else
4377                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4378                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4379         }
4380
4381         mutex_unlock(&dev->struct_mutex);
4382
4383         intel_crtc->cursor_addr = addr;
4384         intel_crtc->cursor_bo = bo;
4385         intel_crtc->cursor_width = width;
4386         intel_crtc->cursor_height = height;
4387
4388         intel_crtc_update_cursor(crtc, true);
4389
4390         return 0;
4391 fail_unpin:
4392         i915_gem_object_unpin(bo);
4393 fail_locked:
4394         mutex_unlock(&dev->struct_mutex);
4395 fail:
4396         drm_gem_object_unreference_unlocked(bo);
4397         return ret;
4398 }
4399
4400 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4401 {
4402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4403
4404         intel_crtc->cursor_x = x;
4405         intel_crtc->cursor_y = y;
4406
4407         intel_crtc_update_cursor(crtc, true);
4408
4409         return 0;
4410 }
4411
4412 /** Sets the color ramps on behalf of RandR */
4413 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4414                                  u16 blue, int regno)
4415 {
4416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417
4418         intel_crtc->lut_r[regno] = red >> 8;
4419         intel_crtc->lut_g[regno] = green >> 8;
4420         intel_crtc->lut_b[regno] = blue >> 8;
4421 }
4422
4423 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4424                              u16 *blue, int regno)
4425 {
4426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4427
4428         *red = intel_crtc->lut_r[regno] << 8;
4429         *green = intel_crtc->lut_g[regno] << 8;
4430         *blue = intel_crtc->lut_b[regno] << 8;
4431 }
4432
4433 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4434                                  u16 *blue, uint32_t start, uint32_t size)
4435 {
4436         int end = (start + size > 256) ? 256 : start + size, i;
4437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4438
4439         for (i = start; i < end; i++) {
4440                 intel_crtc->lut_r[i] = red[i] >> 8;
4441                 intel_crtc->lut_g[i] = green[i] >> 8;
4442                 intel_crtc->lut_b[i] = blue[i] >> 8;
4443         }
4444
4445         intel_crtc_load_lut(crtc);
4446 }
4447
4448 /**
4449  * Get a pipe with a simple mode set on it for doing load-based monitor
4450  * detection.
4451  *
4452  * It will be up to the load-detect code to adjust the pipe as appropriate for
4453  * its requirements.  The pipe will be connected to no other encoders.
4454  *
4455  * Currently this code will only succeed if there is a pipe with no encoders
4456  * configured for it.  In the future, it could choose to temporarily disable
4457  * some outputs to free up a pipe for its use.
4458  *
4459  * \return crtc, or NULL if no pipes are available.
4460  */
4461
4462 /* VESA 640x480x72Hz mode to set on the pipe */
4463 static struct drm_display_mode load_detect_mode = {
4464         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4465                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4466 };
4467
4468 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4469                                             struct drm_connector *connector,
4470                                             struct drm_display_mode *mode,
4471                                             int *dpms_mode)
4472 {
4473         struct intel_crtc *intel_crtc;
4474         struct drm_crtc *possible_crtc;
4475         struct drm_crtc *supported_crtc =NULL;
4476         struct drm_encoder *encoder = &intel_encoder->base;
4477         struct drm_crtc *crtc = NULL;
4478         struct drm_device *dev = encoder->dev;
4479         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4480         struct drm_crtc_helper_funcs *crtc_funcs;
4481         int i = -1;
4482
4483         /*
4484          * Algorithm gets a little messy:
4485          *   - if the connector already has an assigned crtc, use it (but make
4486          *     sure it's on first)
4487          *   - try to find the first unused crtc that can drive this connector,
4488          *     and use that if we find one
4489          *   - if there are no unused crtcs available, try to use the first
4490          *     one we found that supports the connector
4491          */
4492
4493         /* See if we already have a CRTC for this connector */
4494         if (encoder->crtc) {
4495                 crtc = encoder->crtc;
4496                 /* Make sure the crtc and connector are running */
4497                 intel_crtc = to_intel_crtc(crtc);
4498                 *dpms_mode = intel_crtc->dpms_mode;
4499                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4500                         crtc_funcs = crtc->helper_private;
4501                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4502                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4503                 }
4504                 return crtc;
4505         }
4506
4507         /* Find an unused one (if possible) */
4508         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4509                 i++;
4510                 if (!(encoder->possible_crtcs & (1 << i)))
4511                         continue;
4512                 if (!possible_crtc->enabled) {
4513                         crtc = possible_crtc;
4514                         break;
4515                 }
4516                 if (!supported_crtc)
4517                         supported_crtc = possible_crtc;
4518         }
4519
4520         /*
4521          * If we didn't find an unused CRTC, don't use any.
4522          */
4523         if (!crtc) {
4524                 return NULL;
4525         }
4526
4527         encoder->crtc = crtc;
4528         connector->encoder = encoder;
4529         intel_encoder->load_detect_temp = true;
4530
4531         intel_crtc = to_intel_crtc(crtc);
4532         *dpms_mode = intel_crtc->dpms_mode;
4533
4534         if (!crtc->enabled) {
4535                 if (!mode)
4536                         mode = &load_detect_mode;
4537                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4538         } else {
4539                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4540                         crtc_funcs = crtc->helper_private;
4541                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4542                 }
4543
4544                 /* Add this connector to the crtc */
4545                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4546                 encoder_funcs->commit(encoder);
4547         }
4548         /* let the connector get through one full cycle before testing */
4549         intel_wait_for_vblank(dev, intel_crtc->pipe);
4550
4551         return crtc;
4552 }
4553
4554 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4555                                     struct drm_connector *connector, int dpms_mode)
4556 {
4557         struct drm_encoder *encoder = &intel_encoder->base;
4558         struct drm_device *dev = encoder->dev;
4559         struct drm_crtc *crtc = encoder->crtc;
4560         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4561         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4562
4563         if (intel_encoder->load_detect_temp) {
4564                 encoder->crtc = NULL;
4565                 connector->encoder = NULL;
4566                 intel_encoder->load_detect_temp = false;
4567                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4568                 drm_helper_disable_unused_functions(dev);
4569         }
4570
4571         /* Switch crtc and encoder back off if necessary */
4572         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4573                 if (encoder->crtc == crtc)
4574                         encoder_funcs->dpms(encoder, dpms_mode);
4575                 crtc_funcs->dpms(crtc, dpms_mode);
4576         }
4577 }
4578
4579 /* Returns the clock of the currently programmed mode of the given pipe. */
4580 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4581 {
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4584         int pipe = intel_crtc->pipe;
4585         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4586         u32 fp;
4587         intel_clock_t clock;
4588
4589         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4590                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4591         else
4592                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4593
4594         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4595         if (IS_PINEVIEW(dev)) {
4596                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4597                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4598         } else {
4599                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4600                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4601         }
4602
4603         if (!IS_GEN2(dev)) {
4604                 if (IS_PINEVIEW(dev))
4605                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4606                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4607                 else
4608                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4609                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4610
4611                 switch (dpll & DPLL_MODE_MASK) {
4612                 case DPLLB_MODE_DAC_SERIAL:
4613                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4614                                 5 : 10;
4615                         break;
4616                 case DPLLB_MODE_LVDS:
4617                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4618                                 7 : 14;
4619                         break;
4620                 default:
4621                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4622                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4623                         return 0;
4624                 }
4625
4626                 /* XXX: Handle the 100Mhz refclk */
4627                 intel_clock(dev, 96000, &clock);
4628         } else {
4629                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4630
4631                 if (is_lvds) {
4632                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4633                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4634                         clock.p2 = 14;
4635
4636                         if ((dpll & PLL_REF_INPUT_MASK) ==
4637                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4638                                 /* XXX: might not be 66MHz */
4639                                 intel_clock(dev, 66000, &clock);
4640                         } else
4641                                 intel_clock(dev, 48000, &clock);
4642                 } else {
4643                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4644                                 clock.p1 = 2;
4645                         else {
4646                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4647                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4648                         }
4649                         if (dpll & PLL_P2_DIVIDE_BY_4)
4650                                 clock.p2 = 4;
4651                         else
4652                                 clock.p2 = 2;
4653
4654                         intel_clock(dev, 48000, &clock);
4655                 }
4656         }
4657
4658         /* XXX: It would be nice to validate the clocks, but we can't reuse
4659          * i830PllIsValid() because it relies on the xf86_config connector
4660          * configuration being accurate, which it isn't necessarily.
4661          */
4662
4663         return clock.dot;
4664 }
4665
4666 /** Returns the currently programmed mode of the given pipe. */
4667 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4668                                              struct drm_crtc *crtc)
4669 {
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672         int pipe = intel_crtc->pipe;
4673         struct drm_display_mode *mode;
4674         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4675         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4676         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4677         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4678
4679         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4680         if (!mode)
4681                 return NULL;
4682
4683         mode->clock = intel_crtc_clock_get(dev, crtc);
4684         mode->hdisplay = (htot & 0xffff) + 1;
4685         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4686         mode->hsync_start = (hsync & 0xffff) + 1;
4687         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4688         mode->vdisplay = (vtot & 0xffff) + 1;
4689         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4690         mode->vsync_start = (vsync & 0xffff) + 1;
4691         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4692
4693         drm_mode_set_name(mode);
4694         drm_mode_set_crtcinfo(mode, 0);
4695
4696         return mode;
4697 }
4698
4699 #define GPU_IDLE_TIMEOUT 500 /* ms */
4700
4701 /* When this timer fires, we've been idle for awhile */
4702 static void intel_gpu_idle_timer(unsigned long arg)
4703 {
4704         struct drm_device *dev = (struct drm_device *)arg;
4705         drm_i915_private_t *dev_priv = dev->dev_private;
4706
4707         dev_priv->busy = false;
4708
4709         queue_work(dev_priv->wq, &dev_priv->idle_work);
4710 }
4711
4712 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4713
4714 static void intel_crtc_idle_timer(unsigned long arg)
4715 {
4716         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4717         struct drm_crtc *crtc = &intel_crtc->base;
4718         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4719
4720         intel_crtc->busy = false;
4721
4722         queue_work(dev_priv->wq, &dev_priv->idle_work);
4723 }
4724
4725 static void intel_increase_pllclock(struct drm_crtc *crtc)
4726 {
4727         struct drm_device *dev = crtc->dev;
4728         drm_i915_private_t *dev_priv = dev->dev_private;
4729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730         int pipe = intel_crtc->pipe;
4731         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4732         int dpll = I915_READ(dpll_reg);
4733
4734         if (HAS_PCH_SPLIT(dev))
4735                 return;
4736
4737         if (!dev_priv->lvds_downclock_avail)
4738                 return;
4739
4740         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4741                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4742
4743                 /* Unlock panel regs */
4744                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4745                            PANEL_UNLOCK_REGS);
4746
4747                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4748                 I915_WRITE(dpll_reg, dpll);
4749                 dpll = I915_READ(dpll_reg);
4750                 intel_wait_for_vblank(dev, pipe);
4751                 dpll = I915_READ(dpll_reg);
4752                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4753                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4754
4755                 /* ...and lock them again */
4756                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4757         }
4758
4759         /* Schedule downclock */
4760         mod_timer(&intel_crtc->idle_timer, jiffies +
4761                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4762 }
4763
4764 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4765 {
4766         struct drm_device *dev = crtc->dev;
4767         drm_i915_private_t *dev_priv = dev->dev_private;
4768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769         int pipe = intel_crtc->pipe;
4770         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4771         int dpll = I915_READ(dpll_reg);
4772
4773         if (HAS_PCH_SPLIT(dev))
4774                 return;
4775
4776         if (!dev_priv->lvds_downclock_avail)
4777                 return;
4778
4779         /*
4780          * Since this is called by a timer, we should never get here in
4781          * the manual case.
4782          */
4783         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4784                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4785
4786                 /* Unlock panel regs */
4787                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4788                            PANEL_UNLOCK_REGS);
4789
4790                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4791                 I915_WRITE(dpll_reg, dpll);
4792                 dpll = I915_READ(dpll_reg);
4793                 intel_wait_for_vblank(dev, pipe);
4794                 dpll = I915_READ(dpll_reg);
4795                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4796                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4797
4798                 /* ...and lock them again */
4799                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4800         }
4801
4802 }
4803
4804 /**
4805  * intel_idle_update - adjust clocks for idleness
4806  * @work: work struct
4807  *
4808  * Either the GPU or display (or both) went idle.  Check the busy status
4809  * here and adjust the CRTC and GPU clocks as necessary.
4810  */
4811 static void intel_idle_update(struct work_struct *work)
4812 {
4813         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4814                                                     idle_work);
4815         struct drm_device *dev = dev_priv->dev;
4816         struct drm_crtc *crtc;
4817         struct intel_crtc *intel_crtc;
4818         int enabled = 0;
4819
4820         if (!i915_powersave)
4821                 return;
4822
4823         mutex_lock(&dev->struct_mutex);
4824
4825         i915_update_gfx_val(dev_priv);
4826
4827         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4828                 /* Skip inactive CRTCs */
4829                 if (!crtc->fb)
4830                         continue;
4831
4832                 enabled++;
4833                 intel_crtc = to_intel_crtc(crtc);
4834                 if (!intel_crtc->busy)
4835                         intel_decrease_pllclock(crtc);
4836         }
4837
4838         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4839                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4840                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4841         }
4842
4843         mutex_unlock(&dev->struct_mutex);
4844 }
4845
4846 /**
4847  * intel_mark_busy - mark the GPU and possibly the display busy
4848  * @dev: drm device
4849  * @obj: object we're operating on
4850  *
4851  * Callers can use this function to indicate that the GPU is busy processing
4852  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4853  * buffer), we'll also mark the display as busy, so we know to increase its
4854  * clock frequency.
4855  */
4856 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4857 {
4858         drm_i915_private_t *dev_priv = dev->dev_private;
4859         struct drm_crtc *crtc = NULL;
4860         struct intel_framebuffer *intel_fb;
4861         struct intel_crtc *intel_crtc;
4862
4863         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4864                 return;
4865
4866         if (!dev_priv->busy) {
4867                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4868                         u32 fw_blc_self;
4869
4870                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4871                         fw_blc_self = I915_READ(FW_BLC_SELF);
4872                         fw_blc_self &= ~FW_BLC_SELF_EN;
4873                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4874                 }
4875                 dev_priv->busy = true;
4876         } else
4877                 mod_timer(&dev_priv->idle_timer, jiffies +
4878                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4879
4880         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4881                 if (!crtc->fb)
4882                         continue;
4883
4884                 intel_crtc = to_intel_crtc(crtc);
4885                 intel_fb = to_intel_framebuffer(crtc->fb);
4886                 if (intel_fb->obj == obj) {
4887                         if (!intel_crtc->busy) {
4888                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4889                                         u32 fw_blc_self;
4890
4891                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4892                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4893                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4894                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4895                                 }
4896                                 /* Non-busy -> busy, upclock */
4897                                 intel_increase_pllclock(crtc);
4898                                 intel_crtc->busy = true;
4899                         } else {
4900                                 /* Busy -> busy, put off timer */
4901                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4902                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4903                         }
4904                 }
4905         }
4906 }
4907
4908 static void intel_crtc_destroy(struct drm_crtc *crtc)
4909 {
4910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4911         struct drm_device *dev = crtc->dev;
4912         struct intel_unpin_work *work;
4913         unsigned long flags;
4914
4915         spin_lock_irqsave(&dev->event_lock, flags);
4916         work = intel_crtc->unpin_work;
4917         intel_crtc->unpin_work = NULL;
4918         spin_unlock_irqrestore(&dev->event_lock, flags);
4919
4920         if (work) {
4921                 cancel_work_sync(&work->work);
4922                 kfree(work);
4923         }
4924
4925         drm_crtc_cleanup(crtc);
4926
4927         kfree(intel_crtc);
4928 }
4929
4930 static void intel_unpin_work_fn(struct work_struct *__work)
4931 {
4932         struct intel_unpin_work *work =
4933                 container_of(__work, struct intel_unpin_work, work);
4934
4935         mutex_lock(&work->dev->struct_mutex);
4936         i915_gem_object_unpin(work->old_fb_obj);
4937         drm_gem_object_unreference(work->pending_flip_obj);
4938         drm_gem_object_unreference(work->old_fb_obj);
4939         mutex_unlock(&work->dev->struct_mutex);
4940         kfree(work);
4941 }
4942
4943 static void do_intel_finish_page_flip(struct drm_device *dev,
4944                                       struct drm_crtc *crtc)
4945 {
4946         drm_i915_private_t *dev_priv = dev->dev_private;
4947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948         struct intel_unpin_work *work;
4949         struct drm_i915_gem_object *obj_priv;
4950         struct drm_pending_vblank_event *e;
4951         struct timeval now;
4952         unsigned long flags;
4953
4954         /* Ignore early vblank irqs */
4955         if (intel_crtc == NULL)
4956                 return;
4957
4958         spin_lock_irqsave(&dev->event_lock, flags);
4959         work = intel_crtc->unpin_work;
4960         if (work == NULL || !work->pending) {
4961                 spin_unlock_irqrestore(&dev->event_lock, flags);
4962                 return;
4963         }
4964
4965         intel_crtc->unpin_work = NULL;
4966         drm_vblank_put(dev, intel_crtc->pipe);
4967
4968         if (work->event) {
4969                 e = work->event;
4970                 do_gettimeofday(&now);
4971                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4972                 e->event.tv_sec = now.tv_sec;
4973                 e->event.tv_usec = now.tv_usec;
4974                 list_add_tail(&e->base.link,
4975                               &e->base.file_priv->event_list);
4976                 wake_up_interruptible(&e->base.file_priv->event_wait);
4977         }
4978
4979         spin_unlock_irqrestore(&dev->event_lock, flags);
4980
4981         obj_priv = to_intel_bo(work->pending_flip_obj);
4982
4983         /* Initial scanout buffer will have a 0 pending flip count */
4984         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4985             atomic_dec_and_test(&obj_priv->pending_flip))
4986                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4987         schedule_work(&work->work);
4988
4989         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4990 }
4991
4992 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4993 {
4994         drm_i915_private_t *dev_priv = dev->dev_private;
4995         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4996
4997         do_intel_finish_page_flip(dev, crtc);
4998 }
4999
5000 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5001 {
5002         drm_i915_private_t *dev_priv = dev->dev_private;
5003         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5004
5005         do_intel_finish_page_flip(dev, crtc);
5006 }
5007
5008 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5009 {
5010         drm_i915_private_t *dev_priv = dev->dev_private;
5011         struct intel_crtc *intel_crtc =
5012                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5013         unsigned long flags;
5014
5015         spin_lock_irqsave(&dev->event_lock, flags);
5016         if (intel_crtc->unpin_work) {
5017                 if ((++intel_crtc->unpin_work->pending) > 1)
5018                         DRM_ERROR("Prepared flip multiple times\n");
5019         } else {
5020                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5021         }
5022         spin_unlock_irqrestore(&dev->event_lock, flags);
5023 }
5024
5025 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5026                                 struct drm_framebuffer *fb,
5027                                 struct drm_pending_vblank_event *event)
5028 {
5029         struct drm_device *dev = crtc->dev;
5030         struct drm_i915_private *dev_priv = dev->dev_private;
5031         struct intel_framebuffer *intel_fb;
5032         struct drm_i915_gem_object *obj_priv;
5033         struct drm_gem_object *obj;
5034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5035         struct intel_unpin_work *work;
5036         unsigned long flags, offset;
5037         int pipe = intel_crtc->pipe;
5038         u32 pf, pipesrc;
5039         int ret;
5040
5041         work = kzalloc(sizeof *work, GFP_KERNEL);
5042         if (work == NULL)
5043                 return -ENOMEM;
5044
5045         work->event = event;
5046         work->dev = crtc->dev;
5047         intel_fb = to_intel_framebuffer(crtc->fb);
5048         work->old_fb_obj = intel_fb->obj;
5049         INIT_WORK(&work->work, intel_unpin_work_fn);
5050
5051         /* We borrow the event spin lock for protecting unpin_work */
5052         spin_lock_irqsave(&dev->event_lock, flags);
5053         if (intel_crtc->unpin_work) {
5054                 spin_unlock_irqrestore(&dev->event_lock, flags);
5055                 kfree(work);
5056
5057                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5058                 return -EBUSY;
5059         }
5060         intel_crtc->unpin_work = work;
5061         spin_unlock_irqrestore(&dev->event_lock, flags);
5062
5063         intel_fb = to_intel_framebuffer(fb);
5064         obj = intel_fb->obj;
5065
5066         mutex_lock(&dev->struct_mutex);
5067         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5068         if (ret)
5069                 goto cleanup_work;
5070
5071         /* Reference the objects for the scheduled work. */
5072         drm_gem_object_reference(work->old_fb_obj);
5073         drm_gem_object_reference(obj);
5074
5075         crtc->fb = fb;
5076
5077         ret = drm_vblank_get(dev, intel_crtc->pipe);
5078         if (ret)
5079                 goto cleanup_objs;
5080
5081         obj_priv = to_intel_bo(obj);
5082         atomic_inc(&obj_priv->pending_flip);
5083         work->pending_flip_obj = obj;
5084
5085         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5086                 u32 flip_mask;
5087
5088                 /* Can't queue multiple flips, so wait for the previous
5089                  * one to finish before executing the next.
5090                  */
5091                 BEGIN_LP_RING(2);
5092                 if (intel_crtc->plane)
5093                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5094                 else
5095                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5096                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5097                 OUT_RING(MI_NOOP);
5098                 ADVANCE_LP_RING();
5099         }
5100
5101         work->enable_stall_check = true;
5102
5103         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5104         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5105
5106         BEGIN_LP_RING(4);
5107         switch(INTEL_INFO(dev)->gen) {
5108         case 2:
5109                 OUT_RING(MI_DISPLAY_FLIP |
5110                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5111                 OUT_RING(fb->pitch);
5112                 OUT_RING(obj_priv->gtt_offset + offset);
5113                 OUT_RING(MI_NOOP);
5114                 break;
5115
5116         case 3:
5117                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5118                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5119                 OUT_RING(fb->pitch);
5120                 OUT_RING(obj_priv->gtt_offset + offset);
5121                 OUT_RING(MI_NOOP);
5122                 break;
5123
5124         case 4:
5125         case 5:
5126                 /* i965+ uses the linear or tiled offsets from the
5127                  * Display Registers (which do not change across a page-flip)
5128                  * so we need only reprogram the base address.
5129                  */
5130                 OUT_RING(MI_DISPLAY_FLIP |
5131                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5132                 OUT_RING(fb->pitch);
5133                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5134
5135                 /* XXX Enabling the panel-fitter across page-flip is so far
5136                  * untested on non-native modes, so ignore it for now.
5137                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5138                  */
5139                 pf = 0;
5140                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5141                 OUT_RING(pf | pipesrc);
5142                 break;
5143
5144         case 6:
5145                 OUT_RING(MI_DISPLAY_FLIP |
5146                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5147                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5148                 OUT_RING(obj_priv->gtt_offset);
5149
5150                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5151                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5152                 OUT_RING(pf | pipesrc);
5153                 break;
5154         }
5155         ADVANCE_LP_RING();
5156
5157         mutex_unlock(&dev->struct_mutex);
5158
5159         trace_i915_flip_request(intel_crtc->plane, obj);
5160
5161         return 0;
5162
5163 cleanup_objs:
5164         drm_gem_object_unreference(work->old_fb_obj);
5165         drm_gem_object_unreference(obj);
5166 cleanup_work:
5167         mutex_unlock(&dev->struct_mutex);
5168
5169         spin_lock_irqsave(&dev->event_lock, flags);
5170         intel_crtc->unpin_work = NULL;
5171         spin_unlock_irqrestore(&dev->event_lock, flags);
5172
5173         kfree(work);
5174
5175         return ret;
5176 }
5177
5178 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5179         .dpms = intel_crtc_dpms,
5180         .mode_fixup = intel_crtc_mode_fixup,
5181         .mode_set = intel_crtc_mode_set,
5182         .mode_set_base = intel_pipe_set_base,
5183         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5184         .load_lut = intel_crtc_load_lut,
5185         .disable = intel_crtc_disable,
5186 };
5187
5188 static const struct drm_crtc_funcs intel_crtc_funcs = {
5189         .cursor_set = intel_crtc_cursor_set,
5190         .cursor_move = intel_crtc_cursor_move,
5191         .gamma_set = intel_crtc_gamma_set,
5192         .set_config = drm_crtc_helper_set_config,
5193         .destroy = intel_crtc_destroy,
5194         .page_flip = intel_crtc_page_flip,
5195 };
5196
5197
5198 static void intel_crtc_init(struct drm_device *dev, int pipe)
5199 {
5200         drm_i915_private_t *dev_priv = dev->dev_private;
5201         struct intel_crtc *intel_crtc;
5202         int i;
5203
5204         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5205         if (intel_crtc == NULL)
5206                 return;
5207
5208         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5209
5210         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5211         for (i = 0; i < 256; i++) {
5212                 intel_crtc->lut_r[i] = i;
5213                 intel_crtc->lut_g[i] = i;
5214                 intel_crtc->lut_b[i] = i;
5215         }
5216
5217         /* Swap pipes & planes for FBC on pre-965 */
5218         intel_crtc->pipe = pipe;
5219         intel_crtc->plane = pipe;
5220         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5221                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5222                 intel_crtc->plane = !pipe;
5223         }
5224
5225         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5226                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5227         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5228         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5229
5230         intel_crtc->cursor_addr = 0;
5231         intel_crtc->dpms_mode = -1;
5232         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5233
5234         if (HAS_PCH_SPLIT(dev)) {
5235                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5236                 intel_helper_funcs.commit = ironlake_crtc_commit;
5237         } else {
5238                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5239                 intel_helper_funcs.commit = i9xx_crtc_commit;
5240         }
5241
5242         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5243
5244         intel_crtc->busy = false;
5245
5246         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5247                     (unsigned long)intel_crtc);
5248 }
5249
5250 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5251                                 struct drm_file *file_priv)
5252 {
5253         drm_i915_private_t *dev_priv = dev->dev_private;
5254         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5255         struct drm_mode_object *drmmode_obj;
5256         struct intel_crtc *crtc;
5257
5258         if (!dev_priv) {
5259                 DRM_ERROR("called with no initialization\n");
5260                 return -EINVAL;
5261         }
5262
5263         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5264                         DRM_MODE_OBJECT_CRTC);
5265
5266         if (!drmmode_obj) {
5267                 DRM_ERROR("no such CRTC id\n");
5268                 return -EINVAL;
5269         }
5270
5271         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5272         pipe_from_crtc_id->pipe = crtc->pipe;
5273
5274         return 0;
5275 }
5276
5277 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5278 {
5279         struct intel_encoder *encoder;
5280         int index_mask = 0;
5281         int entry = 0;
5282
5283         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5284                 if (type_mask & encoder->clone_mask)
5285                         index_mask |= (1 << entry);
5286                 entry++;
5287         }
5288
5289         return index_mask;
5290 }
5291
5292 static void intel_setup_outputs(struct drm_device *dev)
5293 {
5294         struct drm_i915_private *dev_priv = dev->dev_private;
5295         struct intel_encoder *encoder;
5296         bool dpd_is_edp = false;
5297
5298         if (IS_MOBILE(dev) && !IS_I830(dev))
5299                 intel_lvds_init(dev);
5300
5301         if (HAS_PCH_SPLIT(dev)) {
5302                 dpd_is_edp = intel_dpd_is_edp(dev);
5303
5304                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5305                         intel_dp_init(dev, DP_A);
5306
5307                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5308                         intel_dp_init(dev, PCH_DP_D);
5309         }
5310
5311         intel_crt_init(dev);
5312
5313         if (HAS_PCH_SPLIT(dev)) {
5314                 int found;
5315
5316                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5317                         /* PCH SDVOB multiplex with HDMIB */
5318                         found = intel_sdvo_init(dev, PCH_SDVOB);
5319                         if (!found)
5320                                 intel_hdmi_init(dev, HDMIB);
5321                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5322                                 intel_dp_init(dev, PCH_DP_B);
5323                 }
5324
5325                 if (I915_READ(HDMIC) & PORT_DETECTED)
5326                         intel_hdmi_init(dev, HDMIC);
5327
5328                 if (I915_READ(HDMID) & PORT_DETECTED)
5329                         intel_hdmi_init(dev, HDMID);
5330
5331                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5332                         intel_dp_init(dev, PCH_DP_C);
5333
5334                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5335                         intel_dp_init(dev, PCH_DP_D);
5336
5337         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5338                 bool found = false;
5339
5340                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5341                         DRM_DEBUG_KMS("probing SDVOB\n");
5342                         found = intel_sdvo_init(dev, SDVOB);
5343                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5344                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5345                                 intel_hdmi_init(dev, SDVOB);
5346                         }
5347
5348                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5349                                 DRM_DEBUG_KMS("probing DP_B\n");
5350                                 intel_dp_init(dev, DP_B);
5351                         }
5352                 }
5353
5354                 /* Before G4X SDVOC doesn't have its own detect register */
5355
5356                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5357                         DRM_DEBUG_KMS("probing SDVOC\n");
5358                         found = intel_sdvo_init(dev, SDVOC);
5359                 }
5360
5361                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5362
5363                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5364                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5365                                 intel_hdmi_init(dev, SDVOC);
5366                         }
5367                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5368                                 DRM_DEBUG_KMS("probing DP_C\n");
5369                                 intel_dp_init(dev, DP_C);
5370                         }
5371                 }
5372
5373                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5374                     (I915_READ(DP_D) & DP_DETECTED)) {
5375                         DRM_DEBUG_KMS("probing DP_D\n");
5376                         intel_dp_init(dev, DP_D);
5377                 }
5378         } else if (IS_GEN2(dev))
5379                 intel_dvo_init(dev);
5380
5381         if (SUPPORTS_TV(dev))
5382                 intel_tv_init(dev);
5383
5384         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5385                 encoder->base.possible_crtcs = encoder->crtc_mask;
5386                 encoder->base.possible_clones =
5387                         intel_encoder_clones(dev, encoder->clone_mask);
5388         }
5389 }
5390
5391 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5392 {
5393         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5394
5395         drm_framebuffer_cleanup(fb);
5396         drm_gem_object_unreference_unlocked(intel_fb->obj);
5397
5398         kfree(intel_fb);
5399 }
5400
5401 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5402                                                 struct drm_file *file_priv,
5403                                                 unsigned int *handle)
5404 {
5405         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5406         struct drm_gem_object *object = intel_fb->obj;
5407
5408         return drm_gem_handle_create(file_priv, object, handle);
5409 }
5410
5411 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5412         .destroy = intel_user_framebuffer_destroy,
5413         .create_handle = intel_user_framebuffer_create_handle,
5414 };
5415
5416 int intel_framebuffer_init(struct drm_device *dev,
5417                            struct intel_framebuffer *intel_fb,
5418                            struct drm_mode_fb_cmd *mode_cmd,
5419                            struct drm_gem_object *obj)
5420 {
5421         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5422         int ret;
5423
5424         if (obj_priv->tiling_mode == I915_TILING_Y)
5425                 return -EINVAL;
5426
5427         if (mode_cmd->pitch & 63)
5428                 return -EINVAL;
5429
5430         switch (mode_cmd->bpp) {
5431         case 8:
5432         case 16:
5433         case 24:
5434         case 32:
5435                 break;
5436         default:
5437                 return -EINVAL;
5438         }
5439
5440         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5441         if (ret) {
5442                 DRM_ERROR("framebuffer init failed %d\n", ret);
5443                 return ret;
5444         }
5445
5446         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5447         intel_fb->obj = obj;
5448         return 0;
5449 }
5450
5451 static struct drm_framebuffer *
5452 intel_user_framebuffer_create(struct drm_device *dev,
5453                               struct drm_file *filp,
5454                               struct drm_mode_fb_cmd *mode_cmd)
5455 {
5456         struct drm_gem_object *obj;
5457         struct intel_framebuffer *intel_fb;
5458         int ret;
5459
5460         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5461         if (!obj)
5462                 return ERR_PTR(-ENOENT);
5463
5464         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5465         if (!intel_fb)
5466                 return ERR_PTR(-ENOMEM);
5467
5468         ret = intel_framebuffer_init(dev, intel_fb,
5469                                      mode_cmd, obj);
5470         if (ret) {
5471                 drm_gem_object_unreference_unlocked(obj);
5472                 kfree(intel_fb);
5473                 return ERR_PTR(ret);
5474         }
5475
5476         return &intel_fb->base;
5477 }
5478
5479 static const struct drm_mode_config_funcs intel_mode_funcs = {
5480         .fb_create = intel_user_framebuffer_create,
5481         .output_poll_changed = intel_fb_output_poll_changed,
5482 };
5483
5484 static struct drm_gem_object *
5485 intel_alloc_context_page(struct drm_device *dev)
5486 {
5487         struct drm_gem_object *ctx;
5488         int ret;
5489
5490         ctx = i915_gem_alloc_object(dev, 4096);
5491         if (!ctx) {
5492                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5493                 return NULL;
5494         }
5495
5496         mutex_lock(&dev->struct_mutex);
5497         ret = i915_gem_object_pin(ctx, 4096);
5498         if (ret) {
5499                 DRM_ERROR("failed to pin power context: %d\n", ret);
5500                 goto err_unref;
5501         }
5502
5503         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5504         if (ret) {
5505                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5506                 goto err_unpin;
5507         }
5508         mutex_unlock(&dev->struct_mutex);
5509
5510         return ctx;
5511
5512 err_unpin:
5513         i915_gem_object_unpin(ctx);
5514 err_unref:
5515         drm_gem_object_unreference(ctx);
5516         mutex_unlock(&dev->struct_mutex);
5517         return NULL;
5518 }
5519
5520 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5521 {
5522         struct drm_i915_private *dev_priv = dev->dev_private;
5523         u16 rgvswctl;
5524
5525         rgvswctl = I915_READ16(MEMSWCTL);
5526         if (rgvswctl & MEMCTL_CMD_STS) {
5527                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5528                 return false; /* still busy with another command */
5529         }
5530
5531         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5532                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5533         I915_WRITE16(MEMSWCTL, rgvswctl);
5534         POSTING_READ16(MEMSWCTL);
5535
5536         rgvswctl |= MEMCTL_CMD_STS;
5537         I915_WRITE16(MEMSWCTL, rgvswctl);
5538
5539         return true;
5540 }
5541
5542 void ironlake_enable_drps(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         u32 rgvmodectl = I915_READ(MEMMODECTL);
5546         u8 fmax, fmin, fstart, vstart;
5547
5548         /* Enable temp reporting */
5549         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5550         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5551
5552         /* 100ms RC evaluation intervals */
5553         I915_WRITE(RCUPEI, 100000);
5554         I915_WRITE(RCDNEI, 100000);
5555
5556         /* Set max/min thresholds to 90ms and 80ms respectively */
5557         I915_WRITE(RCBMAXAVG, 90000);
5558         I915_WRITE(RCBMINAVG, 80000);
5559
5560         I915_WRITE(MEMIHYST, 1);
5561
5562         /* Set up min, max, and cur for interrupt handling */
5563         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5564         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5565         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5566                 MEMMODE_FSTART_SHIFT;
5567         fstart = fmax;
5568
5569         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5570                 PXVFREQ_PX_SHIFT;
5571
5572         dev_priv->fmax = fstart; /* IPS callback will increase this */
5573         dev_priv->fstart = fstart;
5574
5575         dev_priv->max_delay = fmax;
5576         dev_priv->min_delay = fmin;
5577         dev_priv->cur_delay = fstart;
5578
5579         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5580                          fstart);
5581
5582         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5583
5584         /*
5585          * Interrupts will be enabled in ironlake_irq_postinstall
5586          */
5587
5588         I915_WRITE(VIDSTART, vstart);
5589         POSTING_READ(VIDSTART);
5590
5591         rgvmodectl |= MEMMODE_SWMODE_EN;
5592         I915_WRITE(MEMMODECTL, rgvmodectl);
5593
5594         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5595                 DRM_ERROR("stuck trying to change perf mode\n");
5596         msleep(1);
5597
5598         ironlake_set_drps(dev, fstart);
5599
5600         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5601                 I915_READ(0x112e0);
5602         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5603         dev_priv->last_count2 = I915_READ(0x112f4);
5604         getrawmonotonic(&dev_priv->last_time2);
5605 }
5606
5607 void ironlake_disable_drps(struct drm_device *dev)
5608 {
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         u16 rgvswctl = I915_READ16(MEMSWCTL);
5611
5612         /* Ack interrupts, disable EFC interrupt */
5613         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5614         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5615         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5616         I915_WRITE(DEIIR, DE_PCU_EVENT);
5617         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5618
5619         /* Go back to the starting frequency */
5620         ironlake_set_drps(dev, dev_priv->fstart);
5621         msleep(1);
5622         rgvswctl |= MEMCTL_CMD_STS;
5623         I915_WRITE(MEMSWCTL, rgvswctl);
5624         msleep(1);
5625
5626 }
5627
5628 static unsigned long intel_pxfreq(u32 vidfreq)
5629 {
5630         unsigned long freq;
5631         int div = (vidfreq & 0x3f0000) >> 16;
5632         int post = (vidfreq & 0x3000) >> 12;
5633         int pre = (vidfreq & 0x7);
5634
5635         if (!pre)
5636                 return 0;
5637
5638         freq = ((div * 133333) / ((1<<post) * pre));
5639
5640         return freq;
5641 }
5642
5643 void intel_init_emon(struct drm_device *dev)
5644 {
5645         struct drm_i915_private *dev_priv = dev->dev_private;
5646         u32 lcfuse;
5647         u8 pxw[16];
5648         int i;
5649
5650         /* Disable to program */
5651         I915_WRITE(ECR, 0);
5652         POSTING_READ(ECR);
5653
5654         /* Program energy weights for various events */
5655         I915_WRITE(SDEW, 0x15040d00);
5656         I915_WRITE(CSIEW0, 0x007f0000);
5657         I915_WRITE(CSIEW1, 0x1e220004);
5658         I915_WRITE(CSIEW2, 0x04000004);
5659
5660         for (i = 0; i < 5; i++)
5661                 I915_WRITE(PEW + (i * 4), 0);
5662         for (i = 0; i < 3; i++)
5663                 I915_WRITE(DEW + (i * 4), 0);
5664
5665         /* Program P-state weights to account for frequency power adjustment */
5666         for (i = 0; i < 16; i++) {
5667                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5668                 unsigned long freq = intel_pxfreq(pxvidfreq);
5669                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5670                         PXVFREQ_PX_SHIFT;
5671                 unsigned long val;
5672
5673                 val = vid * vid;
5674                 val *= (freq / 1000);
5675                 val *= 255;
5676                 val /= (127*127*900);
5677                 if (val > 0xff)
5678                         DRM_ERROR("bad pxval: %ld\n", val);
5679                 pxw[i] = val;
5680         }
5681         /* Render standby states get 0 weight */
5682         pxw[14] = 0;
5683         pxw[15] = 0;
5684
5685         for (i = 0; i < 4; i++) {
5686                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5687                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5688                 I915_WRITE(PXW + (i * 4), val);
5689         }
5690
5691         /* Adjust magic regs to magic values (more experimental results) */
5692         I915_WRITE(OGW0, 0);
5693         I915_WRITE(OGW1, 0);
5694         I915_WRITE(EG0, 0x00007f00);
5695         I915_WRITE(EG1, 0x0000000e);
5696         I915_WRITE(EG2, 0x000e0000);
5697         I915_WRITE(EG3, 0x68000300);
5698         I915_WRITE(EG4, 0x42000000);
5699         I915_WRITE(EG5, 0x00140031);
5700         I915_WRITE(EG6, 0);
5701         I915_WRITE(EG7, 0);
5702
5703         for (i = 0; i < 8; i++)
5704                 I915_WRITE(PXWL + (i * 4), 0);
5705
5706         /* Enable PMON + select events */
5707         I915_WRITE(ECR, 0x80000019);
5708
5709         lcfuse = I915_READ(LCFUSE02);
5710
5711         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5712 }
5713
5714 void intel_init_clock_gating(struct drm_device *dev)
5715 {
5716         struct drm_i915_private *dev_priv = dev->dev_private;
5717
5718         /*
5719          * Disable clock gating reported to work incorrectly according to the
5720          * specs, but enable as much else as we can.
5721          */
5722         if (HAS_PCH_SPLIT(dev)) {
5723                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5724
5725                 if (IS_IRONLAKE(dev)) {
5726                         /* Required for FBC */
5727                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5728                         /* Required for CxSR */
5729                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5730
5731                         I915_WRITE(PCH_3DCGDIS0,
5732                                    MARIUNIT_CLOCK_GATE_DISABLE |
5733                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5734                 }
5735
5736                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5737
5738                 /*
5739                  * According to the spec the following bits should be set in
5740                  * order to enable memory self-refresh
5741                  * The bit 22/21 of 0x42004
5742                  * The bit 5 of 0x42020
5743                  * The bit 15 of 0x45000
5744                  */
5745                 if (IS_IRONLAKE(dev)) {
5746                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5747                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5748                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5749                         I915_WRITE(ILK_DSPCLK_GATE,
5750                                         (I915_READ(ILK_DSPCLK_GATE) |
5751                                                 ILK_DPARB_CLK_GATE));
5752                         I915_WRITE(DISP_ARB_CTL,
5753                                         (I915_READ(DISP_ARB_CTL) |
5754                                                 DISP_FBC_WM_DIS));
5755                 I915_WRITE(WM3_LP_ILK, 0);
5756                 I915_WRITE(WM2_LP_ILK, 0);
5757                 I915_WRITE(WM1_LP_ILK, 0);
5758                 }
5759                 /*
5760                  * Based on the document from hardware guys the following bits
5761                  * should be set unconditionally in order to enable FBC.
5762                  * The bit 22 of 0x42000
5763                  * The bit 22 of 0x42004
5764                  * The bit 7,8,9 of 0x42020.
5765                  */
5766                 if (IS_IRONLAKE_M(dev)) {
5767                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5768                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5769                                    ILK_FBCQ_DIS);
5770                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5771                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5772                                    ILK_DPARB_GATE);
5773                         I915_WRITE(ILK_DSPCLK_GATE,
5774                                    I915_READ(ILK_DSPCLK_GATE) |
5775                                    ILK_DPFC_DIS1 |
5776                                    ILK_DPFC_DIS2 |
5777                                    ILK_CLK_FBC);
5778                 }
5779                 return;
5780         } else if (IS_G4X(dev)) {
5781                 uint32_t dspclk_gate;
5782                 I915_WRITE(RENCLK_GATE_D1, 0);
5783                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5784                        GS_UNIT_CLOCK_GATE_DISABLE |
5785                        CL_UNIT_CLOCK_GATE_DISABLE);
5786                 I915_WRITE(RAMCLK_GATE_D, 0);
5787                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5788                         OVRUNIT_CLOCK_GATE_DISABLE |
5789                         OVCUNIT_CLOCK_GATE_DISABLE;
5790                 if (IS_GM45(dev))
5791                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5792                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5793         } else if (IS_CRESTLINE(dev)) {
5794                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5795                 I915_WRITE(RENCLK_GATE_D2, 0);
5796                 I915_WRITE(DSPCLK_GATE_D, 0);
5797                 I915_WRITE(RAMCLK_GATE_D, 0);
5798                 I915_WRITE16(DEUC, 0);
5799         } else if (IS_BROADWATER(dev)) {
5800                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5801                        I965_RCC_CLOCK_GATE_DISABLE |
5802                        I965_RCPB_CLOCK_GATE_DISABLE |
5803                        I965_ISC_CLOCK_GATE_DISABLE |
5804                        I965_FBC_CLOCK_GATE_DISABLE);
5805                 I915_WRITE(RENCLK_GATE_D2, 0);
5806         } else if (IS_GEN3(dev)) {
5807                 u32 dstate = I915_READ(D_STATE);
5808
5809                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5810                         DSTATE_DOT_CLOCK_GATING;
5811                 I915_WRITE(D_STATE, dstate);
5812         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5813                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5814         } else if (IS_I830(dev)) {
5815                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5816         }
5817
5818         /*
5819          * GPU can automatically power down the render unit if given a page
5820          * to save state.
5821          */
5822         if (IS_IRONLAKE_M(dev)) {
5823                 if (dev_priv->renderctx == NULL)
5824                         dev_priv->renderctx = intel_alloc_context_page(dev);
5825                 if (dev_priv->renderctx) {
5826                         struct drm_i915_gem_object *obj_priv;
5827                         obj_priv = to_intel_bo(dev_priv->renderctx);
5828                         if (obj_priv) {
5829                                 BEGIN_LP_RING(4);
5830                                 OUT_RING(MI_SET_CONTEXT);
5831                                 OUT_RING(obj_priv->gtt_offset |
5832                                                 MI_MM_SPACE_GTT |
5833                                                 MI_SAVE_EXT_STATE_EN |
5834                                                 MI_RESTORE_EXT_STATE_EN |
5835                                                 MI_RESTORE_INHIBIT);
5836                                 OUT_RING(MI_NOOP);
5837                                 OUT_RING(MI_FLUSH);
5838                                 ADVANCE_LP_RING();
5839                         }
5840                 } else
5841                         DRM_DEBUG_KMS("Failed to allocate render context."
5842                                        "Disable RC6\n");
5843         }
5844
5845         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5846                 struct drm_i915_gem_object *obj_priv = NULL;
5847
5848                 if (dev_priv->pwrctx) {
5849                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5850                 } else {
5851                         struct drm_gem_object *pwrctx;
5852
5853                         pwrctx = intel_alloc_context_page(dev);
5854                         if (pwrctx) {
5855                                 dev_priv->pwrctx = pwrctx;
5856                                 obj_priv = to_intel_bo(pwrctx);
5857                         }
5858                 }
5859
5860                 if (obj_priv) {
5861                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5862                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5863                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5864                 }
5865         }
5866 }
5867
5868 /* Set up chip specific display functions */
5869 static void intel_init_display(struct drm_device *dev)
5870 {
5871         struct drm_i915_private *dev_priv = dev->dev_private;
5872
5873         /* We always want a DPMS function */
5874         if (HAS_PCH_SPLIT(dev))
5875                 dev_priv->display.dpms = ironlake_crtc_dpms;
5876         else
5877                 dev_priv->display.dpms = i9xx_crtc_dpms;
5878
5879         if (I915_HAS_FBC(dev)) {
5880                 if (IS_IRONLAKE_M(dev)) {
5881                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5882                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5883                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5884                 } else if (IS_GM45(dev)) {
5885                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5886                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5887                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5888                 } else if (IS_CRESTLINE(dev)) {
5889                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5890                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5891                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5892                 }
5893                 /* 855GM needs testing */
5894         }
5895
5896         /* Returns the core display clock speed */
5897         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5898                 dev_priv->display.get_display_clock_speed =
5899                         i945_get_display_clock_speed;
5900         else if (IS_I915G(dev))
5901                 dev_priv->display.get_display_clock_speed =
5902                         i915_get_display_clock_speed;
5903         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5904                 dev_priv->display.get_display_clock_speed =
5905                         i9xx_misc_get_display_clock_speed;
5906         else if (IS_I915GM(dev))
5907                 dev_priv->display.get_display_clock_speed =
5908                         i915gm_get_display_clock_speed;
5909         else if (IS_I865G(dev))
5910                 dev_priv->display.get_display_clock_speed =
5911                         i865_get_display_clock_speed;
5912         else if (IS_I85X(dev))
5913                 dev_priv->display.get_display_clock_speed =
5914                         i855_get_display_clock_speed;
5915         else /* 852, 830 */
5916                 dev_priv->display.get_display_clock_speed =
5917                         i830_get_display_clock_speed;
5918
5919         /* For FIFO watermark updates */
5920         if (HAS_PCH_SPLIT(dev)) {
5921                 if (IS_IRONLAKE(dev)) {
5922                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5923                                 dev_priv->display.update_wm = ironlake_update_wm;
5924                         else {
5925                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5926                                               "Disable CxSR\n");
5927                                 dev_priv->display.update_wm = NULL;
5928                         }
5929                 } else
5930                         dev_priv->display.update_wm = NULL;
5931         } else if (IS_PINEVIEW(dev)) {
5932                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5933                                             dev_priv->is_ddr3,
5934                                             dev_priv->fsb_freq,
5935                                             dev_priv->mem_freq)) {
5936                         DRM_INFO("failed to find known CxSR latency "
5937                                  "(found ddr%s fsb freq %d, mem freq %d), "
5938                                  "disabling CxSR\n",
5939                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5940                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5941                         /* Disable CxSR and never update its watermark again */
5942                         pineview_disable_cxsr(dev);
5943                         dev_priv->display.update_wm = NULL;
5944                 } else
5945                         dev_priv->display.update_wm = pineview_update_wm;
5946         } else if (IS_G4X(dev))
5947                 dev_priv->display.update_wm = g4x_update_wm;
5948         else if (IS_GEN4(dev))
5949                 dev_priv->display.update_wm = i965_update_wm;
5950         else if (IS_GEN3(dev)) {
5951                 dev_priv->display.update_wm = i9xx_update_wm;
5952                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5953         } else if (IS_I85X(dev)) {
5954                 dev_priv->display.update_wm = i9xx_update_wm;
5955                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5956         } else {
5957                 dev_priv->display.update_wm = i830_update_wm;
5958                 if (IS_845G(dev))
5959                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5960                 else
5961                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5962         }
5963 }
5964
5965 /*
5966  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5967  * resume, or other times.  This quirk makes sure that's the case for
5968  * affected systems.
5969  */
5970 static void quirk_pipea_force (struct drm_device *dev)
5971 {
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973
5974         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5975         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5976 }
5977
5978 struct intel_quirk {
5979         int device;
5980         int subsystem_vendor;
5981         int subsystem_device;
5982         void (*hook)(struct drm_device *dev);
5983 };
5984
5985 struct intel_quirk intel_quirks[] = {
5986         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5987         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5988         /* HP Mini needs pipe A force quirk (LP: #322104) */
5989         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5990
5991         /* Thinkpad R31 needs pipe A force quirk */
5992         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5993         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5994         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5995
5996         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5997         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5998         /* ThinkPad X40 needs pipe A force quirk */
5999
6000         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6001         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6002
6003         /* 855 & before need to leave pipe A & dpll A up */
6004         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6005         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6006 };
6007
6008 static void intel_init_quirks(struct drm_device *dev)
6009 {
6010         struct pci_dev *d = dev->pdev;
6011         int i;
6012
6013         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6014                 struct intel_quirk *q = &intel_quirks[i];
6015
6016                 if (d->device == q->device &&
6017                     (d->subsystem_vendor == q->subsystem_vendor ||
6018                      q->subsystem_vendor == PCI_ANY_ID) &&
6019                     (d->subsystem_device == q->subsystem_device ||
6020                      q->subsystem_device == PCI_ANY_ID))
6021                         q->hook(dev);
6022         }
6023 }
6024
6025 /* Disable the VGA plane that we never use */
6026 static void i915_disable_vga(struct drm_device *dev)
6027 {
6028         struct drm_i915_private *dev_priv = dev->dev_private;
6029         u8 sr1;
6030         u32 vga_reg;
6031
6032         if (HAS_PCH_SPLIT(dev))
6033                 vga_reg = CPU_VGACNTRL;
6034         else
6035                 vga_reg = VGACNTRL;
6036
6037         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6038         outb(1, VGA_SR_INDEX);
6039         sr1 = inb(VGA_SR_DATA);
6040         outb(sr1 | 1<<5, VGA_SR_DATA);
6041         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6042         udelay(300);
6043
6044         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6045         POSTING_READ(vga_reg);
6046 }
6047
6048 void intel_modeset_init(struct drm_device *dev)
6049 {
6050         struct drm_i915_private *dev_priv = dev->dev_private;
6051         int i;
6052
6053         drm_mode_config_init(dev);
6054
6055         dev->mode_config.min_width = 0;
6056         dev->mode_config.min_height = 0;
6057
6058         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6059
6060         intel_init_quirks(dev);
6061
6062         intel_init_display(dev);
6063
6064         if (IS_GEN2(dev)) {
6065                 dev->mode_config.max_width = 2048;
6066                 dev->mode_config.max_height = 2048;
6067         } else if (IS_GEN3(dev)) {
6068                 dev->mode_config.max_width = 4096;
6069                 dev->mode_config.max_height = 4096;
6070         } else {
6071                 dev->mode_config.max_width = 8192;
6072                 dev->mode_config.max_height = 8192;
6073         }
6074
6075         /* set memory base */
6076         if (IS_GEN2(dev))
6077                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6078         else
6079                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6080
6081         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6082                 dev_priv->num_pipe = 2;
6083         else
6084                 dev_priv->num_pipe = 1;
6085         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6086                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6087
6088         for (i = 0; i < dev_priv->num_pipe; i++) {
6089                 intel_crtc_init(dev, i);
6090         }
6091
6092         intel_setup_outputs(dev);
6093
6094         intel_init_clock_gating(dev);
6095
6096         /* Just disable it once at startup */
6097         i915_disable_vga(dev);
6098
6099         if (IS_IRONLAKE_M(dev)) {
6100                 ironlake_enable_drps(dev);
6101                 intel_init_emon(dev);
6102         }
6103
6104         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6105         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6106                     (unsigned long)dev);
6107
6108         intel_setup_overlay(dev);
6109 }
6110
6111 void intel_modeset_cleanup(struct drm_device *dev)
6112 {
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114         struct drm_crtc *crtc;
6115         struct intel_crtc *intel_crtc;
6116
6117         mutex_lock(&dev->struct_mutex);
6118
6119         drm_kms_helper_poll_fini(dev);
6120         intel_fbdev_fini(dev);
6121
6122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6123                 /* Skip inactive CRTCs */
6124                 if (!crtc->fb)
6125                         continue;
6126
6127                 intel_crtc = to_intel_crtc(crtc);
6128                 intel_increase_pllclock(crtc);
6129         }
6130
6131         if (dev_priv->display.disable_fbc)
6132                 dev_priv->display.disable_fbc(dev);
6133
6134         if (dev_priv->renderctx) {
6135                 struct drm_i915_gem_object *obj_priv;
6136
6137                 obj_priv = to_intel_bo(dev_priv->renderctx);
6138                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6139                 I915_READ(CCID);
6140                 i915_gem_object_unpin(dev_priv->renderctx);
6141                 drm_gem_object_unreference(dev_priv->renderctx);
6142         }
6143
6144         if (dev_priv->pwrctx) {
6145                 struct drm_i915_gem_object *obj_priv;
6146
6147                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6148                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6149                 I915_READ(PWRCTXA);
6150                 i915_gem_object_unpin(dev_priv->pwrctx);
6151                 drm_gem_object_unreference(dev_priv->pwrctx);
6152         }
6153
6154         if (IS_IRONLAKE_M(dev))
6155                 ironlake_disable_drps(dev);
6156
6157         mutex_unlock(&dev->struct_mutex);
6158
6159         /* Disable the irq before mode object teardown, for the irq might
6160          * enqueue unpin/hotplug work. */
6161         drm_irq_uninstall(dev);
6162         cancel_work_sync(&dev_priv->hotplug_work);
6163
6164         /* Shut off idle work before the crtcs get freed. */
6165         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6166                 intel_crtc = to_intel_crtc(crtc);
6167                 del_timer_sync(&intel_crtc->idle_timer);
6168         }
6169         del_timer_sync(&dev_priv->idle_timer);
6170         cancel_work_sync(&dev_priv->idle_work);
6171
6172         drm_mode_config_cleanup(dev);
6173 }
6174
6175 /*
6176  * Return which encoder is currently attached for connector.
6177  */
6178 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6179 {
6180         return &intel_attached_encoder(connector)->base;
6181 }
6182
6183 void intel_connector_attach_encoder(struct intel_connector *connector,
6184                                     struct intel_encoder *encoder)
6185 {
6186         connector->encoder = encoder;
6187         drm_mode_connector_attach_encoder(&connector->base,
6188                                           &encoder->base);
6189 }
6190
6191 /*
6192  * set vga decode state - true == enable VGA decode
6193  */
6194 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6195 {
6196         struct drm_i915_private *dev_priv = dev->dev_private;
6197         u16 gmch_ctrl;
6198
6199         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6200         if (state)
6201                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6202         else
6203                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6204         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6205         return 0;
6206 }