drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/firewire.h>
  26 #include <linux/firewire-constants.h>
  27 #include <linux/gfp.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/pci.h>
  37 #include <linux/pci_ids.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/string.h>
  40
  41 #include <asm/byteorder.h>
  42 #include <asm/page.h>
  43 #include <asm/system.h>
  44
  45 #ifdef CONFIG_PPC_PMAC
  46 #include <asm/pmac_feature.h>
  47 #endif
  48
  49 #include "core.h"
  50 #include "ohci.h"
  51
  52 #define DESCRIPTOR_OUTPUT_MORE          0
  53 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  54 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  55 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  56 #define DESCRIPTOR_STATUS               (1 << 11)
  57 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  58 #define DESCRIPTOR_PING                 (1 << 7)
  59 #define DESCRIPTOR_YY                   (1 << 6)
  60 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  61 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  62 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  63 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  64 #define DESCRIPTOR_WAIT                 (3 << 0)
  65
  66 struct descriptor {
  67         __le16 req_count;
  68         __le16 control;
  69         __le32 data_address;
  70         __le32 branch_address;
  71         __le16 res_count;
  72         __le16 transfer_status;
  73 } __attribute__((aligned(16)));
  74
  75 #define CONTROL_SET(regs)       (regs)
  76 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  77 #define COMMAND_PTR(regs)       ((regs) + 12)
  78 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  79
  80 struct ar_buffer {
  81         struct descriptor descriptor;
  82         struct ar_buffer *next;
  83         __le32 data[0];
  84 };
  85
  86 struct ar_context {
  87         struct fw_ohci *ohci;
  88         struct ar_buffer *current_buffer;
  89         struct ar_buffer *last_buffer;
  90         void *pointer;
  91         u32 regs;
  92         struct tasklet_struct tasklet;
  93 };
  94
  95 struct context;
  96
  97 typedef int (*descriptor_callback_t)(struct context *ctx,
  98                                      struct descriptor *d,
  99                                      struct descriptor *last);
 100
 101 /*
 102  * A buffer that contains a block of DMA-able coherent memory used for
 103  * storing a portion of a DMA descriptor program.
 104  */
 105 struct descriptor_buffer {
 106         struct list_head list;
 107         dma_addr_t buffer_bus;
 108         size_t buffer_size;
 109         size_t used;
 110         struct descriptor buffer[0];
 111 };
 112
 113 struct context {
 114         struct fw_ohci *ohci;
 115         u32 regs;
 116         int total_allocation;
 117
 118         /*
 119          * List of page-sized buffers for storing DMA descriptors.
 120          * Head of list contains buffers in use and tail of list contains
 121          * free buffers.
 122          */
 123         struct list_head buffer_list;
 124
 125         /*
 126          * Pointer to a buffer inside buffer_list that contains the tail
 127          * end of the current DMA program.
 128          */
 129         struct descriptor_buffer *buffer_tail;
 130
 131         /*
 132          * The descriptor containing the branch address of the first
 133          * descriptor that has not yet been filled by the device.
 134          */
 135         struct descriptor *last;
 136
 137         /*
 138          * The last descriptor in the DMA program.  It contains the branch
 139          * address that must be updated upon appending a new descriptor.
 140          */
 141         struct descriptor *prev;
 142
 143         descriptor_callback_t callback;
 144
 145         struct tasklet_struct tasklet;
 146 };
 147
 148 #define IT_HEADER_SY(v)          ((v) <<  0)
 149 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 150 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 151 #define IT_HEADER_TAG(v)         ((v) << 14)
 152 #define IT_HEADER_SPEED(v)       ((v) << 16)
 153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 154
 155 struct iso_context {
 156         struct fw_iso_context base;
 157         struct context context;
 158         int excess_bytes;
 159         void *header;
 160         size_t header_length;
 161 };
 162
 163 #define CONFIG_ROM_SIZE 1024
 164
 165 struct fw_ohci {
 166         struct fw_card card;
 167
 168         __iomem char *registers;
 169         int node_id;
 170         int generation;
 171         int request_generation; /* for timestamping incoming requests */
 172         unsigned quirks;
 173
 174         /*
 175          * Spinlock for accessing fw_ohci data.  Never call out of
 176          * this driver with this lock held.
 177          */
 178         spinlock_t lock;
 179
 180         struct ar_context ar_request_ctx;
 181         struct ar_context ar_response_ctx;
 182         struct context at_request_ctx;
 183         struct context at_response_ctx;
 184
 185         u32 it_context_mask;
 186         struct iso_context *it_context_list;
 187         u64 ir_context_channels;
 188         u32 ir_context_mask;
 189         struct iso_context *ir_context_list;
 190
 191         __be32    *config_rom;
 192         dma_addr_t config_rom_bus;
 193         __be32    *next_config_rom;
 194         dma_addr_t next_config_rom_bus;
 195         __be32     next_header;
 196
 197         __le32    *self_id_cpu;
 198         dma_addr_t self_id_bus;
 199         struct tasklet_struct bus_reset_tasklet;
 200
 201         u32 self_id_buffer[512];
 202 };
 203
 204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 205 {
 206         return container_of(card, struct fw_ohci, card);
 207 }
 208
 209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 210 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 211 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 213 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 214 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 215
 216 #define CONTEXT_RUN     0x8000
 217 #define CONTEXT_WAKE    0x1000
 218 #define CONTEXT_DEAD    0x0800
 219 #define CONTEXT_ACTIVE  0x0400
 220
 221 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 222 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 223 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 224
 225 #define OHCI1394_REGISTER_SIZE          0x800
 226 #define OHCI_LOOP_COUNT                 500
 227 #define OHCI1394_PCI_HCI_Control        0x40
 228 #define SELF_ID_BUF_SIZE                0x800
 229 #define OHCI_TCODE_PHY_PACKET           0x0e
 230 #define OHCI_VERSION_1_1                0x010010
 231
 232 static char ohci_driver_name[] = KBUILD_MODNAME;
 233
 234 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 235 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 236
 237 #define QUIRK_CYCLE_TIMER               1
 238 #define QUIRK_RESET_PACKET              2
 239 #define QUIRK_BE_HEADERS                4
 240 #define QUIRK_NO_1394A                  8
 241 #define QUIRK_NO_MSI                    16
 242
 243 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 244 static const struct {
 245         unsigned short vendor, device, flags;
 246 } ohci_quirks[] = {
 247         {PCI_VENDOR_ID_TI,      PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
 248                                                             QUIRK_RESET_PACKET |
 249                                                             QUIRK_NO_1394A},
 250         {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
 251         {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 252         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
 253         {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 254         {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 255         {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
 256 };
 257
 258 /* This overrides anything that was found in ohci_quirks[]. */
 259 static int param_quirks;
 260 module_param_named(quirks, param_quirks, int, 0644);
 261 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 262         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 263         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 264         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 265         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 266         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 267         ")");
 268
 269 #define OHCI_PARAM_DEBUG_AT_AR          1
 270 #define OHCI_PARAM_DEBUG_SELFIDS        2
 271 #define OHCI_PARAM_DEBUG_IRQS           4
 272 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 273
 274 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 275
 276 static int param_debug;
 277 module_param_named(debug, param_debug, int, 0644);
 278 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 279         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 280         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 281         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 282         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 283         ", or a combination, or all = -1)");
 284
 285 static void log_irqs(u32 evt)
 286 {
 287         if (likely(!(param_debug &
 288                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 289                 return;
 290
 291         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 292             !(evt & OHCI1394_busReset))
 293                 return;
 294
 295         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 296             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 297             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 298             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 299             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 300             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 301             evt & OHCI1394_isochRx              ? " IR"                 : "",
 302             evt & OHCI1394_isochTx              ? " IT"                 : "",
 303             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 304             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 305             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 306             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 307             evt & OHCI1394_busReset             ? " busReset"           : "",
 308             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 309                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 310                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 311                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 312                     OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
 313                     OHCI1394_regAccessFail | OHCI1394_busReset)
 314                                                 ? " ?"                  : "");
 315 }
 316
 317 static const char *speed[] = {
 318         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 319 };
 320 static const char *power[] = {
 321         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 322         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 323 };
 324 static const char port[] = { '.', '-', 'p', 'c', };
 325
 326 static char _p(u32 *s, int shift)
 327 {
 328         return port[*s >> shift & 3];
 329 }
 330
 331 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 332 {
 333         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 334                 return;
 335
 336         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 337                   self_id_count, generation, node_id);
 338
 339         for (; self_id_count--; ++s)
 340                 if ((*s & 1 << 23) == 0)
 341                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 342                             "%s gc=%d %s %s%s%s\n",
 343                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 344                             speed[*s >> 14 & 3], *s >> 16 & 63,
 345                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 346                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 347                 else
 348                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 349                             *s, *s >> 24 & 63,
 350                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 351                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 352 }
 353
 354 static const char *evts[] = {
 355         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 356         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 357         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 358         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 359         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 360         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 361         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 362         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 363         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 364         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 365         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 366         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 367         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 368         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 369         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 370         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 371         [0x20] = "pending/cancelled",
 372 };
 373 static const char *tcodes[] = {
 374         [0x0] = "QW req",               [0x1] = "BW req",
 375         [0x2] = "W resp",               [0x3] = "-reserved-",
 376         [0x4] = "QR req",               [0x5] = "BR req",
 377         [0x6] = "QR resp",              [0x7] = "BR resp",
 378         [0x8] = "cycle start",          [0x9] = "Lk req",
 379         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 380         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 381         [0xe] = "link internal",        [0xf] = "-reserved-",
 382 };
 383 static const char *phys[] = {
 384         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 385         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 386 };
 387
 388 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 389 {
 390         int tcode = header[0] >> 4 & 0xf;
 391         char specific[12];
 392
 393         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 394                 return;
 395
 396         if (unlikely(evt >= ARRAY_SIZE(evts)))
 397                         evt = 0x1f;
 398
 399         if (evt == OHCI1394_evt_bus_reset) {
 400                 fw_notify("A%c evt_bus_reset, generation %d\n",
 401                     dir, (header[2] >> 16) & 0xff);
 402                 return;
 403         }
 404
 405         if (header[0] == ~header[1]) {
 406                 fw_notify("A%c %s, %s, %08x\n",
 407                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 408                 return;
 409         }
 410
 411         switch (tcode) {
 412         case 0x0: case 0x6: case 0x8:
 413                 snprintf(specific, sizeof(specific), " = %08x",
 414                          be32_to_cpu((__force __be32)header[3]));
 415                 break;
 416         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 417                 snprintf(specific, sizeof(specific), " %x,%x",
 418                          header[3] >> 16, header[3] & 0xffff);
 419                 break;
 420         default:
 421                 specific[0] = '\0';
 422         }
 423
 424         switch (tcode) {
 425         case 0xe: case 0xa:
 426                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 427                 break;
 428         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 429                 fw_notify("A%c spd %x tl %02x, "
 430                     "%04x -> %04x, %s, "
 431                     "%s, %04x%08x%s\n",
 432                     dir, speed, header[0] >> 10 & 0x3f,
 433                     header[1] >> 16, header[0] >> 16, evts[evt],
 434                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 435                 break;
 436         default:
 437                 fw_notify("A%c spd %x tl %02x, "
 438                     "%04x -> %04x, %s, "
 439                     "%s%s\n",
 440                     dir, speed, header[0] >> 10 & 0x3f,
 441                     header[1] >> 16, header[0] >> 16, evts[evt],
 442                     tcodes[tcode], specific);
 443         }
 444 }
 445
 446 #else
 447
 448 #define param_debug 0
 449 static inline void log_irqs(u32 evt) {}
 450 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 451 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 452
 453 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 454
 455 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 456 {
 457         writel(data, ohci->registers + offset);
 458 }
 459
 460 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 461 {
 462         return readl(ohci->registers + offset);
 463 }
 464
 465 static inline void flush_writes(const struct fw_ohci *ohci)
 466 {
 467         /* Do a dummy read to flush writes. */
 468         reg_read(ohci, OHCI1394_Version);
 469 }
 470
 471 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 472 {
 473         u32 val;
 474         int i;
 475
 476         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 477         for (i = 0; i < 3 + 100; i++) {
 478                 val = reg_read(ohci, OHCI1394_PhyControl);
 479                 if (val & OHCI1394_PhyControl_ReadDone)
 480                         return OHCI1394_PhyControl_ReadData(val);
 481
 482                 /*
 483                  * Try a few times without waiting.  Sleeping is necessary
 484                  * only when the link/PHY interface is busy.
 485                  */
 486                 if (i >= 3)
 487                         msleep(1);
 488         }
 489         fw_error("failed to read phy reg\n");
 490
 491         return -EBUSY;
 492 }
 493
 494 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 495 {
 496         int i;
 497
 498         reg_write(ohci, OHCI1394_PhyControl,
 499                   OHCI1394_PhyControl_Write(addr, val));
 500         for (i = 0; i < 3 + 100; i++) {
 501                 val = reg_read(ohci, OHCI1394_PhyControl);
 502                 if (!(val & OHCI1394_PhyControl_WritePending))
 503                         return 0;
 504
 505                 if (i >= 3)
 506                         msleep(1);
 507         }
 508         fw_error("failed to write phy reg\n");
 509
 510         return -EBUSY;
 511 }
 512
 513 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 514                                int clear_bits, int set_bits)
 515 {
 516         struct fw_ohci *ohci = fw_ohci(card);
 517         int ret;
 518
 519         ret = read_phy_reg(ohci, addr);
 520         if (ret < 0)
 521                 return ret;
 522
 523         /*
 524          * The interrupt status bits are cleared by writing a one bit.
 525          * Avoid clearing them unless explicitly requested in set_bits.
 526          */
 527         if (addr == 5)
 528                 clear_bits |= PHY_INT_STATUS_BITS;
 529
 530         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 531 }
 532
 533 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 534 {
 535         int ret;
 536
 537         ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
 538         if (ret < 0)
 539                 return ret;
 540
 541         return read_phy_reg(ohci, addr);
 542 }
 543
 544 static int ar_context_add_page(struct ar_context *ctx)
 545 {
 546         struct device *dev = ctx->ohci->card.device;
 547         struct ar_buffer *ab;
 548         dma_addr_t uninitialized_var(ab_bus);
 549         size_t offset;
 550
 551         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 552         if (ab == NULL)
 553                 return -ENOMEM;
 554
 555         ab->next = NULL;
 556         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 557         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 558                                                     DESCRIPTOR_STATUS |
 559                                                     DESCRIPTOR_BRANCH_ALWAYS);
 560         offset = offsetof(struct ar_buffer, data);
 561         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 562         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 563         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 564         ab->descriptor.branch_address = 0;
 565
 566         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 567         ctx->last_buffer->next = ab;
 568         ctx->last_buffer = ab;
 569
 570         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 571         flush_writes(ctx->ohci);
 572
 573         return 0;
 574 }
 575
 576 static void ar_context_release(struct ar_context *ctx)
 577 {
 578         struct ar_buffer *ab, *ab_next;
 579         size_t offset;
 580         dma_addr_t ab_bus;
 581
 582         for (ab = ctx->current_buffer; ab; ab = ab_next) {
 583                 ab_next = ab->next;
 584                 offset = offsetof(struct ar_buffer, data);
 585                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 586                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
 587                                   ab, ab_bus);
 588         }
 589 }
 590
 591 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 592 #define cond_le32_to_cpu(v) \
 593         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 594 #else
 595 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 596 #endif
 597
 598 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 599 {
 600         struct fw_ohci *ohci = ctx->ohci;
 601         struct fw_packet p;
 602         u32 status, length, tcode;
 603         int evt;
 604
 605         p.header[0] = cond_le32_to_cpu(buffer[0]);
 606         p.header[1] = cond_le32_to_cpu(buffer[1]);
 607         p.header[2] = cond_le32_to_cpu(buffer[2]);
 608
 609         tcode = (p.header[0] >> 4) & 0x0f;
 610         switch (tcode) {
 611         case TCODE_WRITE_QUADLET_REQUEST:
 612         case TCODE_READ_QUADLET_RESPONSE:
 613                 p.header[3] = (__force __u32) buffer[3];
 614                 p.header_length = 16;
 615                 p.payload_length = 0;
 616                 break;
 617
 618         case TCODE_READ_BLOCK_REQUEST :
 619                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 620                 p.header_length = 16;
 621                 p.payload_length = 0;
 622                 break;
 623
 624         case TCODE_WRITE_BLOCK_REQUEST:
 625         case TCODE_READ_BLOCK_RESPONSE:
 626         case TCODE_LOCK_REQUEST:
 627         case TCODE_LOCK_RESPONSE:
 628                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 629                 p.header_length = 16;
 630                 p.payload_length = p.header[3] >> 16;
 631                 break;
 632
 633         case TCODE_WRITE_RESPONSE:
 634         case TCODE_READ_QUADLET_REQUEST:
 635         case OHCI_TCODE_PHY_PACKET:
 636                 p.header_length = 12;
 637                 p.payload_length = 0;
 638                 break;
 639
 640         default:
 641                 /* FIXME: Stop context, discard everything, and restart? */
 642                 p.header_length = 0;
 643                 p.payload_length = 0;
 644         }
 645
 646         p.payload = (void *) buffer + p.header_length;
 647
 648         /* FIXME: What to do about evt_* errors? */
 649         length = (p.header_length + p.payload_length + 3) / 4;
 650         status = cond_le32_to_cpu(buffer[length]);
 651         evt    = (status >> 16) & 0x1f;
 652
 653         p.ack        = evt - 16;
 654         p.speed      = (status >> 21) & 0x7;
 655         p.timestamp  = status & 0xffff;
 656         p.generation = ohci->request_generation;
 657
 658         log_ar_at_event('R', p.speed, p.header, evt);
 659
 660         /*
 661          * The OHCI bus reset handler synthesizes a phy packet with
 662          * the new generation number when a bus reset happens (see
 663          * section 8.4.2.3).  This helps us determine when a request
 664          * was received and make sure we send the response in the same
 665          * generation.  We only need this for requests; for responses
 666          * we use the unique tlabel for finding the matching
 667          * request.
 668          *
 669          * Alas some chips sometimes emit bus reset packets with a
 670          * wrong generation.  We set the correct generation for these
 671          * at a slightly incorrect time (in bus_reset_tasklet).
 672          */
 673         if (evt == OHCI1394_evt_bus_reset) {
 674                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 675                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 676         } else if (ctx == &ohci->ar_request_ctx) {
 677                 fw_core_handle_request(&ohci->card, &p);
 678         } else {
 679                 fw_core_handle_response(&ohci->card, &p);
 680         }
 681
 682         return buffer + length + 1;
 683 }
 684
 685 static void ar_context_tasklet(unsigned long data)
 686 {
 687         struct ar_context *ctx = (struct ar_context *)data;
 688         struct fw_ohci *ohci = ctx->ohci;
 689         struct ar_buffer *ab;
 690         struct descriptor *d;
 691         void *buffer, *end;
 692
 693         ab = ctx->current_buffer;
 694         d = &ab->descriptor;
 695
 696         if (d->res_count == 0) {
 697                 size_t size, rest, offset;
 698                 dma_addr_t start_bus;
 699                 void *start;
 700
 701                 /*
 702                  * This descriptor is finished and we may have a
 703                  * packet split across this and the next buffer. We
 704                  * reuse the page for reassembling the split packet.
 705                  */
 706
 707                 offset = offsetof(struct ar_buffer, data);
 708                 start = buffer = ab;
 709                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 710
 711                 ab = ab->next;
 712                 d = &ab->descriptor;
 713                 size = buffer + PAGE_SIZE - ctx->pointer;
 714                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 715                 memmove(buffer, ctx->pointer, size);
 716                 memcpy(buffer + size, ab->data, rest);
 717                 ctx->current_buffer = ab;
 718                 ctx->pointer = (void *) ab->data + rest;
 719                 end = buffer + size + rest;
 720
 721                 while (buffer < end)
 722                         buffer = handle_ar_packet(ctx, buffer);
 723
 724                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
 725                                   start, start_bus);
 726                 ar_context_add_page(ctx);
 727         } else {
 728                 buffer = ctx->pointer;
 729                 ctx->pointer = end =
 730                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 731
 732                 while (buffer < end)
 733                         buffer = handle_ar_packet(ctx, buffer);
 734         }
 735 }
 736
 737 static int ar_context_init(struct ar_context *ctx,
 738                            struct fw_ohci *ohci, u32 regs)
 739 {
 740         struct ar_buffer ab;
 741
 742         ctx->regs        = regs;
 743         ctx->ohci        = ohci;
 744         ctx->last_buffer = &ab;
 745         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 746
 747         ar_context_add_page(ctx);
 748         ar_context_add_page(ctx);
 749         ctx->current_buffer = ab.next;
 750         ctx->pointer = ctx->current_buffer->data;
 751
 752         return 0;
 753 }
 754
 755 static void ar_context_run(struct ar_context *ctx)
 756 {
 757         struct ar_buffer *ab = ctx->current_buffer;
 758         dma_addr_t ab_bus;
 759         size_t offset;
 760
 761         offset = offsetof(struct ar_buffer, data);
 762         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 763
 764         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 765         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 766         flush_writes(ctx->ohci);
 767 }
 768
 769 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 770 {
 771         int b, key;
 772
 773         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 774         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 775
 776         /* figure out which descriptor the branch address goes in */
 777         if (z == 2 && (b == 3 || key == 2))
 778                 return d;
 779         else
 780                 return d + z - 1;
 781 }
 782
 783 static void context_tasklet(unsigned long data)
 784 {
 785         struct context *ctx = (struct context *) data;
 786         struct descriptor *d, *last;
 787         u32 address;
 788         int z;
 789         struct descriptor_buffer *desc;
 790
 791         desc = list_entry(ctx->buffer_list.next,
 792                         struct descriptor_buffer, list);
 793         last = ctx->last;
 794         while (last->branch_address != 0) {
 795                 struct descriptor_buffer *old_desc = desc;
 796                 address = le32_to_cpu(last->branch_address);
 797                 z = address & 0xf;
 798                 address &= ~0xf;
 799
 800                 /* If the branch address points to a buffer outside of the
 801                  * current buffer, advance to the next buffer. */
 802                 if (address < desc->buffer_bus ||
 803                                 address >= desc->buffer_bus + desc->used)
 804                         desc = list_entry(desc->list.next,
 805                                         struct descriptor_buffer, list);
 806                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 807                 last = find_branch_descriptor(d, z);
 808
 809                 if (!ctx->callback(ctx, d, last))
 810                         break;
 811
 812                 if (old_desc != desc) {
 813                         /* If we've advanced to the next buffer, move the
 814                          * previous buffer to the free list. */
 815                         unsigned long flags;
 816                         old_desc->used = 0;
 817                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 818                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 819                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 820                 }
 821                 ctx->last = last;
 822         }
 823 }
 824
 825 /*
 826  * Allocate a new buffer and add it to the list of free buffers for this
 827  * context.  Must be called with ohci->lock held.
 828  */
 829 static int context_add_buffer(struct context *ctx)
 830 {
 831         struct descriptor_buffer *desc;
 832         dma_addr_t uninitialized_var(bus_addr);
 833         int offset;
 834
 835         /*
 836          * 16MB of descriptors should be far more than enough for any DMA
 837          * program.  This will catch run-away userspace or DoS attacks.
 838          */
 839         if (ctx->total_allocation >= 16*1024*1024)
 840                 return -ENOMEM;
 841
 842         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 843                         &bus_addr, GFP_ATOMIC);
 844         if (!desc)
 845                 return -ENOMEM;
 846
 847         offset = (void *)&desc->buffer - (void *)desc;
 848         desc->buffer_size = PAGE_SIZE - offset;
 849         desc->buffer_bus = bus_addr + offset;
 850         desc->used = 0;
 851
 852         list_add_tail(&desc->list, &ctx->buffer_list);
 853         ctx->total_allocation += PAGE_SIZE;
 854
 855         return 0;
 856 }
 857
 858 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 859                         u32 regs, descriptor_callback_t callback)
 860 {
 861         ctx->ohci = ohci;
 862         ctx->regs = regs;
 863         ctx->total_allocation = 0;
 864
 865         INIT_LIST_HEAD(&ctx->buffer_list);
 866         if (context_add_buffer(ctx) < 0)
 867                 return -ENOMEM;
 868
 869         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 870                         struct descriptor_buffer, list);
 871
 872         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 873         ctx->callback = callback;
 874
 875         /*
 876          * We put a dummy descriptor in the buffer that has a NULL
 877          * branch address and looks like it's been sent.  That way we
 878          * have a descriptor to append DMA programs to.
 879          */
 880         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 881         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 882         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 883         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 884         ctx->last = ctx->buffer_tail->buffer;
 885         ctx->prev = ctx->buffer_tail->buffer;
 886
 887         return 0;
 888 }
 889
 890 static void context_release(struct context *ctx)
 891 {
 892         struct fw_card *card = &ctx->ohci->card;
 893         struct descriptor_buffer *desc, *tmp;
 894
 895         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 896                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 897                         desc->buffer_bus -
 898                         ((void *)&desc->buffer - (void *)desc));
 899 }
 900
 901 /* Must be called with ohci->lock held */
 902 static struct descriptor *context_get_descriptors(struct context *ctx,
 903                                                   int z, dma_addr_t *d_bus)
 904 {
 905         struct descriptor *d = NULL;
 906         struct descriptor_buffer *desc = ctx->buffer_tail;
 907
 908         if (z * sizeof(*d) > desc->buffer_size)
 909                 return NULL;
 910
 911         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 912                 /* No room for the descriptor in this buffer, so advance to the
 913                  * next one. */
 914
 915                 if (desc->list.next == &ctx->buffer_list) {
 916                         /* If there is no free buffer next in the list,
 917                          * allocate one. */
 918                         if (context_add_buffer(ctx) < 0)
 919                                 return NULL;
 920                 }
 921                 desc = list_entry(desc->list.next,
 922                                 struct descriptor_buffer, list);
 923                 ctx->buffer_tail = desc;
 924         }
 925
 926         d = desc->buffer + desc->used / sizeof(*d);
 927         memset(d, 0, z * sizeof(*d));
 928         *d_bus = desc->buffer_bus + desc->used;
 929
 930         return d;
 931 }
 932
 933 static void context_run(struct context *ctx, u32 extra)
 934 {
 935         struct fw_ohci *ohci = ctx->ohci;
 936
 937         reg_write(ohci, COMMAND_PTR(ctx->regs),
 938                   le32_to_cpu(ctx->last->branch_address));
 939         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 940         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 941         flush_writes(ohci);
 942 }
 943
 944 static void context_append(struct context *ctx,
 945                            struct descriptor *d, int z, int extra)
 946 {
 947         dma_addr_t d_bus;
 948         struct descriptor_buffer *desc = ctx->buffer_tail;
 949
 950         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 951
 952         desc->used += (z + extra) * sizeof(*d);
 953         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 954         ctx->prev = find_branch_descriptor(d, z);
 955
 956         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 957         flush_writes(ctx->ohci);
 958 }
 959
 960 static void context_stop(struct context *ctx)
 961 {
 962         u32 reg;
 963         int i;
 964
 965         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 966         flush_writes(ctx->ohci);
 967
 968         for (i = 0; i < 10; i++) {
 969                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 970                 if ((reg & CONTEXT_ACTIVE) == 0)
 971                         return;
 972
 973                 mdelay(1);
 974         }
 975         fw_error("Error: DMA context still active (0x%08x)\n", reg);
 976 }
 977
 978 struct driver_data {
 979         struct fw_packet *packet;
 980 };
 981
 982 /*
 983  * This function apppends a packet to the DMA queue for transmission.
 984  * Must always be called with the ochi->lock held to ensure proper
 985  * generation handling and locking around packet queue manipulation.
 986  */
 987 static int at_context_queue_packet(struct context *ctx,
 988                                    struct fw_packet *packet)
 989 {
 990         struct fw_ohci *ohci = ctx->ohci;
 991         dma_addr_t d_bus, uninitialized_var(payload_bus);
 992         struct driver_data *driver_data;
 993         struct descriptor *d, *last;
 994         __le32 *header;
 995         int z, tcode;
 996         u32 reg;
 997
 998         d = context_get_descriptors(ctx, 4, &d_bus);
 999         if (d == NULL) {
1000                 packet->ack = RCODE_SEND_ERROR;
1001                 return -1;
1002         }
1003
1004         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1005         d[0].res_count = cpu_to_le16(packet->timestamp);
1006
1007         /*
1008          * The DMA format for asyncronous link packets is different
1009          * from the IEEE1394 layout, so shift the fields around
1010          * accordingly.  If header_length is 8, it's a PHY packet, to
1011          * which we need to prepend an extra quadlet.
1012          */
1013
1014         header = (__le32 *) &d[1];
1015         switch (packet->header_length) {
1016         case 16:
1017         case 12:
1018                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1019                                         (packet->speed << 16));
1020                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1021                                         (packet->header[0] & 0xffff0000));
1022                 header[2] = cpu_to_le32(packet->header[2]);
1023
1024                 tcode = (packet->header[0] >> 4) & 0x0f;
1025                 if (TCODE_IS_BLOCK_PACKET(tcode))
1026                         header[3] = cpu_to_le32(packet->header[3]);
1027                 else
1028                         header[3] = (__force __le32) packet->header[3];
1029
1030                 d[0].req_count = cpu_to_le16(packet->header_length);
1031                 break;
1032
1033         case 8:
1034                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1035                                         (packet->speed << 16));
1036                 header[1] = cpu_to_le32(packet->header[0]);
1037                 header[2] = cpu_to_le32(packet->header[1]);
1038                 d[0].req_count = cpu_to_le16(12);
1039                 break;
1040
1041         case 4:
1042                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1043                                         (packet->speed << 16));
1044                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1045                 d[0].req_count = cpu_to_le16(8);
1046                 break;
1047
1048         default:
1049                 /* BUG(); */
1050                 packet->ack = RCODE_SEND_ERROR;
1051                 return -1;
1052         }
1053
1054         driver_data = (struct driver_data *) &d[3];
1055         driver_data->packet = packet;
1056         packet->driver_data = driver_data;
1057
1058         if (packet->payload_length > 0) {
1059                 payload_bus =
1060                         dma_map_single(ohci->card.device, packet->payload,
1061                                        packet->payload_length, DMA_TO_DEVICE);
1062                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1063                         packet->ack = RCODE_SEND_ERROR;
1064                         return -1;
1065                 }
1066                 packet->payload_bus     = payload_bus;
1067                 packet->payload_mapped  = true;
1068
1069                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1070                 d[2].data_address = cpu_to_le32(payload_bus);
1071                 last = &d[2];
1072                 z = 3;
1073         } else {
1074                 last = &d[0];
1075                 z = 2;
1076         }
1077
1078         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1079                                      DESCRIPTOR_IRQ_ALWAYS |
1080                                      DESCRIPTOR_BRANCH_ALWAYS);
1081
1082         /*
1083          * If the controller and packet generations don't match, we need to
1084          * bail out and try again.  If IntEvent.busReset is set, the AT context
1085          * is halted, so appending to the context and trying to run it is
1086          * futile.  Most controllers do the right thing and just flush the AT
1087          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1088          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1089          * up stalling out.  So we just bail out in software and try again
1090          * later, and everyone is happy.
1091          * FIXME: Document how the locking works.
1092          */
1093         if (ohci->generation != packet->generation ||
1094             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1095                 if (packet->payload_mapped)
1096                         dma_unmap_single(ohci->card.device, payload_bus,
1097                                          packet->payload_length, DMA_TO_DEVICE);
1098                 packet->ack = RCODE_GENERATION;
1099                 return -1;
1100         }
1101
1102         context_append(ctx, d, z, 4 - z);
1103
1104         /* If the context isn't already running, start it up. */
1105         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1106         if ((reg & CONTEXT_RUN) == 0)
1107                 context_run(ctx, 0);
1108
1109         return 0;
1110 }
1111
1112 static int handle_at_packet(struct context *context,
1113                             struct descriptor *d,
1114                             struct descriptor *last)
1115 {
1116         struct driver_data *driver_data;
1117         struct fw_packet *packet;
1118         struct fw_ohci *ohci = context->ohci;
1119         int evt;
1120
1121         if (last->transfer_status == 0)
1122                 /* This descriptor isn't done yet, stop iteration. */
1123                 return 0;
1124
1125         driver_data = (struct driver_data *) &d[3];
1126         packet = driver_data->packet;
1127         if (packet == NULL)
1128                 /* This packet was cancelled, just continue. */
1129                 return 1;
1130
1131         if (packet->payload_mapped)
1132                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1133                                  packet->payload_length, DMA_TO_DEVICE);
1134
1135         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1136         packet->timestamp = le16_to_cpu(last->res_count);
1137
1138         log_ar_at_event('T', packet->speed, packet->header, evt);
1139
1140         switch (evt) {
1141         case OHCI1394_evt_timeout:
1142                 /* Async response transmit timed out. */
1143                 packet->ack = RCODE_CANCELLED;
1144                 break;
1145
1146         case OHCI1394_evt_flushed:
1147                 /*
1148                  * The packet was flushed should give same error as
1149                  * when we try to use a stale generation count.
1150                  */
1151                 packet->ack = RCODE_GENERATION;
1152                 break;
1153
1154         case OHCI1394_evt_missing_ack:
1155                 /*
1156                  * Using a valid (current) generation count, but the
1157                  * node is not on the bus or not sending acks.
1158                  */
1159                 packet->ack = RCODE_NO_ACK;
1160                 break;
1161
1162         case ACK_COMPLETE + 0x10:
1163         case ACK_PENDING + 0x10:
1164         case ACK_BUSY_X + 0x10:
1165         case ACK_BUSY_A + 0x10:
1166         case ACK_BUSY_B + 0x10:
1167         case ACK_DATA_ERROR + 0x10:
1168         case ACK_TYPE_ERROR + 0x10:
1169                 packet->ack = evt - 0x10;
1170                 break;
1171
1172         default:
1173                 packet->ack = RCODE_SEND_ERROR;
1174                 break;
1175         }
1176
1177         packet->callback(packet, &ohci->card, packet->ack);
1178
1179         return 1;
1180 }
1181
1182 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1183 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1184 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1185 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1186 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1187
1188 static void handle_local_rom(struct fw_ohci *ohci,
1189                              struct fw_packet *packet, u32 csr)
1190 {
1191         struct fw_packet response;
1192         int tcode, length, i;
1193
1194         tcode = HEADER_GET_TCODE(packet->header[0]);
1195         if (TCODE_IS_BLOCK_PACKET(tcode))
1196                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1197         else
1198                 length = 4;
1199
1200         i = csr - CSR_CONFIG_ROM;
1201         if (i + length > CONFIG_ROM_SIZE) {
1202                 fw_fill_response(&response, packet->header,
1203                                  RCODE_ADDRESS_ERROR, NULL, 0);
1204         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1205                 fw_fill_response(&response, packet->header,
1206                                  RCODE_TYPE_ERROR, NULL, 0);
1207         } else {
1208                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1209                                  (void *) ohci->config_rom + i, length);
1210         }
1211
1212         fw_core_handle_response(&ohci->card, &response);
1213 }
1214
1215 static void handle_local_lock(struct fw_ohci *ohci,
1216                               struct fw_packet *packet, u32 csr)
1217 {
1218         struct fw_packet response;
1219         int tcode, length, ext_tcode, sel;
1220         __be32 *payload, lock_old;
1221         u32 lock_arg, lock_data;
1222
1223         tcode = HEADER_GET_TCODE(packet->header[0]);
1224         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1225         payload = packet->payload;
1226         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1227
1228         if (tcode == TCODE_LOCK_REQUEST &&
1229             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1230                 lock_arg = be32_to_cpu(payload[0]);
1231                 lock_data = be32_to_cpu(payload[1]);
1232         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1233                 lock_arg = 0;
1234                 lock_data = 0;
1235         } else {
1236                 fw_fill_response(&response, packet->header,
1237                                  RCODE_TYPE_ERROR, NULL, 0);
1238                 goto out;
1239         }
1240
1241         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1242         reg_write(ohci, OHCI1394_CSRData, lock_data);
1243         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1244         reg_write(ohci, OHCI1394_CSRControl, sel);
1245
1246         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1247                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1248         else
1249                 fw_notify("swap not done yet\n");
1250
1251         fw_fill_response(&response, packet->header,
1252                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1253  out:
1254         fw_core_handle_response(&ohci->card, &response);
1255 }
1256
1257 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1258 {
1259         u64 offset;
1260         u32 csr;
1261
1262         if (ctx == &ctx->ohci->at_request_ctx) {
1263                 packet->ack = ACK_PENDING;
1264                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1265         }
1266
1267         offset =
1268                 ((unsigned long long)
1269                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1270                 packet->header[2];
1271         csr = offset - CSR_REGISTER_BASE;
1272
1273         /* Handle config rom reads. */
1274         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1275                 handle_local_rom(ctx->ohci, packet, csr);
1276         else switch (csr) {
1277         case CSR_BUS_MANAGER_ID:
1278         case CSR_BANDWIDTH_AVAILABLE:
1279         case CSR_CHANNELS_AVAILABLE_HI:
1280         case CSR_CHANNELS_AVAILABLE_LO:
1281                 handle_local_lock(ctx->ohci, packet, csr);
1282                 break;
1283         default:
1284                 if (ctx == &ctx->ohci->at_request_ctx)
1285                         fw_core_handle_request(&ctx->ohci->card, packet);
1286                 else
1287                         fw_core_handle_response(&ctx->ohci->card, packet);
1288                 break;
1289         }
1290
1291         if (ctx == &ctx->ohci->at_response_ctx) {
1292                 packet->ack = ACK_COMPLETE;
1293                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1294         }
1295 }
1296
1297 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1298 {
1299         unsigned long flags;
1300         int ret;
1301
1302         spin_lock_irqsave(&ctx->ohci->lock, flags);
1303
1304         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1305             ctx->ohci->generation == packet->generation) {
1306                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1307                 handle_local_request(ctx, packet);
1308                 return;
1309         }
1310
1311         ret = at_context_queue_packet(ctx, packet);
1312         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1313
1314         if (ret < 0)
1315                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1316
1317 }
1318
1319 static void bus_reset_tasklet(unsigned long data)
1320 {
1321         struct fw_ohci *ohci = (struct fw_ohci *)data;
1322         int self_id_count, i, j, reg;
1323         int generation, new_generation;
1324         unsigned long flags;
1325         void *free_rom = NULL;
1326         dma_addr_t free_rom_bus = 0;
1327
1328         reg = reg_read(ohci, OHCI1394_NodeID);
1329         if (!(reg & OHCI1394_NodeID_idValid)) {
1330                 fw_notify("node ID not valid, new bus reset in progress\n");
1331                 return;
1332         }
1333         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1334                 fw_notify("malconfigured bus\n");
1335                 return;
1336         }
1337         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1338                                OHCI1394_NodeID_nodeNumber);
1339
1340         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1341         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1342                 fw_notify("inconsistent self IDs\n");
1343                 return;
1344         }
1345         /*
1346          * The count in the SelfIDCount register is the number of
1347          * bytes in the self ID receive buffer.  Since we also receive
1348          * the inverted quadlets and a header quadlet, we shift one
1349          * bit extra to get the actual number of self IDs.
1350          */
1351         self_id_count = (reg >> 3) & 0xff;
1352         if (self_id_count == 0 || self_id_count > 252) {
1353                 fw_notify("inconsistent self IDs\n");
1354                 return;
1355         }
1356         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1357         rmb();
1358
1359         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1360                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1361                         fw_notify("inconsistent self IDs\n");
1362                         return;
1363                 }
1364                 ohci->self_id_buffer[j] =
1365                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1366         }
1367         rmb();
1368
1369         /*
1370          * Check the consistency of the self IDs we just read.  The
1371          * problem we face is that a new bus reset can start while we
1372          * read out the self IDs from the DMA buffer. If this happens,
1373          * the DMA buffer will be overwritten with new self IDs and we
1374          * will read out inconsistent data.  The OHCI specification
1375          * (section 11.2) recommends a technique similar to
1376          * linux/seqlock.h, where we remember the generation of the
1377          * self IDs in the buffer before reading them out and compare
1378          * it to the current generation after reading them out.  If
1379          * the two generations match we know we have a consistent set
1380          * of self IDs.
1381          */
1382
1383         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1384         if (new_generation != generation) {
1385                 fw_notify("recursive bus reset detected, "
1386                           "discarding self ids\n");
1387                 return;
1388         }
1389
1390         /* FIXME: Document how the locking works. */
1391         spin_lock_irqsave(&ohci->lock, flags);
1392
1393         ohci->generation = generation;
1394         context_stop(&ohci->at_request_ctx);
1395         context_stop(&ohci->at_response_ctx);
1396         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1397
1398         if (ohci->quirks & QUIRK_RESET_PACKET)
1399                 ohci->request_generation = generation;
1400
1401         /*
1402          * This next bit is unrelated to the AT context stuff but we
1403          * have to do it under the spinlock also.  If a new config rom
1404          * was set up before this reset, the old one is now no longer
1405          * in use and we can free it. Update the config rom pointers
1406          * to point to the current config rom and clear the
1407          * next_config_rom pointer so a new udpate can take place.
1408          */
1409
1410         if (ohci->next_config_rom != NULL) {
1411                 if (ohci->next_config_rom != ohci->config_rom) {
1412                         free_rom      = ohci->config_rom;
1413                         free_rom_bus  = ohci->config_rom_bus;
1414                 }
1415                 ohci->config_rom      = ohci->next_config_rom;
1416                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1417                 ohci->next_config_rom = NULL;
1418
1419                 /*
1420                  * Restore config_rom image and manually update
1421                  * config_rom registers.  Writing the header quadlet
1422                  * will indicate that the config rom is ready, so we
1423                  * do that last.
1424                  */
1425                 reg_write(ohci, OHCI1394_BusOptions,
1426                           be32_to_cpu(ohci->config_rom[2]));
1427                 ohci->config_rom[0] = ohci->next_header;
1428                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1429                           be32_to_cpu(ohci->next_header));
1430         }
1431
1432 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1433         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1434         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1435 #endif
1436
1437         spin_unlock_irqrestore(&ohci->lock, flags);
1438
1439         if (free_rom)
1440                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1441                                   free_rom, free_rom_bus);
1442
1443         log_selfids(ohci->node_id, generation,
1444                     self_id_count, ohci->self_id_buffer);
1445
1446         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1447                                  self_id_count, ohci->self_id_buffer);
1448 }
1449
1450 static irqreturn_t irq_handler(int irq, void *data)
1451 {
1452         struct fw_ohci *ohci = data;
1453         u32 event, iso_event;
1454         int i;
1455
1456         event = reg_read(ohci, OHCI1394_IntEventClear);
1457
1458         if (!event || !~event)
1459                 return IRQ_NONE;
1460
1461         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1462         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1463         log_irqs(event);
1464
1465         if (event & OHCI1394_selfIDComplete)
1466                 tasklet_schedule(&ohci->bus_reset_tasklet);
1467
1468         if (event & OHCI1394_RQPkt)
1469                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1470
1471         if (event & OHCI1394_RSPkt)
1472                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1473
1474         if (event & OHCI1394_reqTxComplete)
1475                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1476
1477         if (event & OHCI1394_respTxComplete)
1478                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1479
1480         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1481         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1482
1483         while (iso_event) {
1484                 i = ffs(iso_event) - 1;
1485                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1486                 iso_event &= ~(1 << i);
1487         }
1488
1489         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1490         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1491
1492         while (iso_event) {
1493                 i = ffs(iso_event) - 1;
1494                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1495                 iso_event &= ~(1 << i);
1496         }
1497
1498         if (unlikely(event & OHCI1394_regAccessFail))
1499                 fw_error("Register access failure - "
1500                          "please notify linux1394-devel@lists.sf.net\n");
1501
1502         if (unlikely(event & OHCI1394_postedWriteErr))
1503                 fw_error("PCI posted write error\n");
1504
1505         if (unlikely(event & OHCI1394_cycleTooLong)) {
1506                 if (printk_ratelimit())
1507                         fw_notify("isochronous cycle too long\n");
1508                 reg_write(ohci, OHCI1394_LinkControlSet,
1509                           OHCI1394_LinkControl_cycleMaster);
1510         }
1511
1512         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1513                 /*
1514                  * We need to clear this event bit in order to make
1515                  * cycleMatch isochronous I/O work.  In theory we should
1516                  * stop active cycleMatch iso contexts now and restart
1517                  * them at least two cycles later.  (FIXME?)
1518                  */
1519                 if (printk_ratelimit())
1520                         fw_notify("isochronous cycle inconsistent\n");
1521         }
1522
1523         return IRQ_HANDLED;
1524 }
1525
1526 static int software_reset(struct fw_ohci *ohci)
1527 {
1528         int i;
1529
1530         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1531
1532         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1533                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1534                      OHCI1394_HCControl_softReset) == 0)
1535                         return 0;
1536                 msleep(1);
1537         }
1538
1539         return -EBUSY;
1540 }
1541
1542 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1543 {
1544         size_t size = length * 4;
1545
1546         memcpy(dest, src, size);
1547         if (size < CONFIG_ROM_SIZE)
1548                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1549 }
1550
1551 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1552 {
1553         bool enable_1394a;
1554         int ret, clear, set, offset;
1555
1556         /* Check if the driver should configure link and PHY. */
1557         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1558               OHCI1394_HCControl_programPhyEnable))
1559                 return 0;
1560
1561         /* Paranoia: check whether the PHY supports 1394a, too. */
1562         enable_1394a = false;
1563         ret = read_phy_reg(ohci, 2);
1564         if (ret < 0)
1565                 return ret;
1566         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1567                 ret = read_paged_phy_reg(ohci, 1, 8);
1568                 if (ret < 0)
1569                         return ret;
1570                 if (ret >= 1)
1571                         enable_1394a = true;
1572         }
1573
1574         if (ohci->quirks & QUIRK_NO_1394A)
1575                 enable_1394a = false;
1576
1577         /* Configure PHY and link consistently. */
1578         if (enable_1394a) {
1579                 clear = 0;
1580                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1581         } else {
1582                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1583                 set = 0;
1584         }
1585         ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1586         if (ret < 0)
1587                 return ret;
1588
1589         if (enable_1394a)
1590                 offset = OHCI1394_HCControlSet;
1591         else
1592                 offset = OHCI1394_HCControlClear;
1593         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1594
1595         /* Clean up: configuration has been taken care of. */
1596         reg_write(ohci, OHCI1394_HCControlClear,
1597                   OHCI1394_HCControl_programPhyEnable);
1598
1599         return 0;
1600 }
1601
1602 static int ohci_enable(struct fw_card *card,
1603                        const __be32 *config_rom, size_t length)
1604 {
1605         struct fw_ohci *ohci = fw_ohci(card);
1606         struct pci_dev *dev = to_pci_dev(card->device);
1607         u32 lps, irqs;
1608         int i, ret;
1609
1610         if (software_reset(ohci)) {
1611                 fw_error("Failed to reset ohci card.\n");
1612                 return -EBUSY;
1613         }
1614
1615         /*
1616          * Now enable LPS, which we need in order to start accessing
1617          * most of the registers.  In fact, on some cards (ALI M5251),
1618          * accessing registers in the SClk domain without LPS enabled
1619          * will lock up the machine.  Wait 50msec to make sure we have
1620          * full link enabled.  However, with some cards (well, at least
1621          * a JMicron PCIe card), we have to try again sometimes.
1622          */
1623         reg_write(ohci, OHCI1394_HCControlSet,
1624                   OHCI1394_HCControl_LPS |
1625                   OHCI1394_HCControl_postedWriteEnable);
1626         flush_writes(ohci);
1627
1628         for (lps = 0, i = 0; !lps && i < 3; i++) {
1629                 msleep(50);
1630                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1631                       OHCI1394_HCControl_LPS;
1632         }
1633
1634         if (!lps) {
1635                 fw_error("Failed to set Link Power Status\n");
1636                 return -EIO;
1637         }
1638
1639         reg_write(ohci, OHCI1394_HCControlClear,
1640                   OHCI1394_HCControl_noByteSwapData);
1641
1642         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1643         reg_write(ohci, OHCI1394_LinkControlClear,
1644                   OHCI1394_LinkControl_rcvPhyPkt);
1645         reg_write(ohci, OHCI1394_LinkControlSet,
1646                   OHCI1394_LinkControl_rcvSelfID |
1647                   OHCI1394_LinkControl_cycleTimerEnable |
1648                   OHCI1394_LinkControl_cycleMaster);
1649
1650         reg_write(ohci, OHCI1394_ATRetries,
1651                   OHCI1394_MAX_AT_REQ_RETRIES |
1652                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1653                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1654
1655         ar_context_run(&ohci->ar_request_ctx);
1656         ar_context_run(&ohci->ar_response_ctx);
1657
1658         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1659         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1660         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1661
1662         ret = configure_1394a_enhancements(ohci);
1663         if (ret < 0)
1664                 return ret;
1665
1666         /* Activate link_on bit and contender bit in our self ID packets.*/
1667         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1668         if (ret < 0)
1669                 return ret;
1670
1671         /*
1672          * When the link is not yet enabled, the atomic config rom
1673          * update mechanism described below in ohci_set_config_rom()
1674          * is not active.  We have to update ConfigRomHeader and
1675          * BusOptions manually, and the write to ConfigROMmap takes
1676          * effect immediately.  We tie this to the enabling of the
1677          * link, so we have a valid config rom before enabling - the
1678          * OHCI requires that ConfigROMhdr and BusOptions have valid
1679          * values before enabling.
1680          *
1681          * However, when the ConfigROMmap is written, some controllers
1682          * always read back quadlets 0 and 2 from the config rom to
1683          * the ConfigRomHeader and BusOptions registers on bus reset.
1684          * They shouldn't do that in this initial case where the link
1685          * isn't enabled.  This means we have to use the same
1686          * workaround here, setting the bus header to 0 and then write
1687          * the right values in the bus reset tasklet.
1688          */
1689
1690         if (config_rom) {
1691                 ohci->next_config_rom =
1692                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1693                                            &ohci->next_config_rom_bus,
1694                                            GFP_KERNEL);
1695                 if (ohci->next_config_rom == NULL)
1696                         return -ENOMEM;
1697
1698                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1699         } else {
1700                 /*
1701                  * In the suspend case, config_rom is NULL, which
1702                  * means that we just reuse the old config rom.
1703                  */
1704                 ohci->next_config_rom = ohci->config_rom;
1705                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1706         }
1707
1708         ohci->next_header = ohci->next_config_rom[0];
1709         ohci->next_config_rom[0] = 0;
1710         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1711         reg_write(ohci, OHCI1394_BusOptions,
1712                   be32_to_cpu(ohci->next_config_rom[2]));
1713         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1714
1715         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1716
1717         if (!(ohci->quirks & QUIRK_NO_MSI))
1718                 pci_enable_msi(dev);
1719         if (request_irq(dev->irq, irq_handler,
1720                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1721                         ohci_driver_name, ohci)) {
1722                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1723                 pci_disable_msi(dev);
1724                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1725                                   ohci->config_rom, ohci->config_rom_bus);
1726                 return -EIO;
1727         }
1728
1729         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1730                 OHCI1394_RQPkt | OHCI1394_RSPkt |
1731                 OHCI1394_isochTx | OHCI1394_isochRx |
1732                 OHCI1394_postedWriteErr |
1733                 OHCI1394_selfIDComplete |
1734                 OHCI1394_regAccessFail |
1735                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1736                 OHCI1394_masterIntEnable;
1737         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1738                 irqs |= OHCI1394_busReset;
1739         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1740
1741         reg_write(ohci, OHCI1394_HCControlSet,
1742                   OHCI1394_HCControl_linkEnable |
1743                   OHCI1394_HCControl_BIBimageValid);
1744         flush_writes(ohci);
1745
1746         /*
1747          * We are ready to go, initiate bus reset to finish the
1748          * initialization.
1749          */
1750
1751         fw_core_initiate_bus_reset(&ohci->card, 1);
1752
1753         return 0;
1754 }
1755
1756 static int ohci_set_config_rom(struct fw_card *card,
1757                                const __be32 *config_rom, size_t length)
1758 {
1759         struct fw_ohci *ohci;
1760         unsigned long flags;
1761         int ret = -EBUSY;
1762         __be32 *next_config_rom;
1763         dma_addr_t uninitialized_var(next_config_rom_bus);
1764
1765         ohci = fw_ohci(card);
1766
1767         /*
1768          * When the OHCI controller is enabled, the config rom update
1769          * mechanism is a bit tricky, but easy enough to use.  See
1770          * section 5.5.6 in the OHCI specification.
1771          *
1772          * The OHCI controller caches the new config rom address in a
1773          * shadow register (ConfigROMmapNext) and needs a bus reset
1774          * for the changes to take place.  When the bus reset is
1775          * detected, the controller loads the new values for the
1776          * ConfigRomHeader and BusOptions registers from the specified
1777          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1778          * shadow register. All automatically and atomically.
1779          *
1780          * Now, there's a twist to this story.  The automatic load of
1781          * ConfigRomHeader and BusOptions doesn't honor the
1782          * noByteSwapData bit, so with a be32 config rom, the
1783          * controller will load be32 values in to these registers
1784          * during the atomic update, even on litte endian
1785          * architectures.  The workaround we use is to put a 0 in the
1786          * header quadlet; 0 is endian agnostic and means that the
1787          * config rom isn't ready yet.  In the bus reset tasklet we
1788          * then set up the real values for the two registers.
1789          *
1790          * We use ohci->lock to avoid racing with the code that sets
1791          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1792          */
1793
1794         next_config_rom =
1795                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1796                                    &next_config_rom_bus, GFP_KERNEL);
1797         if (next_config_rom == NULL)
1798                 return -ENOMEM;
1799
1800         spin_lock_irqsave(&ohci->lock, flags);
1801
1802         if (ohci->next_config_rom == NULL) {
1803                 ohci->next_config_rom = next_config_rom;
1804                 ohci->next_config_rom_bus = next_config_rom_bus;
1805
1806                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1807
1808                 ohci->next_header = config_rom[0];
1809                 ohci->next_config_rom[0] = 0;
1810
1811                 reg_write(ohci, OHCI1394_ConfigROMmap,
1812                           ohci->next_config_rom_bus);
1813                 ret = 0;
1814         }
1815
1816         spin_unlock_irqrestore(&ohci->lock, flags);
1817
1818         /*
1819          * Now initiate a bus reset to have the changes take
1820          * effect. We clean up the old config rom memory and DMA
1821          * mappings in the bus reset tasklet, since the OHCI
1822          * controller could need to access it before the bus reset
1823          * takes effect.
1824          */
1825         if (ret == 0)
1826                 fw_core_initiate_bus_reset(&ohci->card, 1);
1827         else
1828                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1829                                   next_config_rom, next_config_rom_bus);
1830
1831         return ret;
1832 }
1833
1834 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1835 {
1836         struct fw_ohci *ohci = fw_ohci(card);
1837
1838         at_context_transmit(&ohci->at_request_ctx, packet);
1839 }
1840
1841 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1842 {
1843         struct fw_ohci *ohci = fw_ohci(card);
1844
1845         at_context_transmit(&ohci->at_response_ctx, packet);
1846 }
1847
1848 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1849 {
1850         struct fw_ohci *ohci = fw_ohci(card);
1851         struct context *ctx = &ohci->at_request_ctx;
1852         struct driver_data *driver_data = packet->driver_data;
1853         int ret = -ENOENT;
1854
1855         tasklet_disable(&ctx->tasklet);
1856
1857         if (packet->ack != 0)
1858                 goto out;
1859
1860         if (packet->payload_mapped)
1861                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1862                                  packet->payload_length, DMA_TO_DEVICE);
1863
1864         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1865         driver_data->packet = NULL;
1866         packet->ack = RCODE_CANCELLED;
1867         packet->callback(packet, &ohci->card, packet->ack);
1868         ret = 0;
1869  out:
1870         tasklet_enable(&ctx->tasklet);
1871
1872         return ret;
1873 }
1874
1875 static int ohci_enable_phys_dma(struct fw_card *card,
1876                                 int node_id, int generation)
1877 {
1878 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1879         return 0;
1880 #else
1881         struct fw_ohci *ohci = fw_ohci(card);
1882         unsigned long flags;
1883         int n, ret = 0;
1884
1885         /*
1886          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1887          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1888          */
1889
1890         spin_lock_irqsave(&ohci->lock, flags);
1891
1892         if (ohci->generation != generation) {
1893                 ret = -ESTALE;
1894                 goto out;
1895         }
1896
1897         /*
1898          * Note, if the node ID contains a non-local bus ID, physical DMA is
1899          * enabled for _all_ nodes on remote buses.
1900          */
1901
1902         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1903         if (n < 32)
1904                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1905         else
1906                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1907
1908         flush_writes(ohci);
1909  out:
1910         spin_unlock_irqrestore(&ohci->lock, flags);
1911
1912         return ret;
1913 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1914 }
1915
1916 static u32 cycle_timer_ticks(u32 cycle_timer)
1917 {
1918         u32 ticks;
1919
1920         ticks = cycle_timer & 0xfff;
1921         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1922         ticks += (3072 * 8000) * (cycle_timer >> 25);
1923
1924         return ticks;
1925 }
1926
1927 /*
1928  * Some controllers exhibit one or more of the following bugs when updating the
1929  * iso cycle timer register:
1930  *  - When the lowest six bits are wrapping around to zero, a read that happens
1931  *    at the same time will return garbage in the lowest ten bits.
1932  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1933  *    not incremented for about 60 ns.
1934  *  - Occasionally, the entire register reads zero.
1935  *
1936  * To catch these, we read the register three times and ensure that the
1937  * difference between each two consecutive reads is approximately the same, i.e.
1938  * less than twice the other.  Furthermore, any negative difference indicates an
1939  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1940  * execute, so we have enough precision to compute the ratio of the differences.)
1941  */
1942 static u32 get_cycle_time(struct fw_ohci *ohci)
1943 {
1944         u32 c0, c1, c2;
1945         u32 t0, t1, t2;
1946         s32 diff01, diff12;
1947         int i;
1948
1949         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1950
1951         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1952                 i = 0;
1953                 c1 = c2;
1954                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1955                 do {
1956                         c0 = c1;
1957                         c1 = c2;
1958                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1959                         t0 = cycle_timer_ticks(c0);
1960                         t1 = cycle_timer_ticks(c1);
1961                         t2 = cycle_timer_ticks(c2);
1962                         diff01 = t1 - t0;
1963                         diff12 = t2 - t1;
1964                 } while ((diff01 <= 0 || diff12 <= 0 ||
1965                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1966                          && i++ < 20);
1967         }
1968
1969         return c2;
1970 }
1971
1972 static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset)
1973 {
1974         struct fw_ohci *ohci = fw_ohci(card);
1975
1976         switch (csr_offset) {
1977         case CSR_NODE_IDS:
1978                 return reg_read(ohci, OHCI1394_NodeID) << 16;
1979
1980         case CSR_CYCLE_TIME:
1981                 return get_cycle_time(ohci);
1982
1983         default:
1984                 WARN_ON(1);
1985                 return 0;
1986         }
1987 }
1988
1989 static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
1990 {
1991         struct fw_ohci *ohci = fw_ohci(card);
1992
1993         switch (csr_offset) {
1994         case CSR_NODE_IDS:
1995                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
1996                 flush_writes(ohci);
1997                 break;
1998
1999         default:
2000                 WARN_ON(1);
2001                 break;
2002         }
2003 }
2004
2005 static void copy_iso_headers(struct iso_context *ctx, void *p)
2006 {
2007         int i = ctx->header_length;
2008
2009         if (i + ctx->base.header_size > PAGE_SIZE)
2010                 return;
2011
2012         /*
2013          * The iso header is byteswapped to little endian by
2014          * the controller, but the remaining header quadlets
2015          * are big endian.  We want to present all the headers
2016          * as big endian, so we have to swap the first quadlet.
2017          */
2018         if (ctx->base.header_size > 0)
2019                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2020         if (ctx->base.header_size > 4)
2021                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2022         if (ctx->base.header_size > 8)
2023                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2024         ctx->header_length += ctx->base.header_size;
2025 }
2026
2027 static int handle_ir_packet_per_buffer(struct context *context,
2028                                        struct descriptor *d,
2029                                        struct descriptor *last)
2030 {
2031         struct iso_context *ctx =
2032                 container_of(context, struct iso_context, context);
2033         struct descriptor *pd;
2034         __le32 *ir_header;
2035         void *p;
2036
2037         for (pd = d; pd <= last; pd++) {
2038                 if (pd->transfer_status)
2039                         break;
2040         }
2041         if (pd > last)
2042                 /* Descriptor(s) not done yet, stop iteration */
2043                 return 0;
2044
2045         p = last + 1;
2046         copy_iso_headers(ctx, p);
2047
2048         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2049                 ir_header = (__le32 *) p;
2050                 ctx->base.callback(&ctx->base,
2051                                    le32_to_cpu(ir_header[0]) & 0xffff,
2052                                    ctx->header_length, ctx->header,
2053                                    ctx->base.callback_data);
2054                 ctx->header_length = 0;
2055         }
2056
2057         return 1;
2058 }
2059
2060 static int handle_it_packet(struct context *context,
2061                             struct descriptor *d,
2062                             struct descriptor *last)
2063 {
2064         struct iso_context *ctx =
2065                 container_of(context, struct iso_context, context);
2066         int i;
2067         struct descriptor *pd;
2068
2069         for (pd = d; pd <= last; pd++)
2070                 if (pd->transfer_status)
2071                         break;
2072         if (pd > last)
2073                 /* Descriptor(s) not done yet, stop iteration */
2074                 return 0;
2075
2076         i = ctx->header_length;
2077         if (i + 4 < PAGE_SIZE) {
2078                 /* Present this value as big-endian to match the receive code */
2079                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2080                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2081                                 le16_to_cpu(pd->res_count));
2082                 ctx->header_length += 4;
2083         }
2084         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2085                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2086                                    ctx->header_length, ctx->header,
2087                                    ctx->base.callback_data);
2088                 ctx->header_length = 0;
2089         }
2090         return 1;
2091 }
2092
2093 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2094                                 int type, int channel, size_t header_size)
2095 {
2096         struct fw_ohci *ohci = fw_ohci(card);
2097         struct iso_context *ctx, *list;
2098         descriptor_callback_t callback;
2099         u64 *channels, dont_care = ~0ULL;
2100         u32 *mask, regs;
2101         unsigned long flags;
2102         int index, ret = -ENOMEM;
2103
2104         if (type == FW_ISO_CONTEXT_TRANSMIT) {
2105                 channels = &dont_care;
2106                 mask = &ohci->it_context_mask;
2107                 list = ohci->it_context_list;
2108                 callback = handle_it_packet;
2109         } else {
2110                 channels = &ohci->ir_context_channels;
2111                 mask = &ohci->ir_context_mask;
2112                 list = ohci->ir_context_list;
2113                 callback = handle_ir_packet_per_buffer;
2114         }
2115
2116         spin_lock_irqsave(&ohci->lock, flags);
2117         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2118         if (index >= 0) {
2119                 *channels &= ~(1ULL << channel);
2120                 *mask &= ~(1 << index);
2121         }
2122         spin_unlock_irqrestore(&ohci->lock, flags);
2123
2124         if (index < 0)
2125                 return ERR_PTR(-EBUSY);
2126
2127         if (type == FW_ISO_CONTEXT_TRANSMIT)
2128                 regs = OHCI1394_IsoXmitContextBase(index);
2129         else
2130                 regs = OHCI1394_IsoRcvContextBase(index);
2131
2132         ctx = &list[index];
2133         memset(ctx, 0, sizeof(*ctx));
2134         ctx->header_length = 0;
2135         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2136         if (ctx->header == NULL)
2137                 goto out;
2138
2139         ret = context_init(&ctx->context, ohci, regs, callback);
2140         if (ret < 0)
2141                 goto out_with_header;
2142
2143         return &ctx->base;
2144
2145  out_with_header:
2146         free_page((unsigned long)ctx->header);
2147  out:
2148         spin_lock_irqsave(&ohci->lock, flags);
2149         *mask |= 1 << index;
2150         spin_unlock_irqrestore(&ohci->lock, flags);
2151
2152         return ERR_PTR(ret);
2153 }
2154
2155 static int ohci_start_iso(struct fw_iso_context *base,
2156                           s32 cycle, u32 sync, u32 tags)
2157 {
2158         struct iso_context *ctx = container_of(base, struct iso_context, base);
2159         struct fw_ohci *ohci = ctx->context.ohci;
2160         u32 control, match;
2161         int index;
2162
2163         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2164                 index = ctx - ohci->it_context_list;
2165                 match = 0;
2166                 if (cycle >= 0)
2167                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2168                                 (cycle & 0x7fff) << 16;
2169
2170                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2171                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2172                 context_run(&ctx->context, match);
2173         } else {
2174                 index = ctx - ohci->ir_context_list;
2175                 control = IR_CONTEXT_ISOCH_HEADER;
2176                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2177                 if (cycle >= 0) {
2178                         match |= (cycle & 0x07fff) << 12;
2179                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2180                 }
2181
2182                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2183                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2184                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2185                 context_run(&ctx->context, control);
2186         }
2187
2188         return 0;
2189 }
2190
2191 static int ohci_stop_iso(struct fw_iso_context *base)
2192 {
2193         struct fw_ohci *ohci = fw_ohci(base->card);
2194         struct iso_context *ctx = container_of(base, struct iso_context, base);
2195         int index;
2196
2197         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2198                 index = ctx - ohci->it_context_list;
2199                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2200         } else {
2201                 index = ctx - ohci->ir_context_list;
2202                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2203         }
2204         flush_writes(ohci);
2205         context_stop(&ctx->context);
2206
2207         return 0;
2208 }
2209
2210 static void ohci_free_iso_context(struct fw_iso_context *base)
2211 {
2212         struct fw_ohci *ohci = fw_ohci(base->card);
2213         struct iso_context *ctx = container_of(base, struct iso_context, base);
2214         unsigned long flags;
2215         int index;
2216
2217         ohci_stop_iso(base);
2218         context_release(&ctx->context);
2219         free_page((unsigned long)ctx->header);
2220
2221         spin_lock_irqsave(&ohci->lock, flags);
2222
2223         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2224                 index = ctx - ohci->it_context_list;
2225                 ohci->it_context_mask |= 1 << index;
2226         } else {
2227                 index = ctx - ohci->ir_context_list;
2228                 ohci->ir_context_mask |= 1 << index;
2229                 ohci->ir_context_channels |= 1ULL << base->channel;
2230         }
2231
2232         spin_unlock_irqrestore(&ohci->lock, flags);
2233 }
2234
2235 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2236                                    struct fw_iso_packet *packet,
2237                                    struct fw_iso_buffer *buffer,
2238                                    unsigned long payload)
2239 {
2240         struct iso_context *ctx = container_of(base, struct iso_context, base);
2241         struct descriptor *d, *last, *pd;
2242         struct fw_iso_packet *p;
2243         __le32 *header;
2244         dma_addr_t d_bus, page_bus;
2245         u32 z, header_z, payload_z, irq;
2246         u32 payload_index, payload_end_index, next_page_index;
2247         int page, end_page, i, length, offset;
2248
2249         p = packet;
2250         payload_index = payload;
2251
2252         if (p->skip)
2253                 z = 1;
2254         else
2255                 z = 2;
2256         if (p->header_length > 0)
2257                 z++;
2258
2259         /* Determine the first page the payload isn't contained in. */
2260         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2261         if (p->payload_length > 0)
2262                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2263         else
2264                 payload_z = 0;
2265
2266         z += payload_z;
2267
2268         /* Get header size in number of descriptors. */
2269         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2270
2271         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2272         if (d == NULL)
2273                 return -ENOMEM;
2274
2275         if (!p->skip) {
2276                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2277                 d[0].req_count = cpu_to_le16(8);
2278                 /*
2279                  * Link the skip address to this descriptor itself.  This causes
2280                  * a context to skip a cycle whenever lost cycles or FIFO
2281                  * overruns occur, without dropping the data.  The application
2282                  * should then decide whether this is an error condition or not.
2283                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2284                  */
2285                 d[0].branch_address = cpu_to_le32(d_bus | z);
2286
2287                 header = (__le32 *) &d[1];
2288                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2289                                         IT_HEADER_TAG(p->tag) |
2290                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2291                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2292                                         IT_HEADER_SPEED(ctx->base.speed));
2293                 header[1] =
2294                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2295                                                           p->payload_length));
2296         }
2297
2298         if (p->header_length > 0) {
2299                 d[2].req_count    = cpu_to_le16(p->header_length);
2300                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2301                 memcpy(&d[z], p->header, p->header_length);
2302         }
2303
2304         pd = d + z - payload_z;
2305         payload_end_index = payload_index + p->payload_length;
2306         for (i = 0; i < payload_z; i++) {
2307                 page               = payload_index >> PAGE_SHIFT;
2308                 offset             = payload_index & ~PAGE_MASK;
2309                 next_page_index    = (page + 1) << PAGE_SHIFT;
2310                 length             =
2311                         min(next_page_index, payload_end_index) - payload_index;
2312                 pd[i].req_count    = cpu_to_le16(length);
2313
2314                 page_bus = page_private(buffer->pages[page]);
2315                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2316
2317                 payload_index += length;
2318         }
2319
2320         if (p->interrupt)
2321                 irq = DESCRIPTOR_IRQ_ALWAYS;
2322         else
2323                 irq = DESCRIPTOR_NO_IRQ;
2324
2325         last = z == 2 ? d : d + z - 1;
2326         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2327                                      DESCRIPTOR_STATUS |
2328                                      DESCRIPTOR_BRANCH_ALWAYS |
2329                                      irq);
2330
2331         context_append(&ctx->context, d, z, header_z);
2332
2333         return 0;
2334 }
2335
2336 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2337                                         struct fw_iso_packet *packet,
2338                                         struct fw_iso_buffer *buffer,
2339                                         unsigned long payload)
2340 {
2341         struct iso_context *ctx = container_of(base, struct iso_context, base);
2342         struct descriptor *d, *pd;
2343         struct fw_iso_packet *p = packet;
2344         dma_addr_t d_bus, page_bus;
2345         u32 z, header_z, rest;
2346         int i, j, length;
2347         int page, offset, packet_count, header_size, payload_per_buffer;
2348
2349         /*
2350          * The OHCI controller puts the isochronous header and trailer in the
2351          * buffer, so we need at least 8 bytes.
2352          */
2353         packet_count = p->header_length / ctx->base.header_size;
2354         header_size  = max(ctx->base.header_size, (size_t)8);
2355
2356         /* Get header size in number of descriptors. */
2357         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2358         page     = payload >> PAGE_SHIFT;
2359         offset   = payload & ~PAGE_MASK;
2360         payload_per_buffer = p->payload_length / packet_count;
2361
2362         for (i = 0; i < packet_count; i++) {
2363                 /* d points to the header descriptor */
2364                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2365                 d = context_get_descriptors(&ctx->context,
2366                                 z + header_z, &d_bus);
2367                 if (d == NULL)
2368                         return -ENOMEM;
2369
2370                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2371                                               DESCRIPTOR_INPUT_MORE);
2372                 if (p->skip && i == 0)
2373                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2374                 d->req_count    = cpu_to_le16(header_size);
2375                 d->res_count    = d->req_count;
2376                 d->transfer_status = 0;
2377                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2378
2379                 rest = payload_per_buffer;
2380                 pd = d;
2381                 for (j = 1; j < z; j++) {
2382                         pd++;
2383                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2384                                                   DESCRIPTOR_INPUT_MORE);
2385
2386                         if (offset + rest < PAGE_SIZE)
2387                                 length = rest;
2388                         else
2389                                 length = PAGE_SIZE - offset;
2390                         pd->req_count = cpu_to_le16(length);
2391                         pd->res_count = pd->req_count;
2392                         pd->transfer_status = 0;
2393
2394                         page_bus = page_private(buffer->pages[page]);
2395                         pd->data_address = cpu_to_le32(page_bus + offset);
2396
2397                         offset = (offset + length) & ~PAGE_MASK;
2398                         rest -= length;
2399                         if (offset == 0)
2400                                 page++;
2401                 }
2402                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2403                                           DESCRIPTOR_INPUT_LAST |
2404                                           DESCRIPTOR_BRANCH_ALWAYS);
2405                 if (p->interrupt && i == packet_count - 1)
2406                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2407
2408                 context_append(&ctx->context, d, z, header_z);
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int ohci_queue_iso(struct fw_iso_context *base,
2415                           struct fw_iso_packet *packet,
2416                           struct fw_iso_buffer *buffer,
2417                           unsigned long payload)
2418 {
2419         struct iso_context *ctx = container_of(base, struct iso_context, base);
2420         unsigned long flags;
2421         int ret;
2422
2423         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2424         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2425                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2426         else
2427                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2428                                                         buffer, payload);
2429         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2430
2431         return ret;
2432 }
2433
2434 static const struct fw_card_driver ohci_driver = {
2435         .enable                 = ohci_enable,
2436         .update_phy_reg         = ohci_update_phy_reg,
2437         .set_config_rom         = ohci_set_config_rom,
2438         .send_request           = ohci_send_request,
2439         .send_response          = ohci_send_response,
2440         .cancel_packet          = ohci_cancel_packet,
2441         .enable_phys_dma        = ohci_enable_phys_dma,
2442         .read_csr_reg           = ohci_read_csr_reg,
2443         .write_csr_reg          = ohci_write_csr_reg,
2444
2445         .allocate_iso_context   = ohci_allocate_iso_context,
2446         .free_iso_context       = ohci_free_iso_context,
2447         .queue_iso              = ohci_queue_iso,
2448         .start_iso              = ohci_start_iso,
2449         .stop_iso               = ohci_stop_iso,
2450 };
2451
2452 #ifdef CONFIG_PPC_PMAC
2453 static void pmac_ohci_on(struct pci_dev *dev)
2454 {
2455         if (machine_is(powermac)) {
2456                 struct device_node *ofn = pci_device_to_OF_node(dev);
2457
2458                 if (ofn) {
2459                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2460                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2461                 }
2462         }
2463 }
2464
2465 static void pmac_ohci_off(struct pci_dev *dev)
2466 {
2467         if (machine_is(powermac)) {
2468                 struct device_node *ofn = pci_device_to_OF_node(dev);
2469
2470                 if (ofn) {
2471                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2472                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2473                 }
2474         }
2475 }
2476 #else
2477 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2478 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2479 #endif /* CONFIG_PPC_PMAC */
2480
2481 static int __devinit pci_probe(struct pci_dev *dev,
2482                                const struct pci_device_id *ent)
2483 {
2484         struct fw_ohci *ohci;
2485         u32 bus_options, max_receive, link_speed, version, link_enh;
2486         u64 guid;
2487         int i, err, n_ir, n_it;
2488         size_t size;
2489
2490         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2491         if (ohci == NULL) {
2492                 err = -ENOMEM;
2493                 goto fail;
2494         }
2495
2496         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2497
2498         pmac_ohci_on(dev);
2499
2500         err = pci_enable_device(dev);
2501         if (err) {
2502                 fw_error("Failed to enable OHCI hardware\n");
2503                 goto fail_free;
2504         }
2505
2506         pci_set_master(dev);
2507         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2508         pci_set_drvdata(dev, ohci);
2509
2510         spin_lock_init(&ohci->lock);
2511
2512         tasklet_init(&ohci->bus_reset_tasklet,
2513                      bus_reset_tasklet, (unsigned long)ohci);
2514
2515         err = pci_request_region(dev, 0, ohci_driver_name);
2516         if (err) {
2517                 fw_error("MMIO resource unavailable\n");
2518                 goto fail_disable;
2519         }
2520
2521         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2522         if (ohci->registers == NULL) {
2523                 fw_error("Failed to remap registers\n");
2524                 err = -ENXIO;
2525                 goto fail_iomem;
2526         }
2527
2528         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2529                 if (ohci_quirks[i].vendor == dev->vendor &&
2530                     (ohci_quirks[i].device == dev->device ||
2531                      ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2532                         ohci->quirks = ohci_quirks[i].flags;
2533                         break;
2534                 }
2535         if (param_quirks)
2536                 ohci->quirks = param_quirks;
2537
2538         /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2539         if (dev->vendor == PCI_VENDOR_ID_TI) {
2540                 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2541
2542                 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2543                 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2544                 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2545
2546                 /* use priority arbitration for asynchronous responses */
2547                 link_enh |= TI_LinkEnh_enab_unfair;
2548
2549                 /* required for aPhyEnhanceEnable to work */
2550                 link_enh |= TI_LinkEnh_enab_accel;
2551
2552                 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2553         }
2554
2555         ar_context_init(&ohci->ar_request_ctx, ohci,
2556                         OHCI1394_AsReqRcvContextControlSet);
2557
2558         ar_context_init(&ohci->ar_response_ctx, ohci,
2559                         OHCI1394_AsRspRcvContextControlSet);
2560
2561         context_init(&ohci->at_request_ctx, ohci,
2562                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2563
2564         context_init(&ohci->at_response_ctx, ohci,
2565                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2566
2567         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2568         ohci->ir_context_channels = ~0ULL;
2569         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2570         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2571         n_ir = hweight32(ohci->ir_context_mask);
2572         size = sizeof(struct iso_context) * n_ir;
2573         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2574
2575         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2576         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2577         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2578         n_it = hweight32(ohci->it_context_mask);
2579         size = sizeof(struct iso_context) * n_it;
2580         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2581
2582         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2583                 err = -ENOMEM;
2584                 goto fail_contexts;
2585         }
2586
2587         /* self-id dma buffer allocation */
2588         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2589                                                SELF_ID_BUF_SIZE,
2590                                                &ohci->self_id_bus,
2591                                                GFP_KERNEL);
2592         if (ohci->self_id_cpu == NULL) {
2593                 err = -ENOMEM;
2594                 goto fail_contexts;
2595         }
2596
2597         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2598         max_receive = (bus_options >> 12) & 0xf;
2599         link_speed = bus_options & 0x7;
2600         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2601                 reg_read(ohci, OHCI1394_GUIDLo);
2602
2603         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2604         if (err)
2605                 goto fail_self_id;
2606
2607         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2608         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2609                   "%d IR + %d IT contexts, quirks 0x%x\n",
2610                   dev_name(&dev->dev), version >> 16, version & 0xff,
2611                   n_ir, n_it, ohci->quirks);
2612
2613         return 0;
2614
2615  fail_self_id:
2616         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2617                           ohci->self_id_cpu, ohci->self_id_bus);
2618  fail_contexts:
2619         kfree(ohci->ir_context_list);
2620         kfree(ohci->it_context_list);
2621         context_release(&ohci->at_response_ctx);
2622         context_release(&ohci->at_request_ctx);
2623         ar_context_release(&ohci->ar_response_ctx);
2624         ar_context_release(&ohci->ar_request_ctx);
2625         pci_iounmap(dev, ohci->registers);
2626  fail_iomem:
2627         pci_release_region(dev, 0);
2628  fail_disable:
2629         pci_disable_device(dev);
2630  fail_free:
2631         kfree(&ohci->card);
2632         pmac_ohci_off(dev);
2633  fail:
2634         if (err == -ENOMEM)
2635                 fw_error("Out of memory\n");
2636
2637         return err;
2638 }
2639
2640 static void pci_remove(struct pci_dev *dev)
2641 {
2642         struct fw_ohci *ohci;
2643
2644         ohci = pci_get_drvdata(dev);
2645         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2646         flush_writes(ohci);
2647         fw_core_remove_card(&ohci->card);
2648
2649         /*
2650          * FIXME: Fail all pending packets here, now that the upper
2651          * layers can't queue any more.
2652          */
2653
2654         software_reset(ohci);
2655         free_irq(dev->irq, ohci);
2656
2657         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2658                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2659                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2660         if (ohci->config_rom)
2661                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2662                                   ohci->config_rom, ohci->config_rom_bus);
2663         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2664                           ohci->self_id_cpu, ohci->self_id_bus);
2665         ar_context_release(&ohci->ar_request_ctx);
2666         ar_context_release(&ohci->ar_response_ctx);
2667         context_release(&ohci->at_request_ctx);
2668         context_release(&ohci->at_response_ctx);
2669         kfree(ohci->it_context_list);
2670         kfree(ohci->ir_context_list);
2671         pci_disable_msi(dev);
2672         pci_iounmap(dev, ohci->registers);
2673         pci_release_region(dev, 0);
2674         pci_disable_device(dev);
2675         kfree(&ohci->card);
2676         pmac_ohci_off(dev);
2677
2678         fw_notify("Removed fw-ohci device.\n");
2679 }
2680
2681 #ifdef CONFIG_PM
2682 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2683 {
2684         struct fw_ohci *ohci = pci_get_drvdata(dev);
2685         int err;
2686
2687         software_reset(ohci);
2688         free_irq(dev->irq, ohci);
2689         pci_disable_msi(dev);
2690         err = pci_save_state(dev);
2691         if (err) {
2692                 fw_error("pci_save_state failed\n");
2693                 return err;
2694         }
2695         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2696         if (err)
2697                 fw_error("pci_set_power_state failed with %d\n", err);
2698         pmac_ohci_off(dev);
2699
2700         return 0;
2701 }
2702
2703 static int pci_resume(struct pci_dev *dev)
2704 {
2705         struct fw_ohci *ohci = pci_get_drvdata(dev);
2706         int err;
2707
2708         pmac_ohci_on(dev);
2709         pci_set_power_state(dev, PCI_D0);
2710         pci_restore_state(dev);
2711         err = pci_enable_device(dev);
2712         if (err) {
2713                 fw_error("pci_enable_device failed\n");
2714                 return err;
2715         }
2716
2717         return ohci_enable(&ohci->card, NULL, 0);
2718 }
2719 #endif
2720
2721 static const struct pci_device_id pci_table[] = {
2722         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2723         { }
2724 };
2725
2726 MODULE_DEVICE_TABLE(pci, pci_table);
2727
2728 static struct pci_driver fw_ohci_pci_driver = {
2729         .name           = ohci_driver_name,
2730         .id_table       = pci_table,
2731         .probe          = pci_probe,
2732         .remove         = pci_remove,
2733 #ifdef CONFIG_PM
2734         .resume         = pci_resume,
2735         .suspend        = pci_suspend,
2736 #endif
2737 };
2738
2739 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2740 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2741 MODULE_LICENSE("GPL");
2742
2743 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2744 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2745 MODULE_ALIAS("ohci1394");
2746 #endif
2747
2748 static int __init fw_ohci_init(void)
2749 {
2750         return pci_register_driver(&fw_ohci_pci_driver);
2751 }
2752
2753 static void __exit fw_ohci_cleanup(void)
2754 {
2755         pci_unregister_driver(&fw_ohci_pci_driver);
2756 }
2757
2758 module_init(fw_ohci_init);
2759 module_exit(fw_ohci_cleanup);