drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 350 }
 351
 352 static const intel_limit_t intel_limits_i8xx_dvo = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i8xx_lvds = {
 367         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 368         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 369         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 370         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 371         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 372         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 373         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 374         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 375         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 376                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_sdvo = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 390                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 391         .find_pll = intel_find_best_PLL,
 392 };
 393
 394 static const intel_limit_t intel_limits_i9xx_lvds = {
 395         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 396         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 397         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 398         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 399         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 400         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 401         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 402         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 403         /* The single-channel range is 25-112Mhz, and dual-channel
 404          * is 80-224Mhz.  Prefer single channel as much as possible.
 405          */
 406         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 407                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 408         .find_pll = intel_find_best_PLL,
 409 };
 410
 411     /* below parameter and function is for G4X Chipset Family*/
 412 static const intel_limit_t intel_limits_g4x_sdvo = {
 413         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 414         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 416         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 417         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 418         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 419         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 420         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 421         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 422                  .p2_slow = G4X_P2_SDVO_SLOW,
 423                  .p2_fast = G4X_P2_SDVO_FAST
 424         },
 425         .find_pll = intel_g4x_find_best_PLL,
 426 };
 427
 428 static const intel_limit_t intel_limits_g4x_hdmi = {
 429         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 430         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 431         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 432         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 433         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 434         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 435         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 436         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 437         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 438                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 439                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 440         },
 441         .find_pll = intel_g4x_find_best_PLL,
 442 };
 443
 444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 445         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 447         .vco = { .min = G4X_VCO_MIN,
 448                  .max = G4X_VCO_MAX },
 449         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 451         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 453         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 454                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 455         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 456                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 457         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 458                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 459         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 460                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 461         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 462                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 463                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 464         },
 465         .find_pll = intel_g4x_find_best_PLL,
 466 };
 467
 468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 469         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 471         .vco = { .min = G4X_VCO_MIN,
 472                  .max = G4X_VCO_MAX },
 473         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 475         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 477         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 478                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 479         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 480                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 481         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 482                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 483         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 484                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 485         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 486                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 487                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 488         },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_g4x_display_port = {
 493         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 494                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 495         .vco = { .min = G4X_VCO_MIN,
 496                  .max = G4X_VCO_MAX},
 497         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 498                  .max = G4X_N_DISPLAY_PORT_MAX },
 499         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 500                  .max = G4X_M_DISPLAY_PORT_MAX },
 501         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 502                  .max = G4X_M1_DISPLAY_PORT_MAX },
 503         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 504                  .max = G4X_M2_DISPLAY_PORT_MAX },
 505         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 506                  .max = G4X_P_DISPLAY_PORT_MAX },
 507         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 508                  .max = G4X_P1_DISPLAY_PORT_MAX},
 509         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 510                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 511                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 512         .find_pll = intel_find_pll_g4x_dp,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_sdvo = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 525                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 526         .find_pll = intel_find_best_PLL,
 527 };
 528
 529 static const intel_limit_t intel_limits_pineview_lvds = {
 530         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 531         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 532         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 533         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 534         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 535         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 536         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 537         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 538         /* Pineview only supports single-channel mode. */
 539         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 540                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 541         .find_pll = intel_find_best_PLL,
 542 };
 543
 544 static const intel_limit_t intel_limits_ironlake_dac = {
 545         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 546         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 547         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 548         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 549         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 550         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 551         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 552         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 553         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 554                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 555                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 556         .find_pll = intel_g4x_find_best_PLL,
 557 };
 558
 559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 560         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 561         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 562         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 563         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 564         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 565         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 566         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 567         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 568         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 569                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 570                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 571         .find_pll = intel_g4x_find_best_PLL,
 572 };
 573
 574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 575         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 576         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 577         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 578         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 579         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 580         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 581         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 582         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 583         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 584                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 585                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 586         .find_pll = intel_g4x_find_best_PLL,
 587 };
 588
 589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 590         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 591         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 592         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 593         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 594         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 595         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 596         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 597         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 598         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 599                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 600                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 601         .find_pll = intel_g4x_find_best_PLL,
 602 };
 603
 604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 605         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 606         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 607         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 608         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 609         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 610         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 611         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 612         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 613         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 614                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 615                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 616         .find_pll = intel_g4x_find_best_PLL,
 617 };
 618
 619 static const intel_limit_t intel_limits_ironlake_display_port = {
 620         .dot = { .min = IRONLAKE_DOT_MIN,
 621                  .max = IRONLAKE_DOT_MAX },
 622         .vco = { .min = IRONLAKE_VCO_MIN,
 623                  .max = IRONLAKE_VCO_MAX},
 624         .n   = { .min = IRONLAKE_DP_N_MIN,
 625                  .max = IRONLAKE_DP_N_MAX },
 626         .m   = { .min = IRONLAKE_DP_M_MIN,
 627                  .max = IRONLAKE_DP_M_MAX },
 628         .m1  = { .min = IRONLAKE_M1_MIN,
 629                  .max = IRONLAKE_M1_MAX },
 630         .m2  = { .min = IRONLAKE_M2_MIN,
 631                  .max = IRONLAKE_M2_MAX },
 632         .p   = { .min = IRONLAKE_DP_P_MIN,
 633                  .max = IRONLAKE_DP_P_MAX },
 634         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 635                  .max = IRONLAKE_DP_P1_MAX},
 636         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 637                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 638                  .p2_fast = IRONLAKE_DP_P2_FAST },
 639         .find_pll = intel_find_pll_ironlake_dp,
 640 };
 641
 642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         const intel_limit_t *limit;
 647         int refclk = 120;
 648
 649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 650                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 651                         refclk = 100;
 652
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 774 {
 775         const intel_limit_t *limit = intel_limit (crtc);
 776         struct drm_device *dev = crtc->dev;
 777
 778         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 779                 INTELPllInvalid ("p1 out of range\n");
 780         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 781                 INTELPllInvalid ("p out of range\n");
 782         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 783                 INTELPllInvalid ("m2 out of range\n");
 784         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 785                 INTELPllInvalid ("m1 out of range\n");
 786         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 787                 INTELPllInvalid ("m1 <= m2\n");
 788         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 789                 INTELPllInvalid ("m out of range\n");
 790         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 791                 INTELPllInvalid ("n out of range\n");
 792         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 793                 INTELPllInvalid ("vco out of range\n");
 794         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 795          * connector, etc., rather than just a single range.
 796          */
 797         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 798                 INTELPllInvalid ("dot out of range\n");
 799
 800         return true;
 801 }
 802
 803 static bool
 804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 805                     int target, int refclk, intel_clock_t *best_clock)
 806
 807 {
 808         struct drm_device *dev = crtc->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         intel_clock_t clock;
 811         int err = target;
 812
 813         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 814             (I915_READ(LVDS)) != 0) {
 815                 /*
 816                  * For LVDS, if the panel is on, just rely on its current
 817                  * settings for dual-channel.  We haven't figured out how to
 818                  * reliably set up different single/dual channel state, if we
 819                  * even can.
 820                  */
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset (best_clock, 0, sizeof (*best_clock));
 834
 835         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 836              clock.m1++) {
 837                 for (clock.m2 = limit->m2.min;
 838                      clock.m2 <= limit->m2.max; clock.m2++) {
 839                         /* m1 is always 0 in Pineview */
 840                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 841                                 break;
 842                         for (clock.n = limit->n.min;
 843                              clock.n <= limit->n.max; clock.n++) {
 844                                 for (clock.p1 = limit->p1.min;
 845                                         clock.p1 <= limit->p1.max; clock.p1++) {
 846                                         int this_err;
 847
 848                                         intel_clock(dev, refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(crtc, &clock))
 851                                                 continue;
 852
 853                                         this_err = abs(clock.dot - target);
 854                                         if (this_err < err) {
 855                                                 *best_clock = clock;
 856                                                 err = this_err;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return (err != target);
 864 }
 865
 866 static bool
 867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 868                         int target, int refclk, intel_clock_t *best_clock)
 869 {
 870         struct drm_device *dev = crtc->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         intel_clock_t clock;
 873         int max_n;
 874         bool found;
 875         /* approximately equals target * 0.00585 */
 876         int err_most = (target >> 8) + (target >> 9);
 877         found = false;
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 int lvds_reg;
 881
 882                 if (HAS_PCH_SPLIT(dev))
 883                         lvds_reg = PCH_LVDS;
 884                 else
 885                         lvds_reg = LVDS;
 886                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 887                     LVDS_CLKB_POWER_UP)
 888                         clock.p2 = limit->p2.p2_fast;
 889                 else
 890                         clock.p2 = limit->p2.p2_slow;
 891         } else {
 892                 if (target < limit->p2.dot_limit)
 893                         clock.p2 = limit->p2.p2_slow;
 894                 else
 895                         clock.p2 = limit->p2.p2_fast;
 896         }
 897
 898         memset(best_clock, 0, sizeof(*best_clock));
 899         max_n = limit->n.max;
 900         /* based on hardware requirement, prefer smaller n to precision */
 901         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 902                 /* based on hardware requirement, prefere larger m1,m2 */
 903                 for (clock.m1 = limit->m1.max;
 904                      clock.m1 >= limit->m1.min; clock.m1--) {
 905                         for (clock.m2 = limit->m2.max;
 906                              clock.m2 >= limit->m2.min; clock.m2--) {
 907                                 for (clock.p1 = limit->p1.max;
 908                                      clock.p1 >= limit->p1.min; clock.p1--) {
 909                                         int this_err;
 910
 911                                         intel_clock(dev, refclk, &clock);
 912                                         if (!intel_PLL_is_valid(crtc, &clock))
 913                                                 continue;
 914                                         this_err = abs(clock.dot - target) ;
 915                                         if (this_err < err_most) {
 916                                                 *best_clock = clock;
 917                                                 err_most = this_err;
 918                                                 max_n = clock.n;
 919                                                 found = true;
 920                                         }
 921                                 }
 922                         }
 923                 }
 924         }
 925         return found;
 926 }
 927
 928 static bool
 929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 930                            int target, int refclk, intel_clock_t *best_clock)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         intel_clock_t clock;
 934
 935         /* return directly when it is eDP */
 936         if (HAS_eDP)
 937                 return true;
 938
 939         if (target < 200000) {
 940                 clock.n = 1;
 941                 clock.p1 = 2;
 942                 clock.p2 = 10;
 943                 clock.m1 = 12;
 944                 clock.m2 = 9;
 945         } else {
 946                 clock.n = 2;
 947                 clock.p1 = 1;
 948                 clock.p2 = 10;
 949                 clock.m1 = 14;
 950                 clock.m2 = 8;
 951         }
 952         intel_clock(dev, refclk, &clock);
 953         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 954         return true;
 955 }
 956
 957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 958 static bool
 959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 960                       int target, int refclk, intel_clock_t *best_clock)
 961 {
 962         intel_clock_t clock;
 963         if (target < 200000) {
 964                 clock.p1 = 2;
 965                 clock.p2 = 10;
 966                 clock.n = 2;
 967                 clock.m1 = 23;
 968                 clock.m2 = 8;
 969         } else {
 970                 clock.p1 = 1;
 971                 clock.p2 = 10;
 972                 clock.n = 1;
 973                 clock.m1 = 14;
 974                 clock.m2 = 2;
 975         }
 976         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 977         clock.p = (clock.p1 * clock.p2);
 978         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 979         clock.vco = 0;
 980         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 981         return true;
 982 }
 983
 984 /**
 985  * intel_wait_for_vblank - wait for vblank on a given pipe
 986  * @dev: drm device
 987  * @pipe: pipe to wait for
 988  *
 989  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 990  * mode setting code.
 991  */
 992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 996
 997         /* Clear existing vblank status. Note this will clear any other
 998          * sticky status fields as well.
 999          *
1000          * This races with i915_driver_irq_handler() with the result
1001          * that either function could miss a vblank event.  Here it is not
1002          * fatal, as we will either wait upon the next vblank interrupt or
1003          * timeout.  Generally speaking intel_wait_for_vblank() is only
1004          * called during modeset at which time the GPU should be idle and
1005          * should *not* be performing page flips and thus not waiting on
1006          * vblanks...
1007          * Currently, the result of us stealing a vblank from the irq
1008          * handler is that a single frame will be skipped during swapbuffers.
1009          */
1010         I915_WRITE(pipestat_reg,
1011                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013         /* Wait for vblank interrupt bit to set */
1014         if (wait_for(I915_READ(pipestat_reg) &
1015                      PIPE_VBLANK_INTERRUPT_STATUS,
1016                      50))
1017                 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /*
1021  * intel_wait_for_pipe_off - wait for pipe to turn off
1022  * @dev: drm device
1023  * @pipe: pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * On Gen4 and above:
1030  *   wait for the pipe register state bit to turn off
1031  *
1032  * Otherwise:
1033  *   wait for the display line value to settle (it usually
1034  *   ends up stopping at the start of the next frame).
1035  *
1036  */
1037 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1038 {
1039         struct drm_i915_private *dev_priv = dev->dev_private;
1040
1041         if (INTEL_INFO(dev)->gen >= 4) {
1042                 int reg = PIPECONF(pipe);
1043
1044                 /* Wait for the Pipe State to go off */
1045                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1046                              100))
1047                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1048         } else {
1049                 u32 last_line;
1050                 int reg = PIPEDSL(pipe);
1051                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1052
1053                 /* Wait for the display line to settle */
1054                 do {
1055                         last_line = I915_READ(reg) & DSL_LINEMASK;
1056                         mdelay(5);
1057                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1058                          time_after(timeout, jiffies));
1059                 if (time_after(jiffies, timeout))
1060                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1065 {
1066         struct drm_device *dev = crtc->dev;
1067         struct drm_i915_private *dev_priv = dev->dev_private;
1068         struct drm_framebuffer *fb = crtc->fb;
1069         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1070         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072         int plane, i;
1073         u32 fbc_ctl, fbc_ctl2;
1074
1075         if (fb->pitch == dev_priv->cfb_pitch &&
1076             obj_priv->fence_reg == dev_priv->cfb_fence &&
1077             intel_crtc->plane == dev_priv->cfb_plane &&
1078             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1079                 return;
1080
1081         i8xx_disable_fbc(dev);
1082
1083         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1084
1085         if (fb->pitch < dev_priv->cfb_pitch)
1086                 dev_priv->cfb_pitch = fb->pitch;
1087
1088         /* FBC_CTL wants 64B units */
1089         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1090         dev_priv->cfb_fence = obj_priv->fence_reg;
1091         dev_priv->cfb_plane = intel_crtc->plane;
1092         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1093
1094         /* Clear old tags */
1095         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1096                 I915_WRITE(FBC_TAG + (i * 4), 0);
1097
1098         /* Set it up... */
1099         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1100         if (obj_priv->tiling_mode != I915_TILING_NONE)
1101                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1102         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1103         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1104
1105         /* enable it... */
1106         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1107         if (IS_I945GM(dev))
1108                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1109         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1110         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1111         if (obj_priv->tiling_mode != I915_TILING_NONE)
1112                 fbc_ctl |= dev_priv->cfb_fence;
1113         I915_WRITE(FBC_CONTROL, fbc_ctl);
1114
1115         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1116                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1117 }
1118
1119 void i8xx_disable_fbc(struct drm_device *dev)
1120 {
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122         u32 fbc_ctl;
1123
1124         /* Disable compression */
1125         fbc_ctl = I915_READ(FBC_CONTROL);
1126         if ((fbc_ctl & FBC_CTL_EN) == 0)
1127                 return;
1128
1129         fbc_ctl &= ~FBC_CTL_EN;
1130         I915_WRITE(FBC_CONTROL, fbc_ctl);
1131
1132         /* Wait for compressing bit to clear */
1133         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1134                 DRM_DEBUG_KMS("FBC idle timed out\n");
1135                 return;
1136         }
1137
1138         DRM_DEBUG_KMS("disabled FBC\n");
1139 }
1140
1141 static bool i8xx_fbc_enabled(struct drm_device *dev)
1142 {
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144
1145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1146 }
1147
1148 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1149 {
1150         struct drm_device *dev = crtc->dev;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         struct drm_framebuffer *fb = crtc->fb;
1153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1154         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1156         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1157         unsigned long stall_watermark = 200;
1158         u32 dpfc_ctl;
1159
1160         dpfc_ctl = I915_READ(DPFC_CONTROL);
1161         if (dpfc_ctl & DPFC_CTL_EN) {
1162                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1163                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1164                     dev_priv->cfb_plane == intel_crtc->plane &&
1165                     dev_priv->cfb_y == crtc->y)
1166                         return;
1167
1168                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1169                 POSTING_READ(DPFC_CONTROL);
1170                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1171         }
1172
1173         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1174         dev_priv->cfb_fence = obj_priv->fence_reg;
1175         dev_priv->cfb_plane = intel_crtc->plane;
1176         dev_priv->cfb_y = crtc->y;
1177
1178         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1179         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1180                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1181                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1182         } else {
1183                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1184         }
1185
1186         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1187                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1188                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1189         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1190
1191         /* enable it... */
1192         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1193
1194         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1195 }
1196
1197 void g4x_disable_fbc(struct drm_device *dev)
1198 {
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         u32 dpfc_ctl;
1201
1202         /* Disable compression */
1203         dpfc_ctl = I915_READ(DPFC_CONTROL);
1204         if (dpfc_ctl & DPFC_CTL_EN) {
1205                 dpfc_ctl &= ~DPFC_CTL_EN;
1206                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1207
1208                 DRM_DEBUG_KMS("disabled FBC\n");
1209         }
1210 }
1211
1212 static bool g4x_fbc_enabled(struct drm_device *dev)
1213 {
1214         struct drm_i915_private *dev_priv = dev->dev_private;
1215
1216         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1217 }
1218
1219 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1220 {
1221         struct drm_device *dev = crtc->dev;
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         struct drm_framebuffer *fb = crtc->fb;
1224         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1225         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1227         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1228         unsigned long stall_watermark = 200;
1229         u32 dpfc_ctl;
1230
1231         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1232         if (dpfc_ctl & DPFC_CTL_EN) {
1233                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1234                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1235                     dev_priv->cfb_plane == intel_crtc->plane &&
1236                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1237                     dev_priv->cfb_y == crtc->y)
1238                         return;
1239
1240                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1241                 POSTING_READ(ILK_DPFC_CONTROL);
1242                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1243         }
1244
1245         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1246         dev_priv->cfb_fence = obj_priv->fence_reg;
1247         dev_priv->cfb_plane = intel_crtc->plane;
1248         dev_priv->cfb_offset = obj_priv->gtt_offset;
1249         dev_priv->cfb_y = crtc->y;
1250
1251         dpfc_ctl &= DPFC_RESERVED;
1252         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1253         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1254                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1255                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1256         } else {
1257                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1258         }
1259
1260         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1261                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1262                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1263         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1264         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1265         /* enable it... */
1266         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1267
1268         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1269 }
1270
1271 void ironlake_disable_fbc(struct drm_device *dev)
1272 {
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         u32 dpfc_ctl;
1275
1276         /* Disable compression */
1277         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1278         if (dpfc_ctl & DPFC_CTL_EN) {
1279                 dpfc_ctl &= ~DPFC_CTL_EN;
1280                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1281
1282                 DRM_DEBUG_KMS("disabled FBC\n");
1283         }
1284 }
1285
1286 static bool ironlake_fbc_enabled(struct drm_device *dev)
1287 {
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289
1290         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1291 }
1292
1293 bool intel_fbc_enabled(struct drm_device *dev)
1294 {
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296
1297         if (!dev_priv->display.fbc_enabled)
1298                 return false;
1299
1300         return dev_priv->display.fbc_enabled(dev);
1301 }
1302
1303 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1304 {
1305         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1306
1307         if (!dev_priv->display.enable_fbc)
1308                 return;
1309
1310         dev_priv->display.enable_fbc(crtc, interval);
1311 }
1312
1313 void intel_disable_fbc(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316
1317         if (!dev_priv->display.disable_fbc)
1318                 return;
1319
1320         dev_priv->display.disable_fbc(dev);
1321 }
1322
1323 /**
1324  * intel_update_fbc - enable/disable FBC as needed
1325  * @dev: the drm_device
1326  *
1327  * Set up the framebuffer compression hardware at mode set time.  We
1328  * enable it if possible:
1329  *   - plane A only (on pre-965)
1330  *   - no pixel mulitply/line duplication
1331  *   - no alpha buffer discard
1332  *   - no dual wide
1333  *   - framebuffer <= 2048 in width, 1536 in height
1334  *
1335  * We can't assume that any compression will take place (worst case),
1336  * so the compressed buffer has to be the same size as the uncompressed
1337  * one.  It also must reside (along with the line length buffer) in
1338  * stolen memory.
1339  *
1340  * We need to enable/disable FBC on a global basis.
1341  */
1342 static void intel_update_fbc(struct drm_device *dev)
1343 {
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         struct drm_crtc *crtc = NULL, *tmp_crtc;
1346         struct intel_crtc *intel_crtc;
1347         struct drm_framebuffer *fb;
1348         struct intel_framebuffer *intel_fb;
1349         struct drm_i915_gem_object *obj_priv;
1350
1351         DRM_DEBUG_KMS("\n");
1352
1353         if (!i915_powersave)
1354                 return;
1355
1356         if (!I915_HAS_FBC(dev))
1357                 return;
1358
1359         /*
1360          * If FBC is already on, we just have to verify that we can
1361          * keep it that way...
1362          * Need to disable if:
1363          *   - more than one pipe is active
1364          *   - changing FBC params (stride, fence, mode)
1365          *   - new fb is too large to fit in compressed buffer
1366          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1367          */
1368         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1369                 if (tmp_crtc->enabled) {
1370                         if (crtc) {
1371                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1372                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1373                                 goto out_disable;
1374                         }
1375                         crtc = tmp_crtc;
1376                 }
1377         }
1378
1379         if (!crtc || crtc->fb == NULL) {
1380                 DRM_DEBUG_KMS("no output, disabling\n");
1381                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1382                 goto out_disable;
1383         }
1384
1385         intel_crtc = to_intel_crtc(crtc);
1386         fb = crtc->fb;
1387         intel_fb = to_intel_framebuffer(fb);
1388         obj_priv = to_intel_bo(intel_fb->obj);
1389
1390         if (intel_fb->obj->size > dev_priv->cfb_size) {
1391                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1392                               "compression\n");
1393                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1394                 goto out_disable;
1395         }
1396         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1397             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1398                 DRM_DEBUG_KMS("mode incompatible with compression, "
1399                               "disabling\n");
1400                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1401                 goto out_disable;
1402         }
1403         if ((crtc->mode.hdisplay > 2048) ||
1404             (crtc->mode.vdisplay > 1536)) {
1405                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1406                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1407                 goto out_disable;
1408         }
1409         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1410                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1411                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1412                 goto out_disable;
1413         }
1414         if (obj_priv->tiling_mode != I915_TILING_X) {
1415                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1416                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1417                 goto out_disable;
1418         }
1419
1420         /* If the kernel debugger is active, always disable compression */
1421         if (in_dbg_master())
1422                 goto out_disable;
1423
1424         intel_enable_fbc(crtc, 500);
1425         return;
1426
1427 out_disable:
1428         /* Multiple disables should be harmless */
1429         if (intel_fbc_enabled(dev)) {
1430                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1431                 intel_disable_fbc(dev);
1432         }
1433 }
1434
1435 int
1436 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1437                            struct drm_gem_object *obj,
1438                            bool pipelined)
1439 {
1440         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1441         u32 alignment;
1442         int ret;
1443
1444         switch (obj_priv->tiling_mode) {
1445         case I915_TILING_NONE:
1446                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1447                         alignment = 128 * 1024;
1448                 else if (INTEL_INFO(dev)->gen >= 4)
1449                         alignment = 4 * 1024;
1450                 else
1451                         alignment = 64 * 1024;
1452                 break;
1453         case I915_TILING_X:
1454                 /* pin() will align the object as required by fence */
1455                 alignment = 0;
1456                 break;
1457         case I915_TILING_Y:
1458                 /* FIXME: Is this true? */
1459                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1460                 return -EINVAL;
1461         default:
1462                 BUG();
1463         }
1464
1465         ret = i915_gem_object_pin(obj, alignment);
1466         if (ret)
1467                 return ret;
1468
1469         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1470         if (ret)
1471                 goto err_unpin;
1472
1473         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1474          * fence, whereas 965+ only requires a fence if using
1475          * framebuffer compression.  For simplicity, we always install
1476          * a fence as the cost is not that onerous.
1477          */
1478         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1479             obj_priv->tiling_mode != I915_TILING_NONE) {
1480                 ret = i915_gem_object_get_fence_reg(obj, false);
1481                 if (ret)
1482                         goto err_unpin;
1483         }
1484
1485         return 0;
1486
1487 err_unpin:
1488         i915_gem_object_unpin(obj);
1489         return ret;
1490 }
1491
1492 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1493 static int
1494 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1495                            int x, int y, int enter)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1500         struct intel_framebuffer *intel_fb;
1501         struct drm_i915_gem_object *obj_priv;
1502         struct drm_gem_object *obj;
1503         int plane = intel_crtc->plane;
1504         unsigned long Start, Offset;
1505         u32 dspcntr;
1506         u32 reg;
1507
1508         switch (plane) {
1509         case 0:
1510         case 1:
1511                 break;
1512         default:
1513                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1514                 return -EINVAL;
1515         }
1516
1517         intel_fb = to_intel_framebuffer(fb);
1518         obj = intel_fb->obj;
1519         obj_priv = to_intel_bo(obj);
1520
1521         reg = DSPCNTR(plane);
1522         dspcntr = I915_READ(reg);
1523         /* Mask out pixel format bits in case we change it */
1524         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1525         switch (fb->bits_per_pixel) {
1526         case 8:
1527                 dspcntr |= DISPPLANE_8BPP;
1528                 break;
1529         case 16:
1530                 if (fb->depth == 15)
1531                         dspcntr |= DISPPLANE_15_16BPP;
1532                 else
1533                         dspcntr |= DISPPLANE_16BPP;
1534                 break;
1535         case 24:
1536         case 32:
1537                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1538                 break;
1539         default:
1540                 DRM_ERROR("Unknown color depth\n");
1541                 return -EINVAL;
1542         }
1543         if (INTEL_INFO(dev)->gen >= 4) {
1544                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1545                         dspcntr |= DISPPLANE_TILED;
1546                 else
1547                         dspcntr &= ~DISPPLANE_TILED;
1548         }
1549
1550         if (HAS_PCH_SPLIT(dev))
1551                 /* must disable */
1552                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1553
1554         I915_WRITE(reg, dspcntr);
1555
1556         Start = obj_priv->gtt_offset;
1557         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1558
1559         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1560                       Start, Offset, x, y, fb->pitch);
1561         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1562         if (INTEL_INFO(dev)->gen >= 4) {
1563                 I915_WRITE(DSPSURF(plane), Start);
1564                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1565                 I915_WRITE(DSPADDR(plane), Offset);
1566         } else
1567                 I915_WRITE(DSPADDR(plane), Start + Offset);
1568         POSTING_READ(reg);
1569
1570         intel_update_fbc(dev);
1571         intel_increase_pllclock(crtc);
1572
1573         return 0;
1574 }
1575
1576 static int
1577 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1578                     struct drm_framebuffer *old_fb)
1579 {
1580         struct drm_device *dev = crtc->dev;
1581         struct drm_i915_master_private *master_priv;
1582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1583         int ret;
1584
1585         /* no fb bound */
1586         if (!crtc->fb) {
1587                 DRM_DEBUG_KMS("No FB bound\n");
1588                 return 0;
1589         }
1590
1591         switch (intel_crtc->plane) {
1592         case 0:
1593         case 1:
1594                 break;
1595         default:
1596                 return -EINVAL;
1597         }
1598
1599         mutex_lock(&dev->struct_mutex);
1600         ret = intel_pin_and_fence_fb_obj(dev,
1601                                          to_intel_framebuffer(crtc->fb)->obj,
1602                                          false);
1603         if (ret != 0) {
1604                 mutex_unlock(&dev->struct_mutex);
1605                 return ret;
1606         }
1607
1608         if (old_fb) {
1609                 struct drm_i915_private *dev_priv = dev->dev_private;
1610                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1611                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1612
1613                 wait_event(dev_priv->pending_flip_queue,
1614                            atomic_read(&obj_priv->pending_flip) == 0);
1615         }
1616
1617         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 0);
1618         if (ret) {
1619                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1620                 mutex_unlock(&dev->struct_mutex);
1621                 return ret;
1622         }
1623
1624         if (old_fb)
1625                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1626
1627         mutex_unlock(&dev->struct_mutex);
1628
1629         if (!dev->primary->master)
1630                 return 0;
1631
1632         master_priv = dev->primary->master->driver_priv;
1633         if (!master_priv->sarea_priv)
1634                 return 0;
1635
1636         if (intel_crtc->pipe) {
1637                 master_priv->sarea_priv->pipeB_x = x;
1638                 master_priv->sarea_priv->pipeB_y = y;
1639         } else {
1640                 master_priv->sarea_priv->pipeA_x = x;
1641                 master_priv->sarea_priv->pipeA_y = y;
1642         }
1643
1644         return 0;
1645 }
1646
1647 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1648 {
1649         struct drm_device *dev = crtc->dev;
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         u32 dpa_ctl;
1652
1653         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1654         dpa_ctl = I915_READ(DP_A);
1655         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1656
1657         if (clock < 200000) {
1658                 u32 temp;
1659                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1660                 /* workaround for 160Mhz:
1661                    1) program 0x4600c bits 15:0 = 0x8124
1662                    2) program 0x46010 bit 0 = 1
1663                    3) program 0x46034 bit 24 = 1
1664                    4) program 0x64000 bit 14 = 1
1665                    */
1666                 temp = I915_READ(0x4600c);
1667                 temp &= 0xffff0000;
1668                 I915_WRITE(0x4600c, temp | 0x8124);
1669
1670                 temp = I915_READ(0x46010);
1671                 I915_WRITE(0x46010, temp | 1);
1672
1673                 temp = I915_READ(0x46034);
1674                 I915_WRITE(0x46034, temp | (1 << 24));
1675         } else {
1676                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1677         }
1678         I915_WRITE(DP_A, dpa_ctl);
1679
1680         POSTING_READ(DP_A);
1681         udelay(500);
1682 }
1683
1684 /* The FDI link training functions for ILK/Ibexpeak. */
1685 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1686 {
1687         struct drm_device *dev = crtc->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1690         int pipe = intel_crtc->pipe;
1691         u32 reg, temp, tries;
1692
1693         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1694            for train result */
1695         reg = FDI_RX_IMR(pipe);
1696         temp = I915_READ(reg);
1697         temp &= ~FDI_RX_SYMBOL_LOCK;
1698         temp &= ~FDI_RX_BIT_LOCK;
1699         I915_WRITE(reg, temp);
1700         I915_READ(reg);
1701         udelay(150);
1702
1703         /* enable CPU FDI TX and PCH FDI RX */
1704         reg = FDI_TX_CTL(pipe);
1705         temp = I915_READ(reg);
1706         temp &= ~(7 << 19);
1707         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1708         temp &= ~FDI_LINK_TRAIN_NONE;
1709         temp |= FDI_LINK_TRAIN_PATTERN_1;
1710         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1711
1712         reg = FDI_RX_CTL(pipe);
1713         temp = I915_READ(reg);
1714         temp &= ~FDI_LINK_TRAIN_NONE;
1715         temp |= FDI_LINK_TRAIN_PATTERN_1;
1716         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1717
1718         POSTING_READ(reg);
1719         udelay(150);
1720
1721         reg = FDI_RX_IIR(pipe);
1722         for (tries = 0; tries < 5; tries++) {
1723                 temp = I915_READ(reg);
1724                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1725
1726                 if ((temp & FDI_RX_BIT_LOCK)) {
1727                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1728                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1729                         break;
1730                 }
1731         }
1732         if (tries == 5)
1733                 DRM_ERROR("FDI train 1 fail!\n");
1734
1735         /* Train 2 */
1736         reg = FDI_TX_CTL(pipe);
1737         temp = I915_READ(reg);
1738         temp &= ~FDI_LINK_TRAIN_NONE;
1739         temp |= FDI_LINK_TRAIN_PATTERN_2;
1740         I915_WRITE(reg, temp);
1741
1742         reg = FDI_RX_CTL(pipe);
1743         temp = I915_READ(reg);
1744         temp &= ~FDI_LINK_TRAIN_NONE;
1745         temp |= FDI_LINK_TRAIN_PATTERN_2;
1746         I915_WRITE(reg, temp);
1747
1748         POSTING_READ(reg);
1749         udelay(150);
1750
1751         reg = FDI_RX_IIR(pipe);
1752         for (tries = 0; tries < 5; tries++) {
1753                 temp = I915_READ(reg);
1754                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1755
1756                 if (temp & FDI_RX_SYMBOL_LOCK) {
1757                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1758                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1759                         break;
1760                 }
1761         }
1762         if (tries == 5)
1763                 DRM_ERROR("FDI train 2 fail!\n");
1764
1765         DRM_DEBUG_KMS("FDI train done\n");
1766 }
1767
1768 static const int const snb_b_fdi_train_param [] = {
1769         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1770         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1771         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1772         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1773 };
1774
1775 /* The FDI link training functions for SNB/Cougarpoint. */
1776 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1781         int pipe = intel_crtc->pipe;
1782         u32 reg, temp, i;
1783
1784         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1785            for train result */
1786         reg = FDI_RX_IMR(pipe);
1787         temp = I915_READ(reg);
1788         temp &= ~FDI_RX_SYMBOL_LOCK;
1789         temp &= ~FDI_RX_BIT_LOCK;
1790         I915_WRITE(reg, temp);
1791
1792         POSTING_READ(reg);
1793         udelay(150);
1794
1795         /* enable CPU FDI TX and PCH FDI RX */
1796         reg = FDI_TX_CTL(pipe);
1797         temp = I915_READ(reg);
1798         temp &= ~(7 << 19);
1799         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1800         temp &= ~FDI_LINK_TRAIN_NONE;
1801         temp |= FDI_LINK_TRAIN_PATTERN_1;
1802         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1803         /* SNB-B */
1804         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1805         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1806
1807         reg = FDI_RX_CTL(pipe);
1808         temp = I915_READ(reg);
1809         if (HAS_PCH_CPT(dev)) {
1810                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1811                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1812         } else {
1813                 temp &= ~FDI_LINK_TRAIN_NONE;
1814                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1815         }
1816         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1817
1818         POSTING_READ(reg);
1819         udelay(150);
1820
1821         for (i = 0; i < 4; i++ ) {
1822                 reg = FDI_TX_CTL(pipe);
1823                 temp = I915_READ(reg);
1824                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1825                 temp |= snb_b_fdi_train_param[i];
1826                 I915_WRITE(reg, temp);
1827
1828                 POSTING_READ(reg);
1829                 udelay(500);
1830
1831                 reg = FDI_RX_IIR(pipe);
1832                 temp = I915_READ(reg);
1833                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1834
1835                 if (temp & FDI_RX_BIT_LOCK) {
1836                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1837                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1838                         break;
1839                 }
1840         }
1841         if (i == 4)
1842                 DRM_ERROR("FDI train 1 fail!\n");
1843
1844         /* Train 2 */
1845         reg = FDI_TX_CTL(pipe);
1846         temp = I915_READ(reg);
1847         temp &= ~FDI_LINK_TRAIN_NONE;
1848         temp |= FDI_LINK_TRAIN_PATTERN_2;
1849         if (IS_GEN6(dev)) {
1850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1851                 /* SNB-B */
1852                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1853         }
1854         I915_WRITE(reg, temp);
1855
1856         reg = FDI_RX_CTL(pipe);
1857         temp = I915_READ(reg);
1858         if (HAS_PCH_CPT(dev)) {
1859                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1860                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1861         } else {
1862                 temp &= ~FDI_LINK_TRAIN_NONE;
1863                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1864         }
1865         I915_WRITE(reg, temp);
1866
1867         POSTING_READ(reg);
1868         udelay(150);
1869
1870         for (i = 0; i < 4; i++ ) {
1871                 reg = FDI_TX_CTL(pipe);
1872                 temp = I915_READ(reg);
1873                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1874                 temp |= snb_b_fdi_train_param[i];
1875                 I915_WRITE(reg, temp);
1876
1877                 POSTING_READ(reg);
1878                 udelay(500);
1879
1880                 reg = FDI_RX_IIR(pipe);
1881                 temp = I915_READ(reg);
1882                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1883
1884                 if (temp & FDI_RX_SYMBOL_LOCK) {
1885                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1886                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1887                         break;
1888                 }
1889         }
1890         if (i == 4)
1891                 DRM_ERROR("FDI train 2 fail!\n");
1892
1893         DRM_DEBUG_KMS("FDI train done.\n");
1894 }
1895
1896 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1897 {
1898         struct drm_device *dev = crtc->dev;
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1901         int pipe = intel_crtc->pipe;
1902         u32 reg, temp;
1903
1904         /* Write the TU size bits so error detection works */
1905         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1906                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1907
1908         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1909         reg = FDI_RX_CTL(pipe);
1910         temp = I915_READ(reg);
1911         temp &= ~((0x7 << 19) | (0x7 << 16));
1912         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1913         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1914         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1915
1916         POSTING_READ(reg);
1917         udelay(200);
1918
1919         /* Switch from Rawclk to PCDclk */
1920         temp = I915_READ(reg);
1921         I915_WRITE(reg, temp | FDI_PCDCLK);
1922
1923         POSTING_READ(reg);
1924         udelay(200);
1925
1926         /* Enable CPU FDI TX PLL, always on for Ironlake */
1927         reg = FDI_TX_CTL(pipe);
1928         temp = I915_READ(reg);
1929         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1930                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1931
1932                 POSTING_READ(reg);
1933                 udelay(100);
1934         }
1935 }
1936
1937 static void intel_flush_display_plane(struct drm_device *dev,
1938                                       int plane)
1939 {
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         u32 reg = DSPADDR(plane);
1942         I915_WRITE(reg, I915_READ(reg));
1943 }
1944
1945 /*
1946  * When we disable a pipe, we need to clear any pending scanline wait events
1947  * to avoid hanging the ring, which we assume we are waiting on.
1948  */
1949 static void intel_clear_scanline_wait(struct drm_device *dev)
1950 {
1951         struct drm_i915_private *dev_priv = dev->dev_private;
1952         u32 tmp;
1953
1954         if (IS_GEN2(dev))
1955                 /* Can't break the hang on i8xx */
1956                 return;
1957
1958         tmp = I915_READ(PRB0_CTL);
1959         if (tmp & RING_WAIT) {
1960                 I915_WRITE(PRB0_CTL, tmp);
1961                 POSTING_READ(PRB0_CTL);
1962         }
1963 }
1964
1965 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
1966 {
1967         struct drm_i915_gem_object *obj_priv;
1968         struct drm_i915_private *dev_priv;
1969
1970         if (crtc->fb == NULL)
1971                 return;
1972
1973         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
1974         dev_priv = crtc->dev->dev_private;
1975         wait_event(dev_priv->pending_flip_queue,
1976                    atomic_read(&obj_priv->pending_flip) == 0);
1977 }
1978
1979 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1980 {
1981         struct drm_device *dev = crtc->dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984         int pipe = intel_crtc->pipe;
1985         int plane = intel_crtc->plane;
1986         u32 reg, temp;
1987
1988         if (intel_crtc->active)
1989                 return;
1990
1991         intel_crtc->active = true;
1992         intel_update_watermarks(dev);
1993
1994         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1995                 temp = I915_READ(PCH_LVDS);
1996                 if ((temp & LVDS_PORT_EN) == 0)
1997                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1998         }
1999
2000         ironlake_fdi_enable(crtc);
2001
2002         /* Enable panel fitting for LVDS */
2003         if (dev_priv->pch_pf_size &&
2004             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2005              || HAS_eDP || intel_pch_has_edp(crtc))) {
2006                 /* Force use of hard-coded filter coefficients
2007                  * as some pre-programmed values are broken,
2008                  * e.g. x201.
2009                  */
2010                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2011                            PF_ENABLE | PF_FILTER_MED_3x3);
2012                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2013                            dev_priv->pch_pf_pos);
2014                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2015                            dev_priv->pch_pf_size);
2016         }
2017
2018         /* Enable CPU pipe */
2019         reg = PIPECONF(pipe);
2020         temp = I915_READ(reg);
2021         if ((temp & PIPECONF_ENABLE) == 0) {
2022                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2023                 POSTING_READ(reg);
2024                 udelay(100);
2025         }
2026
2027         /* configure and enable CPU plane */
2028         reg = DSPCNTR(plane);
2029         temp = I915_READ(reg);
2030         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2031                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2032                 intel_flush_display_plane(dev, plane);
2033         }
2034
2035         /* For PCH output, training FDI link */
2036         if (IS_GEN6(dev))
2037                 gen6_fdi_link_train(crtc);
2038         else
2039                 ironlake_fdi_link_train(crtc);
2040
2041         /* enable PCH DPLL */
2042         reg = PCH_DPLL(pipe);
2043         temp = I915_READ(reg);
2044         if ((temp & DPLL_VCO_ENABLE) == 0) {
2045                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2046                 POSTING_READ(reg);
2047                 udelay(200);
2048         }
2049
2050         if (HAS_PCH_CPT(dev)) {
2051                 /* Be sure PCH DPLL SEL is set */
2052                 temp = I915_READ(PCH_DPLL_SEL);
2053                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2054                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2055                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2056                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2057                 I915_WRITE(PCH_DPLL_SEL, temp);
2058         }
2059
2060         /* set transcoder timing */
2061         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2062         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2063         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2064
2065         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2066         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2067         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2068
2069         /* enable normal train */
2070         reg = FDI_TX_CTL(pipe);
2071         temp = I915_READ(reg);
2072         temp &= ~FDI_LINK_TRAIN_NONE;
2073         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2074         I915_WRITE(reg, temp);
2075
2076         reg = FDI_RX_CTL(pipe);
2077         temp = I915_READ(reg);
2078         if (HAS_PCH_CPT(dev)) {
2079                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2080                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2081         } else {
2082                 temp &= ~FDI_LINK_TRAIN_NONE;
2083                 temp |= FDI_LINK_TRAIN_NONE;
2084         }
2085         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2086
2087         /* wait one idle pattern time */
2088         POSTING_READ(reg);
2089         udelay(100);
2090
2091         /* For PCH DP, enable TRANS_DP_CTL */
2092         if (HAS_PCH_CPT(dev) &&
2093             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2094                 reg = TRANS_DP_CTL(pipe);
2095                 temp = I915_READ(reg);
2096                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2097                           TRANS_DP_SYNC_MASK);
2098                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2099                          TRANS_DP_ENH_FRAMING);
2100
2101                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2102                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2103                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2104                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2105
2106                 switch (intel_trans_dp_port_sel(crtc)) {
2107                 case PCH_DP_B:
2108                         temp |= TRANS_DP_PORT_SEL_B;
2109                         break;
2110                 case PCH_DP_C:
2111                         temp |= TRANS_DP_PORT_SEL_C;
2112                         break;
2113                 case PCH_DP_D:
2114                         temp |= TRANS_DP_PORT_SEL_D;
2115                         break;
2116                 default:
2117                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2118                         temp |= TRANS_DP_PORT_SEL_B;
2119                         break;
2120                 }
2121
2122                 I915_WRITE(reg, temp);
2123         }
2124
2125         /* enable PCH transcoder */
2126         reg = TRANSCONF(pipe);
2127         temp = I915_READ(reg);
2128         /*
2129          * make the BPC in transcoder be consistent with
2130          * that in pipeconf reg.
2131          */
2132         temp &= ~PIPE_BPC_MASK;
2133         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2134         I915_WRITE(reg, temp | TRANS_ENABLE);
2135         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2136                 DRM_ERROR("failed to enable transcoder\n");
2137
2138         intel_crtc_load_lut(crtc);
2139         intel_update_fbc(dev);
2140         intel_crtc_update_cursor(crtc, true);
2141 }
2142
2143 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2144 {
2145         struct drm_device *dev = crtc->dev;
2146         struct drm_i915_private *dev_priv = dev->dev_private;
2147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2148         int pipe = intel_crtc->pipe;
2149         int plane = intel_crtc->plane;
2150         u32 reg, temp;
2151
2152         if (!intel_crtc->active)
2153                 return;
2154
2155         intel_crtc_wait_for_pending_flips(crtc);
2156         drm_vblank_off(dev, pipe);
2157         intel_crtc_update_cursor(crtc, false);
2158
2159         /* Disable display plane */
2160         reg = DSPCNTR(plane);
2161         temp = I915_READ(reg);
2162         if (temp & DISPLAY_PLANE_ENABLE) {
2163                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2164                 intel_flush_display_plane(dev, plane);
2165         }
2166
2167         if (dev_priv->cfb_plane == plane &&
2168             dev_priv->display.disable_fbc)
2169                 dev_priv->display.disable_fbc(dev);
2170
2171         /* disable cpu pipe, disable after all planes disabled */
2172         reg = PIPECONF(pipe);
2173         temp = I915_READ(reg);
2174         if (temp & PIPECONF_ENABLE) {
2175                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2176                 /* wait for cpu pipe off, pipe state */
2177                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2178                         DRM_ERROR("failed to turn off cpu pipe\n");
2179         }
2180
2181         /* Disable PF */
2182         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2183         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2184
2185         /* disable CPU FDI tx and PCH FDI rx */
2186         reg = FDI_TX_CTL(pipe);
2187         temp = I915_READ(reg);
2188         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2189         POSTING_READ(reg);
2190
2191         reg = FDI_RX_CTL(pipe);
2192         temp = I915_READ(reg);
2193         temp &= ~(0x7 << 16);
2194         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2195         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2196
2197         POSTING_READ(reg);
2198         udelay(100);
2199
2200         /* still set train pattern 1 */
2201         reg = FDI_TX_CTL(pipe);
2202         temp = I915_READ(reg);
2203         temp &= ~FDI_LINK_TRAIN_NONE;
2204         temp |= FDI_LINK_TRAIN_PATTERN_1;
2205         I915_WRITE(reg, temp);
2206
2207         reg = FDI_RX_CTL(pipe);
2208         temp = I915_READ(reg);
2209         if (HAS_PCH_CPT(dev)) {
2210                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2211                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2212         } else {
2213                 temp &= ~FDI_LINK_TRAIN_NONE;
2214                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2215         }
2216         /* BPC in FDI rx is consistent with that in PIPECONF */
2217         temp &= ~(0x07 << 16);
2218         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2219         I915_WRITE(reg, temp);
2220
2221         POSTING_READ(reg);
2222         udelay(100);
2223
2224         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2225                 temp = I915_READ(PCH_LVDS);
2226                 if (temp & LVDS_PORT_EN) {
2227                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2228                         POSTING_READ(PCH_LVDS);
2229                         udelay(100);
2230                 }
2231         }
2232
2233         /* disable PCH transcoder */
2234         reg = TRANSCONF(plane);
2235         temp = I915_READ(reg);
2236         if (temp & TRANS_ENABLE) {
2237                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2238                 /* wait for PCH transcoder off, transcoder state */
2239                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2240                         DRM_ERROR("failed to disable transcoder\n");
2241         }
2242
2243         if (HAS_PCH_CPT(dev)) {
2244                 /* disable TRANS_DP_CTL */
2245                 reg = TRANS_DP_CTL(pipe);
2246                 temp = I915_READ(reg);
2247                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2248                 I915_WRITE(reg, temp);
2249
2250                 /* disable DPLL_SEL */
2251                 temp = I915_READ(PCH_DPLL_SEL);
2252                 if (pipe == 0)
2253                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2254                 else
2255                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2256                 I915_WRITE(PCH_DPLL_SEL, temp);
2257         }
2258
2259         /* disable PCH DPLL */
2260         reg = PCH_DPLL(pipe);
2261         temp = I915_READ(reg);
2262         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2263
2264         /* Switch from PCDclk to Rawclk */
2265         reg = FDI_RX_CTL(pipe);
2266         temp = I915_READ(reg);
2267         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2268
2269         /* Disable CPU FDI TX PLL */
2270         reg = FDI_TX_CTL(pipe);
2271         temp = I915_READ(reg);
2272         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2273
2274         POSTING_READ(reg);
2275         udelay(100);
2276
2277         reg = FDI_RX_CTL(pipe);
2278         temp = I915_READ(reg);
2279         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2280
2281         /* Wait for the clocks to turn off. */
2282         POSTING_READ(reg);
2283         udelay(100);
2284
2285         intel_crtc->active = false;
2286         intel_update_watermarks(dev);
2287         intel_update_fbc(dev);
2288         intel_clear_scanline_wait(dev);
2289 }
2290
2291 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2292 {
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         int pipe = intel_crtc->pipe;
2295         int plane = intel_crtc->plane;
2296
2297         /* XXX: When our outputs are all unaware of DPMS modes other than off
2298          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2299          */
2300         switch (mode) {
2301         case DRM_MODE_DPMS_ON:
2302         case DRM_MODE_DPMS_STANDBY:
2303         case DRM_MODE_DPMS_SUSPEND:
2304                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2305                 ironlake_crtc_enable(crtc);
2306                 break;
2307
2308         case DRM_MODE_DPMS_OFF:
2309                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2310                 ironlake_crtc_disable(crtc);
2311                 break;
2312         }
2313 }
2314
2315 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2316 {
2317         if (!enable && intel_crtc->overlay) {
2318                 struct drm_device *dev = intel_crtc->base.dev;
2319
2320                 mutex_lock(&dev->struct_mutex);
2321                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2322                 mutex_unlock(&dev->struct_mutex);
2323         }
2324
2325         /* Let userspace switch the overlay on again. In most cases userspace
2326          * has to recompute where to put it anyway.
2327          */
2328 }
2329
2330 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335         int pipe = intel_crtc->pipe;
2336         int plane = intel_crtc->plane;
2337         u32 reg, temp;
2338
2339         if (intel_crtc->active)
2340                 return;
2341
2342         intel_crtc->active = true;
2343         intel_update_watermarks(dev);
2344
2345         /* Enable the DPLL */
2346         reg = DPLL(pipe);
2347         temp = I915_READ(reg);
2348         if ((temp & DPLL_VCO_ENABLE) == 0) {
2349                 I915_WRITE(reg, temp);
2350
2351                 /* Wait for the clocks to stabilize. */
2352                 POSTING_READ(reg);
2353                 udelay(150);
2354
2355                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2356
2357                 /* Wait for the clocks to stabilize. */
2358                 POSTING_READ(reg);
2359                 udelay(150);
2360
2361                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2362
2363                 /* Wait for the clocks to stabilize. */
2364                 POSTING_READ(reg);
2365                 udelay(150);
2366         }
2367
2368         /* Enable the pipe */
2369         reg = PIPECONF(pipe);
2370         temp = I915_READ(reg);
2371         if ((temp & PIPECONF_ENABLE) == 0)
2372                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2373
2374         /* Enable the plane */
2375         reg = DSPCNTR(plane);
2376         temp = I915_READ(reg);
2377         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2378                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2379                 intel_flush_display_plane(dev, plane);
2380         }
2381
2382         intel_crtc_load_lut(crtc);
2383         intel_update_fbc(dev);
2384
2385         /* Give the overlay scaler a chance to enable if it's on this pipe */
2386         intel_crtc_dpms_overlay(intel_crtc, true);
2387         intel_crtc_update_cursor(crtc, true);
2388 }
2389
2390 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2391 {
2392         struct drm_device *dev = crtc->dev;
2393         struct drm_i915_private *dev_priv = dev->dev_private;
2394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395         int pipe = intel_crtc->pipe;
2396         int plane = intel_crtc->plane;
2397         u32 reg, temp;
2398
2399         if (!intel_crtc->active)
2400                 return;
2401
2402         /* Give the overlay scaler a chance to disable if it's on this pipe */
2403         intel_crtc_wait_for_pending_flips(crtc);
2404         drm_vblank_off(dev, pipe);
2405         intel_crtc_dpms_overlay(intel_crtc, false);
2406         intel_crtc_update_cursor(crtc, false);
2407
2408         if (dev_priv->cfb_plane == plane &&
2409             dev_priv->display.disable_fbc)
2410                 dev_priv->display.disable_fbc(dev);
2411
2412         /* Disable display plane */
2413         reg = DSPCNTR(plane);
2414         temp = I915_READ(reg);
2415         if (temp & DISPLAY_PLANE_ENABLE) {
2416                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2417                 /* Flush the plane changes */
2418                 intel_flush_display_plane(dev, plane);
2419
2420                 /* Wait for vblank for the disable to take effect */
2421                 if (IS_GEN2(dev))
2422                         intel_wait_for_vblank(dev, pipe);
2423         }
2424
2425         /* Don't disable pipe A or pipe A PLLs if needed */
2426         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2427                 goto done;
2428
2429         /* Next, disable display pipes */
2430         reg = PIPECONF(pipe);
2431         temp = I915_READ(reg);
2432         if (temp & PIPECONF_ENABLE) {
2433                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2434
2435                 /* Wait for the pipe to turn off */
2436                 POSTING_READ(reg);
2437                 intel_wait_for_pipe_off(dev, pipe);
2438         }
2439
2440         reg = DPLL(pipe);
2441         temp = I915_READ(reg);
2442         if (temp & DPLL_VCO_ENABLE) {
2443                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2444
2445                 /* Wait for the clocks to turn off. */
2446                 POSTING_READ(reg);
2447                 udelay(150);
2448         }
2449
2450 done:
2451         intel_crtc->active = false;
2452         intel_update_fbc(dev);
2453         intel_update_watermarks(dev);
2454         intel_clear_scanline_wait(dev);
2455 }
2456
2457 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2458 {
2459         /* XXX: When our outputs are all unaware of DPMS modes other than off
2460          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2461          */
2462         switch (mode) {
2463         case DRM_MODE_DPMS_ON:
2464         case DRM_MODE_DPMS_STANDBY:
2465         case DRM_MODE_DPMS_SUSPEND:
2466                 i9xx_crtc_enable(crtc);
2467                 break;
2468         case DRM_MODE_DPMS_OFF:
2469                 i9xx_crtc_disable(crtc);
2470                 break;
2471         }
2472 }
2473
2474 /**
2475  * Sets the power management mode of the pipe and plane.
2476  */
2477 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2478 {
2479         struct drm_device *dev = crtc->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct drm_i915_master_private *master_priv;
2482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2483         int pipe = intel_crtc->pipe;
2484         bool enabled;
2485
2486         if (intel_crtc->dpms_mode == mode)
2487                 return;
2488
2489         intel_crtc->dpms_mode = mode;
2490
2491         dev_priv->display.dpms(crtc, mode);
2492
2493         if (!dev->primary->master)
2494                 return;
2495
2496         master_priv = dev->primary->master->driver_priv;
2497         if (!master_priv->sarea_priv)
2498                 return;
2499
2500         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2501
2502         switch (pipe) {
2503         case 0:
2504                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2505                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2506                 break;
2507         case 1:
2508                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2509                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2510                 break;
2511         default:
2512                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2513                 break;
2514         }
2515 }
2516
2517 static void intel_crtc_disable(struct drm_crtc *crtc)
2518 {
2519         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2520         struct drm_device *dev = crtc->dev;
2521
2522         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2523
2524         if (crtc->fb) {
2525                 mutex_lock(&dev->struct_mutex);
2526                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2527                 mutex_unlock(&dev->struct_mutex);
2528         }
2529 }
2530
2531 /* Prepare for a mode set.
2532  *
2533  * Note we could be a lot smarter here.  We need to figure out which outputs
2534  * will be enabled, which disabled (in short, how the config will changes)
2535  * and perform the minimum necessary steps to accomplish that, e.g. updating
2536  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2537  * panel fitting is in the proper state, etc.
2538  */
2539 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2540 {
2541         i9xx_crtc_disable(crtc);
2542 }
2543
2544 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2545 {
2546         i9xx_crtc_enable(crtc);
2547 }
2548
2549 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2550 {
2551         ironlake_crtc_disable(crtc);
2552 }
2553
2554 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2555 {
2556         ironlake_crtc_enable(crtc);
2557 }
2558
2559 void intel_encoder_prepare (struct drm_encoder *encoder)
2560 {
2561         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2562         /* lvds has its own version of prepare see intel_lvds_prepare */
2563         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2564 }
2565
2566 void intel_encoder_commit (struct drm_encoder *encoder)
2567 {
2568         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2569         /* lvds has its own version of commit see intel_lvds_commit */
2570         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2571 }
2572
2573 void intel_encoder_destroy(struct drm_encoder *encoder)
2574 {
2575         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2576
2577         drm_encoder_cleanup(encoder);
2578         kfree(intel_encoder);
2579 }
2580
2581 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2582                                   struct drm_display_mode *mode,
2583                                   struct drm_display_mode *adjusted_mode)
2584 {
2585         struct drm_device *dev = crtc->dev;
2586
2587         if (HAS_PCH_SPLIT(dev)) {
2588                 /* FDI link clock is fixed at 2.7G */
2589                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2590                         return false;
2591         }
2592
2593         /* XXX some encoders set the crtcinfo, others don't.
2594          * Obviously we need some form of conflict resolution here...
2595          */
2596         if (adjusted_mode->crtc_htotal == 0)
2597                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2598
2599         return true;
2600 }
2601
2602 static int i945_get_display_clock_speed(struct drm_device *dev)
2603 {
2604         return 400000;
2605 }
2606
2607 static int i915_get_display_clock_speed(struct drm_device *dev)
2608 {
2609         return 333000;
2610 }
2611
2612 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2613 {
2614         return 200000;
2615 }
2616
2617 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2618 {
2619         u16 gcfgc = 0;
2620
2621         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2622
2623         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2624                 return 133000;
2625         else {
2626                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2627                 case GC_DISPLAY_CLOCK_333_MHZ:
2628                         return 333000;
2629                 default:
2630                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2631                         return 190000;
2632                 }
2633         }
2634 }
2635
2636 static int i865_get_display_clock_speed(struct drm_device *dev)
2637 {
2638         return 266000;
2639 }
2640
2641 static int i855_get_display_clock_speed(struct drm_device *dev)
2642 {
2643         u16 hpllcc = 0;
2644         /* Assume that the hardware is in the high speed state.  This
2645          * should be the default.
2646          */
2647         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2648         case GC_CLOCK_133_200:
2649         case GC_CLOCK_100_200:
2650                 return 200000;
2651         case GC_CLOCK_166_250:
2652                 return 250000;
2653         case GC_CLOCK_100_133:
2654                 return 133000;
2655         }
2656
2657         /* Shouldn't happen */
2658         return 0;
2659 }
2660
2661 static int i830_get_display_clock_speed(struct drm_device *dev)
2662 {
2663         return 133000;
2664 }
2665
2666 struct fdi_m_n {
2667         u32        tu;
2668         u32        gmch_m;
2669         u32        gmch_n;
2670         u32        link_m;
2671         u32        link_n;
2672 };
2673
2674 static void
2675 fdi_reduce_ratio(u32 *num, u32 *den)
2676 {
2677         while (*num > 0xffffff || *den > 0xffffff) {
2678                 *num >>= 1;
2679                 *den >>= 1;
2680         }
2681 }
2682
2683 #define DATA_N 0x800000
2684 #define LINK_N 0x80000
2685
2686 static void
2687 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2688                      int link_clock, struct fdi_m_n *m_n)
2689 {
2690         u64 temp;
2691
2692         m_n->tu = 64; /* default size */
2693
2694         temp = (u64) DATA_N * pixel_clock;
2695         temp = div_u64(temp, link_clock);
2696         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2697         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2698         m_n->gmch_n = DATA_N;
2699         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2700
2701         temp = (u64) LINK_N * pixel_clock;
2702         m_n->link_m = div_u64(temp, link_clock);
2703         m_n->link_n = LINK_N;
2704         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2705 }
2706
2707
2708 struct intel_watermark_params {
2709         unsigned long fifo_size;
2710         unsigned long max_wm;
2711         unsigned long default_wm;
2712         unsigned long guard_size;
2713         unsigned long cacheline_size;
2714 };
2715
2716 /* Pineview has different values for various configs */
2717 static struct intel_watermark_params pineview_display_wm = {
2718         PINEVIEW_DISPLAY_FIFO,
2719         PINEVIEW_MAX_WM,
2720         PINEVIEW_DFT_WM,
2721         PINEVIEW_GUARD_WM,
2722         PINEVIEW_FIFO_LINE_SIZE
2723 };
2724 static struct intel_watermark_params pineview_display_hplloff_wm = {
2725         PINEVIEW_DISPLAY_FIFO,
2726         PINEVIEW_MAX_WM,
2727         PINEVIEW_DFT_HPLLOFF_WM,
2728         PINEVIEW_GUARD_WM,
2729         PINEVIEW_FIFO_LINE_SIZE
2730 };
2731 static struct intel_watermark_params pineview_cursor_wm = {
2732         PINEVIEW_CURSOR_FIFO,
2733         PINEVIEW_CURSOR_MAX_WM,
2734         PINEVIEW_CURSOR_DFT_WM,
2735         PINEVIEW_CURSOR_GUARD_WM,
2736         PINEVIEW_FIFO_LINE_SIZE,
2737 };
2738 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2739         PINEVIEW_CURSOR_FIFO,
2740         PINEVIEW_CURSOR_MAX_WM,
2741         PINEVIEW_CURSOR_DFT_WM,
2742         PINEVIEW_CURSOR_GUARD_WM,
2743         PINEVIEW_FIFO_LINE_SIZE
2744 };
2745 static struct intel_watermark_params g4x_wm_info = {
2746         G4X_FIFO_SIZE,
2747         G4X_MAX_WM,
2748         G4X_MAX_WM,
2749         2,
2750         G4X_FIFO_LINE_SIZE,
2751 };
2752 static struct intel_watermark_params g4x_cursor_wm_info = {
2753         I965_CURSOR_FIFO,
2754         I965_CURSOR_MAX_WM,
2755         I965_CURSOR_DFT_WM,
2756         2,
2757         G4X_FIFO_LINE_SIZE,
2758 };
2759 static struct intel_watermark_params i965_cursor_wm_info = {
2760         I965_CURSOR_FIFO,
2761         I965_CURSOR_MAX_WM,
2762         I965_CURSOR_DFT_WM,
2763         2,
2764         I915_FIFO_LINE_SIZE,
2765 };
2766 static struct intel_watermark_params i945_wm_info = {
2767         I945_FIFO_SIZE,
2768         I915_MAX_WM,
2769         1,
2770         2,
2771         I915_FIFO_LINE_SIZE
2772 };
2773 static struct intel_watermark_params i915_wm_info = {
2774         I915_FIFO_SIZE,
2775         I915_MAX_WM,
2776         1,
2777         2,
2778         I915_FIFO_LINE_SIZE
2779 };
2780 static struct intel_watermark_params i855_wm_info = {
2781         I855GM_FIFO_SIZE,
2782         I915_MAX_WM,
2783         1,
2784         2,
2785         I830_FIFO_LINE_SIZE
2786 };
2787 static struct intel_watermark_params i830_wm_info = {
2788         I830_FIFO_SIZE,
2789         I915_MAX_WM,
2790         1,
2791         2,
2792         I830_FIFO_LINE_SIZE
2793 };
2794
2795 static struct intel_watermark_params ironlake_display_wm_info = {
2796         ILK_DISPLAY_FIFO,
2797         ILK_DISPLAY_MAXWM,
2798         ILK_DISPLAY_DFTWM,
2799         2,
2800         ILK_FIFO_LINE_SIZE
2801 };
2802
2803 static struct intel_watermark_params ironlake_cursor_wm_info = {
2804         ILK_CURSOR_FIFO,
2805         ILK_CURSOR_MAXWM,
2806         ILK_CURSOR_DFTWM,
2807         2,
2808         ILK_FIFO_LINE_SIZE
2809 };
2810
2811 static struct intel_watermark_params ironlake_display_srwm_info = {
2812         ILK_DISPLAY_SR_FIFO,
2813         ILK_DISPLAY_MAX_SRWM,
2814         ILK_DISPLAY_DFT_SRWM,
2815         2,
2816         ILK_FIFO_LINE_SIZE
2817 };
2818
2819 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2820         ILK_CURSOR_SR_FIFO,
2821         ILK_CURSOR_MAX_SRWM,
2822         ILK_CURSOR_DFT_SRWM,
2823         2,
2824         ILK_FIFO_LINE_SIZE
2825 };
2826
2827 /**
2828  * intel_calculate_wm - calculate watermark level
2829  * @clock_in_khz: pixel clock
2830  * @wm: chip FIFO params
2831  * @pixel_size: display pixel size
2832  * @latency_ns: memory latency for the platform
2833  *
2834  * Calculate the watermark level (the level at which the display plane will
2835  * start fetching from memory again).  Each chip has a different display
2836  * FIFO size and allocation, so the caller needs to figure that out and pass
2837  * in the correct intel_watermark_params structure.
2838  *
2839  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2840  * on the pixel size.  When it reaches the watermark level, it'll start
2841  * fetching FIFO line sized based chunks from memory until the FIFO fills
2842  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2843  * will occur, and a display engine hang could result.
2844  */
2845 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2846                                         struct intel_watermark_params *wm,
2847                                         int pixel_size,
2848                                         unsigned long latency_ns)
2849 {
2850         long entries_required, wm_size;
2851
2852         /*
2853          * Note: we need to make sure we don't overflow for various clock &
2854          * latency values.
2855          * clocks go from a few thousand to several hundred thousand.
2856          * latency is usually a few thousand
2857          */
2858         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2859                 1000;
2860         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2861
2862         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2863
2864         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2865
2866         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2867
2868         /* Don't promote wm_size to unsigned... */
2869         if (wm_size > (long)wm->max_wm)
2870                 wm_size = wm->max_wm;
2871         if (wm_size <= 0)
2872                 wm_size = wm->default_wm;
2873         return wm_size;
2874 }
2875
2876 struct cxsr_latency {
2877         int is_desktop;
2878         int is_ddr3;
2879         unsigned long fsb_freq;
2880         unsigned long mem_freq;
2881         unsigned long display_sr;
2882         unsigned long display_hpll_disable;
2883         unsigned long cursor_sr;
2884         unsigned long cursor_hpll_disable;
2885 };
2886
2887 static const struct cxsr_latency cxsr_latency_table[] = {
2888         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2889         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2890         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2891         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2892         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2893
2894         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2895         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2896         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2897         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2898         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2899
2900         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2901         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2902         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2903         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2904         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2905
2906         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2907         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2908         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2909         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2910         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2911
2912         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2913         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2914         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2915         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2916         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2917
2918         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2919         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2920         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2921         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2922         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2923 };
2924
2925 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2926                                                          int is_ddr3,
2927                                                          int fsb,
2928                                                          int mem)
2929 {
2930         const struct cxsr_latency *latency;
2931         int i;
2932
2933         if (fsb == 0 || mem == 0)
2934                 return NULL;
2935
2936         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2937                 latency = &cxsr_latency_table[i];
2938                 if (is_desktop == latency->is_desktop &&
2939                     is_ddr3 == latency->is_ddr3 &&
2940                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2941                         return latency;
2942         }
2943
2944         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2945
2946         return NULL;
2947 }
2948
2949 static void pineview_disable_cxsr(struct drm_device *dev)
2950 {
2951         struct drm_i915_private *dev_priv = dev->dev_private;
2952
2953         /* deactivate cxsr */
2954         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2955 }
2956
2957 /*
2958  * Latency for FIFO fetches is dependent on several factors:
2959  *   - memory configuration (speed, channels)
2960  *   - chipset
2961  *   - current MCH state
2962  * It can be fairly high in some situations, so here we assume a fairly
2963  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2964  * set this value too high, the FIFO will fetch frequently to stay full)
2965  * and power consumption (set it too low to save power and we might see
2966  * FIFO underruns and display "flicker").
2967  *
2968  * A value of 5us seems to be a good balance; safe for very low end
2969  * platforms but not overly aggressive on lower latency configs.
2970  */
2971 static const int latency_ns = 5000;
2972
2973 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2974 {
2975         struct drm_i915_private *dev_priv = dev->dev_private;
2976         uint32_t dsparb = I915_READ(DSPARB);
2977         int size;
2978
2979         size = dsparb & 0x7f;
2980         if (plane)
2981                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2982
2983         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2984                       plane ? "B" : "A", size);
2985
2986         return size;
2987 }
2988
2989 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2990 {
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         uint32_t dsparb = I915_READ(DSPARB);
2993         int size;
2994
2995         size = dsparb & 0x1ff;
2996         if (plane)
2997                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2998         size >>= 1; /* Convert to cachelines */
2999
3000         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3001                       plane ? "B" : "A", size);
3002
3003         return size;
3004 }
3005
3006 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         uint32_t dsparb = I915_READ(DSPARB);
3010         int size;
3011
3012         size = dsparb & 0x7f;
3013         size >>= 2; /* Convert to cachelines */
3014
3015         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3016                       plane ? "B" : "A",
3017                       size);
3018
3019         return size;
3020 }
3021
3022 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3023 {
3024         struct drm_i915_private *dev_priv = dev->dev_private;
3025         uint32_t dsparb = I915_READ(DSPARB);
3026         int size;
3027
3028         size = dsparb & 0x7f;
3029         size >>= 1; /* Convert to cachelines */
3030
3031         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3032                       plane ? "B" : "A", size);
3033
3034         return size;
3035 }
3036
3037 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3038                                int planeb_clock, int sr_hdisplay, int unused,
3039                                int pixel_size)
3040 {
3041         struct drm_i915_private *dev_priv = dev->dev_private;
3042         const struct cxsr_latency *latency;
3043         u32 reg;
3044         unsigned long wm;
3045         int sr_clock;
3046
3047         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3048                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3049         if (!latency) {
3050                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3051                 pineview_disable_cxsr(dev);
3052                 return;
3053         }
3054
3055         if (!planea_clock || !planeb_clock) {
3056                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3057
3058                 /* Display SR */
3059                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3060                                         pixel_size, latency->display_sr);
3061                 reg = I915_READ(DSPFW1);
3062                 reg &= ~DSPFW_SR_MASK;
3063                 reg |= wm << DSPFW_SR_SHIFT;
3064                 I915_WRITE(DSPFW1, reg);
3065                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3066
3067                 /* cursor SR */
3068                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3069                                         pixel_size, latency->cursor_sr);
3070                 reg = I915_READ(DSPFW3);
3071                 reg &= ~DSPFW_CURSOR_SR_MASK;
3072                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3073                 I915_WRITE(DSPFW3, reg);
3074
3075                 /* Display HPLL off SR */
3076                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3077                                         pixel_size, latency->display_hpll_disable);
3078                 reg = I915_READ(DSPFW3);
3079                 reg &= ~DSPFW_HPLL_SR_MASK;
3080                 reg |= wm & DSPFW_HPLL_SR_MASK;
3081                 I915_WRITE(DSPFW3, reg);
3082
3083                 /* cursor HPLL off SR */
3084                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3085                                         pixel_size, latency->cursor_hpll_disable);
3086                 reg = I915_READ(DSPFW3);
3087                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3088                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3089                 I915_WRITE(DSPFW3, reg);
3090                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3091
3092                 /* activate cxsr */
3093                 I915_WRITE(DSPFW3,
3094                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3095                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3096         } else {
3097                 pineview_disable_cxsr(dev);
3098                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3099         }
3100 }
3101
3102 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3103                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3104                           int pixel_size)
3105 {
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         int total_size, cacheline_size;
3108         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3109         struct intel_watermark_params planea_params, planeb_params;
3110         unsigned long line_time_us;
3111         int sr_clock, sr_entries = 0, entries_required;
3112
3113         /* Create copies of the base settings for each pipe */
3114         planea_params = planeb_params = g4x_wm_info;
3115
3116         /* Grab a couple of global values before we overwrite them */
3117         total_size = planea_params.fifo_size;
3118         cacheline_size = planea_params.cacheline_size;
3119
3120         /*
3121          * Note: we need to make sure we don't overflow for various clock &
3122          * latency values.
3123          * clocks go from a few thousand to several hundred thousand.
3124          * latency is usually a few thousand
3125          */
3126         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3127                 1000;
3128         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3129         planea_wm = entries_required + planea_params.guard_size;
3130
3131         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3132                 1000;
3133         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3134         planeb_wm = entries_required + planeb_params.guard_size;
3135
3136         cursora_wm = cursorb_wm = 16;
3137         cursor_sr = 32;
3138
3139         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3140
3141         /* Calc sr entries for one plane configs */
3142         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3143                 /* self-refresh has much higher latency */
3144                 static const int sr_latency_ns = 12000;
3145
3146                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3147                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3148
3149                 /* Use ns/us then divide to preserve precision */
3150                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3151                         pixel_size * sr_hdisplay;
3152                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3153
3154                 entries_required = (((sr_latency_ns / line_time_us) +
3155                                      1000) / 1000) * pixel_size * 64;
3156                 entries_required = DIV_ROUND_UP(entries_required,
3157                                                 g4x_cursor_wm_info.cacheline_size);
3158                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3159
3160                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3161                         cursor_sr = g4x_cursor_wm_info.max_wm;
3162                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3163                               "cursor %d\n", sr_entries, cursor_sr);
3164
3165                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3166         } else {
3167                 /* Turn off self refresh if both pipes are enabled */
3168                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3169                            & ~FW_BLC_SELF_EN);
3170         }
3171
3172         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3173                   planea_wm, planeb_wm, sr_entries);
3174
3175         planea_wm &= 0x3f;
3176         planeb_wm &= 0x3f;
3177
3178         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3179                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3180                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3181         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3182                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3183         /* HPLL off in SR has some issues on G4x... disable it */
3184         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3185                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3186 }
3187
3188 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3189                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3190                            int pixel_size)
3191 {
3192         struct drm_i915_private *dev_priv = dev->dev_private;
3193         unsigned long line_time_us;
3194         int sr_clock, sr_entries, srwm = 1;
3195         int cursor_sr = 16;
3196
3197         /* Calc sr entries for one plane configs */
3198         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3199                 /* self-refresh has much higher latency */
3200                 static const int sr_latency_ns = 12000;
3201
3202                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3203                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3204
3205                 /* Use ns/us then divide to preserve precision */
3206                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3207                         pixel_size * sr_hdisplay;
3208                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3209                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3210                 srwm = I965_FIFO_SIZE - sr_entries;
3211                 if (srwm < 0)
3212                         srwm = 1;
3213                 srwm &= 0x1ff;
3214
3215                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3216                         pixel_size * 64;
3217                 sr_entries = DIV_ROUND_UP(sr_entries,
3218                                           i965_cursor_wm_info.cacheline_size);
3219                 cursor_sr = i965_cursor_wm_info.fifo_size -
3220                         (sr_entries + i965_cursor_wm_info.guard_size);
3221
3222                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3223                         cursor_sr = i965_cursor_wm_info.max_wm;
3224
3225                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3226                               "cursor %d\n", srwm, cursor_sr);
3227
3228                 if (IS_CRESTLINE(dev))
3229                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3230         } else {
3231                 /* Turn off self refresh if both pipes are enabled */
3232                 if (IS_CRESTLINE(dev))
3233                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3234                                    & ~FW_BLC_SELF_EN);
3235         }
3236
3237         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3238                       srwm);
3239
3240         /* 965 has limitations... */
3241         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3242                    (8 << 0));
3243         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3244         /* update cursor SR watermark */
3245         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3246 }
3247
3248 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3249                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3250                            int pixel_size)
3251 {
3252         struct drm_i915_private *dev_priv = dev->dev_private;
3253         uint32_t fwater_lo;
3254         uint32_t fwater_hi;
3255         int total_size, cacheline_size, cwm, srwm = 1;
3256         int planea_wm, planeb_wm;
3257         struct intel_watermark_params planea_params, planeb_params;
3258         unsigned long line_time_us;
3259         int sr_clock, sr_entries = 0;
3260
3261         /* Create copies of the base settings for each pipe */
3262         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3263                 planea_params = planeb_params = i945_wm_info;
3264         else if (!IS_GEN2(dev))
3265                 planea_params = planeb_params = i915_wm_info;
3266         else
3267                 planea_params = planeb_params = i855_wm_info;
3268
3269         /* Grab a couple of global values before we overwrite them */
3270         total_size = planea_params.fifo_size;
3271         cacheline_size = planea_params.cacheline_size;
3272
3273         /* Update per-plane FIFO sizes */
3274         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3275         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3276
3277         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3278                                        pixel_size, latency_ns);
3279         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3280                                        pixel_size, latency_ns);
3281         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3282
3283         /*
3284          * Overlay gets an aggressive default since video jitter is bad.
3285          */
3286         cwm = 2;
3287
3288         /* Calc sr entries for one plane configs */
3289         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3290             (!planea_clock || !planeb_clock)) {
3291                 /* self-refresh has much higher latency */
3292                 static const int sr_latency_ns = 6000;
3293
3294                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3295                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3296
3297                 /* Use ns/us then divide to preserve precision */
3298                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3299                         pixel_size * sr_hdisplay;
3300                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3301                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3302                 srwm = total_size - sr_entries;
3303                 if (srwm < 0)
3304                         srwm = 1;
3305
3306                 if (IS_I945G(dev) || IS_I945GM(dev))
3307                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3308                 else if (IS_I915GM(dev)) {
3309                         /* 915M has a smaller SRWM field */
3310                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3311                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3312                 }
3313         } else {
3314                 /* Turn off self refresh if both pipes are enabled */
3315                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3316                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3317                                    & ~FW_BLC_SELF_EN);
3318                 } else if (IS_I915GM(dev)) {
3319                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3320                 }
3321         }
3322
3323         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3324                       planea_wm, planeb_wm, cwm, srwm);
3325
3326         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3327         fwater_hi = (cwm & 0x1f);
3328
3329         /* Set request length to 8 cachelines per fetch */
3330         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3331         fwater_hi = fwater_hi | (1 << 8);
3332
3333         I915_WRITE(FW_BLC, fwater_lo);
3334         I915_WRITE(FW_BLC2, fwater_hi);
3335 }
3336
3337 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3338                            int unused2, int unused3, int pixel_size)
3339 {
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3342         int planea_wm;
3343
3344         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3345
3346         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3347                                        pixel_size, latency_ns);
3348         fwater_lo |= (3<<8) | planea_wm;
3349
3350         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3351
3352         I915_WRITE(FW_BLC, fwater_lo);
3353 }
3354
3355 #define ILK_LP0_PLANE_LATENCY           700
3356 #define ILK_LP0_CURSOR_LATENCY          1300
3357
3358 static bool ironlake_compute_wm0(struct drm_device *dev,
3359                                  int pipe,
3360                                  int *plane_wm,
3361                                  int *cursor_wm)
3362 {
3363         struct drm_crtc *crtc;
3364         int htotal, hdisplay, clock, pixel_size = 0;
3365         int line_time_us, line_count, entries;
3366
3367         crtc = intel_get_crtc_for_pipe(dev, pipe);
3368         if (crtc->fb == NULL || !crtc->enabled)
3369                 return false;
3370
3371         htotal = crtc->mode.htotal;
3372         hdisplay = crtc->mode.hdisplay;
3373         clock = crtc->mode.clock;
3374         pixel_size = crtc->fb->bits_per_pixel / 8;
3375
3376         /* Use the small buffer method to calculate plane watermark */
3377         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3378         entries = DIV_ROUND_UP(entries,
3379                                ironlake_display_wm_info.cacheline_size);
3380         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3381         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3382                 *plane_wm = ironlake_display_wm_info.max_wm;
3383
3384         /* Use the large buffer method to calculate cursor watermark */
3385         line_time_us = ((htotal * 1000) / clock);
3386         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3387         entries = line_count * 64 * pixel_size;
3388         entries = DIV_ROUND_UP(entries,
3389                                ironlake_cursor_wm_info.cacheline_size);
3390         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3391         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3392                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3393
3394         return true;
3395 }
3396
3397 static void ironlake_update_wm(struct drm_device *dev,
3398                                int planea_clock, int planeb_clock,
3399                                int sr_hdisplay, int sr_htotal,
3400                                int pixel_size)
3401 {
3402         struct drm_i915_private *dev_priv = dev->dev_private;
3403         int plane_wm, cursor_wm, enabled;
3404         int tmp;
3405
3406         enabled = 0;
3407         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3408                 I915_WRITE(WM0_PIPEA_ILK,
3409                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3410                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3411                               " plane %d, " "cursor: %d\n",
3412                               plane_wm, cursor_wm);
3413                 enabled++;
3414         }
3415
3416         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3417                 I915_WRITE(WM0_PIPEB_ILK,
3418                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3419                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3420                               " plane %d, cursor: %d\n",
3421                               plane_wm, cursor_wm);
3422                 enabled++;
3423         }
3424
3425         /*
3426          * Calculate and update the self-refresh watermark only when one
3427          * display plane is used.
3428          */
3429         tmp = 0;
3430         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3431                 unsigned long line_time_us;
3432                 int small, large, plane_fbc;
3433                 int sr_clock, entries;
3434                 int line_count, line_size;
3435                 /* Read the self-refresh latency. The unit is 0.5us */
3436                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3437
3438                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3439                 line_time_us = (sr_htotal * 1000) / sr_clock;
3440
3441                 /* Use ns/us then divide to preserve precision */
3442                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3443                         / 1000;
3444                 line_size = sr_hdisplay * pixel_size;
3445
3446                 /* Use the minimum of the small and large buffer method for primary */
3447                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3448                 large = line_count * line_size;
3449
3450                 entries = DIV_ROUND_UP(min(small, large),
3451                                        ironlake_display_srwm_info.cacheline_size);
3452
3453                 plane_fbc = entries * 64;
3454                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3455
3456                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3457                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3458                         plane_wm = ironlake_display_srwm_info.max_wm;
3459
3460                 /* calculate the self-refresh watermark for display cursor */
3461                 entries = line_count * pixel_size * 64;
3462                 entries = DIV_ROUND_UP(entries,
3463                                        ironlake_cursor_srwm_info.cacheline_size);
3464
3465                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3466                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3467                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3468
3469                 /* configure watermark and enable self-refresh */
3470                 tmp = (WM1_LP_SR_EN |
3471                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3472                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3473                        (plane_wm << WM1_LP_SR_SHIFT) |
3474                        cursor_wm);
3475                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3476                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3477         }
3478         I915_WRITE(WM1_LP_ILK, tmp);
3479         /* XXX setup WM2 and WM3 */
3480 }
3481
3482 /**
3483  * intel_update_watermarks - update FIFO watermark values based on current modes
3484  *
3485  * Calculate watermark values for the various WM regs based on current mode
3486  * and plane configuration.
3487  *
3488  * There are several cases to deal with here:
3489  *   - normal (i.e. non-self-refresh)
3490  *   - self-refresh (SR) mode
3491  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3492  *   - lines are small relative to FIFO size (buffer can hold more than 2
3493  *     lines), so need to account for TLB latency
3494  *
3495  *   The normal calculation is:
3496  *     watermark = dotclock * bytes per pixel * latency
3497  *   where latency is platform & configuration dependent (we assume pessimal
3498  *   values here).
3499  *
3500  *   The SR calculation is:
3501  *     watermark = (trunc(latency/line time)+1) * surface width *
3502  *       bytes per pixel
3503  *   where
3504  *     line time = htotal / dotclock
3505  *     surface width = hdisplay for normal plane and 64 for cursor
3506  *   and latency is assumed to be high, as above.
3507  *
3508  * The final value programmed to the register should always be rounded up,
3509  * and include an extra 2 entries to account for clock crossings.
3510  *
3511  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3512  * to set the non-SR watermarks to 8.
3513  */
3514 static void intel_update_watermarks(struct drm_device *dev)
3515 {
3516         struct drm_i915_private *dev_priv = dev->dev_private;
3517         struct drm_crtc *crtc;
3518         int sr_hdisplay = 0;
3519         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3520         int enabled = 0, pixel_size = 0;
3521         int sr_htotal = 0;
3522
3523         if (!dev_priv->display.update_wm)
3524                 return;
3525
3526         /* Get the clock config from both planes */
3527         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3528                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3529                 if (intel_crtc->active) {
3530                         enabled++;
3531                         if (intel_crtc->plane == 0) {
3532                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3533                                               intel_crtc->pipe, crtc->mode.clock);
3534                                 planea_clock = crtc->mode.clock;
3535                         } else {
3536                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3537                                               intel_crtc->pipe, crtc->mode.clock);
3538                                 planeb_clock = crtc->mode.clock;
3539                         }
3540                         sr_hdisplay = crtc->mode.hdisplay;
3541                         sr_clock = crtc->mode.clock;
3542                         sr_htotal = crtc->mode.htotal;
3543                         if (crtc->fb)
3544                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3545                         else
3546                                 pixel_size = 4; /* by default */
3547                 }
3548         }
3549
3550         if (enabled <= 0)
3551                 return;
3552
3553         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3554                                     sr_hdisplay, sr_htotal, pixel_size);
3555 }
3556
3557 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3558                                struct drm_display_mode *mode,
3559                                struct drm_display_mode *adjusted_mode,
3560                                int x, int y,
3561                                struct drm_framebuffer *old_fb)
3562 {
3563         struct drm_device *dev = crtc->dev;
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566         int pipe = intel_crtc->pipe;
3567         int plane = intel_crtc->plane;
3568         u32 fp_reg, dpll_reg;
3569         int refclk, num_connectors = 0;
3570         intel_clock_t clock, reduced_clock;
3571         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3572         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3573         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3574         struct intel_encoder *has_edp_encoder = NULL;
3575         struct drm_mode_config *mode_config = &dev->mode_config;
3576         struct intel_encoder *encoder;
3577         const intel_limit_t *limit;
3578         int ret;
3579         struct fdi_m_n m_n = {0};
3580         u32 reg, temp;
3581         int target_clock;
3582
3583         drm_vblank_pre_modeset(dev, pipe);
3584
3585         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3586                 if (encoder->base.crtc != crtc)
3587                         continue;
3588
3589                 switch (encoder->type) {
3590                 case INTEL_OUTPUT_LVDS:
3591                         is_lvds = true;
3592                         break;
3593                 case INTEL_OUTPUT_SDVO:
3594                 case INTEL_OUTPUT_HDMI:
3595                         is_sdvo = true;
3596                         if (encoder->needs_tv_clock)
3597                                 is_tv = true;
3598                         break;
3599                 case INTEL_OUTPUT_DVO:
3600                         is_dvo = true;
3601                         break;
3602                 case INTEL_OUTPUT_TVOUT:
3603                         is_tv = true;
3604                         break;
3605                 case INTEL_OUTPUT_ANALOG:
3606                         is_crt = true;
3607                         break;
3608                 case INTEL_OUTPUT_DISPLAYPORT:
3609                         is_dp = true;
3610                         break;
3611                 case INTEL_OUTPUT_EDP:
3612                         has_edp_encoder = encoder;
3613                         break;
3614                 }
3615
3616                 num_connectors++;
3617         }
3618
3619         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3620                 refclk = dev_priv->lvds_ssc_freq * 1000;
3621                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3622                               refclk / 1000);
3623         } else if (!IS_GEN2(dev)) {
3624                 refclk = 96000;
3625                 if (HAS_PCH_SPLIT(dev))
3626                         refclk = 120000; /* 120Mhz refclk */
3627         } else {
3628                 refclk = 48000;
3629         }
3630
3631         /*
3632          * Returns a set of divisors for the desired target clock with the given
3633          * refclk, or FALSE.  The returned values represent the clock equation:
3634          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3635          */
3636         limit = intel_limit(crtc);
3637         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3638         if (!ok) {
3639                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3640                 drm_vblank_post_modeset(dev, pipe);
3641                 return -EINVAL;
3642         }
3643
3644         /* Ensure that the cursor is valid for the new mode before changing... */
3645         intel_crtc_update_cursor(crtc, true);
3646
3647         if (is_lvds && dev_priv->lvds_downclock_avail) {
3648                 has_reduced_clock = limit->find_pll(limit, crtc,
3649                                                     dev_priv->lvds_downclock,
3650                                                     refclk,
3651                                                     &reduced_clock);
3652                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3653                         /*
3654                          * If the different P is found, it means that we can't
3655                          * switch the display clock by using the FP0/FP1.
3656                          * In such case we will disable the LVDS downclock
3657                          * feature.
3658                          */
3659                         DRM_DEBUG_KMS("Different P is found for "
3660                                       "LVDS clock/downclock\n");
3661                         has_reduced_clock = 0;
3662                 }
3663         }
3664         /* SDVO TV has fixed PLL values depend on its clock range,
3665            this mirrors vbios setting. */
3666         if (is_sdvo && is_tv) {
3667                 if (adjusted_mode->clock >= 100000
3668                     && adjusted_mode->clock < 140500) {
3669                         clock.p1 = 2;
3670                         clock.p2 = 10;
3671                         clock.n = 3;
3672                         clock.m1 = 16;
3673                         clock.m2 = 8;
3674                 } else if (adjusted_mode->clock >= 140500
3675                            && adjusted_mode->clock <= 200000) {
3676                         clock.p1 = 1;
3677                         clock.p2 = 10;
3678                         clock.n = 6;
3679                         clock.m1 = 12;
3680                         clock.m2 = 8;
3681                 }
3682         }
3683
3684         /* FDI link */
3685         if (HAS_PCH_SPLIT(dev)) {
3686                 int lane = 0, link_bw, bpp;
3687                 /* eDP doesn't require FDI link, so just set DP M/N
3688                    according to current link config */
3689                 if (has_edp_encoder) {
3690                         target_clock = mode->clock;
3691                         intel_edp_link_config(has_edp_encoder,
3692                                               &lane, &link_bw);
3693                 } else {
3694                         /* DP over FDI requires target mode clock
3695                            instead of link clock */
3696                         if (is_dp)
3697                                 target_clock = mode->clock;
3698                         else
3699                                 target_clock = adjusted_mode->clock;
3700
3701                         /* FDI is a binary signal running at ~2.7GHz, encoding
3702                          * each output octet as 10 bits. The actual frequency
3703                          * is stored as a divider into a 100MHz clock, and the
3704                          * mode pixel clock is stored in units of 1KHz.
3705                          * Hence the bw of each lane in terms of the mode signal
3706                          * is:
3707                          */
3708                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3709                 }
3710
3711                 /* determine panel color depth */
3712                 temp = I915_READ(PIPECONF(pipe));
3713                 temp &= ~PIPE_BPC_MASK;
3714                 if (is_lvds) {
3715                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3716                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3717                                 temp |= PIPE_8BPC;
3718                         else
3719                                 temp |= PIPE_6BPC;
3720                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3721                         switch (dev_priv->edp.bpp/3) {
3722                         case 8:
3723                                 temp |= PIPE_8BPC;
3724                                 break;
3725                         case 10:
3726                                 temp |= PIPE_10BPC;
3727                                 break;
3728                         case 6:
3729                                 temp |= PIPE_6BPC;
3730                                 break;
3731                         case 12:
3732                                 temp |= PIPE_12BPC;
3733                                 break;
3734                         }
3735                 } else
3736                         temp |= PIPE_8BPC;
3737                 I915_WRITE(PIPECONF(pipe), temp);
3738
3739                 switch (temp & PIPE_BPC_MASK) {
3740                 case PIPE_8BPC:
3741                         bpp = 24;
3742                         break;
3743                 case PIPE_10BPC:
3744                         bpp = 30;
3745                         break;
3746                 case PIPE_6BPC:
3747                         bpp = 18;
3748                         break;
3749                 case PIPE_12BPC:
3750                         bpp = 36;
3751                         break;
3752                 default:
3753                         DRM_ERROR("unknown pipe bpc value\n");
3754                         bpp = 24;
3755                 }
3756
3757                 if (!lane) {
3758                         /*
3759                          * Account for spread spectrum to avoid
3760                          * oversubscribing the link. Max center spread
3761                          * is 2.5%; use 5% for safety's sake.
3762                          */
3763                         u32 bps = target_clock * bpp * 21 / 20;
3764                         lane = bps / (link_bw * 8) + 1;
3765                 }
3766
3767                 intel_crtc->fdi_lanes = lane;
3768
3769                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3770         }
3771
3772         /* Ironlake: try to setup display ref clock before DPLL
3773          * enabling. This is only under driver's control after
3774          * PCH B stepping, previous chipset stepping should be
3775          * ignoring this setting.
3776          */
3777         if (HAS_PCH_SPLIT(dev)) {
3778                 temp = I915_READ(PCH_DREF_CONTROL);
3779                 /* Always enable nonspread source */
3780                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3781                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3782                 temp &= ~DREF_SSC_SOURCE_MASK;
3783                 temp |= DREF_SSC_SOURCE_ENABLE;
3784                 I915_WRITE(PCH_DREF_CONTROL, temp);
3785
3786                 POSTING_READ(PCH_DREF_CONTROL);
3787                 udelay(200);
3788
3789                 if (has_edp_encoder) {
3790                         if (dev_priv->lvds_use_ssc) {
3791                                 temp |= DREF_SSC1_ENABLE;
3792                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3793
3794                                 POSTING_READ(PCH_DREF_CONTROL);
3795                                 udelay(200);
3796
3797                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3798                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3799                         } else {
3800                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3801                         }
3802                         I915_WRITE(PCH_DREF_CONTROL, temp);
3803                 }
3804         }
3805
3806         if (IS_PINEVIEW(dev)) {
3807                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3808                 if (has_reduced_clock)
3809                         fp2 = (1 << reduced_clock.n) << 16 |
3810                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3811         } else {
3812                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3813                 if (has_reduced_clock)
3814                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3815                                 reduced_clock.m2;
3816         }
3817
3818         dpll = 0;
3819         if (!HAS_PCH_SPLIT(dev))
3820                 dpll = DPLL_VGA_MODE_DIS;
3821
3822         if (!IS_GEN2(dev)) {
3823                 if (is_lvds)
3824                         dpll |= DPLLB_MODE_LVDS;
3825                 else
3826                         dpll |= DPLLB_MODE_DAC_SERIAL;
3827                 if (is_sdvo) {
3828                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3829                         if (pixel_multiplier > 1) {
3830                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3831                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3832                                 else if (HAS_PCH_SPLIT(dev))
3833                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3834                         }
3835                         dpll |= DPLL_DVO_HIGH_SPEED;
3836                 }
3837                 if (is_dp)
3838                         dpll |= DPLL_DVO_HIGH_SPEED;
3839
3840                 /* compute bitmask from p1 value */
3841                 if (IS_PINEVIEW(dev))
3842                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3843                 else {
3844                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3845                         /* also FPA1 */
3846                         if (HAS_PCH_SPLIT(dev))
3847                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3848                         if (IS_G4X(dev) && has_reduced_clock)
3849                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3850                 }
3851                 switch (clock.p2) {
3852                 case 5:
3853                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3854                         break;
3855                 case 7:
3856                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3857                         break;
3858                 case 10:
3859                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3860                         break;
3861                 case 14:
3862                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3863                         break;
3864                 }
3865                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3866                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3867         } else {
3868                 if (is_lvds) {
3869                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3870                 } else {
3871                         if (clock.p1 == 2)
3872                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3873                         else
3874                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3875                         if (clock.p2 == 4)
3876                                 dpll |= PLL_P2_DIVIDE_BY_4;
3877                 }
3878         }
3879
3880         if (is_sdvo && is_tv)
3881                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3882         else if (is_tv)
3883                 /* XXX: just matching BIOS for now */
3884                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3885                 dpll |= 3;
3886         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3887                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3888         else
3889                 dpll |= PLL_REF_INPUT_DREFCLK;
3890
3891         /* setup pipeconf */
3892         pipeconf = I915_READ(PIPECONF(pipe));
3893
3894         /* Set up the display plane register */
3895         dspcntr = DISPPLANE_GAMMA_ENABLE;
3896
3897         /* Ironlake's plane is forced to pipe, bit 24 is to
3898            enable color space conversion */
3899         if (!HAS_PCH_SPLIT(dev)) {
3900                 if (pipe == 0)
3901                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3902                 else
3903                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3904         }
3905
3906         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3907                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3908                  * core speed.
3909                  *
3910                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3911                  * pipe == 0 check?
3912                  */
3913                 if (mode->clock >
3914                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3915                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3916                 else
3917                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3918         }
3919
3920         dspcntr |= DISPLAY_PLANE_ENABLE;
3921         pipeconf |= PIPECONF_ENABLE;
3922         dpll |= DPLL_VCO_ENABLE;
3923
3924         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3925         drm_mode_debug_printmodeline(mode);
3926
3927         /* assign to Ironlake registers */
3928         if (HAS_PCH_SPLIT(dev)) {
3929                 fp_reg = PCH_FP0(pipe);
3930                 dpll_reg = PCH_DPLL(pipe);
3931         } else {
3932                 fp_reg = FP0(pipe);
3933                 dpll_reg = DPLL(pipe);
3934         }
3935
3936         if (!has_edp_encoder) {
3937                 I915_WRITE(fp_reg, fp);
3938                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3939
3940                 POSTING_READ(dpll_reg);
3941                 udelay(150);
3942         }
3943
3944         /* enable transcoder DPLL */
3945         if (HAS_PCH_CPT(dev)) {
3946                 temp = I915_READ(PCH_DPLL_SEL);
3947                 if (pipe == 0)
3948                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3949                 else
3950                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3951                 I915_WRITE(PCH_DPLL_SEL, temp);
3952
3953                 POSTING_READ(PCH_DPLL_SEL);
3954                 udelay(150);
3955         }
3956
3957         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3958          * This is an exception to the general rule that mode_set doesn't turn
3959          * things on.
3960          */
3961         if (is_lvds) {
3962                 reg = LVDS;
3963                 if (HAS_PCH_SPLIT(dev))
3964                         reg = PCH_LVDS;
3965
3966                 temp = I915_READ(reg);
3967                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3968                 if (pipe == 1) {
3969                         if (HAS_PCH_CPT(dev))
3970                                 temp |= PORT_TRANS_B_SEL_CPT;
3971                         else
3972                                 temp |= LVDS_PIPEB_SELECT;
3973                 } else {
3974                         if (HAS_PCH_CPT(dev))
3975                                 temp &= ~PORT_TRANS_SEL_MASK;
3976                         else
3977                                 temp &= ~LVDS_PIPEB_SELECT;
3978                 }
3979                 /* set the corresponsding LVDS_BORDER bit */
3980                 temp |= dev_priv->lvds_border_bits;
3981                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3982                  * set the DPLLs for dual-channel mode or not.
3983                  */
3984                 if (clock.p2 == 7)
3985                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3986                 else
3987                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3988
3989                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3990                  * appropriately here, but we need to look more thoroughly into how
3991                  * panels behave in the two modes.
3992                  */
3993                 /* set the dithering flag on non-PCH LVDS as needed */
3994                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
3995                         if (dev_priv->lvds_dither)
3996                                 temp |= LVDS_ENABLE_DITHER;
3997                         else
3998                                 temp &= ~LVDS_ENABLE_DITHER;
3999                 }
4000                 I915_WRITE(reg, temp);
4001         }
4002
4003         /* set the dithering flag and clear for anything other than a panel. */
4004         if (HAS_PCH_SPLIT(dev)) {
4005                 pipeconf &= ~PIPECONF_DITHER_EN;
4006                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4007                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4008                         pipeconf |= PIPECONF_DITHER_EN;
4009                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4010                 }
4011         }
4012
4013         if (is_dp)
4014                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4015         else if (HAS_PCH_SPLIT(dev)) {
4016                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4017                 if (pipe == 0) {
4018                         I915_WRITE(TRANSA_DATA_M1, 0);
4019                         I915_WRITE(TRANSA_DATA_N1, 0);
4020                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4021                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4022                 } else {
4023                         I915_WRITE(TRANSB_DATA_M1, 0);
4024                         I915_WRITE(TRANSB_DATA_N1, 0);
4025                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4026                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4027                 }
4028         }
4029
4030         if (!has_edp_encoder) {
4031                 I915_WRITE(fp_reg, fp);
4032                 I915_WRITE(dpll_reg, dpll);
4033
4034                 /* Wait for the clocks to stabilize. */
4035                 POSTING_READ(dpll_reg);
4036                 udelay(150);
4037
4038                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4039                         temp = 0;
4040                         if (is_sdvo) {
4041                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4042                                 if (temp > 1)
4043                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4044                                 else
4045                                         temp = 0;
4046                         }
4047                         I915_WRITE(DPLL_MD(pipe), temp);
4048                 } else {
4049                         /* write it again -- the BIOS does, after all */
4050                         I915_WRITE(dpll_reg, dpll);
4051                 }
4052
4053                 /* Wait for the clocks to stabilize. */
4054                 POSTING_READ(dpll_reg);
4055                 udelay(150);
4056         }
4057
4058         intel_crtc->lowfreq_avail = false;
4059         if (is_lvds && has_reduced_clock && i915_powersave) {
4060                 I915_WRITE(fp_reg + 4, fp2);
4061                 intel_crtc->lowfreq_avail = true;
4062                 if (HAS_PIPE_CXSR(dev)) {
4063                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4064                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4065                 }
4066         } else {
4067                 I915_WRITE(fp_reg + 4, fp);
4068                 if (HAS_PIPE_CXSR(dev)) {
4069                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4070                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4071                 }
4072         }
4073
4074         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4075                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4076                 /* the chip adds 2 halflines automatically */
4077                 adjusted_mode->crtc_vdisplay -= 1;
4078                 adjusted_mode->crtc_vtotal -= 1;
4079                 adjusted_mode->crtc_vblank_start -= 1;
4080                 adjusted_mode->crtc_vblank_end -= 1;
4081                 adjusted_mode->crtc_vsync_end -= 1;
4082                 adjusted_mode->crtc_vsync_start -= 1;
4083         } else
4084                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4085
4086         I915_WRITE(HTOTAL(pipe),
4087                    (adjusted_mode->crtc_hdisplay - 1) |
4088                    ((adjusted_mode->crtc_htotal - 1) << 16));
4089         I915_WRITE(HBLANK(pipe),
4090                    (adjusted_mode->crtc_hblank_start - 1) |
4091                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4092         I915_WRITE(HSYNC(pipe),
4093                    (adjusted_mode->crtc_hsync_start - 1) |
4094                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4095
4096         I915_WRITE(VTOTAL(pipe),
4097                    (adjusted_mode->crtc_vdisplay - 1) |
4098                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4099         I915_WRITE(VBLANK(pipe),
4100                    (adjusted_mode->crtc_vblank_start - 1) |
4101                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4102         I915_WRITE(VSYNC(pipe),
4103                    (adjusted_mode->crtc_vsync_start - 1) |
4104                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4105
4106         /* pipesrc and dspsize control the size that is scaled from,
4107          * which should always be the user's requested size.
4108          */
4109         if (!HAS_PCH_SPLIT(dev)) {
4110                 I915_WRITE(DSPSIZE(plane),
4111                            ((mode->vdisplay - 1) << 16) |
4112                            (mode->hdisplay - 1));
4113                 I915_WRITE(DSPPOS(plane), 0);
4114         }
4115         I915_WRITE(PIPESRC(pipe),
4116                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4117
4118         if (HAS_PCH_SPLIT(dev)) {
4119                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4120                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4121                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4122                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4123
4124                 if (has_edp_encoder) {
4125                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4126                 } else {
4127                         /* enable FDI RX PLL too */
4128                         reg = FDI_RX_CTL(pipe);
4129                         temp = I915_READ(reg);
4130                         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4131
4132                         POSTING_READ(reg);
4133                         udelay(200);
4134
4135                         /* enable FDI TX PLL too */
4136                         reg = FDI_TX_CTL(pipe);
4137                         temp = I915_READ(reg);
4138                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4139
4140                         /* enable FDI RX PCDCLK */
4141                         reg = FDI_RX_CTL(pipe);
4142                         temp = I915_READ(reg);
4143                         I915_WRITE(reg, temp | FDI_PCDCLK);
4144
4145                         POSTING_READ(reg);
4146                         udelay(200);
4147                 }
4148         }
4149
4150         I915_WRITE(PIPECONF(pipe), pipeconf);
4151         POSTING_READ(PIPECONF(pipe));
4152
4153         intel_wait_for_vblank(dev, pipe);
4154
4155         if (IS_IRONLAKE(dev)) {
4156                 /* enable address swizzle for tiling buffer */
4157                 temp = I915_READ(DISP_ARB_CTL);
4158                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4159         }
4160
4161         I915_WRITE(DSPCNTR(plane), dspcntr);
4162
4163         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4164
4165         intel_update_watermarks(dev);
4166
4167         drm_vblank_post_modeset(dev, pipe);
4168
4169         return ret;
4170 }
4171
4172 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4173 void intel_crtc_load_lut(struct drm_crtc *crtc)
4174 {
4175         struct drm_device *dev = crtc->dev;
4176         struct drm_i915_private *dev_priv = dev->dev_private;
4177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4179         int i;
4180
4181         /* The clocks have to be on to load the palette. */
4182         if (!crtc->enabled)
4183                 return;
4184
4185         /* use legacy palette for Ironlake */
4186         if (HAS_PCH_SPLIT(dev))
4187                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4188                                                    LGC_PALETTE_B;
4189
4190         for (i = 0; i < 256; i++) {
4191                 I915_WRITE(palreg + 4 * i,
4192                            (intel_crtc->lut_r[i] << 16) |
4193                            (intel_crtc->lut_g[i] << 8) |
4194                            intel_crtc->lut_b[i]);
4195         }
4196 }
4197
4198 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4199 {
4200         struct drm_device *dev = crtc->dev;
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203         bool visible = base != 0;
4204         u32 cntl;
4205
4206         if (intel_crtc->cursor_visible == visible)
4207                 return;
4208
4209         cntl = I915_READ(CURACNTR);
4210         if (visible) {
4211                 /* On these chipsets we can only modify the base whilst
4212                  * the cursor is disabled.
4213                  */
4214                 I915_WRITE(CURABASE, base);
4215
4216                 cntl &= ~(CURSOR_FORMAT_MASK);
4217                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4218                 cntl |= CURSOR_ENABLE |
4219                         CURSOR_GAMMA_ENABLE |
4220                         CURSOR_FORMAT_ARGB;
4221         } else
4222                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4223         I915_WRITE(CURACNTR, cntl);
4224
4225         intel_crtc->cursor_visible = visible;
4226 }
4227
4228 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         bool visible = base != 0;
4235
4236         if (intel_crtc->cursor_visible != visible) {
4237                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4238                 if (base) {
4239                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4240                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4241                         cntl |= pipe << 28; /* Connect to correct pipe */
4242                 } else {
4243                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4244                         cntl |= CURSOR_MODE_DISABLE;
4245                 }
4246                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4247
4248                 intel_crtc->cursor_visible = visible;
4249         }
4250         /* and commit changes on next vblank */
4251         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4252 }
4253
4254 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4255 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4256                                      bool on)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct drm_i915_private *dev_priv = dev->dev_private;
4260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4261         int pipe = intel_crtc->pipe;
4262         int x = intel_crtc->cursor_x;
4263         int y = intel_crtc->cursor_y;
4264         u32 base, pos;
4265         bool visible;
4266
4267         pos = 0;
4268
4269         if (on && crtc->enabled && crtc->fb) {
4270                 base = intel_crtc->cursor_addr;
4271                 if (x > (int) crtc->fb->width)
4272                         base = 0;
4273
4274                 if (y > (int) crtc->fb->height)
4275                         base = 0;
4276         } else
4277                 base = 0;
4278
4279         if (x < 0) {
4280                 if (x + intel_crtc->cursor_width < 0)
4281                         base = 0;
4282
4283                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4284                 x = -x;
4285         }
4286         pos |= x << CURSOR_X_SHIFT;
4287
4288         if (y < 0) {
4289                 if (y + intel_crtc->cursor_height < 0)
4290                         base = 0;
4291
4292                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4293                 y = -y;
4294         }
4295         pos |= y << CURSOR_Y_SHIFT;
4296
4297         visible = base != 0;
4298         if (!visible && !intel_crtc->cursor_visible)
4299                 return;
4300
4301         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4302         if (IS_845G(dev) || IS_I865G(dev))
4303                 i845_update_cursor(crtc, base);
4304         else
4305                 i9xx_update_cursor(crtc, base);
4306
4307         if (visible)
4308                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4309 }
4310
4311 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4312                                  struct drm_file *file_priv,
4313                                  uint32_t handle,
4314                                  uint32_t width, uint32_t height)
4315 {
4316         struct drm_device *dev = crtc->dev;
4317         struct drm_i915_private *dev_priv = dev->dev_private;
4318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319         struct drm_gem_object *bo;
4320         struct drm_i915_gem_object *obj_priv;
4321         uint32_t addr;
4322         int ret;
4323
4324         DRM_DEBUG_KMS("\n");
4325
4326         /* if we want to turn off the cursor ignore width and height */
4327         if (!handle) {
4328                 DRM_DEBUG_KMS("cursor off\n");
4329                 addr = 0;
4330                 bo = NULL;
4331                 mutex_lock(&dev->struct_mutex);
4332                 goto finish;
4333         }
4334
4335         /* Currently we only support 64x64 cursors */
4336         if (width != 64 || height != 64) {
4337                 DRM_ERROR("we currently only support 64x64 cursors\n");
4338                 return -EINVAL;
4339         }
4340
4341         bo = drm_gem_object_lookup(dev, file_priv, handle);
4342         if (!bo)
4343                 return -ENOENT;
4344
4345         obj_priv = to_intel_bo(bo);
4346
4347         if (bo->size < width * height * 4) {
4348                 DRM_ERROR("buffer is to small\n");
4349                 ret = -ENOMEM;
4350                 goto fail;
4351         }
4352
4353         /* we only need to pin inside GTT if cursor is non-phy */
4354         mutex_lock(&dev->struct_mutex);
4355         if (!dev_priv->info->cursor_needs_physical) {
4356                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4357                 if (ret) {
4358                         DRM_ERROR("failed to pin cursor bo\n");
4359                         goto fail_locked;
4360                 }
4361
4362                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4363                 if (ret) {
4364                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4365                         goto fail_unpin;
4366                 }
4367
4368                 addr = obj_priv->gtt_offset;
4369         } else {
4370                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4371                 ret = i915_gem_attach_phys_object(dev, bo,
4372                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4373                                                   align);
4374                 if (ret) {
4375                         DRM_ERROR("failed to attach phys object\n");
4376                         goto fail_locked;
4377                 }
4378                 addr = obj_priv->phys_obj->handle->busaddr;
4379         }
4380
4381         if (IS_GEN2(dev))
4382                 I915_WRITE(CURSIZE, (height << 12) | width);
4383
4384  finish:
4385         if (intel_crtc->cursor_bo) {
4386                 if (dev_priv->info->cursor_needs_physical) {
4387                         if (intel_crtc->cursor_bo != bo)
4388                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4389                 } else
4390                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4391                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4392         }
4393
4394         mutex_unlock(&dev->struct_mutex);
4395
4396         intel_crtc->cursor_addr = addr;
4397         intel_crtc->cursor_bo = bo;
4398         intel_crtc->cursor_width = width;
4399         intel_crtc->cursor_height = height;
4400
4401         intel_crtc_update_cursor(crtc, true);
4402
4403         return 0;
4404 fail_unpin:
4405         i915_gem_object_unpin(bo);
4406 fail_locked:
4407         mutex_unlock(&dev->struct_mutex);
4408 fail:
4409         drm_gem_object_unreference_unlocked(bo);
4410         return ret;
4411 }
4412
4413 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4414 {
4415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4416
4417         intel_crtc->cursor_x = x;
4418         intel_crtc->cursor_y = y;
4419
4420         intel_crtc_update_cursor(crtc, true);
4421
4422         return 0;
4423 }
4424
4425 /** Sets the color ramps on behalf of RandR */
4426 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4427                                  u16 blue, int regno)
4428 {
4429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4430
4431         intel_crtc->lut_r[regno] = red >> 8;
4432         intel_crtc->lut_g[regno] = green >> 8;
4433         intel_crtc->lut_b[regno] = blue >> 8;
4434 }
4435
4436 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4437                              u16 *blue, int regno)
4438 {
4439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4440
4441         *red = intel_crtc->lut_r[regno] << 8;
4442         *green = intel_crtc->lut_g[regno] << 8;
4443         *blue = intel_crtc->lut_b[regno] << 8;
4444 }
4445
4446 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4447                                  u16 *blue, uint32_t start, uint32_t size)
4448 {
4449         int end = (start + size > 256) ? 256 : start + size, i;
4450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4451
4452         for (i = start; i < end; i++) {
4453                 intel_crtc->lut_r[i] = red[i] >> 8;
4454                 intel_crtc->lut_g[i] = green[i] >> 8;
4455                 intel_crtc->lut_b[i] = blue[i] >> 8;
4456         }
4457
4458         intel_crtc_load_lut(crtc);
4459 }
4460
4461 /**
4462  * Get a pipe with a simple mode set on it for doing load-based monitor
4463  * detection.
4464  *
4465  * It will be up to the load-detect code to adjust the pipe as appropriate for
4466  * its requirements.  The pipe will be connected to no other encoders.
4467  *
4468  * Currently this code will only succeed if there is a pipe with no encoders
4469  * configured for it.  In the future, it could choose to temporarily disable
4470  * some outputs to free up a pipe for its use.
4471  *
4472  * \return crtc, or NULL if no pipes are available.
4473  */
4474
4475 /* VESA 640x480x72Hz mode to set on the pipe */
4476 static struct drm_display_mode load_detect_mode = {
4477         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4478                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4479 };
4480
4481 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4482                                             struct drm_connector *connector,
4483                                             struct drm_display_mode *mode,
4484                                             int *dpms_mode)
4485 {
4486         struct intel_crtc *intel_crtc;
4487         struct drm_crtc *possible_crtc;
4488         struct drm_crtc *supported_crtc =NULL;
4489         struct drm_encoder *encoder = &intel_encoder->base;
4490         struct drm_crtc *crtc = NULL;
4491         struct drm_device *dev = encoder->dev;
4492         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4493         struct drm_crtc_helper_funcs *crtc_funcs;
4494         int i = -1;
4495
4496         /*
4497          * Algorithm gets a little messy:
4498          *   - if the connector already has an assigned crtc, use it (but make
4499          *     sure it's on first)
4500          *   - try to find the first unused crtc that can drive this connector,
4501          *     and use that if we find one
4502          *   - if there are no unused crtcs available, try to use the first
4503          *     one we found that supports the connector
4504          */
4505
4506         /* See if we already have a CRTC for this connector */
4507         if (encoder->crtc) {
4508                 crtc = encoder->crtc;
4509                 /* Make sure the crtc and connector are running */
4510                 intel_crtc = to_intel_crtc(crtc);
4511                 *dpms_mode = intel_crtc->dpms_mode;
4512                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4513                         crtc_funcs = crtc->helper_private;
4514                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4515                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4516                 }
4517                 return crtc;
4518         }
4519
4520         /* Find an unused one (if possible) */
4521         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4522                 i++;
4523                 if (!(encoder->possible_crtcs & (1 << i)))
4524                         continue;
4525                 if (!possible_crtc->enabled) {
4526                         crtc = possible_crtc;
4527                         break;
4528                 }
4529                 if (!supported_crtc)
4530                         supported_crtc = possible_crtc;
4531         }
4532
4533         /*
4534          * If we didn't find an unused CRTC, don't use any.
4535          */
4536         if (!crtc) {
4537                 return NULL;
4538         }
4539
4540         encoder->crtc = crtc;
4541         connector->encoder = encoder;
4542         intel_encoder->load_detect_temp = true;
4543
4544         intel_crtc = to_intel_crtc(crtc);
4545         *dpms_mode = intel_crtc->dpms_mode;
4546
4547         if (!crtc->enabled) {
4548                 if (!mode)
4549                         mode = &load_detect_mode;
4550                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4551         } else {
4552                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4553                         crtc_funcs = crtc->helper_private;
4554                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4555                 }
4556
4557                 /* Add this connector to the crtc */
4558                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4559                 encoder_funcs->commit(encoder);
4560         }
4561         /* let the connector get through one full cycle before testing */
4562         intel_wait_for_vblank(dev, intel_crtc->pipe);
4563
4564         return crtc;
4565 }
4566
4567 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4568                                     struct drm_connector *connector, int dpms_mode)
4569 {
4570         struct drm_encoder *encoder = &intel_encoder->base;
4571         struct drm_device *dev = encoder->dev;
4572         struct drm_crtc *crtc = encoder->crtc;
4573         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4574         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4575
4576         if (intel_encoder->load_detect_temp) {
4577                 encoder->crtc = NULL;
4578                 connector->encoder = NULL;
4579                 intel_encoder->load_detect_temp = false;
4580                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4581                 drm_helper_disable_unused_functions(dev);
4582         }
4583
4584         /* Switch crtc and encoder back off if necessary */
4585         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4586                 if (encoder->crtc == crtc)
4587                         encoder_funcs->dpms(encoder, dpms_mode);
4588                 crtc_funcs->dpms(crtc, dpms_mode);
4589         }
4590 }
4591
4592 /* Returns the clock of the currently programmed mode of the given pipe. */
4593 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4594 {
4595         struct drm_i915_private *dev_priv = dev->dev_private;
4596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597         int pipe = intel_crtc->pipe;
4598         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4599         u32 fp;
4600         intel_clock_t clock;
4601
4602         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4603                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4604         else
4605                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4606
4607         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4608         if (IS_PINEVIEW(dev)) {
4609                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4610                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4611         } else {
4612                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4613                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4614         }
4615
4616         if (!IS_GEN2(dev)) {
4617                 if (IS_PINEVIEW(dev))
4618                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4619                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4620                 else
4621                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4622                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4623
4624                 switch (dpll & DPLL_MODE_MASK) {
4625                 case DPLLB_MODE_DAC_SERIAL:
4626                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4627                                 5 : 10;
4628                         break;
4629                 case DPLLB_MODE_LVDS:
4630                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4631                                 7 : 14;
4632                         break;
4633                 default:
4634                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4635                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4636                         return 0;
4637                 }
4638
4639                 /* XXX: Handle the 100Mhz refclk */
4640                 intel_clock(dev, 96000, &clock);
4641         } else {
4642                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4643
4644                 if (is_lvds) {
4645                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4646                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4647                         clock.p2 = 14;
4648
4649                         if ((dpll & PLL_REF_INPUT_MASK) ==
4650                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4651                                 /* XXX: might not be 66MHz */
4652                                 intel_clock(dev, 66000, &clock);
4653                         } else
4654                                 intel_clock(dev, 48000, &clock);
4655                 } else {
4656                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4657                                 clock.p1 = 2;
4658                         else {
4659                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4660                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4661                         }
4662                         if (dpll & PLL_P2_DIVIDE_BY_4)
4663                                 clock.p2 = 4;
4664                         else
4665                                 clock.p2 = 2;
4666
4667                         intel_clock(dev, 48000, &clock);
4668                 }
4669         }
4670
4671         /* XXX: It would be nice to validate the clocks, but we can't reuse
4672          * i830PllIsValid() because it relies on the xf86_config connector
4673          * configuration being accurate, which it isn't necessarily.
4674          */
4675
4676         return clock.dot;
4677 }
4678
4679 /** Returns the currently programmed mode of the given pipe. */
4680 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4681                                              struct drm_crtc *crtc)
4682 {
4683         struct drm_i915_private *dev_priv = dev->dev_private;
4684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4685         int pipe = intel_crtc->pipe;
4686         struct drm_display_mode *mode;
4687         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4688         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4689         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4690         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4691
4692         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4693         if (!mode)
4694                 return NULL;
4695
4696         mode->clock = intel_crtc_clock_get(dev, crtc);
4697         mode->hdisplay = (htot & 0xffff) + 1;
4698         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4699         mode->hsync_start = (hsync & 0xffff) + 1;
4700         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4701         mode->vdisplay = (vtot & 0xffff) + 1;
4702         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4703         mode->vsync_start = (vsync & 0xffff) + 1;
4704         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4705
4706         drm_mode_set_name(mode);
4707         drm_mode_set_crtcinfo(mode, 0);
4708
4709         return mode;
4710 }
4711
4712 #define GPU_IDLE_TIMEOUT 500 /* ms */
4713
4714 /* When this timer fires, we've been idle for awhile */
4715 static void intel_gpu_idle_timer(unsigned long arg)
4716 {
4717         struct drm_device *dev = (struct drm_device *)arg;
4718         drm_i915_private_t *dev_priv = dev->dev_private;
4719
4720         dev_priv->busy = false;
4721
4722         queue_work(dev_priv->wq, &dev_priv->idle_work);
4723 }
4724
4725 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4726
4727 static void intel_crtc_idle_timer(unsigned long arg)
4728 {
4729         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4730         struct drm_crtc *crtc = &intel_crtc->base;
4731         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4732
4733         intel_crtc->busy = false;
4734
4735         queue_work(dev_priv->wq, &dev_priv->idle_work);
4736 }
4737
4738 static void intel_increase_pllclock(struct drm_crtc *crtc)
4739 {
4740         struct drm_device *dev = crtc->dev;
4741         drm_i915_private_t *dev_priv = dev->dev_private;
4742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743         int pipe = intel_crtc->pipe;
4744         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4745         int dpll = I915_READ(dpll_reg);
4746
4747         if (HAS_PCH_SPLIT(dev))
4748                 return;
4749
4750         if (!dev_priv->lvds_downclock_avail)
4751                 return;
4752
4753         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4754                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4755
4756                 /* Unlock panel regs */
4757                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4758                            PANEL_UNLOCK_REGS);
4759
4760                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4761                 I915_WRITE(dpll_reg, dpll);
4762                 dpll = I915_READ(dpll_reg);
4763                 intel_wait_for_vblank(dev, pipe);
4764                 dpll = I915_READ(dpll_reg);
4765                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4766                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4767
4768                 /* ...and lock them again */
4769                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4770         }
4771
4772         /* Schedule downclock */
4773         mod_timer(&intel_crtc->idle_timer, jiffies +
4774                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4775 }
4776
4777 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4778 {
4779         struct drm_device *dev = crtc->dev;
4780         drm_i915_private_t *dev_priv = dev->dev_private;
4781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782         int pipe = intel_crtc->pipe;
4783         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4784         int dpll = I915_READ(dpll_reg);
4785
4786         if (HAS_PCH_SPLIT(dev))
4787                 return;
4788
4789         if (!dev_priv->lvds_downclock_avail)
4790                 return;
4791
4792         /*
4793          * Since this is called by a timer, we should never get here in
4794          * the manual case.
4795          */
4796         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4797                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4798
4799                 /* Unlock panel regs */
4800                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4801                            PANEL_UNLOCK_REGS);
4802
4803                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4804                 I915_WRITE(dpll_reg, dpll);
4805                 dpll = I915_READ(dpll_reg);
4806                 intel_wait_for_vblank(dev, pipe);
4807                 dpll = I915_READ(dpll_reg);
4808                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4809                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4810
4811                 /* ...and lock them again */
4812                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4813         }
4814
4815 }
4816
4817 /**
4818  * intel_idle_update - adjust clocks for idleness
4819  * @work: work struct
4820  *
4821  * Either the GPU or display (or both) went idle.  Check the busy status
4822  * here and adjust the CRTC and GPU clocks as necessary.
4823  */
4824 static void intel_idle_update(struct work_struct *work)
4825 {
4826         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4827                                                     idle_work);
4828         struct drm_device *dev = dev_priv->dev;
4829         struct drm_crtc *crtc;
4830         struct intel_crtc *intel_crtc;
4831         int enabled = 0;
4832
4833         if (!i915_powersave)
4834                 return;
4835
4836         mutex_lock(&dev->struct_mutex);
4837
4838         i915_update_gfx_val(dev_priv);
4839
4840         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4841                 /* Skip inactive CRTCs */
4842                 if (!crtc->fb)
4843                         continue;
4844
4845                 enabled++;
4846                 intel_crtc = to_intel_crtc(crtc);
4847                 if (!intel_crtc->busy)
4848                         intel_decrease_pllclock(crtc);
4849         }
4850
4851         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4852                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4853                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4854         }
4855
4856         mutex_unlock(&dev->struct_mutex);
4857 }
4858
4859 /**
4860  * intel_mark_busy - mark the GPU and possibly the display busy
4861  * @dev: drm device
4862  * @obj: object we're operating on
4863  *
4864  * Callers can use this function to indicate that the GPU is busy processing
4865  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4866  * buffer), we'll also mark the display as busy, so we know to increase its
4867  * clock frequency.
4868  */
4869 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4870 {
4871         drm_i915_private_t *dev_priv = dev->dev_private;
4872         struct drm_crtc *crtc = NULL;
4873         struct intel_framebuffer *intel_fb;
4874         struct intel_crtc *intel_crtc;
4875
4876         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4877                 return;
4878
4879         if (!dev_priv->busy) {
4880                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4881                         u32 fw_blc_self;
4882
4883                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4884                         fw_blc_self = I915_READ(FW_BLC_SELF);
4885                         fw_blc_self &= ~FW_BLC_SELF_EN;
4886                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4887                 }
4888                 dev_priv->busy = true;
4889         } else
4890                 mod_timer(&dev_priv->idle_timer, jiffies +
4891                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4892
4893         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4894                 if (!crtc->fb)
4895                         continue;
4896
4897                 intel_crtc = to_intel_crtc(crtc);
4898                 intel_fb = to_intel_framebuffer(crtc->fb);
4899                 if (intel_fb->obj == obj) {
4900                         if (!intel_crtc->busy) {
4901                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4902                                         u32 fw_blc_self;
4903
4904                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4905                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4906                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4907                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4908                                 }
4909                                 /* Non-busy -> busy, upclock */
4910                                 intel_increase_pllclock(crtc);
4911                                 intel_crtc->busy = true;
4912                         } else {
4913                                 /* Busy -> busy, put off timer */
4914                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4915                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4916                         }
4917                 }
4918         }
4919 }
4920
4921 static void intel_crtc_destroy(struct drm_crtc *crtc)
4922 {
4923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4924         struct drm_device *dev = crtc->dev;
4925         struct intel_unpin_work *work;
4926         unsigned long flags;
4927
4928         spin_lock_irqsave(&dev->event_lock, flags);
4929         work = intel_crtc->unpin_work;
4930         intel_crtc->unpin_work = NULL;
4931         spin_unlock_irqrestore(&dev->event_lock, flags);
4932
4933         if (work) {
4934                 cancel_work_sync(&work->work);
4935                 kfree(work);
4936         }
4937
4938         drm_crtc_cleanup(crtc);
4939
4940         kfree(intel_crtc);
4941 }
4942
4943 static void intel_unpin_work_fn(struct work_struct *__work)
4944 {
4945         struct intel_unpin_work *work =
4946                 container_of(__work, struct intel_unpin_work, work);
4947
4948         mutex_lock(&work->dev->struct_mutex);
4949         i915_gem_object_unpin(work->old_fb_obj);
4950         drm_gem_object_unreference(work->pending_flip_obj);
4951         drm_gem_object_unreference(work->old_fb_obj);
4952         mutex_unlock(&work->dev->struct_mutex);
4953         kfree(work);
4954 }
4955
4956 static void do_intel_finish_page_flip(struct drm_device *dev,
4957                                       struct drm_crtc *crtc)
4958 {
4959         drm_i915_private_t *dev_priv = dev->dev_private;
4960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4961         struct intel_unpin_work *work;
4962         struct drm_i915_gem_object *obj_priv;
4963         struct drm_pending_vblank_event *e;
4964         struct timeval now;
4965         unsigned long flags;
4966
4967         /* Ignore early vblank irqs */
4968         if (intel_crtc == NULL)
4969                 return;
4970
4971         spin_lock_irqsave(&dev->event_lock, flags);
4972         work = intel_crtc->unpin_work;
4973         if (work == NULL || !work->pending) {
4974                 spin_unlock_irqrestore(&dev->event_lock, flags);
4975                 return;
4976         }
4977
4978         intel_crtc->unpin_work = NULL;
4979         drm_vblank_put(dev, intel_crtc->pipe);
4980
4981         if (work->event) {
4982                 e = work->event;
4983                 do_gettimeofday(&now);
4984                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4985                 e->event.tv_sec = now.tv_sec;
4986                 e->event.tv_usec = now.tv_usec;
4987                 list_add_tail(&e->base.link,
4988                               &e->base.file_priv->event_list);
4989                 wake_up_interruptible(&e->base.file_priv->event_wait);
4990         }
4991
4992         spin_unlock_irqrestore(&dev->event_lock, flags);
4993
4994         obj_priv = to_intel_bo(work->pending_flip_obj);
4995
4996         /* Initial scanout buffer will have a 0 pending flip count */
4997         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4998             atomic_dec_and_test(&obj_priv->pending_flip))
4999                 wake_up(&dev_priv->pending_flip_queue);
5000         schedule_work(&work->work);
5001
5002         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5003 }
5004
5005 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5006 {
5007         drm_i915_private_t *dev_priv = dev->dev_private;
5008         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5009
5010         do_intel_finish_page_flip(dev, crtc);
5011 }
5012
5013 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5014 {
5015         drm_i915_private_t *dev_priv = dev->dev_private;
5016         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5017
5018         do_intel_finish_page_flip(dev, crtc);
5019 }
5020
5021 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5022 {
5023         drm_i915_private_t *dev_priv = dev->dev_private;
5024         struct intel_crtc *intel_crtc =
5025                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5026         unsigned long flags;
5027
5028         spin_lock_irqsave(&dev->event_lock, flags);
5029         if (intel_crtc->unpin_work) {
5030                 if ((++intel_crtc->unpin_work->pending) > 1)
5031                         DRM_ERROR("Prepared flip multiple times\n");
5032         } else {
5033                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5034         }
5035         spin_unlock_irqrestore(&dev->event_lock, flags);
5036 }
5037
5038 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5039                                 struct drm_framebuffer *fb,
5040                                 struct drm_pending_vblank_event *event)
5041 {
5042         struct drm_device *dev = crtc->dev;
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         struct intel_framebuffer *intel_fb;
5045         struct drm_i915_gem_object *obj_priv;
5046         struct drm_gem_object *obj;
5047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048         struct intel_unpin_work *work;
5049         unsigned long flags, offset;
5050         int pipe = intel_crtc->pipe;
5051         u32 pf, pipesrc;
5052         int ret;
5053
5054         work = kzalloc(sizeof *work, GFP_KERNEL);
5055         if (work == NULL)
5056                 return -ENOMEM;
5057
5058         work->event = event;
5059         work->dev = crtc->dev;
5060         intel_fb = to_intel_framebuffer(crtc->fb);
5061         work->old_fb_obj = intel_fb->obj;
5062         INIT_WORK(&work->work, intel_unpin_work_fn);
5063
5064         /* We borrow the event spin lock for protecting unpin_work */
5065         spin_lock_irqsave(&dev->event_lock, flags);
5066         if (intel_crtc->unpin_work) {
5067                 spin_unlock_irqrestore(&dev->event_lock, flags);
5068                 kfree(work);
5069
5070                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5071                 return -EBUSY;
5072         }
5073         intel_crtc->unpin_work = work;
5074         spin_unlock_irqrestore(&dev->event_lock, flags);
5075
5076         intel_fb = to_intel_framebuffer(fb);
5077         obj = intel_fb->obj;
5078
5079         mutex_lock(&dev->struct_mutex);
5080         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5081         if (ret)
5082                 goto cleanup_work;
5083
5084         /* Reference the objects for the scheduled work. */
5085         drm_gem_object_reference(work->old_fb_obj);
5086         drm_gem_object_reference(obj);
5087
5088         crtc->fb = fb;
5089
5090         ret = drm_vblank_get(dev, intel_crtc->pipe);
5091         if (ret)
5092                 goto cleanup_objs;
5093
5094         obj_priv = to_intel_bo(obj);
5095         atomic_inc(&obj_priv->pending_flip);
5096         work->pending_flip_obj = obj;
5097
5098         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5099                 u32 flip_mask;
5100
5101                 /* Can't queue multiple flips, so wait for the previous
5102                  * one to finish before executing the next.
5103                  */
5104                 BEGIN_LP_RING(2);
5105                 if (intel_crtc->plane)
5106                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5107                 else
5108                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5109                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5110                 OUT_RING(MI_NOOP);
5111                 ADVANCE_LP_RING();
5112         }
5113
5114         work->enable_stall_check = true;
5115
5116         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5117         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5118
5119         BEGIN_LP_RING(4);
5120         switch(INTEL_INFO(dev)->gen) {
5121         case 2:
5122                 OUT_RING(MI_DISPLAY_FLIP |
5123                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5124                 OUT_RING(fb->pitch);
5125                 OUT_RING(obj_priv->gtt_offset + offset);
5126                 OUT_RING(MI_NOOP);
5127                 break;
5128
5129         case 3:
5130                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5131                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5132                 OUT_RING(fb->pitch);
5133                 OUT_RING(obj_priv->gtt_offset + offset);
5134                 OUT_RING(MI_NOOP);
5135                 break;
5136
5137         case 4:
5138         case 5:
5139                 /* i965+ uses the linear or tiled offsets from the
5140                  * Display Registers (which do not change across a page-flip)
5141                  * so we need only reprogram the base address.
5142                  */
5143                 OUT_RING(MI_DISPLAY_FLIP |
5144                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5145                 OUT_RING(fb->pitch);
5146                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5147
5148                 /* XXX Enabling the panel-fitter across page-flip is so far
5149                  * untested on non-native modes, so ignore it for now.
5150                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5151                  */
5152                 pf = 0;
5153                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5154                 OUT_RING(pf | pipesrc);
5155                 break;
5156
5157         case 6:
5158                 OUT_RING(MI_DISPLAY_FLIP |
5159                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5160                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5161                 OUT_RING(obj_priv->gtt_offset);
5162
5163                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5164                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5165                 OUT_RING(pf | pipesrc);
5166                 break;
5167         }
5168         ADVANCE_LP_RING();
5169
5170         mutex_unlock(&dev->struct_mutex);
5171
5172         trace_i915_flip_request(intel_crtc->plane, obj);
5173
5174         return 0;
5175
5176 cleanup_objs:
5177         drm_gem_object_unreference(work->old_fb_obj);
5178         drm_gem_object_unreference(obj);
5179 cleanup_work:
5180         mutex_unlock(&dev->struct_mutex);
5181
5182         spin_lock_irqsave(&dev->event_lock, flags);
5183         intel_crtc->unpin_work = NULL;
5184         spin_unlock_irqrestore(&dev->event_lock, flags);
5185
5186         kfree(work);
5187
5188         return ret;
5189 }
5190
5191 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5192         .dpms = intel_crtc_dpms,
5193         .mode_fixup = intel_crtc_mode_fixup,
5194         .mode_set = intel_crtc_mode_set,
5195         .mode_set_base = intel_pipe_set_base,
5196         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5197         .load_lut = intel_crtc_load_lut,
5198         .disable = intel_crtc_disable,
5199 };
5200
5201 static const struct drm_crtc_funcs intel_crtc_funcs = {
5202         .cursor_set = intel_crtc_cursor_set,
5203         .cursor_move = intel_crtc_cursor_move,
5204         .gamma_set = intel_crtc_gamma_set,
5205         .set_config = drm_crtc_helper_set_config,
5206         .destroy = intel_crtc_destroy,
5207         .page_flip = intel_crtc_page_flip,
5208 };
5209
5210
5211 static void intel_crtc_init(struct drm_device *dev, int pipe)
5212 {
5213         drm_i915_private_t *dev_priv = dev->dev_private;
5214         struct intel_crtc *intel_crtc;
5215         int i;
5216
5217         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5218         if (intel_crtc == NULL)
5219                 return;
5220
5221         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5222
5223         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5224         for (i = 0; i < 256; i++) {
5225                 intel_crtc->lut_r[i] = i;
5226                 intel_crtc->lut_g[i] = i;
5227                 intel_crtc->lut_b[i] = i;
5228         }
5229
5230         /* Swap pipes & planes for FBC on pre-965 */
5231         intel_crtc->pipe = pipe;
5232         intel_crtc->plane = pipe;
5233         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5234                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5235                 intel_crtc->plane = !pipe;
5236         }
5237
5238         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5239                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5240         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5241         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5242
5243         intel_crtc->cursor_addr = 0;
5244         intel_crtc->dpms_mode = -1;
5245         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5246
5247         if (HAS_PCH_SPLIT(dev)) {
5248                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5249                 intel_helper_funcs.commit = ironlake_crtc_commit;
5250         } else {
5251                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5252                 intel_helper_funcs.commit = i9xx_crtc_commit;
5253         }
5254
5255         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5256
5257         intel_crtc->busy = false;
5258
5259         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5260                     (unsigned long)intel_crtc);
5261 }
5262
5263 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5264                                 struct drm_file *file_priv)
5265 {
5266         drm_i915_private_t *dev_priv = dev->dev_private;
5267         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5268         struct drm_mode_object *drmmode_obj;
5269         struct intel_crtc *crtc;
5270
5271         if (!dev_priv) {
5272                 DRM_ERROR("called with no initialization\n");
5273                 return -EINVAL;
5274         }
5275
5276         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5277                         DRM_MODE_OBJECT_CRTC);
5278
5279         if (!drmmode_obj) {
5280                 DRM_ERROR("no such CRTC id\n");
5281                 return -EINVAL;
5282         }
5283
5284         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5285         pipe_from_crtc_id->pipe = crtc->pipe;
5286
5287         return 0;
5288 }
5289
5290 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5291 {
5292         struct intel_encoder *encoder;
5293         int index_mask = 0;
5294         int entry = 0;
5295
5296         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5297                 if (type_mask & encoder->clone_mask)
5298                         index_mask |= (1 << entry);
5299                 entry++;
5300         }
5301
5302         return index_mask;
5303 }
5304
5305 static void intel_setup_outputs(struct drm_device *dev)
5306 {
5307         struct drm_i915_private *dev_priv = dev->dev_private;
5308         struct intel_encoder *encoder;
5309         bool dpd_is_edp = false;
5310
5311         if (IS_MOBILE(dev) && !IS_I830(dev))
5312                 intel_lvds_init(dev);
5313
5314         if (HAS_PCH_SPLIT(dev)) {
5315                 dpd_is_edp = intel_dpd_is_edp(dev);
5316
5317                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5318                         intel_dp_init(dev, DP_A);
5319
5320                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5321                         intel_dp_init(dev, PCH_DP_D);
5322         }
5323
5324         intel_crt_init(dev);
5325
5326         if (HAS_PCH_SPLIT(dev)) {
5327                 int found;
5328
5329                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5330                         /* PCH SDVOB multiplex with HDMIB */
5331                         found = intel_sdvo_init(dev, PCH_SDVOB);
5332                         if (!found)
5333                                 intel_hdmi_init(dev, HDMIB);
5334                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5335                                 intel_dp_init(dev, PCH_DP_B);
5336                 }
5337
5338                 if (I915_READ(HDMIC) & PORT_DETECTED)
5339                         intel_hdmi_init(dev, HDMIC);
5340
5341                 if (I915_READ(HDMID) & PORT_DETECTED)
5342                         intel_hdmi_init(dev, HDMID);
5343
5344                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5345                         intel_dp_init(dev, PCH_DP_C);
5346
5347                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5348                         intel_dp_init(dev, PCH_DP_D);
5349
5350         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5351                 bool found = false;
5352
5353                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5354                         DRM_DEBUG_KMS("probing SDVOB\n");
5355                         found = intel_sdvo_init(dev, SDVOB);
5356                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5357                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5358                                 intel_hdmi_init(dev, SDVOB);
5359                         }
5360
5361                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5362                                 DRM_DEBUG_KMS("probing DP_B\n");
5363                                 intel_dp_init(dev, DP_B);
5364                         }
5365                 }
5366
5367                 /* Before G4X SDVOC doesn't have its own detect register */
5368
5369                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5370                         DRM_DEBUG_KMS("probing SDVOC\n");
5371                         found = intel_sdvo_init(dev, SDVOC);
5372                 }
5373
5374                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5375
5376                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5377                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5378                                 intel_hdmi_init(dev, SDVOC);
5379                         }
5380                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5381                                 DRM_DEBUG_KMS("probing DP_C\n");
5382                                 intel_dp_init(dev, DP_C);
5383                         }
5384                 }
5385
5386                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5387                     (I915_READ(DP_D) & DP_DETECTED)) {
5388                         DRM_DEBUG_KMS("probing DP_D\n");
5389                         intel_dp_init(dev, DP_D);
5390                 }
5391         } else if (IS_GEN2(dev))
5392                 intel_dvo_init(dev);
5393
5394         if (SUPPORTS_TV(dev))
5395                 intel_tv_init(dev);
5396
5397         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5398                 encoder->base.possible_crtcs = encoder->crtc_mask;
5399                 encoder->base.possible_clones =
5400                         intel_encoder_clones(dev, encoder->clone_mask);
5401         }
5402 }
5403
5404 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5405 {
5406         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5407
5408         drm_framebuffer_cleanup(fb);
5409         drm_gem_object_unreference_unlocked(intel_fb->obj);
5410
5411         kfree(intel_fb);
5412 }
5413
5414 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5415                                                 struct drm_file *file_priv,
5416                                                 unsigned int *handle)
5417 {
5418         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5419         struct drm_gem_object *object = intel_fb->obj;
5420
5421         return drm_gem_handle_create(file_priv, object, handle);
5422 }
5423
5424 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5425         .destroy = intel_user_framebuffer_destroy,
5426         .create_handle = intel_user_framebuffer_create_handle,
5427 };
5428
5429 int intel_framebuffer_init(struct drm_device *dev,
5430                            struct intel_framebuffer *intel_fb,
5431                            struct drm_mode_fb_cmd *mode_cmd,
5432                            struct drm_gem_object *obj)
5433 {
5434         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5435         int ret;
5436
5437         if (obj_priv->tiling_mode == I915_TILING_Y)
5438                 return -EINVAL;
5439
5440         if (mode_cmd->pitch & 63)
5441                 return -EINVAL;
5442
5443         switch (mode_cmd->bpp) {
5444         case 8:
5445         case 16:
5446         case 24:
5447         case 32:
5448                 break;
5449         default:
5450                 return -EINVAL;
5451         }
5452
5453         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5454         if (ret) {
5455                 DRM_ERROR("framebuffer init failed %d\n", ret);
5456                 return ret;
5457         }
5458
5459         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5460         intel_fb->obj = obj;
5461         return 0;
5462 }
5463
5464 static struct drm_framebuffer *
5465 intel_user_framebuffer_create(struct drm_device *dev,
5466                               struct drm_file *filp,
5467                               struct drm_mode_fb_cmd *mode_cmd)
5468 {
5469         struct drm_gem_object *obj;
5470         struct intel_framebuffer *intel_fb;
5471         int ret;
5472
5473         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5474         if (!obj)
5475                 return ERR_PTR(-ENOENT);
5476
5477         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5478         if (!intel_fb)
5479                 return ERR_PTR(-ENOMEM);
5480
5481         ret = intel_framebuffer_init(dev, intel_fb,
5482                                      mode_cmd, obj);
5483         if (ret) {
5484                 drm_gem_object_unreference_unlocked(obj);
5485                 kfree(intel_fb);
5486                 return ERR_PTR(ret);
5487         }
5488
5489         return &intel_fb->base;
5490 }
5491
5492 static const struct drm_mode_config_funcs intel_mode_funcs = {
5493         .fb_create = intel_user_framebuffer_create,
5494         .output_poll_changed = intel_fb_output_poll_changed,
5495 };
5496
5497 static struct drm_gem_object *
5498 intel_alloc_context_page(struct drm_device *dev)
5499 {
5500         struct drm_gem_object *ctx;
5501         int ret;
5502
5503         ctx = i915_gem_alloc_object(dev, 4096);
5504         if (!ctx) {
5505                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5506                 return NULL;
5507         }
5508
5509         mutex_lock(&dev->struct_mutex);
5510         ret = i915_gem_object_pin(ctx, 4096);
5511         if (ret) {
5512                 DRM_ERROR("failed to pin power context: %d\n", ret);
5513                 goto err_unref;
5514         }
5515
5516         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5517         if (ret) {
5518                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5519                 goto err_unpin;
5520         }
5521         mutex_unlock(&dev->struct_mutex);
5522
5523         return ctx;
5524
5525 err_unpin:
5526         i915_gem_object_unpin(ctx);
5527 err_unref:
5528         drm_gem_object_unreference(ctx);
5529         mutex_unlock(&dev->struct_mutex);
5530         return NULL;
5531 }
5532
5533 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5534 {
5535         struct drm_i915_private *dev_priv = dev->dev_private;
5536         u16 rgvswctl;
5537
5538         rgvswctl = I915_READ16(MEMSWCTL);
5539         if (rgvswctl & MEMCTL_CMD_STS) {
5540                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5541                 return false; /* still busy with another command */
5542         }
5543
5544         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5545                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5546         I915_WRITE16(MEMSWCTL, rgvswctl);
5547         POSTING_READ16(MEMSWCTL);
5548
5549         rgvswctl |= MEMCTL_CMD_STS;
5550         I915_WRITE16(MEMSWCTL, rgvswctl);
5551
5552         return true;
5553 }
5554
5555 void ironlake_enable_drps(struct drm_device *dev)
5556 {
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         u32 rgvmodectl = I915_READ(MEMMODECTL);
5559         u8 fmax, fmin, fstart, vstart;
5560
5561         /* Enable temp reporting */
5562         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5563         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5564
5565         /* 100ms RC evaluation intervals */
5566         I915_WRITE(RCUPEI, 100000);
5567         I915_WRITE(RCDNEI, 100000);
5568
5569         /* Set max/min thresholds to 90ms and 80ms respectively */
5570         I915_WRITE(RCBMAXAVG, 90000);
5571         I915_WRITE(RCBMINAVG, 80000);
5572
5573         I915_WRITE(MEMIHYST, 1);
5574
5575         /* Set up min, max, and cur for interrupt handling */
5576         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5577         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5578         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5579                 MEMMODE_FSTART_SHIFT;
5580         fstart = fmax;
5581
5582         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5583                 PXVFREQ_PX_SHIFT;
5584
5585         dev_priv->fmax = fstart; /* IPS callback will increase this */
5586         dev_priv->fstart = fstart;
5587
5588         dev_priv->max_delay = fmax;
5589         dev_priv->min_delay = fmin;
5590         dev_priv->cur_delay = fstart;
5591
5592         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5593                          fstart);
5594
5595         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5596
5597         /*
5598          * Interrupts will be enabled in ironlake_irq_postinstall
5599          */
5600
5601         I915_WRITE(VIDSTART, vstart);
5602         POSTING_READ(VIDSTART);
5603
5604         rgvmodectl |= MEMMODE_SWMODE_EN;
5605         I915_WRITE(MEMMODECTL, rgvmodectl);
5606
5607         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5608                 DRM_ERROR("stuck trying to change perf mode\n");
5609         msleep(1);
5610
5611         ironlake_set_drps(dev, fstart);
5612
5613         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5614                 I915_READ(0x112e0);
5615         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5616         dev_priv->last_count2 = I915_READ(0x112f4);
5617         getrawmonotonic(&dev_priv->last_time2);
5618 }
5619
5620 void ironlake_disable_drps(struct drm_device *dev)
5621 {
5622         struct drm_i915_private *dev_priv = dev->dev_private;
5623         u16 rgvswctl = I915_READ16(MEMSWCTL);
5624
5625         /* Ack interrupts, disable EFC interrupt */
5626         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5627         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5628         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5629         I915_WRITE(DEIIR, DE_PCU_EVENT);
5630         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5631
5632         /* Go back to the starting frequency */
5633         ironlake_set_drps(dev, dev_priv->fstart);
5634         msleep(1);
5635         rgvswctl |= MEMCTL_CMD_STS;
5636         I915_WRITE(MEMSWCTL, rgvswctl);
5637         msleep(1);
5638
5639 }
5640
5641 static unsigned long intel_pxfreq(u32 vidfreq)
5642 {
5643         unsigned long freq;
5644         int div = (vidfreq & 0x3f0000) >> 16;
5645         int post = (vidfreq & 0x3000) >> 12;
5646         int pre = (vidfreq & 0x7);
5647
5648         if (!pre)
5649                 return 0;
5650
5651         freq = ((div * 133333) / ((1<<post) * pre));
5652
5653         return freq;
5654 }
5655
5656 void intel_init_emon(struct drm_device *dev)
5657 {
5658         struct drm_i915_private *dev_priv = dev->dev_private;
5659         u32 lcfuse;
5660         u8 pxw[16];
5661         int i;
5662
5663         /* Disable to program */
5664         I915_WRITE(ECR, 0);
5665         POSTING_READ(ECR);
5666
5667         /* Program energy weights for various events */
5668         I915_WRITE(SDEW, 0x15040d00);
5669         I915_WRITE(CSIEW0, 0x007f0000);
5670         I915_WRITE(CSIEW1, 0x1e220004);
5671         I915_WRITE(CSIEW2, 0x04000004);
5672
5673         for (i = 0; i < 5; i++)
5674                 I915_WRITE(PEW + (i * 4), 0);
5675         for (i = 0; i < 3; i++)
5676                 I915_WRITE(DEW + (i * 4), 0);
5677
5678         /* Program P-state weights to account for frequency power adjustment */
5679         for (i = 0; i < 16; i++) {
5680                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5681                 unsigned long freq = intel_pxfreq(pxvidfreq);
5682                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5683                         PXVFREQ_PX_SHIFT;
5684                 unsigned long val;
5685
5686                 val = vid * vid;
5687                 val *= (freq / 1000);
5688                 val *= 255;
5689                 val /= (127*127*900);
5690                 if (val > 0xff)
5691                         DRM_ERROR("bad pxval: %ld\n", val);
5692                 pxw[i] = val;
5693         }
5694         /* Render standby states get 0 weight */
5695         pxw[14] = 0;
5696         pxw[15] = 0;
5697
5698         for (i = 0; i < 4; i++) {
5699                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5700                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5701                 I915_WRITE(PXW + (i * 4), val);
5702         }
5703
5704         /* Adjust magic regs to magic values (more experimental results) */
5705         I915_WRITE(OGW0, 0);
5706         I915_WRITE(OGW1, 0);
5707         I915_WRITE(EG0, 0x00007f00);
5708         I915_WRITE(EG1, 0x0000000e);
5709         I915_WRITE(EG2, 0x000e0000);
5710         I915_WRITE(EG3, 0x68000300);
5711         I915_WRITE(EG4, 0x42000000);
5712         I915_WRITE(EG5, 0x00140031);
5713         I915_WRITE(EG6, 0);
5714         I915_WRITE(EG7, 0);
5715
5716         for (i = 0; i < 8; i++)
5717                 I915_WRITE(PXWL + (i * 4), 0);
5718
5719         /* Enable PMON + select events */
5720         I915_WRITE(ECR, 0x80000019);
5721
5722         lcfuse = I915_READ(LCFUSE02);
5723
5724         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5725 }
5726
5727 void intel_init_clock_gating(struct drm_device *dev)
5728 {
5729         struct drm_i915_private *dev_priv = dev->dev_private;
5730
5731         /*
5732          * Disable clock gating reported to work incorrectly according to the
5733          * specs, but enable as much else as we can.
5734          */
5735         if (HAS_PCH_SPLIT(dev)) {
5736                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5737
5738                 if (IS_IRONLAKE(dev)) {
5739                         /* Required for FBC */
5740                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5741                         /* Required for CxSR */
5742                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5743
5744                         I915_WRITE(PCH_3DCGDIS0,
5745                                    MARIUNIT_CLOCK_GATE_DISABLE |
5746                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5747                 }
5748
5749                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5750
5751                 /*
5752                  * According to the spec the following bits should be set in
5753                  * order to enable memory self-refresh
5754                  * The bit 22/21 of 0x42004
5755                  * The bit 5 of 0x42020
5756                  * The bit 15 of 0x45000
5757                  */
5758                 if (IS_IRONLAKE(dev)) {
5759                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5760                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5761                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5762                         I915_WRITE(ILK_DSPCLK_GATE,
5763                                         (I915_READ(ILK_DSPCLK_GATE) |
5764                                                 ILK_DPARB_CLK_GATE));
5765                         I915_WRITE(DISP_ARB_CTL,
5766                                         (I915_READ(DISP_ARB_CTL) |
5767                                                 DISP_FBC_WM_DIS));
5768                 I915_WRITE(WM3_LP_ILK, 0);
5769                 I915_WRITE(WM2_LP_ILK, 0);
5770                 I915_WRITE(WM1_LP_ILK, 0);
5771                 }
5772                 /*
5773                  * Based on the document from hardware guys the following bits
5774                  * should be set unconditionally in order to enable FBC.
5775                  * The bit 22 of 0x42000
5776                  * The bit 22 of 0x42004
5777                  * The bit 7,8,9 of 0x42020.
5778                  */
5779                 if (IS_IRONLAKE_M(dev)) {
5780                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5781                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5782                                    ILK_FBCQ_DIS);
5783                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5784                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5785                                    ILK_DPARB_GATE);
5786                         I915_WRITE(ILK_DSPCLK_GATE,
5787                                    I915_READ(ILK_DSPCLK_GATE) |
5788                                    ILK_DPFC_DIS1 |
5789                                    ILK_DPFC_DIS2 |
5790                                    ILK_CLK_FBC);
5791                 }
5792                 return;
5793         } else if (IS_G4X(dev)) {
5794                 uint32_t dspclk_gate;
5795                 I915_WRITE(RENCLK_GATE_D1, 0);
5796                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5797                        GS_UNIT_CLOCK_GATE_DISABLE |
5798                        CL_UNIT_CLOCK_GATE_DISABLE);
5799                 I915_WRITE(RAMCLK_GATE_D, 0);
5800                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5801                         OVRUNIT_CLOCK_GATE_DISABLE |
5802                         OVCUNIT_CLOCK_GATE_DISABLE;
5803                 if (IS_GM45(dev))
5804                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5805                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5806         } else if (IS_CRESTLINE(dev)) {
5807                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5808                 I915_WRITE(RENCLK_GATE_D2, 0);
5809                 I915_WRITE(DSPCLK_GATE_D, 0);
5810                 I915_WRITE(RAMCLK_GATE_D, 0);
5811                 I915_WRITE16(DEUC, 0);
5812         } else if (IS_BROADWATER(dev)) {
5813                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5814                        I965_RCC_CLOCK_GATE_DISABLE |
5815                        I965_RCPB_CLOCK_GATE_DISABLE |
5816                        I965_ISC_CLOCK_GATE_DISABLE |
5817                        I965_FBC_CLOCK_GATE_DISABLE);
5818                 I915_WRITE(RENCLK_GATE_D2, 0);
5819         } else if (IS_GEN3(dev)) {
5820                 u32 dstate = I915_READ(D_STATE);
5821
5822                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5823                         DSTATE_DOT_CLOCK_GATING;
5824                 I915_WRITE(D_STATE, dstate);
5825         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5826                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5827         } else if (IS_I830(dev)) {
5828                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5829         }
5830
5831         /*
5832          * GPU can automatically power down the render unit if given a page
5833          * to save state.
5834          */
5835         if (IS_IRONLAKE_M(dev)) {
5836                 if (dev_priv->renderctx == NULL)
5837                         dev_priv->renderctx = intel_alloc_context_page(dev);
5838                 if (dev_priv->renderctx) {
5839                         struct drm_i915_gem_object *obj_priv;
5840                         obj_priv = to_intel_bo(dev_priv->renderctx);
5841                         if (obj_priv) {
5842                                 BEGIN_LP_RING(4);
5843                                 OUT_RING(MI_SET_CONTEXT);
5844                                 OUT_RING(obj_priv->gtt_offset |
5845                                                 MI_MM_SPACE_GTT |
5846                                                 MI_SAVE_EXT_STATE_EN |
5847                                                 MI_RESTORE_EXT_STATE_EN |
5848                                                 MI_RESTORE_INHIBIT);
5849                                 OUT_RING(MI_NOOP);
5850                                 OUT_RING(MI_FLUSH);
5851                                 ADVANCE_LP_RING();
5852                         }
5853                 } else
5854                         DRM_DEBUG_KMS("Failed to allocate render context."
5855                                        "Disable RC6\n");
5856         }
5857
5858         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5859                 struct drm_i915_gem_object *obj_priv = NULL;
5860
5861                 if (dev_priv->pwrctx) {
5862                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5863                 } else {
5864                         struct drm_gem_object *pwrctx;
5865
5866                         pwrctx = intel_alloc_context_page(dev);
5867                         if (pwrctx) {
5868                                 dev_priv->pwrctx = pwrctx;
5869                                 obj_priv = to_intel_bo(pwrctx);
5870                         }
5871                 }
5872
5873                 if (obj_priv) {
5874                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5875                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5876                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5877                 }
5878         }
5879 }
5880
5881 /* Set up chip specific display functions */
5882 static void intel_init_display(struct drm_device *dev)
5883 {
5884         struct drm_i915_private *dev_priv = dev->dev_private;
5885
5886         /* We always want a DPMS function */
5887         if (HAS_PCH_SPLIT(dev))
5888                 dev_priv->display.dpms = ironlake_crtc_dpms;
5889         else
5890                 dev_priv->display.dpms = i9xx_crtc_dpms;
5891
5892         if (I915_HAS_FBC(dev)) {
5893                 if (IS_IRONLAKE_M(dev)) {
5894                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5895                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5896                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5897                 } else if (IS_GM45(dev)) {
5898                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5899                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5900                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5901                 } else if (IS_CRESTLINE(dev)) {
5902                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5903                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5904                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5905                 }
5906                 /* 855GM needs testing */
5907         }
5908
5909         /* Returns the core display clock speed */
5910         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5911                 dev_priv->display.get_display_clock_speed =
5912                         i945_get_display_clock_speed;
5913         else if (IS_I915G(dev))
5914                 dev_priv->display.get_display_clock_speed =
5915                         i915_get_display_clock_speed;
5916         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5917                 dev_priv->display.get_display_clock_speed =
5918                         i9xx_misc_get_display_clock_speed;
5919         else if (IS_I915GM(dev))
5920                 dev_priv->display.get_display_clock_speed =
5921                         i915gm_get_display_clock_speed;
5922         else if (IS_I865G(dev))
5923                 dev_priv->display.get_display_clock_speed =
5924                         i865_get_display_clock_speed;
5925         else if (IS_I85X(dev))
5926                 dev_priv->display.get_display_clock_speed =
5927                         i855_get_display_clock_speed;
5928         else /* 852, 830 */
5929                 dev_priv->display.get_display_clock_speed =
5930                         i830_get_display_clock_speed;
5931
5932         /* For FIFO watermark updates */
5933         if (HAS_PCH_SPLIT(dev)) {
5934                 if (IS_IRONLAKE(dev)) {
5935                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5936                                 dev_priv->display.update_wm = ironlake_update_wm;
5937                         else {
5938                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5939                                               "Disable CxSR\n");
5940                                 dev_priv->display.update_wm = NULL;
5941                         }
5942                 } else
5943                         dev_priv->display.update_wm = NULL;
5944         } else if (IS_PINEVIEW(dev)) {
5945                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5946                                             dev_priv->is_ddr3,
5947                                             dev_priv->fsb_freq,
5948                                             dev_priv->mem_freq)) {
5949                         DRM_INFO("failed to find known CxSR latency "
5950                                  "(found ddr%s fsb freq %d, mem freq %d), "
5951                                  "disabling CxSR\n",
5952                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5953                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5954                         /* Disable CxSR and never update its watermark again */
5955                         pineview_disable_cxsr(dev);
5956                         dev_priv->display.update_wm = NULL;
5957                 } else
5958                         dev_priv->display.update_wm = pineview_update_wm;
5959         } else if (IS_G4X(dev))
5960                 dev_priv->display.update_wm = g4x_update_wm;
5961         else if (IS_GEN4(dev))
5962                 dev_priv->display.update_wm = i965_update_wm;
5963         else if (IS_GEN3(dev)) {
5964                 dev_priv->display.update_wm = i9xx_update_wm;
5965                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5966         } else if (IS_I85X(dev)) {
5967                 dev_priv->display.update_wm = i9xx_update_wm;
5968                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5969         } else {
5970                 dev_priv->display.update_wm = i830_update_wm;
5971                 if (IS_845G(dev))
5972                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5973                 else
5974                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5975         }
5976 }
5977
5978 /*
5979  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5980  * resume, or other times.  This quirk makes sure that's the case for
5981  * affected systems.
5982  */
5983 static void quirk_pipea_force (struct drm_device *dev)
5984 {
5985         struct drm_i915_private *dev_priv = dev->dev_private;
5986
5987         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5988         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5989 }
5990
5991 struct intel_quirk {
5992         int device;
5993         int subsystem_vendor;
5994         int subsystem_device;
5995         void (*hook)(struct drm_device *dev);
5996 };
5997
5998 struct intel_quirk intel_quirks[] = {
5999         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6000         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6001         /* HP Mini needs pipe A force quirk (LP: #322104) */
6002         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6003
6004         /* Thinkpad R31 needs pipe A force quirk */
6005         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6006         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6007         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6008
6009         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6010         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6011         /* ThinkPad X40 needs pipe A force quirk */
6012
6013         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6014         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6015
6016         /* 855 & before need to leave pipe A & dpll A up */
6017         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6018         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6019 };
6020
6021 static void intel_init_quirks(struct drm_device *dev)
6022 {
6023         struct pci_dev *d = dev->pdev;
6024         int i;
6025
6026         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6027                 struct intel_quirk *q = &intel_quirks[i];
6028
6029                 if (d->device == q->device &&
6030                     (d->subsystem_vendor == q->subsystem_vendor ||
6031                      q->subsystem_vendor == PCI_ANY_ID) &&
6032                     (d->subsystem_device == q->subsystem_device ||
6033                      q->subsystem_device == PCI_ANY_ID))
6034                         q->hook(dev);
6035         }
6036 }
6037
6038 /* Disable the VGA plane that we never use */
6039 static void i915_disable_vga(struct drm_device *dev)
6040 {
6041         struct drm_i915_private *dev_priv = dev->dev_private;
6042         u8 sr1;
6043         u32 vga_reg;
6044
6045         if (HAS_PCH_SPLIT(dev))
6046                 vga_reg = CPU_VGACNTRL;
6047         else
6048                 vga_reg = VGACNTRL;
6049
6050         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6051         outb(1, VGA_SR_INDEX);
6052         sr1 = inb(VGA_SR_DATA);
6053         outb(sr1 | 1<<5, VGA_SR_DATA);
6054         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6055         udelay(300);
6056
6057         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6058         POSTING_READ(vga_reg);
6059 }
6060
6061 void intel_modeset_init(struct drm_device *dev)
6062 {
6063         struct drm_i915_private *dev_priv = dev->dev_private;
6064         int i;
6065
6066         drm_mode_config_init(dev);
6067
6068         dev->mode_config.min_width = 0;
6069         dev->mode_config.min_height = 0;
6070
6071         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6072
6073         intel_init_quirks(dev);
6074
6075         intel_init_display(dev);
6076
6077         if (IS_GEN2(dev)) {
6078                 dev->mode_config.max_width = 2048;
6079                 dev->mode_config.max_height = 2048;
6080         } else if (IS_GEN3(dev)) {
6081                 dev->mode_config.max_width = 4096;
6082                 dev->mode_config.max_height = 4096;
6083         } else {
6084                 dev->mode_config.max_width = 8192;
6085                 dev->mode_config.max_height = 8192;
6086         }
6087
6088         /* set memory base */
6089         if (IS_GEN2(dev))
6090                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6091         else
6092                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6093
6094         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6095                 dev_priv->num_pipe = 2;
6096         else
6097                 dev_priv->num_pipe = 1;
6098         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6099                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6100
6101         for (i = 0; i < dev_priv->num_pipe; i++) {
6102                 intel_crtc_init(dev, i);
6103         }
6104
6105         intel_setup_outputs(dev);
6106
6107         intel_init_clock_gating(dev);
6108
6109         /* Just disable it once at startup */
6110         i915_disable_vga(dev);
6111
6112         if (IS_IRONLAKE_M(dev)) {
6113                 ironlake_enable_drps(dev);
6114                 intel_init_emon(dev);
6115         }
6116
6117         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6118         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6119                     (unsigned long)dev);
6120
6121         intel_setup_overlay(dev);
6122 }
6123
6124 void intel_modeset_cleanup(struct drm_device *dev)
6125 {
6126         struct drm_i915_private *dev_priv = dev->dev_private;
6127         struct drm_crtc *crtc;
6128         struct intel_crtc *intel_crtc;
6129
6130         drm_kms_helper_poll_fini(dev);
6131         mutex_lock(&dev->struct_mutex);
6132
6133         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6134                 /* Skip inactive CRTCs */
6135                 if (!crtc->fb)
6136                         continue;
6137
6138                 intel_crtc = to_intel_crtc(crtc);
6139                 intel_increase_pllclock(crtc);
6140         }
6141
6142         if (dev_priv->display.disable_fbc)
6143                 dev_priv->display.disable_fbc(dev);
6144
6145         if (dev_priv->renderctx) {
6146                 struct drm_i915_gem_object *obj_priv;
6147
6148                 obj_priv = to_intel_bo(dev_priv->renderctx);
6149                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6150                 I915_READ(CCID);
6151                 i915_gem_object_unpin(dev_priv->renderctx);
6152                 drm_gem_object_unreference(dev_priv->renderctx);
6153         }
6154
6155         if (dev_priv->pwrctx) {
6156                 struct drm_i915_gem_object *obj_priv;
6157
6158                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6159                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6160                 I915_READ(PWRCTXA);
6161                 i915_gem_object_unpin(dev_priv->pwrctx);
6162                 drm_gem_object_unreference(dev_priv->pwrctx);
6163         }
6164
6165         if (IS_IRONLAKE_M(dev))
6166                 ironlake_disable_drps(dev);
6167
6168         mutex_unlock(&dev->struct_mutex);
6169
6170         /* Disable the irq before mode object teardown, for the irq might
6171          * enqueue unpin/hotplug work. */
6172         drm_irq_uninstall(dev);
6173         cancel_work_sync(&dev_priv->hotplug_work);
6174
6175         /* Shut off idle work before the crtcs get freed. */
6176         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6177                 intel_crtc = to_intel_crtc(crtc);
6178                 del_timer_sync(&intel_crtc->idle_timer);
6179         }
6180         del_timer_sync(&dev_priv->idle_timer);
6181         cancel_work_sync(&dev_priv->idle_work);
6182
6183         drm_mode_config_cleanup(dev);
6184 }
6185
6186 /*
6187  * Return which encoder is currently attached for connector.
6188  */
6189 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6190 {
6191         return &intel_attached_encoder(connector)->base;
6192 }
6193
6194 void intel_connector_attach_encoder(struct intel_connector *connector,
6195                                     struct intel_encoder *encoder)
6196 {
6197         connector->encoder = encoder;
6198         drm_mode_connector_attach_encoder(&connector->base,
6199                                           &encoder->base);
6200 }
6201
6202 /*
6203  * set vga decode state - true == enable VGA decode
6204  */
6205 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6206 {
6207         struct drm_i915_private *dev_priv = dev->dev_private;
6208         u16 gmch_ctrl;
6209
6210         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6211         if (state)
6212                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6213         else
6214                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6215         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6216         return 0;
6217 }