1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
36 #define INTEL_GMCH_CTRL 0x52
37 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
39 /* PCI config space */
41 #define HPLLCC 0xc0 /* 855 only */
42 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
43 #define GC_CLOCK_133_200 (0 << 0)
44 #define GC_CLOCK_100_200 (1 << 0)
45 #define GC_CLOCK_100_133 (2 << 0)
46 #define GC_CLOCK_166_250 (3 << 0)
48 #define GCFGC 0xf0 /* 915+ only */
49 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
53 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
74 /* Graphics reset regs */
75 #define I965_GDRST 0xc0 /* PCI config register */
76 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77 #define GRDOM_FULL (0<<2)
78 #define GRDOM_RENDER (1<<2)
79 #define GRDOM_MEDIA (3<<2)
81 #define GEN6_GDRST 0x941c
82 #define GEN6_GRDOM_FULL (1 << 0)
83 #define GEN6_GRDOM_RENDER (1 << 1)
84 #define GEN6_GRDOM_MEDIA (1 << 2)
85 #define GEN6_GRDOM_BLT (1 << 3)
89 #define VGA_ST01_MDA 0x3ba
90 #define VGA_ST01_CGA 0x3da
92 #define VGA_MSR_WRITE 0x3c2
93 #define VGA_MSR_READ 0x3cc
94 #define VGA_MSR_MEM_EN (1<<1)
95 #define VGA_MSR_CGA_MODE (1<<0)
97 #define VGA_SR_INDEX 0x3c4
98 #define VGA_SR_DATA 0x3c5
100 #define VGA_AR_INDEX 0x3c0
101 #define VGA_AR_VID_EN (1<<5)
102 #define VGA_AR_DATA_WRITE 0x3c0
103 #define VGA_AR_DATA_READ 0x3c1
105 #define VGA_GR_INDEX 0x3ce
106 #define VGA_GR_DATA 0x3cf
108 #define VGA_GR_MEM_READ_MODE_SHIFT 3
109 #define VGA_GR_MEM_READ_MODE_PLANE 1
111 #define VGA_GR_MEM_MODE_MASK 0xc
112 #define VGA_GR_MEM_MODE_SHIFT 2
113 #define VGA_GR_MEM_A0000_AFFFF 0
114 #define VGA_GR_MEM_A0000_BFFFF 1
115 #define VGA_GR_MEM_B0000_B7FFF 2
116 #define VGA_GR_MEM_B0000_BFFFF 3
118 #define VGA_DACMASK 0x3c6
119 #define VGA_DACRX 0x3c7
120 #define VGA_DACWX 0x3c8
121 #define VGA_DACDATA 0x3c9
123 #define VGA_CR_INDEX_MDA 0x3b4
124 #define VGA_CR_DATA_MDA 0x3b5
125 #define VGA_CR_INDEX_CGA 0x3d4
126 #define VGA_CR_DATA_CGA 0x3d5
129 * Memory interface instructions used by the kernel
131 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
133 #define MI_NOOP MI_INSTR(0, 0)
134 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
135 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
136 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
137 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
138 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
139 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
140 #define MI_FLUSH MI_INSTR(0x04, 0)
141 #define MI_READ_FLUSH (1 << 0)
142 #define MI_EXE_FLUSH (1 << 1)
143 #define MI_NO_WRITE_FLUSH (1 << 2)
144 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
145 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
146 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
147 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
148 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
149 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
150 #define MI_OVERLAY_CONTINUE (0x0<<21)
151 #define MI_OVERLAY_ON (0x1<<21)
152 #define MI_OVERLAY_OFF (0x2<<21)
153 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
154 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
155 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
156 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
157 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
158 #define MI_MM_SPACE_GTT (1<<8)
159 #define MI_MM_SPACE_PHYSICAL (0<<8)
160 #define MI_SAVE_EXT_STATE_EN (1<<3)
161 #define MI_RESTORE_EXT_STATE_EN (1<<2)
162 #define MI_RESTORE_INHIBIT (1<<0)
163 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
164 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
165 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
166 #define MI_STORE_DWORD_INDEX_SHIFT 2
167 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
168 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
169 * simply ignores the register load under certain conditions.
170 * - One can actually load arbitrary many arbitrary registers: Simply issue x
171 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
173 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
174 #define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */
175 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
176 #define MI_BATCH_NON_SECURE (1)
177 #define MI_BATCH_NON_SECURE_I965 (1<<8)
178 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
179 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
180 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
181 #define MI_SEMAPHORE_UPDATE (1<<21)
182 #define MI_SEMAPHORE_COMPARE (1<<20)
183 #define MI_SEMAPHORE_REGISTER (1<<18)
185 * 3D instructions used by the kernel
187 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
189 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
190 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
191 #define SC_UPDATE_SCISSOR (0x1<<1)
192 #define SC_ENABLE_MASK (0x1<<0)
193 #define SC_ENABLE (0x1<<0)
194 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
195 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
196 #define SCI_YMIN_MASK (0xffff<<16)
197 #define SCI_XMIN_MASK (0xffff<<0)
198 #define SCI_YMAX_MASK (0xffff<<16)
199 #define SCI_XMAX_MASK (0xffff<<0)
200 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
201 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
202 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
203 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
204 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
205 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
206 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
207 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
208 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
209 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
210 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
211 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
212 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
213 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
214 #define BLT_DEPTH_8 (0<<24)
215 #define BLT_DEPTH_16_565 (1<<24)
216 #define BLT_DEPTH_16_1555 (2<<24)
217 #define BLT_DEPTH_32 (3<<24)
218 #define BLT_ROP_GXCOPY (0xcc<<16)
219 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
220 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
221 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
222 #define ASYNC_FLIP (1<<22)
223 #define DISPLAY_PLANE_A (0<<20)
224 #define DISPLAY_PLANE_B (1<<20)
225 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
226 #define PIPE_CONTROL_QW_WRITE (1<<14)
227 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
228 #define PIPE_CONTROL_WC_FLUSH (1<<12)
229 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
230 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
231 #define PIPE_CONTROL_ISP_DIS (1<<9)
232 #define PIPE_CONTROL_NOTIFY (1<<8)
233 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
234 #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
240 #define DEBUG_RESET_I830 0x6070
241 #define DEBUG_RESET_FULL (1<<7)
242 #define DEBUG_RESET_RENDER (1<<8)
243 #define DEBUG_RESET_DISPLAY (1<<9)
249 #define FENCE_REG_830_0 0x2000
250 #define FENCE_REG_945_8 0x3000
251 #define I830_FENCE_START_MASK 0x07f80000
252 #define I830_FENCE_TILING_Y_SHIFT 12
253 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
254 #define I830_FENCE_PITCH_SHIFT 4
255 #define I830_FENCE_REG_VALID (1<<0)
256 #define I915_FENCE_MAX_PITCH_VAL 4
257 #define I830_FENCE_MAX_PITCH_VAL 6
258 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
260 #define I915_FENCE_START_MASK 0x0ff00000
261 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
263 #define FENCE_REG_965_0 0x03000
264 #define I965_FENCE_PITCH_SHIFT 2
265 #define I965_FENCE_TILING_Y_SHIFT 1
266 #define I965_FENCE_REG_VALID (1<<0)
267 #define I965_FENCE_MAX_PITCH_VAL 0x0400
269 #define FENCE_REG_SANDYBRIDGE_0 0x100000
270 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
273 * Instruction and interrupt control regs
275 #define PGTBL_ER 0x02024
276 #define RENDER_RING_BASE 0x02000
277 #define BSD_RING_BASE 0x04000
278 #define GEN6_BSD_RING_BASE 0x12000
279 #define BLT_RING_BASE 0x22000
280 #define RING_TAIL(base) ((base)+0x30)
281 #define RING_HEAD(base) ((base)+0x34)
282 #define RING_START(base) ((base)+0x38)
283 #define RING_CTL(base) ((base)+0x3c)
284 #define RING_SYNC_0(base) ((base)+0x40)
285 #define RING_SYNC_1(base) ((base)+0x44)
286 #define RING_MAX_IDLE(base) ((base)+0x54)
287 #define RING_HWS_PGA(base) ((base)+0x80)
288 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
289 #define RING_ACTHD(base) ((base)+0x74)
290 #define RING_NOPID(base) ((base)+0x94)
291 #define TAIL_ADDR 0x001FFFF8
292 #define HEAD_WRAP_COUNT 0xFFE00000
293 #define HEAD_WRAP_ONE 0x00200000
294 #define HEAD_ADDR 0x001FFFFC
295 #define RING_NR_PAGES 0x001FF000
296 #define RING_REPORT_MASK 0x00000006
297 #define RING_REPORT_64K 0x00000002
298 #define RING_REPORT_128K 0x00000004
299 #define RING_NO_REPORT 0x00000000
300 #define RING_VALID_MASK 0x00000001
301 #define RING_VALID 0x00000001
302 #define RING_INVALID 0x00000000
303 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
304 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
305 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
307 #define PRB0_TAIL 0x02030
308 #define PRB0_HEAD 0x02034
309 #define PRB0_START 0x02038
310 #define PRB0_CTL 0x0203c
311 #define PRB1_TAIL 0x02040 /* 915+ only */
312 #define PRB1_HEAD 0x02044 /* 915+ only */
313 #define PRB1_START 0x02048 /* 915+ only */
314 #define PRB1_CTL 0x0204c /* 915+ only */
316 #define IPEIR_I965 0x02064
317 #define IPEHR_I965 0x02068
318 #define INSTDONE_I965 0x0206c
319 #define INSTPS 0x02070 /* 965+ only */
320 #define INSTDONE1 0x0207c /* 965+ only */
321 #define ACTHD_I965 0x02074
322 #define HWS_PGA 0x02080
323 #define HWS_ADDRESS_MASK 0xfffff000
324 #define HWS_START_ADDRESS_SHIFT 4
325 #define PWRCTXA 0x2088 /* 965GM+ only */
326 #define PWRCTX_EN (1<<0)
327 #define IPEIR 0x02088
328 #define IPEHR 0x0208c
329 #define INSTDONE 0x02090
330 #define NOPID 0x02094
331 #define HWSTAM 0x02098
332 #define VCS_INSTDONE 0x1206C
333 #define VCS_IPEIR 0x12064
334 #define VCS_IPEHR 0x12068
335 #define VCS_ACTHD 0x12074
336 #define BCS_INSTDONE 0x2206C
337 #define BCS_IPEIR 0x22064
338 #define BCS_IPEHR 0x22068
339 #define BCS_ACTHD 0x22074
341 #define ERROR_GEN6 0x040a0
343 /* GM45+ chicken bits -- debug workaround bits that may be required
344 * for various sorts of correct behavior. The top 16 bits of each are
345 * the enables for writing to the corresponding low bit.
347 #define _3D_CHICKEN 0x02084
348 #define _3D_CHICKEN2 0x0208c
349 /* Disables pipelining of read flushes past the SF-WIZ interface.
350 * Required on all Ironlake steppings according to the B-Spec, but the
351 * particular danger of not doing so is not specified.
353 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
354 #define _3D_CHICKEN3 0x02090
356 #define MI_MODE 0x0209c
357 # define VS_TIMER_DISPATCH (1 << 6)
358 # define MI_FLUSH_ENABLE (1 << 11)
360 #define GFX_MODE 0x02520
361 #define GFX_RUN_LIST_ENABLE (1<<15)
362 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
363 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
364 #define GFX_REPLAY_MODE (1<<11)
365 #define GFX_PSMI_GRANULARITY (1<<10)
366 #define GFX_PPGTT_ENABLE (1<<9)
368 #define SCPD0 0x0209c /* 915+ only */
373 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
374 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
375 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
376 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
377 #define I915_HWB_OOM_INTERRUPT (1<<13)
378 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
379 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
380 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
381 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
382 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
383 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
384 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
385 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
386 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
387 #define I915_DEBUG_INTERRUPT (1<<2)
388 #define I915_USER_INTERRUPT (1<<1)
389 #define I915_ASLE_INTERRUPT (1<<0)
390 #define I915_BSD_USER_INTERRUPT (1<<25)
394 #define GM45_ERROR_PAGE_TABLE (1<<5)
395 #define GM45_ERROR_MEM_PRIV (1<<4)
396 #define I915_ERROR_PAGE_TABLE (1<<4)
397 #define GM45_ERROR_CP_PRIV (1<<3)
398 #define I915_ERROR_MEMORY_REFRESH (1<<1)
399 #define I915_ERROR_INSTRUCTION (1<<0)
400 #define INSTPM 0x020c0
401 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
402 #define ACTHD 0x020c8
403 #define FW_BLC 0x020d8
404 #define FW_BLC2 0x020dc
405 #define FW_BLC_SELF 0x020e0 /* 915+ only */
406 #define FW_BLC_SELF_EN_MASK (1<<31)
407 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
408 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
409 #define MM_BURST_LENGTH 0x00700000
410 #define MM_FIFO_WATERMARK 0x0001F000
411 #define LM_BURST_LENGTH 0x00000700
412 #define LM_FIFO_WATERMARK 0x0000001F
413 #define MI_ARB_STATE 0x020e4 /* 915+ only */
414 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
416 /* Make render/texture TLB fetches lower priorty than associated data
417 * fetches. This is not turned on by default
419 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
421 /* Isoch request wait on GTT enable (Display A/B/C streams).
422 * Make isoch requests stall on the TLB update. May cause
423 * display underruns (test mode only)
425 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
427 /* Block grant count for isoch requests when block count is
428 * set to a finite value.
430 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
431 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
432 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
433 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
434 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
436 /* Enable render writes to complete in C2/C3/C4 power states.
437 * If this isn't enabled, render writes are prevented in low
438 * power states. That seems bad to me.
440 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
442 /* This acknowledges an async flip immediately instead
443 * of waiting for 2TLB fetches.
445 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
447 /* Enables non-sequential data reads through arbiter
449 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
451 /* Disable FSB snooping of cacheable write cycles from binner/render
454 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
456 /* Arbiter time slice for non-isoch streams */
457 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
458 #define MI_ARB_TIME_SLICE_1 (0 << 5)
459 #define MI_ARB_TIME_SLICE_2 (1 << 5)
460 #define MI_ARB_TIME_SLICE_4 (2 << 5)
461 #define MI_ARB_TIME_SLICE_6 (3 << 5)
462 #define MI_ARB_TIME_SLICE_8 (4 << 5)
463 #define MI_ARB_TIME_SLICE_10 (5 << 5)
464 #define MI_ARB_TIME_SLICE_14 (6 << 5)
465 #define MI_ARB_TIME_SLICE_16 (7 << 5)
467 /* Low priority grace period page size */
468 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
469 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
471 /* Disable display A/B trickle feed */
472 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
474 /* Set display plane priority */
475 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
476 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
478 #define CACHE_MODE_0 0x02120 /* 915+ only */
479 #define CM0_MASK_SHIFT 16
480 #define CM0_IZ_OPT_DISABLE (1<<6)
481 #define CM0_ZR_OPT_DISABLE (1<<5)
482 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
483 #define CM0_COLOR_EVICT_DISABLE (1<<3)
484 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
485 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
486 #define BB_ADDR 0x02140 /* 8 bytes */
487 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
488 #define ECOSKPD 0x021d0
489 #define ECO_GATING_CX_ONLY (1<<3)
490 #define ECO_FLIP_DONE (1<<0)
492 /* GEN6 interrupt control */
493 #define GEN6_RENDER_HWSTAM 0x2098
494 #define GEN6_RENDER_IMR 0x20a8
495 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
496 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
497 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
498 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
499 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
500 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
501 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
502 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
503 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
505 #define GEN6_BLITTER_HWSTAM 0x22098
506 #define GEN6_BLITTER_IMR 0x220a8
507 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
508 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
509 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
510 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
512 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
513 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
514 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
515 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
516 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
518 #define GEN6_BSD_IMR 0x120a8
519 #define GEN6_BSD_USER_INTERRUPT (1 << 12)
521 #define GEN6_BSD_RNCID 0x12198
524 * Framebuffer compression (915+ only)
527 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
528 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
529 #define FBC_CONTROL 0x03208
530 #define FBC_CTL_EN (1<<31)
531 #define FBC_CTL_PERIODIC (1<<30)
532 #define FBC_CTL_INTERVAL_SHIFT (16)
533 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
534 #define FBC_CTL_C3_IDLE (1<<13)
535 #define FBC_CTL_STRIDE_SHIFT (5)
536 #define FBC_CTL_FENCENO (1<<0)
537 #define FBC_COMMAND 0x0320c
538 #define FBC_CMD_COMPRESS (1<<0)
539 #define FBC_STATUS 0x03210
540 #define FBC_STAT_COMPRESSING (1<<31)
541 #define FBC_STAT_COMPRESSED (1<<30)
542 #define FBC_STAT_MODIFIED (1<<29)
543 #define FBC_STAT_CURRENT_LINE (1<<0)
544 #define FBC_CONTROL2 0x03214
545 #define FBC_CTL_FENCE_DBL (0<<4)
546 #define FBC_CTL_IDLE_IMM (0<<2)
547 #define FBC_CTL_IDLE_FULL (1<<2)
548 #define FBC_CTL_IDLE_LINE (2<<2)
549 #define FBC_CTL_IDLE_DEBUG (3<<2)
550 #define FBC_CTL_CPU_FENCE (1<<1)
551 #define FBC_CTL_PLANEA (0<<0)
552 #define FBC_CTL_PLANEB (1<<0)
553 #define FBC_FENCE_OFF 0x0321b
554 #define FBC_TAG 0x03300
556 #define FBC_LL_SIZE (1536)
558 /* Framebuffer compression for GM45+ */
559 #define DPFC_CB_BASE 0x3200
560 #define DPFC_CONTROL 0x3208
561 #define DPFC_CTL_EN (1<<31)
562 #define DPFC_CTL_PLANEA (0<<30)
563 #define DPFC_CTL_PLANEB (1<<30)
564 #define DPFC_CTL_FENCE_EN (1<<29)
565 #define DPFC_SR_EN (1<<10)
566 #define DPFC_CTL_LIMIT_1X (0<<6)
567 #define DPFC_CTL_LIMIT_2X (1<<6)
568 #define DPFC_CTL_LIMIT_4X (2<<6)
569 #define DPFC_RECOMP_CTL 0x320c
570 #define DPFC_RECOMP_STALL_EN (1<<27)
571 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
572 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
573 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
574 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
575 #define DPFC_STATUS 0x3210
576 #define DPFC_INVAL_SEG_SHIFT (16)
577 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
578 #define DPFC_COMP_SEG_SHIFT (0)
579 #define DPFC_COMP_SEG_MASK (0x000003ff)
580 #define DPFC_STATUS2 0x3214
581 #define DPFC_FENCE_YOFF 0x3218
582 #define DPFC_CHICKEN 0x3224
583 #define DPFC_HT_MODIFY (1<<31)
585 /* Framebuffer compression for Ironlake */
586 #define ILK_DPFC_CB_BASE 0x43200
587 #define ILK_DPFC_CONTROL 0x43208
588 /* The bit 28-8 is reserved */
589 #define DPFC_RESERVED (0x1FFFFF00)
590 #define ILK_DPFC_RECOMP_CTL 0x4320c
591 #define ILK_DPFC_STATUS 0x43210
592 #define ILK_DPFC_FENCE_YOFF 0x43218
593 #define ILK_DPFC_CHICKEN 0x43224
594 #define ILK_FBC_RT_BASE 0x2128
595 #define ILK_FBC_RT_VALID (1<<0)
597 #define ILK_DISPLAY_CHICKEN1 0x42000
598 #define ILK_FBCQ_DIS (1<<22)
599 #define ILK_PABSTRETCH_DIS (1<<21)
603 * Framebuffer compression for Sandybridge
605 * The following two registers are of type GTTMMADR
607 #define SNB_DPFC_CTL_SA 0x100100
608 #define SNB_CPU_FENCE_ENABLE (1<<29)
609 #define DPFC_CPU_FENCE_OFFSET 0x100104
623 # define GPIO_CLOCK_DIR_MASK (1 << 0)
624 # define GPIO_CLOCK_DIR_IN (0 << 1)
625 # define GPIO_CLOCK_DIR_OUT (1 << 1)
626 # define GPIO_CLOCK_VAL_MASK (1 << 2)
627 # define GPIO_CLOCK_VAL_OUT (1 << 3)
628 # define GPIO_CLOCK_VAL_IN (1 << 4)
629 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
630 # define GPIO_DATA_DIR_MASK (1 << 8)
631 # define GPIO_DATA_DIR_IN (0 << 9)
632 # define GPIO_DATA_DIR_OUT (1 << 9)
633 # define GPIO_DATA_VAL_MASK (1 << 10)
634 # define GPIO_DATA_VAL_OUT (1 << 11)
635 # define GPIO_DATA_VAL_IN (1 << 12)
636 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
638 #define GMBUS0 0x5100 /* clock/port select */
639 #define GMBUS_RATE_100KHZ (0<<8)
640 #define GMBUS_RATE_50KHZ (1<<8)
641 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
642 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
643 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
644 #define GMBUS_PORT_DISABLED 0
645 #define GMBUS_PORT_SSC 1
646 #define GMBUS_PORT_VGADDC 2
647 #define GMBUS_PORT_PANEL 3
648 #define GMBUS_PORT_DPC 4 /* HDMIC */
649 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
651 #define GMBUS_PORT_DPD 7 /* HDMID */
652 #define GMBUS_NUM_PORTS 8
653 #define GMBUS1 0x5104 /* command/status */
654 #define GMBUS_SW_CLR_INT (1<<31)
655 #define GMBUS_SW_RDY (1<<30)
656 #define GMBUS_ENT (1<<29) /* enable timeout */
657 #define GMBUS_CYCLE_NONE (0<<25)
658 #define GMBUS_CYCLE_WAIT (1<<25)
659 #define GMBUS_CYCLE_INDEX (2<<25)
660 #define GMBUS_CYCLE_STOP (4<<25)
661 #define GMBUS_BYTE_COUNT_SHIFT 16
662 #define GMBUS_SLAVE_INDEX_SHIFT 8
663 #define GMBUS_SLAVE_ADDR_SHIFT 1
664 #define GMBUS_SLAVE_READ (1<<0)
665 #define GMBUS_SLAVE_WRITE (0<<0)
666 #define GMBUS2 0x5108 /* status */
667 #define GMBUS_INUSE (1<<15)
668 #define GMBUS_HW_WAIT_PHASE (1<<14)
669 #define GMBUS_STALL_TIMEOUT (1<<13)
670 #define GMBUS_INT (1<<12)
671 #define GMBUS_HW_RDY (1<<11)
672 #define GMBUS_SATOER (1<<10)
673 #define GMBUS_ACTIVE (1<<9)
674 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
675 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
676 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
677 #define GMBUS_NAK_EN (1<<3)
678 #define GMBUS_IDLE_EN (1<<2)
679 #define GMBUS_HW_WAIT_EN (1<<1)
680 #define GMBUS_HW_RDY_EN (1<<0)
681 #define GMBUS5 0x5120 /* byte index */
682 #define GMBUS_2BYTE_INDEX_EN (1<<31)
685 * Clock control & power management
690 #define VGA_PD 0x6010
691 #define VGA0_PD_P2_DIV_4 (1 << 7)
692 #define VGA0_PD_P1_DIV_2 (1 << 5)
693 #define VGA0_PD_P1_SHIFT 0
694 #define VGA0_PD_P1_MASK (0x1f << 0)
695 #define VGA1_PD_P2_DIV_4 (1 << 15)
696 #define VGA1_PD_P1_DIV_2 (1 << 13)
697 #define VGA1_PD_P1_SHIFT 8
698 #define VGA1_PD_P1_MASK (0x1f << 8)
699 #define DPLL_A 0x06014
700 #define DPLL_B 0x06018
701 #define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B)
702 #define DPLL_VCO_ENABLE (1 << 31)
703 #define DPLL_DVO_HIGH_SPEED (1 << 30)
704 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
705 #define DPLL_VGA_MODE_DIS (1 << 28)
706 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
707 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
708 #define DPLL_MODE_MASK (3 << 26)
709 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
710 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
711 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
712 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
713 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
714 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
715 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
717 #define SRX_INDEX 0x3c4
718 #define SRX_DATA 0x3c5
720 #define SR01_SCREEN_OFF (1<<5)
723 #define PPCR_ON (1<<0)
726 #define DVOB_ON (1<<31)
728 #define DVOC_ON (1<<31)
730 #define LVDS_ON (1<<31)
732 /* Scratch pad debug 0 reg:
734 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
736 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
737 * this field (only one bit may be set).
739 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
740 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
741 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
742 /* i830, required in DVO non-gang */
743 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
744 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
745 #define PLL_REF_INPUT_DREFCLK (0 << 13)
746 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
747 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
748 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
749 #define PLL_REF_INPUT_MASK (3 << 13)
750 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
752 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
753 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
754 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
755 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
756 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
759 * Parallel to Serial Load Pulse phase selection.
760 * Selects the phase for the 10X DPLL clock for the PCIe
761 * digital display port. The range is 4 to 13; 10 or more
762 * is just a flip delay. The default is 6
764 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
765 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
767 * SDVO multiplier for 945G/GM. Not used on 965.
769 #define SDVO_MULTIPLIER_MASK 0x000000ff
770 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
771 #define SDVO_MULTIPLIER_SHIFT_VGA 0
772 #define DPLL_A_MD 0x0601c /* 965+ only */
774 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
776 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
778 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
779 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
780 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
781 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
782 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
784 * SDVO/UDI pixel multiplier.
786 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
787 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
788 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
789 * dummy bytes in the datastream at an increased clock rate, with both sides of
790 * the link knowing how many bytes are fill.
792 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
793 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
794 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
795 * through an SDVO command.
797 * This register field has values of multiplication factor minus 1, with
798 * a maximum multiplier of 5 for SDVO.
800 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
801 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
803 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
804 * This best be set to the default value (3) or the CRT won't work. No,
805 * I don't entirely understand what this does...
807 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
808 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
809 #define DPLL_B_MD 0x06020 /* 965+ only */
810 #define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD)
815 #define FP0(pipe) _PIPE(pipe, FPA0, FPB0)
816 #define FP1(pipe) _PIPE(pipe, FPA1, FPB1)
817 #define FP_N_DIV_MASK 0x003f0000
818 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
819 #define FP_N_DIV_SHIFT 16
820 #define FP_M1_DIV_MASK 0x00003f00
821 #define FP_M1_DIV_SHIFT 8
822 #define FP_M2_DIV_MASK 0x0000003f
823 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
824 #define FP_M2_DIV_SHIFT 0
825 #define DPLL_TEST 0x606c
826 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
827 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
828 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
829 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
830 #define DPLLB_TEST_N_BYPASS (1 << 19)
831 #define DPLLB_TEST_M_BYPASS (1 << 18)
832 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
833 #define DPLLA_TEST_N_BYPASS (1 << 3)
834 #define DPLLA_TEST_M_BYPASS (1 << 2)
835 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
836 #define D_STATE 0x6104
837 #define DSTATE_GFX_RESET_I830 (1<<6)
838 #define DSTATE_PLL_D3_OFF (1<<3)
839 #define DSTATE_GFX_CLOCK_GATING (1<<1)
840 #define DSTATE_DOT_CLOCK_GATING (1<<0)
841 #define DSPCLK_GATE_D 0x6200
842 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
843 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
844 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
845 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
846 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
847 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
848 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
849 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
850 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
851 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
852 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
853 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
854 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
855 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
856 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
857 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
858 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
859 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
860 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
861 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
862 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
863 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
864 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
865 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
866 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
867 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
868 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
869 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
871 * This bit must be set on the 830 to prevent hangs when turning off the
874 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
875 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
876 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
877 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
878 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
880 #define RENCLK_GATE_D1 0x6204
881 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
882 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
883 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
884 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
885 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
886 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
887 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
888 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
889 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
890 /** This bit must be unset on 855,865 */
891 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
892 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
893 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
894 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
895 /** This bit must be set on 855,865. */
896 # define SV_CLOCK_GATE_DISABLE (1 << 0)
897 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
898 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
899 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
900 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
901 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
902 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
903 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
904 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
905 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
906 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
907 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
908 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
909 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
910 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
911 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
912 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
913 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
915 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
916 /** This bit must always be set on 965G/965GM */
917 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
918 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
919 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
920 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
921 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
922 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
923 /** This bit must always be set on 965G */
924 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
925 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
926 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
927 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
928 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
929 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
930 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
931 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
932 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
933 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
934 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
935 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
936 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
937 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
938 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
939 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
940 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
941 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
942 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
944 #define RENCLK_GATE_D2 0x6208
945 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
946 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
947 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
948 #define RAMCLK_GATE_D 0x6210 /* CRL only */
949 #define DEUC 0x6214 /* CRL only */
955 #define PALETTE_A 0x0a000
956 #define PALETTE_B 0x0a800
963 * This mirrors the MCHBAR MMIO space whose location is determined by
964 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
965 * every way. It is not accessible from the CP register read instructions.
968 #define MCHBAR_MIRROR_BASE 0x10000
970 #define MCHBAR_MIRROR_BASE_SNB 0x140000
972 /** 915-945 and GM965 MCH register controlling DRAM channel access */
974 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
975 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
976 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
977 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
978 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
979 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
981 /** Pineview MCH register contains DDR3 setting */
982 #define CSHRDDR3CTL 0x101a8
983 #define CSHRDDR3CTL_DDR3 (1 << 2)
985 /** 965 MCH register controlling DRAM channel configuration */
986 #define C0DRB3 0x10206
987 #define C1DRB3 0x10606
989 /* Clocking configuration register */
990 #define CLKCFG 0x10c00
991 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
992 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
993 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
994 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
995 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
996 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
997 /* Note, below two are guess */
998 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
999 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1000 #define CLKCFG_FSB_MASK (7 << 0)
1001 #define CLKCFG_MEM_533 (1 << 4)
1002 #define CLKCFG_MEM_667 (2 << 4)
1003 #define CLKCFG_MEM_800 (3 << 4)
1004 #define CLKCFG_MEM_MASK (7 << 4)
1006 #define TSC1 0x11001
1009 #define TSFS 0x11020
1010 #define TSFS_SLOPE_MASK 0x0000ff00
1011 #define TSFS_SLOPE_SHIFT 8
1012 #define TSFS_INTR_MASK 0x000000ff
1014 #define CRSTANDVID 0x11100
1015 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1016 #define PXVFREQ_PX_MASK 0x7f000000
1017 #define PXVFREQ_PX_SHIFT 24
1018 #define VIDFREQ_BASE 0x11110
1019 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1020 #define VIDFREQ2 0x11114
1021 #define VIDFREQ3 0x11118
1022 #define VIDFREQ4 0x1111c
1023 #define VIDFREQ_P0_MASK 0x1f000000
1024 #define VIDFREQ_P0_SHIFT 24
1025 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1026 #define VIDFREQ_P0_CSCLK_SHIFT 20
1027 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1028 #define VIDFREQ_P0_CRCLK_SHIFT 16
1029 #define VIDFREQ_P1_MASK 0x00001f00
1030 #define VIDFREQ_P1_SHIFT 8
1031 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1032 #define VIDFREQ_P1_CSCLK_SHIFT 4
1033 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1034 #define INTTOEXT_BASE_ILK 0x11300
1035 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1036 #define INTTOEXT_MAP3_SHIFT 24
1037 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1038 #define INTTOEXT_MAP2_SHIFT 16
1039 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1040 #define INTTOEXT_MAP1_SHIFT 8
1041 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1042 #define INTTOEXT_MAP0_SHIFT 0
1043 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1044 #define MEMSWCTL 0x11170 /* Ironlake only */
1045 #define MEMCTL_CMD_MASK 0xe000
1046 #define MEMCTL_CMD_SHIFT 13
1047 #define MEMCTL_CMD_RCLK_OFF 0
1048 #define MEMCTL_CMD_RCLK_ON 1
1049 #define MEMCTL_CMD_CHFREQ 2
1050 #define MEMCTL_CMD_CHVID 3
1051 #define MEMCTL_CMD_VMMOFF 4
1052 #define MEMCTL_CMD_VMMON 5
1053 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1054 when command complete */
1055 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1056 #define MEMCTL_FREQ_SHIFT 8
1057 #define MEMCTL_SFCAVM (1<<7)
1058 #define MEMCTL_TGT_VID_MASK 0x007f
1059 #define MEMIHYST 0x1117c
1060 #define MEMINTREN 0x11180 /* 16 bits */
1061 #define MEMINT_RSEXIT_EN (1<<8)
1062 #define MEMINT_CX_SUPR_EN (1<<7)
1063 #define MEMINT_CONT_BUSY_EN (1<<6)
1064 #define MEMINT_AVG_BUSY_EN (1<<5)
1065 #define MEMINT_EVAL_CHG_EN (1<<4)
1066 #define MEMINT_MON_IDLE_EN (1<<3)
1067 #define MEMINT_UP_EVAL_EN (1<<2)
1068 #define MEMINT_DOWN_EVAL_EN (1<<1)
1069 #define MEMINT_SW_CMD_EN (1<<0)
1070 #define MEMINTRSTR 0x11182 /* 16 bits */
1071 #define MEM_RSEXIT_MASK 0xc000
1072 #define MEM_RSEXIT_SHIFT 14
1073 #define MEM_CONT_BUSY_MASK 0x3000
1074 #define MEM_CONT_BUSY_SHIFT 12
1075 #define MEM_AVG_BUSY_MASK 0x0c00
1076 #define MEM_AVG_BUSY_SHIFT 10
1077 #define MEM_EVAL_CHG_MASK 0x0300
1078 #define MEM_EVAL_BUSY_SHIFT 8
1079 #define MEM_MON_IDLE_MASK 0x00c0
1080 #define MEM_MON_IDLE_SHIFT 6
1081 #define MEM_UP_EVAL_MASK 0x0030
1082 #define MEM_UP_EVAL_SHIFT 4
1083 #define MEM_DOWN_EVAL_MASK 0x000c
1084 #define MEM_DOWN_EVAL_SHIFT 2
1085 #define MEM_SW_CMD_MASK 0x0003
1086 #define MEM_INT_STEER_GFX 0
1087 #define MEM_INT_STEER_CMR 1
1088 #define MEM_INT_STEER_SMI 2
1089 #define MEM_INT_STEER_SCI 3
1090 #define MEMINTRSTS 0x11184
1091 #define MEMINT_RSEXIT (1<<7)
1092 #define MEMINT_CONT_BUSY (1<<6)
1093 #define MEMINT_AVG_BUSY (1<<5)
1094 #define MEMINT_EVAL_CHG (1<<4)
1095 #define MEMINT_MON_IDLE (1<<3)
1096 #define MEMINT_UP_EVAL (1<<2)
1097 #define MEMINT_DOWN_EVAL (1<<1)
1098 #define MEMINT_SW_CMD (1<<0)
1099 #define MEMMODECTL 0x11190
1100 #define MEMMODE_BOOST_EN (1<<31)
1101 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1102 #define MEMMODE_BOOST_FREQ_SHIFT 24
1103 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1104 #define MEMMODE_IDLE_MODE_SHIFT 16
1105 #define MEMMODE_IDLE_MODE_EVAL 0
1106 #define MEMMODE_IDLE_MODE_CONT 1
1107 #define MEMMODE_HWIDLE_EN (1<<15)
1108 #define MEMMODE_SWMODE_EN (1<<14)
1109 #define MEMMODE_RCLK_GATE (1<<13)
1110 #define MEMMODE_HW_UPDATE (1<<12)
1111 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1112 #define MEMMODE_FSTART_SHIFT 8
1113 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1114 #define MEMMODE_FMAX_SHIFT 4
1115 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1116 #define RCBMAXAVG 0x1119c
1117 #define MEMSWCTL2 0x1119e /* Cantiga only */
1118 #define SWMEMCMD_RENDER_OFF (0 << 13)
1119 #define SWMEMCMD_RENDER_ON (1 << 13)
1120 #define SWMEMCMD_SWFREQ (2 << 13)
1121 #define SWMEMCMD_TARVID (3 << 13)
1122 #define SWMEMCMD_VRM_OFF (4 << 13)
1123 #define SWMEMCMD_VRM_ON (5 << 13)
1124 #define CMDSTS (1<<12)
1125 #define SFCAVM (1<<11)
1126 #define SWFREQ_MASK 0x0380 /* P0-7 */
1127 #define SWFREQ_SHIFT 7
1128 #define TARVID_MASK 0x001f
1129 #define MEMSTAT_CTG 0x111a0
1130 #define RCBMINAVG 0x111a0
1131 #define RCUPEI 0x111b0
1132 #define RCDNEI 0x111b4
1133 #define MCHBAR_RENDER_STANDBY 0x111b8
1134 #define RCX_SW_EXIT (1<<23)
1135 #define RSX_STATUS_MASK 0x00700000
1136 #define VIDCTL 0x111c0
1137 #define VIDSTS 0x111c8
1138 #define VIDSTART 0x111cc /* 8 bits */
1139 #define MEMSTAT_ILK 0x111f8
1140 #define MEMSTAT_VID_MASK 0x7f00
1141 #define MEMSTAT_VID_SHIFT 8
1142 #define MEMSTAT_PSTATE_MASK 0x00f8
1143 #define MEMSTAT_PSTATE_SHIFT 3
1144 #define MEMSTAT_MON_ACTV (1<<2)
1145 #define MEMSTAT_SRC_CTL_MASK 0x0003
1146 #define MEMSTAT_SRC_CTL_CORE 0
1147 #define MEMSTAT_SRC_CTL_TRB 1
1148 #define MEMSTAT_SRC_CTL_THM 2
1149 #define MEMSTAT_SRC_CTL_STDBY 3
1150 #define RCPREVBSYTUPAVG 0x113b8
1151 #define RCPREVBSYTDNAVG 0x113bc
1152 #define PMMISC 0x11214
1153 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1154 #define SDEW 0x1124c
1155 #define CSIEW0 0x11250
1156 #define CSIEW1 0x11254
1157 #define CSIEW2 0x11258
1160 #define MCHAFE 0x112c0
1161 #define CSIEC 0x112e0
1162 #define DMIEC 0x112e4
1163 #define DDREC 0x112e8
1164 #define PEG0EC 0x112ec
1165 #define PEG1EC 0x112f0
1166 #define GFXEC 0x112f4
1167 #define RPPREVBSYTUPAVG 0x113b8
1168 #define RPPREVBSYTDNAVG 0x113bc
1170 #define ECR_GPFE (1<<31)
1171 #define ECR_IMONE (1<<30)
1172 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1173 #define OGW0 0x11608
1174 #define OGW1 0x1160c
1184 #define PXWL 0x11680
1185 #define LCFUSE02 0x116c0
1186 #define LCFUSE_HIV_MASK 0x000000ff
1187 #define CSIPLL0 0x12c10
1188 #define DDRMPLL1 0X12c20
1189 #define PEG_BAND_GAP_DATA 0x14d68
1191 #define GEN6_GT_PERF_STATUS 0x145948
1192 #define GEN6_RP_STATE_LIMITS 0x145994
1193 #define GEN6_RP_STATE_CAP 0x145998
1196 * Logical Context regs
1199 #define CCID_EN (1<<0)
1204 #define OVADD 0x30000
1205 #define DOVSTA 0x30008
1206 #define OC_BUF (0x3<<20)
1207 #define OGAMC5 0x30010
1208 #define OGAMC4 0x30014
1209 #define OGAMC3 0x30018
1210 #define OGAMC2 0x3001c
1211 #define OGAMC1 0x30020
1212 #define OGAMC0 0x30024
1215 * Display engine regs
1218 /* Pipe A timing regs */
1219 #define HTOTAL_A 0x60000
1220 #define HBLANK_A 0x60004
1221 #define HSYNC_A 0x60008
1222 #define VTOTAL_A 0x6000c
1223 #define VBLANK_A 0x60010
1224 #define VSYNC_A 0x60014
1225 #define PIPEASRC 0x6001c
1226 #define BCLRPAT_A 0x60020
1228 /* Pipe B timing regs */
1229 #define HTOTAL_B 0x61000
1230 #define HBLANK_B 0x61004
1231 #define HSYNC_B 0x61008
1232 #define VTOTAL_B 0x6100c
1233 #define VBLANK_B 0x61010
1234 #define VSYNC_B 0x61014
1235 #define PIPEBSRC 0x6101c
1236 #define BCLRPAT_B 0x61020
1238 #define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B)
1239 #define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B)
1240 #define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B)
1241 #define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B)
1242 #define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B)
1243 #define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B)
1244 #define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B)
1246 /* VGA port control */
1247 #define ADPA 0x61100
1248 #define ADPA_DAC_ENABLE (1<<31)
1249 #define ADPA_DAC_DISABLE 0
1250 #define ADPA_PIPE_SELECT_MASK (1<<30)
1251 #define ADPA_PIPE_A_SELECT 0
1252 #define ADPA_PIPE_B_SELECT (1<<30)
1253 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1254 #define ADPA_SETS_HVPOLARITY 0
1255 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1256 #define ADPA_VSYNC_CNTL_ENABLE 0
1257 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1258 #define ADPA_HSYNC_CNTL_ENABLE 0
1259 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1260 #define ADPA_VSYNC_ACTIVE_LOW 0
1261 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1262 #define ADPA_HSYNC_ACTIVE_LOW 0
1263 #define ADPA_DPMS_MASK (~(3<<10))
1264 #define ADPA_DPMS_ON (0<<10)
1265 #define ADPA_DPMS_SUSPEND (1<<10)
1266 #define ADPA_DPMS_STANDBY (2<<10)
1267 #define ADPA_DPMS_OFF (3<<10)
1270 /* Hotplug control (945+ only) */
1271 #define PORT_HOTPLUG_EN 0x61110
1272 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1273 #define DPB_HOTPLUG_INT_EN (1 << 29)
1274 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1275 #define DPC_HOTPLUG_INT_EN (1 << 28)
1276 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1277 #define DPD_HOTPLUG_INT_EN (1 << 27)
1278 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1279 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1280 #define TV_HOTPLUG_INT_EN (1 << 18)
1281 #define CRT_HOTPLUG_INT_EN (1 << 9)
1282 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1283 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1284 /* must use period 64 on GM45 according to docs */
1285 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1286 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1287 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1288 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1289 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1290 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1291 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1292 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1293 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1294 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1295 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1296 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1298 #define PORT_HOTPLUG_STAT 0x61114
1299 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1300 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1301 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1302 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1303 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1304 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1305 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1306 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1307 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1308 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1309 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1310 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1311 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1312 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1314 /* SDVO port control */
1315 #define SDVOB 0x61140
1316 #define SDVOC 0x61160
1317 #define SDVO_ENABLE (1 << 31)
1318 #define SDVO_PIPE_B_SELECT (1 << 30)
1319 #define SDVO_STALL_SELECT (1 << 29)
1320 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1322 * 915G/GM SDVO pixel multiplier.
1324 * Programmed value is multiplier - 1, up to 5x.
1326 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1328 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1329 #define SDVO_PORT_MULTIPLY_SHIFT 23
1330 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1331 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1332 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1333 #define SDVOC_GANG_MODE (1 << 16)
1334 #define SDVO_ENCODING_SDVO (0x0 << 10)
1335 #define SDVO_ENCODING_HDMI (0x2 << 10)
1336 /** Requird for HDMI operation */
1337 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1338 #define SDVO_BORDER_ENABLE (1 << 7)
1339 #define SDVO_AUDIO_ENABLE (1 << 6)
1340 /** New with 965, default is to be set */
1341 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1342 /** New with 965, default is to be set */
1343 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1344 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1345 #define SDVO_DETECTED (1 << 2)
1346 /* Bits to be preserved when writing */
1347 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1348 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1350 /* DVO port control */
1351 #define DVOA 0x61120
1352 #define DVOB 0x61140
1353 #define DVOC 0x61160
1354 #define DVO_ENABLE (1 << 31)
1355 #define DVO_PIPE_B_SELECT (1 << 30)
1356 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1357 #define DVO_PIPE_STALL (1 << 28)
1358 #define DVO_PIPE_STALL_TV (2 << 28)
1359 #define DVO_PIPE_STALL_MASK (3 << 28)
1360 #define DVO_USE_VGA_SYNC (1 << 15)
1361 #define DVO_DATA_ORDER_I740 (0 << 14)
1362 #define DVO_DATA_ORDER_FP (1 << 14)
1363 #define DVO_VSYNC_DISABLE (1 << 11)
1364 #define DVO_HSYNC_DISABLE (1 << 10)
1365 #define DVO_VSYNC_TRISTATE (1 << 9)
1366 #define DVO_HSYNC_TRISTATE (1 << 8)
1367 #define DVO_BORDER_ENABLE (1 << 7)
1368 #define DVO_DATA_ORDER_GBRG (1 << 6)
1369 #define DVO_DATA_ORDER_RGGB (0 << 6)
1370 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1371 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1372 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1373 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1374 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1375 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1376 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1377 #define DVO_PRESERVE_MASK (0x7<<24)
1378 #define DVOA_SRCDIM 0x61124
1379 #define DVOB_SRCDIM 0x61144
1380 #define DVOC_SRCDIM 0x61164
1381 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1382 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1384 /* LVDS port control */
1385 #define LVDS 0x61180
1387 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1388 * the DPLL semantics change when the LVDS is assigned to that pipe.
1390 #define LVDS_PORT_EN (1 << 31)
1391 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1392 #define LVDS_PIPEB_SELECT (1 << 30)
1393 /* LVDS dithering flag on 965/g4x platform */
1394 #define LVDS_ENABLE_DITHER (1 << 25)
1395 /* Enable border for unscaled (or aspect-scaled) display */
1396 #define LVDS_BORDER_ENABLE (1 << 15)
1398 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1401 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1402 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1403 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1405 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1406 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1409 #define LVDS_A3_POWER_MASK (3 << 6)
1410 #define LVDS_A3_POWER_DOWN (0 << 6)
1411 #define LVDS_A3_POWER_UP (3 << 6)
1413 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1416 #define LVDS_CLKB_POWER_MASK (3 << 4)
1417 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1418 #define LVDS_CLKB_POWER_UP (3 << 4)
1420 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1421 * setting for whether we are in dual-channel mode. The B3 pair will
1422 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1424 #define LVDS_B0B3_POWER_MASK (3 << 2)
1425 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1426 #define LVDS_B0B3_POWER_UP (3 << 2)
1428 /* Video Data Island Packet control */
1429 #define VIDEO_DIP_DATA 0x61178
1430 #define VIDEO_DIP_CTL 0x61170
1431 #define VIDEO_DIP_ENABLE (1 << 31)
1432 #define VIDEO_DIP_PORT_B (1 << 29)
1433 #define VIDEO_DIP_PORT_C (2 << 29)
1434 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
1435 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1436 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
1437 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1438 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1439 #define VIDEO_DIP_SELECT_SPD (3 << 19)
1440 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1441 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1442 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1444 /* Panel power sequencing */
1445 #define PP_STATUS 0x61200
1446 #define PP_ON (1 << 31)
1448 * Indicates that all dependencies of the panel are on:
1452 * - LVDS/DVOB/DVOC on
1454 #define PP_READY (1 << 30)
1455 #define PP_SEQUENCE_NONE (0 << 28)
1456 #define PP_SEQUENCE_ON (1 << 28)
1457 #define PP_SEQUENCE_OFF (2 << 28)
1458 #define PP_SEQUENCE_MASK 0x30000000
1459 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1460 #define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1461 #define PP_SEQUENCE_STATE_MASK 0x0000000f
1462 #define PP_CONTROL 0x61204
1463 #define POWER_TARGET_ON (1 << 0)
1464 #define PP_ON_DELAYS 0x61208
1465 #define PP_OFF_DELAYS 0x6120c
1466 #define PP_DIVISOR 0x61210
1469 #define PFIT_CONTROL 0x61230
1470 #define PFIT_ENABLE (1 << 31)
1471 #define PFIT_PIPE_MASK (3 << 29)
1472 #define PFIT_PIPE_SHIFT 29
1473 #define VERT_INTERP_DISABLE (0 << 10)
1474 #define VERT_INTERP_BILINEAR (1 << 10)
1475 #define VERT_INTERP_MASK (3 << 10)
1476 #define VERT_AUTO_SCALE (1 << 9)
1477 #define HORIZ_INTERP_DISABLE (0 << 6)
1478 #define HORIZ_INTERP_BILINEAR (1 << 6)
1479 #define HORIZ_INTERP_MASK (3 << 6)
1480 #define HORIZ_AUTO_SCALE (1 << 5)
1481 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1482 #define PFIT_FILTER_FUZZY (0 << 24)
1483 #define PFIT_SCALING_AUTO (0 << 26)
1484 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1485 #define PFIT_SCALING_PILLAR (2 << 26)
1486 #define PFIT_SCALING_LETTER (3 << 26)
1487 #define PFIT_PGM_RATIOS 0x61234
1488 #define PFIT_VERT_SCALE_MASK 0xfff00000
1489 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1491 #define PFIT_VERT_SCALE_SHIFT 20
1492 #define PFIT_VERT_SCALE_MASK 0xfff00000
1493 #define PFIT_HORIZ_SCALE_SHIFT 4
1494 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1496 #define PFIT_VERT_SCALE_SHIFT_965 16
1497 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1498 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1499 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1501 #define PFIT_AUTO_RATIOS 0x61238
1503 /* Backlight control */
1504 #define BLC_PWM_CTL 0x61254
1505 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1506 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1507 #define BLM_COMBINATION_MODE (1 << 30)
1509 * This is the most significant 15 bits of the number of backlight cycles in a
1510 * complete cycle of the modulated backlight control.
1512 * The actual value is this field multiplied by two.
1514 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1515 #define BLM_LEGACY_MODE (1 << 16)
1517 * This is the number of cycles out of the backlight modulation cycle for which
1518 * the backlight is on.
1520 * This field must be no greater than the number of cycles in the complete
1521 * backlight modulation cycle.
1523 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1524 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1526 #define BLC_HIST_CTL 0x61260
1528 /* TV port control */
1529 #define TV_CTL 0x68000
1530 /** Enables the TV encoder */
1531 # define TV_ENC_ENABLE (1 << 31)
1532 /** Sources the TV encoder input from pipe B instead of A. */
1533 # define TV_ENC_PIPEB_SELECT (1 << 30)
1534 /** Outputs composite video (DAC A only) */
1535 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1536 /** Outputs SVideo video (DAC B/C) */
1537 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1538 /** Outputs Component video (DAC A/B/C) */
1539 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1540 /** Outputs Composite and SVideo (DAC A/B/C) */
1541 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1542 # define TV_TRILEVEL_SYNC (1 << 21)
1543 /** Enables slow sync generation (945GM only) */
1544 # define TV_SLOW_SYNC (1 << 20)
1545 /** Selects 4x oversampling for 480i and 576p */
1546 # define TV_OVERSAMPLE_4X (0 << 18)
1547 /** Selects 2x oversampling for 720p and 1080i */
1548 # define TV_OVERSAMPLE_2X (1 << 18)
1549 /** Selects no oversampling for 1080p */
1550 # define TV_OVERSAMPLE_NONE (2 << 18)
1551 /** Selects 8x oversampling */
1552 # define TV_OVERSAMPLE_8X (3 << 18)
1553 /** Selects progressive mode rather than interlaced */
1554 # define TV_PROGRESSIVE (1 << 17)
1555 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1556 # define TV_PAL_BURST (1 << 16)
1557 /** Field for setting delay of Y compared to C */
1558 # define TV_YC_SKEW_MASK (7 << 12)
1559 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1560 # define TV_ENC_SDP_FIX (1 << 11)
1562 * Enables a fix for the 915GM only.
1564 * Not sure what it does.
1566 # define TV_ENC_C0_FIX (1 << 10)
1567 /** Bits that must be preserved by software */
1568 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1569 # define TV_FUSE_STATE_MASK (3 << 4)
1570 /** Read-only state that reports all features enabled */
1571 # define TV_FUSE_STATE_ENABLED (0 << 4)
1572 /** Read-only state that reports that Macrovision is disabled in hardware*/
1573 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1574 /** Read-only state that reports that TV-out is disabled in hardware. */
1575 # define TV_FUSE_STATE_DISABLED (2 << 4)
1576 /** Normal operation */
1577 # define TV_TEST_MODE_NORMAL (0 << 0)
1578 /** Encoder test pattern 1 - combo pattern */
1579 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1580 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1581 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1582 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1583 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1584 /** Encoder test pattern 4 - random noise */
1585 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1586 /** Encoder test pattern 5 - linear color ramps */
1587 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1589 * This test mode forces the DACs to 50% of full output.
1591 * This is used for load detection in combination with TVDAC_SENSE_MASK
1593 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1594 # define TV_TEST_MODE_MASK (7 << 0)
1596 #define TV_DAC 0x68004
1597 # define TV_DAC_SAVE 0x00ffff00
1599 * Reports that DAC state change logic has reported change (RO).
1601 * This gets cleared when TV_DAC_STATE_EN is cleared
1603 # define TVDAC_STATE_CHG (1 << 31)
1604 # define TVDAC_SENSE_MASK (7 << 28)
1605 /** Reports that DAC A voltage is above the detect threshold */
1606 # define TVDAC_A_SENSE (1 << 30)
1607 /** Reports that DAC B voltage is above the detect threshold */
1608 # define TVDAC_B_SENSE (1 << 29)
1609 /** Reports that DAC C voltage is above the detect threshold */
1610 # define TVDAC_C_SENSE (1 << 28)
1612 * Enables DAC state detection logic, for load-based TV detection.
1614 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1615 * to off, for load detection to work.
1617 # define TVDAC_STATE_CHG_EN (1 << 27)
1618 /** Sets the DAC A sense value to high */
1619 # define TVDAC_A_SENSE_CTL (1 << 26)
1620 /** Sets the DAC B sense value to high */
1621 # define TVDAC_B_SENSE_CTL (1 << 25)
1622 /** Sets the DAC C sense value to high */
1623 # define TVDAC_C_SENSE_CTL (1 << 24)
1624 /** Overrides the ENC_ENABLE and DAC voltage levels */
1625 # define DAC_CTL_OVERRIDE (1 << 7)
1626 /** Sets the slew rate. Must be preserved in software */
1627 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1628 # define DAC_A_1_3_V (0 << 4)
1629 # define DAC_A_1_1_V (1 << 4)
1630 # define DAC_A_0_7_V (2 << 4)
1631 # define DAC_A_MASK (3 << 4)
1632 # define DAC_B_1_3_V (0 << 2)
1633 # define DAC_B_1_1_V (1 << 2)
1634 # define DAC_B_0_7_V (2 << 2)
1635 # define DAC_B_MASK (3 << 2)
1636 # define DAC_C_1_3_V (0 << 0)
1637 # define DAC_C_1_1_V (1 << 0)
1638 # define DAC_C_0_7_V (2 << 0)
1639 # define DAC_C_MASK (3 << 0)
1642 * CSC coefficients are stored in a floating point format with 9 bits of
1643 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1644 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1645 * -1 (0x3) being the only legal negative value.
1647 #define TV_CSC_Y 0x68010
1648 # define TV_RY_MASK 0x07ff0000
1649 # define TV_RY_SHIFT 16
1650 # define TV_GY_MASK 0x00000fff
1651 # define TV_GY_SHIFT 0
1653 #define TV_CSC_Y2 0x68014
1654 # define TV_BY_MASK 0x07ff0000
1655 # define TV_BY_SHIFT 16
1657 * Y attenuation for component video.
1659 * Stored in 1.9 fixed point.
1661 # define TV_AY_MASK 0x000003ff
1662 # define TV_AY_SHIFT 0
1664 #define TV_CSC_U 0x68018
1665 # define TV_RU_MASK 0x07ff0000
1666 # define TV_RU_SHIFT 16
1667 # define TV_GU_MASK 0x000007ff
1668 # define TV_GU_SHIFT 0
1670 #define TV_CSC_U2 0x6801c
1671 # define TV_BU_MASK 0x07ff0000
1672 # define TV_BU_SHIFT 16
1674 * U attenuation for component video.
1676 * Stored in 1.9 fixed point.
1678 # define TV_AU_MASK 0x000003ff
1679 # define TV_AU_SHIFT 0
1681 #define TV_CSC_V 0x68020
1682 # define TV_RV_MASK 0x0fff0000
1683 # define TV_RV_SHIFT 16
1684 # define TV_GV_MASK 0x000007ff
1685 # define TV_GV_SHIFT 0
1687 #define TV_CSC_V2 0x68024
1688 # define TV_BV_MASK 0x07ff0000
1689 # define TV_BV_SHIFT 16
1691 * V attenuation for component video.
1693 * Stored in 1.9 fixed point.
1695 # define TV_AV_MASK 0x000007ff
1696 # define TV_AV_SHIFT 0
1698 #define TV_CLR_KNOBS 0x68028
1699 /** 2s-complement brightness adjustment */
1700 # define TV_BRIGHTNESS_MASK 0xff000000
1701 # define TV_BRIGHTNESS_SHIFT 24
1702 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1703 # define TV_CONTRAST_MASK 0x00ff0000
1704 # define TV_CONTRAST_SHIFT 16
1705 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1706 # define TV_SATURATION_MASK 0x0000ff00
1707 # define TV_SATURATION_SHIFT 8
1708 /** Hue adjustment, as an integer phase angle in degrees */
1709 # define TV_HUE_MASK 0x000000ff
1710 # define TV_HUE_SHIFT 0
1712 #define TV_CLR_LEVEL 0x6802c
1713 /** Controls the DAC level for black */
1714 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1715 # define TV_BLACK_LEVEL_SHIFT 16
1716 /** Controls the DAC level for blanking */
1717 # define TV_BLANK_LEVEL_MASK 0x000001ff
1718 # define TV_BLANK_LEVEL_SHIFT 0
1720 #define TV_H_CTL_1 0x68030
1721 /** Number of pixels in the hsync. */
1722 # define TV_HSYNC_END_MASK 0x1fff0000
1723 # define TV_HSYNC_END_SHIFT 16
1724 /** Total number of pixels minus one in the line (display and blanking). */
1725 # define TV_HTOTAL_MASK 0x00001fff
1726 # define TV_HTOTAL_SHIFT 0
1728 #define TV_H_CTL_2 0x68034
1729 /** Enables the colorburst (needed for non-component color) */
1730 # define TV_BURST_ENA (1 << 31)
1731 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1732 # define TV_HBURST_START_SHIFT 16
1733 # define TV_HBURST_START_MASK 0x1fff0000
1734 /** Length of the colorburst */
1735 # define TV_HBURST_LEN_SHIFT 0
1736 # define TV_HBURST_LEN_MASK 0x0001fff
1738 #define TV_H_CTL_3 0x68038
1739 /** End of hblank, measured in pixels minus one from start of hsync */
1740 # define TV_HBLANK_END_SHIFT 16
1741 # define TV_HBLANK_END_MASK 0x1fff0000
1742 /** Start of hblank, measured in pixels minus one from start of hsync */
1743 # define TV_HBLANK_START_SHIFT 0
1744 # define TV_HBLANK_START_MASK 0x0001fff
1746 #define TV_V_CTL_1 0x6803c
1748 # define TV_NBR_END_SHIFT 16
1749 # define TV_NBR_END_MASK 0x07ff0000
1751 # define TV_VI_END_F1_SHIFT 8
1752 # define TV_VI_END_F1_MASK 0x00003f00
1754 # define TV_VI_END_F2_SHIFT 0
1755 # define TV_VI_END_F2_MASK 0x0000003f
1757 #define TV_V_CTL_2 0x68040
1758 /** Length of vsync, in half lines */
1759 # define TV_VSYNC_LEN_MASK 0x07ff0000
1760 # define TV_VSYNC_LEN_SHIFT 16
1761 /** Offset of the start of vsync in field 1, measured in one less than the
1762 * number of half lines.
1764 # define TV_VSYNC_START_F1_MASK 0x00007f00
1765 # define TV_VSYNC_START_F1_SHIFT 8
1767 * Offset of the start of vsync in field 2, measured in one less than the
1768 * number of half lines.
1770 # define TV_VSYNC_START_F2_MASK 0x0000007f
1771 # define TV_VSYNC_START_F2_SHIFT 0
1773 #define TV_V_CTL_3 0x68044
1774 /** Enables generation of the equalization signal */
1775 # define TV_EQUAL_ENA (1 << 31)
1776 /** Length of vsync, in half lines */
1777 # define TV_VEQ_LEN_MASK 0x007f0000
1778 # define TV_VEQ_LEN_SHIFT 16
1779 /** Offset of the start of equalization in field 1, measured in one less than
1780 * the number of half lines.
1782 # define TV_VEQ_START_F1_MASK 0x0007f00
1783 # define TV_VEQ_START_F1_SHIFT 8
1785 * Offset of the start of equalization in field 2, measured in one less than
1786 * the number of half lines.
1788 # define TV_VEQ_START_F2_MASK 0x000007f
1789 # define TV_VEQ_START_F2_SHIFT 0
1791 #define TV_V_CTL_4 0x68048
1793 * Offset to start of vertical colorburst, measured in one less than the
1794 * number of lines from vertical start.
1796 # define TV_VBURST_START_F1_MASK 0x003f0000
1797 # define TV_VBURST_START_F1_SHIFT 16
1799 * Offset to the end of vertical colorburst, measured in one less than the
1800 * number of lines from the start of NBR.
1802 # define TV_VBURST_END_F1_MASK 0x000000ff
1803 # define TV_VBURST_END_F1_SHIFT 0
1805 #define TV_V_CTL_5 0x6804c
1807 * Offset to start of vertical colorburst, measured in one less than the
1808 * number of lines from vertical start.
1810 # define TV_VBURST_START_F2_MASK 0x003f0000
1811 # define TV_VBURST_START_F2_SHIFT 16
1813 * Offset to the end of vertical colorburst, measured in one less than the
1814 * number of lines from the start of NBR.
1816 # define TV_VBURST_END_F2_MASK 0x000000ff
1817 # define TV_VBURST_END_F2_SHIFT 0
1819 #define TV_V_CTL_6 0x68050
1821 * Offset to start of vertical colorburst, measured in one less than the
1822 * number of lines from vertical start.
1824 # define TV_VBURST_START_F3_MASK 0x003f0000
1825 # define TV_VBURST_START_F3_SHIFT 16
1827 * Offset to the end of vertical colorburst, measured in one less than the
1828 * number of lines from the start of NBR.
1830 # define TV_VBURST_END_F3_MASK 0x000000ff
1831 # define TV_VBURST_END_F3_SHIFT 0
1833 #define TV_V_CTL_7 0x68054
1835 * Offset to start of vertical colorburst, measured in one less than the
1836 * number of lines from vertical start.
1838 # define TV_VBURST_START_F4_MASK 0x003f0000
1839 # define TV_VBURST_START_F4_SHIFT 16
1841 * Offset to the end of vertical colorburst, measured in one less than the
1842 * number of lines from the start of NBR.
1844 # define TV_VBURST_END_F4_MASK 0x000000ff
1845 # define TV_VBURST_END_F4_SHIFT 0
1847 #define TV_SC_CTL_1 0x68060
1848 /** Turns on the first subcarrier phase generation DDA */
1849 # define TV_SC_DDA1_EN (1 << 31)
1850 /** Turns on the first subcarrier phase generation DDA */
1851 # define TV_SC_DDA2_EN (1 << 30)
1852 /** Turns on the first subcarrier phase generation DDA */
1853 # define TV_SC_DDA3_EN (1 << 29)
1854 /** Sets the subcarrier DDA to reset frequency every other field */
1855 # define TV_SC_RESET_EVERY_2 (0 << 24)
1856 /** Sets the subcarrier DDA to reset frequency every fourth field */
1857 # define TV_SC_RESET_EVERY_4 (1 << 24)
1858 /** Sets the subcarrier DDA to reset frequency every eighth field */
1859 # define TV_SC_RESET_EVERY_8 (2 << 24)
1860 /** Sets the subcarrier DDA to never reset the frequency */
1861 # define TV_SC_RESET_NEVER (3 << 24)
1862 /** Sets the peak amplitude of the colorburst.*/
1863 # define TV_BURST_LEVEL_MASK 0x00ff0000
1864 # define TV_BURST_LEVEL_SHIFT 16
1865 /** Sets the increment of the first subcarrier phase generation DDA */
1866 # define TV_SCDDA1_INC_MASK 0x00000fff
1867 # define TV_SCDDA1_INC_SHIFT 0
1869 #define TV_SC_CTL_2 0x68064
1870 /** Sets the rollover for the second subcarrier phase generation DDA */
1871 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1872 # define TV_SCDDA2_SIZE_SHIFT 16
1873 /** Sets the increent of the second subcarrier phase generation DDA */
1874 # define TV_SCDDA2_INC_MASK 0x00007fff
1875 # define TV_SCDDA2_INC_SHIFT 0
1877 #define TV_SC_CTL_3 0x68068
1878 /** Sets the rollover for the third subcarrier phase generation DDA */
1879 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1880 # define TV_SCDDA3_SIZE_SHIFT 16
1881 /** Sets the increent of the third subcarrier phase generation DDA */
1882 # define TV_SCDDA3_INC_MASK 0x00007fff
1883 # define TV_SCDDA3_INC_SHIFT 0
1885 #define TV_WIN_POS 0x68070
1886 /** X coordinate of the display from the start of horizontal active */
1887 # define TV_XPOS_MASK 0x1fff0000
1888 # define TV_XPOS_SHIFT 16
1889 /** Y coordinate of the display from the start of vertical active (NBR) */
1890 # define TV_YPOS_MASK 0x00000fff
1891 # define TV_YPOS_SHIFT 0
1893 #define TV_WIN_SIZE 0x68074
1894 /** Horizontal size of the display window, measured in pixels*/
1895 # define TV_XSIZE_MASK 0x1fff0000
1896 # define TV_XSIZE_SHIFT 16
1898 * Vertical size of the display window, measured in pixels.
1900 * Must be even for interlaced modes.
1902 # define TV_YSIZE_MASK 0x00000fff
1903 # define TV_YSIZE_SHIFT 0
1905 #define TV_FILTER_CTL_1 0x68080
1907 * Enables automatic scaling calculation.
1909 * If set, the rest of the registers are ignored, and the calculated values can
1910 * be read back from the register.
1912 # define TV_AUTO_SCALE (1 << 31)
1914 * Disables the vertical filter.
1916 * This is required on modes more than 1024 pixels wide */
1917 # define TV_V_FILTER_BYPASS (1 << 29)
1918 /** Enables adaptive vertical filtering */
1919 # define TV_VADAPT (1 << 28)
1920 # define TV_VADAPT_MODE_MASK (3 << 26)
1921 /** Selects the least adaptive vertical filtering mode */
1922 # define TV_VADAPT_MODE_LEAST (0 << 26)
1923 /** Selects the moderately adaptive vertical filtering mode */
1924 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1925 /** Selects the most adaptive vertical filtering mode */
1926 # define TV_VADAPT_MODE_MOST (3 << 26)
1928 * Sets the horizontal scaling factor.
1930 * This should be the fractional part of the horizontal scaling factor divided
1931 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1933 * (src width - 1) / ((oversample * dest width) - 1)
1935 # define TV_HSCALE_FRAC_MASK 0x00003fff
1936 # define TV_HSCALE_FRAC_SHIFT 0
1938 #define TV_FILTER_CTL_2 0x68084
1940 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1942 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1944 # define TV_VSCALE_INT_MASK 0x00038000
1945 # define TV_VSCALE_INT_SHIFT 15
1947 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1949 * \sa TV_VSCALE_INT_MASK
1951 # define TV_VSCALE_FRAC_MASK 0x00007fff
1952 # define TV_VSCALE_FRAC_SHIFT 0
1954 #define TV_FILTER_CTL_3 0x68088
1956 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1958 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1960 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1962 # define TV_VSCALE_IP_INT_MASK 0x00038000
1963 # define TV_VSCALE_IP_INT_SHIFT 15
1965 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1967 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1969 * \sa TV_VSCALE_IP_INT_MASK
1971 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1972 # define TV_VSCALE_IP_FRAC_SHIFT 0
1974 #define TV_CC_CONTROL 0x68090
1975 # define TV_CC_ENABLE (1 << 31)
1977 * Specifies which field to send the CC data in.
1979 * CC data is usually sent in field 0.
1981 # define TV_CC_FID_MASK (1 << 27)
1982 # define TV_CC_FID_SHIFT 27
1983 /** Sets the horizontal position of the CC data. Usually 135. */
1984 # define TV_CC_HOFF_MASK 0x03ff0000
1985 # define TV_CC_HOFF_SHIFT 16
1986 /** Sets the vertical position of the CC data. Usually 21 */
1987 # define TV_CC_LINE_MASK 0x0000003f
1988 # define TV_CC_LINE_SHIFT 0
1990 #define TV_CC_DATA 0x68094
1991 # define TV_CC_RDY (1 << 31)
1992 /** Second word of CC data to be transmitted. */
1993 # define TV_CC_DATA_2_MASK 0x007f0000
1994 # define TV_CC_DATA_2_SHIFT 16
1995 /** First word of CC data to be transmitted. */
1996 # define TV_CC_DATA_1_MASK 0x0000007f
1997 # define TV_CC_DATA_1_SHIFT 0
1999 #define TV_H_LUMA_0 0x68100
2000 #define TV_H_LUMA_59 0x681ec
2001 #define TV_H_CHROMA_0 0x68200
2002 #define TV_H_CHROMA_59 0x682ec
2003 #define TV_V_LUMA_0 0x68300
2004 #define TV_V_LUMA_42 0x683a8
2005 #define TV_V_CHROMA_0 0x68400
2006 #define TV_V_CHROMA_42 0x684a8
2009 #define DP_A 0x64000 /* eDP */
2010 #define DP_B 0x64100
2011 #define DP_C 0x64200
2012 #define DP_D 0x64300
2014 #define DP_PORT_EN (1 << 31)
2015 #define DP_PIPEB_SELECT (1 << 30)
2017 /* Link training mode - select a suitable mode for each stage */
2018 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2019 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2020 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2021 #define DP_LINK_TRAIN_OFF (3 << 28)
2022 #define DP_LINK_TRAIN_MASK (3 << 28)
2023 #define DP_LINK_TRAIN_SHIFT 28
2025 /* CPT Link training mode */
2026 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2027 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2028 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2029 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2030 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2031 #define DP_LINK_TRAIN_SHIFT_CPT 8
2033 /* Signal voltages. These are mostly controlled by the other end */
2034 #define DP_VOLTAGE_0_4 (0 << 25)
2035 #define DP_VOLTAGE_0_6 (1 << 25)
2036 #define DP_VOLTAGE_0_8 (2 << 25)
2037 #define DP_VOLTAGE_1_2 (3 << 25)
2038 #define DP_VOLTAGE_MASK (7 << 25)
2039 #define DP_VOLTAGE_SHIFT 25
2041 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2044 #define DP_PRE_EMPHASIS_0 (0 << 22)
2045 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2046 #define DP_PRE_EMPHASIS_6 (2 << 22)
2047 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2048 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2049 #define DP_PRE_EMPHASIS_SHIFT 22
2051 /* How many wires to use. I guess 3 was too hard */
2052 #define DP_PORT_WIDTH_1 (0 << 19)
2053 #define DP_PORT_WIDTH_2 (1 << 19)
2054 #define DP_PORT_WIDTH_4 (3 << 19)
2055 #define DP_PORT_WIDTH_MASK (7 << 19)
2057 /* Mystic DPCD version 1.1 special mode */
2058 #define DP_ENHANCED_FRAMING (1 << 18)
2061 #define DP_PLL_FREQ_270MHZ (0 << 16)
2062 #define DP_PLL_FREQ_160MHZ (1 << 16)
2063 #define DP_PLL_FREQ_MASK (3 << 16)
2065 /** locked once port is enabled */
2066 #define DP_PORT_REVERSAL (1 << 15)
2069 #define DP_PLL_ENABLE (1 << 14)
2071 /** sends the clock on lane 15 of the PEG for debug */
2072 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2074 #define DP_SCRAMBLING_DISABLE (1 << 12)
2075 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2077 /** limit RGB values to avoid confusing TVs */
2078 #define DP_COLOR_RANGE_16_235 (1 << 8)
2080 /** Turn on the audio link */
2081 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2083 /** vs and hs sync polarity */
2084 #define DP_SYNC_VS_HIGH (1 << 4)
2085 #define DP_SYNC_HS_HIGH (1 << 3)
2088 #define DP_DETECTED (1 << 2)
2090 /** The aux channel provides a way to talk to the
2091 * signal sink for DDC etc. Max packet size supported
2092 * is 20 bytes in each direction, hence the 5 fixed
2095 #define DPA_AUX_CH_CTL 0x64010
2096 #define DPA_AUX_CH_DATA1 0x64014
2097 #define DPA_AUX_CH_DATA2 0x64018
2098 #define DPA_AUX_CH_DATA3 0x6401c
2099 #define DPA_AUX_CH_DATA4 0x64020
2100 #define DPA_AUX_CH_DATA5 0x64024
2102 #define DPB_AUX_CH_CTL 0x64110
2103 #define DPB_AUX_CH_DATA1 0x64114
2104 #define DPB_AUX_CH_DATA2 0x64118
2105 #define DPB_AUX_CH_DATA3 0x6411c
2106 #define DPB_AUX_CH_DATA4 0x64120
2107 #define DPB_AUX_CH_DATA5 0x64124
2109 #define DPC_AUX_CH_CTL 0x64210
2110 #define DPC_AUX_CH_DATA1 0x64214
2111 #define DPC_AUX_CH_DATA2 0x64218
2112 #define DPC_AUX_CH_DATA3 0x6421c
2113 #define DPC_AUX_CH_DATA4 0x64220
2114 #define DPC_AUX_CH_DATA5 0x64224
2116 #define DPD_AUX_CH_CTL 0x64310
2117 #define DPD_AUX_CH_DATA1 0x64314
2118 #define DPD_AUX_CH_DATA2 0x64318
2119 #define DPD_AUX_CH_DATA3 0x6431c
2120 #define DPD_AUX_CH_DATA4 0x64320
2121 #define DPD_AUX_CH_DATA5 0x64324
2123 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2124 #define DP_AUX_CH_CTL_DONE (1 << 30)
2125 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2126 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2127 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2128 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2129 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2130 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2131 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2132 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2133 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2134 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2135 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2136 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2137 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2138 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2139 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2140 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2141 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2142 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2143 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2146 * Computing GMCH M and N values for the Display Port link
2148 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2150 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2152 * The GMCH value is used internally
2154 * bytes_per_pixel is the number of bytes coming out of the plane,
2155 * which is after the LUTs, so we want the bytes for our color format.
2156 * For our current usage, this is always 3, one byte for R, G and B.
2158 #define PIPEA_GMCH_DATA_M 0x70050
2159 #define PIPEB_GMCH_DATA_M 0x71050
2161 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2162 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2163 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2165 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2167 #define PIPEA_GMCH_DATA_N 0x70054
2168 #define PIPEB_GMCH_DATA_N 0x71054
2169 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2172 * Computing Link M and N values for the Display Port link
2174 * Link M / N = pixel_clock / ls_clk
2176 * (the DP spec calls pixel_clock the 'strm_clk')
2178 * The Link value is transmitted in the Main Stream
2179 * Attributes and VB-ID.
2182 #define PIPEA_DP_LINK_M 0x70060
2183 #define PIPEB_DP_LINK_M 0x71060
2184 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2186 #define PIPEA_DP_LINK_N 0x70064
2187 #define PIPEB_DP_LINK_N 0x71064
2188 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2190 /* Display & cursor control */
2193 #define PIPEADSL 0x70000
2194 #define DSL_LINEMASK 0x00000fff
2195 #define PIPEACONF 0x70008
2196 #define PIPECONF_ENABLE (1<<31)
2197 #define PIPECONF_DISABLE 0
2198 #define PIPECONF_DOUBLE_WIDE (1<<30)
2199 #define I965_PIPECONF_ACTIVE (1<<30)
2200 #define PIPECONF_SINGLE_WIDE 0
2201 #define PIPECONF_PIPE_UNLOCKED 0
2202 #define PIPECONF_PIPE_LOCKED (1<<25)
2203 #define PIPECONF_PALETTE 0
2204 #define PIPECONF_GAMMA (1<<24)
2205 #define PIPECONF_FORCE_BORDER (1<<25)
2206 #define PIPECONF_PROGRESSIVE (0 << 21)
2207 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2208 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2209 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2210 #define PIPECONF_BPP_MASK (0x000000e0)
2211 #define PIPECONF_BPP_8 (0<<5)
2212 #define PIPECONF_BPP_10 (1<<5)
2213 #define PIPECONF_BPP_6 (2<<5)
2214 #define PIPECONF_BPP_12 (3<<5)
2215 #define PIPECONF_DITHER_EN (1<<4)
2216 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2217 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2218 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2219 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2220 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2221 #define PIPEASTAT 0x70024
2222 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2223 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2224 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2225 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2226 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2227 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2228 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2229 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2230 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2231 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2232 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2233 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2234 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2235 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2236 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2237 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2238 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2239 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2240 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2241 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2242 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2243 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2244 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2245 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2246 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2247 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2248 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2249 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2250 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2251 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2252 #define PIPE_8BPC (0 << 5)
2253 #define PIPE_10BPC (1 << 5)
2254 #define PIPE_6BPC (2 << 5)
2255 #define PIPE_12BPC (3 << 5)
2257 #define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC)
2258 #define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF)
2259 #define PIPEDSL(pipe) _PIPE(pipe, PIPEADSL, PIPEBDSL)
2260 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, PIPEAFRAMEPIXEL, PIPEBFRAMEPIXEL)
2262 #define DSPARB 0x70030
2263 #define DSPARB_CSTART_MASK (0x7f << 7)
2264 #define DSPARB_CSTART_SHIFT 7
2265 #define DSPARB_BSTART_MASK (0x7f)
2266 #define DSPARB_BSTART_SHIFT 0
2267 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2268 #define DSPARB_AEND_SHIFT 0
2270 #define DSPFW1 0x70034
2271 #define DSPFW_SR_SHIFT 23
2272 #define DSPFW_SR_MASK (0x1ff<<23)
2273 #define DSPFW_CURSORB_SHIFT 16
2274 #define DSPFW_CURSORB_MASK (0x3f<<16)
2275 #define DSPFW_PLANEB_SHIFT 8
2276 #define DSPFW_PLANEB_MASK (0x7f<<8)
2277 #define DSPFW_PLANEA_MASK (0x7f)
2278 #define DSPFW2 0x70038
2279 #define DSPFW_CURSORA_MASK 0x00003f00
2280 #define DSPFW_CURSORA_SHIFT 8
2281 #define DSPFW_PLANEC_MASK (0x7f)
2282 #define DSPFW3 0x7003c
2283 #define DSPFW_HPLL_SR_EN (1<<31)
2284 #define DSPFW_CURSOR_SR_SHIFT 24
2285 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2286 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2287 #define DSPFW_HPLL_CURSOR_SHIFT 16
2288 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2289 #define DSPFW_HPLL_SR_MASK (0x1ff)
2291 /* FIFO watermark sizes etc */
2292 #define G4X_FIFO_LINE_SIZE 64
2293 #define I915_FIFO_LINE_SIZE 64
2294 #define I830_FIFO_LINE_SIZE 32
2296 #define G4X_FIFO_SIZE 127
2297 #define I965_FIFO_SIZE 512
2298 #define I945_FIFO_SIZE 127
2299 #define I915_FIFO_SIZE 95
2300 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2301 #define I830_FIFO_SIZE 95
2303 #define G4X_MAX_WM 0x3f
2304 #define I915_MAX_WM 0x3f
2306 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2307 #define PINEVIEW_FIFO_LINE_SIZE 64
2308 #define PINEVIEW_MAX_WM 0x1ff
2309 #define PINEVIEW_DFT_WM 0x3f
2310 #define PINEVIEW_DFT_HPLLOFF_WM 0
2311 #define PINEVIEW_GUARD_WM 10
2312 #define PINEVIEW_CURSOR_FIFO 64
2313 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2314 #define PINEVIEW_CURSOR_DFT_WM 0
2315 #define PINEVIEW_CURSOR_GUARD_WM 5
2317 #define I965_CURSOR_FIFO 64
2318 #define I965_CURSOR_MAX_WM 32
2319 #define I965_CURSOR_DFT_WM 8
2321 /* define the Watermark register on Ironlake */
2322 #define WM0_PIPEA_ILK 0x45100
2323 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2324 #define WM0_PIPE_PLANE_SHIFT 16
2325 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2326 #define WM0_PIPE_SPRITE_SHIFT 8
2327 #define WM0_PIPE_CURSOR_MASK (0x1f)
2329 #define WM0_PIPEB_ILK 0x45104
2330 #define WM1_LP_ILK 0x45108
2331 #define WM1_LP_SR_EN (1<<31)
2332 #define WM1_LP_LATENCY_SHIFT 24
2333 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2334 #define WM1_LP_FBC_MASK (0xf<<20)
2335 #define WM1_LP_FBC_SHIFT 20
2336 #define WM1_LP_SR_MASK (0x1ff<<8)
2337 #define WM1_LP_SR_SHIFT 8
2338 #define WM1_LP_CURSOR_MASK (0x3f)
2339 #define WM2_LP_ILK 0x4510c
2340 #define WM2_LP_EN (1<<31)
2341 #define WM3_LP_ILK 0x45110
2342 #define WM3_LP_EN (1<<31)
2343 #define WM1S_LP_ILK 0x45120
2344 #define WM1S_LP_EN (1<<31)
2346 /* Memory latency timer register */
2347 #define MLTR_ILK 0x11222
2348 /* the unit of memory self-refresh latency time is 0.5us */
2349 #define ILK_SRLT_MASK 0x3f
2351 /* define the fifo size on Ironlake */
2352 #define ILK_DISPLAY_FIFO 128
2353 #define ILK_DISPLAY_MAXWM 64
2354 #define ILK_DISPLAY_DFTWM 8
2355 #define ILK_CURSOR_FIFO 32
2356 #define ILK_CURSOR_MAXWM 16
2357 #define ILK_CURSOR_DFTWM 8
2359 #define ILK_DISPLAY_SR_FIFO 512
2360 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2361 #define ILK_DISPLAY_DFT_SRWM 0x3f
2362 #define ILK_CURSOR_SR_FIFO 64
2363 #define ILK_CURSOR_MAX_SRWM 0x3f
2364 #define ILK_CURSOR_DFT_SRWM 8
2366 #define ILK_FIFO_LINE_SIZE 64
2368 /* define the WM info on Sandybridge */
2369 #define SNB_DISPLAY_FIFO 128
2370 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2371 #define SNB_DISPLAY_DFTWM 8
2372 #define SNB_CURSOR_FIFO 32
2373 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2374 #define SNB_CURSOR_DFTWM 8
2376 #define SNB_DISPLAY_SR_FIFO 512
2377 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2378 #define SNB_DISPLAY_DFT_SRWM 0x3f
2379 #define SNB_CURSOR_SR_FIFO 64
2380 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2381 #define SNB_CURSOR_DFT_SRWM 8
2383 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2385 #define SNB_FIFO_LINE_SIZE 64
2388 /* the address where we get all kinds of latency value */
2389 #define SSKPD 0x5d10
2390 #define SSKPD_WM_MASK 0x3f
2391 #define SSKPD_WM0_SHIFT 0
2392 #define SSKPD_WM1_SHIFT 8
2393 #define SSKPD_WM2_SHIFT 16
2394 #define SSKPD_WM3_SHIFT 24
2396 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2397 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2398 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2399 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2400 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2403 * The two pipe frame counter registers are not synchronized, so
2404 * reading a stable value is somewhat tricky. The following code
2408 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2409 * PIPE_FRAME_HIGH_SHIFT;
2410 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2411 * PIPE_FRAME_LOW_SHIFT);
2412 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2413 * PIPE_FRAME_HIGH_SHIFT);
2414 * } while (high1 != high2);
2415 * frame = (high1 << 8) | low1;
2417 #define PIPEAFRAMEHIGH 0x70040
2418 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2419 #define PIPE_FRAME_HIGH_SHIFT 0
2420 #define PIPEAFRAMEPIXEL 0x70044
2421 #define PIPE_FRAME_LOW_MASK 0xff000000
2422 #define PIPE_FRAME_LOW_SHIFT 24
2423 #define PIPE_PIXEL_MASK 0x00ffffff
2424 #define PIPE_PIXEL_SHIFT 0
2425 /* GM45+ just has to be different */
2426 #define PIPEA_FRMCOUNT_GM45 0x70040
2427 #define PIPEA_FLIPCOUNT_GM45 0x70044
2429 /* Cursor A & B regs */
2430 #define CURACNTR 0x70080
2431 /* Old style CUR*CNTR flags (desktop 8xx) */
2432 #define CURSOR_ENABLE 0x80000000
2433 #define CURSOR_GAMMA_ENABLE 0x40000000
2434 #define CURSOR_STRIDE_MASK 0x30000000
2435 #define CURSOR_FORMAT_SHIFT 24
2436 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2437 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2438 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2439 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2440 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2441 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2442 /* New style CUR*CNTR flags */
2443 #define CURSOR_MODE 0x27
2444 #define CURSOR_MODE_DISABLE 0x00
2445 #define CURSOR_MODE_64_32B_AX 0x07
2446 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2447 #define MCURSOR_PIPE_SELECT (1 << 28)
2448 #define MCURSOR_PIPE_A 0x00
2449 #define MCURSOR_PIPE_B (1 << 28)
2450 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2451 #define CURABASE 0x70084
2452 #define CURAPOS 0x70088
2453 #define CURSOR_POS_MASK 0x007FF
2454 #define CURSOR_POS_SIGN 0x8000
2455 #define CURSOR_X_SHIFT 0
2456 #define CURSOR_Y_SHIFT 16
2457 #define CURSIZE 0x700a0
2458 #define CURBCNTR 0x700c0
2459 #define CURBBASE 0x700c4
2460 #define CURBPOS 0x700c8
2462 #define CURCNTR(pipe) _PIPE(pipe, CURACNTR, CURBCNTR)
2463 #define CURBASE(pipe) _PIPE(pipe, CURABASE, CURBBASE)
2464 #define CURPOS(pipe) _PIPE(pipe, CURAPOS, CURBPOS)
2466 /* Display A control */
2467 #define DSPACNTR 0x70180
2468 #define DISPLAY_PLANE_ENABLE (1<<31)
2469 #define DISPLAY_PLANE_DISABLE 0
2470 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2471 #define DISPPLANE_GAMMA_DISABLE 0
2472 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2473 #define DISPPLANE_8BPP (0x2<<26)
2474 #define DISPPLANE_15_16BPP (0x4<<26)
2475 #define DISPPLANE_16BPP (0x5<<26)
2476 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2477 #define DISPPLANE_32BPP (0x7<<26)
2478 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2479 #define DISPPLANE_STEREO_ENABLE (1<<25)
2480 #define DISPPLANE_STEREO_DISABLE 0
2481 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
2482 #define DISPPLANE_SEL_PIPE_A 0
2483 #define DISPPLANE_SEL_PIPE_B (1<<24)
2484 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2485 #define DISPPLANE_SRC_KEY_DISABLE 0
2486 #define DISPPLANE_LINE_DOUBLE (1<<20)
2487 #define DISPPLANE_NO_LINE_DOUBLE 0
2488 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2489 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2490 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2491 #define DISPPLANE_TILED (1<<10)
2492 #define DSPAADDR 0x70184
2493 #define DSPASTRIDE 0x70188
2494 #define DSPAPOS 0x7018C /* reserved */
2495 #define DSPASIZE 0x70190
2496 #define DSPASURF 0x7019C /* 965+ only */
2497 #define DSPATILEOFF 0x701A4 /* 965+ only */
2499 #define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR)
2500 #define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR)
2501 #define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE)
2502 #define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS)
2503 #define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE)
2504 #define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF)
2505 #define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF)
2508 #define SWF00 0x71410
2509 #define SWF01 0x71414
2510 #define SWF02 0x71418
2511 #define SWF03 0x7141c
2512 #define SWF04 0x71420
2513 #define SWF05 0x71424
2514 #define SWF06 0x71428
2515 #define SWF10 0x70410
2516 #define SWF11 0x70414
2517 #define SWF14 0x71420
2518 #define SWF30 0x72414
2519 #define SWF31 0x72418
2520 #define SWF32 0x7241c
2523 #define PIPEBDSL 0x71000
2524 #define PIPEBCONF 0x71008
2525 #define PIPEBSTAT 0x71024
2526 #define PIPEBFRAMEHIGH 0x71040
2527 #define PIPEBFRAMEPIXEL 0x71044
2528 #define PIPEB_FRMCOUNT_GM45 0x71040
2529 #define PIPEB_FLIPCOUNT_GM45 0x71044
2532 /* Display B control */
2533 #define DSPBCNTR 0x71180
2534 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2535 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2536 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2537 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2538 #define DSPBADDR 0x71184
2539 #define DSPBSTRIDE 0x71188
2540 #define DSPBPOS 0x7118C
2541 #define DSPBSIZE 0x71190
2542 #define DSPBSURF 0x7119C
2543 #define DSPBTILEOFF 0x711A4
2546 #define VGACNTRL 0x71400
2547 # define VGA_DISP_DISABLE (1 << 31)
2548 # define VGA_2X_MODE (1 << 30)
2549 # define VGA_PIPE_B_SELECT (1 << 29)
2553 #define CPU_VGACNTRL 0x41000
2555 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2556 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2557 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2558 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2559 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2560 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2561 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2562 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2563 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2565 /* refresh rate hardware control */
2566 #define RR_HW_CTL 0x45300
2567 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2568 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2570 #define FDI_PLL_BIOS_0 0x46000
2571 #define FDI_PLL_FB_CLOCK_MASK 0xff
2572 #define FDI_PLL_BIOS_1 0x46004
2573 #define FDI_PLL_BIOS_2 0x46008
2574 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2575 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2576 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2578 #define PCH_DSPCLK_GATE_D 0x42020
2579 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2580 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2582 #define PCH_3DCGDIS0 0x46020
2583 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2584 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2586 #define PCH_3DCGDIS1 0x46024
2587 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2589 #define FDI_PLL_FREQ_CTL 0x46030
2590 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2591 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2592 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2595 #define PIPEA_DATA_M1 0x60030
2596 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2597 #define TU_SIZE_MASK 0x7e000000
2598 #define PIPE_DATA_M1_OFFSET 0
2599 #define PIPEA_DATA_N1 0x60034
2600 #define PIPE_DATA_N1_OFFSET 0
2602 #define PIPEA_DATA_M2 0x60038
2603 #define PIPE_DATA_M2_OFFSET 0
2604 #define PIPEA_DATA_N2 0x6003c
2605 #define PIPE_DATA_N2_OFFSET 0
2607 #define PIPEA_LINK_M1 0x60040
2608 #define PIPE_LINK_M1_OFFSET 0
2609 #define PIPEA_LINK_N1 0x60044
2610 #define PIPE_LINK_N1_OFFSET 0
2612 #define PIPEA_LINK_M2 0x60048
2613 #define PIPE_LINK_M2_OFFSET 0
2614 #define PIPEA_LINK_N2 0x6004c
2615 #define PIPE_LINK_N2_OFFSET 0
2617 /* PIPEB timing regs are same start from 0x61000 */
2619 #define PIPEB_DATA_M1 0x61030
2620 #define PIPEB_DATA_N1 0x61034
2622 #define PIPEB_DATA_M2 0x61038
2623 #define PIPEB_DATA_N2 0x6103c
2625 #define PIPEB_LINK_M1 0x61040
2626 #define PIPEB_LINK_N1 0x61044
2628 #define PIPEB_LINK_M2 0x61048
2629 #define PIPEB_LINK_N2 0x6104c
2631 #define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1)
2632 #define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1)
2633 #define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2)
2634 #define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2)
2635 #define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1)
2636 #define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1)
2637 #define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2)
2638 #define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2)
2640 /* CPU panel fitter */
2641 #define PFA_CTL_1 0x68080
2642 #define PFB_CTL_1 0x68880
2643 #define PF_ENABLE (1<<31)
2644 #define PF_FILTER_MASK (3<<23)
2645 #define PF_FILTER_PROGRAMMED (0<<23)
2646 #define PF_FILTER_MED_3x3 (1<<23)
2647 #define PF_FILTER_EDGE_ENHANCE (2<<23)
2648 #define PF_FILTER_EDGE_SOFTEN (3<<23)
2649 #define PFA_WIN_SZ 0x68074
2650 #define PFB_WIN_SZ 0x68874
2651 #define PFA_WIN_POS 0x68070
2652 #define PFB_WIN_POS 0x68870
2654 /* legacy palette */
2655 #define LGC_PALETTE_A 0x4a000
2656 #define LGC_PALETTE_B 0x4a800
2659 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2660 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2661 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2662 #define DE_PLANEB_FLIP_DONE (1 << 27)
2663 #define DE_PLANEA_FLIP_DONE (1 << 26)
2664 #define DE_PCU_EVENT (1 << 25)
2665 #define DE_GTT_FAULT (1 << 24)
2666 #define DE_POISON (1 << 23)
2667 #define DE_PERFORM_COUNTER (1 << 22)
2668 #define DE_PCH_EVENT (1 << 21)
2669 #define DE_AUX_CHANNEL_A (1 << 20)
2670 #define DE_DP_A_HOTPLUG (1 << 19)
2671 #define DE_GSE (1 << 18)
2672 #define DE_PIPEB_VBLANK (1 << 15)
2673 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2674 #define DE_PIPEB_ODD_FIELD (1 << 13)
2675 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2676 #define DE_PIPEB_VSYNC (1 << 11)
2677 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2678 #define DE_PIPEA_VBLANK (1 << 7)
2679 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2680 #define DE_PIPEA_ODD_FIELD (1 << 5)
2681 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2682 #define DE_PIPEA_VSYNC (1 << 3)
2683 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2685 #define DEISR 0x44000
2686 #define DEIMR 0x44004
2687 #define DEIIR 0x44008
2688 #define DEIER 0x4400c
2691 #define GT_PIPE_NOTIFY (1 << 4)
2692 #define GT_SYNC_STATUS (1 << 2)
2693 #define GT_USER_INTERRUPT (1 << 0)
2694 #define GT_BSD_USER_INTERRUPT (1 << 5)
2695 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2696 #define GT_BLT_USER_INTERRUPT (1 << 22)
2698 #define GTISR 0x44010
2699 #define GTIMR 0x44014
2700 #define GTIIR 0x44018
2701 #define GTIER 0x4401c
2703 #define ILK_DISPLAY_CHICKEN2 0x42004
2704 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
2705 #define ILK_ELPIN_409_SELECT (1 << 25)
2706 #define ILK_DPARB_GATE (1<<22)
2707 #define ILK_VSDPFD_FULL (1<<21)
2708 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2709 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2710 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2711 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2712 #define ILK_HDCP_DISABLE (1<<25)
2713 #define ILK_eDP_A_DISABLE (1<<24)
2714 #define ILK_DESKTOP (1<<23)
2715 #define ILK_DSPCLK_GATE 0x42020
2716 #define ILK_DPARB_CLK_GATE (1<<5)
2717 #define ILK_DPFD_CLK_GATE (1<<7)
2719 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2720 #define ILK_CLK_FBC (1<<7)
2721 #define ILK_DPFC_DIS1 (1<<8)
2722 #define ILK_DPFC_DIS2 (1<<9)
2724 #define DISP_ARB_CTL 0x45000
2725 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2726 #define DISP_FBC_WM_DIS (1<<15)
2730 /* south display engine interrupt */
2731 #define SDE_CRT_HOTPLUG (1 << 11)
2732 #define SDE_PORTD_HOTPLUG (1 << 10)
2733 #define SDE_PORTC_HOTPLUG (1 << 9)
2734 #define SDE_PORTB_HOTPLUG (1 << 8)
2735 #define SDE_SDVOB_HOTPLUG (1 << 6)
2736 #define SDE_HOTPLUG_MASK (0xf << 8)
2738 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
2739 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2740 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2741 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2742 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2743 SDE_PORTD_HOTPLUG_CPT | \
2744 SDE_PORTC_HOTPLUG_CPT | \
2745 SDE_PORTB_HOTPLUG_CPT)
2747 #define SDEISR 0xc4000
2748 #define SDEIMR 0xc4004
2749 #define SDEIIR 0xc4008
2750 #define SDEIER 0xc400c
2752 /* digital port hotplug */
2753 #define PCH_PORT_HOTPLUG 0xc4030
2754 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2755 #define PORTD_PULSE_DURATION_2ms (0)
2756 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2757 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2758 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2759 #define PORTD_HOTPLUG_NO_DETECT (0)
2760 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2761 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2762 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2763 #define PORTC_PULSE_DURATION_2ms (0)
2764 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2765 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2766 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2767 #define PORTC_HOTPLUG_NO_DETECT (0)
2768 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2769 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2770 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2771 #define PORTB_PULSE_DURATION_2ms (0)
2772 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2773 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2774 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2775 #define PORTB_HOTPLUG_NO_DETECT (0)
2776 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2777 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2779 #define PCH_GPIOA 0xc5010
2780 #define PCH_GPIOB 0xc5014
2781 #define PCH_GPIOC 0xc5018
2782 #define PCH_GPIOD 0xc501c
2783 #define PCH_GPIOE 0xc5020
2784 #define PCH_GPIOF 0xc5024
2786 #define PCH_GMBUS0 0xc5100
2787 #define PCH_GMBUS1 0xc5104
2788 #define PCH_GMBUS2 0xc5108
2789 #define PCH_GMBUS3 0xc510c
2790 #define PCH_GMBUS4 0xc5110
2791 #define PCH_GMBUS5 0xc5120
2793 #define PCH_DPLL_A 0xc6014
2794 #define PCH_DPLL_B 0xc6018
2795 #define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B)
2797 #define PCH_FPA0 0xc6040
2798 #define FP_CB_TUNE (0x3<<22)
2799 #define PCH_FPA1 0xc6044
2800 #define PCH_FPB0 0xc6048
2801 #define PCH_FPB1 0xc604c
2802 #define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0)
2803 #define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1)
2805 #define PCH_DPLL_TEST 0xc606c
2807 #define PCH_DREF_CONTROL 0xC6200
2808 #define DREF_CONTROL_MASK 0x7fc3
2809 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2810 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2811 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2812 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2813 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2814 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2815 #define DREF_SSC_SOURCE_MASK (3<<11)
2816 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2817 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2818 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2819 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2820 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2821 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2822 #define DREF_SSC4_DOWNSPREAD (0<<6)
2823 #define DREF_SSC4_CENTERSPREAD (1<<6)
2824 #define DREF_SSC1_DISABLE (0<<1)
2825 #define DREF_SSC1_ENABLE (1<<1)
2826 #define DREF_SSC4_DISABLE (0)
2827 #define DREF_SSC4_ENABLE (1)
2829 #define PCH_RAWCLK_FREQ 0xc6204
2830 #define FDL_TP1_TIMER_SHIFT 12
2831 #define FDL_TP1_TIMER_MASK (3<<12)
2832 #define FDL_TP2_TIMER_SHIFT 10
2833 #define FDL_TP2_TIMER_MASK (3<<10)
2834 #define RAWCLK_FREQ_MASK 0x3ff
2836 #define PCH_DPLL_TMR_CFG 0xc6208
2838 #define PCH_SSC4_PARMS 0xc6210
2839 #define PCH_SSC4_AUX_PARMS 0xc6214
2841 #define PCH_DPLL_SEL 0xc7000
2842 #define TRANSA_DPLL_ENABLE (1<<3)
2843 #define TRANSA_DPLLB_SEL (1<<0)
2844 #define TRANSA_DPLLA_SEL 0
2845 #define TRANSB_DPLL_ENABLE (1<<7)
2846 #define TRANSB_DPLLB_SEL (1<<4)
2847 #define TRANSB_DPLLA_SEL (0)
2848 #define TRANSC_DPLL_ENABLE (1<<11)
2849 #define TRANSC_DPLLB_SEL (1<<8)
2850 #define TRANSC_DPLLA_SEL (0)
2854 #define TRANS_HTOTAL_A 0xe0000
2855 #define TRANS_HTOTAL_SHIFT 16
2856 #define TRANS_HACTIVE_SHIFT 0
2857 #define TRANS_HBLANK_A 0xe0004
2858 #define TRANS_HBLANK_END_SHIFT 16
2859 #define TRANS_HBLANK_START_SHIFT 0
2860 #define TRANS_HSYNC_A 0xe0008
2861 #define TRANS_HSYNC_END_SHIFT 16
2862 #define TRANS_HSYNC_START_SHIFT 0
2863 #define TRANS_VTOTAL_A 0xe000c
2864 #define TRANS_VTOTAL_SHIFT 16
2865 #define TRANS_VACTIVE_SHIFT 0
2866 #define TRANS_VBLANK_A 0xe0010
2867 #define TRANS_VBLANK_END_SHIFT 16
2868 #define TRANS_VBLANK_START_SHIFT 0
2869 #define TRANS_VSYNC_A 0xe0014
2870 #define TRANS_VSYNC_END_SHIFT 16
2871 #define TRANS_VSYNC_START_SHIFT 0
2873 #define TRANSA_DATA_M1 0xe0030
2874 #define TRANSA_DATA_N1 0xe0034
2875 #define TRANSA_DATA_M2 0xe0038
2876 #define TRANSA_DATA_N2 0xe003c
2877 #define TRANSA_DP_LINK_M1 0xe0040
2878 #define TRANSA_DP_LINK_N1 0xe0044
2879 #define TRANSA_DP_LINK_M2 0xe0048
2880 #define TRANSA_DP_LINK_N2 0xe004c
2882 #define TRANS_HTOTAL_B 0xe1000
2883 #define TRANS_HBLANK_B 0xe1004
2884 #define TRANS_HSYNC_B 0xe1008
2885 #define TRANS_VTOTAL_B 0xe100c
2886 #define TRANS_VBLANK_B 0xe1010
2887 #define TRANS_VSYNC_B 0xe1014
2889 #define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B)
2890 #define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B)
2891 #define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B)
2892 #define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B)
2893 #define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B)
2894 #define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B)
2896 #define TRANSB_DATA_M1 0xe1030
2897 #define TRANSB_DATA_N1 0xe1034
2898 #define TRANSB_DATA_M2 0xe1038
2899 #define TRANSB_DATA_N2 0xe103c
2900 #define TRANSB_DP_LINK_M1 0xe1040
2901 #define TRANSB_DP_LINK_N1 0xe1044
2902 #define TRANSB_DP_LINK_M2 0xe1048
2903 #define TRANSB_DP_LINK_N2 0xe104c
2905 #define TRANSACONF 0xf0008
2906 #define TRANSBCONF 0xf1008
2907 #define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF)
2908 #define TRANS_DISABLE (0<<31)
2909 #define TRANS_ENABLE (1<<31)
2910 #define TRANS_STATE_MASK (1<<30)
2911 #define TRANS_STATE_DISABLE (0<<30)
2912 #define TRANS_STATE_ENABLE (1<<30)
2913 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2914 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2915 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2916 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2917 #define TRANS_DP_AUDIO_ONLY (1<<26)
2918 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2919 #define TRANS_PROGRESSIVE (0<<21)
2920 #define TRANS_8BPC (0<<5)
2921 #define TRANS_10BPC (1<<5)
2922 #define TRANS_6BPC (2<<5)
2923 #define TRANS_12BPC (3<<5)
2925 #define FDI_RXA_CHICKEN 0xc200c
2926 #define FDI_RXB_CHICKEN 0xc2010
2927 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2928 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)
2930 #define SOUTH_DSPCLK_GATE_D 0xc2020
2931 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
2934 #define FDI_TXA_CTL 0x60100
2935 #define FDI_TXB_CTL 0x61100
2936 #define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL)
2937 #define FDI_TX_DISABLE (0<<31)
2938 #define FDI_TX_ENABLE (1<<31)
2939 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2940 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2941 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2942 #define FDI_LINK_TRAIN_NONE (3<<28)
2943 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2944 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2945 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2946 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2947 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2948 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2949 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2950 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2951 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
2952 SNB has different settings. */
2953 /* SNB A-stepping */
2954 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
2955 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
2956 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2957 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2958 /* SNB B-stepping */
2959 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
2960 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
2961 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
2962 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
2963 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
2964 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2965 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2966 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2967 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2968 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2969 /* Ironlake: hardwired to 1 */
2970 #define FDI_TX_PLL_ENABLE (1<<14)
2971 /* both Tx and Rx */
2972 #define FDI_SCRAMBLING_ENABLE (0<<7)
2973 #define FDI_SCRAMBLING_DISABLE (1<<7)
2975 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2976 #define FDI_RXA_CTL 0xf000c
2977 #define FDI_RXB_CTL 0xf100c
2978 #define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL)
2979 #define FDI_RX_ENABLE (1<<31)
2980 /* train, dp width same as FDI_TX */
2981 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2982 #define FDI_8BPC (0<<16)
2983 #define FDI_10BPC (1<<16)
2984 #define FDI_6BPC (2<<16)
2985 #define FDI_12BPC (3<<16)
2986 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2987 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2988 #define FDI_RX_PLL_ENABLE (1<<13)
2989 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2990 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2991 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2992 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2993 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2994 #define FDI_PCDCLK (1<<4)
2996 #define FDI_AUTO_TRAINING (1<<10)
2997 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
2998 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
2999 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3000 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3001 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3003 #define FDI_RXA_MISC 0xf0010
3004 #define FDI_RXB_MISC 0xf1010
3005 #define FDI_RXA_TUSIZE1 0xf0030
3006 #define FDI_RXA_TUSIZE2 0xf0038
3007 #define FDI_RXB_TUSIZE1 0xf1030
3008 #define FDI_RXB_TUSIZE2 0xf1038
3009 #define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC)
3010 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1)
3011 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2)
3013 /* FDI_RX interrupt register format */
3014 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3015 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3016 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3017 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3018 #define FDI_RX_FS_CODE_ERR (1<<6)
3019 #define FDI_RX_FE_CODE_ERR (1<<5)
3020 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3021 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3022 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3023 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3024 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3026 #define FDI_RXA_IIR 0xf0014
3027 #define FDI_RXA_IMR 0xf0018
3028 #define FDI_RXB_IIR 0xf1014
3029 #define FDI_RXB_IMR 0xf1018
3030 #define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR)
3031 #define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR)
3033 #define FDI_PLL_CTL_1 0xfe000
3034 #define FDI_PLL_CTL_2 0xfe004
3037 #define PCH_ADPA 0xe1100
3038 #define ADPA_TRANS_SELECT_MASK (1<<30)
3039 #define ADPA_TRANS_A_SELECT 0
3040 #define ADPA_TRANS_B_SELECT (1<<30)
3041 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3042 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3043 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3044 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3045 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3046 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3047 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3048 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3049 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3050 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3051 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3052 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3053 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3054 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3055 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3056 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3057 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3058 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3059 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3062 #define HDMIB 0xe1140
3063 #define PORT_ENABLE (1 << 31)
3064 #define TRANSCODER_A (0)
3065 #define TRANSCODER_B (1 << 30)
3066 #define COLOR_FORMAT_8bpc (0)
3067 #define COLOR_FORMAT_12bpc (3 << 26)
3068 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
3069 #define SDVO_ENCODING (0)
3070 #define TMDS_ENCODING (2 << 10)
3071 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3073 #define HDMI_MODE_SELECT (1 << 9)
3074 #define DVI_MODE_SELECT (0)
3075 #define SDVOB_BORDER_ENABLE (1 << 7)
3076 #define AUDIO_ENABLE (1 << 6)
3077 #define VSYNC_ACTIVE_HIGH (1 << 4)
3078 #define HSYNC_ACTIVE_HIGH (1 << 3)
3079 #define PORT_DETECTED (1 << 2)
3081 /* PCH SDVOB multiplex with HDMIB */
3082 #define PCH_SDVOB HDMIB
3084 #define HDMIC 0xe1150
3085 #define HDMID 0xe1160
3087 #define PCH_LVDS 0xe1180
3088 #define LVDS_DETECTED (1 << 1)
3090 #define BLC_PWM_CPU_CTL2 0x48250
3091 #define PWM_ENABLE (1 << 31)
3092 #define PWM_PIPE_A (0 << 29)
3093 #define PWM_PIPE_B (1 << 29)
3094 #define BLC_PWM_CPU_CTL 0x48254
3096 #define BLC_PWM_PCH_CTL1 0xc8250
3097 #define PWM_PCH_ENABLE (1 << 31)
3098 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3099 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3100 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3101 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3103 #define BLC_PWM_PCH_CTL2 0xc8254
3105 #define PCH_PP_STATUS 0xc7200
3106 #define PCH_PP_CONTROL 0xc7204
3107 #define PANEL_UNLOCK_REGS (0xabcd << 16)
3108 #define EDP_FORCE_VDD (1 << 3)
3109 #define EDP_BLC_ENABLE (1 << 2)
3110 #define PANEL_POWER_RESET (1 << 1)
3111 #define PANEL_POWER_OFF (0 << 0)
3112 #define PANEL_POWER_ON (1 << 0)
3113 #define PCH_PP_ON_DELAYS 0xc7208
3114 #define EDP_PANEL (1 << 30)
3115 #define PCH_PP_OFF_DELAYS 0xc720c
3116 #define PCH_PP_DIVISOR 0xc7210
3118 #define PCH_DP_B 0xe4100
3119 #define PCH_DPB_AUX_CH_CTL 0xe4110
3120 #define PCH_DPB_AUX_CH_DATA1 0xe4114
3121 #define PCH_DPB_AUX_CH_DATA2 0xe4118
3122 #define PCH_DPB_AUX_CH_DATA3 0xe411c
3123 #define PCH_DPB_AUX_CH_DATA4 0xe4120
3124 #define PCH_DPB_AUX_CH_DATA5 0xe4124
3126 #define PCH_DP_C 0xe4200
3127 #define PCH_DPC_AUX_CH_CTL 0xe4210
3128 #define PCH_DPC_AUX_CH_DATA1 0xe4214
3129 #define PCH_DPC_AUX_CH_DATA2 0xe4218
3130 #define PCH_DPC_AUX_CH_DATA3 0xe421c
3131 #define PCH_DPC_AUX_CH_DATA4 0xe4220
3132 #define PCH_DPC_AUX_CH_DATA5 0xe4224
3134 #define PCH_DP_D 0xe4300
3135 #define PCH_DPD_AUX_CH_CTL 0xe4310
3136 #define PCH_DPD_AUX_CH_DATA1 0xe4314
3137 #define PCH_DPD_AUX_CH_DATA2 0xe4318
3138 #define PCH_DPD_AUX_CH_DATA3 0xe431c
3139 #define PCH_DPD_AUX_CH_DATA4 0xe4320
3140 #define PCH_DPD_AUX_CH_DATA5 0xe4324
3143 #define PORT_TRANS_A_SEL_CPT 0
3144 #define PORT_TRANS_B_SEL_CPT (1<<29)
3145 #define PORT_TRANS_C_SEL_CPT (2<<29)
3146 #define PORT_TRANS_SEL_MASK (3<<29)
3148 #define TRANS_DP_CTL_A 0xe0300
3149 #define TRANS_DP_CTL_B 0xe1300
3150 #define TRANS_DP_CTL_C 0xe2300
3151 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3152 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
3153 #define TRANS_DP_PORT_SEL_B (0<<29)
3154 #define TRANS_DP_PORT_SEL_C (1<<29)
3155 #define TRANS_DP_PORT_SEL_D (2<<29)
3156 #define TRANS_DP_PORT_SEL_MASK (3<<29)
3157 #define TRANS_DP_AUDIO_ONLY (1<<26)
3158 #define TRANS_DP_ENH_FRAMING (1<<18)
3159 #define TRANS_DP_8BPC (0<<9)
3160 #define TRANS_DP_10BPC (1<<9)
3161 #define TRANS_DP_6BPC (2<<9)
3162 #define TRANS_DP_12BPC (3<<9)
3163 #define TRANS_DP_BPC_MASK (3<<9)
3164 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3165 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
3166 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3167 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
3168 #define TRANS_DP_SYNC_MASK (3<<3)
3170 /* SNB eDP training params */
3171 /* SNB A-stepping */
3172 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3173 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3174 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3175 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3176 /* SNB B-stepping */
3177 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3178 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3179 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3180 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3181 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3182 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3184 #define FORCEWAKE 0xA18C
3185 #define FORCEWAKE_ACK 0x130090
3187 #define GEN6_RPNSWREQ 0xA008
3188 #define GEN6_TURBO_DISABLE (1<<31)
3189 #define GEN6_FREQUENCY(x) ((x)<<25)
3190 #define GEN6_OFFSET(x) ((x)<<19)
3191 #define GEN6_AGGRESSIVE_TURBO (0<<15)
3192 #define GEN6_RC_VIDEO_FREQ 0xA00C
3193 #define GEN6_RC_CONTROL 0xA090
3194 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3195 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3196 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3197 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3198 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3199 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3200 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
3201 #define GEN6_RP_DOWN_TIMEOUT 0xA010
3202 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
3203 #define GEN6_RPSTAT1 0xA01C
3204 #define GEN6_RP_CONTROL 0xA024
3205 #define GEN6_RP_MEDIA_TURBO (1<<11)
3206 #define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3207 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
3208 #define GEN6_RP_ENABLE (1<<7)
3209 #define GEN6_RP_UP_BUSY_MAX (0x2<<3)
3210 #define GEN6_RP_DOWN_BUSY_MIN (0x2<<0)
3211 #define GEN6_RP_UP_THRESHOLD 0xA02C
3212 #define GEN6_RP_DOWN_THRESHOLD 0xA030
3213 #define GEN6_RP_UP_EI 0xA068
3214 #define GEN6_RP_DOWN_EI 0xA06C
3215 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
3216 #define GEN6_RC_STATE 0xA094
3217 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3218 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3219 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3220 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3221 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3222 #define GEN6_RC_SLEEP 0xA0B0
3223 #define GEN6_RC1e_THRESHOLD 0xA0B4
3224 #define GEN6_RC6_THRESHOLD 0xA0B8
3225 #define GEN6_RC6p_THRESHOLD 0xA0BC
3226 #define GEN6_RC6pp_THRESHOLD 0xA0C0
3227 #define GEN6_PMINTRMSK 0xA168
3229 #define GEN6_PMISR 0x44020
3230 #define GEN6_PMIMR 0x44024
3231 #define GEN6_PMIIR 0x44028
3232 #define GEN6_PMIER 0x4402C
3233 #define GEN6_PM_MBOX_EVENT (1<<25)
3234 #define GEN6_PM_THERMAL_EVENT (1<<24)
3235 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3236 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3237 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3238 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3239 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3241 #define GEN6_PCODE_MAILBOX 0x138124
3242 #define GEN6_PCODE_READY (1<<31)
3243 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x9
3244 #define GEN6_PCODE_DATA 0x138128
3246 #endif /* _I915_REG_H_ */
projects / linux-flexiantxendom0-natty.git / blob