drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj_priv->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj_priv->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj_priv->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj_priv->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj_priv->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj_priv->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj_priv;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj_priv = to_intel_bo(intel_fb->obj);
1388
1389         if (intel_fb->obj->size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj_priv->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_gem_object *obj,
1437                            bool pipelined)
1438 {
1439         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440         u32 alignment;
1441         int ret;
1442
1443         switch (obj_priv->tiling_mode) {
1444         case I915_TILING_NONE:
1445                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446                         alignment = 128 * 1024;
1447                 else if (INTEL_INFO(dev)->gen >= 4)
1448                         alignment = 4 * 1024;
1449                 else
1450                         alignment = 64 * 1024;
1451                 break;
1452         case I915_TILING_X:
1453                 /* pin() will align the object as required by fence */
1454                 alignment = 0;
1455                 break;
1456         case I915_TILING_Y:
1457                 /* FIXME: Is this true? */
1458                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459                 return -EINVAL;
1460         default:
1461                 BUG();
1462         }
1463
1464         ret = i915_gem_object_pin(obj, alignment, true);
1465         if (ret)
1466                 return ret;
1467
1468         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469         if (ret)
1470                 goto err_unpin;
1471
1472         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473          * fence, whereas 965+ only requires a fence if using
1474          * framebuffer compression.  For simplicity, we always install
1475          * a fence as the cost is not that onerous.
1476          */
1477         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1478                 ret = i915_gem_object_get_fence_reg(obj, false);
1479                 if (ret)
1480                         goto err_unpin;
1481         }
1482
1483         return 0;
1484
1485 err_unpin:
1486         i915_gem_object_unpin(obj);
1487         return ret;
1488 }
1489
1490 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1491 static int
1492 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1493                            int x, int y, enum mode_set_atomic state)
1494 {
1495         struct drm_device *dev = crtc->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1498         struct intel_framebuffer *intel_fb;
1499         struct drm_i915_gem_object *obj_priv;
1500         struct drm_gem_object *obj;
1501         int plane = intel_crtc->plane;
1502         unsigned long Start, Offset;
1503         u32 dspcntr;
1504         u32 reg;
1505
1506         switch (plane) {
1507         case 0:
1508         case 1:
1509                 break;
1510         default:
1511                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1512                 return -EINVAL;
1513         }
1514
1515         intel_fb = to_intel_framebuffer(fb);
1516         obj = intel_fb->obj;
1517         obj_priv = to_intel_bo(obj);
1518
1519         reg = DSPCNTR(plane);
1520         dspcntr = I915_READ(reg);
1521         /* Mask out pixel format bits in case we change it */
1522         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1523         switch (fb->bits_per_pixel) {
1524         case 8:
1525                 dspcntr |= DISPPLANE_8BPP;
1526                 break;
1527         case 16:
1528                 if (fb->depth == 15)
1529                         dspcntr |= DISPPLANE_15_16BPP;
1530                 else
1531                         dspcntr |= DISPPLANE_16BPP;
1532                 break;
1533         case 24:
1534         case 32:
1535                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1536                 break;
1537         default:
1538                 DRM_ERROR("Unknown color depth\n");
1539                 return -EINVAL;
1540         }
1541         if (INTEL_INFO(dev)->gen >= 4) {
1542                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1543                         dspcntr |= DISPPLANE_TILED;
1544                 else
1545                         dspcntr &= ~DISPPLANE_TILED;
1546         }
1547
1548         if (HAS_PCH_SPLIT(dev))
1549                 /* must disable */
1550                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1551
1552         I915_WRITE(reg, dspcntr);
1553
1554         Start = obj_priv->gtt_offset;
1555         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1556
1557         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1558                       Start, Offset, x, y, fb->pitch);
1559         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1560         if (INTEL_INFO(dev)->gen >= 4) {
1561                 I915_WRITE(DSPSURF(plane), Start);
1562                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1563                 I915_WRITE(DSPADDR(plane), Offset);
1564         } else
1565                 I915_WRITE(DSPADDR(plane), Start + Offset);
1566         POSTING_READ(reg);
1567
1568         intel_update_fbc(dev);
1569         intel_increase_pllclock(crtc);
1570
1571         return 0;
1572 }
1573
1574 static int
1575 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1576                     struct drm_framebuffer *old_fb)
1577 {
1578         struct drm_device *dev = crtc->dev;
1579         struct drm_i915_master_private *master_priv;
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         int ret;
1582
1583         /* no fb bound */
1584         if (!crtc->fb) {
1585                 DRM_DEBUG_KMS("No FB bound\n");
1586                 return 0;
1587         }
1588
1589         switch (intel_crtc->plane) {
1590         case 0:
1591         case 1:
1592                 break;
1593         default:
1594                 return -EINVAL;
1595         }
1596
1597         mutex_lock(&dev->struct_mutex);
1598         ret = intel_pin_and_fence_fb_obj(dev,
1599                                          to_intel_framebuffer(crtc->fb)->obj,
1600                                          false);
1601         if (ret != 0) {
1602                 mutex_unlock(&dev->struct_mutex);
1603                 return ret;
1604         }
1605
1606         if (old_fb) {
1607                 struct drm_i915_private *dev_priv = dev->dev_private;
1608                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1609                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1610
1611                 wait_event(dev_priv->pending_flip_queue,
1612                            atomic_read(&obj_priv->pending_flip) == 0);
1613         }
1614
1615         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1616                                          LEAVE_ATOMIC_MODE_SET);
1617         if (ret) {
1618                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1619                 mutex_unlock(&dev->struct_mutex);
1620                 return ret;
1621         }
1622
1623         if (old_fb)
1624                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1625
1626         mutex_unlock(&dev->struct_mutex);
1627
1628         if (!dev->primary->master)
1629                 return 0;
1630
1631         master_priv = dev->primary->master->driver_priv;
1632         if (!master_priv->sarea_priv)
1633                 return 0;
1634
1635         if (intel_crtc->pipe) {
1636                 master_priv->sarea_priv->pipeB_x = x;
1637                 master_priv->sarea_priv->pipeB_y = y;
1638         } else {
1639                 master_priv->sarea_priv->pipeA_x = x;
1640                 master_priv->sarea_priv->pipeA_y = y;
1641         }
1642
1643         return 0;
1644 }
1645
1646 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1647 {
1648         struct drm_device *dev = crtc->dev;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         u32 dpa_ctl;
1651
1652         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1653         dpa_ctl = I915_READ(DP_A);
1654         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1655
1656         if (clock < 200000) {
1657                 u32 temp;
1658                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1659                 /* workaround for 160Mhz:
1660                    1) program 0x4600c bits 15:0 = 0x8124
1661                    2) program 0x46010 bit 0 = 1
1662                    3) program 0x46034 bit 24 = 1
1663                    4) program 0x64000 bit 14 = 1
1664                    */
1665                 temp = I915_READ(0x4600c);
1666                 temp &= 0xffff0000;
1667                 I915_WRITE(0x4600c, temp | 0x8124);
1668
1669                 temp = I915_READ(0x46010);
1670                 I915_WRITE(0x46010, temp | 1);
1671
1672                 temp = I915_READ(0x46034);
1673                 I915_WRITE(0x46034, temp | (1 << 24));
1674         } else {
1675                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1676         }
1677         I915_WRITE(DP_A, dpa_ctl);
1678
1679         POSTING_READ(DP_A);
1680         udelay(500);
1681 }
1682
1683 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1684 {
1685         struct drm_device *dev = crtc->dev;
1686         struct drm_i915_private *dev_priv = dev->dev_private;
1687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1688         int pipe = intel_crtc->pipe;
1689         u32 reg, temp;
1690
1691         /* enable normal train */
1692         reg = FDI_TX_CTL(pipe);
1693         temp = I915_READ(reg);
1694         temp &= ~FDI_LINK_TRAIN_NONE;
1695         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1696         I915_WRITE(reg, temp);
1697
1698         reg = FDI_RX_CTL(pipe);
1699         temp = I915_READ(reg);
1700         if (HAS_PCH_CPT(dev)) {
1701                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1702                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1703         } else {
1704                 temp &= ~FDI_LINK_TRAIN_NONE;
1705                 temp |= FDI_LINK_TRAIN_NONE;
1706         }
1707         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1708
1709         /* wait one idle pattern time */
1710         POSTING_READ(reg);
1711         udelay(1000);
1712 }
1713
1714 /* The FDI link training functions for ILK/Ibexpeak. */
1715 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1716 {
1717         struct drm_device *dev = crtc->dev;
1718         struct drm_i915_private *dev_priv = dev->dev_private;
1719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1720         int pipe = intel_crtc->pipe;
1721         u32 reg, temp, tries;
1722
1723         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1724            for train result */
1725         reg = FDI_RX_IMR(pipe);
1726         temp = I915_READ(reg);
1727         temp &= ~FDI_RX_SYMBOL_LOCK;
1728         temp &= ~FDI_RX_BIT_LOCK;
1729         I915_WRITE(reg, temp);
1730         I915_READ(reg);
1731         udelay(150);
1732
1733         /* enable CPU FDI TX and PCH FDI RX */
1734         reg = FDI_TX_CTL(pipe);
1735         temp = I915_READ(reg);
1736         temp &= ~(7 << 19);
1737         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1738         temp &= ~FDI_LINK_TRAIN_NONE;
1739         temp |= FDI_LINK_TRAIN_PATTERN_1;
1740         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1741
1742         reg = FDI_RX_CTL(pipe);
1743         temp = I915_READ(reg);
1744         temp &= ~FDI_LINK_TRAIN_NONE;
1745         temp |= FDI_LINK_TRAIN_PATTERN_1;
1746         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1747
1748         POSTING_READ(reg);
1749         udelay(150);
1750
1751         /* Ironlake workaround, enable clock pointer after FDI enable*/
1752         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1753
1754         reg = FDI_RX_IIR(pipe);
1755         for (tries = 0; tries < 5; tries++) {
1756                 temp = I915_READ(reg);
1757                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1758
1759                 if ((temp & FDI_RX_BIT_LOCK)) {
1760                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1761                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1762                         break;
1763                 }
1764         }
1765         if (tries == 5)
1766                 DRM_ERROR("FDI train 1 fail!\n");
1767
1768         /* Train 2 */
1769         reg = FDI_TX_CTL(pipe);
1770         temp = I915_READ(reg);
1771         temp &= ~FDI_LINK_TRAIN_NONE;
1772         temp |= FDI_LINK_TRAIN_PATTERN_2;
1773         I915_WRITE(reg, temp);
1774
1775         reg = FDI_RX_CTL(pipe);
1776         temp = I915_READ(reg);
1777         temp &= ~FDI_LINK_TRAIN_NONE;
1778         temp |= FDI_LINK_TRAIN_PATTERN_2;
1779         I915_WRITE(reg, temp);
1780
1781         POSTING_READ(reg);
1782         udelay(150);
1783
1784         reg = FDI_RX_IIR(pipe);
1785         for (tries = 0; tries < 5; tries++) {
1786                 temp = I915_READ(reg);
1787                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1788
1789                 if (temp & FDI_RX_SYMBOL_LOCK) {
1790                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1791                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1792                         break;
1793                 }
1794         }
1795         if (tries == 5)
1796                 DRM_ERROR("FDI train 2 fail!\n");
1797
1798         DRM_DEBUG_KMS("FDI train done\n");
1799
1800 }
1801
1802 static const int const snb_b_fdi_train_param [] = {
1803         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1804         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1805         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1806         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1807 };
1808
1809 /* The FDI link training functions for SNB/Cougarpoint. */
1810 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1811 {
1812         struct drm_device *dev = crtc->dev;
1813         struct drm_i915_private *dev_priv = dev->dev_private;
1814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1815         int pipe = intel_crtc->pipe;
1816         u32 reg, temp, i;
1817
1818         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1819            for train result */
1820         reg = FDI_RX_IMR(pipe);
1821         temp = I915_READ(reg);
1822         temp &= ~FDI_RX_SYMBOL_LOCK;
1823         temp &= ~FDI_RX_BIT_LOCK;
1824         I915_WRITE(reg, temp);
1825
1826         POSTING_READ(reg);
1827         udelay(150);
1828
1829         /* enable CPU FDI TX and PCH FDI RX */
1830         reg = FDI_TX_CTL(pipe);
1831         temp = I915_READ(reg);
1832         temp &= ~(7 << 19);
1833         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1834         temp &= ~FDI_LINK_TRAIN_NONE;
1835         temp |= FDI_LINK_TRAIN_PATTERN_1;
1836         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1837         /* SNB-B */
1838         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1839         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1840
1841         reg = FDI_RX_CTL(pipe);
1842         temp = I915_READ(reg);
1843         if (HAS_PCH_CPT(dev)) {
1844                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1845                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1846         } else {
1847                 temp &= ~FDI_LINK_TRAIN_NONE;
1848                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1849         }
1850         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1851
1852         POSTING_READ(reg);
1853         udelay(150);
1854
1855         for (i = 0; i < 4; i++ ) {
1856                 reg = FDI_TX_CTL(pipe);
1857                 temp = I915_READ(reg);
1858                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1859                 temp |= snb_b_fdi_train_param[i];
1860                 I915_WRITE(reg, temp);
1861
1862                 POSTING_READ(reg);
1863                 udelay(500);
1864
1865                 reg = FDI_RX_IIR(pipe);
1866                 temp = I915_READ(reg);
1867                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1868
1869                 if (temp & FDI_RX_BIT_LOCK) {
1870                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1871                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1872                         break;
1873                 }
1874         }
1875         if (i == 4)
1876                 DRM_ERROR("FDI train 1 fail!\n");
1877
1878         /* Train 2 */
1879         reg = FDI_TX_CTL(pipe);
1880         temp = I915_READ(reg);
1881         temp &= ~FDI_LINK_TRAIN_NONE;
1882         temp |= FDI_LINK_TRAIN_PATTERN_2;
1883         if (IS_GEN6(dev)) {
1884                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1885                 /* SNB-B */
1886                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1887         }
1888         I915_WRITE(reg, temp);
1889
1890         reg = FDI_RX_CTL(pipe);
1891         temp = I915_READ(reg);
1892         if (HAS_PCH_CPT(dev)) {
1893                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1894                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1895         } else {
1896                 temp &= ~FDI_LINK_TRAIN_NONE;
1897                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1898         }
1899         I915_WRITE(reg, temp);
1900
1901         POSTING_READ(reg);
1902         udelay(150);
1903
1904         for (i = 0; i < 4; i++ ) {
1905                 reg = FDI_TX_CTL(pipe);
1906                 temp = I915_READ(reg);
1907                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1908                 temp |= snb_b_fdi_train_param[i];
1909                 I915_WRITE(reg, temp);
1910
1911                 POSTING_READ(reg);
1912                 udelay(500);
1913
1914                 reg = FDI_RX_IIR(pipe);
1915                 temp = I915_READ(reg);
1916                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1917
1918                 if (temp & FDI_RX_SYMBOL_LOCK) {
1919                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1920                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1921                         break;
1922                 }
1923         }
1924         if (i == 4)
1925                 DRM_ERROR("FDI train 2 fail!\n");
1926
1927         DRM_DEBUG_KMS("FDI train done.\n");
1928 }
1929
1930 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1931 {
1932         struct drm_device *dev = crtc->dev;
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1935         int pipe = intel_crtc->pipe;
1936         u32 reg, temp;
1937
1938         /* Write the TU size bits so error detection works */
1939         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1940                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1941
1942         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1943         reg = FDI_RX_CTL(pipe);
1944         temp = I915_READ(reg);
1945         temp &= ~((0x7 << 19) | (0x7 << 16));
1946         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1947         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1948         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1949
1950         POSTING_READ(reg);
1951         udelay(200);
1952
1953         /* Switch from Rawclk to PCDclk */
1954         temp = I915_READ(reg);
1955         I915_WRITE(reg, temp | FDI_PCDCLK);
1956
1957         POSTING_READ(reg);
1958         udelay(200);
1959
1960         /* Enable CPU FDI TX PLL, always on for Ironlake */
1961         reg = FDI_TX_CTL(pipe);
1962         temp = I915_READ(reg);
1963         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1964                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1965
1966                 POSTING_READ(reg);
1967                 udelay(100);
1968         }
1969 }
1970
1971 static void intel_flush_display_plane(struct drm_device *dev,
1972                                       int plane)
1973 {
1974         struct drm_i915_private *dev_priv = dev->dev_private;
1975         u32 reg = DSPADDR(plane);
1976         I915_WRITE(reg, I915_READ(reg));
1977 }
1978
1979 /*
1980  * When we disable a pipe, we need to clear any pending scanline wait events
1981  * to avoid hanging the ring, which we assume we are waiting on.
1982  */
1983 static void intel_clear_scanline_wait(struct drm_device *dev)
1984 {
1985         struct drm_i915_private *dev_priv = dev->dev_private;
1986         u32 tmp;
1987
1988         if (IS_GEN2(dev))
1989                 /* Can't break the hang on i8xx */
1990                 return;
1991
1992         tmp = I915_READ(PRB0_CTL);
1993         if (tmp & RING_WAIT) {
1994                 I915_WRITE(PRB0_CTL, tmp);
1995                 POSTING_READ(PRB0_CTL);
1996         }
1997 }
1998
1999 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2000 {
2001         struct drm_i915_gem_object *obj_priv;
2002         struct drm_i915_private *dev_priv;
2003
2004         if (crtc->fb == NULL)
2005                 return;
2006
2007         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2008         dev_priv = crtc->dev->dev_private;
2009         wait_event(dev_priv->pending_flip_queue,
2010                    atomic_read(&obj_priv->pending_flip) == 0);
2011 }
2012
2013 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2014 {
2015         struct drm_device *dev = crtc->dev;
2016         struct drm_i915_private *dev_priv = dev->dev_private;
2017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2018         int pipe = intel_crtc->pipe;
2019         int plane = intel_crtc->plane;
2020         u32 reg, temp;
2021
2022         if (intel_crtc->active)
2023                 return;
2024
2025         intel_crtc->active = true;
2026         intel_update_watermarks(dev);
2027
2028         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2029                 temp = I915_READ(PCH_LVDS);
2030                 if ((temp & LVDS_PORT_EN) == 0)
2031                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2032         }
2033
2034         ironlake_fdi_enable(crtc);
2035
2036         /* Enable panel fitting for LVDS */
2037         if (dev_priv->pch_pf_size &&
2038             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2039                 /* Force use of hard-coded filter coefficients
2040                  * as some pre-programmed values are broken,
2041                  * e.g. x201.
2042                  */
2043                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2044                            PF_ENABLE | PF_FILTER_MED_3x3);
2045                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2046                            dev_priv->pch_pf_pos);
2047                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2048                            dev_priv->pch_pf_size);
2049         }
2050
2051         /* Enable CPU pipe */
2052         reg = PIPECONF(pipe);
2053         temp = I915_READ(reg);
2054         if ((temp & PIPECONF_ENABLE) == 0) {
2055                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2056                 POSTING_READ(reg);
2057                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2058         }
2059
2060         /* configure and enable CPU plane */
2061         reg = DSPCNTR(plane);
2062         temp = I915_READ(reg);
2063         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2064                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2065                 intel_flush_display_plane(dev, plane);
2066         }
2067
2068         /* For PCH output, training FDI link */
2069         if (IS_GEN6(dev))
2070                 gen6_fdi_link_train(crtc);
2071         else
2072                 ironlake_fdi_link_train(crtc);
2073
2074         /* enable PCH DPLL */
2075         reg = PCH_DPLL(pipe);
2076         temp = I915_READ(reg);
2077         if ((temp & DPLL_VCO_ENABLE) == 0) {
2078                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2079                 POSTING_READ(reg);
2080                 udelay(200);
2081         }
2082
2083         if (HAS_PCH_CPT(dev)) {
2084                 /* Be sure PCH DPLL SEL is set */
2085                 temp = I915_READ(PCH_DPLL_SEL);
2086                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2087                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2088                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2089                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2090                 I915_WRITE(PCH_DPLL_SEL, temp);
2091         }
2092
2093         /* set transcoder timing */
2094         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2095         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2096         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2097
2098         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2099         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2100         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2101
2102         intel_fdi_normal_train(crtc);
2103
2104         /* For PCH DP, enable TRANS_DP_CTL */
2105         if (HAS_PCH_CPT(dev) &&
2106             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2107                 reg = TRANS_DP_CTL(pipe);
2108                 temp = I915_READ(reg);
2109                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2110                           TRANS_DP_SYNC_MASK);
2111                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2112                          TRANS_DP_ENH_FRAMING);
2113
2114                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2115                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2116                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2117                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2118
2119                 switch (intel_trans_dp_port_sel(crtc)) {
2120                 case PCH_DP_B:
2121                         temp |= TRANS_DP_PORT_SEL_B;
2122                         break;
2123                 case PCH_DP_C:
2124                         temp |= TRANS_DP_PORT_SEL_C;
2125                         break;
2126                 case PCH_DP_D:
2127                         temp |= TRANS_DP_PORT_SEL_D;
2128                         break;
2129                 default:
2130                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2131                         temp |= TRANS_DP_PORT_SEL_B;
2132                         break;
2133                 }
2134
2135                 I915_WRITE(reg, temp);
2136         }
2137
2138         /* enable PCH transcoder */
2139         reg = TRANSCONF(pipe);
2140         temp = I915_READ(reg);
2141         /*
2142          * make the BPC in transcoder be consistent with
2143          * that in pipeconf reg.
2144          */
2145         temp &= ~PIPE_BPC_MASK;
2146         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2147         I915_WRITE(reg, temp | TRANS_ENABLE);
2148         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2149                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2150
2151         intel_crtc_load_lut(crtc);
2152         intel_update_fbc(dev);
2153         intel_crtc_update_cursor(crtc, true);
2154 }
2155
2156 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2157 {
2158         struct drm_device *dev = crtc->dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161         int pipe = intel_crtc->pipe;
2162         int plane = intel_crtc->plane;
2163         u32 reg, temp;
2164
2165         if (!intel_crtc->active)
2166                 return;
2167
2168         intel_crtc_wait_for_pending_flips(crtc);
2169         drm_vblank_off(dev, pipe);
2170         intel_crtc_update_cursor(crtc, false);
2171
2172         /* Disable display plane */
2173         reg = DSPCNTR(plane);
2174         temp = I915_READ(reg);
2175         if (temp & DISPLAY_PLANE_ENABLE) {
2176                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2177                 intel_flush_display_plane(dev, plane);
2178         }
2179
2180         if (dev_priv->cfb_plane == plane &&
2181             dev_priv->display.disable_fbc)
2182                 dev_priv->display.disable_fbc(dev);
2183
2184         /* disable cpu pipe, disable after all planes disabled */
2185         reg = PIPECONF(pipe);
2186         temp = I915_READ(reg);
2187         if (temp & PIPECONF_ENABLE) {
2188                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2189                 POSTING_READ(reg);
2190                 /* wait for cpu pipe off, pipe state */
2191                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2192         }
2193
2194         /* Disable PF */
2195         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2196         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2197
2198         /* disable CPU FDI tx and PCH FDI rx */
2199         reg = FDI_TX_CTL(pipe);
2200         temp = I915_READ(reg);
2201         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2202         POSTING_READ(reg);
2203
2204         reg = FDI_RX_CTL(pipe);
2205         temp = I915_READ(reg);
2206         temp &= ~(0x7 << 16);
2207         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2208         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2209
2210         POSTING_READ(reg);
2211         udelay(100);
2212
2213         /* Ironlake workaround, disable clock pointer after downing FDI */
2214         if (HAS_PCH_IBX(dev))
2215                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2216                            I915_READ(FDI_RX_CHICKEN(pipe) &
2217                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2218
2219         /* still set train pattern 1 */
2220         reg = FDI_TX_CTL(pipe);
2221         temp = I915_READ(reg);
2222         temp &= ~FDI_LINK_TRAIN_NONE;
2223         temp |= FDI_LINK_TRAIN_PATTERN_1;
2224         I915_WRITE(reg, temp);
2225
2226         reg = FDI_RX_CTL(pipe);
2227         temp = I915_READ(reg);
2228         if (HAS_PCH_CPT(dev)) {
2229                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2230                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2231         } else {
2232                 temp &= ~FDI_LINK_TRAIN_NONE;
2233                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2234         }
2235         /* BPC in FDI rx is consistent with that in PIPECONF */
2236         temp &= ~(0x07 << 16);
2237         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2238         I915_WRITE(reg, temp);
2239
2240         POSTING_READ(reg);
2241         udelay(100);
2242
2243         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2244                 temp = I915_READ(PCH_LVDS);
2245                 if (temp & LVDS_PORT_EN) {
2246                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2247                         POSTING_READ(PCH_LVDS);
2248                         udelay(100);
2249                 }
2250         }
2251
2252         /* disable PCH transcoder */
2253         reg = TRANSCONF(plane);
2254         temp = I915_READ(reg);
2255         if (temp & TRANS_ENABLE) {
2256                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2257                 /* wait for PCH transcoder off, transcoder state */
2258                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2259                         DRM_ERROR("failed to disable transcoder\n");
2260         }
2261
2262         if (HAS_PCH_CPT(dev)) {
2263                 /* disable TRANS_DP_CTL */
2264                 reg = TRANS_DP_CTL(pipe);
2265                 temp = I915_READ(reg);
2266                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2267                 I915_WRITE(reg, temp);
2268
2269                 /* disable DPLL_SEL */
2270                 temp = I915_READ(PCH_DPLL_SEL);
2271                 if (pipe == 0)
2272                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2273                 else
2274                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2275                 I915_WRITE(PCH_DPLL_SEL, temp);
2276         }
2277
2278         /* disable PCH DPLL */
2279         reg = PCH_DPLL(pipe);
2280         temp = I915_READ(reg);
2281         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2282
2283         /* Switch from PCDclk to Rawclk */
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2287
2288         /* Disable CPU FDI TX PLL */
2289         reg = FDI_TX_CTL(pipe);
2290         temp = I915_READ(reg);
2291         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2292
2293         POSTING_READ(reg);
2294         udelay(100);
2295
2296         reg = FDI_RX_CTL(pipe);
2297         temp = I915_READ(reg);
2298         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2299
2300         /* Wait for the clocks to turn off. */
2301         POSTING_READ(reg);
2302         udelay(100);
2303
2304         intel_crtc->active = false;
2305         intel_update_watermarks(dev);
2306         intel_update_fbc(dev);
2307         intel_clear_scanline_wait(dev);
2308 }
2309
2310 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2311 {
2312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2313         int pipe = intel_crtc->pipe;
2314         int plane = intel_crtc->plane;
2315
2316         /* XXX: When our outputs are all unaware of DPMS modes other than off
2317          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2318          */
2319         switch (mode) {
2320         case DRM_MODE_DPMS_ON:
2321         case DRM_MODE_DPMS_STANDBY:
2322         case DRM_MODE_DPMS_SUSPEND:
2323                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2324                 ironlake_crtc_enable(crtc);
2325                 break;
2326
2327         case DRM_MODE_DPMS_OFF:
2328                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2329                 ironlake_crtc_disable(crtc);
2330                 break;
2331         }
2332 }
2333
2334 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2335 {
2336         if (!enable && intel_crtc->overlay) {
2337                 struct drm_device *dev = intel_crtc->base.dev;
2338
2339                 mutex_lock(&dev->struct_mutex);
2340                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2341                 mutex_unlock(&dev->struct_mutex);
2342         }
2343
2344         /* Let userspace switch the overlay on again. In most cases userspace
2345          * has to recompute where to put it anyway.
2346          */
2347 }
2348
2349 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2354         int pipe = intel_crtc->pipe;
2355         int plane = intel_crtc->plane;
2356         u32 reg, temp;
2357
2358         if (intel_crtc->active)
2359                 return;
2360
2361         intel_crtc->active = true;
2362         intel_update_watermarks(dev);
2363
2364         /* Enable the DPLL */
2365         reg = DPLL(pipe);
2366         temp = I915_READ(reg);
2367         if ((temp & DPLL_VCO_ENABLE) == 0) {
2368                 I915_WRITE(reg, temp);
2369
2370                 /* Wait for the clocks to stabilize. */
2371                 POSTING_READ(reg);
2372                 udelay(150);
2373
2374                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2375
2376                 /* Wait for the clocks to stabilize. */
2377                 POSTING_READ(reg);
2378                 udelay(150);
2379
2380                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2381
2382                 /* Wait for the clocks to stabilize. */
2383                 POSTING_READ(reg);
2384                 udelay(150);
2385         }
2386
2387         /* Enable the pipe */
2388         reg = PIPECONF(pipe);
2389         temp = I915_READ(reg);
2390         if ((temp & PIPECONF_ENABLE) == 0)
2391                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2392
2393         /* Enable the plane */
2394         reg = DSPCNTR(plane);
2395         temp = I915_READ(reg);
2396         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2397                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2398                 intel_flush_display_plane(dev, plane);
2399         }
2400
2401         intel_crtc_load_lut(crtc);
2402         intel_update_fbc(dev);
2403
2404         /* Give the overlay scaler a chance to enable if it's on this pipe */
2405         intel_crtc_dpms_overlay(intel_crtc, true);
2406         intel_crtc_update_cursor(crtc, true);
2407 }
2408
2409 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2410 {
2411         struct drm_device *dev = crtc->dev;
2412         struct drm_i915_private *dev_priv = dev->dev_private;
2413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414         int pipe = intel_crtc->pipe;
2415         int plane = intel_crtc->plane;
2416         u32 reg, temp;
2417
2418         if (!intel_crtc->active)
2419                 return;
2420
2421         /* Give the overlay scaler a chance to disable if it's on this pipe */
2422         intel_crtc_wait_for_pending_flips(crtc);
2423         drm_vblank_off(dev, pipe);
2424         intel_crtc_dpms_overlay(intel_crtc, false);
2425         intel_crtc_update_cursor(crtc, false);
2426
2427         if (dev_priv->cfb_plane == plane &&
2428             dev_priv->display.disable_fbc)
2429                 dev_priv->display.disable_fbc(dev);
2430
2431         /* Disable display plane */
2432         reg = DSPCNTR(plane);
2433         temp = I915_READ(reg);
2434         if (temp & DISPLAY_PLANE_ENABLE) {
2435                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2436                 /* Flush the plane changes */
2437                 intel_flush_display_plane(dev, plane);
2438
2439                 /* Wait for vblank for the disable to take effect */
2440                 if (IS_GEN2(dev))
2441                         intel_wait_for_vblank(dev, pipe);
2442         }
2443
2444         /* Don't disable pipe A or pipe A PLLs if needed */
2445         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2446                 goto done;
2447
2448         /* Next, disable display pipes */
2449         reg = PIPECONF(pipe);
2450         temp = I915_READ(reg);
2451         if (temp & PIPECONF_ENABLE) {
2452                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2453
2454                 /* Wait for the pipe to turn off */
2455                 POSTING_READ(reg);
2456                 intel_wait_for_pipe_off(dev, pipe);
2457         }
2458
2459         reg = DPLL(pipe);
2460         temp = I915_READ(reg);
2461         if (temp & DPLL_VCO_ENABLE) {
2462                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2463
2464                 /* Wait for the clocks to turn off. */
2465                 POSTING_READ(reg);
2466                 udelay(150);
2467         }
2468
2469 done:
2470         intel_crtc->active = false;
2471         intel_update_fbc(dev);
2472         intel_update_watermarks(dev);
2473         intel_clear_scanline_wait(dev);
2474 }
2475
2476 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2477 {
2478         /* XXX: When our outputs are all unaware of DPMS modes other than off
2479          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2480          */
2481         switch (mode) {
2482         case DRM_MODE_DPMS_ON:
2483         case DRM_MODE_DPMS_STANDBY:
2484         case DRM_MODE_DPMS_SUSPEND:
2485                 i9xx_crtc_enable(crtc);
2486                 break;
2487         case DRM_MODE_DPMS_OFF:
2488                 i9xx_crtc_disable(crtc);
2489                 break;
2490         }
2491 }
2492
2493 /**
2494  * Sets the power management mode of the pipe and plane.
2495  */
2496 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2497 {
2498         struct drm_device *dev = crtc->dev;
2499         struct drm_i915_private *dev_priv = dev->dev_private;
2500         struct drm_i915_master_private *master_priv;
2501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2502         int pipe = intel_crtc->pipe;
2503         bool enabled;
2504
2505         if (intel_crtc->dpms_mode == mode)
2506                 return;
2507
2508         intel_crtc->dpms_mode = mode;
2509
2510         dev_priv->display.dpms(crtc, mode);
2511
2512         if (!dev->primary->master)
2513                 return;
2514
2515         master_priv = dev->primary->master->driver_priv;
2516         if (!master_priv->sarea_priv)
2517                 return;
2518
2519         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2520
2521         switch (pipe) {
2522         case 0:
2523                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2524                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2525                 break;
2526         case 1:
2527                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2528                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2529                 break;
2530         default:
2531                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2532                 break;
2533         }
2534 }
2535
2536 static void intel_crtc_disable(struct drm_crtc *crtc)
2537 {
2538         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2539         struct drm_device *dev = crtc->dev;
2540
2541         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2542
2543         if (crtc->fb) {
2544                 mutex_lock(&dev->struct_mutex);
2545                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2546                 mutex_unlock(&dev->struct_mutex);
2547         }
2548 }
2549
2550 /* Prepare for a mode set.
2551  *
2552  * Note we could be a lot smarter here.  We need to figure out which outputs
2553  * will be enabled, which disabled (in short, how the config will changes)
2554  * and perform the minimum necessary steps to accomplish that, e.g. updating
2555  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2556  * panel fitting is in the proper state, etc.
2557  */
2558 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2559 {
2560         i9xx_crtc_disable(crtc);
2561 }
2562
2563 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2564 {
2565         i9xx_crtc_enable(crtc);
2566 }
2567
2568 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2569 {
2570         ironlake_crtc_disable(crtc);
2571 }
2572
2573 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2574 {
2575         ironlake_crtc_enable(crtc);
2576 }
2577
2578 void intel_encoder_prepare (struct drm_encoder *encoder)
2579 {
2580         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2581         /* lvds has its own version of prepare see intel_lvds_prepare */
2582         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2583 }
2584
2585 void intel_encoder_commit (struct drm_encoder *encoder)
2586 {
2587         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2588         /* lvds has its own version of commit see intel_lvds_commit */
2589         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2590 }
2591
2592 void intel_encoder_destroy(struct drm_encoder *encoder)
2593 {
2594         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2595
2596         drm_encoder_cleanup(encoder);
2597         kfree(intel_encoder);
2598 }
2599
2600 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2601                                   struct drm_display_mode *mode,
2602                                   struct drm_display_mode *adjusted_mode)
2603 {
2604         struct drm_device *dev = crtc->dev;
2605
2606         if (HAS_PCH_SPLIT(dev)) {
2607                 /* FDI link clock is fixed at 2.7G */
2608                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2609                         return false;
2610         }
2611
2612         /* XXX some encoders set the crtcinfo, others don't.
2613          * Obviously we need some form of conflict resolution here...
2614          */
2615         if (adjusted_mode->crtc_htotal == 0)
2616                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2617
2618         return true;
2619 }
2620
2621 static int i945_get_display_clock_speed(struct drm_device *dev)
2622 {
2623         return 400000;
2624 }
2625
2626 static int i915_get_display_clock_speed(struct drm_device *dev)
2627 {
2628         return 333000;
2629 }
2630
2631 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2632 {
2633         return 200000;
2634 }
2635
2636 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2637 {
2638         u16 gcfgc = 0;
2639
2640         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2641
2642         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2643                 return 133000;
2644         else {
2645                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2646                 case GC_DISPLAY_CLOCK_333_MHZ:
2647                         return 333000;
2648                 default:
2649                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2650                         return 190000;
2651                 }
2652         }
2653 }
2654
2655 static int i865_get_display_clock_speed(struct drm_device *dev)
2656 {
2657         return 266000;
2658 }
2659
2660 static int i855_get_display_clock_speed(struct drm_device *dev)
2661 {
2662         u16 hpllcc = 0;
2663         /* Assume that the hardware is in the high speed state.  This
2664          * should be the default.
2665          */
2666         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2667         case GC_CLOCK_133_200:
2668         case GC_CLOCK_100_200:
2669                 return 200000;
2670         case GC_CLOCK_166_250:
2671                 return 250000;
2672         case GC_CLOCK_100_133:
2673                 return 133000;
2674         }
2675
2676         /* Shouldn't happen */
2677         return 0;
2678 }
2679
2680 static int i830_get_display_clock_speed(struct drm_device *dev)
2681 {
2682         return 133000;
2683 }
2684
2685 struct fdi_m_n {
2686         u32        tu;
2687         u32        gmch_m;
2688         u32        gmch_n;
2689         u32        link_m;
2690         u32        link_n;
2691 };
2692
2693 static void
2694 fdi_reduce_ratio(u32 *num, u32 *den)
2695 {
2696         while (*num > 0xffffff || *den > 0xffffff) {
2697                 *num >>= 1;
2698                 *den >>= 1;
2699         }
2700 }
2701
2702 #define DATA_N 0x800000
2703 #define LINK_N 0x80000
2704
2705 static void
2706 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2707                      int link_clock, struct fdi_m_n *m_n)
2708 {
2709         u64 temp;
2710
2711         m_n->tu = 64; /* default size */
2712
2713         temp = (u64) DATA_N * pixel_clock;
2714         temp = div_u64(temp, link_clock);
2715         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2716         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2717         m_n->gmch_n = DATA_N;
2718         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2719
2720         temp = (u64) LINK_N * pixel_clock;
2721         m_n->link_m = div_u64(temp, link_clock);
2722         m_n->link_n = LINK_N;
2723         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2724 }
2725
2726
2727 struct intel_watermark_params {
2728         unsigned long fifo_size;
2729         unsigned long max_wm;
2730         unsigned long default_wm;
2731         unsigned long guard_size;
2732         unsigned long cacheline_size;
2733 };
2734
2735 /* Pineview has different values for various configs */
2736 static struct intel_watermark_params pineview_display_wm = {
2737         PINEVIEW_DISPLAY_FIFO,
2738         PINEVIEW_MAX_WM,
2739         PINEVIEW_DFT_WM,
2740         PINEVIEW_GUARD_WM,
2741         PINEVIEW_FIFO_LINE_SIZE
2742 };
2743 static struct intel_watermark_params pineview_display_hplloff_wm = {
2744         PINEVIEW_DISPLAY_FIFO,
2745         PINEVIEW_MAX_WM,
2746         PINEVIEW_DFT_HPLLOFF_WM,
2747         PINEVIEW_GUARD_WM,
2748         PINEVIEW_FIFO_LINE_SIZE
2749 };
2750 static struct intel_watermark_params pineview_cursor_wm = {
2751         PINEVIEW_CURSOR_FIFO,
2752         PINEVIEW_CURSOR_MAX_WM,
2753         PINEVIEW_CURSOR_DFT_WM,
2754         PINEVIEW_CURSOR_GUARD_WM,
2755         PINEVIEW_FIFO_LINE_SIZE,
2756 };
2757 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2758         PINEVIEW_CURSOR_FIFO,
2759         PINEVIEW_CURSOR_MAX_WM,
2760         PINEVIEW_CURSOR_DFT_WM,
2761         PINEVIEW_CURSOR_GUARD_WM,
2762         PINEVIEW_FIFO_LINE_SIZE
2763 };
2764 static struct intel_watermark_params g4x_wm_info = {
2765         G4X_FIFO_SIZE,
2766         G4X_MAX_WM,
2767         G4X_MAX_WM,
2768         2,
2769         G4X_FIFO_LINE_SIZE,
2770 };
2771 static struct intel_watermark_params g4x_cursor_wm_info = {
2772         I965_CURSOR_FIFO,
2773         I965_CURSOR_MAX_WM,
2774         I965_CURSOR_DFT_WM,
2775         2,
2776         G4X_FIFO_LINE_SIZE,
2777 };
2778 static struct intel_watermark_params i965_cursor_wm_info = {
2779         I965_CURSOR_FIFO,
2780         I965_CURSOR_MAX_WM,
2781         I965_CURSOR_DFT_WM,
2782         2,
2783         I915_FIFO_LINE_SIZE,
2784 };
2785 static struct intel_watermark_params i945_wm_info = {
2786         I945_FIFO_SIZE,
2787         I915_MAX_WM,
2788         1,
2789         2,
2790         I915_FIFO_LINE_SIZE
2791 };
2792 static struct intel_watermark_params i915_wm_info = {
2793         I915_FIFO_SIZE,
2794         I915_MAX_WM,
2795         1,
2796         2,
2797         I915_FIFO_LINE_SIZE
2798 };
2799 static struct intel_watermark_params i855_wm_info = {
2800         I855GM_FIFO_SIZE,
2801         I915_MAX_WM,
2802         1,
2803         2,
2804         I830_FIFO_LINE_SIZE
2805 };
2806 static struct intel_watermark_params i830_wm_info = {
2807         I830_FIFO_SIZE,
2808         I915_MAX_WM,
2809         1,
2810         2,
2811         I830_FIFO_LINE_SIZE
2812 };
2813
2814 static struct intel_watermark_params ironlake_display_wm_info = {
2815         ILK_DISPLAY_FIFO,
2816         ILK_DISPLAY_MAXWM,
2817         ILK_DISPLAY_DFTWM,
2818         2,
2819         ILK_FIFO_LINE_SIZE
2820 };
2821
2822 static struct intel_watermark_params ironlake_cursor_wm_info = {
2823         ILK_CURSOR_FIFO,
2824         ILK_CURSOR_MAXWM,
2825         ILK_CURSOR_DFTWM,
2826         2,
2827         ILK_FIFO_LINE_SIZE
2828 };
2829
2830 static struct intel_watermark_params ironlake_display_srwm_info = {
2831         ILK_DISPLAY_SR_FIFO,
2832         ILK_DISPLAY_MAX_SRWM,
2833         ILK_DISPLAY_DFT_SRWM,
2834         2,
2835         ILK_FIFO_LINE_SIZE
2836 };
2837
2838 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2839         ILK_CURSOR_SR_FIFO,
2840         ILK_CURSOR_MAX_SRWM,
2841         ILK_CURSOR_DFT_SRWM,
2842         2,
2843         ILK_FIFO_LINE_SIZE
2844 };
2845
2846 /**
2847  * intel_calculate_wm - calculate watermark level
2848  * @clock_in_khz: pixel clock
2849  * @wm: chip FIFO params
2850  * @pixel_size: display pixel size
2851  * @latency_ns: memory latency for the platform
2852  *
2853  * Calculate the watermark level (the level at which the display plane will
2854  * start fetching from memory again).  Each chip has a different display
2855  * FIFO size and allocation, so the caller needs to figure that out and pass
2856  * in the correct intel_watermark_params structure.
2857  *
2858  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2859  * on the pixel size.  When it reaches the watermark level, it'll start
2860  * fetching FIFO line sized based chunks from memory until the FIFO fills
2861  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2862  * will occur, and a display engine hang could result.
2863  */
2864 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2865                                         struct intel_watermark_params *wm,
2866                                         int pixel_size,
2867                                         unsigned long latency_ns)
2868 {
2869         long entries_required, wm_size;
2870
2871         /*
2872          * Note: we need to make sure we don't overflow for various clock &
2873          * latency values.
2874          * clocks go from a few thousand to several hundred thousand.
2875          * latency is usually a few thousand
2876          */
2877         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2878                 1000;
2879         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2880
2881         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2882
2883         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2884
2885         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2886
2887         /* Don't promote wm_size to unsigned... */
2888         if (wm_size > (long)wm->max_wm)
2889                 wm_size = wm->max_wm;
2890         if (wm_size <= 0)
2891                 wm_size = wm->default_wm;
2892         return wm_size;
2893 }
2894
2895 struct cxsr_latency {
2896         int is_desktop;
2897         int is_ddr3;
2898         unsigned long fsb_freq;
2899         unsigned long mem_freq;
2900         unsigned long display_sr;
2901         unsigned long display_hpll_disable;
2902         unsigned long cursor_sr;
2903         unsigned long cursor_hpll_disable;
2904 };
2905
2906 static const struct cxsr_latency cxsr_latency_table[] = {
2907         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2908         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2909         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2910         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2911         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2912
2913         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2914         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2915         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2916         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2917         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2918
2919         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2920         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2921         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2922         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2923         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2924
2925         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2926         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2927         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2928         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2929         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2930
2931         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2932         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2933         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2934         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2935         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2936
2937         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2938         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2939         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2940         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2941         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2942 };
2943
2944 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2945                                                          int is_ddr3,
2946                                                          int fsb,
2947                                                          int mem)
2948 {
2949         const struct cxsr_latency *latency;
2950         int i;
2951
2952         if (fsb == 0 || mem == 0)
2953                 return NULL;
2954
2955         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2956                 latency = &cxsr_latency_table[i];
2957                 if (is_desktop == latency->is_desktop &&
2958                     is_ddr3 == latency->is_ddr3 &&
2959                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2960                         return latency;
2961         }
2962
2963         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2964
2965         return NULL;
2966 }
2967
2968 static void pineview_disable_cxsr(struct drm_device *dev)
2969 {
2970         struct drm_i915_private *dev_priv = dev->dev_private;
2971
2972         /* deactivate cxsr */
2973         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2974 }
2975
2976 /*
2977  * Latency for FIFO fetches is dependent on several factors:
2978  *   - memory configuration (speed, channels)
2979  *   - chipset
2980  *   - current MCH state
2981  * It can be fairly high in some situations, so here we assume a fairly
2982  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2983  * set this value too high, the FIFO will fetch frequently to stay full)
2984  * and power consumption (set it too low to save power and we might see
2985  * FIFO underruns and display "flicker").
2986  *
2987  * A value of 5us seems to be a good balance; safe for very low end
2988  * platforms but not overly aggressive on lower latency configs.
2989  */
2990 static const int latency_ns = 5000;
2991
2992 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2993 {
2994         struct drm_i915_private *dev_priv = dev->dev_private;
2995         uint32_t dsparb = I915_READ(DSPARB);
2996         int size;
2997
2998         size = dsparb & 0x7f;
2999         if (plane)
3000                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3001
3002         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3003                       plane ? "B" : "A", size);
3004
3005         return size;
3006 }
3007
3008 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3009 {
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         uint32_t dsparb = I915_READ(DSPARB);
3012         int size;
3013
3014         size = dsparb & 0x1ff;
3015         if (plane)
3016                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3017         size >>= 1; /* Convert to cachelines */
3018
3019         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3020                       plane ? "B" : "A", size);
3021
3022         return size;
3023 }
3024
3025 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3026 {
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         uint32_t dsparb = I915_READ(DSPARB);
3029         int size;
3030
3031         size = dsparb & 0x7f;
3032         size >>= 2; /* Convert to cachelines */
3033
3034         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3035                       plane ? "B" : "A",
3036                       size);
3037
3038         return size;
3039 }
3040
3041 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3042 {
3043         struct drm_i915_private *dev_priv = dev->dev_private;
3044         uint32_t dsparb = I915_READ(DSPARB);
3045         int size;
3046
3047         size = dsparb & 0x7f;
3048         size >>= 1; /* Convert to cachelines */
3049
3050         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3051                       plane ? "B" : "A", size);
3052
3053         return size;
3054 }
3055
3056 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3057                                int planeb_clock, int sr_hdisplay, int unused,
3058                                int pixel_size)
3059 {
3060         struct drm_i915_private *dev_priv = dev->dev_private;
3061         const struct cxsr_latency *latency;
3062         u32 reg;
3063         unsigned long wm;
3064         int sr_clock;
3065
3066         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3067                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3068         if (!latency) {
3069                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3070                 pineview_disable_cxsr(dev);
3071                 return;
3072         }
3073
3074         if (!planea_clock || !planeb_clock) {
3075                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3076
3077                 /* Display SR */
3078                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3079                                         pixel_size, latency->display_sr);
3080                 reg = I915_READ(DSPFW1);
3081                 reg &= ~DSPFW_SR_MASK;
3082                 reg |= wm << DSPFW_SR_SHIFT;
3083                 I915_WRITE(DSPFW1, reg);
3084                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3085
3086                 /* cursor SR */
3087                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3088                                         pixel_size, latency->cursor_sr);
3089                 reg = I915_READ(DSPFW3);
3090                 reg &= ~DSPFW_CURSOR_SR_MASK;
3091                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3092                 I915_WRITE(DSPFW3, reg);
3093
3094                 /* Display HPLL off SR */
3095                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3096                                         pixel_size, latency->display_hpll_disable);
3097                 reg = I915_READ(DSPFW3);
3098                 reg &= ~DSPFW_HPLL_SR_MASK;
3099                 reg |= wm & DSPFW_HPLL_SR_MASK;
3100                 I915_WRITE(DSPFW3, reg);
3101
3102                 /* cursor HPLL off SR */
3103                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3104                                         pixel_size, latency->cursor_hpll_disable);
3105                 reg = I915_READ(DSPFW3);
3106                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3107                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3108                 I915_WRITE(DSPFW3, reg);
3109                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3110
3111                 /* activate cxsr */
3112                 I915_WRITE(DSPFW3,
3113                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3114                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3115         } else {
3116                 pineview_disable_cxsr(dev);
3117                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3118         }
3119 }
3120
3121 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3122                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3123                           int pixel_size)
3124 {
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         int total_size, cacheline_size;
3127         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3128         struct intel_watermark_params planea_params, planeb_params;
3129         unsigned long line_time_us;
3130         int sr_clock, sr_entries = 0, entries_required;
3131
3132         /* Create copies of the base settings for each pipe */
3133         planea_params = planeb_params = g4x_wm_info;
3134
3135         /* Grab a couple of global values before we overwrite them */
3136         total_size = planea_params.fifo_size;
3137         cacheline_size = planea_params.cacheline_size;
3138
3139         /*
3140          * Note: we need to make sure we don't overflow for various clock &
3141          * latency values.
3142          * clocks go from a few thousand to several hundred thousand.
3143          * latency is usually a few thousand
3144          */
3145         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3146                 1000;
3147         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3148         planea_wm = entries_required + planea_params.guard_size;
3149
3150         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3151                 1000;
3152         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3153         planeb_wm = entries_required + planeb_params.guard_size;
3154
3155         cursora_wm = cursorb_wm = 16;
3156         cursor_sr = 32;
3157
3158         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3159
3160         /* Calc sr entries for one plane configs */
3161         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3162                 /* self-refresh has much higher latency */
3163                 static const int sr_latency_ns = 12000;
3164
3165                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3166                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3167
3168                 /* Use ns/us then divide to preserve precision */
3169                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3170                         pixel_size * sr_hdisplay;
3171                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3172
3173                 entries_required = (((sr_latency_ns / line_time_us) +
3174                                      1000) / 1000) * pixel_size * 64;
3175                 entries_required = DIV_ROUND_UP(entries_required,
3176                                                 g4x_cursor_wm_info.cacheline_size);
3177                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3178
3179                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3180                         cursor_sr = g4x_cursor_wm_info.max_wm;
3181                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3182                               "cursor %d\n", sr_entries, cursor_sr);
3183
3184                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3185         } else {
3186                 /* Turn off self refresh if both pipes are enabled */
3187                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3188                            & ~FW_BLC_SELF_EN);
3189         }
3190
3191         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3192                   planea_wm, planeb_wm, sr_entries);
3193
3194         planea_wm &= 0x3f;
3195         planeb_wm &= 0x3f;
3196
3197         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3198                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3199                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3200         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3201                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3202         /* HPLL off in SR has some issues on G4x... disable it */
3203         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3204                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3205 }
3206
3207 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3208                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3209                            int pixel_size)
3210 {
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         unsigned long line_time_us;
3213         int sr_clock, sr_entries, srwm = 1;
3214         int cursor_sr = 16;
3215
3216         /* Calc sr entries for one plane configs */
3217         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3218                 /* self-refresh has much higher latency */
3219                 static const int sr_latency_ns = 12000;
3220
3221                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3222                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3223
3224                 /* Use ns/us then divide to preserve precision */
3225                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3226                         pixel_size * sr_hdisplay;
3227                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3228                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3229                 srwm = I965_FIFO_SIZE - sr_entries;
3230                 if (srwm < 0)
3231                         srwm = 1;
3232                 srwm &= 0x1ff;
3233
3234                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3235                         pixel_size * 64;
3236                 sr_entries = DIV_ROUND_UP(sr_entries,
3237                                           i965_cursor_wm_info.cacheline_size);
3238                 cursor_sr = i965_cursor_wm_info.fifo_size -
3239                         (sr_entries + i965_cursor_wm_info.guard_size);
3240
3241                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3242                         cursor_sr = i965_cursor_wm_info.max_wm;
3243
3244                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3245                               "cursor %d\n", srwm, cursor_sr);
3246
3247                 if (IS_CRESTLINE(dev))
3248                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3249         } else {
3250                 /* Turn off self refresh if both pipes are enabled */
3251                 if (IS_CRESTLINE(dev))
3252                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3253                                    & ~FW_BLC_SELF_EN);
3254         }
3255
3256         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3257                       srwm);
3258
3259         /* 965 has limitations... */
3260         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3261                    (8 << 0));
3262         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3263         /* update cursor SR watermark */
3264         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3265 }
3266
3267 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3268                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3269                            int pixel_size)
3270 {
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         uint32_t fwater_lo;
3273         uint32_t fwater_hi;
3274         int total_size, cacheline_size, cwm, srwm = 1;
3275         int planea_wm, planeb_wm;
3276         struct intel_watermark_params planea_params, planeb_params;
3277         unsigned long line_time_us;
3278         int sr_clock, sr_entries = 0;
3279
3280         /* Create copies of the base settings for each pipe */
3281         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3282                 planea_params = planeb_params = i945_wm_info;
3283         else if (!IS_GEN2(dev))
3284                 planea_params = planeb_params = i915_wm_info;
3285         else
3286                 planea_params = planeb_params = i855_wm_info;
3287
3288         /* Grab a couple of global values before we overwrite them */
3289         total_size = planea_params.fifo_size;
3290         cacheline_size = planea_params.cacheline_size;
3291
3292         /* Update per-plane FIFO sizes */
3293         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3294         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3295
3296         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3297                                        pixel_size, latency_ns);
3298         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3299                                        pixel_size, latency_ns);
3300         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3301
3302         /*
3303          * Overlay gets an aggressive default since video jitter is bad.
3304          */
3305         cwm = 2;
3306
3307         /* Calc sr entries for one plane configs */
3308         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3309             (!planea_clock || !planeb_clock)) {
3310                 /* self-refresh has much higher latency */
3311                 static const int sr_latency_ns = 6000;
3312
3313                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3314                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3315
3316                 /* Use ns/us then divide to preserve precision */
3317                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3318                         pixel_size * sr_hdisplay;
3319                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3320                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3321                 srwm = total_size - sr_entries;
3322                 if (srwm < 0)
3323                         srwm = 1;
3324
3325                 if (IS_I945G(dev) || IS_I945GM(dev))
3326                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3327                 else if (IS_I915GM(dev)) {
3328                         /* 915M has a smaller SRWM field */
3329                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3330                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3331                 }
3332         } else {
3333                 /* Turn off self refresh if both pipes are enabled */
3334                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3335                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3336                                    & ~FW_BLC_SELF_EN);
3337                 } else if (IS_I915GM(dev)) {
3338                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3339                 }
3340         }
3341
3342         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3343                       planea_wm, planeb_wm, cwm, srwm);
3344
3345         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3346         fwater_hi = (cwm & 0x1f);
3347
3348         /* Set request length to 8 cachelines per fetch */
3349         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3350         fwater_hi = fwater_hi | (1 << 8);
3351
3352         I915_WRITE(FW_BLC, fwater_lo);
3353         I915_WRITE(FW_BLC2, fwater_hi);
3354 }
3355
3356 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3357                            int unused2, int unused3, int pixel_size)
3358 {
3359         struct drm_i915_private *dev_priv = dev->dev_private;
3360         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3361         int planea_wm;
3362
3363         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3364
3365         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3366                                        pixel_size, latency_ns);
3367         fwater_lo |= (3<<8) | planea_wm;
3368
3369         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3370
3371         I915_WRITE(FW_BLC, fwater_lo);
3372 }
3373
3374 #define ILK_LP0_PLANE_LATENCY           700
3375 #define ILK_LP0_CURSOR_LATENCY          1300
3376
3377 static bool ironlake_compute_wm0(struct drm_device *dev,
3378                                  int pipe,
3379                                  int *plane_wm,
3380                                  int *cursor_wm)
3381 {
3382         struct drm_crtc *crtc;
3383         int htotal, hdisplay, clock, pixel_size = 0;
3384         int line_time_us, line_count, entries;
3385
3386         crtc = intel_get_crtc_for_pipe(dev, pipe);
3387         if (crtc->fb == NULL || !crtc->enabled)
3388                 return false;
3389
3390         htotal = crtc->mode.htotal;
3391         hdisplay = crtc->mode.hdisplay;
3392         clock = crtc->mode.clock;
3393         pixel_size = crtc->fb->bits_per_pixel / 8;
3394
3395         /* Use the small buffer method to calculate plane watermark */
3396         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3397         entries = DIV_ROUND_UP(entries,
3398                                ironlake_display_wm_info.cacheline_size);
3399         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3400         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3401                 *plane_wm = ironlake_display_wm_info.max_wm;
3402
3403         /* Use the large buffer method to calculate cursor watermark */
3404         line_time_us = ((htotal * 1000) / clock);
3405         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3406         entries = line_count * 64 * pixel_size;
3407         entries = DIV_ROUND_UP(entries,
3408                                ironlake_cursor_wm_info.cacheline_size);
3409         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3410         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3411                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3412
3413         return true;
3414 }
3415
3416 static void ironlake_update_wm(struct drm_device *dev,
3417                                int planea_clock, int planeb_clock,
3418                                int sr_hdisplay, int sr_htotal,
3419                                int pixel_size)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         int plane_wm, cursor_wm, enabled;
3423         int tmp;
3424
3425         enabled = 0;
3426         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3427                 I915_WRITE(WM0_PIPEA_ILK,
3428                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3429                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3430                               " plane %d, " "cursor: %d\n",
3431                               plane_wm, cursor_wm);
3432                 enabled++;
3433         }
3434
3435         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3436                 I915_WRITE(WM0_PIPEB_ILK,
3437                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3438                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3439                               " plane %d, cursor: %d\n",
3440                               plane_wm, cursor_wm);
3441                 enabled++;
3442         }
3443
3444         /*
3445          * Calculate and update the self-refresh watermark only when one
3446          * display plane is used.
3447          */
3448         tmp = 0;
3449         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3450                 unsigned long line_time_us;
3451                 int small, large, plane_fbc;
3452                 int sr_clock, entries;
3453                 int line_count, line_size;
3454                 /* Read the self-refresh latency. The unit is 0.5us */
3455                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3456
3457                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3458                 line_time_us = (sr_htotal * 1000) / sr_clock;
3459
3460                 /* Use ns/us then divide to preserve precision */
3461                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3462                         / 1000;
3463                 line_size = sr_hdisplay * pixel_size;
3464
3465                 /* Use the minimum of the small and large buffer method for primary */
3466                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3467                 large = line_count * line_size;
3468
3469                 entries = DIV_ROUND_UP(min(small, large),
3470                                        ironlake_display_srwm_info.cacheline_size);
3471
3472                 plane_fbc = entries * 64;
3473                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3474
3475                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3476                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3477                         plane_wm = ironlake_display_srwm_info.max_wm;
3478
3479                 /* calculate the self-refresh watermark for display cursor */
3480                 entries = line_count * pixel_size * 64;
3481                 entries = DIV_ROUND_UP(entries,
3482                                        ironlake_cursor_srwm_info.cacheline_size);
3483
3484                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3485                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3486                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3487
3488                 /* configure watermark and enable self-refresh */
3489                 tmp = (WM1_LP_SR_EN |
3490                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3491                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3492                        (plane_wm << WM1_LP_SR_SHIFT) |
3493                        cursor_wm);
3494                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3495                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3496         }
3497         I915_WRITE(WM1_LP_ILK, tmp);
3498         /* XXX setup WM2 and WM3 */
3499 }
3500
3501 /**
3502  * intel_update_watermarks - update FIFO watermark values based on current modes
3503  *
3504  * Calculate watermark values for the various WM regs based on current mode
3505  * and plane configuration.
3506  *
3507  * There are several cases to deal with here:
3508  *   - normal (i.e. non-self-refresh)
3509  *   - self-refresh (SR) mode
3510  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3511  *   - lines are small relative to FIFO size (buffer can hold more than 2
3512  *     lines), so need to account for TLB latency
3513  *
3514  *   The normal calculation is:
3515  *     watermark = dotclock * bytes per pixel * latency
3516  *   where latency is platform & configuration dependent (we assume pessimal
3517  *   values here).
3518  *
3519  *   The SR calculation is:
3520  *     watermark = (trunc(latency/line time)+1) * surface width *
3521  *       bytes per pixel
3522  *   where
3523  *     line time = htotal / dotclock
3524  *     surface width = hdisplay for normal plane and 64 for cursor
3525  *   and latency is assumed to be high, as above.
3526  *
3527  * The final value programmed to the register should always be rounded up,
3528  * and include an extra 2 entries to account for clock crossings.
3529  *
3530  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3531  * to set the non-SR watermarks to 8.
3532  */
3533 static void intel_update_watermarks(struct drm_device *dev)
3534 {
3535         struct drm_i915_private *dev_priv = dev->dev_private;
3536         struct drm_crtc *crtc;
3537         int sr_hdisplay = 0;
3538         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3539         int enabled = 0, pixel_size = 0;
3540         int sr_htotal = 0;
3541
3542         if (!dev_priv->display.update_wm)
3543                 return;
3544
3545         /* Get the clock config from both planes */
3546         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3547                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548                 if (intel_crtc->active) {
3549                         enabled++;
3550                         if (intel_crtc->plane == 0) {
3551                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3552                                               intel_crtc->pipe, crtc->mode.clock);
3553                                 planea_clock = crtc->mode.clock;
3554                         } else {
3555                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3556                                               intel_crtc->pipe, crtc->mode.clock);
3557                                 planeb_clock = crtc->mode.clock;
3558                         }
3559                         sr_hdisplay = crtc->mode.hdisplay;
3560                         sr_clock = crtc->mode.clock;
3561                         sr_htotal = crtc->mode.htotal;
3562                         if (crtc->fb)
3563                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3564                         else
3565                                 pixel_size = 4; /* by default */
3566                 }
3567         }
3568
3569         if (enabled <= 0)
3570                 return;
3571
3572         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3573                                     sr_hdisplay, sr_htotal, pixel_size);
3574 }
3575
3576 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3577                                struct drm_display_mode *mode,
3578                                struct drm_display_mode *adjusted_mode,
3579                                int x, int y,
3580                                struct drm_framebuffer *old_fb)
3581 {
3582         struct drm_device *dev = crtc->dev;
3583         struct drm_i915_private *dev_priv = dev->dev_private;
3584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585         int pipe = intel_crtc->pipe;
3586         int plane = intel_crtc->plane;
3587         u32 fp_reg, dpll_reg;
3588         int refclk, num_connectors = 0;
3589         intel_clock_t clock, reduced_clock;
3590         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3591         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3592         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3593         struct intel_encoder *has_edp_encoder = NULL;
3594         struct drm_mode_config *mode_config = &dev->mode_config;
3595         struct intel_encoder *encoder;
3596         const intel_limit_t *limit;
3597         int ret;
3598         struct fdi_m_n m_n = {0};
3599         u32 reg, temp;
3600         int target_clock;
3601
3602         drm_vblank_pre_modeset(dev, pipe);
3603
3604         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3605                 if (encoder->base.crtc != crtc)
3606                         continue;
3607
3608                 switch (encoder->type) {
3609                 case INTEL_OUTPUT_LVDS:
3610                         is_lvds = true;
3611                         break;
3612                 case INTEL_OUTPUT_SDVO:
3613                 case INTEL_OUTPUT_HDMI:
3614                         is_sdvo = true;
3615                         if (encoder->needs_tv_clock)
3616                                 is_tv = true;
3617                         break;
3618                 case INTEL_OUTPUT_DVO:
3619                         is_dvo = true;
3620                         break;
3621                 case INTEL_OUTPUT_TVOUT:
3622                         is_tv = true;
3623                         break;
3624                 case INTEL_OUTPUT_ANALOG:
3625                         is_crt = true;
3626                         break;
3627                 case INTEL_OUTPUT_DISPLAYPORT:
3628                         is_dp = true;
3629                         break;
3630                 case INTEL_OUTPUT_EDP:
3631                         has_edp_encoder = encoder;
3632                         break;
3633                 }
3634
3635                 num_connectors++;
3636         }
3637
3638         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3639                 refclk = dev_priv->lvds_ssc_freq * 1000;
3640                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3641                               refclk / 1000);
3642         } else if (!IS_GEN2(dev)) {
3643                 refclk = 96000;
3644                 if (HAS_PCH_SPLIT(dev) &&
3645                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3646                         refclk = 120000; /* 120Mhz refclk */
3647         } else {
3648                 refclk = 48000;
3649         }
3650
3651         /*
3652          * Returns a set of divisors for the desired target clock with the given
3653          * refclk, or FALSE.  The returned values represent the clock equation:
3654          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3655          */
3656         limit = intel_limit(crtc);
3657         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3658         if (!ok) {
3659                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3660                 drm_vblank_post_modeset(dev, pipe);
3661                 return -EINVAL;
3662         }
3663
3664         /* Ensure that the cursor is valid for the new mode before changing... */
3665         intel_crtc_update_cursor(crtc, true);
3666
3667         if (is_lvds && dev_priv->lvds_downclock_avail) {
3668                 has_reduced_clock = limit->find_pll(limit, crtc,
3669                                                     dev_priv->lvds_downclock,
3670                                                     refclk,
3671                                                     &reduced_clock);
3672                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3673                         /*
3674                          * If the different P is found, it means that we can't
3675                          * switch the display clock by using the FP0/FP1.
3676                          * In such case we will disable the LVDS downclock
3677                          * feature.
3678                          */
3679                         DRM_DEBUG_KMS("Different P is found for "
3680                                       "LVDS clock/downclock\n");
3681                         has_reduced_clock = 0;
3682                 }
3683         }
3684         /* SDVO TV has fixed PLL values depend on its clock range,
3685            this mirrors vbios setting. */
3686         if (is_sdvo && is_tv) {
3687                 if (adjusted_mode->clock >= 100000
3688                     && adjusted_mode->clock < 140500) {
3689                         clock.p1 = 2;
3690                         clock.p2 = 10;
3691                         clock.n = 3;
3692                         clock.m1 = 16;
3693                         clock.m2 = 8;
3694                 } else if (adjusted_mode->clock >= 140500
3695                            && adjusted_mode->clock <= 200000) {
3696                         clock.p1 = 1;
3697                         clock.p2 = 10;
3698                         clock.n = 6;
3699                         clock.m1 = 12;
3700                         clock.m2 = 8;
3701                 }
3702         }
3703
3704         /* FDI link */
3705         if (HAS_PCH_SPLIT(dev)) {
3706                 int lane = 0, link_bw, bpp;
3707                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3708                    according to current link config */
3709                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3710                         target_clock = mode->clock;
3711                         intel_edp_link_config(has_edp_encoder,
3712                                               &lane, &link_bw);
3713                 } else {
3714                         /* [e]DP over FDI requires target mode clock
3715                            instead of link clock */
3716                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3717                                 target_clock = mode->clock;
3718                         else
3719                                 target_clock = adjusted_mode->clock;
3720
3721                         /* FDI is a binary signal running at ~2.7GHz, encoding
3722                          * each output octet as 10 bits. The actual frequency
3723                          * is stored as a divider into a 100MHz clock, and the
3724                          * mode pixel clock is stored in units of 1KHz.
3725                          * Hence the bw of each lane in terms of the mode signal
3726                          * is:
3727                          */
3728                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3729                 }
3730
3731                 /* determine panel color depth */
3732                 temp = I915_READ(PIPECONF(pipe));
3733                 temp &= ~PIPE_BPC_MASK;
3734                 if (is_lvds) {
3735                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3736                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3737                                 temp |= PIPE_8BPC;
3738                         else
3739                                 temp |= PIPE_6BPC;
3740                 } else if (has_edp_encoder) {
3741                         switch (dev_priv->edp.bpp/3) {
3742                         case 8:
3743                                 temp |= PIPE_8BPC;
3744                                 break;
3745                         case 10:
3746                                 temp |= PIPE_10BPC;
3747                                 break;
3748                         case 6:
3749                                 temp |= PIPE_6BPC;
3750                                 break;
3751                         case 12:
3752                                 temp |= PIPE_12BPC;
3753                                 break;
3754                         }
3755                 } else
3756                         temp |= PIPE_8BPC;
3757                 I915_WRITE(PIPECONF(pipe), temp);
3758
3759                 switch (temp & PIPE_BPC_MASK) {
3760                 case PIPE_8BPC:
3761                         bpp = 24;
3762                         break;
3763                 case PIPE_10BPC:
3764                         bpp = 30;
3765                         break;
3766                 case PIPE_6BPC:
3767                         bpp = 18;
3768                         break;
3769                 case PIPE_12BPC:
3770                         bpp = 36;
3771                         break;
3772                 default:
3773                         DRM_ERROR("unknown pipe bpc value\n");
3774                         bpp = 24;
3775                 }
3776
3777                 if (!lane) {
3778                         /*
3779                          * Account for spread spectrum to avoid
3780                          * oversubscribing the link. Max center spread
3781                          * is 2.5%; use 5% for safety's sake.
3782                          */
3783                         u32 bps = target_clock * bpp * 21 / 20;
3784                         lane = bps / (link_bw * 8) + 1;
3785                 }
3786
3787                 intel_crtc->fdi_lanes = lane;
3788
3789                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3790         }
3791
3792         /* Ironlake: try to setup display ref clock before DPLL
3793          * enabling. This is only under driver's control after
3794          * PCH B stepping, previous chipset stepping should be
3795          * ignoring this setting.
3796          */
3797         if (HAS_PCH_SPLIT(dev)) {
3798                 temp = I915_READ(PCH_DREF_CONTROL);
3799                 /* Always enable nonspread source */
3800                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3801                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3802                 temp &= ~DREF_SSC_SOURCE_MASK;
3803                 temp |= DREF_SSC_SOURCE_ENABLE;
3804                 I915_WRITE(PCH_DREF_CONTROL, temp);
3805
3806                 POSTING_READ(PCH_DREF_CONTROL);
3807                 udelay(200);
3808
3809                 if (has_edp_encoder) {
3810                         if (dev_priv->lvds_use_ssc) {
3811                                 temp |= DREF_SSC1_ENABLE;
3812                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3813
3814                                 POSTING_READ(PCH_DREF_CONTROL);
3815                                 udelay(200);
3816                         }
3817                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3818
3819                         /* Enable CPU source on CPU attached eDP */
3820                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3821                                 if (dev_priv->lvds_use_ssc)
3822                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3823                                 else
3824                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3825                         } else {
3826                                 /* Enable SSC on PCH eDP if needed */
3827                                 if (dev_priv->lvds_use_ssc) {
3828                                         DRM_ERROR("enabling SSC on PCH\n");
3829                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3830                                 }
3831                         }
3832                         I915_WRITE(PCH_DREF_CONTROL, temp);
3833                         POSTING_READ(PCH_DREF_CONTROL);
3834                         udelay(200);
3835                 }
3836         }
3837
3838         if (IS_PINEVIEW(dev)) {
3839                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3840                 if (has_reduced_clock)
3841                         fp2 = (1 << reduced_clock.n) << 16 |
3842                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3843         } else {
3844                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3845                 if (has_reduced_clock)
3846                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3847                                 reduced_clock.m2;
3848         }
3849
3850         dpll = 0;
3851         if (!HAS_PCH_SPLIT(dev))
3852                 dpll = DPLL_VGA_MODE_DIS;
3853
3854         if (!IS_GEN2(dev)) {
3855                 if (is_lvds)
3856                         dpll |= DPLLB_MODE_LVDS;
3857                 else
3858                         dpll |= DPLLB_MODE_DAC_SERIAL;
3859                 if (is_sdvo) {
3860                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3861                         if (pixel_multiplier > 1) {
3862                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3863                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3864                                 else if (HAS_PCH_SPLIT(dev))
3865                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3866                         }
3867                         dpll |= DPLL_DVO_HIGH_SPEED;
3868                 }
3869                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3870                         dpll |= DPLL_DVO_HIGH_SPEED;
3871
3872                 /* compute bitmask from p1 value */
3873                 if (IS_PINEVIEW(dev))
3874                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3875                 else {
3876                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3877                         /* also FPA1 */
3878                         if (HAS_PCH_SPLIT(dev))
3879                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3880                         if (IS_G4X(dev) && has_reduced_clock)
3881                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3882                 }
3883                 switch (clock.p2) {
3884                 case 5:
3885                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3886                         break;
3887                 case 7:
3888                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3889                         break;
3890                 case 10:
3891                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3892                         break;
3893                 case 14:
3894                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3895                         break;
3896                 }
3897                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3898                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3899         } else {
3900                 if (is_lvds) {
3901                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3902                 } else {
3903                         if (clock.p1 == 2)
3904                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3905                         else
3906                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3907                         if (clock.p2 == 4)
3908                                 dpll |= PLL_P2_DIVIDE_BY_4;
3909                 }
3910         }
3911
3912         if (is_sdvo && is_tv)
3913                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3914         else if (is_tv)
3915                 /* XXX: just matching BIOS for now */
3916                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3917                 dpll |= 3;
3918         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3919                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3920         else
3921                 dpll |= PLL_REF_INPUT_DREFCLK;
3922
3923         /* setup pipeconf */
3924         pipeconf = I915_READ(PIPECONF(pipe));
3925
3926         /* Set up the display plane register */
3927         dspcntr = DISPPLANE_GAMMA_ENABLE;
3928
3929         /* Ironlake's plane is forced to pipe, bit 24 is to
3930            enable color space conversion */
3931         if (!HAS_PCH_SPLIT(dev)) {
3932                 if (pipe == 0)
3933                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3934                 else
3935                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3936         }
3937
3938         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3939                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3940                  * core speed.
3941                  *
3942                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3943                  * pipe == 0 check?
3944                  */
3945                 if (mode->clock >
3946                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3947                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3948                 else
3949                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3950         }
3951
3952         dspcntr |= DISPLAY_PLANE_ENABLE;
3953         pipeconf |= PIPECONF_ENABLE;
3954         dpll |= DPLL_VCO_ENABLE;
3955
3956         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3957         drm_mode_debug_printmodeline(mode);
3958
3959         /* assign to Ironlake registers */
3960         if (HAS_PCH_SPLIT(dev)) {
3961                 fp_reg = PCH_FP0(pipe);
3962                 dpll_reg = PCH_DPLL(pipe);
3963         } else {
3964                 fp_reg = FP0(pipe);
3965                 dpll_reg = DPLL(pipe);
3966         }
3967
3968         /* PCH eDP needs FDI, but CPU eDP does not */
3969         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3970                 I915_WRITE(fp_reg, fp);
3971                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3972
3973                 POSTING_READ(dpll_reg);
3974                 udelay(150);
3975         }
3976
3977         /* enable transcoder DPLL */
3978         if (HAS_PCH_CPT(dev)) {
3979                 temp = I915_READ(PCH_DPLL_SEL);
3980                 if (pipe == 0)
3981                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3982                 else
3983                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3984                 I915_WRITE(PCH_DPLL_SEL, temp);
3985
3986                 POSTING_READ(PCH_DPLL_SEL);
3987                 udelay(150);
3988         }
3989
3990         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3991          * This is an exception to the general rule that mode_set doesn't turn
3992          * things on.
3993          */
3994         if (is_lvds) {
3995                 reg = LVDS;
3996                 if (HAS_PCH_SPLIT(dev))
3997                         reg = PCH_LVDS;
3998
3999                 temp = I915_READ(reg);
4000                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4001                 if (pipe == 1) {
4002                         if (HAS_PCH_CPT(dev))
4003                                 temp |= PORT_TRANS_B_SEL_CPT;
4004                         else
4005                                 temp |= LVDS_PIPEB_SELECT;
4006                 } else {
4007                         if (HAS_PCH_CPT(dev))
4008                                 temp &= ~PORT_TRANS_SEL_MASK;
4009                         else
4010                                 temp &= ~LVDS_PIPEB_SELECT;
4011                 }
4012                 /* set the corresponsding LVDS_BORDER bit */
4013                 temp |= dev_priv->lvds_border_bits;
4014                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4015                  * set the DPLLs for dual-channel mode or not.
4016                  */
4017                 if (clock.p2 == 7)
4018                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4019                 else
4020                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4021
4022                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4023                  * appropriately here, but we need to look more thoroughly into how
4024                  * panels behave in the two modes.
4025                  */
4026                 /* set the dithering flag on non-PCH LVDS as needed */
4027                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4028                         if (dev_priv->lvds_dither)
4029                                 temp |= LVDS_ENABLE_DITHER;
4030                         else
4031                                 temp &= ~LVDS_ENABLE_DITHER;
4032                 }
4033                 I915_WRITE(reg, temp);
4034         }
4035
4036         /* set the dithering flag and clear for anything other than a panel. */
4037         if (HAS_PCH_SPLIT(dev)) {
4038                 pipeconf &= ~PIPECONF_DITHER_EN;
4039                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4040                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4041                         pipeconf |= PIPECONF_DITHER_EN;
4042                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4043                 }
4044         }
4045
4046         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4047                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4048         } else if (HAS_PCH_SPLIT(dev)) {
4049                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4050                 if (pipe == 0) {
4051                         I915_WRITE(TRANSA_DATA_M1, 0);
4052                         I915_WRITE(TRANSA_DATA_N1, 0);
4053                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4054                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4055                 } else {
4056                         I915_WRITE(TRANSB_DATA_M1, 0);
4057                         I915_WRITE(TRANSB_DATA_N1, 0);
4058                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4059                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4060                 }
4061         }
4062
4063         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4064                 I915_WRITE(fp_reg, fp);
4065                 I915_WRITE(dpll_reg, dpll);
4066
4067                 /* Wait for the clocks to stabilize. */
4068                 POSTING_READ(dpll_reg);
4069                 udelay(150);
4070
4071                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4072                         temp = 0;
4073                         if (is_sdvo) {
4074                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4075                                 if (temp > 1)
4076                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4077                                 else
4078                                         temp = 0;
4079                         }
4080                         I915_WRITE(DPLL_MD(pipe), temp);
4081                 } else {
4082                         /* write it again -- the BIOS does, after all */
4083                         I915_WRITE(dpll_reg, dpll);
4084                 }
4085
4086                 /* Wait for the clocks to stabilize. */
4087                 POSTING_READ(dpll_reg);
4088                 udelay(150);
4089         }
4090
4091         intel_crtc->lowfreq_avail = false;
4092         if (is_lvds && has_reduced_clock && i915_powersave) {
4093                 I915_WRITE(fp_reg + 4, fp2);
4094                 intel_crtc->lowfreq_avail = true;
4095                 if (HAS_PIPE_CXSR(dev)) {
4096                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4097                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4098                 }
4099         } else {
4100                 I915_WRITE(fp_reg + 4, fp);
4101                 if (HAS_PIPE_CXSR(dev)) {
4102                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4103                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4104                 }
4105         }
4106
4107         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4108                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4109                 /* the chip adds 2 halflines automatically */
4110                 adjusted_mode->crtc_vdisplay -= 1;
4111                 adjusted_mode->crtc_vtotal -= 1;
4112                 adjusted_mode->crtc_vblank_start -= 1;
4113                 adjusted_mode->crtc_vblank_end -= 1;
4114                 adjusted_mode->crtc_vsync_end -= 1;
4115                 adjusted_mode->crtc_vsync_start -= 1;
4116         } else
4117                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4118
4119         I915_WRITE(HTOTAL(pipe),
4120                    (adjusted_mode->crtc_hdisplay - 1) |
4121                    ((adjusted_mode->crtc_htotal - 1) << 16));
4122         I915_WRITE(HBLANK(pipe),
4123                    (adjusted_mode->crtc_hblank_start - 1) |
4124                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4125         I915_WRITE(HSYNC(pipe),
4126                    (adjusted_mode->crtc_hsync_start - 1) |
4127                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4128
4129         I915_WRITE(VTOTAL(pipe),
4130                    (adjusted_mode->crtc_vdisplay - 1) |
4131                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4132         I915_WRITE(VBLANK(pipe),
4133                    (adjusted_mode->crtc_vblank_start - 1) |
4134                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4135         I915_WRITE(VSYNC(pipe),
4136                    (adjusted_mode->crtc_vsync_start - 1) |
4137                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4138
4139         /* pipesrc and dspsize control the size that is scaled from,
4140          * which should always be the user's requested size.
4141          */
4142         if (!HAS_PCH_SPLIT(dev)) {
4143                 I915_WRITE(DSPSIZE(plane),
4144                            ((mode->vdisplay - 1) << 16) |
4145                            (mode->hdisplay - 1));
4146                 I915_WRITE(DSPPOS(plane), 0);
4147         }
4148         I915_WRITE(PIPESRC(pipe),
4149                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4150
4151         if (HAS_PCH_SPLIT(dev)) {
4152                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4153                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4154                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4155                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4156
4157                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4158                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4159                 }
4160         }
4161
4162         I915_WRITE(PIPECONF(pipe), pipeconf);
4163         POSTING_READ(PIPECONF(pipe));
4164
4165         intel_wait_for_vblank(dev, pipe);
4166
4167         if (IS_GEN5(dev)) {
4168                 /* enable address swizzle for tiling buffer */
4169                 temp = I915_READ(DISP_ARB_CTL);
4170                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4171         }
4172
4173         I915_WRITE(DSPCNTR(plane), dspcntr);
4174
4175         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4176
4177         intel_update_watermarks(dev);
4178
4179         drm_vblank_post_modeset(dev, pipe);
4180
4181         return ret;
4182 }
4183
4184 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4185 void intel_crtc_load_lut(struct drm_crtc *crtc)
4186 {
4187         struct drm_device *dev = crtc->dev;
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4191         int i;
4192
4193         /* The clocks have to be on to load the palette. */
4194         if (!crtc->enabled)
4195                 return;
4196
4197         /* use legacy palette for Ironlake */
4198         if (HAS_PCH_SPLIT(dev))
4199                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4200                                                    LGC_PALETTE_B;
4201
4202         for (i = 0; i < 256; i++) {
4203                 I915_WRITE(palreg + 4 * i,
4204                            (intel_crtc->lut_r[i] << 16) |
4205                            (intel_crtc->lut_g[i] << 8) |
4206                            intel_crtc->lut_b[i]);
4207         }
4208 }
4209
4210 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4211 {
4212         struct drm_device *dev = crtc->dev;
4213         struct drm_i915_private *dev_priv = dev->dev_private;
4214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4215         bool visible = base != 0;
4216         u32 cntl;
4217
4218         if (intel_crtc->cursor_visible == visible)
4219                 return;
4220
4221         cntl = I915_READ(CURACNTR);
4222         if (visible) {
4223                 /* On these chipsets we can only modify the base whilst
4224                  * the cursor is disabled.
4225                  */
4226                 I915_WRITE(CURABASE, base);
4227
4228                 cntl &= ~(CURSOR_FORMAT_MASK);
4229                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4230                 cntl |= CURSOR_ENABLE |
4231                         CURSOR_GAMMA_ENABLE |
4232                         CURSOR_FORMAT_ARGB;
4233         } else
4234                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4235         I915_WRITE(CURACNTR, cntl);
4236
4237         intel_crtc->cursor_visible = visible;
4238 }
4239
4240 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4241 {
4242         struct drm_device *dev = crtc->dev;
4243         struct drm_i915_private *dev_priv = dev->dev_private;
4244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4245         int pipe = intel_crtc->pipe;
4246         bool visible = base != 0;
4247
4248         if (intel_crtc->cursor_visible != visible) {
4249                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4250                 if (base) {
4251                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4252                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4253                         cntl |= pipe << 28; /* Connect to correct pipe */
4254                 } else {
4255                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4256                         cntl |= CURSOR_MODE_DISABLE;
4257                 }
4258                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4259
4260                 intel_crtc->cursor_visible = visible;
4261         }
4262         /* and commit changes on next vblank */
4263         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4264 }
4265
4266 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4267 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4268                                      bool on)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct drm_i915_private *dev_priv = dev->dev_private;
4272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273         int pipe = intel_crtc->pipe;
4274         int x = intel_crtc->cursor_x;
4275         int y = intel_crtc->cursor_y;
4276         u32 base, pos;
4277         bool visible;
4278
4279         pos = 0;
4280
4281         if (on && crtc->enabled && crtc->fb) {
4282                 base = intel_crtc->cursor_addr;
4283                 if (x > (int) crtc->fb->width)
4284                         base = 0;
4285
4286                 if (y > (int) crtc->fb->height)
4287                         base = 0;
4288         } else
4289                 base = 0;
4290
4291         if (x < 0) {
4292                 if (x + intel_crtc->cursor_width < 0)
4293                         base = 0;
4294
4295                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4296                 x = -x;
4297         }
4298         pos |= x << CURSOR_X_SHIFT;
4299
4300         if (y < 0) {
4301                 if (y + intel_crtc->cursor_height < 0)
4302                         base = 0;
4303
4304                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4305                 y = -y;
4306         }
4307         pos |= y << CURSOR_Y_SHIFT;
4308
4309         visible = base != 0;
4310         if (!visible && !intel_crtc->cursor_visible)
4311                 return;
4312
4313         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4314         if (IS_845G(dev) || IS_I865G(dev))
4315                 i845_update_cursor(crtc, base);
4316         else
4317                 i9xx_update_cursor(crtc, base);
4318
4319         if (visible)
4320                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4321 }
4322
4323 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4324                                  struct drm_file *file_priv,
4325                                  uint32_t handle,
4326                                  uint32_t width, uint32_t height)
4327 {
4328         struct drm_device *dev = crtc->dev;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4331         struct drm_gem_object *bo;
4332         struct drm_i915_gem_object *obj_priv;
4333         uint32_t addr;
4334         int ret;
4335
4336         DRM_DEBUG_KMS("\n");
4337
4338         /* if we want to turn off the cursor ignore width and height */
4339         if (!handle) {
4340                 DRM_DEBUG_KMS("cursor off\n");
4341                 addr = 0;
4342                 bo = NULL;
4343                 mutex_lock(&dev->struct_mutex);
4344                 goto finish;
4345         }
4346
4347         /* Currently we only support 64x64 cursors */
4348         if (width != 64 || height != 64) {
4349                 DRM_ERROR("we currently only support 64x64 cursors\n");
4350                 return -EINVAL;
4351         }
4352
4353         bo = drm_gem_object_lookup(dev, file_priv, handle);
4354         if (!bo)
4355                 return -ENOENT;
4356
4357         obj_priv = to_intel_bo(bo);
4358
4359         if (bo->size < width * height * 4) {
4360                 DRM_ERROR("buffer is to small\n");
4361                 ret = -ENOMEM;
4362                 goto fail;
4363         }
4364
4365         /* we only need to pin inside GTT if cursor is non-phy */
4366         mutex_lock(&dev->struct_mutex);
4367         if (!dev_priv->info->cursor_needs_physical) {
4368                 ret = i915_gem_object_pin(bo, PAGE_SIZE, true);
4369                 if (ret) {
4370                         DRM_ERROR("failed to pin cursor bo\n");
4371                         goto fail_locked;
4372                 }
4373
4374                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4375                 if (ret) {
4376                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4377                         goto fail_unpin;
4378                 }
4379
4380                 addr = obj_priv->gtt_offset;
4381         } else {
4382                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4383                 ret = i915_gem_attach_phys_object(dev, bo,
4384                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4385                                                   align);
4386                 if (ret) {
4387                         DRM_ERROR("failed to attach phys object\n");
4388                         goto fail_locked;
4389                 }
4390                 addr = obj_priv->phys_obj->handle->busaddr;
4391         }
4392
4393         if (IS_GEN2(dev))
4394                 I915_WRITE(CURSIZE, (height << 12) | width);
4395
4396  finish:
4397         if (intel_crtc->cursor_bo) {
4398                 if (dev_priv->info->cursor_needs_physical) {
4399                         if (intel_crtc->cursor_bo != bo)
4400                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4401                 } else
4402                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4403                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4404         }
4405
4406         mutex_unlock(&dev->struct_mutex);
4407
4408         intel_crtc->cursor_addr = addr;
4409         intel_crtc->cursor_bo = bo;
4410         intel_crtc->cursor_width = width;
4411         intel_crtc->cursor_height = height;
4412
4413         intel_crtc_update_cursor(crtc, true);
4414
4415         return 0;
4416 fail_unpin:
4417         i915_gem_object_unpin(bo);
4418 fail_locked:
4419         mutex_unlock(&dev->struct_mutex);
4420 fail:
4421         drm_gem_object_unreference_unlocked(bo);
4422         return ret;
4423 }
4424
4425 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4426 {
4427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4428
4429         intel_crtc->cursor_x = x;
4430         intel_crtc->cursor_y = y;
4431
4432         intel_crtc_update_cursor(crtc, true);
4433
4434         return 0;
4435 }
4436
4437 /** Sets the color ramps on behalf of RandR */
4438 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4439                                  u16 blue, int regno)
4440 {
4441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4442
4443         intel_crtc->lut_r[regno] = red >> 8;
4444         intel_crtc->lut_g[regno] = green >> 8;
4445         intel_crtc->lut_b[regno] = blue >> 8;
4446 }
4447
4448 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4449                              u16 *blue, int regno)
4450 {
4451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4452
4453         *red = intel_crtc->lut_r[regno] << 8;
4454         *green = intel_crtc->lut_g[regno] << 8;
4455         *blue = intel_crtc->lut_b[regno] << 8;
4456 }
4457
4458 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4459                                  u16 *blue, uint32_t start, uint32_t size)
4460 {
4461         int end = (start + size > 256) ? 256 : start + size, i;
4462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4463
4464         for (i = start; i < end; i++) {
4465                 intel_crtc->lut_r[i] = red[i] >> 8;
4466                 intel_crtc->lut_g[i] = green[i] >> 8;
4467                 intel_crtc->lut_b[i] = blue[i] >> 8;
4468         }
4469
4470         intel_crtc_load_lut(crtc);
4471 }
4472
4473 /**
4474  * Get a pipe with a simple mode set on it for doing load-based monitor
4475  * detection.
4476  *
4477  * It will be up to the load-detect code to adjust the pipe as appropriate for
4478  * its requirements.  The pipe will be connected to no other encoders.
4479  *
4480  * Currently this code will only succeed if there is a pipe with no encoders
4481  * configured for it.  In the future, it could choose to temporarily disable
4482  * some outputs to free up a pipe for its use.
4483  *
4484  * \return crtc, or NULL if no pipes are available.
4485  */
4486
4487 /* VESA 640x480x72Hz mode to set on the pipe */
4488 static struct drm_display_mode load_detect_mode = {
4489         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4490                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4491 };
4492
4493 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4494                                             struct drm_connector *connector,
4495                                             struct drm_display_mode *mode,
4496                                             int *dpms_mode)
4497 {
4498         struct intel_crtc *intel_crtc;
4499         struct drm_crtc *possible_crtc;
4500         struct drm_crtc *supported_crtc =NULL;
4501         struct drm_encoder *encoder = &intel_encoder->base;
4502         struct drm_crtc *crtc = NULL;
4503         struct drm_device *dev = encoder->dev;
4504         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4505         struct drm_crtc_helper_funcs *crtc_funcs;
4506         int i = -1;
4507
4508         /*
4509          * Algorithm gets a little messy:
4510          *   - if the connector already has an assigned crtc, use it (but make
4511          *     sure it's on first)
4512          *   - try to find the first unused crtc that can drive this connector,
4513          *     and use that if we find one
4514          *   - if there are no unused crtcs available, try to use the first
4515          *     one we found that supports the connector
4516          */
4517
4518         /* See if we already have a CRTC for this connector */
4519         if (encoder->crtc) {
4520                 crtc = encoder->crtc;
4521                 /* Make sure the crtc and connector are running */
4522                 intel_crtc = to_intel_crtc(crtc);
4523                 *dpms_mode = intel_crtc->dpms_mode;
4524                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4525                         crtc_funcs = crtc->helper_private;
4526                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4527                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4528                 }
4529                 return crtc;
4530         }
4531
4532         /* Find an unused one (if possible) */
4533         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4534                 i++;
4535                 if (!(encoder->possible_crtcs & (1 << i)))
4536                         continue;
4537                 if (!possible_crtc->enabled) {
4538                         crtc = possible_crtc;
4539                         break;
4540                 }
4541                 if (!supported_crtc)
4542                         supported_crtc = possible_crtc;
4543         }
4544
4545         /*
4546          * If we didn't find an unused CRTC, don't use any.
4547          */
4548         if (!crtc) {
4549                 return NULL;
4550         }
4551
4552         encoder->crtc = crtc;
4553         connector->encoder = encoder;
4554         intel_encoder->load_detect_temp = true;
4555
4556         intel_crtc = to_intel_crtc(crtc);
4557         *dpms_mode = intel_crtc->dpms_mode;
4558
4559         if (!crtc->enabled) {
4560                 if (!mode)
4561                         mode = &load_detect_mode;
4562                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4563         } else {
4564                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4565                         crtc_funcs = crtc->helper_private;
4566                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4567                 }
4568
4569                 /* Add this connector to the crtc */
4570                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4571                 encoder_funcs->commit(encoder);
4572         }
4573         /* let the connector get through one full cycle before testing */
4574         intel_wait_for_vblank(dev, intel_crtc->pipe);
4575
4576         return crtc;
4577 }
4578
4579 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4580                                     struct drm_connector *connector, int dpms_mode)
4581 {
4582         struct drm_encoder *encoder = &intel_encoder->base;
4583         struct drm_device *dev = encoder->dev;
4584         struct drm_crtc *crtc = encoder->crtc;
4585         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4586         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4587
4588         if (intel_encoder->load_detect_temp) {
4589                 encoder->crtc = NULL;
4590                 connector->encoder = NULL;
4591                 intel_encoder->load_detect_temp = false;
4592                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4593                 drm_helper_disable_unused_functions(dev);
4594         }
4595
4596         /* Switch crtc and encoder back off if necessary */
4597         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4598                 if (encoder->crtc == crtc)
4599                         encoder_funcs->dpms(encoder, dpms_mode);
4600                 crtc_funcs->dpms(crtc, dpms_mode);
4601         }
4602 }
4603
4604 /* Returns the clock of the currently programmed mode of the given pipe. */
4605 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4606 {
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4609         int pipe = intel_crtc->pipe;
4610         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4611         u32 fp;
4612         intel_clock_t clock;
4613
4614         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4615                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4616         else
4617                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4618
4619         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4620         if (IS_PINEVIEW(dev)) {
4621                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4622                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4623         } else {
4624                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4625                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4626         }
4627
4628         if (!IS_GEN2(dev)) {
4629                 if (IS_PINEVIEW(dev))
4630                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4631                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4632                 else
4633                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4634                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4635
4636                 switch (dpll & DPLL_MODE_MASK) {
4637                 case DPLLB_MODE_DAC_SERIAL:
4638                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4639                                 5 : 10;
4640                         break;
4641                 case DPLLB_MODE_LVDS:
4642                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4643                                 7 : 14;
4644                         break;
4645                 default:
4646                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4647                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4648                         return 0;
4649                 }
4650
4651                 /* XXX: Handle the 100Mhz refclk */
4652                 intel_clock(dev, 96000, &clock);
4653         } else {
4654                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4655
4656                 if (is_lvds) {
4657                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4658                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4659                         clock.p2 = 14;
4660
4661                         if ((dpll & PLL_REF_INPUT_MASK) ==
4662                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4663                                 /* XXX: might not be 66MHz */
4664                                 intel_clock(dev, 66000, &clock);
4665                         } else
4666                                 intel_clock(dev, 48000, &clock);
4667                 } else {
4668                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4669                                 clock.p1 = 2;
4670                         else {
4671                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4672                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4673                         }
4674                         if (dpll & PLL_P2_DIVIDE_BY_4)
4675                                 clock.p2 = 4;
4676                         else
4677                                 clock.p2 = 2;
4678
4679                         intel_clock(dev, 48000, &clock);
4680                 }
4681         }
4682
4683         /* XXX: It would be nice to validate the clocks, but we can't reuse
4684          * i830PllIsValid() because it relies on the xf86_config connector
4685          * configuration being accurate, which it isn't necessarily.
4686          */
4687
4688         return clock.dot;
4689 }
4690
4691 /** Returns the currently programmed mode of the given pipe. */
4692 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4693                                              struct drm_crtc *crtc)
4694 {
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697         int pipe = intel_crtc->pipe;
4698         struct drm_display_mode *mode;
4699         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4700         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4701         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4702         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4703
4704         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4705         if (!mode)
4706                 return NULL;
4707
4708         mode->clock = intel_crtc_clock_get(dev, crtc);
4709         mode->hdisplay = (htot & 0xffff) + 1;
4710         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4711         mode->hsync_start = (hsync & 0xffff) + 1;
4712         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4713         mode->vdisplay = (vtot & 0xffff) + 1;
4714         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4715         mode->vsync_start = (vsync & 0xffff) + 1;
4716         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4717
4718         drm_mode_set_name(mode);
4719         drm_mode_set_crtcinfo(mode, 0);
4720
4721         return mode;
4722 }
4723
4724 #define GPU_IDLE_TIMEOUT 500 /* ms */
4725
4726 /* When this timer fires, we've been idle for awhile */
4727 static void intel_gpu_idle_timer(unsigned long arg)
4728 {
4729         struct drm_device *dev = (struct drm_device *)arg;
4730         drm_i915_private_t *dev_priv = dev->dev_private;
4731
4732         dev_priv->busy = false;
4733
4734         queue_work(dev_priv->wq, &dev_priv->idle_work);
4735 }
4736
4737 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4738
4739 static void intel_crtc_idle_timer(unsigned long arg)
4740 {
4741         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4742         struct drm_crtc *crtc = &intel_crtc->base;
4743         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4744
4745         intel_crtc->busy = false;
4746
4747         queue_work(dev_priv->wq, &dev_priv->idle_work);
4748 }
4749
4750 static void intel_increase_pllclock(struct drm_crtc *crtc)
4751 {
4752         struct drm_device *dev = crtc->dev;
4753         drm_i915_private_t *dev_priv = dev->dev_private;
4754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4755         int pipe = intel_crtc->pipe;
4756         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4757         int dpll = I915_READ(dpll_reg);
4758
4759         if (HAS_PCH_SPLIT(dev))
4760                 return;
4761
4762         if (!dev_priv->lvds_downclock_avail)
4763                 return;
4764
4765         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4766                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4767
4768                 /* Unlock panel regs */
4769                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4770                            PANEL_UNLOCK_REGS);
4771
4772                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4773                 I915_WRITE(dpll_reg, dpll);
4774                 dpll = I915_READ(dpll_reg);
4775                 intel_wait_for_vblank(dev, pipe);
4776                 dpll = I915_READ(dpll_reg);
4777                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4778                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4779
4780                 /* ...and lock them again */
4781                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4782         }
4783
4784         /* Schedule downclock */
4785         mod_timer(&intel_crtc->idle_timer, jiffies +
4786                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4787 }
4788
4789 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4790 {
4791         struct drm_device *dev = crtc->dev;
4792         drm_i915_private_t *dev_priv = dev->dev_private;
4793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794         int pipe = intel_crtc->pipe;
4795         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4796         int dpll = I915_READ(dpll_reg);
4797
4798         if (HAS_PCH_SPLIT(dev))
4799                 return;
4800
4801         if (!dev_priv->lvds_downclock_avail)
4802                 return;
4803
4804         /*
4805          * Since this is called by a timer, we should never get here in
4806          * the manual case.
4807          */
4808         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4809                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4810
4811                 /* Unlock panel regs */
4812                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4813                            PANEL_UNLOCK_REGS);
4814
4815                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4816                 I915_WRITE(dpll_reg, dpll);
4817                 dpll = I915_READ(dpll_reg);
4818                 intel_wait_for_vblank(dev, pipe);
4819                 dpll = I915_READ(dpll_reg);
4820                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4821                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4822
4823                 /* ...and lock them again */
4824                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4825         }
4826
4827 }
4828
4829 /**
4830  * intel_idle_update - adjust clocks for idleness
4831  * @work: work struct
4832  *
4833  * Either the GPU or display (or both) went idle.  Check the busy status
4834  * here and adjust the CRTC and GPU clocks as necessary.
4835  */
4836 static void intel_idle_update(struct work_struct *work)
4837 {
4838         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4839                                                     idle_work);
4840         struct drm_device *dev = dev_priv->dev;
4841         struct drm_crtc *crtc;
4842         struct intel_crtc *intel_crtc;
4843         int enabled = 0;
4844
4845         if (!i915_powersave)
4846                 return;
4847
4848         mutex_lock(&dev->struct_mutex);
4849
4850         i915_update_gfx_val(dev_priv);
4851
4852         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4853                 /* Skip inactive CRTCs */
4854                 if (!crtc->fb)
4855                         continue;
4856
4857                 enabled++;
4858                 intel_crtc = to_intel_crtc(crtc);
4859                 if (!intel_crtc->busy)
4860                         intel_decrease_pllclock(crtc);
4861         }
4862
4863         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4864                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4865                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4866         }
4867
4868         mutex_unlock(&dev->struct_mutex);
4869 }
4870
4871 /**
4872  * intel_mark_busy - mark the GPU and possibly the display busy
4873  * @dev: drm device
4874  * @obj: object we're operating on
4875  *
4876  * Callers can use this function to indicate that the GPU is busy processing
4877  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4878  * buffer), we'll also mark the display as busy, so we know to increase its
4879  * clock frequency.
4880  */
4881 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4882 {
4883         drm_i915_private_t *dev_priv = dev->dev_private;
4884         struct drm_crtc *crtc = NULL;
4885         struct intel_framebuffer *intel_fb;
4886         struct intel_crtc *intel_crtc;
4887
4888         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4889                 return;
4890
4891         if (!dev_priv->busy) {
4892                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4893                         u32 fw_blc_self;
4894
4895                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4896                         fw_blc_self = I915_READ(FW_BLC_SELF);
4897                         fw_blc_self &= ~FW_BLC_SELF_EN;
4898                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4899                 }
4900                 dev_priv->busy = true;
4901         } else
4902                 mod_timer(&dev_priv->idle_timer, jiffies +
4903                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4904
4905         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4906                 if (!crtc->fb)
4907                         continue;
4908
4909                 intel_crtc = to_intel_crtc(crtc);
4910                 intel_fb = to_intel_framebuffer(crtc->fb);
4911                 if (intel_fb->obj == obj) {
4912                         if (!intel_crtc->busy) {
4913                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4914                                         u32 fw_blc_self;
4915
4916                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4917                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4918                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4919                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4920                                 }
4921                                 /* Non-busy -> busy, upclock */
4922                                 intel_increase_pllclock(crtc);
4923                                 intel_crtc->busy = true;
4924                         } else {
4925                                 /* Busy -> busy, put off timer */
4926                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4927                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4928                         }
4929                 }
4930         }
4931 }
4932
4933 static void intel_crtc_destroy(struct drm_crtc *crtc)
4934 {
4935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4936         struct drm_device *dev = crtc->dev;
4937         struct intel_unpin_work *work;
4938         unsigned long flags;
4939
4940         spin_lock_irqsave(&dev->event_lock, flags);
4941         work = intel_crtc->unpin_work;
4942         intel_crtc->unpin_work = NULL;
4943         spin_unlock_irqrestore(&dev->event_lock, flags);
4944
4945         if (work) {
4946                 cancel_work_sync(&work->work);
4947                 kfree(work);
4948         }
4949
4950         drm_crtc_cleanup(crtc);
4951
4952         kfree(intel_crtc);
4953 }
4954
4955 static void intel_unpin_work_fn(struct work_struct *__work)
4956 {
4957         struct intel_unpin_work *work =
4958                 container_of(__work, struct intel_unpin_work, work);
4959
4960         mutex_lock(&work->dev->struct_mutex);
4961         i915_gem_object_unpin(work->old_fb_obj);
4962         drm_gem_object_unreference(work->pending_flip_obj);
4963         drm_gem_object_unreference(work->old_fb_obj);
4964         mutex_unlock(&work->dev->struct_mutex);
4965         kfree(work);
4966 }
4967
4968 static void do_intel_finish_page_flip(struct drm_device *dev,
4969                                       struct drm_crtc *crtc)
4970 {
4971         drm_i915_private_t *dev_priv = dev->dev_private;
4972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4973         struct intel_unpin_work *work;
4974         struct drm_i915_gem_object *obj_priv;
4975         struct drm_pending_vblank_event *e;
4976         struct timeval now;
4977         unsigned long flags;
4978
4979         /* Ignore early vblank irqs */
4980         if (intel_crtc == NULL)
4981                 return;
4982
4983         spin_lock_irqsave(&dev->event_lock, flags);
4984         work = intel_crtc->unpin_work;
4985         if (work == NULL || !work->pending) {
4986                 spin_unlock_irqrestore(&dev->event_lock, flags);
4987                 return;
4988         }
4989
4990         intel_crtc->unpin_work = NULL;
4991         drm_vblank_put(dev, intel_crtc->pipe);
4992
4993         if (work->event) {
4994                 e = work->event;
4995                 do_gettimeofday(&now);
4996                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4997                 e->event.tv_sec = now.tv_sec;
4998                 e->event.tv_usec = now.tv_usec;
4999                 list_add_tail(&e->base.link,
5000                               &e->base.file_priv->event_list);
5001                 wake_up_interruptible(&e->base.file_priv->event_wait);
5002         }
5003
5004         spin_unlock_irqrestore(&dev->event_lock, flags);
5005
5006         obj_priv = to_intel_bo(work->old_fb_obj);
5007         atomic_clear_mask(1 << intel_crtc->plane,
5008                           &obj_priv->pending_flip.counter);
5009         if (atomic_read(&obj_priv->pending_flip) == 0)
5010                 wake_up(&dev_priv->pending_flip_queue);
5011         schedule_work(&work->work);
5012
5013         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5014 }
5015
5016 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5017 {
5018         drm_i915_private_t *dev_priv = dev->dev_private;
5019         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5020
5021         do_intel_finish_page_flip(dev, crtc);
5022 }
5023
5024 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5025 {
5026         drm_i915_private_t *dev_priv = dev->dev_private;
5027         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5028
5029         do_intel_finish_page_flip(dev, crtc);
5030 }
5031
5032 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5033 {
5034         drm_i915_private_t *dev_priv = dev->dev_private;
5035         struct intel_crtc *intel_crtc =
5036                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5037         unsigned long flags;
5038
5039         spin_lock_irqsave(&dev->event_lock, flags);
5040         if (intel_crtc->unpin_work) {
5041                 if ((++intel_crtc->unpin_work->pending) > 1)
5042                         DRM_ERROR("Prepared flip multiple times\n");
5043         } else {
5044                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5045         }
5046         spin_unlock_irqrestore(&dev->event_lock, flags);
5047 }
5048
5049 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5050                                 struct drm_framebuffer *fb,
5051                                 struct drm_pending_vblank_event *event)
5052 {
5053         struct drm_device *dev = crtc->dev;
5054         struct drm_i915_private *dev_priv = dev->dev_private;
5055         struct intel_framebuffer *intel_fb;
5056         struct drm_i915_gem_object *obj_priv;
5057         struct drm_gem_object *obj;
5058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059         struct intel_unpin_work *work;
5060         unsigned long flags, offset;
5061         int pipe = intel_crtc->pipe;
5062         u32 pf, pipesrc;
5063         int ret;
5064
5065         work = kzalloc(sizeof *work, GFP_KERNEL);
5066         if (work == NULL)
5067                 return -ENOMEM;
5068
5069         work->event = event;
5070         work->dev = crtc->dev;
5071         intel_fb = to_intel_framebuffer(crtc->fb);
5072         work->old_fb_obj = intel_fb->obj;
5073         INIT_WORK(&work->work, intel_unpin_work_fn);
5074
5075         /* We borrow the event spin lock for protecting unpin_work */
5076         spin_lock_irqsave(&dev->event_lock, flags);
5077         if (intel_crtc->unpin_work) {
5078                 spin_unlock_irqrestore(&dev->event_lock, flags);
5079                 kfree(work);
5080
5081                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5082                 return -EBUSY;
5083         }
5084         intel_crtc->unpin_work = work;
5085         spin_unlock_irqrestore(&dev->event_lock, flags);
5086
5087         intel_fb = to_intel_framebuffer(fb);
5088         obj = intel_fb->obj;
5089
5090         mutex_lock(&dev->struct_mutex);
5091         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5092         if (ret)
5093                 goto cleanup_work;
5094
5095         /* Reference the objects for the scheduled work. */
5096         drm_gem_object_reference(work->old_fb_obj);
5097         drm_gem_object_reference(obj);
5098
5099         crtc->fb = fb;
5100
5101         ret = drm_vblank_get(dev, intel_crtc->pipe);
5102         if (ret)
5103                 goto cleanup_objs;
5104
5105         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5106                 u32 flip_mask;
5107
5108                 /* Can't queue multiple flips, so wait for the previous
5109                  * one to finish before executing the next.
5110                  */
5111                 ret = BEGIN_LP_RING(2);
5112                 if (ret)
5113                         goto cleanup_objs;
5114
5115                 if (intel_crtc->plane)
5116                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5117                 else
5118                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5119                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5120                 OUT_RING(MI_NOOP);
5121                 ADVANCE_LP_RING();
5122         }
5123
5124         work->pending_flip_obj = obj;
5125         obj_priv = to_intel_bo(obj);
5126
5127         work->enable_stall_check = true;
5128
5129         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5130         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5131
5132         ret = BEGIN_LP_RING(4);
5133         if (ret)
5134                 goto cleanup_objs;
5135
5136         /* Block clients from rendering to the new back buffer until
5137          * the flip occurs and the object is no longer visible.
5138          */
5139         atomic_add(1 << intel_crtc->plane,
5140                    &to_intel_bo(work->old_fb_obj)->pending_flip);
5141
5142         switch (INTEL_INFO(dev)->gen) {
5143         case 2:
5144                 OUT_RING(MI_DISPLAY_FLIP |
5145                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5146                 OUT_RING(fb->pitch);
5147                 OUT_RING(obj_priv->gtt_offset + offset);
5148                 OUT_RING(MI_NOOP);
5149                 break;
5150
5151         case 3:
5152                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5153                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5154                 OUT_RING(fb->pitch);
5155                 OUT_RING(obj_priv->gtt_offset + offset);
5156                 OUT_RING(MI_NOOP);
5157                 break;
5158
5159         case 4:
5160         case 5:
5161                 /* i965+ uses the linear or tiled offsets from the
5162                  * Display Registers (which do not change across a page-flip)
5163                  * so we need only reprogram the base address.
5164                  */
5165                 OUT_RING(MI_DISPLAY_FLIP |
5166                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5167                 OUT_RING(fb->pitch);
5168                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5169
5170                 /* XXX Enabling the panel-fitter across page-flip is so far
5171                  * untested on non-native modes, so ignore it for now.
5172                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5173                  */
5174                 pf = 0;
5175                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5176                 OUT_RING(pf | pipesrc);
5177                 break;
5178
5179         case 6:
5180                 OUT_RING(MI_DISPLAY_FLIP |
5181                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5182                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5183                 OUT_RING(obj_priv->gtt_offset);
5184
5185                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5186                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5187                 OUT_RING(pf | pipesrc);
5188                 break;
5189         }
5190         ADVANCE_LP_RING();
5191
5192         mutex_unlock(&dev->struct_mutex);
5193
5194         trace_i915_flip_request(intel_crtc->plane, obj);
5195
5196         return 0;
5197
5198 cleanup_objs:
5199         drm_gem_object_unreference(work->old_fb_obj);
5200         drm_gem_object_unreference(obj);
5201 cleanup_work:
5202         mutex_unlock(&dev->struct_mutex);
5203
5204         spin_lock_irqsave(&dev->event_lock, flags);
5205         intel_crtc->unpin_work = NULL;
5206         spin_unlock_irqrestore(&dev->event_lock, flags);
5207
5208         kfree(work);
5209
5210         return ret;
5211 }
5212
5213 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5214         .dpms = intel_crtc_dpms,
5215         .mode_fixup = intel_crtc_mode_fixup,
5216         .mode_set = intel_crtc_mode_set,
5217         .mode_set_base = intel_pipe_set_base,
5218         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5219         .load_lut = intel_crtc_load_lut,
5220         .disable = intel_crtc_disable,
5221 };
5222
5223 static const struct drm_crtc_funcs intel_crtc_funcs = {
5224         .cursor_set = intel_crtc_cursor_set,
5225         .cursor_move = intel_crtc_cursor_move,
5226         .gamma_set = intel_crtc_gamma_set,
5227         .set_config = drm_crtc_helper_set_config,
5228         .destroy = intel_crtc_destroy,
5229         .page_flip = intel_crtc_page_flip,
5230 };
5231
5232
5233 static void intel_crtc_init(struct drm_device *dev, int pipe)
5234 {
5235         drm_i915_private_t *dev_priv = dev->dev_private;
5236         struct intel_crtc *intel_crtc;
5237         int i;
5238
5239         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5240         if (intel_crtc == NULL)
5241                 return;
5242
5243         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5244
5245         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5246         for (i = 0; i < 256; i++) {
5247                 intel_crtc->lut_r[i] = i;
5248                 intel_crtc->lut_g[i] = i;
5249                 intel_crtc->lut_b[i] = i;
5250         }
5251
5252         /* Swap pipes & planes for FBC on pre-965 */
5253         intel_crtc->pipe = pipe;
5254         intel_crtc->plane = pipe;
5255         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5256                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5257                 intel_crtc->plane = !pipe;
5258         }
5259
5260         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5261                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5262         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5263         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5264
5265         intel_crtc->cursor_addr = 0;
5266         intel_crtc->dpms_mode = -1;
5267         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5268
5269         if (HAS_PCH_SPLIT(dev)) {
5270                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5271                 intel_helper_funcs.commit = ironlake_crtc_commit;
5272         } else {
5273                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5274                 intel_helper_funcs.commit = i9xx_crtc_commit;
5275         }
5276
5277         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5278
5279         intel_crtc->busy = false;
5280
5281         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5282                     (unsigned long)intel_crtc);
5283 }
5284
5285 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5286                                 struct drm_file *file_priv)
5287 {
5288         drm_i915_private_t *dev_priv = dev->dev_private;
5289         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5290         struct drm_mode_object *drmmode_obj;
5291         struct intel_crtc *crtc;
5292
5293         if (!dev_priv) {
5294                 DRM_ERROR("called with no initialization\n");
5295                 return -EINVAL;
5296         }
5297
5298         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5299                         DRM_MODE_OBJECT_CRTC);
5300
5301         if (!drmmode_obj) {
5302                 DRM_ERROR("no such CRTC id\n");
5303                 return -EINVAL;
5304         }
5305
5306         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5307         pipe_from_crtc_id->pipe = crtc->pipe;
5308
5309         return 0;
5310 }
5311
5312 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5313 {
5314         struct intel_encoder *encoder;
5315         int index_mask = 0;
5316         int entry = 0;
5317
5318         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5319                 if (type_mask & encoder->clone_mask)
5320                         index_mask |= (1 << entry);
5321                 entry++;
5322         }
5323
5324         return index_mask;
5325 }
5326
5327 static void intel_setup_outputs(struct drm_device *dev)
5328 {
5329         struct drm_i915_private *dev_priv = dev->dev_private;
5330         struct intel_encoder *encoder;
5331         bool dpd_is_edp = false;
5332
5333         if (IS_MOBILE(dev) && !IS_I830(dev))
5334                 intel_lvds_init(dev);
5335
5336         if (HAS_PCH_SPLIT(dev)) {
5337                 dpd_is_edp = intel_dpd_is_edp(dev);
5338
5339                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5340                         intel_dp_init(dev, DP_A);
5341
5342                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5343                         intel_dp_init(dev, PCH_DP_D);
5344         }
5345
5346         intel_crt_init(dev);
5347
5348         if (HAS_PCH_SPLIT(dev)) {
5349                 int found;
5350
5351                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5352                         /* PCH SDVOB multiplex with HDMIB */
5353                         found = intel_sdvo_init(dev, PCH_SDVOB);
5354                         if (!found)
5355                                 intel_hdmi_init(dev, HDMIB);
5356                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5357                                 intel_dp_init(dev, PCH_DP_B);
5358                 }
5359
5360                 if (I915_READ(HDMIC) & PORT_DETECTED)
5361                         intel_hdmi_init(dev, HDMIC);
5362
5363                 if (I915_READ(HDMID) & PORT_DETECTED)
5364                         intel_hdmi_init(dev, HDMID);
5365
5366                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5367                         intel_dp_init(dev, PCH_DP_C);
5368
5369                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5370                         intel_dp_init(dev, PCH_DP_D);
5371
5372         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5373                 bool found = false;
5374
5375                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5376                         DRM_DEBUG_KMS("probing SDVOB\n");
5377                         found = intel_sdvo_init(dev, SDVOB);
5378                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5379                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5380                                 intel_hdmi_init(dev, SDVOB);
5381                         }
5382
5383                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5384                                 DRM_DEBUG_KMS("probing DP_B\n");
5385                                 intel_dp_init(dev, DP_B);
5386                         }
5387                 }
5388
5389                 /* Before G4X SDVOC doesn't have its own detect register */
5390
5391                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5392                         DRM_DEBUG_KMS("probing SDVOC\n");
5393                         found = intel_sdvo_init(dev, SDVOC);
5394                 }
5395
5396                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5397
5398                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5399                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5400                                 intel_hdmi_init(dev, SDVOC);
5401                         }
5402                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5403                                 DRM_DEBUG_KMS("probing DP_C\n");
5404                                 intel_dp_init(dev, DP_C);
5405                         }
5406                 }
5407
5408                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5409                     (I915_READ(DP_D) & DP_DETECTED)) {
5410                         DRM_DEBUG_KMS("probing DP_D\n");
5411                         intel_dp_init(dev, DP_D);
5412                 }
5413         } else if (IS_GEN2(dev))
5414                 intel_dvo_init(dev);
5415
5416         if (SUPPORTS_TV(dev))
5417                 intel_tv_init(dev);
5418
5419         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5420                 encoder->base.possible_crtcs = encoder->crtc_mask;
5421                 encoder->base.possible_clones =
5422                         intel_encoder_clones(dev, encoder->clone_mask);
5423         }
5424 }
5425
5426 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5427 {
5428         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5429
5430         drm_framebuffer_cleanup(fb);
5431         drm_gem_object_unreference_unlocked(intel_fb->obj);
5432
5433         kfree(intel_fb);
5434 }
5435
5436 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5437                                                 struct drm_file *file_priv,
5438                                                 unsigned int *handle)
5439 {
5440         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5441         struct drm_gem_object *object = intel_fb->obj;
5442
5443         return drm_gem_handle_create(file_priv, object, handle);
5444 }
5445
5446 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5447         .destroy = intel_user_framebuffer_destroy,
5448         .create_handle = intel_user_framebuffer_create_handle,
5449 };
5450
5451 int intel_framebuffer_init(struct drm_device *dev,
5452                            struct intel_framebuffer *intel_fb,
5453                            struct drm_mode_fb_cmd *mode_cmd,
5454                            struct drm_gem_object *obj)
5455 {
5456         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5457         int ret;
5458
5459         if (obj_priv->tiling_mode == I915_TILING_Y)
5460                 return -EINVAL;
5461
5462         if (mode_cmd->pitch & 63)
5463                 return -EINVAL;
5464
5465         switch (mode_cmd->bpp) {
5466         case 8:
5467         case 16:
5468         case 24:
5469         case 32:
5470                 break;
5471         default:
5472                 return -EINVAL;
5473         }
5474
5475         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5476         if (ret) {
5477                 DRM_ERROR("framebuffer init failed %d\n", ret);
5478                 return ret;
5479         }
5480
5481         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5482         intel_fb->obj = obj;
5483         return 0;
5484 }
5485
5486 static struct drm_framebuffer *
5487 intel_user_framebuffer_create(struct drm_device *dev,
5488                               struct drm_file *filp,
5489                               struct drm_mode_fb_cmd *mode_cmd)
5490 {
5491         struct drm_gem_object *obj;
5492         struct intel_framebuffer *intel_fb;
5493         int ret;
5494
5495         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5496         if (!obj)
5497                 return ERR_PTR(-ENOENT);
5498
5499         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5500         if (!intel_fb)
5501                 return ERR_PTR(-ENOMEM);
5502
5503         ret = intel_framebuffer_init(dev, intel_fb,
5504                                      mode_cmd, obj);
5505         if (ret) {
5506                 drm_gem_object_unreference_unlocked(obj);
5507                 kfree(intel_fb);
5508                 return ERR_PTR(ret);
5509         }
5510
5511         return &intel_fb->base;
5512 }
5513
5514 static const struct drm_mode_config_funcs intel_mode_funcs = {
5515         .fb_create = intel_user_framebuffer_create,
5516         .output_poll_changed = intel_fb_output_poll_changed,
5517 };
5518
5519 static struct drm_gem_object *
5520 intel_alloc_context_page(struct drm_device *dev)
5521 {
5522         struct drm_gem_object *ctx;
5523         int ret;
5524
5525         ctx = i915_gem_alloc_object(dev, 4096);
5526         if (!ctx) {
5527                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5528                 return NULL;
5529         }
5530
5531         mutex_lock(&dev->struct_mutex);
5532         ret = i915_gem_object_pin(ctx, 4096, true);
5533         if (ret) {
5534                 DRM_ERROR("failed to pin power context: %d\n", ret);
5535                 goto err_unref;
5536         }
5537
5538         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5539         if (ret) {
5540                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5541                 goto err_unpin;
5542         }
5543         mutex_unlock(&dev->struct_mutex);
5544
5545         return ctx;
5546
5547 err_unpin:
5548         i915_gem_object_unpin(ctx);
5549 err_unref:
5550         drm_gem_object_unreference(ctx);
5551         mutex_unlock(&dev->struct_mutex);
5552         return NULL;
5553 }
5554
5555 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5556 {
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         u16 rgvswctl;
5559
5560         rgvswctl = I915_READ16(MEMSWCTL);
5561         if (rgvswctl & MEMCTL_CMD_STS) {
5562                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5563                 return false; /* still busy with another command */
5564         }
5565
5566         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5567                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5568         I915_WRITE16(MEMSWCTL, rgvswctl);
5569         POSTING_READ16(MEMSWCTL);
5570
5571         rgvswctl |= MEMCTL_CMD_STS;
5572         I915_WRITE16(MEMSWCTL, rgvswctl);
5573
5574         return true;
5575 }
5576
5577 void ironlake_enable_drps(struct drm_device *dev)
5578 {
5579         struct drm_i915_private *dev_priv = dev->dev_private;
5580         u32 rgvmodectl = I915_READ(MEMMODECTL);
5581         u8 fmax, fmin, fstart, vstart;
5582
5583         /* Enable temp reporting */
5584         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5585         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5586
5587         /* 100ms RC evaluation intervals */
5588         I915_WRITE(RCUPEI, 100000);
5589         I915_WRITE(RCDNEI, 100000);
5590
5591         /* Set max/min thresholds to 90ms and 80ms respectively */
5592         I915_WRITE(RCBMAXAVG, 90000);
5593         I915_WRITE(RCBMINAVG, 80000);
5594
5595         I915_WRITE(MEMIHYST, 1);
5596
5597         /* Set up min, max, and cur for interrupt handling */
5598         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5599         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5600         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5601                 MEMMODE_FSTART_SHIFT;
5602
5603         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5604                 PXVFREQ_PX_SHIFT;
5605
5606         dev_priv->fmax = fmax; /* IPS callback will increase this */
5607         dev_priv->fstart = fstart;
5608
5609         dev_priv->max_delay = fstart;
5610         dev_priv->min_delay = fmin;
5611         dev_priv->cur_delay = fstart;
5612
5613         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5614                          fmax, fmin, fstart);
5615
5616         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5617
5618         /*
5619          * Interrupts will be enabled in ironlake_irq_postinstall
5620          */
5621
5622         I915_WRITE(VIDSTART, vstart);
5623         POSTING_READ(VIDSTART);
5624
5625         rgvmodectl |= MEMMODE_SWMODE_EN;
5626         I915_WRITE(MEMMODECTL, rgvmodectl);
5627
5628         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5629                 DRM_ERROR("stuck trying to change perf mode\n");
5630         msleep(1);
5631
5632         ironlake_set_drps(dev, fstart);
5633
5634         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5635                 I915_READ(0x112e0);
5636         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5637         dev_priv->last_count2 = I915_READ(0x112f4);
5638         getrawmonotonic(&dev_priv->last_time2);
5639 }
5640
5641 void ironlake_disable_drps(struct drm_device *dev)
5642 {
5643         struct drm_i915_private *dev_priv = dev->dev_private;
5644         u16 rgvswctl = I915_READ16(MEMSWCTL);
5645
5646         /* Ack interrupts, disable EFC interrupt */
5647         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5648         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5649         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5650         I915_WRITE(DEIIR, DE_PCU_EVENT);
5651         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5652
5653         /* Go back to the starting frequency */
5654         ironlake_set_drps(dev, dev_priv->fstart);
5655         msleep(1);
5656         rgvswctl |= MEMCTL_CMD_STS;
5657         I915_WRITE(MEMSWCTL, rgvswctl);
5658         msleep(1);
5659
5660 }
5661
5662 static unsigned long intel_pxfreq(u32 vidfreq)
5663 {
5664         unsigned long freq;
5665         int div = (vidfreq & 0x3f0000) >> 16;
5666         int post = (vidfreq & 0x3000) >> 12;
5667         int pre = (vidfreq & 0x7);
5668
5669         if (!pre)
5670                 return 0;
5671
5672         freq = ((div * 133333) / ((1<<post) * pre));
5673
5674         return freq;
5675 }
5676
5677 void intel_init_emon(struct drm_device *dev)
5678 {
5679         struct drm_i915_private *dev_priv = dev->dev_private;
5680         u32 lcfuse;
5681         u8 pxw[16];
5682         int i;
5683
5684         /* Disable to program */
5685         I915_WRITE(ECR, 0);
5686         POSTING_READ(ECR);
5687
5688         /* Program energy weights for various events */
5689         I915_WRITE(SDEW, 0x15040d00);
5690         I915_WRITE(CSIEW0, 0x007f0000);
5691         I915_WRITE(CSIEW1, 0x1e220004);
5692         I915_WRITE(CSIEW2, 0x04000004);
5693
5694         for (i = 0; i < 5; i++)
5695                 I915_WRITE(PEW + (i * 4), 0);
5696         for (i = 0; i < 3; i++)
5697                 I915_WRITE(DEW + (i * 4), 0);
5698
5699         /* Program P-state weights to account for frequency power adjustment */
5700         for (i = 0; i < 16; i++) {
5701                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5702                 unsigned long freq = intel_pxfreq(pxvidfreq);
5703                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5704                         PXVFREQ_PX_SHIFT;
5705                 unsigned long val;
5706
5707                 val = vid * vid;
5708                 val *= (freq / 1000);
5709                 val *= 255;
5710                 val /= (127*127*900);
5711                 if (val > 0xff)
5712                         DRM_ERROR("bad pxval: %ld\n", val);
5713                 pxw[i] = val;
5714         }
5715         /* Render standby states get 0 weight */
5716         pxw[14] = 0;
5717         pxw[15] = 0;
5718
5719         for (i = 0; i < 4; i++) {
5720                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5721                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5722                 I915_WRITE(PXW + (i * 4), val);
5723         }
5724
5725         /* Adjust magic regs to magic values (more experimental results) */
5726         I915_WRITE(OGW0, 0);
5727         I915_WRITE(OGW1, 0);
5728         I915_WRITE(EG0, 0x00007f00);
5729         I915_WRITE(EG1, 0x0000000e);
5730         I915_WRITE(EG2, 0x000e0000);
5731         I915_WRITE(EG3, 0x68000300);
5732         I915_WRITE(EG4, 0x42000000);
5733         I915_WRITE(EG5, 0x00140031);
5734         I915_WRITE(EG6, 0);
5735         I915_WRITE(EG7, 0);
5736
5737         for (i = 0; i < 8; i++)
5738                 I915_WRITE(PXWL + (i * 4), 0);
5739
5740         /* Enable PMON + select events */
5741         I915_WRITE(ECR, 0x80000019);
5742
5743         lcfuse = I915_READ(LCFUSE02);
5744
5745         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5746 }
5747
5748 void intel_init_clock_gating(struct drm_device *dev)
5749 {
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751
5752         /*
5753          * Disable clock gating reported to work incorrectly according to the
5754          * specs, but enable as much else as we can.
5755          */
5756         if (HAS_PCH_SPLIT(dev)) {
5757                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5758
5759                 if (IS_GEN5(dev)) {
5760                         /* Required for FBC */
5761                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5762                         /* Required for CxSR */
5763                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5764
5765                         I915_WRITE(PCH_3DCGDIS0,
5766                                    MARIUNIT_CLOCK_GATE_DISABLE |
5767                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5768                 }
5769
5770                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5771
5772                 /*
5773                  * On Ibex Peak and Cougar Point, we need to disable clock
5774                  * gating for the panel power sequencer or it will fail to
5775                  * start up when no ports are active.
5776                  */
5777                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5778
5779                 /*
5780                  * According to the spec the following bits should be set in
5781                  * order to enable memory self-refresh
5782                  * The bit 22/21 of 0x42004
5783                  * The bit 5 of 0x42020
5784                  * The bit 15 of 0x45000
5785                  */
5786                 if (IS_GEN5(dev)) {
5787                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5788                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5789                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5790                         I915_WRITE(ILK_DSPCLK_GATE,
5791                                         (I915_READ(ILK_DSPCLK_GATE) |
5792                                                 ILK_DPARB_CLK_GATE));
5793                         I915_WRITE(DISP_ARB_CTL,
5794                                         (I915_READ(DISP_ARB_CTL) |
5795                                                 DISP_FBC_WM_DIS));
5796                 I915_WRITE(WM3_LP_ILK, 0);
5797                 I915_WRITE(WM2_LP_ILK, 0);
5798                 I915_WRITE(WM1_LP_ILK, 0);
5799                 }
5800                 /*
5801                  * Based on the document from hardware guys the following bits
5802                  * should be set unconditionally in order to enable FBC.
5803                  * The bit 22 of 0x42000
5804                  * The bit 22 of 0x42004
5805                  * The bit 7,8,9 of 0x42020.
5806                  */
5807                 if (IS_IRONLAKE_M(dev)) {
5808                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5809                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5810                                    ILK_FBCQ_DIS);
5811                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5812                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5813                                    ILK_DPARB_GATE);
5814                         I915_WRITE(ILK_DSPCLK_GATE,
5815                                    I915_READ(ILK_DSPCLK_GATE) |
5816                                    ILK_DPFC_DIS1 |
5817                                    ILK_DPFC_DIS2 |
5818                                    ILK_CLK_FBC);
5819                 }
5820
5821                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5822                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5823                            ILK_ELPIN_409_SELECT);
5824
5825                 if (IS_GEN5(dev)) {
5826                         I915_WRITE(_3D_CHICKEN2,
5827                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5828                                    _3D_CHICKEN2_WM_READ_PIPELINED);
5829                 }
5830                 return;
5831         } else if (IS_G4X(dev)) {
5832                 uint32_t dspclk_gate;
5833                 I915_WRITE(RENCLK_GATE_D1, 0);
5834                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5835                        GS_UNIT_CLOCK_GATE_DISABLE |
5836                        CL_UNIT_CLOCK_GATE_DISABLE);
5837                 I915_WRITE(RAMCLK_GATE_D, 0);
5838                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5839                         OVRUNIT_CLOCK_GATE_DISABLE |
5840                         OVCUNIT_CLOCK_GATE_DISABLE;
5841                 if (IS_GM45(dev))
5842                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5843                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5844         } else if (IS_CRESTLINE(dev)) {
5845                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5846                 I915_WRITE(RENCLK_GATE_D2, 0);
5847                 I915_WRITE(DSPCLK_GATE_D, 0);
5848                 I915_WRITE(RAMCLK_GATE_D, 0);
5849                 I915_WRITE16(DEUC, 0);
5850         } else if (IS_BROADWATER(dev)) {
5851                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5852                        I965_RCC_CLOCK_GATE_DISABLE |
5853                        I965_RCPB_CLOCK_GATE_DISABLE |
5854                        I965_ISC_CLOCK_GATE_DISABLE |
5855                        I965_FBC_CLOCK_GATE_DISABLE);
5856                 I915_WRITE(RENCLK_GATE_D2, 0);
5857         } else if (IS_GEN3(dev)) {
5858                 u32 dstate = I915_READ(D_STATE);
5859
5860                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5861                         DSTATE_DOT_CLOCK_GATING;
5862                 I915_WRITE(D_STATE, dstate);
5863         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5864                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5865         } else if (IS_I830(dev)) {
5866                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5867         }
5868
5869         /*
5870          * GPU can automatically power down the render unit if given a page
5871          * to save state.
5872          */
5873         if (IS_IRONLAKE_M(dev)) {
5874                 if (dev_priv->renderctx == NULL)
5875                         dev_priv->renderctx = intel_alloc_context_page(dev);
5876                 if (dev_priv->renderctx) {
5877                         struct drm_i915_gem_object *obj_priv;
5878                         obj_priv = to_intel_bo(dev_priv->renderctx);
5879                         if (obj_priv) {
5880                                 if (BEGIN_LP_RING(4) == 0) {
5881                                         OUT_RING(MI_SET_CONTEXT);
5882                                         OUT_RING(obj_priv->gtt_offset |
5883                                                  MI_MM_SPACE_GTT |
5884                                                  MI_SAVE_EXT_STATE_EN |
5885                                                  MI_RESTORE_EXT_STATE_EN |
5886                                                  MI_RESTORE_INHIBIT);
5887                                         OUT_RING(MI_NOOP);
5888                                         OUT_RING(MI_FLUSH);
5889                                         ADVANCE_LP_RING();
5890                                 }
5891                         }
5892                 } else
5893                         DRM_DEBUG_KMS("Failed to allocate render context."
5894                                        "Disable RC6\n");
5895         }
5896
5897         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5898                 struct drm_i915_gem_object *obj_priv = NULL;
5899
5900                 if (dev_priv->pwrctx) {
5901                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5902                 } else {
5903                         struct drm_gem_object *pwrctx;
5904
5905                         pwrctx = intel_alloc_context_page(dev);
5906                         if (pwrctx) {
5907                                 dev_priv->pwrctx = pwrctx;
5908                                 obj_priv = to_intel_bo(pwrctx);
5909                         }
5910                 }
5911
5912                 if (obj_priv) {
5913                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5914                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5915                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5916                 }
5917         }
5918 }
5919
5920 /* Set up chip specific display functions */
5921 static void intel_init_display(struct drm_device *dev)
5922 {
5923         struct drm_i915_private *dev_priv = dev->dev_private;
5924
5925         /* We always want a DPMS function */
5926         if (HAS_PCH_SPLIT(dev))
5927                 dev_priv->display.dpms = ironlake_crtc_dpms;
5928         else
5929                 dev_priv->display.dpms = i9xx_crtc_dpms;
5930
5931         if (I915_HAS_FBC(dev)) {
5932                 if (IS_IRONLAKE_M(dev)) {
5933                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5934                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5935                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5936                 } else if (IS_GM45(dev)) {
5937                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5938                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5939                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5940                 } else if (IS_CRESTLINE(dev)) {
5941                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5942                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5943                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5944                 }
5945                 /* 855GM needs testing */
5946         }
5947
5948         /* Returns the core display clock speed */
5949         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5950                 dev_priv->display.get_display_clock_speed =
5951                         i945_get_display_clock_speed;
5952         else if (IS_I915G(dev))
5953                 dev_priv->display.get_display_clock_speed =
5954                         i915_get_display_clock_speed;
5955         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5956                 dev_priv->display.get_display_clock_speed =
5957                         i9xx_misc_get_display_clock_speed;
5958         else if (IS_I915GM(dev))
5959                 dev_priv->display.get_display_clock_speed =
5960                         i915gm_get_display_clock_speed;
5961         else if (IS_I865G(dev))
5962                 dev_priv->display.get_display_clock_speed =
5963                         i865_get_display_clock_speed;
5964         else if (IS_I85X(dev))
5965                 dev_priv->display.get_display_clock_speed =
5966                         i855_get_display_clock_speed;
5967         else /* 852, 830 */
5968                 dev_priv->display.get_display_clock_speed =
5969                         i830_get_display_clock_speed;
5970
5971         /* For FIFO watermark updates */
5972         if (HAS_PCH_SPLIT(dev)) {
5973                 if (IS_GEN5(dev)) {
5974                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5975                                 dev_priv->display.update_wm = ironlake_update_wm;
5976                         else {
5977                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5978                                               "Disable CxSR\n");
5979                                 dev_priv->display.update_wm = NULL;
5980                         }
5981                 } else
5982                         dev_priv->display.update_wm = NULL;
5983         } else if (IS_PINEVIEW(dev)) {
5984                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5985                                             dev_priv->is_ddr3,
5986                                             dev_priv->fsb_freq,
5987                                             dev_priv->mem_freq)) {
5988                         DRM_INFO("failed to find known CxSR latency "
5989                                  "(found ddr%s fsb freq %d, mem freq %d), "
5990                                  "disabling CxSR\n",
5991                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5992                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5993                         /* Disable CxSR and never update its watermark again */
5994                         pineview_disable_cxsr(dev);
5995                         dev_priv->display.update_wm = NULL;
5996                 } else
5997                         dev_priv->display.update_wm = pineview_update_wm;
5998         } else if (IS_G4X(dev))
5999                 dev_priv->display.update_wm = g4x_update_wm;
6000         else if (IS_GEN4(dev))
6001                 dev_priv->display.update_wm = i965_update_wm;
6002         else if (IS_GEN3(dev)) {
6003                 dev_priv->display.update_wm = i9xx_update_wm;
6004                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6005         } else if (IS_I85X(dev)) {
6006                 dev_priv->display.update_wm = i9xx_update_wm;
6007                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6008         } else {
6009                 dev_priv->display.update_wm = i830_update_wm;
6010                 if (IS_845G(dev))
6011                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6012                 else
6013                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6014         }
6015 }
6016
6017 /*
6018  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6019  * resume, or other times.  This quirk makes sure that's the case for
6020  * affected systems.
6021  */
6022 static void quirk_pipea_force (struct drm_device *dev)
6023 {
6024         struct drm_i915_private *dev_priv = dev->dev_private;
6025
6026         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6027         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6028 }
6029
6030 struct intel_quirk {
6031         int device;
6032         int subsystem_vendor;
6033         int subsystem_device;
6034         void (*hook)(struct drm_device *dev);
6035 };
6036
6037 struct intel_quirk intel_quirks[] = {
6038         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6039         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6040         /* HP Mini needs pipe A force quirk (LP: #322104) */
6041         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6042
6043         /* Thinkpad R31 needs pipe A force quirk */
6044         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6045         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6046         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6047
6048         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6049         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6050         /* ThinkPad X40 needs pipe A force quirk */
6051
6052         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6053         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6054
6055         /* 855 & before need to leave pipe A & dpll A up */
6056         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6057         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6058 };
6059
6060 static void intel_init_quirks(struct drm_device *dev)
6061 {
6062         struct pci_dev *d = dev->pdev;
6063         int i;
6064
6065         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6066                 struct intel_quirk *q = &intel_quirks[i];
6067
6068                 if (d->device == q->device &&
6069                     (d->subsystem_vendor == q->subsystem_vendor ||
6070                      q->subsystem_vendor == PCI_ANY_ID) &&
6071                     (d->subsystem_device == q->subsystem_device ||
6072                      q->subsystem_device == PCI_ANY_ID))
6073                         q->hook(dev);
6074         }
6075 }
6076
6077 /* Disable the VGA plane that we never use */
6078 static void i915_disable_vga(struct drm_device *dev)
6079 {
6080         struct drm_i915_private *dev_priv = dev->dev_private;
6081         u8 sr1;
6082         u32 vga_reg;
6083
6084         if (HAS_PCH_SPLIT(dev))
6085                 vga_reg = CPU_VGACNTRL;
6086         else
6087                 vga_reg = VGACNTRL;
6088
6089         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6090         outb(1, VGA_SR_INDEX);
6091         sr1 = inb(VGA_SR_DATA);
6092         outb(sr1 | 1<<5, VGA_SR_DATA);
6093         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6094         udelay(300);
6095
6096         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6097         POSTING_READ(vga_reg);
6098 }
6099
6100 void intel_modeset_init(struct drm_device *dev)
6101 {
6102         struct drm_i915_private *dev_priv = dev->dev_private;
6103         int i;
6104
6105         drm_mode_config_init(dev);
6106
6107         dev->mode_config.min_width = 0;
6108         dev->mode_config.min_height = 0;
6109
6110         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6111
6112         intel_init_quirks(dev);
6113
6114         intel_init_display(dev);
6115
6116         if (IS_GEN2(dev)) {
6117                 dev->mode_config.max_width = 2048;
6118                 dev->mode_config.max_height = 2048;
6119         } else if (IS_GEN3(dev)) {
6120                 dev->mode_config.max_width = 4096;
6121                 dev->mode_config.max_height = 4096;
6122         } else {
6123                 dev->mode_config.max_width = 8192;
6124                 dev->mode_config.max_height = 8192;
6125         }
6126
6127         /* set memory base */
6128         if (IS_GEN2(dev))
6129                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6130         else
6131                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6132
6133         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6134                 dev_priv->num_pipe = 2;
6135         else
6136                 dev_priv->num_pipe = 1;
6137         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6138                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6139
6140         for (i = 0; i < dev_priv->num_pipe; i++) {
6141                 intel_crtc_init(dev, i);
6142         }
6143
6144         intel_setup_outputs(dev);
6145
6146         intel_init_clock_gating(dev);
6147
6148         /* Just disable it once at startup */
6149         i915_disable_vga(dev);
6150
6151         if (IS_IRONLAKE_M(dev)) {
6152                 ironlake_enable_drps(dev);
6153                 intel_init_emon(dev);
6154         }
6155
6156         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6157         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6158                     (unsigned long)dev);
6159
6160         intel_setup_overlay(dev);
6161 }
6162
6163 void intel_modeset_cleanup(struct drm_device *dev)
6164 {
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         struct drm_crtc *crtc;
6167         struct intel_crtc *intel_crtc;
6168
6169         drm_kms_helper_poll_fini(dev);
6170         mutex_lock(&dev->struct_mutex);
6171
6172         intel_unregister_dsm_handler();
6173
6174
6175         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6176                 /* Skip inactive CRTCs */
6177                 if (!crtc->fb)
6178                         continue;
6179
6180                 intel_crtc = to_intel_crtc(crtc);
6181                 intel_increase_pllclock(crtc);
6182         }
6183
6184         if (dev_priv->display.disable_fbc)
6185                 dev_priv->display.disable_fbc(dev);
6186
6187         if (dev_priv->renderctx) {
6188                 struct drm_i915_gem_object *obj_priv;
6189
6190                 obj_priv = to_intel_bo(dev_priv->renderctx);
6191                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6192                 I915_READ(CCID);
6193                 i915_gem_object_unpin(dev_priv->renderctx);
6194                 drm_gem_object_unreference(dev_priv->renderctx);
6195         }
6196
6197         if (dev_priv->pwrctx) {
6198                 struct drm_i915_gem_object *obj_priv;
6199
6200                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6201                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6202                 I915_READ(PWRCTXA);
6203                 i915_gem_object_unpin(dev_priv->pwrctx);
6204                 drm_gem_object_unreference(dev_priv->pwrctx);
6205         }
6206
6207         if (IS_IRONLAKE_M(dev))
6208                 ironlake_disable_drps(dev);
6209
6210         mutex_unlock(&dev->struct_mutex);
6211
6212         /* Disable the irq before mode object teardown, for the irq might
6213          * enqueue unpin/hotplug work. */
6214         drm_irq_uninstall(dev);
6215         cancel_work_sync(&dev_priv->hotplug_work);
6216
6217         /* Shut off idle work before the crtcs get freed. */
6218         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6219                 intel_crtc = to_intel_crtc(crtc);
6220                 del_timer_sync(&intel_crtc->idle_timer);
6221         }
6222         del_timer_sync(&dev_priv->idle_timer);
6223         cancel_work_sync(&dev_priv->idle_work);
6224
6225         drm_mode_config_cleanup(dev);
6226 }
6227
6228 /*
6229  * Return which encoder is currently attached for connector.
6230  */
6231 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6232 {
6233         return &intel_attached_encoder(connector)->base;
6234 }
6235
6236 void intel_connector_attach_encoder(struct intel_connector *connector,
6237                                     struct intel_encoder *encoder)
6238 {
6239         connector->encoder = encoder;
6240         drm_mode_connector_attach_encoder(&connector->base,
6241                                           &encoder->base);
6242 }
6243
6244 /*
6245  * set vga decode state - true == enable VGA decode
6246  */
6247 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6248 {
6249         struct drm_i915_private *dev_priv = dev->dev_private;
6250         u16 gmch_ctrl;
6251
6252         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6253         if (state)
6254                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6255         else
6256                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6257         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6258         return 0;
6259 }