sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  82                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, int, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, CPT},"
 129                          "{Intel, PBG},"
 130                          "{Intel, SCH},"
 131                          "{ATI, SB450},"
 132                          "{ATI, SB600},"
 133                          "{ATI, RS600},"
 134                          "{ATI, RS690},"
 135                          "{ATI, RS780},"
 136                          "{ATI, R600},"
 137                          "{ATI, RV630},"
 138                          "{ATI, RV610},"
 139                          "{ATI, RV670},"
 140                          "{ATI, RV635},"
 141                          "{ATI, RV620},"
 142                          "{ATI, RV770},"
 143                          "{VIA, VT8251},"
 144                          "{VIA, VT8237A},"
 145                          "{SiS, SIS966},"
 146                          "{ULI, M5461}}");
 147 MODULE_DESCRIPTION("Intel HDA driver");
 148
 149 #ifdef CONFIG_SND_VERBOSE_PRINTK
 150 #define SFX     /* nop */
 151 #else
 152 #define SFX     "hda-intel: "
 153 #endif
 154
 155 /*
 156  * registers
 157  */
 158 #define ICH6_REG_GCAP                   0x00
 159 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 160 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 161 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 162 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 163 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 164 #define ICH6_REG_VMIN                   0x02
 165 #define ICH6_REG_VMAJ                   0x03
 166 #define ICH6_REG_OUTPAY                 0x04
 167 #define ICH6_REG_INPAY                  0x06
 168 #define ICH6_REG_GCTL                   0x08
 169 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 170 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 171 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 172 #define ICH6_REG_WAKEEN                 0x0c
 173 #define ICH6_REG_STATESTS               0x0e
 174 #define ICH6_REG_GSTS                   0x10
 175 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 176 #define ICH6_REG_INTCTL                 0x20
 177 #define ICH6_REG_INTSTS                 0x24
 178 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 179 #define ICH6_REG_SYNC                   0x34
 180 #define ICH6_REG_CORBLBASE              0x40
 181 #define ICH6_REG_CORBUBASE              0x44
 182 #define ICH6_REG_CORBWP                 0x48
 183 #define ICH6_REG_CORBRP                 0x4a
 184 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 185 #define ICH6_REG_CORBCTL                0x4c
 186 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 187 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 188 #define ICH6_REG_CORBSTS                0x4d
 189 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 190 #define ICH6_REG_CORBSIZE               0x4e
 191
 192 #define ICH6_REG_RIRBLBASE              0x50
 193 #define ICH6_REG_RIRBUBASE              0x54
 194 #define ICH6_REG_RIRBWP                 0x58
 195 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 196 #define ICH6_REG_RINTCNT                0x5a
 197 #define ICH6_REG_RIRBCTL                0x5c
 198 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 199 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 200 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 201 #define ICH6_REG_RIRBSTS                0x5d
 202 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 203 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 204 #define ICH6_REG_RIRBSIZE               0x5e
 205
 206 #define ICH6_REG_IC                     0x60
 207 #define ICH6_REG_IR                     0x64
 208 #define ICH6_REG_IRS                    0x68
 209 #define   ICH6_IRS_VALID        (1<<1)
 210 #define   ICH6_IRS_BUSY         (1<<0)
 211
 212 #define ICH6_REG_DPLBASE                0x70
 213 #define ICH6_REG_DPUBASE                0x74
 214 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 215
 216 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 217 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 218
 219 /* stream register offsets from stream base */
 220 #define ICH6_REG_SD_CTL                 0x00
 221 #define ICH6_REG_SD_STS                 0x03
 222 #define ICH6_REG_SD_LPIB                0x04
 223 #define ICH6_REG_SD_CBL                 0x08
 224 #define ICH6_REG_SD_LVI                 0x0c
 225 #define ICH6_REG_SD_FIFOW               0x0e
 226 #define ICH6_REG_SD_FIFOSIZE            0x10
 227 #define ICH6_REG_SD_FORMAT              0x12
 228 #define ICH6_REG_SD_BDLPL               0x18
 229 #define ICH6_REG_SD_BDLPU               0x1c
 230
 231 /* PCI space */
 232 #define ICH6_PCIREG_TCSEL       0x44
 233
 234 /*
 235  * other constants
 236  */
 237
 238 /* max number of SDs */
 239 /* ICH, ATI and VIA have 4 playback and 4 capture */
 240 #define ICH6_NUM_CAPTURE        4
 241 #define ICH6_NUM_PLAYBACK       4
 242
 243 /* ULI has 6 playback and 5 capture */
 244 #define ULI_NUM_CAPTURE         5
 245 #define ULI_NUM_PLAYBACK        6
 246
 247 /* ATI HDMI has 1 playback and 0 capture */
 248 #define ATIHDMI_NUM_CAPTURE     0
 249 #define ATIHDMI_NUM_PLAYBACK    1
 250
 251 /* TERA has 4 playback and 3 capture */
 252 #define TERA_NUM_CAPTURE        3
 253 #define TERA_NUM_PLAYBACK       4
 254
 255 /* this number is statically defined for simplicity */
 256 #define MAX_AZX_DEV             16
 257
 258 /* max number of fragments - we may use more if allocating more pages for BDL */
 259 #define BDL_SIZE                4096
 260 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 261 #define AZX_MAX_FRAG            32
 262 /* max buffer size - no h/w limit, you can increase as you like */
 263 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 264
 265 /* RIRB int mask: overrun[2], response[0] */
 266 #define RIRB_INT_RESPONSE       0x01
 267 #define RIRB_INT_OVERRUN        0x04
 268 #define RIRB_INT_MASK           0x05
 269
 270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 271 #define AZX_MAX_CODECS          8
 272 #define AZX_DEFAULT_CODECS      4
 273 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 274
 275 /* SD_CTL bits */
 276 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 277 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 278 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 279 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 280 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 281 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 282 #define SD_CTL_STREAM_TAG_SHIFT 20
 283
 284 /* SD_CTL and SD_STS */
 285 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 286 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 287 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 288 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 289                                  SD_INT_COMPLETE)
 290
 291 /* SD_STS */
 292 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 293
 294 /* INTCTL and INTSTS */
 295 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 296 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 297 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 298
 299 /* below are so far hardcoded - should read registers in future */
 300 #define ICH6_MAX_CORB_ENTRIES   256
 301 #define ICH6_MAX_RIRB_ENTRIES   256
 302
 303 /* position fix mode */
 304 enum {
 305         POS_FIX_AUTO,
 306         POS_FIX_LPIB,
 307         POS_FIX_POSBUF,
 308         POS_FIX_VIACOMBO,
 309 };
 310
 311 /* Defines for ATI HD Audio support in SB450 south bridge */
 312 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 313 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 314
 315 /* Defines for Nvidia HDA support */
 316 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 317 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 318 #define NVIDIA_HDA_ISTRM_COH          0x4d
 319 #define NVIDIA_HDA_OSTRM_COH          0x4c
 320 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 321
 322 /* Defines for Intel SCH HDA snoop control */
 323 #define INTEL_SCH_HDA_DEVC      0x78
 324 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 325
 326 /* Define IN stream 0 FIFO size offset in VIA controller */
 327 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 328 /* Define VIA HD Audio Device ID*/
 329 #define VIA_HDAC_DEVICE_ID              0x3288
 330
 331 /* HD Audio class code */
 332 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 333
 334 /*
 335  */
 336
 337 struct azx_dev {
 338         struct snd_dma_buffer bdl; /* BDL buffer */
 339         u32 *posbuf;            /* position buffer pointer */
 340
 341         unsigned int bufsize;   /* size of the play buffer in bytes */
 342         unsigned int period_bytes; /* size of the period in bytes */
 343         unsigned int frags;     /* number for period in the play buffer */
 344         unsigned int fifo_size; /* FIFO size */
 345         unsigned long start_wallclk;    /* start + minimum wallclk */
 346         unsigned long period_wallclk;   /* wallclk for period */
 347
 348         void __iomem *sd_addr;  /* stream descriptor pointer */
 349
 350         u32 sd_int_sta_mask;    /* stream int status mask */
 351
 352         /* pcm support */
 353         struct snd_pcm_substream *substream;    /* assigned substream,
 354                                                  * set in PCM open
 355                                                  */
 356         unsigned int format_val;        /* format value to be set in the
 357                                          * controller and the codec
 358                                          */
 359         unsigned char stream_tag;       /* assigned stream */
 360         unsigned char index;            /* stream index */
 361         int device;                     /* last device number assigned to */
 362
 363         unsigned int opened :1;
 364         unsigned int running :1;
 365         unsigned int irq_pending :1;
 366         /*
 367          * For VIA:
 368          *  A flag to ensure DMA position is 0
 369          *  when link position is not greater than FIFO size
 370          */
 371         unsigned int insufficient :1;
 372 };
 373
 374 /* CORB/RIRB */
 375 struct azx_rb {
 376         u32 *buf;               /* CORB/RIRB buffer
 377                                  * Each CORB entry is 4byte, RIRB is 8byte
 378                                  */
 379         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 380         /* for RIRB */
 381         unsigned short rp, wp;  /* read/write pointers */
 382         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 383         u32 res[AZX_MAX_CODECS];        /* last read value */
 384 };
 385
 386 struct azx {
 387         struct snd_card *card;
 388         struct pci_dev *pci;
 389         int dev_index;
 390
 391         /* chip type specific */
 392         int driver_type;
 393         int playback_streams;
 394         int playback_index_offset;
 395         int capture_streams;
 396         int capture_index_offset;
 397         int num_streams;
 398
 399         /* pci resources */
 400         unsigned long addr;
 401         void __iomem *remap_addr;
 402         int irq;
 403
 404         /* locks */
 405         spinlock_t reg_lock;
 406         struct mutex open_mutex;
 407
 408         /* streams (x num_streams) */
 409         struct azx_dev *azx_dev;
 410
 411         /* PCM */
 412         struct snd_pcm *pcm[HDA_MAX_PCMS];
 413
 414         /* HD codec */
 415         unsigned short codec_mask;
 416         int  codec_probe_mask; /* copied from probe_mask option */
 417         struct hda_bus *bus;
 418         unsigned int beep_mode;
 419
 420         /* CORB/RIRB */
 421         struct azx_rb corb;
 422         struct azx_rb rirb;
 423
 424         /* CORB/RIRB and position buffers */
 425         struct snd_dma_buffer rb;
 426         struct snd_dma_buffer posbuf;
 427
 428         /* flags */
 429         int position_fix[2]; /* for both playback/capture streams */
 430         int poll_count;
 431         unsigned int running :1;
 432         unsigned int initialized :1;
 433         unsigned int single_cmd :1;
 434         unsigned int polling_mode :1;
 435         unsigned int msi :1;
 436         unsigned int irq_pending_warned :1;
 437         unsigned int probing :1; /* codec probing phase */
 438
 439         /* for debugging */
 440         unsigned int last_cmd[AZX_MAX_CODECS];
 441
 442         /* for pending irqs */
 443         struct work_struct irq_pending_work;
 444
 445         /* reboot notifier (for mysterious hangup problem at power-down) */
 446         struct notifier_block reboot_notifier;
 447 };
 448
 449 /* driver types */
 450 enum {
 451         AZX_DRIVER_ICH,
 452         AZX_DRIVER_PCH,
 453         AZX_DRIVER_SCH,
 454         AZX_DRIVER_ATI,
 455         AZX_DRIVER_ATIHDMI,
 456         AZX_DRIVER_VIA,
 457         AZX_DRIVER_SIS,
 458         AZX_DRIVER_ULI,
 459         AZX_DRIVER_NVIDIA,
 460         AZX_DRIVER_TERA,
 461         AZX_DRIVER_CTX,
 462         AZX_DRIVER_GENERIC,
 463         AZX_NUM_DRIVERS, /* keep this as last entry */
 464 };
 465
 466 static char *driver_short_names[] __devinitdata = {
 467         [AZX_DRIVER_ICH] = "HDA Intel",
 468         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 469         [AZX_DRIVER_SCH] = "HDA Intel MID",
 470         [AZX_DRIVER_ATI] = "HDA ATI SB",
 471         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 472         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 473         [AZX_DRIVER_SIS] = "HDA SIS966",
 474         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 475         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 476         [AZX_DRIVER_TERA] = "HDA Teradici",
 477         [AZX_DRIVER_CTX] = "HDA Creative",
 478         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 479 };
 480
 481 /*
 482  * macros for easy use
 483  */
 484 #define azx_writel(chip,reg,value) \
 485         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 486 #define azx_readl(chip,reg) \
 487         readl((chip)->remap_addr + ICH6_REG_##reg)
 488 #define azx_writew(chip,reg,value) \
 489         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 490 #define azx_readw(chip,reg) \
 491         readw((chip)->remap_addr + ICH6_REG_##reg)
 492 #define azx_writeb(chip,reg,value) \
 493         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 494 #define azx_readb(chip,reg) \
 495         readb((chip)->remap_addr + ICH6_REG_##reg)
 496
 497 #define azx_sd_writel(dev,reg,value) \
 498         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 499 #define azx_sd_readl(dev,reg) \
 500         readl((dev)->sd_addr + ICH6_REG_##reg)
 501 #define azx_sd_writew(dev,reg,value) \
 502         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 503 #define azx_sd_readw(dev,reg) \
 504         readw((dev)->sd_addr + ICH6_REG_##reg)
 505 #define azx_sd_writeb(dev,reg,value) \
 506         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 507 #define azx_sd_readb(dev,reg) \
 508         readb((dev)->sd_addr + ICH6_REG_##reg)
 509
 510 /* for pcm support */
 511 #define get_azx_dev(substream) (substream->runtime->private_data)
 512
 513 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 514 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 515 /*
 516  * Interface for HD codec
 517  */
 518
 519 /*
 520  * CORB / RIRB interface
 521  */
 522 static int azx_alloc_cmd_io(struct azx *chip)
 523 {
 524         int err;
 525
 526         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 527         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 528                                   snd_dma_pci_data(chip->pci),
 529                                   PAGE_SIZE, &chip->rb);
 530         if (err < 0) {
 531                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 532                 return err;
 533         }
 534         return 0;
 535 }
 536
 537 static void azx_init_cmd_io(struct azx *chip)
 538 {
 539         spin_lock_irq(&chip->reg_lock);
 540         /* CORB set up */
 541         chip->corb.addr = chip->rb.addr;
 542         chip->corb.buf = (u32 *)chip->rb.area;
 543         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 544         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 545
 546         /* set the corb size to 256 entries (ULI requires explicitly) */
 547         azx_writeb(chip, CORBSIZE, 0x02);
 548         /* set the corb write pointer to 0 */
 549         azx_writew(chip, CORBWP, 0);
 550         /* reset the corb hw read pointer */
 551         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 552         /* enable corb dma */
 553         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 554
 555         /* RIRB set up */
 556         chip->rirb.addr = chip->rb.addr + 2048;
 557         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 558         chip->rirb.wp = chip->rirb.rp = 0;
 559         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 560         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 561         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 562
 563         /* set the rirb size to 256 entries (ULI requires explicitly) */
 564         azx_writeb(chip, RIRBSIZE, 0x02);
 565         /* reset the rirb hw write pointer */
 566         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 567         /* set N=1, get RIRB response interrupt for new entry */
 568         if (chip->driver_type == AZX_DRIVER_CTX)
 569                 azx_writew(chip, RINTCNT, 0xc0);
 570         else
 571                 azx_writew(chip, RINTCNT, 1);
 572         /* enable rirb dma and response irq */
 573         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 574         spin_unlock_irq(&chip->reg_lock);
 575 }
 576
 577 static void azx_free_cmd_io(struct azx *chip)
 578 {
 579         spin_lock_irq(&chip->reg_lock);
 580         /* disable ringbuffer DMAs */
 581         azx_writeb(chip, RIRBCTL, 0);
 582         azx_writeb(chip, CORBCTL, 0);
 583         spin_unlock_irq(&chip->reg_lock);
 584 }
 585
 586 static unsigned int azx_command_addr(u32 cmd)
 587 {
 588         unsigned int addr = cmd >> 28;
 589
 590         if (addr >= AZX_MAX_CODECS) {
 591                 snd_BUG();
 592                 addr = 0;
 593         }
 594
 595         return addr;
 596 }
 597
 598 static unsigned int azx_response_addr(u32 res)
 599 {
 600         unsigned int addr = res & 0xf;
 601
 602         if (addr >= AZX_MAX_CODECS) {
 603                 snd_BUG();
 604                 addr = 0;
 605         }
 606
 607         return addr;
 608 }
 609
 610 /* send a command */
 611 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 612 {
 613         struct azx *chip = bus->private_data;
 614         unsigned int addr = azx_command_addr(val);
 615         unsigned int wp;
 616
 617         spin_lock_irq(&chip->reg_lock);
 618
 619         /* add command to corb */
 620         wp = azx_readb(chip, CORBWP);
 621         wp++;
 622         wp %= ICH6_MAX_CORB_ENTRIES;
 623
 624         chip->rirb.cmds[addr]++;
 625         chip->corb.buf[wp] = cpu_to_le32(val);
 626         azx_writel(chip, CORBWP, wp);
 627
 628         spin_unlock_irq(&chip->reg_lock);
 629
 630         return 0;
 631 }
 632
 633 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 634
 635 /* retrieve RIRB entry - called from interrupt handler */
 636 static void azx_update_rirb(struct azx *chip)
 637 {
 638         unsigned int rp, wp;
 639         unsigned int addr;
 640         u32 res, res_ex;
 641
 642         wp = azx_readb(chip, RIRBWP);
 643         if (wp == chip->rirb.wp)
 644                 return;
 645         chip->rirb.wp = wp;
 646
 647         while (chip->rirb.rp != wp) {
 648                 chip->rirb.rp++;
 649                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 650
 651                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 652                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 653                 res = le32_to_cpu(chip->rirb.buf[rp]);
 654                 addr = azx_response_addr(res_ex);
 655                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 656                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 657                 else if (chip->rirb.cmds[addr]) {
 658                         chip->rirb.res[addr] = res;
 659                         smp_wmb();
 660                         chip->rirb.cmds[addr]--;
 661                 } else
 662                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 663                                    "last cmd=%#08x\n",
 664                                    res, res_ex,
 665                                    chip->last_cmd[addr]);
 666         }
 667 }
 668
 669 /* receive a response */
 670 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 671                                           unsigned int addr)
 672 {
 673         struct azx *chip = bus->private_data;
 674         unsigned long timeout;
 675         int do_poll = 0;
 676
 677  again:
 678         timeout = jiffies + msecs_to_jiffies(1000);
 679         for (;;) {
 680                 if (chip->polling_mode || do_poll) {
 681                         spin_lock_irq(&chip->reg_lock);
 682                         azx_update_rirb(chip);
 683                         spin_unlock_irq(&chip->reg_lock);
 684                 }
 685                 if (!chip->rirb.cmds[addr]) {
 686                         smp_rmb();
 687                         bus->rirb_error = 0;
 688
 689                         if (!do_poll)
 690                                 chip->poll_count = 0;
 691                         return chip->rirb.res[addr]; /* the last value */
 692                 }
 693                 if (time_after(jiffies, timeout))
 694                         break;
 695                 if (bus->needs_damn_long_delay)
 696                         msleep(2); /* temporary workaround */
 697                 else {
 698                         udelay(10);
 699                         cond_resched();
 700                 }
 701         }
 702
 703         if (!chip->polling_mode && chip->poll_count < 2) {
 704                 snd_printdd(SFX "azx_get_response timeout, "
 705                            "polling the codec once: last cmd=0x%08x\n",
 706                            chip->last_cmd[addr]);
 707                 do_poll = 1;
 708                 chip->poll_count++;
 709                 goto again;
 710         }
 711
 712
 713         if (!chip->polling_mode) {
 714                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 715                            "switching to polling mode: last cmd=0x%08x\n",
 716                            chip->last_cmd[addr]);
 717                 chip->polling_mode = 1;
 718                 goto again;
 719         }
 720
 721         if (chip->msi) {
 722                 snd_printk(KERN_WARNING SFX "No response from codec, "
 723                            "disabling MSI: last cmd=0x%08x\n",
 724                            chip->last_cmd[addr]);
 725                 free_irq(chip->irq, chip);
 726                 chip->irq = -1;
 727                 pci_disable_msi(chip->pci);
 728                 chip->msi = 0;
 729                 if (azx_acquire_irq(chip, 1) < 0) {
 730                         bus->rirb_error = 1;
 731                         return -1;
 732                 }
 733                 goto again;
 734         }
 735
 736         if (chip->probing) {
 737                 /* If this critical timeout happens during the codec probing
 738                  * phase, this is likely an access to a non-existing codec
 739                  * slot.  Better to return an error and reset the system.
 740                  */
 741                 return -1;
 742         }
 743
 744         /* a fatal communication error; need either to reset or to fallback
 745          * to the single_cmd mode
 746          */
 747         bus->rirb_error = 1;
 748         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 749                 bus->response_reset = 1;
 750                 return -1; /* give a chance to retry */
 751         }
 752
 753         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 754                    "switching to single_cmd mode: last cmd=0x%08x\n",
 755                    chip->last_cmd[addr]);
 756         chip->single_cmd = 1;
 757         bus->response_reset = 0;
 758         /* release CORB/RIRB */
 759         azx_free_cmd_io(chip);
 760         /* disable unsolicited responses */
 761         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 762         return -1;
 763 }
 764
 765 /*
 766  * Use the single immediate command instead of CORB/RIRB for simplicity
 767  *
 768  * Note: according to Intel, this is not preferred use.  The command was
 769  *       intended for the BIOS only, and may get confused with unsolicited
 770  *       responses.  So, we shouldn't use it for normal operation from the
 771  *       driver.
 772  *       I left the codes, however, for debugging/testing purposes.
 773  */
 774
 775 /* receive a response */
 776 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 777 {
 778         int timeout = 50;
 779
 780         while (timeout--) {
 781                 /* check IRV busy bit */
 782                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 783                         /* reuse rirb.res as the response return value */
 784                         chip->rirb.res[addr] = azx_readl(chip, IR);
 785                         return 0;
 786                 }
 787                 udelay(1);
 788         }
 789         if (printk_ratelimit())
 790                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 791                            azx_readw(chip, IRS));
 792         chip->rirb.res[addr] = -1;
 793         return -EIO;
 794 }
 795
 796 /* send a command */
 797 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 798 {
 799         struct azx *chip = bus->private_data;
 800         unsigned int addr = azx_command_addr(val);
 801         int timeout = 50;
 802
 803         bus->rirb_error = 0;
 804         while (timeout--) {
 805                 /* check ICB busy bit */
 806                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 807                         /* Clear IRV valid bit */
 808                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 809                                    ICH6_IRS_VALID);
 810                         azx_writel(chip, IC, val);
 811                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 812                                    ICH6_IRS_BUSY);
 813                         return azx_single_wait_for_response(chip, addr);
 814                 }
 815                 udelay(1);
 816         }
 817         if (printk_ratelimit())
 818                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 819                            azx_readw(chip, IRS), val);
 820         return -EIO;
 821 }
 822
 823 /* receive a response */
 824 static unsigned int azx_single_get_response(struct hda_bus *bus,
 825                                             unsigned int addr)
 826 {
 827         struct azx *chip = bus->private_data;
 828         return chip->rirb.res[addr];
 829 }
 830
 831 /*
 832  * The below are the main callbacks from hda_codec.
 833  *
 834  * They are just the skeleton to call sub-callbacks according to the
 835  * current setting of chip->single_cmd.
 836  */
 837
 838 /* send a command */
 839 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 840 {
 841         struct azx *chip = bus->private_data;
 842
 843         chip->last_cmd[azx_command_addr(val)] = val;
 844         if (chip->single_cmd)
 845                 return azx_single_send_cmd(bus, val);
 846         else
 847                 return azx_corb_send_cmd(bus, val);
 848 }
 849
 850 /* get a response */
 851 static unsigned int azx_get_response(struct hda_bus *bus,
 852                                      unsigned int addr)
 853 {
 854         struct azx *chip = bus->private_data;
 855         if (chip->single_cmd)
 856                 return azx_single_get_response(bus, addr);
 857         else
 858                 return azx_rirb_get_response(bus, addr);
 859 }
 860
 861 #ifdef CONFIG_SND_HDA_POWER_SAVE
 862 static void azx_power_notify(struct hda_bus *bus);
 863 #endif
 864
 865 /* reset codec link */
 866 static int azx_reset(struct azx *chip, int full_reset)
 867 {
 868         int count;
 869
 870         if (!full_reset)
 871                 goto __skip;
 872
 873         /* clear STATESTS */
 874         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 875
 876         /* reset controller */
 877         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 878
 879         count = 50;
 880         while (azx_readb(chip, GCTL) && --count)
 881                 msleep(1);
 882
 883         /* delay for >= 100us for codec PLL to settle per spec
 884          * Rev 0.9 section 5.5.1
 885          */
 886         msleep(1);
 887
 888         /* Bring controller out of reset */
 889         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 890
 891         count = 50;
 892         while (!azx_readb(chip, GCTL) && --count)
 893                 msleep(1);
 894
 895         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 896         msleep(1);
 897
 898       __skip:
 899         /* check to see if controller is ready */
 900         if (!azx_readb(chip, GCTL)) {
 901                 snd_printd(SFX "azx_reset: controller not ready!\n");
 902                 return -EBUSY;
 903         }
 904
 905         /* Accept unsolicited responses */
 906         if (!chip->single_cmd)
 907                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 908                            ICH6_GCTL_UNSOL);
 909
 910         /* detect codecs */
 911         if (!chip->codec_mask) {
 912                 chip->codec_mask = azx_readw(chip, STATESTS);
 913                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 914         }
 915
 916         return 0;
 917 }
 918
 919
 920 /*
 921  * Lowlevel interface
 922  */
 923
 924 /* enable interrupts */
 925 static void azx_int_enable(struct azx *chip)
 926 {
 927         /* enable controller CIE and GIE */
 928         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 929                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 930 }
 931
 932 /* disable interrupts */
 933 static void azx_int_disable(struct azx *chip)
 934 {
 935         int i;
 936
 937         /* disable interrupts in stream descriptor */
 938         for (i = 0; i < chip->num_streams; i++) {
 939                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 940                 azx_sd_writeb(azx_dev, SD_CTL,
 941                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 942         }
 943
 944         /* disable SIE for all streams */
 945         azx_writeb(chip, INTCTL, 0);
 946
 947         /* disable controller CIE and GIE */
 948         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 949                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 950 }
 951
 952 /* clear interrupts */
 953 static void azx_int_clear(struct azx *chip)
 954 {
 955         int i;
 956
 957         /* clear stream status */
 958         for (i = 0; i < chip->num_streams; i++) {
 959                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 960                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 961         }
 962
 963         /* clear STATESTS */
 964         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 965
 966         /* clear rirb status */
 967         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 968
 969         /* clear int status */
 970         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 971 }
 972
 973 /* start a stream */
 974 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 975 {
 976         /*
 977          * Before stream start, initialize parameter
 978          */
 979         azx_dev->insufficient = 1;
 980
 981         /* enable SIE */
 982         azx_writel(chip, INTCTL,
 983                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
 984         /* set DMA start and interrupt mask */
 985         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 986                       SD_CTL_DMA_START | SD_INT_MASK);
 987 }
 988
 989 /* stop DMA */
 990 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 991 {
 992         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 993                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 994         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 995 }
 996
 997 /* stop a stream */
 998 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 999 {
1000         azx_stream_clear(chip, azx_dev);
1001         /* disable SIE */
1002         azx_writel(chip, INTCTL,
1003                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1004 }
1005
1006
1007 /*
1008  * reset and start the controller registers
1009  */
1010 static void azx_init_chip(struct azx *chip, int full_reset)
1011 {
1012         if (chip->initialized)
1013                 return;
1014
1015         /* reset controller */
1016         azx_reset(chip, full_reset);
1017
1018         /* initialize interrupts */
1019         azx_int_clear(chip);
1020         azx_int_enable(chip);
1021
1022         /* initialize the codec command I/O */
1023         if (!chip->single_cmd)
1024                 azx_init_cmd_io(chip);
1025
1026         /* program the position buffer */
1027         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1028         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1029
1030         chip->initialized = 1;
1031 }
1032
1033 /*
1034  * initialize the PCI registers
1035  */
1036 /* update bits in a PCI register byte */
1037 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1038                             unsigned char mask, unsigned char val)
1039 {
1040         unsigned char data;
1041
1042         pci_read_config_byte(pci, reg, &data);
1043         data &= ~mask;
1044         data |= (val & mask);
1045         pci_write_config_byte(pci, reg, data);
1046 }
1047
1048 static void azx_init_pci(struct azx *chip)
1049 {
1050         unsigned short snoop;
1051
1052         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1053          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1054          * Ensuring these bits are 0 clears playback static on some HD Audio
1055          * codecs
1056          */
1057         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1058
1059         switch (chip->driver_type) {
1060         case AZX_DRIVER_ATI:
1061                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1062                 update_pci_byte(chip->pci,
1063                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1064                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1065                 break;
1066         case AZX_DRIVER_NVIDIA:
1067                 /* For NVIDIA HDA, enable snoop */
1068                 update_pci_byte(chip->pci,
1069                                 NVIDIA_HDA_TRANSREG_ADDR,
1070                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1071                 update_pci_byte(chip->pci,
1072                                 NVIDIA_HDA_ISTRM_COH,
1073                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1074                 update_pci_byte(chip->pci,
1075                                 NVIDIA_HDA_OSTRM_COH,
1076                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1077                 break;
1078         case AZX_DRIVER_SCH:
1079         case AZX_DRIVER_PCH:
1080                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1081                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1082                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1083                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1084                         pci_read_config_word(chip->pci,
1085                                 INTEL_SCH_HDA_DEVC, &snoop);
1086                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1087                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1088                                 ? "Failed" : "OK");
1089                 }
1090                 break;
1091         default:
1092                 /* AMD Hudson needs the similar snoop, as it seems... */
1093                 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1094                         update_pci_byte(chip->pci,
1095                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1096                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1097                 break;
1098         }
1099 }
1100
1101
1102 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1103
1104 /*
1105  * interrupt handler
1106  */
1107 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1108 {
1109         struct azx *chip = dev_id;
1110         struct azx_dev *azx_dev;
1111         u32 status;
1112         u8 sd_status;
1113         int i, ok;
1114
1115         spin_lock(&chip->reg_lock);
1116
1117         status = azx_readl(chip, INTSTS);
1118         if (status == 0) {
1119                 spin_unlock(&chip->reg_lock);
1120                 return IRQ_NONE;
1121         }
1122
1123         for (i = 0; i < chip->num_streams; i++) {
1124                 azx_dev = &chip->azx_dev[i];
1125                 if (status & azx_dev->sd_int_sta_mask) {
1126                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1127                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1128                         if (!azx_dev->substream || !azx_dev->running ||
1129                             !(sd_status & SD_INT_COMPLETE))
1130                                 continue;
1131                         /* check whether this IRQ is really acceptable */
1132                         ok = azx_position_ok(chip, azx_dev);
1133                         if (ok == 1) {
1134                                 azx_dev->irq_pending = 0;
1135                                 spin_unlock(&chip->reg_lock);
1136                                 snd_pcm_period_elapsed(azx_dev->substream);
1137                                 spin_lock(&chip->reg_lock);
1138                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1139                                 /* bogus IRQ, process it later */
1140                                 azx_dev->irq_pending = 1;
1141                                 queue_work(chip->bus->workq,
1142                                            &chip->irq_pending_work);
1143                         }
1144                 }
1145         }
1146
1147         /* clear rirb int */
1148         status = azx_readb(chip, RIRBSTS);
1149         if (status & RIRB_INT_MASK) {
1150                 if (status & RIRB_INT_RESPONSE) {
1151                         if (chip->driver_type == AZX_DRIVER_CTX)
1152                                 udelay(80);
1153                         azx_update_rirb(chip);
1154                 }
1155                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1156         }
1157
1158 #if 0
1159         /* clear state status int */
1160         if (azx_readb(chip, STATESTS) & 0x04)
1161                 azx_writeb(chip, STATESTS, 0x04);
1162 #endif
1163         spin_unlock(&chip->reg_lock);
1164
1165         return IRQ_HANDLED;
1166 }
1167
1168
1169 /*
1170  * set up a BDL entry
1171  */
1172 static int setup_bdle(struct snd_pcm_substream *substream,
1173                       struct azx_dev *azx_dev, u32 **bdlp,
1174                       int ofs, int size, int with_ioc)
1175 {
1176         u32 *bdl = *bdlp;
1177
1178         while (size > 0) {
1179                 dma_addr_t addr;
1180                 int chunk;
1181
1182                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1183                         return -EINVAL;
1184
1185                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1186                 /* program the address field of the BDL entry */
1187                 bdl[0] = cpu_to_le32((u32)addr);
1188                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1189                 /* program the size field of the BDL entry */
1190                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1191                 bdl[2] = cpu_to_le32(chunk);
1192                 /* program the IOC to enable interrupt
1193                  * only when the whole fragment is processed
1194                  */
1195                 size -= chunk;
1196                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1197                 bdl += 4;
1198                 azx_dev->frags++;
1199                 ofs += chunk;
1200         }
1201         *bdlp = bdl;
1202         return ofs;
1203 }
1204
1205 /*
1206  * set up BDL entries
1207  */
1208 static int azx_setup_periods(struct azx *chip,
1209                              struct snd_pcm_substream *substream,
1210                              struct azx_dev *azx_dev)
1211 {
1212         u32 *bdl;
1213         int i, ofs, periods, period_bytes;
1214         int pos_adj;
1215
1216         /* reset BDL address */
1217         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1218         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1219
1220         period_bytes = azx_dev->period_bytes;
1221         periods = azx_dev->bufsize / period_bytes;
1222
1223         /* program the initial BDL entries */
1224         bdl = (u32 *)azx_dev->bdl.area;
1225         ofs = 0;
1226         azx_dev->frags = 0;
1227         pos_adj = bdl_pos_adj[chip->dev_index];
1228         if (pos_adj > 0) {
1229                 struct snd_pcm_runtime *runtime = substream->runtime;
1230                 int pos_align = pos_adj;
1231                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1232                 if (!pos_adj)
1233                         pos_adj = pos_align;
1234                 else
1235                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1236                                 pos_align;
1237                 pos_adj = frames_to_bytes(runtime, pos_adj);
1238                 if (pos_adj >= period_bytes) {
1239                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1240                                    bdl_pos_adj[chip->dev_index]);
1241                         pos_adj = 0;
1242                 } else {
1243                         ofs = setup_bdle(substream, azx_dev,
1244                                          &bdl, ofs, pos_adj,
1245                                          !substream->runtime->no_period_wakeup);
1246                         if (ofs < 0)
1247                                 goto error;
1248                 }
1249         } else
1250                 pos_adj = 0;
1251         for (i = 0; i < periods; i++) {
1252                 if (i == periods - 1 && pos_adj)
1253                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1254                                          period_bytes - pos_adj, 0);
1255                 else
1256                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1257                                          period_bytes,
1258                                          !substream->runtime->no_period_wakeup);
1259                 if (ofs < 0)
1260                         goto error;
1261         }
1262         return 0;
1263
1264  error:
1265         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1266                    azx_dev->bufsize, period_bytes);
1267         return -EINVAL;
1268 }
1269
1270 /* reset stream */
1271 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1272 {
1273         unsigned char val;
1274         int timeout;
1275
1276         azx_stream_clear(chip, azx_dev);
1277
1278         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1279                       SD_CTL_STREAM_RESET);
1280         udelay(3);
1281         timeout = 300;
1282         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1283                --timeout)
1284                 ;
1285         val &= ~SD_CTL_STREAM_RESET;
1286         azx_sd_writeb(azx_dev, SD_CTL, val);
1287         udelay(3);
1288
1289         timeout = 300;
1290         /* waiting for hardware to report that the stream is out of reset */
1291         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1292                --timeout)
1293                 ;
1294
1295         /* reset first position - may not be synced with hw at this time */
1296         *azx_dev->posbuf = 0;
1297 }
1298
1299 /*
1300  * set up the SD for streaming
1301  */
1302 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1303 {
1304         /* make sure the run bit is zero for SD */
1305         azx_stream_clear(chip, azx_dev);
1306         /* program the stream_tag */
1307         azx_sd_writel(azx_dev, SD_CTL,
1308                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1309                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1310
1311         /* program the length of samples in cyclic buffer */
1312         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1313
1314         /* program the stream format */
1315         /* this value needs to be the same as the one programmed */
1316         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1317
1318         /* program the stream LVI (last valid index) of the BDL */
1319         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1320
1321         /* program the BDL address */
1322         /* lower BDL address */
1323         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1324         /* upper BDL address */
1325         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1326
1327         /* enable the position buffer */
1328         if (chip->position_fix[0] != POS_FIX_LPIB ||
1329             chip->position_fix[1] != POS_FIX_LPIB) {
1330                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1331                         azx_writel(chip, DPLBASE,
1332                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1333         }
1334
1335         /* set the interrupt enable bits in the descriptor control register */
1336         azx_sd_writel(azx_dev, SD_CTL,
1337                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1338
1339         return 0;
1340 }
1341
1342 /*
1343  * Probe the given codec address
1344  */
1345 static int probe_codec(struct azx *chip, int addr)
1346 {
1347         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1348                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1349         unsigned int res;
1350
1351         mutex_lock(&chip->bus->cmd_mutex);
1352         chip->probing = 1;
1353         azx_send_cmd(chip->bus, cmd);
1354         res = azx_get_response(chip->bus, addr);
1355         chip->probing = 0;
1356         mutex_unlock(&chip->bus->cmd_mutex);
1357         if (res == -1)
1358                 return -EIO;
1359         snd_printdd(SFX "codec #%d probed OK\n", addr);
1360         return 0;
1361 }
1362
1363 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1364                                  struct hda_pcm *cpcm);
1365 static void azx_stop_chip(struct azx *chip);
1366
1367 static void azx_bus_reset(struct hda_bus *bus)
1368 {
1369         struct azx *chip = bus->private_data;
1370
1371         bus->in_reset = 1;
1372         azx_stop_chip(chip);
1373         azx_init_chip(chip, 1);
1374 #ifdef CONFIG_PM
1375         if (chip->initialized) {
1376                 int i;
1377
1378                 for (i = 0; i < HDA_MAX_PCMS; i++)
1379                         snd_pcm_suspend_all(chip->pcm[i]);
1380                 snd_hda_suspend(chip->bus);
1381                 snd_hda_resume(chip->bus);
1382         }
1383 #endif
1384         bus->in_reset = 0;
1385 }
1386
1387 /*
1388  * Codec initialization
1389  */
1390
1391 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1392 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1393         [AZX_DRIVER_NVIDIA] = 8,
1394         [AZX_DRIVER_TERA] = 1,
1395 };
1396
1397 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1398 {
1399         struct hda_bus_template bus_temp;
1400         int c, codecs, err;
1401         int max_slots;
1402
1403         memset(&bus_temp, 0, sizeof(bus_temp));
1404         bus_temp.private_data = chip;
1405         bus_temp.modelname = model;
1406         bus_temp.pci = chip->pci;
1407         bus_temp.ops.command = azx_send_cmd;
1408         bus_temp.ops.get_response = azx_get_response;
1409         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1410         bus_temp.ops.bus_reset = azx_bus_reset;
1411 #ifdef CONFIG_SND_HDA_POWER_SAVE
1412         bus_temp.power_save = &power_save;
1413         bus_temp.ops.pm_notify = azx_power_notify;
1414 #endif
1415
1416         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1417         if (err < 0)
1418                 return err;
1419
1420         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1421                 chip->bus->needs_damn_long_delay = 1;
1422
1423         codecs = 0;
1424         max_slots = azx_max_codecs[chip->driver_type];
1425         if (!max_slots)
1426                 max_slots = AZX_DEFAULT_CODECS;
1427
1428         /* First try to probe all given codec slots */
1429         for (c = 0; c < max_slots; c++) {
1430                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1431                         if (probe_codec(chip, c) < 0) {
1432                                 /* Some BIOSen give you wrong codec addresses
1433                                  * that don't exist
1434                                  */
1435                                 snd_printk(KERN_WARNING SFX
1436                                            "Codec #%d probe error; "
1437                                            "disabling it...\n", c);
1438                                 chip->codec_mask &= ~(1 << c);
1439                                 /* More badly, accessing to a non-existing
1440                                  * codec often screws up the controller chip,
1441                                  * and disturbs the further communications.
1442                                  * Thus if an error occurs during probing,
1443                                  * better to reset the controller chip to
1444                                  * get back to the sanity state.
1445                                  */
1446                                 azx_stop_chip(chip);
1447                                 azx_init_chip(chip, 1);
1448                         }
1449                 }
1450         }
1451
1452         /* AMD chipsets often cause the communication stalls upon certain
1453          * sequence like the pin-detection.  It seems that forcing the synced
1454          * access works around the stall.  Grrr...
1455          */
1456         if (chip->pci->vendor == PCI_VENDOR_ID_AMD ||
1457             chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1458                 snd_printk(KERN_INFO SFX "Enable sync_write for AMD chipset\n");
1459                 chip->bus->sync_write = 1;
1460                 chip->bus->allow_bus_reset = 1;
1461         }
1462
1463         /* Then create codec instances */
1464         for (c = 0; c < max_slots; c++) {
1465                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1466                         struct hda_codec *codec;
1467                         err = snd_hda_codec_new(chip->bus, c, &codec);
1468                         if (err < 0)
1469                                 continue;
1470                         codec->beep_mode = chip->beep_mode;
1471                         codecs++;
1472                 }
1473         }
1474         if (!codecs) {
1475                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1476                 return -ENXIO;
1477         }
1478         return 0;
1479 }
1480
1481 /* configure each codec instance */
1482 static int __devinit azx_codec_configure(struct azx *chip)
1483 {
1484         struct hda_codec *codec;
1485         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1486                 snd_hda_codec_configure(codec);
1487         }
1488         return 0;
1489 }
1490
1491
1492 /*
1493  * PCM support
1494  */
1495
1496 /* assign a stream for the PCM */
1497 static inline struct azx_dev *
1498 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1499 {
1500         int dev, i, nums;
1501         struct azx_dev *res = NULL;
1502
1503         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1504                 dev = chip->playback_index_offset;
1505                 nums = chip->playback_streams;
1506         } else {
1507                 dev = chip->capture_index_offset;
1508                 nums = chip->capture_streams;
1509         }
1510         for (i = 0; i < nums; i++, dev++)
1511                 if (!chip->azx_dev[dev].opened) {
1512                         res = &chip->azx_dev[dev];
1513                         if (res->device == substream->pcm->device)
1514                                 break;
1515                 }
1516         if (res) {
1517                 res->opened = 1;
1518                 res->device = substream->pcm->device;
1519         }
1520         return res;
1521 }
1522
1523 /* release the assigned stream */
1524 static inline void azx_release_device(struct azx_dev *azx_dev)
1525 {
1526         azx_dev->opened = 0;
1527 }
1528
1529 static struct snd_pcm_hardware azx_pcm_hw = {
1530         .info =                 (SNDRV_PCM_INFO_MMAP |
1531                                  SNDRV_PCM_INFO_INTERLEAVED |
1532                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1533                                  SNDRV_PCM_INFO_MMAP_VALID |
1534                                  /* No full-resume yet implemented */
1535                                  /* SNDRV_PCM_INFO_RESUME |*/
1536                                  SNDRV_PCM_INFO_PAUSE |
1537                                  SNDRV_PCM_INFO_SYNC_START |
1538                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1539         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1540         .rates =                SNDRV_PCM_RATE_48000,
1541         .rate_min =             48000,
1542         .rate_max =             48000,
1543         .channels_min =         2,
1544         .channels_max =         2,
1545         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1546         .period_bytes_min =     128,
1547         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1548         .periods_min =          2,
1549         .periods_max =          AZX_MAX_FRAG,
1550         .fifo_size =            0,
1551 };
1552
1553 struct azx_pcm {
1554         struct azx *chip;
1555         struct hda_codec *codec;
1556         struct hda_pcm_stream *hinfo[2];
1557 };
1558
1559 static int azx_pcm_open(struct snd_pcm_substream *substream)
1560 {
1561         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1562         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1563         struct azx *chip = apcm->chip;
1564         struct azx_dev *azx_dev;
1565         struct snd_pcm_runtime *runtime = substream->runtime;
1566         unsigned long flags;
1567         int err;
1568
1569         mutex_lock(&chip->open_mutex);
1570         azx_dev = azx_assign_device(chip, substream);
1571         if (azx_dev == NULL) {
1572                 mutex_unlock(&chip->open_mutex);
1573                 return -EBUSY;
1574         }
1575         runtime->hw = azx_pcm_hw;
1576         runtime->hw.channels_min = hinfo->channels_min;
1577         runtime->hw.channels_max = hinfo->channels_max;
1578         runtime->hw.formats = hinfo->formats;
1579         runtime->hw.rates = hinfo->rates;
1580         snd_pcm_limit_hw_rates(runtime);
1581         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1582         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1583                                    128);
1584         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1585                                    128);
1586         snd_hda_power_up(apcm->codec);
1587         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1588         if (err < 0) {
1589                 azx_release_device(azx_dev);
1590                 snd_hda_power_down(apcm->codec);
1591                 mutex_unlock(&chip->open_mutex);
1592                 return err;
1593         }
1594         snd_pcm_limit_hw_rates(runtime);
1595         /* sanity check */
1596         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1597             snd_BUG_ON(!runtime->hw.channels_max) ||
1598             snd_BUG_ON(!runtime->hw.formats) ||
1599             snd_BUG_ON(!runtime->hw.rates)) {
1600                 azx_release_device(azx_dev);
1601                 hinfo->ops.close(hinfo, apcm->codec, substream);
1602                 snd_hda_power_down(apcm->codec);
1603                 mutex_unlock(&chip->open_mutex);
1604                 return -EINVAL;
1605         }
1606         spin_lock_irqsave(&chip->reg_lock, flags);
1607         azx_dev->substream = substream;
1608         azx_dev->running = 0;
1609         spin_unlock_irqrestore(&chip->reg_lock, flags);
1610
1611         runtime->private_data = azx_dev;
1612         snd_pcm_set_sync(substream);
1613         mutex_unlock(&chip->open_mutex);
1614         return 0;
1615 }
1616
1617 static int azx_pcm_close(struct snd_pcm_substream *substream)
1618 {
1619         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1620         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1621         struct azx *chip = apcm->chip;
1622         struct azx_dev *azx_dev = get_azx_dev(substream);
1623         unsigned long flags;
1624
1625         mutex_lock(&chip->open_mutex);
1626         spin_lock_irqsave(&chip->reg_lock, flags);
1627         azx_dev->substream = NULL;
1628         azx_dev->running = 0;
1629         spin_unlock_irqrestore(&chip->reg_lock, flags);
1630         azx_release_device(azx_dev);
1631         hinfo->ops.close(hinfo, apcm->codec, substream);
1632         snd_hda_power_down(apcm->codec);
1633         mutex_unlock(&chip->open_mutex);
1634         return 0;
1635 }
1636
1637 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1638                              struct snd_pcm_hw_params *hw_params)
1639 {
1640         struct azx_dev *azx_dev = get_azx_dev(substream);
1641
1642         azx_dev->bufsize = 0;
1643         azx_dev->period_bytes = 0;
1644         azx_dev->format_val = 0;
1645         return snd_pcm_lib_malloc_pages(substream,
1646                                         params_buffer_bytes(hw_params));
1647 }
1648
1649 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1650 {
1651         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1652         struct azx_dev *azx_dev = get_azx_dev(substream);
1653         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1654
1655         /* reset BDL address */
1656         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1657         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1658         azx_sd_writel(azx_dev, SD_CTL, 0);
1659         azx_dev->bufsize = 0;
1660         azx_dev->period_bytes = 0;
1661         azx_dev->format_val = 0;
1662
1663         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1664
1665         return snd_pcm_lib_free_pages(substream);
1666 }
1667
1668 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1669 {
1670         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1671         struct azx *chip = apcm->chip;
1672         struct azx_dev *azx_dev = get_azx_dev(substream);
1673         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1674         struct snd_pcm_runtime *runtime = substream->runtime;
1675         unsigned int bufsize, period_bytes, format_val, stream_tag;
1676         int err;
1677
1678         azx_stream_reset(chip, azx_dev);
1679         format_val = snd_hda_calc_stream_format(runtime->rate,
1680                                                 runtime->channels,
1681                                                 runtime->format,
1682                                                 hinfo->maxbps,
1683                                                 apcm->codec->spdif_ctls);
1684         if (!format_val) {
1685                 snd_printk(KERN_ERR SFX
1686                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1687                            runtime->rate, runtime->channels, runtime->format);
1688                 return -EINVAL;
1689         }
1690
1691         bufsize = snd_pcm_lib_buffer_bytes(substream);
1692         period_bytes = snd_pcm_lib_period_bytes(substream);
1693
1694         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1695                     bufsize, format_val);
1696
1697         if (bufsize != azx_dev->bufsize ||
1698             period_bytes != azx_dev->period_bytes ||
1699             format_val != azx_dev->format_val) {
1700                 azx_dev->bufsize = bufsize;
1701                 azx_dev->period_bytes = period_bytes;
1702                 azx_dev->format_val = format_val;
1703                 err = azx_setup_periods(chip, substream, azx_dev);
1704                 if (err < 0)
1705                         return err;
1706         }
1707
1708         /* wallclk has 24Mhz clock source */
1709         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1710                                                 runtime->rate) * 1000);
1711         azx_setup_controller(chip, azx_dev);
1712         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1713                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1714         else
1715                 azx_dev->fifo_size = 0;
1716
1717         stream_tag = azx_dev->stream_tag;
1718         /* CA-IBG chips need the playback stream starting from 1 */
1719         if (chip->driver_type == AZX_DRIVER_CTX &&
1720             stream_tag > chip->capture_streams)
1721                 stream_tag -= chip->capture_streams;
1722         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1723                                      azx_dev->format_val, substream);
1724 }
1725
1726 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1727 {
1728         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1729         struct azx *chip = apcm->chip;
1730         struct azx_dev *azx_dev;
1731         struct snd_pcm_substream *s;
1732         int rstart = 0, start, nsync = 0, sbits = 0;
1733         int nwait, timeout;
1734
1735         switch (cmd) {
1736         case SNDRV_PCM_TRIGGER_START:
1737                 rstart = 1;
1738         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1739         case SNDRV_PCM_TRIGGER_RESUME:
1740                 start = 1;
1741                 break;
1742         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1743         case SNDRV_PCM_TRIGGER_SUSPEND:
1744         case SNDRV_PCM_TRIGGER_STOP:
1745                 start = 0;
1746                 break;
1747         default:
1748                 return -EINVAL;
1749         }
1750
1751         snd_pcm_group_for_each_entry(s, substream) {
1752                 if (s->pcm->card != substream->pcm->card)
1753                         continue;
1754                 azx_dev = get_azx_dev(s);
1755                 sbits |= 1 << azx_dev->index;
1756                 nsync++;
1757                 snd_pcm_trigger_done(s, substream);
1758         }
1759
1760         spin_lock(&chip->reg_lock);
1761         if (nsync > 1) {
1762                 /* first, set SYNC bits of corresponding streams */
1763                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1764         }
1765         snd_pcm_group_for_each_entry(s, substream) {
1766                 if (s->pcm->card != substream->pcm->card)
1767                         continue;
1768                 azx_dev = get_azx_dev(s);
1769                 if (start) {
1770                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1771                         if (!rstart)
1772                                 azx_dev->start_wallclk -=
1773                                                 azx_dev->period_wallclk;
1774                         azx_stream_start(chip, azx_dev);
1775                 } else {
1776                         azx_stream_stop(chip, azx_dev);
1777                 }
1778                 azx_dev->running = start;
1779         }
1780         spin_unlock(&chip->reg_lock);
1781         if (start) {
1782                 if (nsync == 1)
1783                         return 0;
1784                 /* wait until all FIFOs get ready */
1785                 for (timeout = 5000; timeout; timeout--) {
1786                         nwait = 0;
1787                         snd_pcm_group_for_each_entry(s, substream) {
1788                                 if (s->pcm->card != substream->pcm->card)
1789                                         continue;
1790                                 azx_dev = get_azx_dev(s);
1791                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1792                                       SD_STS_FIFO_READY))
1793                                         nwait++;
1794                         }
1795                         if (!nwait)
1796                                 break;
1797                         cpu_relax();
1798                 }
1799         } else {
1800                 /* wait until all RUN bits are cleared */
1801                 for (timeout = 5000; timeout; timeout--) {
1802                         nwait = 0;
1803                         snd_pcm_group_for_each_entry(s, substream) {
1804                                 if (s->pcm->card != substream->pcm->card)
1805                                         continue;
1806                                 azx_dev = get_azx_dev(s);
1807                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1808                                     SD_CTL_DMA_START)
1809                                         nwait++;
1810                         }
1811                         if (!nwait)
1812                                 break;
1813                         cpu_relax();
1814                 }
1815         }
1816         if (nsync > 1) {
1817                 spin_lock(&chip->reg_lock);
1818                 /* reset SYNC bits */
1819                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1820                 spin_unlock(&chip->reg_lock);
1821         }
1822         return 0;
1823 }
1824
1825 /* get the current DMA position with correction on VIA chips */
1826 static unsigned int azx_via_get_position(struct azx *chip,
1827                                          struct azx_dev *azx_dev)
1828 {
1829         unsigned int link_pos, mini_pos, bound_pos;
1830         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1831         unsigned int fifo_size;
1832
1833         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1834         if (azx_dev->index >= 4) {
1835                 /* Playback, no problem using link position */
1836                 return link_pos;
1837         }
1838
1839         /* Capture */
1840         /* For new chipset,
1841          * use mod to get the DMA position just like old chipset
1842          */
1843         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1844         mod_dma_pos %= azx_dev->period_bytes;
1845
1846         /* azx_dev->fifo_size can't get FIFO size of in stream.
1847          * Get from base address + offset.
1848          */
1849         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1850
1851         if (azx_dev->insufficient) {
1852                 /* Link position never gather than FIFO size */
1853                 if (link_pos <= fifo_size)
1854                         return 0;
1855
1856                 azx_dev->insufficient = 0;
1857         }
1858
1859         if (link_pos <= fifo_size)
1860                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1861         else
1862                 mini_pos = link_pos - fifo_size;
1863
1864         /* Find nearest previous boudary */
1865         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1866         mod_link_pos = link_pos % azx_dev->period_bytes;
1867         if (mod_link_pos >= fifo_size)
1868                 bound_pos = link_pos - mod_link_pos;
1869         else if (mod_dma_pos >= mod_mini_pos)
1870                 bound_pos = mini_pos - mod_mini_pos;
1871         else {
1872                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1873                 if (bound_pos >= azx_dev->bufsize)
1874                         bound_pos = 0;
1875         }
1876
1877         /* Calculate real DMA position we want */
1878         return bound_pos + mod_dma_pos;
1879 }
1880
1881 static unsigned int azx_get_position(struct azx *chip,
1882                                      struct azx_dev *azx_dev)
1883 {
1884         unsigned int pos;
1885         int stream = azx_dev->substream->stream;
1886
1887         switch (chip->position_fix[stream]) {
1888         case POS_FIX_LPIB:
1889                 /* read LPIB */
1890                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1891                 break;
1892         case POS_FIX_VIACOMBO:
1893                 pos = azx_via_get_position(chip, azx_dev);
1894                 break;
1895         default:
1896                 /* use the position buffer */
1897                 pos = le32_to_cpu(*azx_dev->posbuf);
1898         }
1899
1900         if (pos >= azx_dev->bufsize)
1901                 pos = 0;
1902         return pos;
1903 }
1904
1905 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1906 {
1907         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1908         struct azx *chip = apcm->chip;
1909         struct azx_dev *azx_dev = get_azx_dev(substream);
1910         return bytes_to_frames(substream->runtime,
1911                                azx_get_position(chip, azx_dev));
1912 }
1913
1914 /*
1915  * Check whether the current DMA position is acceptable for updating
1916  * periods.  Returns non-zero if it's OK.
1917  *
1918  * Many HD-audio controllers appear pretty inaccurate about
1919  * the update-IRQ timing.  The IRQ is issued before actually the
1920  * data is processed.  So, we need to process it afterwords in a
1921  * workqueue.
1922  */
1923 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1924 {
1925         u32 wallclk;
1926         unsigned int pos;
1927         int stream;
1928
1929         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1930         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1931                 return -1;      /* bogus (too early) interrupt */
1932
1933         stream = azx_dev->substream->stream;
1934         pos = azx_get_position(chip, azx_dev);
1935         if (chip->position_fix[stream] == POS_FIX_AUTO) {
1936                 if (!pos) {
1937                         printk(KERN_WARNING
1938                                "hda-intel: Invalid position buffer, "
1939                                "using LPIB read method instead.\n");
1940                         chip->position_fix[stream] = POS_FIX_LPIB;
1941                         pos = azx_get_position(chip, azx_dev);
1942                 } else
1943                         chip->position_fix[stream] = POS_FIX_POSBUF;
1944         }
1945
1946         if (WARN_ONCE(!azx_dev->period_bytes,
1947                       "hda-intel: zero azx_dev->period_bytes"))
1948                 return -1; /* this shouldn't happen! */
1949         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1950             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1951                 /* NG - it's below the first next period boundary */
1952                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1953         azx_dev->start_wallclk += wallclk;
1954         return 1; /* OK, it's fine */
1955 }
1956
1957 /*
1958  * The work for pending PCM period updates.
1959  */
1960 static void azx_irq_pending_work(struct work_struct *work)
1961 {
1962         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1963         int i, pending, ok;
1964
1965         if (!chip->irq_pending_warned) {
1966                 printk(KERN_WARNING
1967                        "hda-intel: IRQ timing workaround is activated "
1968                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1969                        chip->card->number);
1970                 chip->irq_pending_warned = 1;
1971         }
1972
1973         for (;;) {
1974                 pending = 0;
1975                 spin_lock_irq(&chip->reg_lock);
1976                 for (i = 0; i < chip->num_streams; i++) {
1977                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1978                         if (!azx_dev->irq_pending ||
1979                             !azx_dev->substream ||
1980                             !azx_dev->running)
1981                                 continue;
1982                         ok = azx_position_ok(chip, azx_dev);
1983                         if (ok > 0) {
1984                                 azx_dev->irq_pending = 0;
1985                                 spin_unlock(&chip->reg_lock);
1986                                 snd_pcm_period_elapsed(azx_dev->substream);
1987                                 spin_lock(&chip->reg_lock);
1988                         } else if (ok < 0) {
1989                                 pending = 0;    /* too early */
1990                         } else
1991                                 pending++;
1992                 }
1993                 spin_unlock_irq(&chip->reg_lock);
1994                 if (!pending)
1995                         return;
1996                 msleep(1);
1997         }
1998 }
1999
2000 /* clear irq_pending flags and assure no on-going workq */
2001 static void azx_clear_irq_pending(struct azx *chip)
2002 {
2003         int i;
2004
2005         spin_lock_irq(&chip->reg_lock);
2006         for (i = 0; i < chip->num_streams; i++)
2007                 chip->azx_dev[i].irq_pending = 0;
2008         spin_unlock_irq(&chip->reg_lock);
2009 }
2010
2011 static struct snd_pcm_ops azx_pcm_ops = {
2012         .open = azx_pcm_open,
2013         .close = azx_pcm_close,
2014         .ioctl = snd_pcm_lib_ioctl,
2015         .hw_params = azx_pcm_hw_params,
2016         .hw_free = azx_pcm_hw_free,
2017         .prepare = azx_pcm_prepare,
2018         .trigger = azx_pcm_trigger,
2019         .pointer = azx_pcm_pointer,
2020         .page = snd_pcm_sgbuf_ops_page,
2021 };
2022
2023 static void azx_pcm_free(struct snd_pcm *pcm)
2024 {
2025         struct azx_pcm *apcm = pcm->private_data;
2026         if (apcm) {
2027                 apcm->chip->pcm[pcm->device] = NULL;
2028                 kfree(apcm);
2029         }
2030 }
2031
2032 static int
2033 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2034                       struct hda_pcm *cpcm)
2035 {
2036         struct azx *chip = bus->private_data;
2037         struct snd_pcm *pcm;
2038         struct azx_pcm *apcm;
2039         int pcm_dev = cpcm->device;
2040         int s, err;
2041         size_t prealloc_min = 64*1024;  /* 64KB */
2042
2043         if (pcm_dev >= HDA_MAX_PCMS) {
2044                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2045                            pcm_dev);
2046                 return -EINVAL;
2047         }
2048         if (chip->pcm[pcm_dev]) {
2049                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2050                 return -EBUSY;
2051         }
2052         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2053                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2054                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2055                           &pcm);
2056         if (err < 0)
2057                 return err;
2058         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2059         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2060         if (apcm == NULL)
2061                 return -ENOMEM;
2062         apcm->chip = chip;
2063         apcm->codec = codec;
2064         pcm->private_data = apcm;
2065         pcm->private_free = azx_pcm_free;
2066         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2067                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2068         chip->pcm[pcm_dev] = pcm;
2069         cpcm->pcm = pcm;
2070         for (s = 0; s < 2; s++) {
2071                 apcm->hinfo[s] = &cpcm->stream[s];
2072                 if (cpcm->stream[s].substreams)
2073                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2074         }
2075
2076         /* buffer pre-allocation */
2077
2078         /* subtle, don't allocate a big buffer for modems...
2079          * also, don't just test 32BIT_MASK, since azx supports
2080          * 64-bit DMA in some cases.
2081          */
2082         /* lennart wants a 2.2MB buffer for 2sec of 48khz */
2083         if (pcm->dev_class == SNDRV_PCM_CLASS_GENERIC &&
2084             chip->pci->dma_mask >= DMA_32BIT_MASK)
2085                 prealloc_min = 4 * 1024 * 1024; /* 4MB */
2086
2087         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2088                                               snd_dma_pci_data(chip->pci),
2089                                               prealloc_min, 32 * 1024 * 1024);
2090         return 0;
2091 }
2092
2093 /*
2094  * mixer creation - all stuff is implemented in hda module
2095  */
2096 static int __devinit azx_mixer_create(struct azx *chip)
2097 {
2098         return snd_hda_build_controls(chip->bus);
2099 }
2100
2101
2102 /*
2103  * initialize SD streams
2104  */
2105 static int __devinit azx_init_stream(struct azx *chip)
2106 {
2107         int i;
2108
2109         /* initialize each stream (aka device)
2110          * assign the starting bdl address to each stream (device)
2111          * and initialize
2112          */
2113         for (i = 0; i < chip->num_streams; i++) {
2114                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2115                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2116                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2117                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2118                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2119                 azx_dev->sd_int_sta_mask = 1 << i;
2120                 /* stream tag: must be non-zero and unique */
2121                 azx_dev->index = i;
2122                 azx_dev->stream_tag = i + 1;
2123         }
2124
2125         return 0;
2126 }
2127
2128 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2129 {
2130         if (request_irq(chip->pci->irq, azx_interrupt,
2131                         chip->msi ? 0 : IRQF_SHARED,
2132                         "hda_intel", chip)) {
2133                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2134                        "disabling device\n", chip->pci->irq);
2135                 if (do_disconnect)
2136                         snd_card_disconnect(chip->card);
2137                 return -1;
2138         }
2139         chip->irq = chip->pci->irq;
2140         pci_intx(chip->pci, !chip->msi);
2141         return 0;
2142 }
2143
2144
2145 static void azx_stop_chip(struct azx *chip)
2146 {
2147         if (!chip->initialized)
2148                 return;
2149
2150         /* disable interrupts */
2151         azx_int_disable(chip);
2152         azx_int_clear(chip);
2153
2154         /* disable CORB/RIRB */
2155         azx_free_cmd_io(chip);
2156
2157         /* disable position buffer */
2158         azx_writel(chip, DPLBASE, 0);
2159         azx_writel(chip, DPUBASE, 0);
2160
2161         chip->initialized = 0;
2162 }
2163
2164 #ifdef CONFIG_SND_HDA_POWER_SAVE
2165 /* power-up/down the controller */
2166 static void azx_power_notify(struct hda_bus *bus)
2167 {
2168         struct azx *chip = bus->private_data;
2169         struct hda_codec *c;
2170         int power_on = 0;
2171
2172         list_for_each_entry(c, &bus->codec_list, list) {
2173                 if (c->power_on) {
2174                         power_on = 1;
2175                         break;
2176                 }
2177         }
2178         if (power_on)
2179                 azx_init_chip(chip, 1);
2180         else if (chip->running && power_save_controller &&
2181                  !bus->power_keep_link_on)
2182                 azx_stop_chip(chip);
2183 }
2184 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2185
2186 #ifdef CONFIG_PM
2187 /*
2188  * power management
2189  */
2190
2191 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2192 {
2193         struct hda_codec *codec;
2194
2195         list_for_each_entry(codec, &bus->codec_list, list) {
2196                 if (snd_hda_codec_needs_resume(codec))
2197                         return 1;
2198         }
2199         return 0;
2200 }
2201
2202 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2203 {
2204         struct snd_card *card = pci_get_drvdata(pci);
2205         struct azx *chip = card->private_data;
2206         int i;
2207
2208         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2209         azx_clear_irq_pending(chip);
2210         for (i = 0; i < HDA_MAX_PCMS; i++)
2211                 snd_pcm_suspend_all(chip->pcm[i]);
2212         if (chip->initialized)
2213                 snd_hda_suspend(chip->bus);
2214         azx_stop_chip(chip);
2215         if (chip->irq >= 0) {
2216                 free_irq(chip->irq, chip);
2217                 chip->irq = -1;
2218         }
2219         if (chip->msi)
2220                 pci_disable_msi(chip->pci);
2221         pci_disable_device(pci);
2222         pci_save_state(pci);
2223         pci_set_power_state(pci, pci_choose_state(pci, state));
2224         return 0;
2225 }
2226
2227 static int azx_resume(struct pci_dev *pci)
2228 {
2229         struct snd_card *card = pci_get_drvdata(pci);
2230         struct azx *chip = card->private_data;
2231
2232         pci_set_power_state(pci, PCI_D0);
2233         pci_restore_state(pci);
2234         if (pci_enable_device(pci) < 0) {
2235                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2236                        "disabling device\n");
2237                 snd_card_disconnect(card);
2238                 return -EIO;
2239         }
2240         pci_set_master(pci);
2241         if (chip->msi)
2242                 if (pci_enable_msi(pci) < 0)
2243                         chip->msi = 0;
2244         if (azx_acquire_irq(chip, 1) < 0)
2245                 return -EIO;
2246         azx_init_pci(chip);
2247
2248         if (snd_hda_codecs_inuse(chip->bus))
2249                 azx_init_chip(chip, 1);
2250
2251         snd_hda_resume(chip->bus);
2252         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2253         return 0;
2254 }
2255 #endif /* CONFIG_PM */
2256
2257
2258 /*
2259  * reboot notifier for hang-up problem at power-down
2260  */
2261 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2262 {
2263         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2264         snd_hda_bus_reboot_notify(chip->bus);
2265         azx_stop_chip(chip);
2266         return NOTIFY_OK;
2267 }
2268
2269 static void azx_notifier_register(struct azx *chip)
2270 {
2271         chip->reboot_notifier.notifier_call = azx_halt;
2272         register_reboot_notifier(&chip->reboot_notifier);
2273 }
2274
2275 static void azx_notifier_unregister(struct azx *chip)
2276 {
2277         if (chip->reboot_notifier.notifier_call)
2278                 unregister_reboot_notifier(&chip->reboot_notifier);
2279 }
2280
2281 /*
2282  * destructor
2283  */
2284 static int azx_free(struct azx *chip)
2285 {
2286         int i;
2287
2288         azx_notifier_unregister(chip);
2289
2290         if (chip->initialized) {
2291                 azx_clear_irq_pending(chip);
2292                 for (i = 0; i < chip->num_streams; i++)
2293                         azx_stream_stop(chip, &chip->azx_dev[i]);
2294                 azx_stop_chip(chip);
2295         }
2296
2297         if (chip->irq >= 0)
2298                 free_irq(chip->irq, (void*)chip);
2299         if (chip->msi)
2300                 pci_disable_msi(chip->pci);
2301         if (chip->remap_addr)
2302                 iounmap(chip->remap_addr);
2303
2304         if (chip->azx_dev) {
2305                 for (i = 0; i < chip->num_streams; i++)
2306                         if (chip->azx_dev[i].bdl.area)
2307                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2308         }
2309         if (chip->rb.area)
2310                 snd_dma_free_pages(&chip->rb);
2311         if (chip->posbuf.area)
2312                 snd_dma_free_pages(&chip->posbuf);
2313         pci_release_regions(chip->pci);
2314         pci_disable_device(chip->pci);
2315         kfree(chip->azx_dev);
2316         kfree(chip);
2317
2318         return 0;
2319 }
2320
2321 static int azx_dev_free(struct snd_device *device)
2322 {
2323         return azx_free(device->device_data);
2324 }
2325
2326 /*
2327  * white/black-listing for position_fix
2328  */
2329 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2330         SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2331         SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
2332         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2333         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2334         SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2335         SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2336         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2337         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2338         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2339         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2340         SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB),
2341         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2342         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2343         SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2344         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2345         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2346         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2347         SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2348         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2349         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2350         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2351         SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2352         {}
2353 };
2354
2355 static int __devinit check_position_fix(struct azx *chip, int fix)
2356 {
2357         const struct snd_pci_quirk *q;
2358
2359         switch (fix) {
2360         case POS_FIX_LPIB:
2361         case POS_FIX_POSBUF:
2362         case POS_FIX_VIACOMBO:
2363                 return fix;
2364         }
2365
2366         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2367         if (q) {
2368                 printk(KERN_INFO
2369                        "hda_intel: position_fix set to %d "
2370                        "for device %04x:%04x\n",
2371                        q->value, q->subvendor, q->subdevice);
2372                 return q->value;
2373         }
2374
2375         /* Check VIA/ATI HD Audio Controller exist */
2376         switch (chip->driver_type) {
2377         case AZX_DRIVER_VIA:
2378                 /* Use link position directly, avoid any transfer problem. */
2379                 return POS_FIX_VIACOMBO;
2380         case AZX_DRIVER_ATI:
2381                 /* ATI chipsets don't work well with position-buffer */
2382                 return POS_FIX_LPIB;
2383         case AZX_DRIVER_GENERIC:
2384                 /* AMD chipsets also don't work with position-buffer */
2385                 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
2386                         return POS_FIX_LPIB;
2387                 break;
2388         }
2389
2390         return POS_FIX_AUTO;
2391 }
2392
2393 /*
2394  * black-lists for probe_mask
2395  */
2396 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2397         /* Thinkpad often breaks the controller communication when accessing
2398          * to the non-working (or non-existing) modem codec slot.
2399          */
2400         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2401         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2402         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2403         /* broken BIOS */
2404         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2405         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2406         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2407         /* forced codec slots */
2408         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2409         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2410         {}
2411 };
2412
2413 #define AZX_FORCE_CODEC_MASK    0x100
2414
2415 static void __devinit check_probe_mask(struct azx *chip, int dev)
2416 {
2417         const struct snd_pci_quirk *q;
2418
2419         chip->codec_probe_mask = probe_mask[dev];
2420         if (chip->codec_probe_mask == -1) {
2421                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2422                 if (q) {
2423                         printk(KERN_INFO
2424                                "hda_intel: probe_mask set to 0x%x "
2425                                "for device %04x:%04x\n",
2426                                q->value, q->subvendor, q->subdevice);
2427                         chip->codec_probe_mask = q->value;
2428                 }
2429         }
2430
2431         /* check forced option */
2432         if (chip->codec_probe_mask != -1 &&
2433             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2434                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2435                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2436                        chip->codec_mask);
2437         }
2438 }
2439
2440 /*
2441  * white/black-list for enable_msi
2442  */
2443 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2444         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2445         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2446         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2447         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2448         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2449         {}
2450 };
2451
2452 static void __devinit check_msi(struct azx *chip)
2453 {
2454         const struct snd_pci_quirk *q;
2455
2456         if (enable_msi >= 0) {
2457                 chip->msi = !!enable_msi;
2458                 return;
2459         }
2460         chip->msi = 1;  /* enable MSI as default */
2461         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2462         if (q) {
2463                 printk(KERN_INFO
2464                        "hda_intel: msi for device %04x:%04x set to %d\n",
2465                        q->subvendor, q->subdevice, q->value);
2466                 chip->msi = q->value;
2467                 return;
2468         }
2469
2470         /* NVidia chipsets seem to cause troubles with MSI */
2471         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2472                 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2473                 chip->msi = 0;
2474         }
2475 }
2476
2477
2478 /*
2479  * constructor
2480  */
2481 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2482                                 int dev, int driver_type,
2483                                 struct azx **rchip)
2484 {
2485         struct azx *chip;
2486         int i, err;
2487         unsigned short gcap;
2488         static struct snd_device_ops ops = {
2489                 .dev_free = azx_dev_free,
2490         };
2491
2492         *rchip = NULL;
2493
2494         err = pci_enable_device(pci);
2495         if (err < 0)
2496                 return err;
2497
2498         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2499         if (!chip) {
2500                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2501                 pci_disable_device(pci);
2502                 return -ENOMEM;
2503         }
2504
2505         spin_lock_init(&chip->reg_lock);
2506         mutex_init(&chip->open_mutex);
2507         chip->card = card;
2508         chip->pci = pci;
2509         chip->irq = -1;
2510         chip->driver_type = driver_type;
2511         check_msi(chip);
2512         chip->dev_index = dev;
2513         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2514
2515         chip->position_fix[0] = chip->position_fix[1] =
2516                 check_position_fix(chip, position_fix[dev]);
2517         check_probe_mask(chip, dev);
2518
2519         chip->single_cmd = single_cmd;
2520
2521         if (bdl_pos_adj[dev] < 0) {
2522                 switch (chip->driver_type) {
2523                 case AZX_DRIVER_ICH:
2524                 case AZX_DRIVER_PCH:
2525                         bdl_pos_adj[dev] = 1;
2526                         break;
2527                 default:
2528                         bdl_pos_adj[dev] = 32;
2529                         break;
2530                 }
2531         }
2532
2533 #if BITS_PER_LONG != 64
2534         /* Fix up base address on ULI M5461 */
2535         if (chip->driver_type == AZX_DRIVER_ULI) {
2536                 u16 tmp3;
2537                 pci_read_config_word(pci, 0x40, &tmp3);
2538                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2539                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2540         }
2541 #endif
2542
2543         err = pci_request_regions(pci, "ICH HD audio");
2544         if (err < 0) {
2545                 kfree(chip);
2546                 pci_disable_device(pci);
2547                 return err;
2548         }
2549
2550         chip->addr = pci_resource_start(pci, 0);
2551         chip->remap_addr = pci_ioremap_bar(pci, 0);
2552         if (chip->remap_addr == NULL) {
2553                 snd_printk(KERN_ERR SFX "ioremap error\n");
2554                 err = -ENXIO;
2555                 goto errout;
2556         }
2557
2558         if (chip->msi)
2559                 if (pci_enable_msi(pci) < 0)
2560                         chip->msi = 0;
2561
2562         if (azx_acquire_irq(chip, 0) < 0) {
2563                 err = -EBUSY;
2564                 goto errout;
2565         }
2566
2567         pci_set_master(pci);
2568         synchronize_irq(chip->irq);
2569
2570         gcap = azx_readw(chip, GCAP);
2571         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2572
2573         /* disable SB600 64bit support for safety */
2574         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2575             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2576                 struct pci_dev *p_smbus;
2577                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2578                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2579                                          NULL);
2580                 if (p_smbus) {
2581                         if (p_smbus->revision < 0x30)
2582                                 gcap &= ~ICH6_GCAP_64OK;
2583                         pci_dev_put(p_smbus);
2584                 }
2585         } else {
2586                 /* FIXME: not sure whether this is really needed, but
2587                  * Hudson isn't stable enough for allowing everything...
2588                  * let's check later again.
2589                  */
2590                 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
2591                         gcap &= ~ICH6_GCAP_64OK;
2592         }
2593
2594         /* disable 64bit DMA address for Teradici */
2595         /* it does not work with device 6549:1200 subsys e4a2:040b */
2596         if (chip->driver_type == AZX_DRIVER_TERA)
2597                 gcap &= ~ICH6_GCAP_64OK;
2598
2599         /* allow 64bit DMA address if supported by H/W */
2600         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2601                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2602         else {
2603                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2604                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2605         }
2606
2607         /* read number of streams from GCAP register instead of using
2608          * hardcoded value
2609          */
2610         chip->capture_streams = (gcap >> 8) & 0x0f;
2611         chip->playback_streams = (gcap >> 12) & 0x0f;
2612         if (!chip->playback_streams && !chip->capture_streams) {
2613                 /* gcap didn't give any info, switching to old method */
2614
2615                 switch (chip->driver_type) {
2616                 case AZX_DRIVER_ULI:
2617                         chip->playback_streams = ULI_NUM_PLAYBACK;
2618                         chip->capture_streams = ULI_NUM_CAPTURE;
2619                         break;
2620                 case AZX_DRIVER_ATIHDMI:
2621                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2622                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2623                         break;
2624                 case AZX_DRIVER_GENERIC:
2625                 default:
2626                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2627                         chip->capture_streams = ICH6_NUM_CAPTURE;
2628                         break;
2629                 }
2630         }
2631         chip->capture_index_offset = 0;
2632         chip->playback_index_offset = chip->capture_streams;
2633         chip->num_streams = chip->playback_streams + chip->capture_streams;
2634         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2635                                 GFP_KERNEL);
2636         if (!chip->azx_dev) {
2637                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2638                 goto errout;
2639         }
2640
2641         for (i = 0; i < chip->num_streams; i++) {
2642                 /* allocate memory for the BDL for each stream */
2643                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2644                                           snd_dma_pci_data(chip->pci),
2645                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2646                 if (err < 0) {
2647                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2648                         goto errout;
2649                 }
2650         }
2651         /* allocate memory for the position buffer */
2652         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2653                                   snd_dma_pci_data(chip->pci),
2654                                   chip->num_streams * 8, &chip->posbuf);
2655         if (err < 0) {
2656                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2657                 goto errout;
2658         }
2659         /* allocate CORB/RIRB */
2660         err = azx_alloc_cmd_io(chip);
2661         if (err < 0)
2662                 goto errout;
2663
2664         /* initialize streams */
2665         azx_init_stream(chip);
2666
2667         /* initialize chip */
2668         azx_init_pci(chip);
2669         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2670
2671         /* codec detection */
2672         if (!chip->codec_mask) {
2673                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2674                 err = -ENODEV;
2675                 goto errout;
2676         }
2677
2678         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2679         if (err <0) {
2680                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2681                 goto errout;
2682         }
2683
2684         strcpy(card->driver, "HDA-Intel");
2685         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2686                 sizeof(card->shortname));
2687         snprintf(card->longname, sizeof(card->longname),
2688                  "%s at 0x%lx irq %i",
2689                  card->shortname, chip->addr, chip->irq);
2690
2691         *rchip = chip;
2692         return 0;
2693
2694  errout:
2695         azx_free(chip);
2696         return err;
2697 }
2698
2699 static void power_down_all_codecs(struct azx *chip)
2700 {
2701 #ifdef CONFIG_SND_HDA_POWER_SAVE
2702         /* The codecs were powered up in snd_hda_codec_new().
2703          * Now all initialization done, so turn them down if possible
2704          */
2705         struct hda_codec *codec;
2706         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2707                 snd_hda_power_down(codec);
2708         }
2709 #endif
2710 }
2711
2712 static int __devinit azx_probe(struct pci_dev *pci,
2713                                const struct pci_device_id *pci_id)
2714 {
2715         static int dev;
2716         struct snd_card *card;
2717         struct azx *chip;
2718         int err;
2719
2720         if (dev >= SNDRV_CARDS)
2721                 return -ENODEV;
2722         if (!enable[dev]) {
2723                 dev++;
2724                 return -ENOENT;
2725         }
2726
2727         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2728         if (err < 0) {
2729                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2730                 return err;
2731         }
2732
2733         /* set this here since it's referred in snd_hda_load_patch() */
2734         snd_card_set_dev(card, &pci->dev);
2735
2736         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2737         if (err < 0)
2738                 goto out_free;
2739         card->private_data = chip;
2740
2741 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2742         chip->beep_mode = beep_mode[dev];
2743 #endif
2744
2745         /* create codec instances */
2746         err = azx_codec_create(chip, model[dev]);
2747         if (err < 0)
2748                 goto out_free;
2749 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2750         if (patch[dev] && *patch[dev]) {
2751                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2752                            patch[dev]);
2753                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2754                 if (err < 0)
2755                         goto out_free;
2756         }
2757 #endif
2758         if ((probe_only[dev] & 1) == 0) {
2759                 err = azx_codec_configure(chip);
2760                 if (err < 0)
2761                         goto out_free;
2762         }
2763
2764         /* create PCM streams */
2765         err = snd_hda_build_pcms(chip->bus);
2766         if (err < 0)
2767                 goto out_free;
2768
2769         /* create mixer controls */
2770         err = azx_mixer_create(chip);
2771         if (err < 0)
2772                 goto out_free;
2773
2774         err = snd_card_register(card);
2775         if (err < 0)
2776                 goto out_free;
2777
2778         pci_set_drvdata(pci, card);
2779         chip->running = 1;
2780         power_down_all_codecs(chip);
2781         azx_notifier_register(chip);
2782
2783         dev++;
2784         return err;
2785 out_free:
2786         snd_card_free(card);
2787         return err;
2788 }
2789
2790 static void __devexit azx_remove(struct pci_dev *pci)
2791 {
2792         snd_card_free(pci_get_drvdata(pci));
2793         pci_set_drvdata(pci, NULL);
2794 }
2795
2796 /* PCI IDs */
2797 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2798         /* CPT */
2799         { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2800         /* PBG */
2801         { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
2802         /* SCH */
2803         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2804         /* Generic Intel */
2805         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2806           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2807           .class_mask = 0xffffff,
2808           .driver_data = AZX_DRIVER_ICH },
2809         /* ATI SB 450/600 */
2810         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2811         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2812         /* ATI HDMI */
2813         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2814         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2815         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2816         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2817         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2818         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2819         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2820         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2821         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2822         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2823         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2824         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2825         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2826         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2827         /* VIA VT8251/VT8237A */
2828         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2829         /* SIS966 */
2830         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2831         /* ULI M5461 */
2832         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2833         /* NVIDIA MCP */
2834         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2835           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2836           .class_mask = 0xffffff,
2837           .driver_data = AZX_DRIVER_NVIDIA },
2838         /* Teradici */
2839         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2840         /* Creative X-Fi (CA0110-IBG) */
2841 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2842         /* the following entry conflicts with snd-ctxfi driver,
2843          * as ctxfi driver mutates from HD-audio to native mode with
2844          * a special command sequence.
2845          */
2846         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2847           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2848           .class_mask = 0xffffff,
2849           .driver_data = AZX_DRIVER_CTX },
2850 #else
2851         /* this entry seems still valid -- i.e. without emu20kx chip */
2852         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
2853 #endif
2854         /* Vortex86MX */
2855         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2856         /* VMware HDAudio */
2857         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2858         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2859         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2860           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2861           .class_mask = 0xffffff,
2862           .driver_data = AZX_DRIVER_GENERIC },
2863         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2864           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2865           .class_mask = 0xffffff,
2866           .driver_data = AZX_DRIVER_GENERIC },
2867         { 0, }
2868 };
2869 MODULE_DEVICE_TABLE(pci, azx_ids);
2870
2871 /* pci_driver definition */
2872 static struct pci_driver driver = {
2873         .name = "HDA Intel",
2874         .id_table = azx_ids,
2875         .probe = azx_probe,
2876         .remove = __devexit_p(azx_remove),
2877 #ifdef CONFIG_PM
2878         .suspend = azx_suspend,
2879         .resume = azx_resume,
2880 #endif
2881 };
2882
2883 static int __init alsa_card_azx_init(void)
2884 {
2885         return pci_register_driver(&driver);
2886 }
2887
2888 static void __exit alsa_card_azx_exit(void)
2889 {
2890         pci_unregister_driver(&driver);
2891 }
2892
2893 module_init(alsa_card_azx_init)
2894 module_exit(alsa_card_azx_exit)