2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/byteorder.h>
43 #include <asm/system.h>
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
70 __le32 branch_address;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
81 struct descriptor descriptor;
82 struct ar_buffer *next;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
92 struct tasklet_struct tasklet;
97 typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *last);
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
110 struct descriptor buffer[0];
114 struct fw_ohci *ohci;
116 int total_allocation;
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
123 struct list_head buffer_list;
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
129 struct descriptor_buffer *buffer_tail;
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
135 struct descriptor *last;
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
141 struct descriptor *prev;
143 descriptor_callback_t callback;
145 struct tasklet_struct tasklet;
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
156 struct fw_iso_context base;
157 struct context context;
160 size_t header_length;
163 #define CONFIG_ROM_SIZE 1024
168 __iomem char *registers;
171 int request_generation; /* for timestamping incoming requests */
175 * Spinlock for accessing fw_ohci data. Never call out of
176 * this driver with this lock held.
180 struct ar_context ar_request_ctx;
181 struct ar_context ar_response_ctx;
182 struct context at_request_ctx;
183 struct context at_response_ctx;
186 struct iso_context *it_context_list;
187 u64 ir_context_channels;
189 struct iso_context *ir_context_list;
192 dma_addr_t config_rom_bus;
193 __be32 *next_config_rom;
194 dma_addr_t next_config_rom_bus;
198 dma_addr_t self_id_bus;
199 struct tasklet_struct bus_reset_tasklet;
201 u32 self_id_buffer[512];
204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
206 return container_of(card, struct fw_ohci, card);
209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
210 #define IR_CONTEXT_BUFFER_FILL 0x80000000
211 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
213 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
214 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
216 #define CONTEXT_RUN 0x8000
217 #define CONTEXT_WAKE 0x1000
218 #define CONTEXT_DEAD 0x0800
219 #define CONTEXT_ACTIVE 0x0400
221 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
222 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
223 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
225 #define OHCI1394_REGISTER_SIZE 0x800
226 #define OHCI_LOOP_COUNT 500
227 #define OHCI1394_PCI_HCI_Control 0x40
228 #define SELF_ID_BUF_SIZE 0x800
229 #define OHCI_TCODE_PHY_PACKET 0x0e
230 #define OHCI_VERSION_1_1 0x010010
232 static char ohci_driver_name[] = KBUILD_MODNAME;
234 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
235 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
237 #define QUIRK_CYCLE_TIMER 1
238 #define QUIRK_RESET_PACKET 2
239 #define QUIRK_BE_HEADERS 4
240 #define QUIRK_NO_1394A 8
241 #define QUIRK_NO_MSI 16
243 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
244 static const struct {
245 unsigned short vendor, device, flags;
247 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
250 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
251 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
252 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
253 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
254 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
255 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
258 /* This overrides anything that was found in ohci_quirks[]. */
259 static int param_quirks;
260 module_param_named(quirks, param_quirks, int, 0644);
261 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
262 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
263 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
264 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
265 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
266 ", disable MSI = " __stringify(QUIRK_NO_MSI)
269 #define OHCI_PARAM_DEBUG_AT_AR 1
270 #define OHCI_PARAM_DEBUG_SELFIDS 2
271 #define OHCI_PARAM_DEBUG_IRQS 4
272 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
274 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
276 static int param_debug;
277 module_param_named(debug, param_debug, int, 0644);
278 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
279 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
280 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
281 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
282 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
283 ", or a combination, or all = -1)");
285 static void log_irqs(u32 evt)
287 if (likely(!(param_debug &
288 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
291 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
292 !(evt & OHCI1394_busReset))
295 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
296 evt & OHCI1394_selfIDComplete ? " selfID" : "",
297 evt & OHCI1394_RQPkt ? " AR_req" : "",
298 evt & OHCI1394_RSPkt ? " AR_resp" : "",
299 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
300 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
301 evt & OHCI1394_isochRx ? " IR" : "",
302 evt & OHCI1394_isochTx ? " IT" : "",
303 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
304 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
305 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
306 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
307 evt & OHCI1394_busReset ? " busReset" : "",
308 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
309 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
310 OHCI1394_respTxComplete | OHCI1394_isochRx |
311 OHCI1394_isochTx | OHCI1394_postedWriteErr |
312 OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
313 OHCI1394_regAccessFail | OHCI1394_busReset)
317 static const char *speed[] = {
318 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
320 static const char *power[] = {
321 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
322 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
324 static const char port[] = { '.', '-', 'p', 'c', };
326 static char _p(u32 *s, int shift)
328 return port[*s >> shift & 3];
331 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
333 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
336 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
337 self_id_count, generation, node_id);
339 for (; self_id_count--; ++s)
340 if ((*s & 1 << 23) == 0)
341 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
342 "%s gc=%d %s %s%s%s\n",
343 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
344 speed[*s >> 14 & 3], *s >> 16 & 63,
345 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
346 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
348 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
350 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
351 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
354 static const char *evts[] = {
355 [0x00] = "evt_no_status", [0x01] = "-reserved-",
356 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
357 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
358 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
359 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
360 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
361 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
362 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
363 [0x10] = "-reserved-", [0x11] = "ack_complete",
364 [0x12] = "ack_pending ", [0x13] = "-reserved-",
365 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
366 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
367 [0x18] = "-reserved-", [0x19] = "-reserved-",
368 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
369 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
370 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
371 [0x20] = "pending/cancelled",
373 static const char *tcodes[] = {
374 [0x0] = "QW req", [0x1] = "BW req",
375 [0x2] = "W resp", [0x3] = "-reserved-",
376 [0x4] = "QR req", [0x5] = "BR req",
377 [0x6] = "QR resp", [0x7] = "BR resp",
378 [0x8] = "cycle start", [0x9] = "Lk req",
379 [0xa] = "async stream packet", [0xb] = "Lk resp",
380 [0xc] = "-reserved-", [0xd] = "-reserved-",
381 [0xe] = "link internal", [0xf] = "-reserved-",
383 static const char *phys[] = {
384 [0x0] = "phy config packet", [0x1] = "link-on packet",
385 [0x2] = "self-id packet", [0x3] = "-reserved-",
388 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
390 int tcode = header[0] >> 4 & 0xf;
393 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
396 if (unlikely(evt >= ARRAY_SIZE(evts)))
399 if (evt == OHCI1394_evt_bus_reset) {
400 fw_notify("A%c evt_bus_reset, generation %d\n",
401 dir, (header[2] >> 16) & 0xff);
405 if (header[0] == ~header[1]) {
406 fw_notify("A%c %s, %s, %08x\n",
407 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
412 case 0x0: case 0x6: case 0x8:
413 snprintf(specific, sizeof(specific), " = %08x",
414 be32_to_cpu((__force __be32)header[3]));
416 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
417 snprintf(specific, sizeof(specific), " %x,%x",
418 header[3] >> 16, header[3] & 0xffff);
426 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
428 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
429 fw_notify("A%c spd %x tl %02x, "
432 dir, speed, header[0] >> 10 & 0x3f,
433 header[1] >> 16, header[0] >> 16, evts[evt],
434 tcodes[tcode], header[1] & 0xffff, header[2], specific);
437 fw_notify("A%c spd %x tl %02x, "
440 dir, speed, header[0] >> 10 & 0x3f,
441 header[1] >> 16, header[0] >> 16, evts[evt],
442 tcodes[tcode], specific);
448 #define param_debug 0
449 static inline void log_irqs(u32 evt) {}
450 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
451 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
453 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
455 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
457 writel(data, ohci->registers + offset);
460 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
462 return readl(ohci->registers + offset);
465 static inline void flush_writes(const struct fw_ohci *ohci)
467 /* Do a dummy read to flush writes. */
468 reg_read(ohci, OHCI1394_Version);
471 static int read_phy_reg(struct fw_ohci *ohci, int addr)
476 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
477 for (i = 0; i < 10; i++) {
478 val = reg_read(ohci, OHCI1394_PhyControl);
479 if (val & OHCI1394_PhyControl_ReadDone)
480 return OHCI1394_PhyControl_ReadData(val);
484 fw_error("failed to read phy reg\n");
489 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
493 reg_write(ohci, OHCI1394_PhyControl,
494 OHCI1394_PhyControl_Write(addr, val));
495 for (i = 0; i < 100; i++) {
496 val = reg_read(ohci, OHCI1394_PhyControl);
497 if (!(val & OHCI1394_PhyControl_WritePending))
502 fw_error("failed to write phy reg\n");
507 static int ohci_update_phy_reg(struct fw_card *card, int addr,
508 int clear_bits, int set_bits)
510 struct fw_ohci *ohci = fw_ohci(card);
513 ret = read_phy_reg(ohci, addr);
518 * The interrupt status bits are cleared by writing a one bit.
519 * Avoid clearing them unless explicitly requested in set_bits.
522 clear_bits |= PHY_INT_STATUS_BITS;
524 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
527 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
531 ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
535 return read_phy_reg(ohci, addr);
538 static int ar_context_add_page(struct ar_context *ctx)
540 struct device *dev = ctx->ohci->card.device;
541 struct ar_buffer *ab;
542 dma_addr_t uninitialized_var(ab_bus);
545 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
550 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
551 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
553 DESCRIPTOR_BRANCH_ALWAYS);
554 offset = offsetof(struct ar_buffer, data);
555 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
556 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
557 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
558 ab->descriptor.branch_address = 0;
560 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
561 ctx->last_buffer->next = ab;
562 ctx->last_buffer = ab;
564 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
565 flush_writes(ctx->ohci);
570 static void ar_context_release(struct ar_context *ctx)
572 struct ar_buffer *ab, *ab_next;
576 for (ab = ctx->current_buffer; ab; ab = ab_next) {
578 offset = offsetof(struct ar_buffer, data);
579 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
580 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
585 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
586 #define cond_le32_to_cpu(v) \
587 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
589 #define cond_le32_to_cpu(v) le32_to_cpu(v)
592 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
594 struct fw_ohci *ohci = ctx->ohci;
596 u32 status, length, tcode;
599 p.header[0] = cond_le32_to_cpu(buffer[0]);
600 p.header[1] = cond_le32_to_cpu(buffer[1]);
601 p.header[2] = cond_le32_to_cpu(buffer[2]);
603 tcode = (p.header[0] >> 4) & 0x0f;
605 case TCODE_WRITE_QUADLET_REQUEST:
606 case TCODE_READ_QUADLET_RESPONSE:
607 p.header[3] = (__force __u32) buffer[3];
608 p.header_length = 16;
609 p.payload_length = 0;
612 case TCODE_READ_BLOCK_REQUEST :
613 p.header[3] = cond_le32_to_cpu(buffer[3]);
614 p.header_length = 16;
615 p.payload_length = 0;
618 case TCODE_WRITE_BLOCK_REQUEST:
619 case TCODE_READ_BLOCK_RESPONSE:
620 case TCODE_LOCK_REQUEST:
621 case TCODE_LOCK_RESPONSE:
622 p.header[3] = cond_le32_to_cpu(buffer[3]);
623 p.header_length = 16;
624 p.payload_length = p.header[3] >> 16;
627 case TCODE_WRITE_RESPONSE:
628 case TCODE_READ_QUADLET_REQUEST:
629 case OHCI_TCODE_PHY_PACKET:
630 p.header_length = 12;
631 p.payload_length = 0;
635 /* FIXME: Stop context, discard everything, and restart? */
637 p.payload_length = 0;
640 p.payload = (void *) buffer + p.header_length;
642 /* FIXME: What to do about evt_* errors? */
643 length = (p.header_length + p.payload_length + 3) / 4;
644 status = cond_le32_to_cpu(buffer[length]);
645 evt = (status >> 16) & 0x1f;
648 p.speed = (status >> 21) & 0x7;
649 p.timestamp = status & 0xffff;
650 p.generation = ohci->request_generation;
652 log_ar_at_event('R', p.speed, p.header, evt);
655 * The OHCI bus reset handler synthesizes a phy packet with
656 * the new generation number when a bus reset happens (see
657 * section 8.4.2.3). This helps us determine when a request
658 * was received and make sure we send the response in the same
659 * generation. We only need this for requests; for responses
660 * we use the unique tlabel for finding the matching
663 * Alas some chips sometimes emit bus reset packets with a
664 * wrong generation. We set the correct generation for these
665 * at a slightly incorrect time (in bus_reset_tasklet).
667 if (evt == OHCI1394_evt_bus_reset) {
668 if (!(ohci->quirks & QUIRK_RESET_PACKET))
669 ohci->request_generation = (p.header[2] >> 16) & 0xff;
670 } else if (ctx == &ohci->ar_request_ctx) {
671 fw_core_handle_request(&ohci->card, &p);
673 fw_core_handle_response(&ohci->card, &p);
676 return buffer + length + 1;
679 static void ar_context_tasklet(unsigned long data)
681 struct ar_context *ctx = (struct ar_context *)data;
682 struct fw_ohci *ohci = ctx->ohci;
683 struct ar_buffer *ab;
684 struct descriptor *d;
687 ab = ctx->current_buffer;
690 if (d->res_count == 0) {
691 size_t size, rest, offset;
692 dma_addr_t start_bus;
696 * This descriptor is finished and we may have a
697 * packet split across this and the next buffer. We
698 * reuse the page for reassembling the split packet.
701 offset = offsetof(struct ar_buffer, data);
703 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
707 size = buffer + PAGE_SIZE - ctx->pointer;
708 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
709 memmove(buffer, ctx->pointer, size);
710 memcpy(buffer + size, ab->data, rest);
711 ctx->current_buffer = ab;
712 ctx->pointer = (void *) ab->data + rest;
713 end = buffer + size + rest;
716 buffer = handle_ar_packet(ctx, buffer);
718 dma_free_coherent(ohci->card.device, PAGE_SIZE,
720 ar_context_add_page(ctx);
722 buffer = ctx->pointer;
724 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
727 buffer = handle_ar_packet(ctx, buffer);
731 static int ar_context_init(struct ar_context *ctx,
732 struct fw_ohci *ohci, u32 regs)
738 ctx->last_buffer = &ab;
739 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
741 ar_context_add_page(ctx);
742 ar_context_add_page(ctx);
743 ctx->current_buffer = ab.next;
744 ctx->pointer = ctx->current_buffer->data;
749 static void ar_context_run(struct ar_context *ctx)
751 struct ar_buffer *ab = ctx->current_buffer;
755 offset = offsetof(struct ar_buffer, data);
756 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
758 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
759 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
760 flush_writes(ctx->ohci);
763 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
767 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
768 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
770 /* figure out which descriptor the branch address goes in */
771 if (z == 2 && (b == 3 || key == 2))
777 static void context_tasklet(unsigned long data)
779 struct context *ctx = (struct context *) data;
780 struct descriptor *d, *last;
783 struct descriptor_buffer *desc;
785 desc = list_entry(ctx->buffer_list.next,
786 struct descriptor_buffer, list);
788 while (last->branch_address != 0) {
789 struct descriptor_buffer *old_desc = desc;
790 address = le32_to_cpu(last->branch_address);
794 /* If the branch address points to a buffer outside of the
795 * current buffer, advance to the next buffer. */
796 if (address < desc->buffer_bus ||
797 address >= desc->buffer_bus + desc->used)
798 desc = list_entry(desc->list.next,
799 struct descriptor_buffer, list);
800 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
801 last = find_branch_descriptor(d, z);
803 if (!ctx->callback(ctx, d, last))
806 if (old_desc != desc) {
807 /* If we've advanced to the next buffer, move the
808 * previous buffer to the free list. */
811 spin_lock_irqsave(&ctx->ohci->lock, flags);
812 list_move_tail(&old_desc->list, &ctx->buffer_list);
813 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
820 * Allocate a new buffer and add it to the list of free buffers for this
821 * context. Must be called with ohci->lock held.
823 static int context_add_buffer(struct context *ctx)
825 struct descriptor_buffer *desc;
826 dma_addr_t uninitialized_var(bus_addr);
830 * 16MB of descriptors should be far more than enough for any DMA
831 * program. This will catch run-away userspace or DoS attacks.
833 if (ctx->total_allocation >= 16*1024*1024)
836 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
837 &bus_addr, GFP_ATOMIC);
841 offset = (void *)&desc->buffer - (void *)desc;
842 desc->buffer_size = PAGE_SIZE - offset;
843 desc->buffer_bus = bus_addr + offset;
846 list_add_tail(&desc->list, &ctx->buffer_list);
847 ctx->total_allocation += PAGE_SIZE;
852 static int context_init(struct context *ctx, struct fw_ohci *ohci,
853 u32 regs, descriptor_callback_t callback)
857 ctx->total_allocation = 0;
859 INIT_LIST_HEAD(&ctx->buffer_list);
860 if (context_add_buffer(ctx) < 0)
863 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
864 struct descriptor_buffer, list);
866 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
867 ctx->callback = callback;
870 * We put a dummy descriptor in the buffer that has a NULL
871 * branch address and looks like it's been sent. That way we
872 * have a descriptor to append DMA programs to.
874 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
875 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
876 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
877 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
878 ctx->last = ctx->buffer_tail->buffer;
879 ctx->prev = ctx->buffer_tail->buffer;
884 static void context_release(struct context *ctx)
886 struct fw_card *card = &ctx->ohci->card;
887 struct descriptor_buffer *desc, *tmp;
889 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
890 dma_free_coherent(card->device, PAGE_SIZE, desc,
892 ((void *)&desc->buffer - (void *)desc));
895 /* Must be called with ohci->lock held */
896 static struct descriptor *context_get_descriptors(struct context *ctx,
897 int z, dma_addr_t *d_bus)
899 struct descriptor *d = NULL;
900 struct descriptor_buffer *desc = ctx->buffer_tail;
902 if (z * sizeof(*d) > desc->buffer_size)
905 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
906 /* No room for the descriptor in this buffer, so advance to the
909 if (desc->list.next == &ctx->buffer_list) {
910 /* If there is no free buffer next in the list,
912 if (context_add_buffer(ctx) < 0)
915 desc = list_entry(desc->list.next,
916 struct descriptor_buffer, list);
917 ctx->buffer_tail = desc;
920 d = desc->buffer + desc->used / sizeof(*d);
921 memset(d, 0, z * sizeof(*d));
922 *d_bus = desc->buffer_bus + desc->used;
927 static void context_run(struct context *ctx, u32 extra)
929 struct fw_ohci *ohci = ctx->ohci;
931 reg_write(ohci, COMMAND_PTR(ctx->regs),
932 le32_to_cpu(ctx->last->branch_address));
933 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
934 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
938 static void context_append(struct context *ctx,
939 struct descriptor *d, int z, int extra)
942 struct descriptor_buffer *desc = ctx->buffer_tail;
944 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
946 desc->used += (z + extra) * sizeof(*d);
947 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
948 ctx->prev = find_branch_descriptor(d, z);
950 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
951 flush_writes(ctx->ohci);
954 static void context_stop(struct context *ctx)
959 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
960 flush_writes(ctx->ohci);
962 for (i = 0; i < 10; i++) {
963 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
964 if ((reg & CONTEXT_ACTIVE) == 0)
969 fw_error("Error: DMA context still active (0x%08x)\n", reg);
973 struct fw_packet *packet;
977 * This function apppends a packet to the DMA queue for transmission.
978 * Must always be called with the ochi->lock held to ensure proper
979 * generation handling and locking around packet queue manipulation.
981 static int at_context_queue_packet(struct context *ctx,
982 struct fw_packet *packet)
984 struct fw_ohci *ohci = ctx->ohci;
985 dma_addr_t d_bus, uninitialized_var(payload_bus);
986 struct driver_data *driver_data;
987 struct descriptor *d, *last;
992 d = context_get_descriptors(ctx, 4, &d_bus);
994 packet->ack = RCODE_SEND_ERROR;
998 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
999 d[0].res_count = cpu_to_le16(packet->timestamp);
1002 * The DMA format for asyncronous link packets is different
1003 * from the IEEE1394 layout, so shift the fields around
1004 * accordingly. If header_length is 8, it's a PHY packet, to
1005 * which we need to prepend an extra quadlet.
1008 header = (__le32 *) &d[1];
1009 switch (packet->header_length) {
1012 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1013 (packet->speed << 16));
1014 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1015 (packet->header[0] & 0xffff0000));
1016 header[2] = cpu_to_le32(packet->header[2]);
1018 tcode = (packet->header[0] >> 4) & 0x0f;
1019 if (TCODE_IS_BLOCK_PACKET(tcode))
1020 header[3] = cpu_to_le32(packet->header[3]);
1022 header[3] = (__force __le32) packet->header[3];
1024 d[0].req_count = cpu_to_le16(packet->header_length);
1028 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1029 (packet->speed << 16));
1030 header[1] = cpu_to_le32(packet->header[0]);
1031 header[2] = cpu_to_le32(packet->header[1]);
1032 d[0].req_count = cpu_to_le16(12);
1036 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1037 (packet->speed << 16));
1038 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1039 d[0].req_count = cpu_to_le16(8);
1044 packet->ack = RCODE_SEND_ERROR;
1048 driver_data = (struct driver_data *) &d[3];
1049 driver_data->packet = packet;
1050 packet->driver_data = driver_data;
1052 if (packet->payload_length > 0) {
1054 dma_map_single(ohci->card.device, packet->payload,
1055 packet->payload_length, DMA_TO_DEVICE);
1056 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1057 packet->ack = RCODE_SEND_ERROR;
1060 packet->payload_bus = payload_bus;
1061 packet->payload_mapped = true;
1063 d[2].req_count = cpu_to_le16(packet->payload_length);
1064 d[2].data_address = cpu_to_le32(payload_bus);
1072 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1073 DESCRIPTOR_IRQ_ALWAYS |
1074 DESCRIPTOR_BRANCH_ALWAYS);
1077 * If the controller and packet generations don't match, we need to
1078 * bail out and try again. If IntEvent.busReset is set, the AT context
1079 * is halted, so appending to the context and trying to run it is
1080 * futile. Most controllers do the right thing and just flush the AT
1081 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1082 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1083 * up stalling out. So we just bail out in software and try again
1084 * later, and everyone is happy.
1085 * FIXME: Document how the locking works.
1087 if (ohci->generation != packet->generation ||
1088 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1089 if (packet->payload_mapped)
1090 dma_unmap_single(ohci->card.device, payload_bus,
1091 packet->payload_length, DMA_TO_DEVICE);
1092 packet->ack = RCODE_GENERATION;
1096 context_append(ctx, d, z, 4 - z);
1098 /* If the context isn't already running, start it up. */
1099 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1100 if ((reg & CONTEXT_RUN) == 0)
1101 context_run(ctx, 0);
1106 static int handle_at_packet(struct context *context,
1107 struct descriptor *d,
1108 struct descriptor *last)
1110 struct driver_data *driver_data;
1111 struct fw_packet *packet;
1112 struct fw_ohci *ohci = context->ohci;
1115 if (last->transfer_status == 0)
1116 /* This descriptor isn't done yet, stop iteration. */
1119 driver_data = (struct driver_data *) &d[3];
1120 packet = driver_data->packet;
1122 /* This packet was cancelled, just continue. */
1125 if (packet->payload_mapped)
1126 dma_unmap_single(ohci->card.device, packet->payload_bus,
1127 packet->payload_length, DMA_TO_DEVICE);
1129 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1130 packet->timestamp = le16_to_cpu(last->res_count);
1132 log_ar_at_event('T', packet->speed, packet->header, evt);
1135 case OHCI1394_evt_timeout:
1136 /* Async response transmit timed out. */
1137 packet->ack = RCODE_CANCELLED;
1140 case OHCI1394_evt_flushed:
1142 * The packet was flushed should give same error as
1143 * when we try to use a stale generation count.
1145 packet->ack = RCODE_GENERATION;
1148 case OHCI1394_evt_missing_ack:
1150 * Using a valid (current) generation count, but the
1151 * node is not on the bus or not sending acks.
1153 packet->ack = RCODE_NO_ACK;
1156 case ACK_COMPLETE + 0x10:
1157 case ACK_PENDING + 0x10:
1158 case ACK_BUSY_X + 0x10:
1159 case ACK_BUSY_A + 0x10:
1160 case ACK_BUSY_B + 0x10:
1161 case ACK_DATA_ERROR + 0x10:
1162 case ACK_TYPE_ERROR + 0x10:
1163 packet->ack = evt - 0x10;
1167 packet->ack = RCODE_SEND_ERROR;
1171 packet->callback(packet, &ohci->card, packet->ack);
1176 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1177 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1178 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1179 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1180 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1182 static void handle_local_rom(struct fw_ohci *ohci,
1183 struct fw_packet *packet, u32 csr)
1185 struct fw_packet response;
1186 int tcode, length, i;
1188 tcode = HEADER_GET_TCODE(packet->header[0]);
1189 if (TCODE_IS_BLOCK_PACKET(tcode))
1190 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1194 i = csr - CSR_CONFIG_ROM;
1195 if (i + length > CONFIG_ROM_SIZE) {
1196 fw_fill_response(&response, packet->header,
1197 RCODE_ADDRESS_ERROR, NULL, 0);
1198 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1199 fw_fill_response(&response, packet->header,
1200 RCODE_TYPE_ERROR, NULL, 0);
1202 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1203 (void *) ohci->config_rom + i, length);
1206 fw_core_handle_response(&ohci->card, &response);
1209 static void handle_local_lock(struct fw_ohci *ohci,
1210 struct fw_packet *packet, u32 csr)
1212 struct fw_packet response;
1213 int tcode, length, ext_tcode, sel;
1214 __be32 *payload, lock_old;
1215 u32 lock_arg, lock_data;
1217 tcode = HEADER_GET_TCODE(packet->header[0]);
1218 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1219 payload = packet->payload;
1220 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1222 if (tcode == TCODE_LOCK_REQUEST &&
1223 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1224 lock_arg = be32_to_cpu(payload[0]);
1225 lock_data = be32_to_cpu(payload[1]);
1226 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1230 fw_fill_response(&response, packet->header,
1231 RCODE_TYPE_ERROR, NULL, 0);
1235 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1236 reg_write(ohci, OHCI1394_CSRData, lock_data);
1237 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1238 reg_write(ohci, OHCI1394_CSRControl, sel);
1240 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1241 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1243 fw_notify("swap not done yet\n");
1245 fw_fill_response(&response, packet->header,
1246 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1248 fw_core_handle_response(&ohci->card, &response);
1251 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1256 if (ctx == &ctx->ohci->at_request_ctx) {
1257 packet->ack = ACK_PENDING;
1258 packet->callback(packet, &ctx->ohci->card, packet->ack);
1262 ((unsigned long long)
1263 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1265 csr = offset - CSR_REGISTER_BASE;
1267 /* Handle config rom reads. */
1268 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1269 handle_local_rom(ctx->ohci, packet, csr);
1271 case CSR_BUS_MANAGER_ID:
1272 case CSR_BANDWIDTH_AVAILABLE:
1273 case CSR_CHANNELS_AVAILABLE_HI:
1274 case CSR_CHANNELS_AVAILABLE_LO:
1275 handle_local_lock(ctx->ohci, packet, csr);
1278 if (ctx == &ctx->ohci->at_request_ctx)
1279 fw_core_handle_request(&ctx->ohci->card, packet);
1281 fw_core_handle_response(&ctx->ohci->card, packet);
1285 if (ctx == &ctx->ohci->at_response_ctx) {
1286 packet->ack = ACK_COMPLETE;
1287 packet->callback(packet, &ctx->ohci->card, packet->ack);
1291 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1293 unsigned long flags;
1296 spin_lock_irqsave(&ctx->ohci->lock, flags);
1298 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1299 ctx->ohci->generation == packet->generation) {
1300 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1301 handle_local_request(ctx, packet);
1305 ret = at_context_queue_packet(ctx, packet);
1306 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1309 packet->callback(packet, &ctx->ohci->card, packet->ack);
1313 static void bus_reset_tasklet(unsigned long data)
1315 struct fw_ohci *ohci = (struct fw_ohci *)data;
1316 int self_id_count, i, j, reg;
1317 int generation, new_generation;
1318 unsigned long flags;
1319 void *free_rom = NULL;
1320 dma_addr_t free_rom_bus = 0;
1322 reg = reg_read(ohci, OHCI1394_NodeID);
1323 if (!(reg & OHCI1394_NodeID_idValid)) {
1324 fw_notify("node ID not valid, new bus reset in progress\n");
1327 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1328 fw_notify("malconfigured bus\n");
1331 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1332 OHCI1394_NodeID_nodeNumber);
1334 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1335 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1336 fw_notify("inconsistent self IDs\n");
1340 * The count in the SelfIDCount register is the number of
1341 * bytes in the self ID receive buffer. Since we also receive
1342 * the inverted quadlets and a header quadlet, we shift one
1343 * bit extra to get the actual number of self IDs.
1345 self_id_count = (reg >> 3) & 0xff;
1346 if (self_id_count == 0 || self_id_count > 252) {
1347 fw_notify("inconsistent self IDs\n");
1350 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1353 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1354 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1355 fw_notify("inconsistent self IDs\n");
1358 ohci->self_id_buffer[j] =
1359 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1364 * Check the consistency of the self IDs we just read. The
1365 * problem we face is that a new bus reset can start while we
1366 * read out the self IDs from the DMA buffer. If this happens,
1367 * the DMA buffer will be overwritten with new self IDs and we
1368 * will read out inconsistent data. The OHCI specification
1369 * (section 11.2) recommends a technique similar to
1370 * linux/seqlock.h, where we remember the generation of the
1371 * self IDs in the buffer before reading them out and compare
1372 * it to the current generation after reading them out. If
1373 * the two generations match we know we have a consistent set
1377 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1378 if (new_generation != generation) {
1379 fw_notify("recursive bus reset detected, "
1380 "discarding self ids\n");
1384 /* FIXME: Document how the locking works. */
1385 spin_lock_irqsave(&ohci->lock, flags);
1387 ohci->generation = generation;
1388 context_stop(&ohci->at_request_ctx);
1389 context_stop(&ohci->at_response_ctx);
1390 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1392 if (ohci->quirks & QUIRK_RESET_PACKET)
1393 ohci->request_generation = generation;
1396 * This next bit is unrelated to the AT context stuff but we
1397 * have to do it under the spinlock also. If a new config rom
1398 * was set up before this reset, the old one is now no longer
1399 * in use and we can free it. Update the config rom pointers
1400 * to point to the current config rom and clear the
1401 * next_config_rom pointer so a new udpate can take place.
1404 if (ohci->next_config_rom != NULL) {
1405 if (ohci->next_config_rom != ohci->config_rom) {
1406 free_rom = ohci->config_rom;
1407 free_rom_bus = ohci->config_rom_bus;
1409 ohci->config_rom = ohci->next_config_rom;
1410 ohci->config_rom_bus = ohci->next_config_rom_bus;
1411 ohci->next_config_rom = NULL;
1414 * Restore config_rom image and manually update
1415 * config_rom registers. Writing the header quadlet
1416 * will indicate that the config rom is ready, so we
1419 reg_write(ohci, OHCI1394_BusOptions,
1420 be32_to_cpu(ohci->config_rom[2]));
1421 ohci->config_rom[0] = ohci->next_header;
1422 reg_write(ohci, OHCI1394_ConfigROMhdr,
1423 be32_to_cpu(ohci->next_header));
1426 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1427 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1428 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1431 spin_unlock_irqrestore(&ohci->lock, flags);
1434 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1435 free_rom, free_rom_bus);
1437 log_selfids(ohci->node_id, generation,
1438 self_id_count, ohci->self_id_buffer);
1440 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1441 self_id_count, ohci->self_id_buffer);
1444 static irqreturn_t irq_handler(int irq, void *data)
1446 struct fw_ohci *ohci = data;
1447 u32 event, iso_event;
1450 event = reg_read(ohci, OHCI1394_IntEventClear);
1452 if (!event || !~event)
1455 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1456 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1459 if (event & OHCI1394_selfIDComplete)
1460 tasklet_schedule(&ohci->bus_reset_tasklet);
1462 if (event & OHCI1394_RQPkt)
1463 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1465 if (event & OHCI1394_RSPkt)
1466 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1468 if (event & OHCI1394_reqTxComplete)
1469 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1471 if (event & OHCI1394_respTxComplete)
1472 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1474 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1475 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1478 i = ffs(iso_event) - 1;
1479 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1480 iso_event &= ~(1 << i);
1483 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1484 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1487 i = ffs(iso_event) - 1;
1488 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1489 iso_event &= ~(1 << i);
1492 if (unlikely(event & OHCI1394_regAccessFail))
1493 fw_error("Register access failure - "
1494 "please notify linux1394-devel@lists.sf.net\n");
1496 if (unlikely(event & OHCI1394_postedWriteErr))
1497 fw_error("PCI posted write error\n");
1499 if (unlikely(event & OHCI1394_cycleTooLong)) {
1500 if (printk_ratelimit())
1501 fw_notify("isochronous cycle too long\n");
1502 reg_write(ohci, OHCI1394_LinkControlSet,
1503 OHCI1394_LinkControl_cycleMaster);
1506 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1508 * We need to clear this event bit in order to make
1509 * cycleMatch isochronous I/O work. In theory we should
1510 * stop active cycleMatch iso contexts now and restart
1511 * them at least two cycles later. (FIXME?)
1513 if (printk_ratelimit())
1514 fw_notify("isochronous cycle inconsistent\n");
1520 static int software_reset(struct fw_ohci *ohci)
1524 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1526 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1527 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1528 OHCI1394_HCControl_softReset) == 0)
1536 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1538 size_t size = length * 4;
1540 memcpy(dest, src, size);
1541 if (size < CONFIG_ROM_SIZE)
1542 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1545 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1548 int ret, clear, set, offset;
1550 /* Check if the driver should configure link and PHY. */
1551 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1552 OHCI1394_HCControl_programPhyEnable))
1555 /* Paranoia: check whether the PHY supports 1394a, too. */
1556 enable_1394a = false;
1557 ret = read_phy_reg(ohci, 2);
1560 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1561 ret = read_paged_phy_reg(ohci, 1, 8);
1565 enable_1394a = true;
1568 if (ohci->quirks & QUIRK_NO_1394A)
1569 enable_1394a = false;
1571 /* Configure PHY and link consistently. */
1574 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1576 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1579 ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1584 offset = OHCI1394_HCControlSet;
1586 offset = OHCI1394_HCControlClear;
1587 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1589 /* Clean up: configuration has been taken care of. */
1590 reg_write(ohci, OHCI1394_HCControlClear,
1591 OHCI1394_HCControl_programPhyEnable);
1596 static int ohci_enable(struct fw_card *card,
1597 const __be32 *config_rom, size_t length)
1599 struct fw_ohci *ohci = fw_ohci(card);
1600 struct pci_dev *dev = to_pci_dev(card->device);
1604 if (software_reset(ohci)) {
1605 fw_error("Failed to reset ohci card.\n");
1610 * Now enable LPS, which we need in order to start accessing
1611 * most of the registers. In fact, on some cards (ALI M5251),
1612 * accessing registers in the SClk domain without LPS enabled
1613 * will lock up the machine. Wait 50msec to make sure we have
1614 * full link enabled. However, with some cards (well, at least
1615 * a JMicron PCIe card), we have to try again sometimes.
1617 reg_write(ohci, OHCI1394_HCControlSet,
1618 OHCI1394_HCControl_LPS |
1619 OHCI1394_HCControl_postedWriteEnable);
1622 for (lps = 0, i = 0; !lps && i < 3; i++) {
1624 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1625 OHCI1394_HCControl_LPS;
1629 fw_error("Failed to set Link Power Status\n");
1633 reg_write(ohci, OHCI1394_HCControlClear,
1634 OHCI1394_HCControl_noByteSwapData);
1636 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1637 reg_write(ohci, OHCI1394_LinkControlClear,
1638 OHCI1394_LinkControl_rcvPhyPkt);
1639 reg_write(ohci, OHCI1394_LinkControlSet,
1640 OHCI1394_LinkControl_rcvSelfID |
1641 OHCI1394_LinkControl_cycleTimerEnable |
1642 OHCI1394_LinkControl_cycleMaster);
1644 reg_write(ohci, OHCI1394_ATRetries,
1645 OHCI1394_MAX_AT_REQ_RETRIES |
1646 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1647 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1649 ar_context_run(&ohci->ar_request_ctx);
1650 ar_context_run(&ohci->ar_response_ctx);
1652 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1653 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1654 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1656 ret = configure_1394a_enhancements(ohci);
1660 /* Activate link_on bit and contender bit in our self ID packets.*/
1661 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1666 * When the link is not yet enabled, the atomic config rom
1667 * update mechanism described below in ohci_set_config_rom()
1668 * is not active. We have to update ConfigRomHeader and
1669 * BusOptions manually, and the write to ConfigROMmap takes
1670 * effect immediately. We tie this to the enabling of the
1671 * link, so we have a valid config rom before enabling - the
1672 * OHCI requires that ConfigROMhdr and BusOptions have valid
1673 * values before enabling.
1675 * However, when the ConfigROMmap is written, some controllers
1676 * always read back quadlets 0 and 2 from the config rom to
1677 * the ConfigRomHeader and BusOptions registers on bus reset.
1678 * They shouldn't do that in this initial case where the link
1679 * isn't enabled. This means we have to use the same
1680 * workaround here, setting the bus header to 0 and then write
1681 * the right values in the bus reset tasklet.
1685 ohci->next_config_rom =
1686 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1687 &ohci->next_config_rom_bus,
1689 if (ohci->next_config_rom == NULL)
1692 copy_config_rom(ohci->next_config_rom, config_rom, length);
1695 * In the suspend case, config_rom is NULL, which
1696 * means that we just reuse the old config rom.
1698 ohci->next_config_rom = ohci->config_rom;
1699 ohci->next_config_rom_bus = ohci->config_rom_bus;
1702 ohci->next_header = ohci->next_config_rom[0];
1703 ohci->next_config_rom[0] = 0;
1704 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1705 reg_write(ohci, OHCI1394_BusOptions,
1706 be32_to_cpu(ohci->next_config_rom[2]));
1707 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1709 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1711 if (!(ohci->quirks & QUIRK_NO_MSI))
1712 pci_enable_msi(dev);
1713 if (request_irq(dev->irq, irq_handler,
1714 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1715 ohci_driver_name, ohci)) {
1716 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1717 pci_disable_msi(dev);
1718 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1719 ohci->config_rom, ohci->config_rom_bus);
1723 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1724 OHCI1394_RQPkt | OHCI1394_RSPkt |
1725 OHCI1394_isochTx | OHCI1394_isochRx |
1726 OHCI1394_postedWriteErr |
1727 OHCI1394_selfIDComplete |
1728 OHCI1394_regAccessFail |
1729 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1730 OHCI1394_masterIntEnable;
1731 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1732 irqs |= OHCI1394_busReset;
1733 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1735 reg_write(ohci, OHCI1394_HCControlSet,
1736 OHCI1394_HCControl_linkEnable |
1737 OHCI1394_HCControl_BIBimageValid);
1741 * We are ready to go, initiate bus reset to finish the
1745 fw_core_initiate_bus_reset(&ohci->card, 1);
1750 static int ohci_set_config_rom(struct fw_card *card,
1751 const __be32 *config_rom, size_t length)
1753 struct fw_ohci *ohci;
1754 unsigned long flags;
1756 __be32 *next_config_rom;
1757 dma_addr_t uninitialized_var(next_config_rom_bus);
1759 ohci = fw_ohci(card);
1762 * When the OHCI controller is enabled, the config rom update
1763 * mechanism is a bit tricky, but easy enough to use. See
1764 * section 5.5.6 in the OHCI specification.
1766 * The OHCI controller caches the new config rom address in a
1767 * shadow register (ConfigROMmapNext) and needs a bus reset
1768 * for the changes to take place. When the bus reset is
1769 * detected, the controller loads the new values for the
1770 * ConfigRomHeader and BusOptions registers from the specified
1771 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1772 * shadow register. All automatically and atomically.
1774 * Now, there's a twist to this story. The automatic load of
1775 * ConfigRomHeader and BusOptions doesn't honor the
1776 * noByteSwapData bit, so with a be32 config rom, the
1777 * controller will load be32 values in to these registers
1778 * during the atomic update, even on litte endian
1779 * architectures. The workaround we use is to put a 0 in the
1780 * header quadlet; 0 is endian agnostic and means that the
1781 * config rom isn't ready yet. In the bus reset tasklet we
1782 * then set up the real values for the two registers.
1784 * We use ohci->lock to avoid racing with the code that sets
1785 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1789 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1790 &next_config_rom_bus, GFP_KERNEL);
1791 if (next_config_rom == NULL)
1794 spin_lock_irqsave(&ohci->lock, flags);
1796 if (ohci->next_config_rom == NULL) {
1797 ohci->next_config_rom = next_config_rom;
1798 ohci->next_config_rom_bus = next_config_rom_bus;
1800 copy_config_rom(ohci->next_config_rom, config_rom, length);
1802 ohci->next_header = config_rom[0];
1803 ohci->next_config_rom[0] = 0;
1805 reg_write(ohci, OHCI1394_ConfigROMmap,
1806 ohci->next_config_rom_bus);
1810 spin_unlock_irqrestore(&ohci->lock, flags);
1813 * Now initiate a bus reset to have the changes take
1814 * effect. We clean up the old config rom memory and DMA
1815 * mappings in the bus reset tasklet, since the OHCI
1816 * controller could need to access it before the bus reset
1820 fw_core_initiate_bus_reset(&ohci->card, 1);
1822 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1823 next_config_rom, next_config_rom_bus);
1828 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1830 struct fw_ohci *ohci = fw_ohci(card);
1832 at_context_transmit(&ohci->at_request_ctx, packet);
1835 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1837 struct fw_ohci *ohci = fw_ohci(card);
1839 at_context_transmit(&ohci->at_response_ctx, packet);
1842 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1844 struct fw_ohci *ohci = fw_ohci(card);
1845 struct context *ctx = &ohci->at_request_ctx;
1846 struct driver_data *driver_data = packet->driver_data;
1849 tasklet_disable(&ctx->tasklet);
1851 if (packet->ack != 0)
1854 if (packet->payload_mapped)
1855 dma_unmap_single(ohci->card.device, packet->payload_bus,
1856 packet->payload_length, DMA_TO_DEVICE);
1858 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1859 driver_data->packet = NULL;
1860 packet->ack = RCODE_CANCELLED;
1861 packet->callback(packet, &ohci->card, packet->ack);
1864 tasklet_enable(&ctx->tasklet);
1869 static int ohci_enable_phys_dma(struct fw_card *card,
1870 int node_id, int generation)
1872 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1875 struct fw_ohci *ohci = fw_ohci(card);
1876 unsigned long flags;
1880 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1881 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1884 spin_lock_irqsave(&ohci->lock, flags);
1886 if (ohci->generation != generation) {
1892 * Note, if the node ID contains a non-local bus ID, physical DMA is
1893 * enabled for _all_ nodes on remote buses.
1896 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1898 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1900 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1904 spin_unlock_irqrestore(&ohci->lock, flags);
1907 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1910 static u32 cycle_timer_ticks(u32 cycle_timer)
1914 ticks = cycle_timer & 0xfff;
1915 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1916 ticks += (3072 * 8000) * (cycle_timer >> 25);
1922 * Some controllers exhibit one or more of the following bugs when updating the
1923 * iso cycle timer register:
1924 * - When the lowest six bits are wrapping around to zero, a read that happens
1925 * at the same time will return garbage in the lowest ten bits.
1926 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1927 * not incremented for about 60 ns.
1928 * - Occasionally, the entire register reads zero.
1930 * To catch these, we read the register three times and ensure that the
1931 * difference between each two consecutive reads is approximately the same, i.e.
1932 * less than twice the other. Furthermore, any negative difference indicates an
1933 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1934 * execute, so we have enough precision to compute the ratio of the differences.)
1936 static u32 ohci_get_cycle_time(struct fw_card *card)
1938 struct fw_ohci *ohci = fw_ohci(card);
1944 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1946 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1949 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1953 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1954 t0 = cycle_timer_ticks(c0);
1955 t1 = cycle_timer_ticks(c1);
1956 t2 = cycle_timer_ticks(c2);
1959 } while ((diff01 <= 0 || diff12 <= 0 ||
1960 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1967 static void copy_iso_headers(struct iso_context *ctx, void *p)
1969 int i = ctx->header_length;
1971 if (i + ctx->base.header_size > PAGE_SIZE)
1975 * The iso header is byteswapped to little endian by
1976 * the controller, but the remaining header quadlets
1977 * are big endian. We want to present all the headers
1978 * as big endian, so we have to swap the first quadlet.
1980 if (ctx->base.header_size > 0)
1981 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1982 if (ctx->base.header_size > 4)
1983 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1984 if (ctx->base.header_size > 8)
1985 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1986 ctx->header_length += ctx->base.header_size;
1989 static int handle_ir_packet_per_buffer(struct context *context,
1990 struct descriptor *d,
1991 struct descriptor *last)
1993 struct iso_context *ctx =
1994 container_of(context, struct iso_context, context);
1995 struct descriptor *pd;
1999 for (pd = d; pd <= last; pd++) {
2000 if (pd->transfer_status)
2004 /* Descriptor(s) not done yet, stop iteration */
2008 copy_iso_headers(ctx, p);
2010 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2011 ir_header = (__le32 *) p;
2012 ctx->base.callback(&ctx->base,
2013 le32_to_cpu(ir_header[0]) & 0xffff,
2014 ctx->header_length, ctx->header,
2015 ctx->base.callback_data);
2016 ctx->header_length = 0;
2022 static int handle_it_packet(struct context *context,
2023 struct descriptor *d,
2024 struct descriptor *last)
2026 struct iso_context *ctx =
2027 container_of(context, struct iso_context, context);
2029 struct descriptor *pd;
2031 for (pd = d; pd <= last; pd++)
2032 if (pd->transfer_status)
2035 /* Descriptor(s) not done yet, stop iteration */
2038 i = ctx->header_length;
2039 if (i + 4 < PAGE_SIZE) {
2040 /* Present this value as big-endian to match the receive code */
2041 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2042 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2043 le16_to_cpu(pd->res_count));
2044 ctx->header_length += 4;
2046 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2047 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2048 ctx->header_length, ctx->header,
2049 ctx->base.callback_data);
2050 ctx->header_length = 0;
2055 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2056 int type, int channel, size_t header_size)
2058 struct fw_ohci *ohci = fw_ohci(card);
2059 struct iso_context *ctx, *list;
2060 descriptor_callback_t callback;
2061 u64 *channels, dont_care = ~0ULL;
2063 unsigned long flags;
2064 int index, ret = -ENOMEM;
2066 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2067 channels = &dont_care;
2068 mask = &ohci->it_context_mask;
2069 list = ohci->it_context_list;
2070 callback = handle_it_packet;
2072 channels = &ohci->ir_context_channels;
2073 mask = &ohci->ir_context_mask;
2074 list = ohci->ir_context_list;
2075 callback = handle_ir_packet_per_buffer;
2078 spin_lock_irqsave(&ohci->lock, flags);
2079 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2081 *channels &= ~(1ULL << channel);
2082 *mask &= ~(1 << index);
2084 spin_unlock_irqrestore(&ohci->lock, flags);
2087 return ERR_PTR(-EBUSY);
2089 if (type == FW_ISO_CONTEXT_TRANSMIT)
2090 regs = OHCI1394_IsoXmitContextBase(index);
2092 regs = OHCI1394_IsoRcvContextBase(index);
2095 memset(ctx, 0, sizeof(*ctx));
2096 ctx->header_length = 0;
2097 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2098 if (ctx->header == NULL)
2101 ret = context_init(&ctx->context, ohci, regs, callback);
2103 goto out_with_header;
2108 free_page((unsigned long)ctx->header);
2110 spin_lock_irqsave(&ohci->lock, flags);
2111 *mask |= 1 << index;
2112 spin_unlock_irqrestore(&ohci->lock, flags);
2114 return ERR_PTR(ret);
2117 static int ohci_start_iso(struct fw_iso_context *base,
2118 s32 cycle, u32 sync, u32 tags)
2120 struct iso_context *ctx = container_of(base, struct iso_context, base);
2121 struct fw_ohci *ohci = ctx->context.ohci;
2125 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2126 index = ctx - ohci->it_context_list;
2129 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2130 (cycle & 0x7fff) << 16;
2132 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2133 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2134 context_run(&ctx->context, match);
2136 index = ctx - ohci->ir_context_list;
2137 control = IR_CONTEXT_ISOCH_HEADER;
2138 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2140 match |= (cycle & 0x07fff) << 12;
2141 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2144 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2145 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2146 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2147 context_run(&ctx->context, control);
2153 static int ohci_stop_iso(struct fw_iso_context *base)
2155 struct fw_ohci *ohci = fw_ohci(base->card);
2156 struct iso_context *ctx = container_of(base, struct iso_context, base);
2159 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2160 index = ctx - ohci->it_context_list;
2161 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2163 index = ctx - ohci->ir_context_list;
2164 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2167 context_stop(&ctx->context);
2172 static void ohci_free_iso_context(struct fw_iso_context *base)
2174 struct fw_ohci *ohci = fw_ohci(base->card);
2175 struct iso_context *ctx = container_of(base, struct iso_context, base);
2176 unsigned long flags;
2179 ohci_stop_iso(base);
2180 context_release(&ctx->context);
2181 free_page((unsigned long)ctx->header);
2183 spin_lock_irqsave(&ohci->lock, flags);
2185 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2186 index = ctx - ohci->it_context_list;
2187 ohci->it_context_mask |= 1 << index;
2189 index = ctx - ohci->ir_context_list;
2190 ohci->ir_context_mask |= 1 << index;
2191 ohci->ir_context_channels |= 1ULL << base->channel;
2194 spin_unlock_irqrestore(&ohci->lock, flags);
2197 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2198 struct fw_iso_packet *packet,
2199 struct fw_iso_buffer *buffer,
2200 unsigned long payload)
2202 struct iso_context *ctx = container_of(base, struct iso_context, base);
2203 struct descriptor *d, *last, *pd;
2204 struct fw_iso_packet *p;
2206 dma_addr_t d_bus, page_bus;
2207 u32 z, header_z, payload_z, irq;
2208 u32 payload_index, payload_end_index, next_page_index;
2209 int page, end_page, i, length, offset;
2212 payload_index = payload;
2218 if (p->header_length > 0)
2221 /* Determine the first page the payload isn't contained in. */
2222 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2223 if (p->payload_length > 0)
2224 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2230 /* Get header size in number of descriptors. */
2231 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2233 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2238 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2239 d[0].req_count = cpu_to_le16(8);
2241 * Link the skip address to this descriptor itself. This causes
2242 * a context to skip a cycle whenever lost cycles or FIFO
2243 * overruns occur, without dropping the data. The application
2244 * should then decide whether this is an error condition or not.
2245 * FIXME: Make the context's cycle-lost behaviour configurable?
2247 d[0].branch_address = cpu_to_le32(d_bus | z);
2249 header = (__le32 *) &d[1];
2250 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2251 IT_HEADER_TAG(p->tag) |
2252 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2253 IT_HEADER_CHANNEL(ctx->base.channel) |
2254 IT_HEADER_SPEED(ctx->base.speed));
2256 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2257 p->payload_length));
2260 if (p->header_length > 0) {
2261 d[2].req_count = cpu_to_le16(p->header_length);
2262 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2263 memcpy(&d[z], p->header, p->header_length);
2266 pd = d + z - payload_z;
2267 payload_end_index = payload_index + p->payload_length;
2268 for (i = 0; i < payload_z; i++) {
2269 page = payload_index >> PAGE_SHIFT;
2270 offset = payload_index & ~PAGE_MASK;
2271 next_page_index = (page + 1) << PAGE_SHIFT;
2273 min(next_page_index, payload_end_index) - payload_index;
2274 pd[i].req_count = cpu_to_le16(length);
2276 page_bus = page_private(buffer->pages[page]);
2277 pd[i].data_address = cpu_to_le32(page_bus + offset);
2279 payload_index += length;
2283 irq = DESCRIPTOR_IRQ_ALWAYS;
2285 irq = DESCRIPTOR_NO_IRQ;
2287 last = z == 2 ? d : d + z - 1;
2288 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2290 DESCRIPTOR_BRANCH_ALWAYS |
2293 context_append(&ctx->context, d, z, header_z);
2298 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2299 struct fw_iso_packet *packet,
2300 struct fw_iso_buffer *buffer,
2301 unsigned long payload)
2303 struct iso_context *ctx = container_of(base, struct iso_context, base);
2304 struct descriptor *d, *pd;
2305 struct fw_iso_packet *p = packet;
2306 dma_addr_t d_bus, page_bus;
2307 u32 z, header_z, rest;
2309 int page, offset, packet_count, header_size, payload_per_buffer;
2312 * The OHCI controller puts the isochronous header and trailer in the
2313 * buffer, so we need at least 8 bytes.
2315 packet_count = p->header_length / ctx->base.header_size;
2316 header_size = max(ctx->base.header_size, (size_t)8);
2318 /* Get header size in number of descriptors. */
2319 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2320 page = payload >> PAGE_SHIFT;
2321 offset = payload & ~PAGE_MASK;
2322 payload_per_buffer = p->payload_length / packet_count;
2324 for (i = 0; i < packet_count; i++) {
2325 /* d points to the header descriptor */
2326 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2327 d = context_get_descriptors(&ctx->context,
2328 z + header_z, &d_bus);
2332 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2333 DESCRIPTOR_INPUT_MORE);
2334 if (p->skip && i == 0)
2335 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2336 d->req_count = cpu_to_le16(header_size);
2337 d->res_count = d->req_count;
2338 d->transfer_status = 0;
2339 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2341 rest = payload_per_buffer;
2343 for (j = 1; j < z; j++) {
2345 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2346 DESCRIPTOR_INPUT_MORE);
2348 if (offset + rest < PAGE_SIZE)
2351 length = PAGE_SIZE - offset;
2352 pd->req_count = cpu_to_le16(length);
2353 pd->res_count = pd->req_count;
2354 pd->transfer_status = 0;
2356 page_bus = page_private(buffer->pages[page]);
2357 pd->data_address = cpu_to_le32(page_bus + offset);
2359 offset = (offset + length) & ~PAGE_MASK;
2364 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2365 DESCRIPTOR_INPUT_LAST |
2366 DESCRIPTOR_BRANCH_ALWAYS);
2367 if (p->interrupt && i == packet_count - 1)
2368 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2370 context_append(&ctx->context, d, z, header_z);
2376 static int ohci_queue_iso(struct fw_iso_context *base,
2377 struct fw_iso_packet *packet,
2378 struct fw_iso_buffer *buffer,
2379 unsigned long payload)
2381 struct iso_context *ctx = container_of(base, struct iso_context, base);
2382 unsigned long flags;
2385 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2386 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2387 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2389 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2391 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2396 static const struct fw_card_driver ohci_driver = {
2397 .enable = ohci_enable,
2398 .update_phy_reg = ohci_update_phy_reg,
2399 .set_config_rom = ohci_set_config_rom,
2400 .send_request = ohci_send_request,
2401 .send_response = ohci_send_response,
2402 .cancel_packet = ohci_cancel_packet,
2403 .enable_phys_dma = ohci_enable_phys_dma,
2404 .get_cycle_time = ohci_get_cycle_time,
2406 .allocate_iso_context = ohci_allocate_iso_context,
2407 .free_iso_context = ohci_free_iso_context,
2408 .queue_iso = ohci_queue_iso,
2409 .start_iso = ohci_start_iso,
2410 .stop_iso = ohci_stop_iso,
2413 #ifdef CONFIG_PPC_PMAC
2414 static void pmac_ohci_on(struct pci_dev *dev)
2416 if (machine_is(powermac)) {
2417 struct device_node *ofn = pci_device_to_OF_node(dev);
2420 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2421 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2426 static void pmac_ohci_off(struct pci_dev *dev)
2428 if (machine_is(powermac)) {
2429 struct device_node *ofn = pci_device_to_OF_node(dev);
2432 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2433 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2438 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2439 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2440 #endif /* CONFIG_PPC_PMAC */
2442 static int __devinit pci_probe(struct pci_dev *dev,
2443 const struct pci_device_id *ent)
2445 struct fw_ohci *ohci;
2446 u32 bus_options, max_receive, link_speed, version, link_enh;
2448 int i, err, n_ir, n_it;
2451 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2457 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2461 err = pci_enable_device(dev);
2463 fw_error("Failed to enable OHCI hardware\n");
2467 pci_set_master(dev);
2468 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2469 pci_set_drvdata(dev, ohci);
2471 spin_lock_init(&ohci->lock);
2473 tasklet_init(&ohci->bus_reset_tasklet,
2474 bus_reset_tasklet, (unsigned long)ohci);
2476 err = pci_request_region(dev, 0, ohci_driver_name);
2478 fw_error("MMIO resource unavailable\n");
2482 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2483 if (ohci->registers == NULL) {
2484 fw_error("Failed to remap registers\n");
2489 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2490 if (ohci_quirks[i].vendor == dev->vendor &&
2491 (ohci_quirks[i].device == dev->device ||
2492 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2493 ohci->quirks = ohci_quirks[i].flags;
2497 ohci->quirks = param_quirks;
2499 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2500 if (dev->vendor == PCI_VENDOR_ID_TI) {
2501 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2503 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2504 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2505 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2507 /* use priority arbitration for asynchronous responses */
2508 link_enh |= TI_LinkEnh_enab_unfair;
2510 /* required for aPhyEnhanceEnable to work */
2511 link_enh |= TI_LinkEnh_enab_accel;
2513 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2516 ar_context_init(&ohci->ar_request_ctx, ohci,
2517 OHCI1394_AsReqRcvContextControlSet);
2519 ar_context_init(&ohci->ar_response_ctx, ohci,
2520 OHCI1394_AsRspRcvContextControlSet);
2522 context_init(&ohci->at_request_ctx, ohci,
2523 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2525 context_init(&ohci->at_response_ctx, ohci,
2526 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2528 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2529 ohci->ir_context_channels = ~0ULL;
2530 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2531 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2532 n_ir = hweight32(ohci->ir_context_mask);
2533 size = sizeof(struct iso_context) * n_ir;
2534 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2536 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2537 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2538 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2539 n_it = hweight32(ohci->it_context_mask);
2540 size = sizeof(struct iso_context) * n_it;
2541 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2543 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2548 /* self-id dma buffer allocation */
2549 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2553 if (ohci->self_id_cpu == NULL) {
2558 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2559 max_receive = (bus_options >> 12) & 0xf;
2560 link_speed = bus_options & 0x7;
2561 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2562 reg_read(ohci, OHCI1394_GUIDLo);
2564 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2568 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2569 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2570 "%d IR + %d IT contexts, quirks 0x%x\n",
2571 dev_name(&dev->dev), version >> 16, version & 0xff,
2572 n_ir, n_it, ohci->quirks);
2577 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2578 ohci->self_id_cpu, ohci->self_id_bus);
2580 kfree(ohci->ir_context_list);
2581 kfree(ohci->it_context_list);
2582 context_release(&ohci->at_response_ctx);
2583 context_release(&ohci->at_request_ctx);
2584 ar_context_release(&ohci->ar_response_ctx);
2585 ar_context_release(&ohci->ar_request_ctx);
2586 pci_iounmap(dev, ohci->registers);
2588 pci_release_region(dev, 0);
2590 pci_disable_device(dev);
2596 fw_error("Out of memory\n");
2601 static void pci_remove(struct pci_dev *dev)
2603 struct fw_ohci *ohci;
2605 ohci = pci_get_drvdata(dev);
2606 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2608 fw_core_remove_card(&ohci->card);
2611 * FIXME: Fail all pending packets here, now that the upper
2612 * layers can't queue any more.
2615 software_reset(ohci);
2616 free_irq(dev->irq, ohci);
2618 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2619 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2620 ohci->next_config_rom, ohci->next_config_rom_bus);
2621 if (ohci->config_rom)
2622 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2623 ohci->config_rom, ohci->config_rom_bus);
2624 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2625 ohci->self_id_cpu, ohci->self_id_bus);
2626 ar_context_release(&ohci->ar_request_ctx);
2627 ar_context_release(&ohci->ar_response_ctx);
2628 context_release(&ohci->at_request_ctx);
2629 context_release(&ohci->at_response_ctx);
2630 kfree(ohci->it_context_list);
2631 kfree(ohci->ir_context_list);
2632 pci_disable_msi(dev);
2633 pci_iounmap(dev, ohci->registers);
2634 pci_release_region(dev, 0);
2635 pci_disable_device(dev);
2639 fw_notify("Removed fw-ohci device.\n");
2643 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2645 struct fw_ohci *ohci = pci_get_drvdata(dev);
2648 software_reset(ohci);
2649 free_irq(dev->irq, ohci);
2650 pci_disable_msi(dev);
2651 err = pci_save_state(dev);
2653 fw_error("pci_save_state failed\n");
2656 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2658 fw_error("pci_set_power_state failed with %d\n", err);
2664 static int pci_resume(struct pci_dev *dev)
2666 struct fw_ohci *ohci = pci_get_drvdata(dev);
2670 pci_set_power_state(dev, PCI_D0);
2671 pci_restore_state(dev);
2672 err = pci_enable_device(dev);
2674 fw_error("pci_enable_device failed\n");
2678 return ohci_enable(&ohci->card, NULL, 0);
2682 static const struct pci_device_id pci_table[] = {
2683 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2687 MODULE_DEVICE_TABLE(pci, pci_table);
2689 static struct pci_driver fw_ohci_pci_driver = {
2690 .name = ohci_driver_name,
2691 .id_table = pci_table,
2693 .remove = pci_remove,
2695 .resume = pci_resume,
2696 .suspend = pci_suspend,
2700 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2701 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2702 MODULE_LICENSE("GPL");
2704 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2705 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2706 MODULE_ALIAS("ohci1394");
2709 static int __init fw_ohci_init(void)
2711 return pci_register_driver(&fw_ohci_pci_driver);
2714 static void __exit fw_ohci_cleanup(void)
2716 pci_unregister_driver(&fw_ohci_pci_driver);
2719 module_init(fw_ohci_init);
2720 module_exit(fw_ohci_cleanup);