drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 350 }
 351
 352 static const intel_limit_t intel_limits_i8xx_dvo = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i8xx_lvds = {
 367         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 368         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 369         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 370         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 371         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 372         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 373         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 374         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 375         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 376                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_sdvo = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 390                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 391         .find_pll = intel_find_best_PLL,
 392 };
 393
 394 static const intel_limit_t intel_limits_i9xx_lvds = {
 395         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 396         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 397         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 398         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 399         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 400         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 401         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 402         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 403         /* The single-channel range is 25-112Mhz, and dual-channel
 404          * is 80-224Mhz.  Prefer single channel as much as possible.
 405          */
 406         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 407                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 408         .find_pll = intel_find_best_PLL,
 409 };
 410
 411     /* below parameter and function is for G4X Chipset Family*/
 412 static const intel_limit_t intel_limits_g4x_sdvo = {
 413         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 414         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 416         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 417         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 418         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 419         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 420         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 421         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 422                  .p2_slow = G4X_P2_SDVO_SLOW,
 423                  .p2_fast = G4X_P2_SDVO_FAST
 424         },
 425         .find_pll = intel_g4x_find_best_PLL,
 426 };
 427
 428 static const intel_limit_t intel_limits_g4x_hdmi = {
 429         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 430         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 431         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 432         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 433         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 434         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 435         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 436         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 437         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 438                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 439                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 440         },
 441         .find_pll = intel_g4x_find_best_PLL,
 442 };
 443
 444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 445         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 447         .vco = { .min = G4X_VCO_MIN,
 448                  .max = G4X_VCO_MAX },
 449         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 451         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 453         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 454                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 455         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 456                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 457         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 458                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 459         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 460                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 461         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 462                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 463                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 464         },
 465         .find_pll = intel_g4x_find_best_PLL,
 466 };
 467
 468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 469         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 471         .vco = { .min = G4X_VCO_MIN,
 472                  .max = G4X_VCO_MAX },
 473         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 475         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 477         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 478                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 479         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 480                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 481         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 482                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 483         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 484                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 485         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 486                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 487                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 488         },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_g4x_display_port = {
 493         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 494                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 495         .vco = { .min = G4X_VCO_MIN,
 496                  .max = G4X_VCO_MAX},
 497         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 498                  .max = G4X_N_DISPLAY_PORT_MAX },
 499         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 500                  .max = G4X_M_DISPLAY_PORT_MAX },
 501         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 502                  .max = G4X_M1_DISPLAY_PORT_MAX },
 503         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 504                  .max = G4X_M2_DISPLAY_PORT_MAX },
 505         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 506                  .max = G4X_P_DISPLAY_PORT_MAX },
 507         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 508                  .max = G4X_P1_DISPLAY_PORT_MAX},
 509         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 510                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 511                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 512         .find_pll = intel_find_pll_g4x_dp,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_sdvo = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 525                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 526         .find_pll = intel_find_best_PLL,
 527 };
 528
 529 static const intel_limit_t intel_limits_pineview_lvds = {
 530         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 531         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 532         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 533         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 534         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 535         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 536         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 537         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 538         /* Pineview only supports single-channel mode. */
 539         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 540                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 541         .find_pll = intel_find_best_PLL,
 542 };
 543
 544 static const intel_limit_t intel_limits_ironlake_dac = {
 545         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 546         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 547         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 548         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 549         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 550         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 551         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 552         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 553         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 554                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 555                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 556         .find_pll = intel_g4x_find_best_PLL,
 557 };
 558
 559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 560         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 561         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 562         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 563         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 564         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 565         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 566         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 567         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 568         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 569                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 570                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 571         .find_pll = intel_g4x_find_best_PLL,
 572 };
 573
 574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 575         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 576         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 577         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 578         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 579         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 580         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 581         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 582         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 583         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 584                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 585                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 586         .find_pll = intel_g4x_find_best_PLL,
 587 };
 588
 589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 590         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 591         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 592         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 593         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 594         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 595         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 596         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 597         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 598         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 599                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 600                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 601         .find_pll = intel_g4x_find_best_PLL,
 602 };
 603
 604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 605         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 606         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 607         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 608         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 609         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 610         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 611         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 612         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 613         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 614                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 615                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 616         .find_pll = intel_g4x_find_best_PLL,
 617 };
 618
 619 static const intel_limit_t intel_limits_ironlake_display_port = {
 620         .dot = { .min = IRONLAKE_DOT_MIN,
 621                  .max = IRONLAKE_DOT_MAX },
 622         .vco = { .min = IRONLAKE_VCO_MIN,
 623                  .max = IRONLAKE_VCO_MAX},
 624         .n   = { .min = IRONLAKE_DP_N_MIN,
 625                  .max = IRONLAKE_DP_N_MAX },
 626         .m   = { .min = IRONLAKE_DP_M_MIN,
 627                  .max = IRONLAKE_DP_M_MAX },
 628         .m1  = { .min = IRONLAKE_M1_MIN,
 629                  .max = IRONLAKE_M1_MAX },
 630         .m2  = { .min = IRONLAKE_M2_MIN,
 631                  .max = IRONLAKE_M2_MAX },
 632         .p   = { .min = IRONLAKE_DP_P_MIN,
 633                  .max = IRONLAKE_DP_P_MAX },
 634         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 635                  .max = IRONLAKE_DP_P1_MAX},
 636         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 637                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 638                  .p2_fast = IRONLAKE_DP_P2_FAST },
 639         .find_pll = intel_find_pll_ironlake_dp,
 640 };
 641
 642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         const intel_limit_t *limit;
 647         int refclk = 120;
 648
 649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 650                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 651                         refclk = 100;
 652
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 774 {
 775         const intel_limit_t *limit = intel_limit (crtc);
 776         struct drm_device *dev = crtc->dev;
 777
 778         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 779                 INTELPllInvalid ("p1 out of range\n");
 780         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 781                 INTELPllInvalid ("p out of range\n");
 782         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 783                 INTELPllInvalid ("m2 out of range\n");
 784         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 785                 INTELPllInvalid ("m1 out of range\n");
 786         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 787                 INTELPllInvalid ("m1 <= m2\n");
 788         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 789                 INTELPllInvalid ("m out of range\n");
 790         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 791                 INTELPllInvalid ("n out of range\n");
 792         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 793                 INTELPllInvalid ("vco out of range\n");
 794         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 795          * connector, etc., rather than just a single range.
 796          */
 797         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 798                 INTELPllInvalid ("dot out of range\n");
 799
 800         return true;
 801 }
 802
 803 static bool
 804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 805                     int target, int refclk, intel_clock_t *best_clock)
 806
 807 {
 808         struct drm_device *dev = crtc->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         intel_clock_t clock;
 811         int err = target;
 812
 813         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 814             (I915_READ(LVDS)) != 0) {
 815                 /*
 816                  * For LVDS, if the panel is on, just rely on its current
 817                  * settings for dual-channel.  We haven't figured out how to
 818                  * reliably set up different single/dual channel state, if we
 819                  * even can.
 820                  */
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset (best_clock, 0, sizeof (*best_clock));
 834
 835         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 836              clock.m1++) {
 837                 for (clock.m2 = limit->m2.min;
 838                      clock.m2 <= limit->m2.max; clock.m2++) {
 839                         /* m1 is always 0 in Pineview */
 840                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 841                                 break;
 842                         for (clock.n = limit->n.min;
 843                              clock.n <= limit->n.max; clock.n++) {
 844                                 for (clock.p1 = limit->p1.min;
 845                                         clock.p1 <= limit->p1.max; clock.p1++) {
 846                                         int this_err;
 847
 848                                         intel_clock(dev, refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(crtc, &clock))
 851                                                 continue;
 852
 853                                         this_err = abs(clock.dot - target);
 854                                         if (this_err < err) {
 855                                                 *best_clock = clock;
 856                                                 err = this_err;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return (err != target);
 864 }
 865
 866 static bool
 867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 868                         int target, int refclk, intel_clock_t *best_clock)
 869 {
 870         struct drm_device *dev = crtc->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         intel_clock_t clock;
 873         int max_n;
 874         bool found;
 875         /* approximately equals target * 0.00585 */
 876         int err_most = (target >> 8) + (target >> 9);
 877         found = false;
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 int lvds_reg;
 881
 882                 if (HAS_PCH_SPLIT(dev))
 883                         lvds_reg = PCH_LVDS;
 884                 else
 885                         lvds_reg = LVDS;
 886                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 887                     LVDS_CLKB_POWER_UP)
 888                         clock.p2 = limit->p2.p2_fast;
 889                 else
 890                         clock.p2 = limit->p2.p2_slow;
 891         } else {
 892                 if (target < limit->p2.dot_limit)
 893                         clock.p2 = limit->p2.p2_slow;
 894                 else
 895                         clock.p2 = limit->p2.p2_fast;
 896         }
 897
 898         memset(best_clock, 0, sizeof(*best_clock));
 899         max_n = limit->n.max;
 900         /* based on hardware requirement, prefer smaller n to precision */
 901         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 902                 /* based on hardware requirement, prefere larger m1,m2 */
 903                 for (clock.m1 = limit->m1.max;
 904                      clock.m1 >= limit->m1.min; clock.m1--) {
 905                         for (clock.m2 = limit->m2.max;
 906                              clock.m2 >= limit->m2.min; clock.m2--) {
 907                                 for (clock.p1 = limit->p1.max;
 908                                      clock.p1 >= limit->p1.min; clock.p1--) {
 909                                         int this_err;
 910
 911                                         intel_clock(dev, refclk, &clock);
 912                                         if (!intel_PLL_is_valid(crtc, &clock))
 913                                                 continue;
 914                                         this_err = abs(clock.dot - target) ;
 915                                         if (this_err < err_most) {
 916                                                 *best_clock = clock;
 917                                                 err_most = this_err;
 918                                                 max_n = clock.n;
 919                                                 found = true;
 920                                         }
 921                                 }
 922                         }
 923                 }
 924         }
 925         return found;
 926 }
 927
 928 static bool
 929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 930                            int target, int refclk, intel_clock_t *best_clock)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         intel_clock_t clock;
 934
 935         /* return directly when it is eDP */
 936         if (HAS_eDP)
 937                 return true;
 938
 939         if (target < 200000) {
 940                 clock.n = 1;
 941                 clock.p1 = 2;
 942                 clock.p2 = 10;
 943                 clock.m1 = 12;
 944                 clock.m2 = 9;
 945         } else {
 946                 clock.n = 2;
 947                 clock.p1 = 1;
 948                 clock.p2 = 10;
 949                 clock.m1 = 14;
 950                 clock.m2 = 8;
 951         }
 952         intel_clock(dev, refclk, &clock);
 953         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 954         return true;
 955 }
 956
 957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 958 static bool
 959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 960                       int target, int refclk, intel_clock_t *best_clock)
 961 {
 962         intel_clock_t clock;
 963         if (target < 200000) {
 964                 clock.p1 = 2;
 965                 clock.p2 = 10;
 966                 clock.n = 2;
 967                 clock.m1 = 23;
 968                 clock.m2 = 8;
 969         } else {
 970                 clock.p1 = 1;
 971                 clock.p2 = 10;
 972                 clock.n = 1;
 973                 clock.m1 = 14;
 974                 clock.m2 = 2;
 975         }
 976         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 977         clock.p = (clock.p1 * clock.p2);
 978         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 979         clock.vco = 0;
 980         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 981         return true;
 982 }
 983
 984 /**
 985  * intel_wait_for_vblank - wait for vblank on a given pipe
 986  * @dev: drm device
 987  * @pipe: pipe to wait for
 988  *
 989  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 990  * mode setting code.
 991  */
 992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 996
 997         /* Clear existing vblank status. Note this will clear any other
 998          * sticky status fields as well.
 999          *
1000          * This races with i915_driver_irq_handler() with the result
1001          * that either function could miss a vblank event.  Here it is not
1002          * fatal, as we will either wait upon the next vblank interrupt or
1003          * timeout.  Generally speaking intel_wait_for_vblank() is only
1004          * called during modeset at which time the GPU should be idle and
1005          * should *not* be performing page flips and thus not waiting on
1006          * vblanks...
1007          * Currently, the result of us stealing a vblank from the irq
1008          * handler is that a single frame will be skipped during swapbuffers.
1009          */
1010         I915_WRITE(pipestat_reg,
1011                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013         /* Wait for vblank interrupt bit to set */
1014         if (wait_for(I915_READ(pipestat_reg) &
1015                      PIPE_VBLANK_INTERRUPT_STATUS,
1016                      50))
1017                 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /*
1021  * intel_wait_for_pipe_off - wait for pipe to turn off
1022  * @dev: drm device
1023  * @pipe: pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * On Gen4 and above:
1030  *   wait for the pipe register state bit to turn off
1031  *
1032  * Otherwise:
1033  *   wait for the display line value to settle (it usually
1034  *   ends up stopping at the start of the next frame).
1035  *
1036  */
1037 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1038 {
1039         struct drm_i915_private *dev_priv = dev->dev_private;
1040
1041         if (INTEL_INFO(dev)->gen >= 4) {
1042                 int reg = PIPECONF(pipe);
1043
1044                 /* Wait for the Pipe State to go off */
1045                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1046                              100))
1047                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1048         } else {
1049                 u32 last_line;
1050                 int reg = PIPEDSL(pipe);
1051                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1052
1053                 /* Wait for the display line to settle */
1054                 do {
1055                         last_line = I915_READ(reg) & DSL_LINEMASK;
1056                         mdelay(5);
1057                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1058                          time_after(timeout, jiffies));
1059                 if (time_after(jiffies, timeout))
1060                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1065 {
1066         struct drm_device *dev = crtc->dev;
1067         struct drm_i915_private *dev_priv = dev->dev_private;
1068         struct drm_framebuffer *fb = crtc->fb;
1069         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1070         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072         int plane, i;
1073         u32 fbc_ctl, fbc_ctl2;
1074
1075         if (fb->pitch == dev_priv->cfb_pitch &&
1076             obj_priv->fence_reg == dev_priv->cfb_fence &&
1077             intel_crtc->plane == dev_priv->cfb_plane &&
1078             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1079                 return;
1080
1081         i8xx_disable_fbc(dev);
1082
1083         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1084
1085         if (fb->pitch < dev_priv->cfb_pitch)
1086                 dev_priv->cfb_pitch = fb->pitch;
1087
1088         /* FBC_CTL wants 64B units */
1089         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1090         dev_priv->cfb_fence = obj_priv->fence_reg;
1091         dev_priv->cfb_plane = intel_crtc->plane;
1092         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1093
1094         /* Clear old tags */
1095         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1096                 I915_WRITE(FBC_TAG + (i * 4), 0);
1097
1098         /* Set it up... */
1099         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1100         if (obj_priv->tiling_mode != I915_TILING_NONE)
1101                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1102         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1103         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1104
1105         /* enable it... */
1106         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1107         if (IS_I945GM(dev))
1108                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1109         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1110         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1111         if (obj_priv->tiling_mode != I915_TILING_NONE)
1112                 fbc_ctl |= dev_priv->cfb_fence;
1113         I915_WRITE(FBC_CONTROL, fbc_ctl);
1114
1115         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1116                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1117 }
1118
1119 void i8xx_disable_fbc(struct drm_device *dev)
1120 {
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122         u32 fbc_ctl;
1123
1124         /* Disable compression */
1125         fbc_ctl = I915_READ(FBC_CONTROL);
1126         if ((fbc_ctl & FBC_CTL_EN) == 0)
1127                 return;
1128
1129         fbc_ctl &= ~FBC_CTL_EN;
1130         I915_WRITE(FBC_CONTROL, fbc_ctl);
1131
1132         /* Wait for compressing bit to clear */
1133         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1134                 DRM_DEBUG_KMS("FBC idle timed out\n");
1135                 return;
1136         }
1137
1138         DRM_DEBUG_KMS("disabled FBC\n");
1139 }
1140
1141 static bool i8xx_fbc_enabled(struct drm_device *dev)
1142 {
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144
1145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1146 }
1147
1148 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1149 {
1150         struct drm_device *dev = crtc->dev;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         struct drm_framebuffer *fb = crtc->fb;
1153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1154         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1156         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1157         unsigned long stall_watermark = 200;
1158         u32 dpfc_ctl;
1159
1160         dpfc_ctl = I915_READ(DPFC_CONTROL);
1161         if (dpfc_ctl & DPFC_CTL_EN) {
1162                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1163                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1164                     dev_priv->cfb_plane == intel_crtc->plane &&
1165                     dev_priv->cfb_y == crtc->y)
1166                         return;
1167
1168                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1169                 POSTING_READ(DPFC_CONTROL);
1170                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1171         }
1172
1173         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1174         dev_priv->cfb_fence = obj_priv->fence_reg;
1175         dev_priv->cfb_plane = intel_crtc->plane;
1176         dev_priv->cfb_y = crtc->y;
1177
1178         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1179         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1180                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1181                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1182         } else {
1183                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1184         }
1185
1186         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1187                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1188                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1189         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1190
1191         /* enable it... */
1192         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1193
1194         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1195 }
1196
1197 void g4x_disable_fbc(struct drm_device *dev)
1198 {
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         u32 dpfc_ctl;
1201
1202         /* Disable compression */
1203         dpfc_ctl = I915_READ(DPFC_CONTROL);
1204         if (dpfc_ctl & DPFC_CTL_EN) {
1205                 dpfc_ctl &= ~DPFC_CTL_EN;
1206                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1207
1208                 DRM_DEBUG_KMS("disabled FBC\n");
1209         }
1210 }
1211
1212 static bool g4x_fbc_enabled(struct drm_device *dev)
1213 {
1214         struct drm_i915_private *dev_priv = dev->dev_private;
1215
1216         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1217 }
1218
1219 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1220 {
1221         struct drm_device *dev = crtc->dev;
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         struct drm_framebuffer *fb = crtc->fb;
1224         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1225         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1227         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1228         unsigned long stall_watermark = 200;
1229         u32 dpfc_ctl;
1230
1231         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1232         if (dpfc_ctl & DPFC_CTL_EN) {
1233                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1234                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1235                     dev_priv->cfb_plane == intel_crtc->plane &&
1236                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1237                     dev_priv->cfb_y == crtc->y)
1238                         return;
1239
1240                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1241                 POSTING_READ(ILK_DPFC_CONTROL);
1242                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1243         }
1244
1245         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1246         dev_priv->cfb_fence = obj_priv->fence_reg;
1247         dev_priv->cfb_plane = intel_crtc->plane;
1248         dev_priv->cfb_offset = obj_priv->gtt_offset;
1249         dev_priv->cfb_y = crtc->y;
1250
1251         dpfc_ctl &= DPFC_RESERVED;
1252         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1253         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1254                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1255                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1256         } else {
1257                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1258         }
1259
1260         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1261                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1262                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1263         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1264         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1265         /* enable it... */
1266         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1267
1268         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1269 }
1270
1271 void ironlake_disable_fbc(struct drm_device *dev)
1272 {
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         u32 dpfc_ctl;
1275
1276         /* Disable compression */
1277         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1278         if (dpfc_ctl & DPFC_CTL_EN) {
1279                 dpfc_ctl &= ~DPFC_CTL_EN;
1280                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1281
1282                 DRM_DEBUG_KMS("disabled FBC\n");
1283         }
1284 }
1285
1286 static bool ironlake_fbc_enabled(struct drm_device *dev)
1287 {
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289
1290         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1291 }
1292
1293 bool intel_fbc_enabled(struct drm_device *dev)
1294 {
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296
1297         if (!dev_priv->display.fbc_enabled)
1298                 return false;
1299
1300         return dev_priv->display.fbc_enabled(dev);
1301 }
1302
1303 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1304 {
1305         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1306
1307         if (!dev_priv->display.enable_fbc)
1308                 return;
1309
1310         dev_priv->display.enable_fbc(crtc, interval);
1311 }
1312
1313 void intel_disable_fbc(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316
1317         if (!dev_priv->display.disable_fbc)
1318                 return;
1319
1320         dev_priv->display.disable_fbc(dev);
1321 }
1322
1323 /**
1324  * intel_update_fbc - enable/disable FBC as needed
1325  * @dev: the drm_device
1326  *
1327  * Set up the framebuffer compression hardware at mode set time.  We
1328  * enable it if possible:
1329  *   - plane A only (on pre-965)
1330  *   - no pixel mulitply/line duplication
1331  *   - no alpha buffer discard
1332  *   - no dual wide
1333  *   - framebuffer <= 2048 in width, 1536 in height
1334  *
1335  * We can't assume that any compression will take place (worst case),
1336  * so the compressed buffer has to be the same size as the uncompressed
1337  * one.  It also must reside (along with the line length buffer) in
1338  * stolen memory.
1339  *
1340  * We need to enable/disable FBC on a global basis.
1341  */
1342 static void intel_update_fbc(struct drm_device *dev)
1343 {
1344         struct drm_i915_private *dev_priv = dev->dev_private;
1345         struct drm_crtc *crtc = NULL, *tmp_crtc;
1346         struct intel_crtc *intel_crtc;
1347         struct drm_framebuffer *fb;
1348         struct intel_framebuffer *intel_fb;
1349         struct drm_i915_gem_object *obj_priv;
1350
1351         DRM_DEBUG_KMS("\n");
1352
1353         if (!i915_powersave)
1354                 return;
1355
1356         if (!I915_HAS_FBC(dev))
1357                 return;
1358
1359         /*
1360          * If FBC is already on, we just have to verify that we can
1361          * keep it that way...
1362          * Need to disable if:
1363          *   - more than one pipe is active
1364          *   - changing FBC params (stride, fence, mode)
1365          *   - new fb is too large to fit in compressed buffer
1366          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1367          */
1368         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1369                 if (tmp_crtc->enabled) {
1370                         if (crtc) {
1371                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1372                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1373                                 goto out_disable;
1374                         }
1375                         crtc = tmp_crtc;
1376                 }
1377         }
1378
1379         if (!crtc || crtc->fb == NULL) {
1380                 DRM_DEBUG_KMS("no output, disabling\n");
1381                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1382                 goto out_disable;
1383         }
1384
1385         intel_crtc = to_intel_crtc(crtc);
1386         fb = crtc->fb;
1387         intel_fb = to_intel_framebuffer(fb);
1388         obj_priv = to_intel_bo(intel_fb->obj);
1389
1390         if (intel_fb->obj->size > dev_priv->cfb_size) {
1391                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1392                               "compression\n");
1393                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1394                 goto out_disable;
1395         }
1396         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1397             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1398                 DRM_DEBUG_KMS("mode incompatible with compression, "
1399                               "disabling\n");
1400                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1401                 goto out_disable;
1402         }
1403         if ((crtc->mode.hdisplay > 2048) ||
1404             (crtc->mode.vdisplay > 1536)) {
1405                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1406                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1407                 goto out_disable;
1408         }
1409         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1410                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1411                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1412                 goto out_disable;
1413         }
1414         if (obj_priv->tiling_mode != I915_TILING_X) {
1415                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1416                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1417                 goto out_disable;
1418         }
1419
1420         /* If the kernel debugger is active, always disable compression */
1421         if (in_dbg_master())
1422                 goto out_disable;
1423
1424         intel_enable_fbc(crtc, 500);
1425         return;
1426
1427 out_disable:
1428         /* Multiple disables should be harmless */
1429         if (intel_fbc_enabled(dev)) {
1430                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1431                 intel_disable_fbc(dev);
1432         }
1433 }
1434
1435 int
1436 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1437                            struct drm_gem_object *obj,
1438                            bool pipelined)
1439 {
1440         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1441         u32 alignment;
1442         int ret;
1443
1444         switch (obj_priv->tiling_mode) {
1445         case I915_TILING_NONE:
1446                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1447                         alignment = 128 * 1024;
1448                 else if (INTEL_INFO(dev)->gen >= 4)
1449                         alignment = 4 * 1024;
1450                 else
1451                         alignment = 64 * 1024;
1452                 break;
1453         case I915_TILING_X:
1454                 /* pin() will align the object as required by fence */
1455                 alignment = 0;
1456                 break;
1457         case I915_TILING_Y:
1458                 /* FIXME: Is this true? */
1459                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1460                 return -EINVAL;
1461         default:
1462                 BUG();
1463         }
1464
1465         ret = i915_gem_object_pin(obj, alignment);
1466         if (ret)
1467                 return ret;
1468
1469         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1470         if (ret)
1471                 goto err_unpin;
1472
1473         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1474          * fence, whereas 965+ only requires a fence if using
1475          * framebuffer compression.  For simplicity, we always install
1476          * a fence as the cost is not that onerous.
1477          */
1478         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1479             obj_priv->tiling_mode != I915_TILING_NONE) {
1480                 ret = i915_gem_object_get_fence_reg(obj, false);
1481                 if (ret)
1482                         goto err_unpin;
1483         }
1484
1485         return 0;
1486
1487 err_unpin:
1488         i915_gem_object_unpin(obj);
1489         return ret;
1490 }
1491
1492 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1493 static int
1494 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1495                            int x, int y, enum mode_set_atomic state)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1500         struct intel_framebuffer *intel_fb;
1501         struct drm_i915_gem_object *obj_priv;
1502         struct drm_gem_object *obj;
1503         int plane = intel_crtc->plane;
1504         unsigned long Start, Offset;
1505         u32 dspcntr;
1506         u32 reg;
1507
1508         switch (plane) {
1509         case 0:
1510         case 1:
1511                 break;
1512         default:
1513                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1514                 return -EINVAL;
1515         }
1516
1517         intel_fb = to_intel_framebuffer(fb);
1518         obj = intel_fb->obj;
1519         obj_priv = to_intel_bo(obj);
1520
1521         reg = DSPCNTR(plane);
1522         dspcntr = I915_READ(reg);
1523         /* Mask out pixel format bits in case we change it */
1524         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1525         switch (fb->bits_per_pixel) {
1526         case 8:
1527                 dspcntr |= DISPPLANE_8BPP;
1528                 break;
1529         case 16:
1530                 if (fb->depth == 15)
1531                         dspcntr |= DISPPLANE_15_16BPP;
1532                 else
1533                         dspcntr |= DISPPLANE_16BPP;
1534                 break;
1535         case 24:
1536         case 32:
1537                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1538                 break;
1539         default:
1540                 DRM_ERROR("Unknown color depth\n");
1541                 return -EINVAL;
1542         }
1543         if (INTEL_INFO(dev)->gen >= 4) {
1544                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1545                         dspcntr |= DISPPLANE_TILED;
1546                 else
1547                         dspcntr &= ~DISPPLANE_TILED;
1548         }
1549
1550         if (HAS_PCH_SPLIT(dev))
1551                 /* must disable */
1552                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1553
1554         I915_WRITE(reg, dspcntr);
1555
1556         Start = obj_priv->gtt_offset;
1557         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1558
1559         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1560                       Start, Offset, x, y, fb->pitch);
1561         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1562         if (INTEL_INFO(dev)->gen >= 4) {
1563                 I915_WRITE(DSPSURF(plane), Start);
1564                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1565                 I915_WRITE(DSPADDR(plane), Offset);
1566         } else
1567                 I915_WRITE(DSPADDR(plane), Start + Offset);
1568         POSTING_READ(reg);
1569
1570         intel_update_fbc(dev);
1571         intel_increase_pllclock(crtc);
1572
1573         return 0;
1574 }
1575
1576 static int
1577 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1578                     struct drm_framebuffer *old_fb)
1579 {
1580         struct drm_device *dev = crtc->dev;
1581         struct drm_i915_master_private *master_priv;
1582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1583         int ret;
1584
1585         /* no fb bound */
1586         if (!crtc->fb) {
1587                 DRM_DEBUG_KMS("No FB bound\n");
1588                 return 0;
1589         }
1590
1591         switch (intel_crtc->plane) {
1592         case 0:
1593         case 1:
1594                 break;
1595         default:
1596                 return -EINVAL;
1597         }
1598
1599         mutex_lock(&dev->struct_mutex);
1600         ret = intel_pin_and_fence_fb_obj(dev,
1601                                          to_intel_framebuffer(crtc->fb)->obj,
1602                                          false);
1603         if (ret != 0) {
1604                 mutex_unlock(&dev->struct_mutex);
1605                 return ret;
1606         }
1607
1608         if (old_fb) {
1609                 struct drm_i915_private *dev_priv = dev->dev_private;
1610                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1611                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1612
1613                 wait_event(dev_priv->pending_flip_queue,
1614                            atomic_read(&obj_priv->pending_flip) == 0);
1615         }
1616
1617         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1618                                          LEAVE_ATOMIC_MODE_SET);
1619         if (ret) {
1620                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1621                 mutex_unlock(&dev->struct_mutex);
1622                 return ret;
1623         }
1624
1625         if (old_fb)
1626                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1627
1628         mutex_unlock(&dev->struct_mutex);
1629
1630         if (!dev->primary->master)
1631                 return 0;
1632
1633         master_priv = dev->primary->master->driver_priv;
1634         if (!master_priv->sarea_priv)
1635                 return 0;
1636
1637         if (intel_crtc->pipe) {
1638                 master_priv->sarea_priv->pipeB_x = x;
1639                 master_priv->sarea_priv->pipeB_y = y;
1640         } else {
1641                 master_priv->sarea_priv->pipeA_x = x;
1642                 master_priv->sarea_priv->pipeA_y = y;
1643         }
1644
1645         return 0;
1646 }
1647
1648 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1649 {
1650         struct drm_device *dev = crtc->dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         u32 dpa_ctl;
1653
1654         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1655         dpa_ctl = I915_READ(DP_A);
1656         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1657
1658         if (clock < 200000) {
1659                 u32 temp;
1660                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1661                 /* workaround for 160Mhz:
1662                    1) program 0x4600c bits 15:0 = 0x8124
1663                    2) program 0x46010 bit 0 = 1
1664                    3) program 0x46034 bit 24 = 1
1665                    4) program 0x64000 bit 14 = 1
1666                    */
1667                 temp = I915_READ(0x4600c);
1668                 temp &= 0xffff0000;
1669                 I915_WRITE(0x4600c, temp | 0x8124);
1670
1671                 temp = I915_READ(0x46010);
1672                 I915_WRITE(0x46010, temp | 1);
1673
1674                 temp = I915_READ(0x46034);
1675                 I915_WRITE(0x46034, temp | (1 << 24));
1676         } else {
1677                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1678         }
1679         I915_WRITE(DP_A, dpa_ctl);
1680
1681         POSTING_READ(DP_A);
1682         udelay(500);
1683 }
1684
1685 /* The FDI link training functions for ILK/Ibexpeak. */
1686 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1687 {
1688         struct drm_device *dev = crtc->dev;
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1691         int pipe = intel_crtc->pipe;
1692         u32 reg, temp, tries;
1693
1694         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1695            for train result */
1696         reg = FDI_RX_IMR(pipe);
1697         temp = I915_READ(reg);
1698         temp &= ~FDI_RX_SYMBOL_LOCK;
1699         temp &= ~FDI_RX_BIT_LOCK;
1700         I915_WRITE(reg, temp);
1701         I915_READ(reg);
1702         udelay(150);
1703
1704         /* enable CPU FDI TX and PCH FDI RX */
1705         reg = FDI_TX_CTL(pipe);
1706         temp = I915_READ(reg);
1707         temp &= ~(7 << 19);
1708         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1709         temp &= ~FDI_LINK_TRAIN_NONE;
1710         temp |= FDI_LINK_TRAIN_PATTERN_1;
1711         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1712
1713         reg = FDI_RX_CTL(pipe);
1714         temp = I915_READ(reg);
1715         temp &= ~FDI_LINK_TRAIN_NONE;
1716         temp |= FDI_LINK_TRAIN_PATTERN_1;
1717         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1718
1719         POSTING_READ(reg);
1720         udelay(150);
1721
1722         reg = FDI_RX_IIR(pipe);
1723         for (tries = 0; tries < 5; tries++) {
1724                 temp = I915_READ(reg);
1725                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1726
1727                 if ((temp & FDI_RX_BIT_LOCK)) {
1728                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1729                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1730                         break;
1731                 }
1732         }
1733         if (tries == 5)
1734                 DRM_ERROR("FDI train 1 fail!\n");
1735
1736         /* Train 2 */
1737         reg = FDI_TX_CTL(pipe);
1738         temp = I915_READ(reg);
1739         temp &= ~FDI_LINK_TRAIN_NONE;
1740         temp |= FDI_LINK_TRAIN_PATTERN_2;
1741         I915_WRITE(reg, temp);
1742
1743         reg = FDI_RX_CTL(pipe);
1744         temp = I915_READ(reg);
1745         temp &= ~FDI_LINK_TRAIN_NONE;
1746         temp |= FDI_LINK_TRAIN_PATTERN_2;
1747         I915_WRITE(reg, temp);
1748
1749         POSTING_READ(reg);
1750         udelay(150);
1751
1752         reg = FDI_RX_IIR(pipe);
1753         for (tries = 0; tries < 5; tries++) {
1754                 temp = I915_READ(reg);
1755                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1756
1757                 if (temp & FDI_RX_SYMBOL_LOCK) {
1758                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1759                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1760                         break;
1761                 }
1762         }
1763         if (tries == 5)
1764                 DRM_ERROR("FDI train 2 fail!\n");
1765
1766         DRM_DEBUG_KMS("FDI train done\n");
1767 }
1768
1769 static const int const snb_b_fdi_train_param [] = {
1770         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1771         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1772         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1773         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1774 };
1775
1776 /* The FDI link training functions for SNB/Cougarpoint. */
1777 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1778 {
1779         struct drm_device *dev = crtc->dev;
1780         struct drm_i915_private *dev_priv = dev->dev_private;
1781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1782         int pipe = intel_crtc->pipe;
1783         u32 reg, temp, i;
1784
1785         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1786            for train result */
1787         reg = FDI_RX_IMR(pipe);
1788         temp = I915_READ(reg);
1789         temp &= ~FDI_RX_SYMBOL_LOCK;
1790         temp &= ~FDI_RX_BIT_LOCK;
1791         I915_WRITE(reg, temp);
1792
1793         POSTING_READ(reg);
1794         udelay(150);
1795
1796         /* enable CPU FDI TX and PCH FDI RX */
1797         reg = FDI_TX_CTL(pipe);
1798         temp = I915_READ(reg);
1799         temp &= ~(7 << 19);
1800         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1801         temp &= ~FDI_LINK_TRAIN_NONE;
1802         temp |= FDI_LINK_TRAIN_PATTERN_1;
1803         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1804         /* SNB-B */
1805         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1806         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1807
1808         reg = FDI_RX_CTL(pipe);
1809         temp = I915_READ(reg);
1810         if (HAS_PCH_CPT(dev)) {
1811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1812                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1813         } else {
1814                 temp &= ~FDI_LINK_TRAIN_NONE;
1815                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1816         }
1817         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1818
1819         POSTING_READ(reg);
1820         udelay(150);
1821
1822         for (i = 0; i < 4; i++ ) {
1823                 reg = FDI_TX_CTL(pipe);
1824                 temp = I915_READ(reg);
1825                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1826                 temp |= snb_b_fdi_train_param[i];
1827                 I915_WRITE(reg, temp);
1828
1829                 POSTING_READ(reg);
1830                 udelay(500);
1831
1832                 reg = FDI_RX_IIR(pipe);
1833                 temp = I915_READ(reg);
1834                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1835
1836                 if (temp & FDI_RX_BIT_LOCK) {
1837                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1838                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1839                         break;
1840                 }
1841         }
1842         if (i == 4)
1843                 DRM_ERROR("FDI train 1 fail!\n");
1844
1845         /* Train 2 */
1846         reg = FDI_TX_CTL(pipe);
1847         temp = I915_READ(reg);
1848         temp &= ~FDI_LINK_TRAIN_NONE;
1849         temp |= FDI_LINK_TRAIN_PATTERN_2;
1850         if (IS_GEN6(dev)) {
1851                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1852                 /* SNB-B */
1853                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1854         }
1855         I915_WRITE(reg, temp);
1856
1857         reg = FDI_RX_CTL(pipe);
1858         temp = I915_READ(reg);
1859         if (HAS_PCH_CPT(dev)) {
1860                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1861                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1862         } else {
1863                 temp &= ~FDI_LINK_TRAIN_NONE;
1864                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1865         }
1866         I915_WRITE(reg, temp);
1867
1868         POSTING_READ(reg);
1869         udelay(150);
1870
1871         for (i = 0; i < 4; i++ ) {
1872                 reg = FDI_TX_CTL(pipe);
1873                 temp = I915_READ(reg);
1874                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1875                 temp |= snb_b_fdi_train_param[i];
1876                 I915_WRITE(reg, temp);
1877
1878                 POSTING_READ(reg);
1879                 udelay(500);
1880
1881                 reg = FDI_RX_IIR(pipe);
1882                 temp = I915_READ(reg);
1883                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1884
1885                 if (temp & FDI_RX_SYMBOL_LOCK) {
1886                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1887                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1888                         break;
1889                 }
1890         }
1891         if (i == 4)
1892                 DRM_ERROR("FDI train 2 fail!\n");
1893
1894         DRM_DEBUG_KMS("FDI train done.\n");
1895 }
1896
1897 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1898 {
1899         struct drm_device *dev = crtc->dev;
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1902         int pipe = intel_crtc->pipe;
1903         u32 reg, temp;
1904
1905         /* Write the TU size bits so error detection works */
1906         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1907                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1908
1909         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1910         reg = FDI_RX_CTL(pipe);
1911         temp = I915_READ(reg);
1912         temp &= ~((0x7 << 19) | (0x7 << 16));
1913         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1914         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1915         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1916
1917         POSTING_READ(reg);
1918         udelay(200);
1919
1920         /* Switch from Rawclk to PCDclk */
1921         temp = I915_READ(reg);
1922         I915_WRITE(reg, temp | FDI_PCDCLK);
1923
1924         POSTING_READ(reg);
1925         udelay(200);
1926
1927         /* Enable CPU FDI TX PLL, always on for Ironlake */
1928         reg = FDI_TX_CTL(pipe);
1929         temp = I915_READ(reg);
1930         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1931                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1932
1933                 POSTING_READ(reg);
1934                 udelay(100);
1935         }
1936 }
1937
1938 static void intel_flush_display_plane(struct drm_device *dev,
1939                                       int plane)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         u32 reg = DSPADDR(plane);
1943         I915_WRITE(reg, I915_READ(reg));
1944 }
1945
1946 /*
1947  * When we disable a pipe, we need to clear any pending scanline wait events
1948  * to avoid hanging the ring, which we assume we are waiting on.
1949  */
1950 static void intel_clear_scanline_wait(struct drm_device *dev)
1951 {
1952         struct drm_i915_private *dev_priv = dev->dev_private;
1953         u32 tmp;
1954
1955         if (IS_GEN2(dev))
1956                 /* Can't break the hang on i8xx */
1957                 return;
1958
1959         tmp = I915_READ(PRB0_CTL);
1960         if (tmp & RING_WAIT) {
1961                 I915_WRITE(PRB0_CTL, tmp);
1962                 POSTING_READ(PRB0_CTL);
1963         }
1964 }
1965
1966 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
1967 {
1968         struct drm_i915_gem_object *obj_priv;
1969         struct drm_i915_private *dev_priv;
1970
1971         if (crtc->fb == NULL)
1972                 return;
1973
1974         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
1975         dev_priv = crtc->dev->dev_private;
1976         wait_event(dev_priv->pending_flip_queue,
1977                    atomic_read(&obj_priv->pending_flip) == 0);
1978 }
1979
1980 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1981 {
1982         struct drm_device *dev = crtc->dev;
1983         struct drm_i915_private *dev_priv = dev->dev_private;
1984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1985         int pipe = intel_crtc->pipe;
1986         int plane = intel_crtc->plane;
1987         u32 reg, temp;
1988
1989         if (intel_crtc->active)
1990                 return;
1991
1992         intel_crtc->active = true;
1993         intel_update_watermarks(dev);
1994
1995         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1996                 temp = I915_READ(PCH_LVDS);
1997                 if ((temp & LVDS_PORT_EN) == 0)
1998                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1999         }
2000
2001         ironlake_fdi_enable(crtc);
2002
2003         /* Enable panel fitting for LVDS */
2004         if (dev_priv->pch_pf_size &&
2005             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2006              || HAS_eDP || intel_pch_has_edp(crtc))) {
2007                 /* Force use of hard-coded filter coefficients
2008                  * as some pre-programmed values are broken,
2009                  * e.g. x201.
2010                  */
2011                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2012                            PF_ENABLE | PF_FILTER_MED_3x3);
2013                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2014                            dev_priv->pch_pf_pos);
2015                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2016                            dev_priv->pch_pf_size);
2017         }
2018
2019         /* Enable CPU pipe */
2020         reg = PIPECONF(pipe);
2021         temp = I915_READ(reg);
2022         if ((temp & PIPECONF_ENABLE) == 0) {
2023                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2024                 POSTING_READ(reg);
2025                 udelay(100);
2026         }
2027
2028         /* configure and enable CPU plane */
2029         reg = DSPCNTR(plane);
2030         temp = I915_READ(reg);
2031         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2032                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2033                 intel_flush_display_plane(dev, plane);
2034         }
2035
2036         /* For PCH output, training FDI link */
2037         if (IS_GEN6(dev))
2038                 gen6_fdi_link_train(crtc);
2039         else
2040                 ironlake_fdi_link_train(crtc);
2041
2042         /* enable PCH DPLL */
2043         reg = PCH_DPLL(pipe);
2044         temp = I915_READ(reg);
2045         if ((temp & DPLL_VCO_ENABLE) == 0) {
2046                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2047                 POSTING_READ(reg);
2048                 udelay(200);
2049         }
2050
2051         if (HAS_PCH_CPT(dev)) {
2052                 /* Be sure PCH DPLL SEL is set */
2053                 temp = I915_READ(PCH_DPLL_SEL);
2054                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2055                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2056                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2057                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2058                 I915_WRITE(PCH_DPLL_SEL, temp);
2059         }
2060
2061         /* set transcoder timing */
2062         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2063         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2064         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2065
2066         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2067         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2068         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2069
2070         /* enable normal train */
2071         reg = FDI_TX_CTL(pipe);
2072         temp = I915_READ(reg);
2073         temp &= ~FDI_LINK_TRAIN_NONE;
2074         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2075         I915_WRITE(reg, temp);
2076
2077         reg = FDI_RX_CTL(pipe);
2078         temp = I915_READ(reg);
2079         if (HAS_PCH_CPT(dev)) {
2080                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2081                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2082         } else {
2083                 temp &= ~FDI_LINK_TRAIN_NONE;
2084                 temp |= FDI_LINK_TRAIN_NONE;
2085         }
2086         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2087
2088         /* wait one idle pattern time */
2089         POSTING_READ(reg);
2090         udelay(100);
2091
2092         /* For PCH DP, enable TRANS_DP_CTL */
2093         if (HAS_PCH_CPT(dev) &&
2094             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2095                 reg = TRANS_DP_CTL(pipe);
2096                 temp = I915_READ(reg);
2097                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2098                           TRANS_DP_SYNC_MASK);
2099                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2100                          TRANS_DP_ENH_FRAMING);
2101
2102                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2103                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2104                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2105                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2106
2107                 switch (intel_trans_dp_port_sel(crtc)) {
2108                 case PCH_DP_B:
2109                         temp |= TRANS_DP_PORT_SEL_B;
2110                         break;
2111                 case PCH_DP_C:
2112                         temp |= TRANS_DP_PORT_SEL_C;
2113                         break;
2114                 case PCH_DP_D:
2115                         temp |= TRANS_DP_PORT_SEL_D;
2116                         break;
2117                 default:
2118                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2119                         temp |= TRANS_DP_PORT_SEL_B;
2120                         break;
2121                 }
2122
2123                 I915_WRITE(reg, temp);
2124         }
2125
2126         /* enable PCH transcoder */
2127         reg = TRANSCONF(pipe);
2128         temp = I915_READ(reg);
2129         /*
2130          * make the BPC in transcoder be consistent with
2131          * that in pipeconf reg.
2132          */
2133         temp &= ~PIPE_BPC_MASK;
2134         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2135         I915_WRITE(reg, temp | TRANS_ENABLE);
2136         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2137                 DRM_ERROR("failed to enable transcoder\n");
2138
2139         intel_crtc_load_lut(crtc);
2140         intel_update_fbc(dev);
2141         intel_crtc_update_cursor(crtc, true);
2142 }
2143
2144 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2145 {
2146         struct drm_device *dev = crtc->dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149         int pipe = intel_crtc->pipe;
2150         int plane = intel_crtc->plane;
2151         u32 reg, temp;
2152
2153         if (!intel_crtc->active)
2154                 return;
2155
2156         intel_crtc_wait_for_pending_flips(crtc);
2157         drm_vblank_off(dev, pipe);
2158         intel_crtc_update_cursor(crtc, false);
2159
2160         /* Disable display plane */
2161         reg = DSPCNTR(plane);
2162         temp = I915_READ(reg);
2163         if (temp & DISPLAY_PLANE_ENABLE) {
2164                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2165                 intel_flush_display_plane(dev, plane);
2166         }
2167
2168         if (dev_priv->cfb_plane == plane &&
2169             dev_priv->display.disable_fbc)
2170                 dev_priv->display.disable_fbc(dev);
2171
2172         /* disable cpu pipe, disable after all planes disabled */
2173         reg = PIPECONF(pipe);
2174         temp = I915_READ(reg);
2175         if (temp & PIPECONF_ENABLE) {
2176                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2177                 /* wait for cpu pipe off, pipe state */
2178                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2179                         DRM_ERROR("failed to turn off cpu pipe\n");
2180         }
2181
2182         /* Disable PF */
2183         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2184         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2185
2186         /* disable CPU FDI tx and PCH FDI rx */
2187         reg = FDI_TX_CTL(pipe);
2188         temp = I915_READ(reg);
2189         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2190         POSTING_READ(reg);
2191
2192         reg = FDI_RX_CTL(pipe);
2193         temp = I915_READ(reg);
2194         temp &= ~(0x7 << 16);
2195         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2196         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2197
2198         POSTING_READ(reg);
2199         udelay(100);
2200
2201         /* still set train pattern 1 */
2202         reg = FDI_TX_CTL(pipe);
2203         temp = I915_READ(reg);
2204         temp &= ~FDI_LINK_TRAIN_NONE;
2205         temp |= FDI_LINK_TRAIN_PATTERN_1;
2206         I915_WRITE(reg, temp);
2207
2208         reg = FDI_RX_CTL(pipe);
2209         temp = I915_READ(reg);
2210         if (HAS_PCH_CPT(dev)) {
2211                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2212                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2213         } else {
2214                 temp &= ~FDI_LINK_TRAIN_NONE;
2215                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2216         }
2217         /* BPC in FDI rx is consistent with that in PIPECONF */
2218         temp &= ~(0x07 << 16);
2219         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2220         I915_WRITE(reg, temp);
2221
2222         POSTING_READ(reg);
2223         udelay(100);
2224
2225         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2226                 temp = I915_READ(PCH_LVDS);
2227                 if (temp & LVDS_PORT_EN) {
2228                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2229                         POSTING_READ(PCH_LVDS);
2230                         udelay(100);
2231                 }
2232         }
2233
2234         /* disable PCH transcoder */
2235         reg = TRANSCONF(plane);
2236         temp = I915_READ(reg);
2237         if (temp & TRANS_ENABLE) {
2238                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2239                 /* wait for PCH transcoder off, transcoder state */
2240                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2241                         DRM_ERROR("failed to disable transcoder\n");
2242         }
2243
2244         if (HAS_PCH_CPT(dev)) {
2245                 /* disable TRANS_DP_CTL */
2246                 reg = TRANS_DP_CTL(pipe);
2247                 temp = I915_READ(reg);
2248                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2249                 I915_WRITE(reg, temp);
2250
2251                 /* disable DPLL_SEL */
2252                 temp = I915_READ(PCH_DPLL_SEL);
2253                 if (pipe == 0)
2254                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2255                 else
2256                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2257                 I915_WRITE(PCH_DPLL_SEL, temp);
2258         }
2259
2260         /* disable PCH DPLL */
2261         reg = PCH_DPLL(pipe);
2262         temp = I915_READ(reg);
2263         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2264
2265         /* Switch from PCDclk to Rawclk */
2266         reg = FDI_RX_CTL(pipe);
2267         temp = I915_READ(reg);
2268         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2269
2270         /* Disable CPU FDI TX PLL */
2271         reg = FDI_TX_CTL(pipe);
2272         temp = I915_READ(reg);
2273         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2274
2275         POSTING_READ(reg);
2276         udelay(100);
2277
2278         reg = FDI_RX_CTL(pipe);
2279         temp = I915_READ(reg);
2280         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2281
2282         /* Wait for the clocks to turn off. */
2283         POSTING_READ(reg);
2284         udelay(100);
2285
2286         intel_crtc->active = false;
2287         intel_update_watermarks(dev);
2288         intel_update_fbc(dev);
2289         intel_clear_scanline_wait(dev);
2290 }
2291
2292 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2293 {
2294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2295         int pipe = intel_crtc->pipe;
2296         int plane = intel_crtc->plane;
2297
2298         /* XXX: When our outputs are all unaware of DPMS modes other than off
2299          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2300          */
2301         switch (mode) {
2302         case DRM_MODE_DPMS_ON:
2303         case DRM_MODE_DPMS_STANDBY:
2304         case DRM_MODE_DPMS_SUSPEND:
2305                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2306                 ironlake_crtc_enable(crtc);
2307                 break;
2308
2309         case DRM_MODE_DPMS_OFF:
2310                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2311                 ironlake_crtc_disable(crtc);
2312                 break;
2313         }
2314 }
2315
2316 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2317 {
2318         if (!enable && intel_crtc->overlay) {
2319                 struct drm_device *dev = intel_crtc->base.dev;
2320
2321                 mutex_lock(&dev->struct_mutex);
2322                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2323                 mutex_unlock(&dev->struct_mutex);
2324         }
2325
2326         /* Let userspace switch the overlay on again. In most cases userspace
2327          * has to recompute where to put it anyway.
2328          */
2329 }
2330
2331 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         int plane = intel_crtc->plane;
2338         u32 reg, temp;
2339
2340         if (intel_crtc->active)
2341                 return;
2342
2343         intel_crtc->active = true;
2344         intel_update_watermarks(dev);
2345
2346         /* Enable the DPLL */
2347         reg = DPLL(pipe);
2348         temp = I915_READ(reg);
2349         if ((temp & DPLL_VCO_ENABLE) == 0) {
2350                 I915_WRITE(reg, temp);
2351
2352                 /* Wait for the clocks to stabilize. */
2353                 POSTING_READ(reg);
2354                 udelay(150);
2355
2356                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2357
2358                 /* Wait for the clocks to stabilize. */
2359                 POSTING_READ(reg);
2360                 udelay(150);
2361
2362                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2363
2364                 /* Wait for the clocks to stabilize. */
2365                 POSTING_READ(reg);
2366                 udelay(150);
2367         }
2368
2369         /* Enable the pipe */
2370         reg = PIPECONF(pipe);
2371         temp = I915_READ(reg);
2372         if ((temp & PIPECONF_ENABLE) == 0)
2373                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2374
2375         /* Enable the plane */
2376         reg = DSPCNTR(plane);
2377         temp = I915_READ(reg);
2378         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2379                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2380                 intel_flush_display_plane(dev, plane);
2381         }
2382
2383         intel_crtc_load_lut(crtc);
2384         intel_update_fbc(dev);
2385
2386         /* Give the overlay scaler a chance to enable if it's on this pipe */
2387         intel_crtc_dpms_overlay(intel_crtc, true);
2388         intel_crtc_update_cursor(crtc, true);
2389 }
2390
2391 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2392 {
2393         struct drm_device *dev = crtc->dev;
2394         struct drm_i915_private *dev_priv = dev->dev_private;
2395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2396         int pipe = intel_crtc->pipe;
2397         int plane = intel_crtc->plane;
2398         u32 reg, temp;
2399
2400         if (!intel_crtc->active)
2401                 return;
2402
2403         /* Give the overlay scaler a chance to disable if it's on this pipe */
2404         intel_crtc_wait_for_pending_flips(crtc);
2405         drm_vblank_off(dev, pipe);
2406         intel_crtc_dpms_overlay(intel_crtc, false);
2407         intel_crtc_update_cursor(crtc, false);
2408
2409         if (dev_priv->cfb_plane == plane &&
2410             dev_priv->display.disable_fbc)
2411                 dev_priv->display.disable_fbc(dev);
2412
2413         /* Disable display plane */
2414         reg = DSPCNTR(plane);
2415         temp = I915_READ(reg);
2416         if (temp & DISPLAY_PLANE_ENABLE) {
2417                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2418                 /* Flush the plane changes */
2419                 intel_flush_display_plane(dev, plane);
2420
2421                 /* Wait for vblank for the disable to take effect */
2422                 if (IS_GEN2(dev))
2423                         intel_wait_for_vblank(dev, pipe);
2424         }
2425
2426         /* Don't disable pipe A or pipe A PLLs if needed */
2427         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2428                 goto done;
2429
2430         /* Next, disable display pipes */
2431         reg = PIPECONF(pipe);
2432         temp = I915_READ(reg);
2433         if (temp & PIPECONF_ENABLE) {
2434                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2435
2436                 /* Wait for the pipe to turn off */
2437                 POSTING_READ(reg);
2438                 intel_wait_for_pipe_off(dev, pipe);
2439         }
2440
2441         reg = DPLL(pipe);
2442         temp = I915_READ(reg);
2443         if (temp & DPLL_VCO_ENABLE) {
2444                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2445
2446                 /* Wait for the clocks to turn off. */
2447                 POSTING_READ(reg);
2448                 udelay(150);
2449         }
2450
2451 done:
2452         intel_crtc->active = false;
2453         intel_update_fbc(dev);
2454         intel_update_watermarks(dev);
2455         intel_clear_scanline_wait(dev);
2456 }
2457
2458 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2459 {
2460         /* XXX: When our outputs are all unaware of DPMS modes other than off
2461          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2462          */
2463         switch (mode) {
2464         case DRM_MODE_DPMS_ON:
2465         case DRM_MODE_DPMS_STANDBY:
2466         case DRM_MODE_DPMS_SUSPEND:
2467                 i9xx_crtc_enable(crtc);
2468                 break;
2469         case DRM_MODE_DPMS_OFF:
2470                 i9xx_crtc_disable(crtc);
2471                 break;
2472         }
2473 }
2474
2475 /**
2476  * Sets the power management mode of the pipe and plane.
2477  */
2478 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2479 {
2480         struct drm_device *dev = crtc->dev;
2481         struct drm_i915_private *dev_priv = dev->dev_private;
2482         struct drm_i915_master_private *master_priv;
2483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2484         int pipe = intel_crtc->pipe;
2485         bool enabled;
2486
2487         if (intel_crtc->dpms_mode == mode)
2488                 return;
2489
2490         intel_crtc->dpms_mode = mode;
2491
2492         dev_priv->display.dpms(crtc, mode);
2493
2494         if (!dev->primary->master)
2495                 return;
2496
2497         master_priv = dev->primary->master->driver_priv;
2498         if (!master_priv->sarea_priv)
2499                 return;
2500
2501         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2502
2503         switch (pipe) {
2504         case 0:
2505                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2506                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2507                 break;
2508         case 1:
2509                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2510                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2511                 break;
2512         default:
2513                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2514                 break;
2515         }
2516 }
2517
2518 static void intel_crtc_disable(struct drm_crtc *crtc)
2519 {
2520         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2521         struct drm_device *dev = crtc->dev;
2522
2523         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2524
2525         if (crtc->fb) {
2526                 mutex_lock(&dev->struct_mutex);
2527                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2528                 mutex_unlock(&dev->struct_mutex);
2529         }
2530 }
2531
2532 /* Prepare for a mode set.
2533  *
2534  * Note we could be a lot smarter here.  We need to figure out which outputs
2535  * will be enabled, which disabled (in short, how the config will changes)
2536  * and perform the minimum necessary steps to accomplish that, e.g. updating
2537  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2538  * panel fitting is in the proper state, etc.
2539  */
2540 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2541 {
2542         i9xx_crtc_disable(crtc);
2543 }
2544
2545 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2546 {
2547         i9xx_crtc_enable(crtc);
2548 }
2549
2550 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2551 {
2552         ironlake_crtc_disable(crtc);
2553 }
2554
2555 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2556 {
2557         ironlake_crtc_enable(crtc);
2558 }
2559
2560 void intel_encoder_prepare (struct drm_encoder *encoder)
2561 {
2562         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2563         /* lvds has its own version of prepare see intel_lvds_prepare */
2564         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2565 }
2566
2567 void intel_encoder_commit (struct drm_encoder *encoder)
2568 {
2569         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2570         /* lvds has its own version of commit see intel_lvds_commit */
2571         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2572 }
2573
2574 void intel_encoder_destroy(struct drm_encoder *encoder)
2575 {
2576         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2577
2578         drm_encoder_cleanup(encoder);
2579         kfree(intel_encoder);
2580 }
2581
2582 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2583                                   struct drm_display_mode *mode,
2584                                   struct drm_display_mode *adjusted_mode)
2585 {
2586         struct drm_device *dev = crtc->dev;
2587
2588         if (HAS_PCH_SPLIT(dev)) {
2589                 /* FDI link clock is fixed at 2.7G */
2590                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2591                         return false;
2592         }
2593
2594         /* XXX some encoders set the crtcinfo, others don't.
2595          * Obviously we need some form of conflict resolution here...
2596          */
2597         if (adjusted_mode->crtc_htotal == 0)
2598                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2599
2600         return true;
2601 }
2602
2603 static int i945_get_display_clock_speed(struct drm_device *dev)
2604 {
2605         return 400000;
2606 }
2607
2608 static int i915_get_display_clock_speed(struct drm_device *dev)
2609 {
2610         return 333000;
2611 }
2612
2613 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2614 {
2615         return 200000;
2616 }
2617
2618 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2619 {
2620         u16 gcfgc = 0;
2621
2622         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2623
2624         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2625                 return 133000;
2626         else {
2627                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2628                 case GC_DISPLAY_CLOCK_333_MHZ:
2629                         return 333000;
2630                 default:
2631                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2632                         return 190000;
2633                 }
2634         }
2635 }
2636
2637 static int i865_get_display_clock_speed(struct drm_device *dev)
2638 {
2639         return 266000;
2640 }
2641
2642 static int i855_get_display_clock_speed(struct drm_device *dev)
2643 {
2644         u16 hpllcc = 0;
2645         /* Assume that the hardware is in the high speed state.  This
2646          * should be the default.
2647          */
2648         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2649         case GC_CLOCK_133_200:
2650         case GC_CLOCK_100_200:
2651                 return 200000;
2652         case GC_CLOCK_166_250:
2653                 return 250000;
2654         case GC_CLOCK_100_133:
2655                 return 133000;
2656         }
2657
2658         /* Shouldn't happen */
2659         return 0;
2660 }
2661
2662 static int i830_get_display_clock_speed(struct drm_device *dev)
2663 {
2664         return 133000;
2665 }
2666
2667 struct fdi_m_n {
2668         u32        tu;
2669         u32        gmch_m;
2670         u32        gmch_n;
2671         u32        link_m;
2672         u32        link_n;
2673 };
2674
2675 static void
2676 fdi_reduce_ratio(u32 *num, u32 *den)
2677 {
2678         while (*num > 0xffffff || *den > 0xffffff) {
2679                 *num >>= 1;
2680                 *den >>= 1;
2681         }
2682 }
2683
2684 #define DATA_N 0x800000
2685 #define LINK_N 0x80000
2686
2687 static void
2688 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2689                      int link_clock, struct fdi_m_n *m_n)
2690 {
2691         u64 temp;
2692
2693         m_n->tu = 64; /* default size */
2694
2695         temp = (u64) DATA_N * pixel_clock;
2696         temp = div_u64(temp, link_clock);
2697         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2698         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2699         m_n->gmch_n = DATA_N;
2700         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2701
2702         temp = (u64) LINK_N * pixel_clock;
2703         m_n->link_m = div_u64(temp, link_clock);
2704         m_n->link_n = LINK_N;
2705         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2706 }
2707
2708
2709 struct intel_watermark_params {
2710         unsigned long fifo_size;
2711         unsigned long max_wm;
2712         unsigned long default_wm;
2713         unsigned long guard_size;
2714         unsigned long cacheline_size;
2715 };
2716
2717 /* Pineview has different values for various configs */
2718 static struct intel_watermark_params pineview_display_wm = {
2719         PINEVIEW_DISPLAY_FIFO,
2720         PINEVIEW_MAX_WM,
2721         PINEVIEW_DFT_WM,
2722         PINEVIEW_GUARD_WM,
2723         PINEVIEW_FIFO_LINE_SIZE
2724 };
2725 static struct intel_watermark_params pineview_display_hplloff_wm = {
2726         PINEVIEW_DISPLAY_FIFO,
2727         PINEVIEW_MAX_WM,
2728         PINEVIEW_DFT_HPLLOFF_WM,
2729         PINEVIEW_GUARD_WM,
2730         PINEVIEW_FIFO_LINE_SIZE
2731 };
2732 static struct intel_watermark_params pineview_cursor_wm = {
2733         PINEVIEW_CURSOR_FIFO,
2734         PINEVIEW_CURSOR_MAX_WM,
2735         PINEVIEW_CURSOR_DFT_WM,
2736         PINEVIEW_CURSOR_GUARD_WM,
2737         PINEVIEW_FIFO_LINE_SIZE,
2738 };
2739 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2740         PINEVIEW_CURSOR_FIFO,
2741         PINEVIEW_CURSOR_MAX_WM,
2742         PINEVIEW_CURSOR_DFT_WM,
2743         PINEVIEW_CURSOR_GUARD_WM,
2744         PINEVIEW_FIFO_LINE_SIZE
2745 };
2746 static struct intel_watermark_params g4x_wm_info = {
2747         G4X_FIFO_SIZE,
2748         G4X_MAX_WM,
2749         G4X_MAX_WM,
2750         2,
2751         G4X_FIFO_LINE_SIZE,
2752 };
2753 static struct intel_watermark_params g4x_cursor_wm_info = {
2754         I965_CURSOR_FIFO,
2755         I965_CURSOR_MAX_WM,
2756         I965_CURSOR_DFT_WM,
2757         2,
2758         G4X_FIFO_LINE_SIZE,
2759 };
2760 static struct intel_watermark_params i965_cursor_wm_info = {
2761         I965_CURSOR_FIFO,
2762         I965_CURSOR_MAX_WM,
2763         I965_CURSOR_DFT_WM,
2764         2,
2765         I915_FIFO_LINE_SIZE,
2766 };
2767 static struct intel_watermark_params i945_wm_info = {
2768         I945_FIFO_SIZE,
2769         I915_MAX_WM,
2770         1,
2771         2,
2772         I915_FIFO_LINE_SIZE
2773 };
2774 static struct intel_watermark_params i915_wm_info = {
2775         I915_FIFO_SIZE,
2776         I915_MAX_WM,
2777         1,
2778         2,
2779         I915_FIFO_LINE_SIZE
2780 };
2781 static struct intel_watermark_params i855_wm_info = {
2782         I855GM_FIFO_SIZE,
2783         I915_MAX_WM,
2784         1,
2785         2,
2786         I830_FIFO_LINE_SIZE
2787 };
2788 static struct intel_watermark_params i830_wm_info = {
2789         I830_FIFO_SIZE,
2790         I915_MAX_WM,
2791         1,
2792         2,
2793         I830_FIFO_LINE_SIZE
2794 };
2795
2796 static struct intel_watermark_params ironlake_display_wm_info = {
2797         ILK_DISPLAY_FIFO,
2798         ILK_DISPLAY_MAXWM,
2799         ILK_DISPLAY_DFTWM,
2800         2,
2801         ILK_FIFO_LINE_SIZE
2802 };
2803
2804 static struct intel_watermark_params ironlake_cursor_wm_info = {
2805         ILK_CURSOR_FIFO,
2806         ILK_CURSOR_MAXWM,
2807         ILK_CURSOR_DFTWM,
2808         2,
2809         ILK_FIFO_LINE_SIZE
2810 };
2811
2812 static struct intel_watermark_params ironlake_display_srwm_info = {
2813         ILK_DISPLAY_SR_FIFO,
2814         ILK_DISPLAY_MAX_SRWM,
2815         ILK_DISPLAY_DFT_SRWM,
2816         2,
2817         ILK_FIFO_LINE_SIZE
2818 };
2819
2820 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2821         ILK_CURSOR_SR_FIFO,
2822         ILK_CURSOR_MAX_SRWM,
2823         ILK_CURSOR_DFT_SRWM,
2824         2,
2825         ILK_FIFO_LINE_SIZE
2826 };
2827
2828 /**
2829  * intel_calculate_wm - calculate watermark level
2830  * @clock_in_khz: pixel clock
2831  * @wm: chip FIFO params
2832  * @pixel_size: display pixel size
2833  * @latency_ns: memory latency for the platform
2834  *
2835  * Calculate the watermark level (the level at which the display plane will
2836  * start fetching from memory again).  Each chip has a different display
2837  * FIFO size and allocation, so the caller needs to figure that out and pass
2838  * in the correct intel_watermark_params structure.
2839  *
2840  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2841  * on the pixel size.  When it reaches the watermark level, it'll start
2842  * fetching FIFO line sized based chunks from memory until the FIFO fills
2843  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2844  * will occur, and a display engine hang could result.
2845  */
2846 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2847                                         struct intel_watermark_params *wm,
2848                                         int pixel_size,
2849                                         unsigned long latency_ns)
2850 {
2851         long entries_required, wm_size;
2852
2853         /*
2854          * Note: we need to make sure we don't overflow for various clock &
2855          * latency values.
2856          * clocks go from a few thousand to several hundred thousand.
2857          * latency is usually a few thousand
2858          */
2859         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2860                 1000;
2861         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2862
2863         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2864
2865         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2866
2867         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2868
2869         /* Don't promote wm_size to unsigned... */
2870         if (wm_size > (long)wm->max_wm)
2871                 wm_size = wm->max_wm;
2872         if (wm_size <= 0)
2873                 wm_size = wm->default_wm;
2874         return wm_size;
2875 }
2876
2877 struct cxsr_latency {
2878         int is_desktop;
2879         int is_ddr3;
2880         unsigned long fsb_freq;
2881         unsigned long mem_freq;
2882         unsigned long display_sr;
2883         unsigned long display_hpll_disable;
2884         unsigned long cursor_sr;
2885         unsigned long cursor_hpll_disable;
2886 };
2887
2888 static const struct cxsr_latency cxsr_latency_table[] = {
2889         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2890         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2891         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2892         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2893         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2894
2895         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2896         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2897         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2898         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2899         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2900
2901         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2902         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2903         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2904         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2905         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2906
2907         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2908         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2909         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2910         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2911         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2912
2913         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2914         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2915         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2916         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2917         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2918
2919         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2920         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2921         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2922         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2923         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2924 };
2925
2926 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2927                                                          int is_ddr3,
2928                                                          int fsb,
2929                                                          int mem)
2930 {
2931         const struct cxsr_latency *latency;
2932         int i;
2933
2934         if (fsb == 0 || mem == 0)
2935                 return NULL;
2936
2937         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2938                 latency = &cxsr_latency_table[i];
2939                 if (is_desktop == latency->is_desktop &&
2940                     is_ddr3 == latency->is_ddr3 &&
2941                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2942                         return latency;
2943         }
2944
2945         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2946
2947         return NULL;
2948 }
2949
2950 static void pineview_disable_cxsr(struct drm_device *dev)
2951 {
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953
2954         /* deactivate cxsr */
2955         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2956 }
2957
2958 /*
2959  * Latency for FIFO fetches is dependent on several factors:
2960  *   - memory configuration (speed, channels)
2961  *   - chipset
2962  *   - current MCH state
2963  * It can be fairly high in some situations, so here we assume a fairly
2964  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2965  * set this value too high, the FIFO will fetch frequently to stay full)
2966  * and power consumption (set it too low to save power and we might see
2967  * FIFO underruns and display "flicker").
2968  *
2969  * A value of 5us seems to be a good balance; safe for very low end
2970  * platforms but not overly aggressive on lower latency configs.
2971  */
2972 static const int latency_ns = 5000;
2973
2974 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2975 {
2976         struct drm_i915_private *dev_priv = dev->dev_private;
2977         uint32_t dsparb = I915_READ(DSPARB);
2978         int size;
2979
2980         size = dsparb & 0x7f;
2981         if (plane)
2982                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2983
2984         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2985                       plane ? "B" : "A", size);
2986
2987         return size;
2988 }
2989
2990 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2991 {
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         uint32_t dsparb = I915_READ(DSPARB);
2994         int size;
2995
2996         size = dsparb & 0x1ff;
2997         if (plane)
2998                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2999         size >>= 1; /* Convert to cachelines */
3000
3001         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3002                       plane ? "B" : "A", size);
3003
3004         return size;
3005 }
3006
3007 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3008 {
3009         struct drm_i915_private *dev_priv = dev->dev_private;
3010         uint32_t dsparb = I915_READ(DSPARB);
3011         int size;
3012
3013         size = dsparb & 0x7f;
3014         size >>= 2; /* Convert to cachelines */
3015
3016         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3017                       plane ? "B" : "A",
3018                       size);
3019
3020         return size;
3021 }
3022
3023 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3024 {
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         uint32_t dsparb = I915_READ(DSPARB);
3027         int size;
3028
3029         size = dsparb & 0x7f;
3030         size >>= 1; /* Convert to cachelines */
3031
3032         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3033                       plane ? "B" : "A", size);
3034
3035         return size;
3036 }
3037
3038 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3039                                int planeb_clock, int sr_hdisplay, int unused,
3040                                int pixel_size)
3041 {
3042         struct drm_i915_private *dev_priv = dev->dev_private;
3043         const struct cxsr_latency *latency;
3044         u32 reg;
3045         unsigned long wm;
3046         int sr_clock;
3047
3048         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3049                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3050         if (!latency) {
3051                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3052                 pineview_disable_cxsr(dev);
3053                 return;
3054         }
3055
3056         if (!planea_clock || !planeb_clock) {
3057                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3058
3059                 /* Display SR */
3060                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3061                                         pixel_size, latency->display_sr);
3062                 reg = I915_READ(DSPFW1);
3063                 reg &= ~DSPFW_SR_MASK;
3064                 reg |= wm << DSPFW_SR_SHIFT;
3065                 I915_WRITE(DSPFW1, reg);
3066                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3067
3068                 /* cursor SR */
3069                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3070                                         pixel_size, latency->cursor_sr);
3071                 reg = I915_READ(DSPFW3);
3072                 reg &= ~DSPFW_CURSOR_SR_MASK;
3073                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3074                 I915_WRITE(DSPFW3, reg);
3075
3076                 /* Display HPLL off SR */
3077                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3078                                         pixel_size, latency->display_hpll_disable);
3079                 reg = I915_READ(DSPFW3);
3080                 reg &= ~DSPFW_HPLL_SR_MASK;
3081                 reg |= wm & DSPFW_HPLL_SR_MASK;
3082                 I915_WRITE(DSPFW3, reg);
3083
3084                 /* cursor HPLL off SR */
3085                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3086                                         pixel_size, latency->cursor_hpll_disable);
3087                 reg = I915_READ(DSPFW3);
3088                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3089                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3090                 I915_WRITE(DSPFW3, reg);
3091                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3092
3093                 /* activate cxsr */
3094                 I915_WRITE(DSPFW3,
3095                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3096                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3097         } else {
3098                 pineview_disable_cxsr(dev);
3099                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3100         }
3101 }
3102
3103 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3104                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3105                           int pixel_size)
3106 {
3107         struct drm_i915_private *dev_priv = dev->dev_private;
3108         int total_size, cacheline_size;
3109         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3110         struct intel_watermark_params planea_params, planeb_params;
3111         unsigned long line_time_us;
3112         int sr_clock, sr_entries = 0, entries_required;
3113
3114         /* Create copies of the base settings for each pipe */
3115         planea_params = planeb_params = g4x_wm_info;
3116
3117         /* Grab a couple of global values before we overwrite them */
3118         total_size = planea_params.fifo_size;
3119         cacheline_size = planea_params.cacheline_size;
3120
3121         /*
3122          * Note: we need to make sure we don't overflow for various clock &
3123          * latency values.
3124          * clocks go from a few thousand to several hundred thousand.
3125          * latency is usually a few thousand
3126          */
3127         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3128                 1000;
3129         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3130         planea_wm = entries_required + planea_params.guard_size;
3131
3132         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3133                 1000;
3134         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3135         planeb_wm = entries_required + planeb_params.guard_size;
3136
3137         cursora_wm = cursorb_wm = 16;
3138         cursor_sr = 32;
3139
3140         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3141
3142         /* Calc sr entries for one plane configs */
3143         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3144                 /* self-refresh has much higher latency */
3145                 static const int sr_latency_ns = 12000;
3146
3147                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3148                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3149
3150                 /* Use ns/us then divide to preserve precision */
3151                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3152                         pixel_size * sr_hdisplay;
3153                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3154
3155                 entries_required = (((sr_latency_ns / line_time_us) +
3156                                      1000) / 1000) * pixel_size * 64;
3157                 entries_required = DIV_ROUND_UP(entries_required,
3158                                                 g4x_cursor_wm_info.cacheline_size);
3159                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3160
3161                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3162                         cursor_sr = g4x_cursor_wm_info.max_wm;
3163                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3164                               "cursor %d\n", sr_entries, cursor_sr);
3165
3166                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3167         } else {
3168                 /* Turn off self refresh if both pipes are enabled */
3169                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3170                            & ~FW_BLC_SELF_EN);
3171         }
3172
3173         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3174                   planea_wm, planeb_wm, sr_entries);
3175
3176         planea_wm &= 0x3f;
3177         planeb_wm &= 0x3f;
3178
3179         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3180                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3181                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3182         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3183                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3184         /* HPLL off in SR has some issues on G4x... disable it */
3185         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3186                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3187 }
3188
3189 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3190                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3191                            int pixel_size)
3192 {
3193         struct drm_i915_private *dev_priv = dev->dev_private;
3194         unsigned long line_time_us;
3195         int sr_clock, sr_entries, srwm = 1;
3196         int cursor_sr = 16;
3197
3198         /* Calc sr entries for one plane configs */
3199         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3200                 /* self-refresh has much higher latency */
3201                 static const int sr_latency_ns = 12000;
3202
3203                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3204                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3205
3206                 /* Use ns/us then divide to preserve precision */
3207                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3208                         pixel_size * sr_hdisplay;
3209                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3210                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3211                 srwm = I965_FIFO_SIZE - sr_entries;
3212                 if (srwm < 0)
3213                         srwm = 1;
3214                 srwm &= 0x1ff;
3215
3216                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3217                         pixel_size * 64;
3218                 sr_entries = DIV_ROUND_UP(sr_entries,
3219                                           i965_cursor_wm_info.cacheline_size);
3220                 cursor_sr = i965_cursor_wm_info.fifo_size -
3221                         (sr_entries + i965_cursor_wm_info.guard_size);
3222
3223                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3224                         cursor_sr = i965_cursor_wm_info.max_wm;
3225
3226                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3227                               "cursor %d\n", srwm, cursor_sr);
3228
3229                 if (IS_CRESTLINE(dev))
3230                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3231         } else {
3232                 /* Turn off self refresh if both pipes are enabled */
3233                 if (IS_CRESTLINE(dev))
3234                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3235                                    & ~FW_BLC_SELF_EN);
3236         }
3237
3238         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3239                       srwm);
3240
3241         /* 965 has limitations... */
3242         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3243                    (8 << 0));
3244         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3245         /* update cursor SR watermark */
3246         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3247 }
3248
3249 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3250                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3251                            int pixel_size)
3252 {
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         uint32_t fwater_lo;
3255         uint32_t fwater_hi;
3256         int total_size, cacheline_size, cwm, srwm = 1;
3257         int planea_wm, planeb_wm;
3258         struct intel_watermark_params planea_params, planeb_params;
3259         unsigned long line_time_us;
3260         int sr_clock, sr_entries = 0;
3261
3262         /* Create copies of the base settings for each pipe */
3263         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3264                 planea_params = planeb_params = i945_wm_info;
3265         else if (!IS_GEN2(dev))
3266                 planea_params = planeb_params = i915_wm_info;
3267         else
3268                 planea_params = planeb_params = i855_wm_info;
3269
3270         /* Grab a couple of global values before we overwrite them */
3271         total_size = planea_params.fifo_size;
3272         cacheline_size = planea_params.cacheline_size;
3273
3274         /* Update per-plane FIFO sizes */
3275         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3276         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3277
3278         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3279                                        pixel_size, latency_ns);
3280         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3281                                        pixel_size, latency_ns);
3282         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3283
3284         /*
3285          * Overlay gets an aggressive default since video jitter is bad.
3286          */
3287         cwm = 2;
3288
3289         /* Calc sr entries for one plane configs */
3290         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3291             (!planea_clock || !planeb_clock)) {
3292                 /* self-refresh has much higher latency */
3293                 static const int sr_latency_ns = 6000;
3294
3295                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3296                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3297
3298                 /* Use ns/us then divide to preserve precision */
3299                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3300                         pixel_size * sr_hdisplay;
3301                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3302                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3303                 srwm = total_size - sr_entries;
3304                 if (srwm < 0)
3305                         srwm = 1;
3306
3307                 if (IS_I945G(dev) || IS_I945GM(dev))
3308                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3309                 else if (IS_I915GM(dev)) {
3310                         /* 915M has a smaller SRWM field */
3311                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3312                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3313                 }
3314         } else {
3315                 /* Turn off self refresh if both pipes are enabled */
3316                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3317                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3318                                    & ~FW_BLC_SELF_EN);
3319                 } else if (IS_I915GM(dev)) {
3320                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3321                 }
3322         }
3323
3324         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3325                       planea_wm, planeb_wm, cwm, srwm);
3326
3327         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3328         fwater_hi = (cwm & 0x1f);
3329
3330         /* Set request length to 8 cachelines per fetch */
3331         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3332         fwater_hi = fwater_hi | (1 << 8);
3333
3334         I915_WRITE(FW_BLC, fwater_lo);
3335         I915_WRITE(FW_BLC2, fwater_hi);
3336 }
3337
3338 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3339                            int unused2, int unused3, int pixel_size)
3340 {
3341         struct drm_i915_private *dev_priv = dev->dev_private;
3342         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3343         int planea_wm;
3344
3345         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3346
3347         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3348                                        pixel_size, latency_ns);
3349         fwater_lo |= (3<<8) | planea_wm;
3350
3351         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3352
3353         I915_WRITE(FW_BLC, fwater_lo);
3354 }
3355
3356 #define ILK_LP0_PLANE_LATENCY           700
3357 #define ILK_LP0_CURSOR_LATENCY          1300
3358
3359 static bool ironlake_compute_wm0(struct drm_device *dev,
3360                                  int pipe,
3361                                  int *plane_wm,
3362                                  int *cursor_wm)
3363 {
3364         struct drm_crtc *crtc;
3365         int htotal, hdisplay, clock, pixel_size = 0;
3366         int line_time_us, line_count, entries;
3367
3368         crtc = intel_get_crtc_for_pipe(dev, pipe);
3369         if (crtc->fb == NULL || !crtc->enabled)
3370                 return false;
3371
3372         htotal = crtc->mode.htotal;
3373         hdisplay = crtc->mode.hdisplay;
3374         clock = crtc->mode.clock;
3375         pixel_size = crtc->fb->bits_per_pixel / 8;
3376
3377         /* Use the small buffer method to calculate plane watermark */
3378         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3379         entries = DIV_ROUND_UP(entries,
3380                                ironlake_display_wm_info.cacheline_size);
3381         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3382         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3383                 *plane_wm = ironlake_display_wm_info.max_wm;
3384
3385         /* Use the large buffer method to calculate cursor watermark */
3386         line_time_us = ((htotal * 1000) / clock);
3387         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3388         entries = line_count * 64 * pixel_size;
3389         entries = DIV_ROUND_UP(entries,
3390                                ironlake_cursor_wm_info.cacheline_size);
3391         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3392         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3393                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3394
3395         return true;
3396 }
3397
3398 static void ironlake_update_wm(struct drm_device *dev,
3399                                int planea_clock, int planeb_clock,
3400                                int sr_hdisplay, int sr_htotal,
3401                                int pixel_size)
3402 {
3403         struct drm_i915_private *dev_priv = dev->dev_private;
3404         int plane_wm, cursor_wm, enabled;
3405         int tmp;
3406
3407         enabled = 0;
3408         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3409                 I915_WRITE(WM0_PIPEA_ILK,
3410                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3411                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3412                               " plane %d, " "cursor: %d\n",
3413                               plane_wm, cursor_wm);
3414                 enabled++;
3415         }
3416
3417         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3418                 I915_WRITE(WM0_PIPEB_ILK,
3419                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3420                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3421                               " plane %d, cursor: %d\n",
3422                               plane_wm, cursor_wm);
3423                 enabled++;
3424         }
3425
3426         /*
3427          * Calculate and update the self-refresh watermark only when one
3428          * display plane is used.
3429          */
3430         tmp = 0;
3431         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3432                 unsigned long line_time_us;
3433                 int small, large, plane_fbc;
3434                 int sr_clock, entries;
3435                 int line_count, line_size;
3436                 /* Read the self-refresh latency. The unit is 0.5us */
3437                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3438
3439                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3440                 line_time_us = (sr_htotal * 1000) / sr_clock;
3441
3442                 /* Use ns/us then divide to preserve precision */
3443                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3444                         / 1000;
3445                 line_size = sr_hdisplay * pixel_size;
3446
3447                 /* Use the minimum of the small and large buffer method for primary */
3448                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3449                 large = line_count * line_size;
3450
3451                 entries = DIV_ROUND_UP(min(small, large),
3452                                        ironlake_display_srwm_info.cacheline_size);
3453
3454                 plane_fbc = entries * 64;
3455                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3456
3457                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3458                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3459                         plane_wm = ironlake_display_srwm_info.max_wm;
3460
3461                 /* calculate the self-refresh watermark for display cursor */
3462                 entries = line_count * pixel_size * 64;
3463                 entries = DIV_ROUND_UP(entries,
3464                                        ironlake_cursor_srwm_info.cacheline_size);
3465
3466                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3467                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3468                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3469
3470                 /* configure watermark and enable self-refresh */
3471                 tmp = (WM1_LP_SR_EN |
3472                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3473                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3474                        (plane_wm << WM1_LP_SR_SHIFT) |
3475                        cursor_wm);
3476                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3477                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3478         }
3479         I915_WRITE(WM1_LP_ILK, tmp);
3480         /* XXX setup WM2 and WM3 */
3481 }
3482
3483 /**
3484  * intel_update_watermarks - update FIFO watermark values based on current modes
3485  *
3486  * Calculate watermark values for the various WM regs based on current mode
3487  * and plane configuration.
3488  *
3489  * There are several cases to deal with here:
3490  *   - normal (i.e. non-self-refresh)
3491  *   - self-refresh (SR) mode
3492  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3493  *   - lines are small relative to FIFO size (buffer can hold more than 2
3494  *     lines), so need to account for TLB latency
3495  *
3496  *   The normal calculation is:
3497  *     watermark = dotclock * bytes per pixel * latency
3498  *   where latency is platform & configuration dependent (we assume pessimal
3499  *   values here).
3500  *
3501  *   The SR calculation is:
3502  *     watermark = (trunc(latency/line time)+1) * surface width *
3503  *       bytes per pixel
3504  *   where
3505  *     line time = htotal / dotclock
3506  *     surface width = hdisplay for normal plane and 64 for cursor
3507  *   and latency is assumed to be high, as above.
3508  *
3509  * The final value programmed to the register should always be rounded up,
3510  * and include an extra 2 entries to account for clock crossings.
3511  *
3512  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3513  * to set the non-SR watermarks to 8.
3514  */
3515 static void intel_update_watermarks(struct drm_device *dev)
3516 {
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518         struct drm_crtc *crtc;
3519         int sr_hdisplay = 0;
3520         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3521         int enabled = 0, pixel_size = 0;
3522         int sr_htotal = 0;
3523
3524         if (!dev_priv->display.update_wm)
3525                 return;
3526
3527         /* Get the clock config from both planes */
3528         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3529                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530                 if (intel_crtc->active) {
3531                         enabled++;
3532                         if (intel_crtc->plane == 0) {
3533                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3534                                               intel_crtc->pipe, crtc->mode.clock);
3535                                 planea_clock = crtc->mode.clock;
3536                         } else {
3537                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3538                                               intel_crtc->pipe, crtc->mode.clock);
3539                                 planeb_clock = crtc->mode.clock;
3540                         }
3541                         sr_hdisplay = crtc->mode.hdisplay;
3542                         sr_clock = crtc->mode.clock;
3543                         sr_htotal = crtc->mode.htotal;
3544                         if (crtc->fb)
3545                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3546                         else
3547                                 pixel_size = 4; /* by default */
3548                 }
3549         }
3550
3551         if (enabled <= 0)
3552                 return;
3553
3554         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3555                                     sr_hdisplay, sr_htotal, pixel_size);
3556 }
3557
3558 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3559                                struct drm_display_mode *mode,
3560                                struct drm_display_mode *adjusted_mode,
3561                                int x, int y,
3562                                struct drm_framebuffer *old_fb)
3563 {
3564         struct drm_device *dev = crtc->dev;
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567         int pipe = intel_crtc->pipe;
3568         int plane = intel_crtc->plane;
3569         u32 fp_reg, dpll_reg;
3570         int refclk, num_connectors = 0;
3571         intel_clock_t clock, reduced_clock;
3572         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3573         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3574         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3575         struct intel_encoder *has_edp_encoder = NULL;
3576         struct drm_mode_config *mode_config = &dev->mode_config;
3577         struct intel_encoder *encoder;
3578         const intel_limit_t *limit;
3579         int ret;
3580         struct fdi_m_n m_n = {0};
3581         u32 reg, temp;
3582         int target_clock;
3583
3584         drm_vblank_pre_modeset(dev, pipe);
3585
3586         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3587                 if (encoder->base.crtc != crtc)
3588                         continue;
3589
3590                 switch (encoder->type) {
3591                 case INTEL_OUTPUT_LVDS:
3592                         is_lvds = true;
3593                         break;
3594                 case INTEL_OUTPUT_SDVO:
3595                 case INTEL_OUTPUT_HDMI:
3596                         is_sdvo = true;
3597                         if (encoder->needs_tv_clock)
3598                                 is_tv = true;
3599                         break;
3600                 case INTEL_OUTPUT_DVO:
3601                         is_dvo = true;
3602                         break;
3603                 case INTEL_OUTPUT_TVOUT:
3604                         is_tv = true;
3605                         break;
3606                 case INTEL_OUTPUT_ANALOG:
3607                         is_crt = true;
3608                         break;
3609                 case INTEL_OUTPUT_DISPLAYPORT:
3610                         is_dp = true;
3611                         break;
3612                 case INTEL_OUTPUT_EDP:
3613                         has_edp_encoder = encoder;
3614                         break;
3615                 }
3616
3617                 num_connectors++;
3618         }
3619
3620         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3621                 refclk = dev_priv->lvds_ssc_freq * 1000;
3622                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3623                               refclk / 1000);
3624         } else if (!IS_GEN2(dev)) {
3625                 refclk = 96000;
3626                 if (HAS_PCH_SPLIT(dev))
3627                         refclk = 120000; /* 120Mhz refclk */
3628         } else {
3629                 refclk = 48000;
3630         }
3631
3632         /*
3633          * Returns a set of divisors for the desired target clock with the given
3634          * refclk, or FALSE.  The returned values represent the clock equation:
3635          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3636          */
3637         limit = intel_limit(crtc);
3638         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3639         if (!ok) {
3640                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3641                 drm_vblank_post_modeset(dev, pipe);
3642                 return -EINVAL;
3643         }
3644
3645         /* Ensure that the cursor is valid for the new mode before changing... */
3646         intel_crtc_update_cursor(crtc, true);
3647
3648         if (is_lvds && dev_priv->lvds_downclock_avail) {
3649                 has_reduced_clock = limit->find_pll(limit, crtc,
3650                                                     dev_priv->lvds_downclock,
3651                                                     refclk,
3652                                                     &reduced_clock);
3653                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3654                         /*
3655                          * If the different P is found, it means that we can't
3656                          * switch the display clock by using the FP0/FP1.
3657                          * In such case we will disable the LVDS downclock
3658                          * feature.
3659                          */
3660                         DRM_DEBUG_KMS("Different P is found for "
3661                                       "LVDS clock/downclock\n");
3662                         has_reduced_clock = 0;
3663                 }
3664         }
3665         /* SDVO TV has fixed PLL values depend on its clock range,
3666            this mirrors vbios setting. */
3667         if (is_sdvo && is_tv) {
3668                 if (adjusted_mode->clock >= 100000
3669                     && adjusted_mode->clock < 140500) {
3670                         clock.p1 = 2;
3671                         clock.p2 = 10;
3672                         clock.n = 3;
3673                         clock.m1 = 16;
3674                         clock.m2 = 8;
3675                 } else if (adjusted_mode->clock >= 140500
3676                            && adjusted_mode->clock <= 200000) {
3677                         clock.p1 = 1;
3678                         clock.p2 = 10;
3679                         clock.n = 6;
3680                         clock.m1 = 12;
3681                         clock.m2 = 8;
3682                 }
3683         }
3684
3685         /* FDI link */
3686         if (HAS_PCH_SPLIT(dev)) {
3687                 int lane = 0, link_bw, bpp;
3688                 /* eDP doesn't require FDI link, so just set DP M/N
3689                    according to current link config */
3690                 if (has_edp_encoder) {
3691                         target_clock = mode->clock;
3692                         intel_edp_link_config(has_edp_encoder,
3693                                               &lane, &link_bw);
3694                 } else {
3695                         /* DP over FDI requires target mode clock
3696                            instead of link clock */
3697                         if (is_dp)
3698                                 target_clock = mode->clock;
3699                         else
3700                                 target_clock = adjusted_mode->clock;
3701
3702                         /* FDI is a binary signal running at ~2.7GHz, encoding
3703                          * each output octet as 10 bits. The actual frequency
3704                          * is stored as a divider into a 100MHz clock, and the
3705                          * mode pixel clock is stored in units of 1KHz.
3706                          * Hence the bw of each lane in terms of the mode signal
3707                          * is:
3708                          */
3709                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3710                 }
3711
3712                 /* determine panel color depth */
3713                 temp = I915_READ(PIPECONF(pipe));
3714                 temp &= ~PIPE_BPC_MASK;
3715                 if (is_lvds) {
3716                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3717                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3718                                 temp |= PIPE_8BPC;
3719                         else
3720                                 temp |= PIPE_6BPC;
3721                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3722                         switch (dev_priv->edp.bpp/3) {
3723                         case 8:
3724                                 temp |= PIPE_8BPC;
3725                                 break;
3726                         case 10:
3727                                 temp |= PIPE_10BPC;
3728                                 break;
3729                         case 6:
3730                                 temp |= PIPE_6BPC;
3731                                 break;
3732                         case 12:
3733                                 temp |= PIPE_12BPC;
3734                                 break;
3735                         }
3736                 } else
3737                         temp |= PIPE_8BPC;
3738                 I915_WRITE(PIPECONF(pipe), temp);
3739
3740                 switch (temp & PIPE_BPC_MASK) {
3741                 case PIPE_8BPC:
3742                         bpp = 24;
3743                         break;
3744                 case PIPE_10BPC:
3745                         bpp = 30;
3746                         break;
3747                 case PIPE_6BPC:
3748                         bpp = 18;
3749                         break;
3750                 case PIPE_12BPC:
3751                         bpp = 36;
3752                         break;
3753                 default:
3754                         DRM_ERROR("unknown pipe bpc value\n");
3755                         bpp = 24;
3756                 }
3757
3758                 if (!lane) {
3759                         /*
3760                          * Account for spread spectrum to avoid
3761                          * oversubscribing the link. Max center spread
3762                          * is 2.5%; use 5% for safety's sake.
3763                          */
3764                         u32 bps = target_clock * bpp * 21 / 20;
3765                         lane = bps / (link_bw * 8) + 1;
3766                 }
3767
3768                 intel_crtc->fdi_lanes = lane;
3769
3770                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3771         }
3772
3773         /* Ironlake: try to setup display ref clock before DPLL
3774          * enabling. This is only under driver's control after
3775          * PCH B stepping, previous chipset stepping should be
3776          * ignoring this setting.
3777          */
3778         if (HAS_PCH_SPLIT(dev)) {
3779                 temp = I915_READ(PCH_DREF_CONTROL);
3780                 /* Always enable nonspread source */
3781                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3782                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3783                 temp &= ~DREF_SSC_SOURCE_MASK;
3784                 temp |= DREF_SSC_SOURCE_ENABLE;
3785                 I915_WRITE(PCH_DREF_CONTROL, temp);
3786
3787                 POSTING_READ(PCH_DREF_CONTROL);
3788                 udelay(200);
3789
3790                 if (has_edp_encoder) {
3791                         if (dev_priv->lvds_use_ssc) {
3792                                 temp |= DREF_SSC1_ENABLE;
3793                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3794
3795                                 POSTING_READ(PCH_DREF_CONTROL);
3796                                 udelay(200);
3797
3798                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3799                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3800                         } else {
3801                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3802                         }
3803                         I915_WRITE(PCH_DREF_CONTROL, temp);
3804                 }
3805         }
3806
3807         if (IS_PINEVIEW(dev)) {
3808                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3809                 if (has_reduced_clock)
3810                         fp2 = (1 << reduced_clock.n) << 16 |
3811                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3812         } else {
3813                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3814                 if (has_reduced_clock)
3815                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3816                                 reduced_clock.m2;
3817         }
3818
3819         dpll = 0;
3820         if (!HAS_PCH_SPLIT(dev))
3821                 dpll = DPLL_VGA_MODE_DIS;
3822
3823         if (!IS_GEN2(dev)) {
3824                 if (is_lvds)
3825                         dpll |= DPLLB_MODE_LVDS;
3826                 else
3827                         dpll |= DPLLB_MODE_DAC_SERIAL;
3828                 if (is_sdvo) {
3829                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3830                         if (pixel_multiplier > 1) {
3831                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3832                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3833                                 else if (HAS_PCH_SPLIT(dev))
3834                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3835                         }
3836                         dpll |= DPLL_DVO_HIGH_SPEED;
3837                 }
3838                 if (is_dp)
3839                         dpll |= DPLL_DVO_HIGH_SPEED;
3840
3841                 /* compute bitmask from p1 value */
3842                 if (IS_PINEVIEW(dev))
3843                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3844                 else {
3845                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3846                         /* also FPA1 */
3847                         if (HAS_PCH_SPLIT(dev))
3848                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3849                         if (IS_G4X(dev) && has_reduced_clock)
3850                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3851                 }
3852                 switch (clock.p2) {
3853                 case 5:
3854                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3855                         break;
3856                 case 7:
3857                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3858                         break;
3859                 case 10:
3860                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3861                         break;
3862                 case 14:
3863                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3864                         break;
3865                 }
3866                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3867                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3868         } else {
3869                 if (is_lvds) {
3870                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3871                 } else {
3872                         if (clock.p1 == 2)
3873                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3874                         else
3875                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3876                         if (clock.p2 == 4)
3877                                 dpll |= PLL_P2_DIVIDE_BY_4;
3878                 }
3879         }
3880
3881         if (is_sdvo && is_tv)
3882                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3883         else if (is_tv)
3884                 /* XXX: just matching BIOS for now */
3885                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3886                 dpll |= 3;
3887         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3888                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3889         else
3890                 dpll |= PLL_REF_INPUT_DREFCLK;
3891
3892         /* setup pipeconf */
3893         pipeconf = I915_READ(PIPECONF(pipe));
3894
3895         /* Set up the display plane register */
3896         dspcntr = DISPPLANE_GAMMA_ENABLE;
3897
3898         /* Ironlake's plane is forced to pipe, bit 24 is to
3899            enable color space conversion */
3900         if (!HAS_PCH_SPLIT(dev)) {
3901                 if (pipe == 0)
3902                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3903                 else
3904                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3905         }
3906
3907         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3908                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3909                  * core speed.
3910                  *
3911                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3912                  * pipe == 0 check?
3913                  */
3914                 if (mode->clock >
3915                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3916                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3917                 else
3918                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3919         }
3920
3921         dspcntr |= DISPLAY_PLANE_ENABLE;
3922         pipeconf |= PIPECONF_ENABLE;
3923         dpll |= DPLL_VCO_ENABLE;
3924
3925         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3926         drm_mode_debug_printmodeline(mode);
3927
3928         /* assign to Ironlake registers */
3929         if (HAS_PCH_SPLIT(dev)) {
3930                 fp_reg = PCH_FP0(pipe);
3931                 dpll_reg = PCH_DPLL(pipe);
3932         } else {
3933                 fp_reg = FP0(pipe);
3934                 dpll_reg = DPLL(pipe);
3935         }
3936
3937         if (!has_edp_encoder) {
3938                 I915_WRITE(fp_reg, fp);
3939                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3940
3941                 POSTING_READ(dpll_reg);
3942                 udelay(150);
3943         }
3944
3945         /* enable transcoder DPLL */
3946         if (HAS_PCH_CPT(dev)) {
3947                 temp = I915_READ(PCH_DPLL_SEL);
3948                 if (pipe == 0)
3949                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3950                 else
3951                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3952                 I915_WRITE(PCH_DPLL_SEL, temp);
3953
3954                 POSTING_READ(PCH_DPLL_SEL);
3955                 udelay(150);
3956         }
3957
3958         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3959          * This is an exception to the general rule that mode_set doesn't turn
3960          * things on.
3961          */
3962         if (is_lvds) {
3963                 reg = LVDS;
3964                 if (HAS_PCH_SPLIT(dev))
3965                         reg = PCH_LVDS;
3966
3967                 temp = I915_READ(reg);
3968                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3969                 if (pipe == 1) {
3970                         if (HAS_PCH_CPT(dev))
3971                                 temp |= PORT_TRANS_B_SEL_CPT;
3972                         else
3973                                 temp |= LVDS_PIPEB_SELECT;
3974                 } else {
3975                         if (HAS_PCH_CPT(dev))
3976                                 temp &= ~PORT_TRANS_SEL_MASK;
3977                         else
3978                                 temp &= ~LVDS_PIPEB_SELECT;
3979                 }
3980                 /* set the corresponsding LVDS_BORDER bit */
3981                 temp |= dev_priv->lvds_border_bits;
3982                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3983                  * set the DPLLs for dual-channel mode or not.
3984                  */
3985                 if (clock.p2 == 7)
3986                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3987                 else
3988                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3989
3990                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3991                  * appropriately here, but we need to look more thoroughly into how
3992                  * panels behave in the two modes.
3993                  */
3994                 /* set the dithering flag on non-PCH LVDS as needed */
3995                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
3996                         if (dev_priv->lvds_dither)
3997                                 temp |= LVDS_ENABLE_DITHER;
3998                         else
3999                                 temp &= ~LVDS_ENABLE_DITHER;
4000                 }
4001                 I915_WRITE(reg, temp);
4002         }
4003
4004         /* set the dithering flag and clear for anything other than a panel. */
4005         if (HAS_PCH_SPLIT(dev)) {
4006                 pipeconf &= ~PIPECONF_DITHER_EN;
4007                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4008                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4009                         pipeconf |= PIPECONF_DITHER_EN;
4010                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4011                 }
4012         }
4013
4014         if (is_dp)
4015                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4016         else if (HAS_PCH_SPLIT(dev)) {
4017                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4018                 if (pipe == 0) {
4019                         I915_WRITE(TRANSA_DATA_M1, 0);
4020                         I915_WRITE(TRANSA_DATA_N1, 0);
4021                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4022                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4023                 } else {
4024                         I915_WRITE(TRANSB_DATA_M1, 0);
4025                         I915_WRITE(TRANSB_DATA_N1, 0);
4026                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4027                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4028                 }
4029         }
4030
4031         if (!has_edp_encoder) {
4032                 I915_WRITE(fp_reg, fp);
4033                 I915_WRITE(dpll_reg, dpll);
4034
4035                 /* Wait for the clocks to stabilize. */
4036                 POSTING_READ(dpll_reg);
4037                 udelay(150);
4038
4039                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4040                         temp = 0;
4041                         if (is_sdvo) {
4042                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4043                                 if (temp > 1)
4044                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4045                                 else
4046                                         temp = 0;
4047                         }
4048                         I915_WRITE(DPLL_MD(pipe), temp);
4049                 } else {
4050                         /* write it again -- the BIOS does, after all */
4051                         I915_WRITE(dpll_reg, dpll);
4052                 }
4053
4054                 /* Wait for the clocks to stabilize. */
4055                 POSTING_READ(dpll_reg);
4056                 udelay(150);
4057         }
4058
4059         intel_crtc->lowfreq_avail = false;
4060         if (is_lvds && has_reduced_clock && i915_powersave) {
4061                 I915_WRITE(fp_reg + 4, fp2);
4062                 intel_crtc->lowfreq_avail = true;
4063                 if (HAS_PIPE_CXSR(dev)) {
4064                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4065                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4066                 }
4067         } else {
4068                 I915_WRITE(fp_reg + 4, fp);
4069                 if (HAS_PIPE_CXSR(dev)) {
4070                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4071                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4072                 }
4073         }
4074
4075         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4076                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4077                 /* the chip adds 2 halflines automatically */
4078                 adjusted_mode->crtc_vdisplay -= 1;
4079                 adjusted_mode->crtc_vtotal -= 1;
4080                 adjusted_mode->crtc_vblank_start -= 1;
4081                 adjusted_mode->crtc_vblank_end -= 1;
4082                 adjusted_mode->crtc_vsync_end -= 1;
4083                 adjusted_mode->crtc_vsync_start -= 1;
4084         } else
4085                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4086
4087         I915_WRITE(HTOTAL(pipe),
4088                    (adjusted_mode->crtc_hdisplay - 1) |
4089                    ((adjusted_mode->crtc_htotal - 1) << 16));
4090         I915_WRITE(HBLANK(pipe),
4091                    (adjusted_mode->crtc_hblank_start - 1) |
4092                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4093         I915_WRITE(HSYNC(pipe),
4094                    (adjusted_mode->crtc_hsync_start - 1) |
4095                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4096
4097         I915_WRITE(VTOTAL(pipe),
4098                    (adjusted_mode->crtc_vdisplay - 1) |
4099                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4100         I915_WRITE(VBLANK(pipe),
4101                    (adjusted_mode->crtc_vblank_start - 1) |
4102                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4103         I915_WRITE(VSYNC(pipe),
4104                    (adjusted_mode->crtc_vsync_start - 1) |
4105                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4106
4107         /* pipesrc and dspsize control the size that is scaled from,
4108          * which should always be the user's requested size.
4109          */
4110         if (!HAS_PCH_SPLIT(dev)) {
4111                 I915_WRITE(DSPSIZE(plane),
4112                            ((mode->vdisplay - 1) << 16) |
4113                            (mode->hdisplay - 1));
4114                 I915_WRITE(DSPPOS(plane), 0);
4115         }
4116         I915_WRITE(PIPESRC(pipe),
4117                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4118
4119         if (HAS_PCH_SPLIT(dev)) {
4120                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4121                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4122                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4123                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4124
4125                 if (has_edp_encoder) {
4126                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4127                 } else {
4128                         /* enable FDI RX PLL too */
4129                         reg = FDI_RX_CTL(pipe);
4130                         temp = I915_READ(reg);
4131                         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4132
4133                         POSTING_READ(reg);
4134                         udelay(200);
4135
4136                         /* enable FDI TX PLL too */
4137                         reg = FDI_TX_CTL(pipe);
4138                         temp = I915_READ(reg);
4139                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4140
4141                         /* enable FDI RX PCDCLK */
4142                         reg = FDI_RX_CTL(pipe);
4143                         temp = I915_READ(reg);
4144                         I915_WRITE(reg, temp | FDI_PCDCLK);
4145
4146                         POSTING_READ(reg);
4147                         udelay(200);
4148                 }
4149         }
4150
4151         I915_WRITE(PIPECONF(pipe), pipeconf);
4152         POSTING_READ(PIPECONF(pipe));
4153
4154         intel_wait_for_vblank(dev, pipe);
4155
4156         if (IS_IRONLAKE(dev)) {
4157                 /* enable address swizzle for tiling buffer */
4158                 temp = I915_READ(DISP_ARB_CTL);
4159                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4160         }
4161
4162         I915_WRITE(DSPCNTR(plane), dspcntr);
4163
4164         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4165
4166         intel_update_watermarks(dev);
4167
4168         drm_vblank_post_modeset(dev, pipe);
4169
4170         return ret;
4171 }
4172
4173 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4174 void intel_crtc_load_lut(struct drm_crtc *crtc)
4175 {
4176         struct drm_device *dev = crtc->dev;
4177         struct drm_i915_private *dev_priv = dev->dev_private;
4178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4180         int i;
4181
4182         /* The clocks have to be on to load the palette. */
4183         if (!crtc->enabled)
4184                 return;
4185
4186         /* use legacy palette for Ironlake */
4187         if (HAS_PCH_SPLIT(dev))
4188                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4189                                                    LGC_PALETTE_B;
4190
4191         for (i = 0; i < 256; i++) {
4192                 I915_WRITE(palreg + 4 * i,
4193                            (intel_crtc->lut_r[i] << 16) |
4194                            (intel_crtc->lut_g[i] << 8) |
4195                            intel_crtc->lut_b[i]);
4196         }
4197 }
4198
4199 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4200 {
4201         struct drm_device *dev = crtc->dev;
4202         struct drm_i915_private *dev_priv = dev->dev_private;
4203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204         bool visible = base != 0;
4205         u32 cntl;
4206
4207         if (intel_crtc->cursor_visible == visible)
4208                 return;
4209
4210         cntl = I915_READ(CURACNTR);
4211         if (visible) {
4212                 /* On these chipsets we can only modify the base whilst
4213                  * the cursor is disabled.
4214                  */
4215                 I915_WRITE(CURABASE, base);
4216
4217                 cntl &= ~(CURSOR_FORMAT_MASK);
4218                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4219                 cntl |= CURSOR_ENABLE |
4220                         CURSOR_GAMMA_ENABLE |
4221                         CURSOR_FORMAT_ARGB;
4222         } else
4223                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4224         I915_WRITE(CURACNTR, cntl);
4225
4226         intel_crtc->cursor_visible = visible;
4227 }
4228
4229 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4230 {
4231         struct drm_device *dev = crtc->dev;
4232         struct drm_i915_private *dev_priv = dev->dev_private;
4233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4234         int pipe = intel_crtc->pipe;
4235         bool visible = base != 0;
4236
4237         if (intel_crtc->cursor_visible != visible) {
4238                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4239                 if (base) {
4240                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4241                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4242                         cntl |= pipe << 28; /* Connect to correct pipe */
4243                 } else {
4244                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4245                         cntl |= CURSOR_MODE_DISABLE;
4246                 }
4247                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4248
4249                 intel_crtc->cursor_visible = visible;
4250         }
4251         /* and commit changes on next vblank */
4252         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4253 }
4254
4255 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4256 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4257                                      bool on)
4258 {
4259         struct drm_device *dev = crtc->dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4262         int pipe = intel_crtc->pipe;
4263         int x = intel_crtc->cursor_x;
4264         int y = intel_crtc->cursor_y;
4265         u32 base, pos;
4266         bool visible;
4267
4268         pos = 0;
4269
4270         if (on && crtc->enabled && crtc->fb) {
4271                 base = intel_crtc->cursor_addr;
4272                 if (x > (int) crtc->fb->width)
4273                         base = 0;
4274
4275                 if (y > (int) crtc->fb->height)
4276                         base = 0;
4277         } else
4278                 base = 0;
4279
4280         if (x < 0) {
4281                 if (x + intel_crtc->cursor_width < 0)
4282                         base = 0;
4283
4284                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4285                 x = -x;
4286         }
4287         pos |= x << CURSOR_X_SHIFT;
4288
4289         if (y < 0) {
4290                 if (y + intel_crtc->cursor_height < 0)
4291                         base = 0;
4292
4293                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4294                 y = -y;
4295         }
4296         pos |= y << CURSOR_Y_SHIFT;
4297
4298         visible = base != 0;
4299         if (!visible && !intel_crtc->cursor_visible)
4300                 return;
4301
4302         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4303         if (IS_845G(dev) || IS_I865G(dev))
4304                 i845_update_cursor(crtc, base);
4305         else
4306                 i9xx_update_cursor(crtc, base);
4307
4308         if (visible)
4309                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4310 }
4311
4312 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4313                                  struct drm_file *file_priv,
4314                                  uint32_t handle,
4315                                  uint32_t width, uint32_t height)
4316 {
4317         struct drm_device *dev = crtc->dev;
4318         struct drm_i915_private *dev_priv = dev->dev_private;
4319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320         struct drm_gem_object *bo;
4321         struct drm_i915_gem_object *obj_priv;
4322         uint32_t addr;
4323         int ret;
4324
4325         DRM_DEBUG_KMS("\n");
4326
4327         /* if we want to turn off the cursor ignore width and height */
4328         if (!handle) {
4329                 DRM_DEBUG_KMS("cursor off\n");
4330                 addr = 0;
4331                 bo = NULL;
4332                 mutex_lock(&dev->struct_mutex);
4333                 goto finish;
4334         }
4335
4336         /* Currently we only support 64x64 cursors */
4337         if (width != 64 || height != 64) {
4338                 DRM_ERROR("we currently only support 64x64 cursors\n");
4339                 return -EINVAL;
4340         }
4341
4342         bo = drm_gem_object_lookup(dev, file_priv, handle);
4343         if (!bo)
4344                 return -ENOENT;
4345
4346         obj_priv = to_intel_bo(bo);
4347
4348         if (bo->size < width * height * 4) {
4349                 DRM_ERROR("buffer is to small\n");
4350                 ret = -ENOMEM;
4351                 goto fail;
4352         }
4353
4354         /* we only need to pin inside GTT if cursor is non-phy */
4355         mutex_lock(&dev->struct_mutex);
4356         if (!dev_priv->info->cursor_needs_physical) {
4357                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4358                 if (ret) {
4359                         DRM_ERROR("failed to pin cursor bo\n");
4360                         goto fail_locked;
4361                 }
4362
4363                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4364                 if (ret) {
4365                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4366                         goto fail_unpin;
4367                 }
4368
4369                 addr = obj_priv->gtt_offset;
4370         } else {
4371                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4372                 ret = i915_gem_attach_phys_object(dev, bo,
4373                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4374                                                   align);
4375                 if (ret) {
4376                         DRM_ERROR("failed to attach phys object\n");
4377                         goto fail_locked;
4378                 }
4379                 addr = obj_priv->phys_obj->handle->busaddr;
4380         }
4381
4382         if (IS_GEN2(dev))
4383                 I915_WRITE(CURSIZE, (height << 12) | width);
4384
4385  finish:
4386         if (intel_crtc->cursor_bo) {
4387                 if (dev_priv->info->cursor_needs_physical) {
4388                         if (intel_crtc->cursor_bo != bo)
4389                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4390                 } else
4391                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4392                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4393         }
4394
4395         mutex_unlock(&dev->struct_mutex);
4396
4397         intel_crtc->cursor_addr = addr;
4398         intel_crtc->cursor_bo = bo;
4399         intel_crtc->cursor_width = width;
4400         intel_crtc->cursor_height = height;
4401
4402         intel_crtc_update_cursor(crtc, true);
4403
4404         return 0;
4405 fail_unpin:
4406         i915_gem_object_unpin(bo);
4407 fail_locked:
4408         mutex_unlock(&dev->struct_mutex);
4409 fail:
4410         drm_gem_object_unreference_unlocked(bo);
4411         return ret;
4412 }
4413
4414 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4415 {
4416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417
4418         intel_crtc->cursor_x = x;
4419         intel_crtc->cursor_y = y;
4420
4421         intel_crtc_update_cursor(crtc, true);
4422
4423         return 0;
4424 }
4425
4426 /** Sets the color ramps on behalf of RandR */
4427 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4428                                  u16 blue, int regno)
4429 {
4430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4431
4432         intel_crtc->lut_r[regno] = red >> 8;
4433         intel_crtc->lut_g[regno] = green >> 8;
4434         intel_crtc->lut_b[regno] = blue >> 8;
4435 }
4436
4437 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4438                              u16 *blue, int regno)
4439 {
4440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4441
4442         *red = intel_crtc->lut_r[regno] << 8;
4443         *green = intel_crtc->lut_g[regno] << 8;
4444         *blue = intel_crtc->lut_b[regno] << 8;
4445 }
4446
4447 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4448                                  u16 *blue, uint32_t start, uint32_t size)
4449 {
4450         int end = (start + size > 256) ? 256 : start + size, i;
4451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4452
4453         for (i = start; i < end; i++) {
4454                 intel_crtc->lut_r[i] = red[i] >> 8;
4455                 intel_crtc->lut_g[i] = green[i] >> 8;
4456                 intel_crtc->lut_b[i] = blue[i] >> 8;
4457         }
4458
4459         intel_crtc_load_lut(crtc);
4460 }
4461
4462 /**
4463  * Get a pipe with a simple mode set on it for doing load-based monitor
4464  * detection.
4465  *
4466  * It will be up to the load-detect code to adjust the pipe as appropriate for
4467  * its requirements.  The pipe will be connected to no other encoders.
4468  *
4469  * Currently this code will only succeed if there is a pipe with no encoders
4470  * configured for it.  In the future, it could choose to temporarily disable
4471  * some outputs to free up a pipe for its use.
4472  *
4473  * \return crtc, or NULL if no pipes are available.
4474  */
4475
4476 /* VESA 640x480x72Hz mode to set on the pipe */
4477 static struct drm_display_mode load_detect_mode = {
4478         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4479                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4480 };
4481
4482 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4483                                             struct drm_connector *connector,
4484                                             struct drm_display_mode *mode,
4485                                             int *dpms_mode)
4486 {
4487         struct intel_crtc *intel_crtc;
4488         struct drm_crtc *possible_crtc;
4489         struct drm_crtc *supported_crtc =NULL;
4490         struct drm_encoder *encoder = &intel_encoder->base;
4491         struct drm_crtc *crtc = NULL;
4492         struct drm_device *dev = encoder->dev;
4493         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4494         struct drm_crtc_helper_funcs *crtc_funcs;
4495         int i = -1;
4496
4497         /*
4498          * Algorithm gets a little messy:
4499          *   - if the connector already has an assigned crtc, use it (but make
4500          *     sure it's on first)
4501          *   - try to find the first unused crtc that can drive this connector,
4502          *     and use that if we find one
4503          *   - if there are no unused crtcs available, try to use the first
4504          *     one we found that supports the connector
4505          */
4506
4507         /* See if we already have a CRTC for this connector */
4508         if (encoder->crtc) {
4509                 crtc = encoder->crtc;
4510                 /* Make sure the crtc and connector are running */
4511                 intel_crtc = to_intel_crtc(crtc);
4512                 *dpms_mode = intel_crtc->dpms_mode;
4513                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4514                         crtc_funcs = crtc->helper_private;
4515                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4516                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4517                 }
4518                 return crtc;
4519         }
4520
4521         /* Find an unused one (if possible) */
4522         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4523                 i++;
4524                 if (!(encoder->possible_crtcs & (1 << i)))
4525                         continue;
4526                 if (!possible_crtc->enabled) {
4527                         crtc = possible_crtc;
4528                         break;
4529                 }
4530                 if (!supported_crtc)
4531                         supported_crtc = possible_crtc;
4532         }
4533
4534         /*
4535          * If we didn't find an unused CRTC, don't use any.
4536          */
4537         if (!crtc) {
4538                 return NULL;
4539         }
4540
4541         encoder->crtc = crtc;
4542         connector->encoder = encoder;
4543         intel_encoder->load_detect_temp = true;
4544
4545         intel_crtc = to_intel_crtc(crtc);
4546         *dpms_mode = intel_crtc->dpms_mode;
4547
4548         if (!crtc->enabled) {
4549                 if (!mode)
4550                         mode = &load_detect_mode;
4551                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4552         } else {
4553                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4554                         crtc_funcs = crtc->helper_private;
4555                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4556                 }
4557
4558                 /* Add this connector to the crtc */
4559                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4560                 encoder_funcs->commit(encoder);
4561         }
4562         /* let the connector get through one full cycle before testing */
4563         intel_wait_for_vblank(dev, intel_crtc->pipe);
4564
4565         return crtc;
4566 }
4567
4568 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4569                                     struct drm_connector *connector, int dpms_mode)
4570 {
4571         struct drm_encoder *encoder = &intel_encoder->base;
4572         struct drm_device *dev = encoder->dev;
4573         struct drm_crtc *crtc = encoder->crtc;
4574         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4575         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4576
4577         if (intel_encoder->load_detect_temp) {
4578                 encoder->crtc = NULL;
4579                 connector->encoder = NULL;
4580                 intel_encoder->load_detect_temp = false;
4581                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4582                 drm_helper_disable_unused_functions(dev);
4583         }
4584
4585         /* Switch crtc and encoder back off if necessary */
4586         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4587                 if (encoder->crtc == crtc)
4588                         encoder_funcs->dpms(encoder, dpms_mode);
4589                 crtc_funcs->dpms(crtc, dpms_mode);
4590         }
4591 }
4592
4593 /* Returns the clock of the currently programmed mode of the given pipe. */
4594 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4595 {
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         int pipe = intel_crtc->pipe;
4599         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4600         u32 fp;
4601         intel_clock_t clock;
4602
4603         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4604                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4605         else
4606                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4607
4608         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4609         if (IS_PINEVIEW(dev)) {
4610                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4611                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4612         } else {
4613                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4614                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4615         }
4616
4617         if (!IS_GEN2(dev)) {
4618                 if (IS_PINEVIEW(dev))
4619                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4620                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4621                 else
4622                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4623                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4624
4625                 switch (dpll & DPLL_MODE_MASK) {
4626                 case DPLLB_MODE_DAC_SERIAL:
4627                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4628                                 5 : 10;
4629                         break;
4630                 case DPLLB_MODE_LVDS:
4631                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4632                                 7 : 14;
4633                         break;
4634                 default:
4635                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4636                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4637                         return 0;
4638                 }
4639
4640                 /* XXX: Handle the 100Mhz refclk */
4641                 intel_clock(dev, 96000, &clock);
4642         } else {
4643                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4644
4645                 if (is_lvds) {
4646                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4647                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4648                         clock.p2 = 14;
4649
4650                         if ((dpll & PLL_REF_INPUT_MASK) ==
4651                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4652                                 /* XXX: might not be 66MHz */
4653                                 intel_clock(dev, 66000, &clock);
4654                         } else
4655                                 intel_clock(dev, 48000, &clock);
4656                 } else {
4657                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4658                                 clock.p1 = 2;
4659                         else {
4660                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4661                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4662                         }
4663                         if (dpll & PLL_P2_DIVIDE_BY_4)
4664                                 clock.p2 = 4;
4665                         else
4666                                 clock.p2 = 2;
4667
4668                         intel_clock(dev, 48000, &clock);
4669                 }
4670         }
4671
4672         /* XXX: It would be nice to validate the clocks, but we can't reuse
4673          * i830PllIsValid() because it relies on the xf86_config connector
4674          * configuration being accurate, which it isn't necessarily.
4675          */
4676
4677         return clock.dot;
4678 }
4679
4680 /** Returns the currently programmed mode of the given pipe. */
4681 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4682                                              struct drm_crtc *crtc)
4683 {
4684         struct drm_i915_private *dev_priv = dev->dev_private;
4685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4686         int pipe = intel_crtc->pipe;
4687         struct drm_display_mode *mode;
4688         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4689         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4690         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4691         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4692
4693         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4694         if (!mode)
4695                 return NULL;
4696
4697         mode->clock = intel_crtc_clock_get(dev, crtc);
4698         mode->hdisplay = (htot & 0xffff) + 1;
4699         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4700         mode->hsync_start = (hsync & 0xffff) + 1;
4701         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4702         mode->vdisplay = (vtot & 0xffff) + 1;
4703         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4704         mode->vsync_start = (vsync & 0xffff) + 1;
4705         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4706
4707         drm_mode_set_name(mode);
4708         drm_mode_set_crtcinfo(mode, 0);
4709
4710         return mode;
4711 }
4712
4713 #define GPU_IDLE_TIMEOUT 500 /* ms */
4714
4715 /* When this timer fires, we've been idle for awhile */
4716 static void intel_gpu_idle_timer(unsigned long arg)
4717 {
4718         struct drm_device *dev = (struct drm_device *)arg;
4719         drm_i915_private_t *dev_priv = dev->dev_private;
4720
4721         dev_priv->busy = false;
4722
4723         queue_work(dev_priv->wq, &dev_priv->idle_work);
4724 }
4725
4726 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4727
4728 static void intel_crtc_idle_timer(unsigned long arg)
4729 {
4730         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4731         struct drm_crtc *crtc = &intel_crtc->base;
4732         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4733
4734         intel_crtc->busy = false;
4735
4736         queue_work(dev_priv->wq, &dev_priv->idle_work);
4737 }
4738
4739 static void intel_increase_pllclock(struct drm_crtc *crtc)
4740 {
4741         struct drm_device *dev = crtc->dev;
4742         drm_i915_private_t *dev_priv = dev->dev_private;
4743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744         int pipe = intel_crtc->pipe;
4745         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4746         int dpll = I915_READ(dpll_reg);
4747
4748         if (HAS_PCH_SPLIT(dev))
4749                 return;
4750
4751         if (!dev_priv->lvds_downclock_avail)
4752                 return;
4753
4754         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4755                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4756
4757                 /* Unlock panel regs */
4758                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4759                            PANEL_UNLOCK_REGS);
4760
4761                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4762                 I915_WRITE(dpll_reg, dpll);
4763                 dpll = I915_READ(dpll_reg);
4764                 intel_wait_for_vblank(dev, pipe);
4765                 dpll = I915_READ(dpll_reg);
4766                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4767                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4768
4769                 /* ...and lock them again */
4770                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4771         }
4772
4773         /* Schedule downclock */
4774         mod_timer(&intel_crtc->idle_timer, jiffies +
4775                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4776 }
4777
4778 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4779 {
4780         struct drm_device *dev = crtc->dev;
4781         drm_i915_private_t *dev_priv = dev->dev_private;
4782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783         int pipe = intel_crtc->pipe;
4784         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4785         int dpll = I915_READ(dpll_reg);
4786
4787         if (HAS_PCH_SPLIT(dev))
4788                 return;
4789
4790         if (!dev_priv->lvds_downclock_avail)
4791                 return;
4792
4793         /*
4794          * Since this is called by a timer, we should never get here in
4795          * the manual case.
4796          */
4797         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4798                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4799
4800                 /* Unlock panel regs */
4801                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4802                            PANEL_UNLOCK_REGS);
4803
4804                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4805                 I915_WRITE(dpll_reg, dpll);
4806                 dpll = I915_READ(dpll_reg);
4807                 intel_wait_for_vblank(dev, pipe);
4808                 dpll = I915_READ(dpll_reg);
4809                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4810                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4811
4812                 /* ...and lock them again */
4813                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4814         }
4815
4816 }
4817
4818 /**
4819  * intel_idle_update - adjust clocks for idleness
4820  * @work: work struct
4821  *
4822  * Either the GPU or display (or both) went idle.  Check the busy status
4823  * here and adjust the CRTC and GPU clocks as necessary.
4824  */
4825 static void intel_idle_update(struct work_struct *work)
4826 {
4827         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4828                                                     idle_work);
4829         struct drm_device *dev = dev_priv->dev;
4830         struct drm_crtc *crtc;
4831         struct intel_crtc *intel_crtc;
4832         int enabled = 0;
4833
4834         if (!i915_powersave)
4835                 return;
4836
4837         mutex_lock(&dev->struct_mutex);
4838
4839         i915_update_gfx_val(dev_priv);
4840
4841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4842                 /* Skip inactive CRTCs */
4843                 if (!crtc->fb)
4844                         continue;
4845
4846                 enabled++;
4847                 intel_crtc = to_intel_crtc(crtc);
4848                 if (!intel_crtc->busy)
4849                         intel_decrease_pllclock(crtc);
4850         }
4851
4852         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4853                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4854                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4855         }
4856
4857         mutex_unlock(&dev->struct_mutex);
4858 }
4859
4860 /**
4861  * intel_mark_busy - mark the GPU and possibly the display busy
4862  * @dev: drm device
4863  * @obj: object we're operating on
4864  *
4865  * Callers can use this function to indicate that the GPU is busy processing
4866  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4867  * buffer), we'll also mark the display as busy, so we know to increase its
4868  * clock frequency.
4869  */
4870 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4871 {
4872         drm_i915_private_t *dev_priv = dev->dev_private;
4873         struct drm_crtc *crtc = NULL;
4874         struct intel_framebuffer *intel_fb;
4875         struct intel_crtc *intel_crtc;
4876
4877         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4878                 return;
4879
4880         if (!dev_priv->busy) {
4881                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4882                         u32 fw_blc_self;
4883
4884                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4885                         fw_blc_self = I915_READ(FW_BLC_SELF);
4886                         fw_blc_self &= ~FW_BLC_SELF_EN;
4887                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4888                 }
4889                 dev_priv->busy = true;
4890         } else
4891                 mod_timer(&dev_priv->idle_timer, jiffies +
4892                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4893
4894         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4895                 if (!crtc->fb)
4896                         continue;
4897
4898                 intel_crtc = to_intel_crtc(crtc);
4899                 intel_fb = to_intel_framebuffer(crtc->fb);
4900                 if (intel_fb->obj == obj) {
4901                         if (!intel_crtc->busy) {
4902                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4903                                         u32 fw_blc_self;
4904
4905                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4906                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4907                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4908                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4909                                 }
4910                                 /* Non-busy -> busy, upclock */
4911                                 intel_increase_pllclock(crtc);
4912                                 intel_crtc->busy = true;
4913                         } else {
4914                                 /* Busy -> busy, put off timer */
4915                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4916                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4917                         }
4918                 }
4919         }
4920 }
4921
4922 static void intel_crtc_destroy(struct drm_crtc *crtc)
4923 {
4924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4925         struct drm_device *dev = crtc->dev;
4926         struct intel_unpin_work *work;
4927         unsigned long flags;
4928
4929         spin_lock_irqsave(&dev->event_lock, flags);
4930         work = intel_crtc->unpin_work;
4931         intel_crtc->unpin_work = NULL;
4932         spin_unlock_irqrestore(&dev->event_lock, flags);
4933
4934         if (work) {
4935                 cancel_work_sync(&work->work);
4936                 kfree(work);
4937         }
4938
4939         drm_crtc_cleanup(crtc);
4940
4941         kfree(intel_crtc);
4942 }
4943
4944 static void intel_unpin_work_fn(struct work_struct *__work)
4945 {
4946         struct intel_unpin_work *work =
4947                 container_of(__work, struct intel_unpin_work, work);
4948
4949         mutex_lock(&work->dev->struct_mutex);
4950         i915_gem_object_unpin(work->old_fb_obj);
4951         drm_gem_object_unreference(work->pending_flip_obj);
4952         drm_gem_object_unreference(work->old_fb_obj);
4953         mutex_unlock(&work->dev->struct_mutex);
4954         kfree(work);
4955 }
4956
4957 static void do_intel_finish_page_flip(struct drm_device *dev,
4958                                       struct drm_crtc *crtc)
4959 {
4960         drm_i915_private_t *dev_priv = dev->dev_private;
4961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962         struct intel_unpin_work *work;
4963         struct drm_i915_gem_object *obj_priv;
4964         struct drm_pending_vblank_event *e;
4965         struct timeval now;
4966         unsigned long flags;
4967
4968         /* Ignore early vblank irqs */
4969         if (intel_crtc == NULL)
4970                 return;
4971
4972         spin_lock_irqsave(&dev->event_lock, flags);
4973         work = intel_crtc->unpin_work;
4974         if (work == NULL || !work->pending) {
4975                 spin_unlock_irqrestore(&dev->event_lock, flags);
4976                 return;
4977         }
4978
4979         intel_crtc->unpin_work = NULL;
4980         drm_vblank_put(dev, intel_crtc->pipe);
4981
4982         if (work->event) {
4983                 e = work->event;
4984                 do_gettimeofday(&now);
4985                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4986                 e->event.tv_sec = now.tv_sec;
4987                 e->event.tv_usec = now.tv_usec;
4988                 list_add_tail(&e->base.link,
4989                               &e->base.file_priv->event_list);
4990                 wake_up_interruptible(&e->base.file_priv->event_wait);
4991         }
4992
4993         spin_unlock_irqrestore(&dev->event_lock, flags);
4994
4995         obj_priv = to_intel_bo(work->pending_flip_obj);
4996
4997         /* Initial scanout buffer will have a 0 pending flip count */
4998         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4999             atomic_dec_and_test(&obj_priv->pending_flip))
5000                 wake_up(&dev_priv->pending_flip_queue);
5001         schedule_work(&work->work);
5002
5003         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5004 }
5005
5006 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5007 {
5008         drm_i915_private_t *dev_priv = dev->dev_private;
5009         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5010
5011         do_intel_finish_page_flip(dev, crtc);
5012 }
5013
5014 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5015 {
5016         drm_i915_private_t *dev_priv = dev->dev_private;
5017         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5018
5019         do_intel_finish_page_flip(dev, crtc);
5020 }
5021
5022 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5023 {
5024         drm_i915_private_t *dev_priv = dev->dev_private;
5025         struct intel_crtc *intel_crtc =
5026                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5027         unsigned long flags;
5028
5029         spin_lock_irqsave(&dev->event_lock, flags);
5030         if (intel_crtc->unpin_work) {
5031                 if ((++intel_crtc->unpin_work->pending) > 1)
5032                         DRM_ERROR("Prepared flip multiple times\n");
5033         } else {
5034                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5035         }
5036         spin_unlock_irqrestore(&dev->event_lock, flags);
5037 }
5038
5039 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5040                                 struct drm_framebuffer *fb,
5041                                 struct drm_pending_vblank_event *event)
5042 {
5043         struct drm_device *dev = crtc->dev;
5044         struct drm_i915_private *dev_priv = dev->dev_private;
5045         struct intel_framebuffer *intel_fb;
5046         struct drm_i915_gem_object *obj_priv;
5047         struct drm_gem_object *obj;
5048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049         struct intel_unpin_work *work;
5050         unsigned long flags, offset;
5051         int pipe = intel_crtc->pipe;
5052         u32 pf, pipesrc;
5053         int ret;
5054
5055         work = kzalloc(sizeof *work, GFP_KERNEL);
5056         if (work == NULL)
5057                 return -ENOMEM;
5058
5059         work->event = event;
5060         work->dev = crtc->dev;
5061         intel_fb = to_intel_framebuffer(crtc->fb);
5062         work->old_fb_obj = intel_fb->obj;
5063         INIT_WORK(&work->work, intel_unpin_work_fn);
5064
5065         /* We borrow the event spin lock for protecting unpin_work */
5066         spin_lock_irqsave(&dev->event_lock, flags);
5067         if (intel_crtc->unpin_work) {
5068                 spin_unlock_irqrestore(&dev->event_lock, flags);
5069                 kfree(work);
5070
5071                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5072                 return -EBUSY;
5073         }
5074         intel_crtc->unpin_work = work;
5075         spin_unlock_irqrestore(&dev->event_lock, flags);
5076
5077         intel_fb = to_intel_framebuffer(fb);
5078         obj = intel_fb->obj;
5079
5080         mutex_lock(&dev->struct_mutex);
5081         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5082         if (ret)
5083                 goto cleanup_work;
5084
5085         /* Reference the objects for the scheduled work. */
5086         drm_gem_object_reference(work->old_fb_obj);
5087         drm_gem_object_reference(obj);
5088
5089         crtc->fb = fb;
5090
5091         ret = drm_vblank_get(dev, intel_crtc->pipe);
5092         if (ret)
5093                 goto cleanup_objs;
5094
5095         obj_priv = to_intel_bo(obj);
5096         atomic_inc(&obj_priv->pending_flip);
5097         work->pending_flip_obj = obj;
5098
5099         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5100                 u32 flip_mask;
5101
5102                 /* Can't queue multiple flips, so wait for the previous
5103                  * one to finish before executing the next.
5104                  */
5105                 BEGIN_LP_RING(2);
5106                 if (intel_crtc->plane)
5107                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5108                 else
5109                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5110                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5111                 OUT_RING(MI_NOOP);
5112                 ADVANCE_LP_RING();
5113         }
5114
5115         work->enable_stall_check = true;
5116
5117         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5118         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5119
5120         BEGIN_LP_RING(4);
5121         switch(INTEL_INFO(dev)->gen) {
5122         case 2:
5123                 OUT_RING(MI_DISPLAY_FLIP |
5124                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5125                 OUT_RING(fb->pitch);
5126                 OUT_RING(obj_priv->gtt_offset + offset);
5127                 OUT_RING(MI_NOOP);
5128                 break;
5129
5130         case 3:
5131                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5132                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5133                 OUT_RING(fb->pitch);
5134                 OUT_RING(obj_priv->gtt_offset + offset);
5135                 OUT_RING(MI_NOOP);
5136                 break;
5137
5138         case 4:
5139         case 5:
5140                 /* i965+ uses the linear or tiled offsets from the
5141                  * Display Registers (which do not change across a page-flip)
5142                  * so we need only reprogram the base address.
5143                  */
5144                 OUT_RING(MI_DISPLAY_FLIP |
5145                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5146                 OUT_RING(fb->pitch);
5147                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5148
5149                 /* XXX Enabling the panel-fitter across page-flip is so far
5150                  * untested on non-native modes, so ignore it for now.
5151                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5152                  */
5153                 pf = 0;
5154                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5155                 OUT_RING(pf | pipesrc);
5156                 break;
5157
5158         case 6:
5159                 OUT_RING(MI_DISPLAY_FLIP |
5160                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5161                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5162                 OUT_RING(obj_priv->gtt_offset);
5163
5164                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5165                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5166                 OUT_RING(pf | pipesrc);
5167                 break;
5168         }
5169         ADVANCE_LP_RING();
5170
5171         mutex_unlock(&dev->struct_mutex);
5172
5173         trace_i915_flip_request(intel_crtc->plane, obj);
5174
5175         return 0;
5176
5177 cleanup_objs:
5178         drm_gem_object_unreference(work->old_fb_obj);
5179         drm_gem_object_unreference(obj);
5180 cleanup_work:
5181         mutex_unlock(&dev->struct_mutex);
5182
5183         spin_lock_irqsave(&dev->event_lock, flags);
5184         intel_crtc->unpin_work = NULL;
5185         spin_unlock_irqrestore(&dev->event_lock, flags);
5186
5187         kfree(work);
5188
5189         return ret;
5190 }
5191
5192 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5193         .dpms = intel_crtc_dpms,
5194         .mode_fixup = intel_crtc_mode_fixup,
5195         .mode_set = intel_crtc_mode_set,
5196         .mode_set_base = intel_pipe_set_base,
5197         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5198         .load_lut = intel_crtc_load_lut,
5199         .disable = intel_crtc_disable,
5200 };
5201
5202 static const struct drm_crtc_funcs intel_crtc_funcs = {
5203         .cursor_set = intel_crtc_cursor_set,
5204         .cursor_move = intel_crtc_cursor_move,
5205         .gamma_set = intel_crtc_gamma_set,
5206         .set_config = drm_crtc_helper_set_config,
5207         .destroy = intel_crtc_destroy,
5208         .page_flip = intel_crtc_page_flip,
5209 };
5210
5211
5212 static void intel_crtc_init(struct drm_device *dev, int pipe)
5213 {
5214         drm_i915_private_t *dev_priv = dev->dev_private;
5215         struct intel_crtc *intel_crtc;
5216         int i;
5217
5218         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5219         if (intel_crtc == NULL)
5220                 return;
5221
5222         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5223
5224         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5225         for (i = 0; i < 256; i++) {
5226                 intel_crtc->lut_r[i] = i;
5227                 intel_crtc->lut_g[i] = i;
5228                 intel_crtc->lut_b[i] = i;
5229         }
5230
5231         /* Swap pipes & planes for FBC on pre-965 */
5232         intel_crtc->pipe = pipe;
5233         intel_crtc->plane = pipe;
5234         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5235                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5236                 intel_crtc->plane = !pipe;
5237         }
5238
5239         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5240                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5241         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5242         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5243
5244         intel_crtc->cursor_addr = 0;
5245         intel_crtc->dpms_mode = -1;
5246         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5247
5248         if (HAS_PCH_SPLIT(dev)) {
5249                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5250                 intel_helper_funcs.commit = ironlake_crtc_commit;
5251         } else {
5252                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5253                 intel_helper_funcs.commit = i9xx_crtc_commit;
5254         }
5255
5256         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5257
5258         intel_crtc->busy = false;
5259
5260         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5261                     (unsigned long)intel_crtc);
5262 }
5263
5264 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5265                                 struct drm_file *file_priv)
5266 {
5267         drm_i915_private_t *dev_priv = dev->dev_private;
5268         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5269         struct drm_mode_object *drmmode_obj;
5270         struct intel_crtc *crtc;
5271
5272         if (!dev_priv) {
5273                 DRM_ERROR("called with no initialization\n");
5274                 return -EINVAL;
5275         }
5276
5277         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5278                         DRM_MODE_OBJECT_CRTC);
5279
5280         if (!drmmode_obj) {
5281                 DRM_ERROR("no such CRTC id\n");
5282                 return -EINVAL;
5283         }
5284
5285         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5286         pipe_from_crtc_id->pipe = crtc->pipe;
5287
5288         return 0;
5289 }
5290
5291 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5292 {
5293         struct intel_encoder *encoder;
5294         int index_mask = 0;
5295         int entry = 0;
5296
5297         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5298                 if (type_mask & encoder->clone_mask)
5299                         index_mask |= (1 << entry);
5300                 entry++;
5301         }
5302
5303         return index_mask;
5304 }
5305
5306 static void intel_setup_outputs(struct drm_device *dev)
5307 {
5308         struct drm_i915_private *dev_priv = dev->dev_private;
5309         struct intel_encoder *encoder;
5310         bool dpd_is_edp = false;
5311
5312         if (IS_MOBILE(dev) && !IS_I830(dev))
5313                 intel_lvds_init(dev);
5314
5315         if (HAS_PCH_SPLIT(dev)) {
5316                 dpd_is_edp = intel_dpd_is_edp(dev);
5317
5318                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5319                         intel_dp_init(dev, DP_A);
5320
5321                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5322                         intel_dp_init(dev, PCH_DP_D);
5323         }
5324
5325         intel_crt_init(dev);
5326
5327         if (HAS_PCH_SPLIT(dev)) {
5328                 int found;
5329
5330                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5331                         /* PCH SDVOB multiplex with HDMIB */
5332                         found = intel_sdvo_init(dev, PCH_SDVOB);
5333                         if (!found)
5334                                 intel_hdmi_init(dev, HDMIB);
5335                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5336                                 intel_dp_init(dev, PCH_DP_B);
5337                 }
5338
5339                 if (I915_READ(HDMIC) & PORT_DETECTED)
5340                         intel_hdmi_init(dev, HDMIC);
5341
5342                 if (I915_READ(HDMID) & PORT_DETECTED)
5343                         intel_hdmi_init(dev, HDMID);
5344
5345                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5346                         intel_dp_init(dev, PCH_DP_C);
5347
5348                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5349                         intel_dp_init(dev, PCH_DP_D);
5350
5351         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5352                 bool found = false;
5353
5354                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5355                         DRM_DEBUG_KMS("probing SDVOB\n");
5356                         found = intel_sdvo_init(dev, SDVOB);
5357                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5358                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5359                                 intel_hdmi_init(dev, SDVOB);
5360                         }
5361
5362                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5363                                 DRM_DEBUG_KMS("probing DP_B\n");
5364                                 intel_dp_init(dev, DP_B);
5365                         }
5366                 }
5367
5368                 /* Before G4X SDVOC doesn't have its own detect register */
5369
5370                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5371                         DRM_DEBUG_KMS("probing SDVOC\n");
5372                         found = intel_sdvo_init(dev, SDVOC);
5373                 }
5374
5375                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5376
5377                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5378                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5379                                 intel_hdmi_init(dev, SDVOC);
5380                         }
5381                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5382                                 DRM_DEBUG_KMS("probing DP_C\n");
5383                                 intel_dp_init(dev, DP_C);
5384                         }
5385                 }
5386
5387                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5388                     (I915_READ(DP_D) & DP_DETECTED)) {
5389                         DRM_DEBUG_KMS("probing DP_D\n");
5390                         intel_dp_init(dev, DP_D);
5391                 }
5392         } else if (IS_GEN2(dev))
5393                 intel_dvo_init(dev);
5394
5395         if (SUPPORTS_TV(dev))
5396                 intel_tv_init(dev);
5397
5398         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5399                 encoder->base.possible_crtcs = encoder->crtc_mask;
5400                 encoder->base.possible_clones =
5401                         intel_encoder_clones(dev, encoder->clone_mask);
5402         }
5403 }
5404
5405 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5406 {
5407         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5408
5409         drm_framebuffer_cleanup(fb);
5410         drm_gem_object_unreference_unlocked(intel_fb->obj);
5411
5412         kfree(intel_fb);
5413 }
5414
5415 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5416                                                 struct drm_file *file_priv,
5417                                                 unsigned int *handle)
5418 {
5419         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5420         struct drm_gem_object *object = intel_fb->obj;
5421
5422         return drm_gem_handle_create(file_priv, object, handle);
5423 }
5424
5425 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5426         .destroy = intel_user_framebuffer_destroy,
5427         .create_handle = intel_user_framebuffer_create_handle,
5428 };
5429
5430 int intel_framebuffer_init(struct drm_device *dev,
5431                            struct intel_framebuffer *intel_fb,
5432                            struct drm_mode_fb_cmd *mode_cmd,
5433                            struct drm_gem_object *obj)
5434 {
5435         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5436         int ret;
5437
5438         if (obj_priv->tiling_mode == I915_TILING_Y)
5439                 return -EINVAL;
5440
5441         if (mode_cmd->pitch & 63)
5442                 return -EINVAL;
5443
5444         switch (mode_cmd->bpp) {
5445         case 8:
5446         case 16:
5447         case 24:
5448         case 32:
5449                 break;
5450         default:
5451                 return -EINVAL;
5452         }
5453
5454         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5455         if (ret) {
5456                 DRM_ERROR("framebuffer init failed %d\n", ret);
5457                 return ret;
5458         }
5459
5460         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5461         intel_fb->obj = obj;
5462         return 0;
5463 }
5464
5465 static struct drm_framebuffer *
5466 intel_user_framebuffer_create(struct drm_device *dev,
5467                               struct drm_file *filp,
5468                               struct drm_mode_fb_cmd *mode_cmd)
5469 {
5470         struct drm_gem_object *obj;
5471         struct intel_framebuffer *intel_fb;
5472         int ret;
5473
5474         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5475         if (!obj)
5476                 return ERR_PTR(-ENOENT);
5477
5478         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5479         if (!intel_fb)
5480                 return ERR_PTR(-ENOMEM);
5481
5482         ret = intel_framebuffer_init(dev, intel_fb,
5483                                      mode_cmd, obj);
5484         if (ret) {
5485                 drm_gem_object_unreference_unlocked(obj);
5486                 kfree(intel_fb);
5487                 return ERR_PTR(ret);
5488         }
5489
5490         return &intel_fb->base;
5491 }
5492
5493 static const struct drm_mode_config_funcs intel_mode_funcs = {
5494         .fb_create = intel_user_framebuffer_create,
5495         .output_poll_changed = intel_fb_output_poll_changed,
5496 };
5497
5498 static struct drm_gem_object *
5499 intel_alloc_context_page(struct drm_device *dev)
5500 {
5501         struct drm_gem_object *ctx;
5502         int ret;
5503
5504         ctx = i915_gem_alloc_object(dev, 4096);
5505         if (!ctx) {
5506                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5507                 return NULL;
5508         }
5509
5510         mutex_lock(&dev->struct_mutex);
5511         ret = i915_gem_object_pin(ctx, 4096);
5512         if (ret) {
5513                 DRM_ERROR("failed to pin power context: %d\n", ret);
5514                 goto err_unref;
5515         }
5516
5517         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5518         if (ret) {
5519                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5520                 goto err_unpin;
5521         }
5522         mutex_unlock(&dev->struct_mutex);
5523
5524         return ctx;
5525
5526 err_unpin:
5527         i915_gem_object_unpin(ctx);
5528 err_unref:
5529         drm_gem_object_unreference(ctx);
5530         mutex_unlock(&dev->struct_mutex);
5531         return NULL;
5532 }
5533
5534 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5535 {
5536         struct drm_i915_private *dev_priv = dev->dev_private;
5537         u16 rgvswctl;
5538
5539         rgvswctl = I915_READ16(MEMSWCTL);
5540         if (rgvswctl & MEMCTL_CMD_STS) {
5541                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5542                 return false; /* still busy with another command */
5543         }
5544
5545         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5546                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5547         I915_WRITE16(MEMSWCTL, rgvswctl);
5548         POSTING_READ16(MEMSWCTL);
5549
5550         rgvswctl |= MEMCTL_CMD_STS;
5551         I915_WRITE16(MEMSWCTL, rgvswctl);
5552
5553         return true;
5554 }
5555
5556 void ironlake_enable_drps(struct drm_device *dev)
5557 {
5558         struct drm_i915_private *dev_priv = dev->dev_private;
5559         u32 rgvmodectl = I915_READ(MEMMODECTL);
5560         u8 fmax, fmin, fstart, vstart;
5561
5562         /* Enable temp reporting */
5563         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5564         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5565
5566         /* 100ms RC evaluation intervals */
5567         I915_WRITE(RCUPEI, 100000);
5568         I915_WRITE(RCDNEI, 100000);
5569
5570         /* Set max/min thresholds to 90ms and 80ms respectively */
5571         I915_WRITE(RCBMAXAVG, 90000);
5572         I915_WRITE(RCBMINAVG, 80000);
5573
5574         I915_WRITE(MEMIHYST, 1);
5575
5576         /* Set up min, max, and cur for interrupt handling */
5577         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5578         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5579         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5580                 MEMMODE_FSTART_SHIFT;
5581         fstart = fmax;
5582
5583         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5584                 PXVFREQ_PX_SHIFT;
5585
5586         dev_priv->fmax = fstart; /* IPS callback will increase this */
5587         dev_priv->fstart = fstart;
5588
5589         dev_priv->max_delay = fmax;
5590         dev_priv->min_delay = fmin;
5591         dev_priv->cur_delay = fstart;
5592
5593         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5594                          fstart);
5595
5596         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5597
5598         /*
5599          * Interrupts will be enabled in ironlake_irq_postinstall
5600          */
5601
5602         I915_WRITE(VIDSTART, vstart);
5603         POSTING_READ(VIDSTART);
5604
5605         rgvmodectl |= MEMMODE_SWMODE_EN;
5606         I915_WRITE(MEMMODECTL, rgvmodectl);
5607
5608         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5609                 DRM_ERROR("stuck trying to change perf mode\n");
5610         msleep(1);
5611
5612         ironlake_set_drps(dev, fstart);
5613
5614         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5615                 I915_READ(0x112e0);
5616         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5617         dev_priv->last_count2 = I915_READ(0x112f4);
5618         getrawmonotonic(&dev_priv->last_time2);
5619 }
5620
5621 void ironlake_disable_drps(struct drm_device *dev)
5622 {
5623         struct drm_i915_private *dev_priv = dev->dev_private;
5624         u16 rgvswctl = I915_READ16(MEMSWCTL);
5625
5626         /* Ack interrupts, disable EFC interrupt */
5627         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5628         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5629         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5630         I915_WRITE(DEIIR, DE_PCU_EVENT);
5631         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5632
5633         /* Go back to the starting frequency */
5634         ironlake_set_drps(dev, dev_priv->fstart);
5635         msleep(1);
5636         rgvswctl |= MEMCTL_CMD_STS;
5637         I915_WRITE(MEMSWCTL, rgvswctl);
5638         msleep(1);
5639
5640 }
5641
5642 static unsigned long intel_pxfreq(u32 vidfreq)
5643 {
5644         unsigned long freq;
5645         int div = (vidfreq & 0x3f0000) >> 16;
5646         int post = (vidfreq & 0x3000) >> 12;
5647         int pre = (vidfreq & 0x7);
5648
5649         if (!pre)
5650                 return 0;
5651
5652         freq = ((div * 133333) / ((1<<post) * pre));
5653
5654         return freq;
5655 }
5656
5657 void intel_init_emon(struct drm_device *dev)
5658 {
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660         u32 lcfuse;
5661         u8 pxw[16];
5662         int i;
5663
5664         /* Disable to program */
5665         I915_WRITE(ECR, 0);
5666         POSTING_READ(ECR);
5667
5668         /* Program energy weights for various events */
5669         I915_WRITE(SDEW, 0x15040d00);
5670         I915_WRITE(CSIEW0, 0x007f0000);
5671         I915_WRITE(CSIEW1, 0x1e220004);
5672         I915_WRITE(CSIEW2, 0x04000004);
5673
5674         for (i = 0; i < 5; i++)
5675                 I915_WRITE(PEW + (i * 4), 0);
5676         for (i = 0; i < 3; i++)
5677                 I915_WRITE(DEW + (i * 4), 0);
5678
5679         /* Program P-state weights to account for frequency power adjustment */
5680         for (i = 0; i < 16; i++) {
5681                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5682                 unsigned long freq = intel_pxfreq(pxvidfreq);
5683                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5684                         PXVFREQ_PX_SHIFT;
5685                 unsigned long val;
5686
5687                 val = vid * vid;
5688                 val *= (freq / 1000);
5689                 val *= 255;
5690                 val /= (127*127*900);
5691                 if (val > 0xff)
5692                         DRM_ERROR("bad pxval: %ld\n", val);
5693                 pxw[i] = val;
5694         }
5695         /* Render standby states get 0 weight */
5696         pxw[14] = 0;
5697         pxw[15] = 0;
5698
5699         for (i = 0; i < 4; i++) {
5700                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5701                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5702                 I915_WRITE(PXW + (i * 4), val);
5703         }
5704
5705         /* Adjust magic regs to magic values (more experimental results) */
5706         I915_WRITE(OGW0, 0);
5707         I915_WRITE(OGW1, 0);
5708         I915_WRITE(EG0, 0x00007f00);
5709         I915_WRITE(EG1, 0x0000000e);
5710         I915_WRITE(EG2, 0x000e0000);
5711         I915_WRITE(EG3, 0x68000300);
5712         I915_WRITE(EG4, 0x42000000);
5713         I915_WRITE(EG5, 0x00140031);
5714         I915_WRITE(EG6, 0);
5715         I915_WRITE(EG7, 0);
5716
5717         for (i = 0; i < 8; i++)
5718                 I915_WRITE(PXWL + (i * 4), 0);
5719
5720         /* Enable PMON + select events */
5721         I915_WRITE(ECR, 0x80000019);
5722
5723         lcfuse = I915_READ(LCFUSE02);
5724
5725         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5726 }
5727
5728 void intel_init_clock_gating(struct drm_device *dev)
5729 {
5730         struct drm_i915_private *dev_priv = dev->dev_private;
5731
5732         /*
5733          * Disable clock gating reported to work incorrectly according to the
5734          * specs, but enable as much else as we can.
5735          */
5736         if (HAS_PCH_SPLIT(dev)) {
5737                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5738
5739                 if (IS_IRONLAKE(dev)) {
5740                         /* Required for FBC */
5741                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5742                         /* Required for CxSR */
5743                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5744
5745                         I915_WRITE(PCH_3DCGDIS0,
5746                                    MARIUNIT_CLOCK_GATE_DISABLE |
5747                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5748                 }
5749
5750                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5751
5752                 /*
5753                  * According to the spec the following bits should be set in
5754                  * order to enable memory self-refresh
5755                  * The bit 22/21 of 0x42004
5756                  * The bit 5 of 0x42020
5757                  * The bit 15 of 0x45000
5758                  */
5759                 if (IS_IRONLAKE(dev)) {
5760                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5761                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5762                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5763                         I915_WRITE(ILK_DSPCLK_GATE,
5764                                         (I915_READ(ILK_DSPCLK_GATE) |
5765                                                 ILK_DPARB_CLK_GATE));
5766                         I915_WRITE(DISP_ARB_CTL,
5767                                         (I915_READ(DISP_ARB_CTL) |
5768                                                 DISP_FBC_WM_DIS));
5769                 I915_WRITE(WM3_LP_ILK, 0);
5770                 I915_WRITE(WM2_LP_ILK, 0);
5771                 I915_WRITE(WM1_LP_ILK, 0);
5772                 }
5773                 /*
5774                  * Based on the document from hardware guys the following bits
5775                  * should be set unconditionally in order to enable FBC.
5776                  * The bit 22 of 0x42000
5777                  * The bit 22 of 0x42004
5778                  * The bit 7,8,9 of 0x42020.
5779                  */
5780                 if (IS_IRONLAKE_M(dev)) {
5781                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5782                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5783                                    ILK_FBCQ_DIS);
5784                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5785                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5786                                    ILK_DPARB_GATE);
5787                         I915_WRITE(ILK_DSPCLK_GATE,
5788                                    I915_READ(ILK_DSPCLK_GATE) |
5789                                    ILK_DPFC_DIS1 |
5790                                    ILK_DPFC_DIS2 |
5791                                    ILK_CLK_FBC);
5792                 }
5793                 return;
5794         } else if (IS_G4X(dev)) {
5795                 uint32_t dspclk_gate;
5796                 I915_WRITE(RENCLK_GATE_D1, 0);
5797                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5798                        GS_UNIT_CLOCK_GATE_DISABLE |
5799                        CL_UNIT_CLOCK_GATE_DISABLE);
5800                 I915_WRITE(RAMCLK_GATE_D, 0);
5801                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5802                         OVRUNIT_CLOCK_GATE_DISABLE |
5803                         OVCUNIT_CLOCK_GATE_DISABLE;
5804                 if (IS_GM45(dev))
5805                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5806                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5807         } else if (IS_CRESTLINE(dev)) {
5808                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5809                 I915_WRITE(RENCLK_GATE_D2, 0);
5810                 I915_WRITE(DSPCLK_GATE_D, 0);
5811                 I915_WRITE(RAMCLK_GATE_D, 0);
5812                 I915_WRITE16(DEUC, 0);
5813         } else if (IS_BROADWATER(dev)) {
5814                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5815                        I965_RCC_CLOCK_GATE_DISABLE |
5816                        I965_RCPB_CLOCK_GATE_DISABLE |
5817                        I965_ISC_CLOCK_GATE_DISABLE |
5818                        I965_FBC_CLOCK_GATE_DISABLE);
5819                 I915_WRITE(RENCLK_GATE_D2, 0);
5820         } else if (IS_GEN3(dev)) {
5821                 u32 dstate = I915_READ(D_STATE);
5822
5823                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5824                         DSTATE_DOT_CLOCK_GATING;
5825                 I915_WRITE(D_STATE, dstate);
5826         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5827                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5828         } else if (IS_I830(dev)) {
5829                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5830         }
5831
5832         /*
5833          * GPU can automatically power down the render unit if given a page
5834          * to save state.
5835          */
5836         if (IS_IRONLAKE_M(dev)) {
5837                 if (dev_priv->renderctx == NULL)
5838                         dev_priv->renderctx = intel_alloc_context_page(dev);
5839                 if (dev_priv->renderctx) {
5840                         struct drm_i915_gem_object *obj_priv;
5841                         obj_priv = to_intel_bo(dev_priv->renderctx);
5842                         if (obj_priv) {
5843                                 BEGIN_LP_RING(4);
5844                                 OUT_RING(MI_SET_CONTEXT);
5845                                 OUT_RING(obj_priv->gtt_offset |
5846                                                 MI_MM_SPACE_GTT |
5847                                                 MI_SAVE_EXT_STATE_EN |
5848                                                 MI_RESTORE_EXT_STATE_EN |
5849                                                 MI_RESTORE_INHIBIT);
5850                                 OUT_RING(MI_NOOP);
5851                                 OUT_RING(MI_FLUSH);
5852                                 ADVANCE_LP_RING();
5853                         }
5854                 } else
5855                         DRM_DEBUG_KMS("Failed to allocate render context."
5856                                        "Disable RC6\n");
5857         }
5858
5859         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5860                 struct drm_i915_gem_object *obj_priv = NULL;
5861
5862                 if (dev_priv->pwrctx) {
5863                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5864                 } else {
5865                         struct drm_gem_object *pwrctx;
5866
5867                         pwrctx = intel_alloc_context_page(dev);
5868                         if (pwrctx) {
5869                                 dev_priv->pwrctx = pwrctx;
5870                                 obj_priv = to_intel_bo(pwrctx);
5871                         }
5872                 }
5873
5874                 if (obj_priv) {
5875                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5876                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5877                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5878                 }
5879         }
5880 }
5881
5882 /* Set up chip specific display functions */
5883 static void intel_init_display(struct drm_device *dev)
5884 {
5885         struct drm_i915_private *dev_priv = dev->dev_private;
5886
5887         /* We always want a DPMS function */
5888         if (HAS_PCH_SPLIT(dev))
5889                 dev_priv->display.dpms = ironlake_crtc_dpms;
5890         else
5891                 dev_priv->display.dpms = i9xx_crtc_dpms;
5892
5893         if (I915_HAS_FBC(dev)) {
5894                 if (IS_IRONLAKE_M(dev)) {
5895                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5896                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5897                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5898                 } else if (IS_GM45(dev)) {
5899                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5900                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5901                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5902                 } else if (IS_CRESTLINE(dev)) {
5903                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5904                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5905                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5906                 }
5907                 /* 855GM needs testing */
5908         }
5909
5910         /* Returns the core display clock speed */
5911         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5912                 dev_priv->display.get_display_clock_speed =
5913                         i945_get_display_clock_speed;
5914         else if (IS_I915G(dev))
5915                 dev_priv->display.get_display_clock_speed =
5916                         i915_get_display_clock_speed;
5917         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5918                 dev_priv->display.get_display_clock_speed =
5919                         i9xx_misc_get_display_clock_speed;
5920         else if (IS_I915GM(dev))
5921                 dev_priv->display.get_display_clock_speed =
5922                         i915gm_get_display_clock_speed;
5923         else if (IS_I865G(dev))
5924                 dev_priv->display.get_display_clock_speed =
5925                         i865_get_display_clock_speed;
5926         else if (IS_I85X(dev))
5927                 dev_priv->display.get_display_clock_speed =
5928                         i855_get_display_clock_speed;
5929         else /* 852, 830 */
5930                 dev_priv->display.get_display_clock_speed =
5931                         i830_get_display_clock_speed;
5932
5933         /* For FIFO watermark updates */
5934         if (HAS_PCH_SPLIT(dev)) {
5935                 if (IS_IRONLAKE(dev)) {
5936                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5937                                 dev_priv->display.update_wm = ironlake_update_wm;
5938                         else {
5939                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5940                                               "Disable CxSR\n");
5941                                 dev_priv->display.update_wm = NULL;
5942                         }
5943                 } else
5944                         dev_priv->display.update_wm = NULL;
5945         } else if (IS_PINEVIEW(dev)) {
5946                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5947                                             dev_priv->is_ddr3,
5948                                             dev_priv->fsb_freq,
5949                                             dev_priv->mem_freq)) {
5950                         DRM_INFO("failed to find known CxSR latency "
5951                                  "(found ddr%s fsb freq %d, mem freq %d), "
5952                                  "disabling CxSR\n",
5953                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5954                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5955                         /* Disable CxSR and never update its watermark again */
5956                         pineview_disable_cxsr(dev);
5957                         dev_priv->display.update_wm = NULL;
5958                 } else
5959                         dev_priv->display.update_wm = pineview_update_wm;
5960         } else if (IS_G4X(dev))
5961                 dev_priv->display.update_wm = g4x_update_wm;
5962         else if (IS_GEN4(dev))
5963                 dev_priv->display.update_wm = i965_update_wm;
5964         else if (IS_GEN3(dev)) {
5965                 dev_priv->display.update_wm = i9xx_update_wm;
5966                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5967         } else if (IS_I85X(dev)) {
5968                 dev_priv->display.update_wm = i9xx_update_wm;
5969                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5970         } else {
5971                 dev_priv->display.update_wm = i830_update_wm;
5972                 if (IS_845G(dev))
5973                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5974                 else
5975                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5976         }
5977 }
5978
5979 /*
5980  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5981  * resume, or other times.  This quirk makes sure that's the case for
5982  * affected systems.
5983  */
5984 static void quirk_pipea_force (struct drm_device *dev)
5985 {
5986         struct drm_i915_private *dev_priv = dev->dev_private;
5987
5988         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5989         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5990 }
5991
5992 struct intel_quirk {
5993         int device;
5994         int subsystem_vendor;
5995         int subsystem_device;
5996         void (*hook)(struct drm_device *dev);
5997 };
5998
5999 struct intel_quirk intel_quirks[] = {
6000         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6001         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6002         /* HP Mini needs pipe A force quirk (LP: #322104) */
6003         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6004
6005         /* Thinkpad R31 needs pipe A force quirk */
6006         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6007         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6008         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6009
6010         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6011         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6012         /* ThinkPad X40 needs pipe A force quirk */
6013
6014         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6015         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6016
6017         /* 855 & before need to leave pipe A & dpll A up */
6018         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6019         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6020 };
6021
6022 static void intel_init_quirks(struct drm_device *dev)
6023 {
6024         struct pci_dev *d = dev->pdev;
6025         int i;
6026
6027         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6028                 struct intel_quirk *q = &intel_quirks[i];
6029
6030                 if (d->device == q->device &&
6031                     (d->subsystem_vendor == q->subsystem_vendor ||
6032                      q->subsystem_vendor == PCI_ANY_ID) &&
6033                     (d->subsystem_device == q->subsystem_device ||
6034                      q->subsystem_device == PCI_ANY_ID))
6035                         q->hook(dev);
6036         }
6037 }
6038
6039 /* Disable the VGA plane that we never use */
6040 static void i915_disable_vga(struct drm_device *dev)
6041 {
6042         struct drm_i915_private *dev_priv = dev->dev_private;
6043         u8 sr1;
6044         u32 vga_reg;
6045
6046         if (HAS_PCH_SPLIT(dev))
6047                 vga_reg = CPU_VGACNTRL;
6048         else
6049                 vga_reg = VGACNTRL;
6050
6051         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6052         outb(1, VGA_SR_INDEX);
6053         sr1 = inb(VGA_SR_DATA);
6054         outb(sr1 | 1<<5, VGA_SR_DATA);
6055         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6056         udelay(300);
6057
6058         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6059         POSTING_READ(vga_reg);
6060 }
6061
6062 void intel_modeset_init(struct drm_device *dev)
6063 {
6064         struct drm_i915_private *dev_priv = dev->dev_private;
6065         int i;
6066
6067         drm_mode_config_init(dev);
6068
6069         dev->mode_config.min_width = 0;
6070         dev->mode_config.min_height = 0;
6071
6072         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6073
6074         intel_init_quirks(dev);
6075
6076         intel_init_display(dev);
6077
6078         if (IS_GEN2(dev)) {
6079                 dev->mode_config.max_width = 2048;
6080                 dev->mode_config.max_height = 2048;
6081         } else if (IS_GEN3(dev)) {
6082                 dev->mode_config.max_width = 4096;
6083                 dev->mode_config.max_height = 4096;
6084         } else {
6085                 dev->mode_config.max_width = 8192;
6086                 dev->mode_config.max_height = 8192;
6087         }
6088
6089         /* set memory base */
6090         if (IS_GEN2(dev))
6091                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6092         else
6093                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6094
6095         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6096                 dev_priv->num_pipe = 2;
6097         else
6098                 dev_priv->num_pipe = 1;
6099         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6100                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6101
6102         for (i = 0; i < dev_priv->num_pipe; i++) {
6103                 intel_crtc_init(dev, i);
6104         }
6105
6106         intel_setup_outputs(dev);
6107
6108         intel_init_clock_gating(dev);
6109
6110         /* Just disable it once at startup */
6111         i915_disable_vga(dev);
6112
6113         if (IS_IRONLAKE_M(dev)) {
6114                 ironlake_enable_drps(dev);
6115                 intel_init_emon(dev);
6116         }
6117
6118         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6119         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6120                     (unsigned long)dev);
6121
6122         intel_setup_overlay(dev);
6123 }
6124
6125 void intel_modeset_cleanup(struct drm_device *dev)
6126 {
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128         struct drm_crtc *crtc;
6129         struct intel_crtc *intel_crtc;
6130
6131         drm_kms_helper_poll_fini(dev);
6132         mutex_lock(&dev->struct_mutex);
6133
6134         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6135                 /* Skip inactive CRTCs */
6136                 if (!crtc->fb)
6137                         continue;
6138
6139                 intel_crtc = to_intel_crtc(crtc);
6140                 intel_increase_pllclock(crtc);
6141         }
6142
6143         if (dev_priv->display.disable_fbc)
6144                 dev_priv->display.disable_fbc(dev);
6145
6146         if (dev_priv->renderctx) {
6147                 struct drm_i915_gem_object *obj_priv;
6148
6149                 obj_priv = to_intel_bo(dev_priv->renderctx);
6150                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6151                 I915_READ(CCID);
6152                 i915_gem_object_unpin(dev_priv->renderctx);
6153                 drm_gem_object_unreference(dev_priv->renderctx);
6154         }
6155
6156         if (dev_priv->pwrctx) {
6157                 struct drm_i915_gem_object *obj_priv;
6158
6159                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6160                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6161                 I915_READ(PWRCTXA);
6162                 i915_gem_object_unpin(dev_priv->pwrctx);
6163                 drm_gem_object_unreference(dev_priv->pwrctx);
6164         }
6165
6166         if (IS_IRONLAKE_M(dev))
6167                 ironlake_disable_drps(dev);
6168
6169         mutex_unlock(&dev->struct_mutex);
6170
6171         /* Disable the irq before mode object teardown, for the irq might
6172          * enqueue unpin/hotplug work. */
6173         drm_irq_uninstall(dev);
6174         cancel_work_sync(&dev_priv->hotplug_work);
6175
6176         /* Shut off idle work before the crtcs get freed. */
6177         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6178                 intel_crtc = to_intel_crtc(crtc);
6179                 del_timer_sync(&intel_crtc->idle_timer);
6180         }
6181         del_timer_sync(&dev_priv->idle_timer);
6182         cancel_work_sync(&dev_priv->idle_work);
6183
6184         drm_mode_config_cleanup(dev);
6185 }
6186
6187 /*
6188  * Return which encoder is currently attached for connector.
6189  */
6190 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6191 {
6192         return &intel_attached_encoder(connector)->base;
6193 }
6194
6195 void intel_connector_attach_encoder(struct intel_connector *connector,
6196                                     struct intel_encoder *encoder)
6197 {
6198         connector->encoder = encoder;
6199         drm_mode_connector_attach_encoder(&connector->base,
6200                                           &encoder->base);
6201 }
6202
6203 /*
6204  * set vga decode state - true == enable VGA decode
6205  */
6206 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6207 {
6208         struct drm_i915_private *dev_priv = dev->dev_private;
6209         u16 gmch_ctrl;
6210
6211         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6212         if (state)
6213                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6214         else
6215                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6216         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6217         return 0;
6218 }