sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <linux/moduleparam.h>
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/rawmidi.h>
  35 #ifdef CHIP1371
  36 #include <sound/ac97_codec.h>
  37 #else
  38 #include <sound/ak4531_codec.h>
  39 #endif
  40 #include <sound/initval.h>
  41 #include <sound/asoundef.h>
  42
  43 #ifndef CHIP1371
  44 #undef CHIP1370
  45 #define CHIP1370
  46 #endif
  47
  48 #ifdef CHIP1370
  49 #define DRIVER_NAME "ENS1370"
  50 #else
  51 #define DRIVER_NAME "ENS1371"
  52 #endif
  53
  54
  55 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  56 MODULE_LICENSE("GPL");
  57 #ifdef CHIP1370
  58 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  59 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  60                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  61 #endif
  62 #ifdef CHIP1371
  63 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  64 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  65                 "{Ensoniq,AudioPCI ES1373},"
  66                 "{Creative Labs,Ectiva EV1938},"
  67                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  68                 "{Creative Labs,Vibra PCI128},"
  69                 "{Ectiva,EV1938}}");
  70 #endif
  71
  72 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  73 #define SUPPORT_JOYSTICK
  74 #endif
  75
  76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  79 #ifdef SUPPORT_JOYSTICK
  80 #ifdef CHIP1371
  81 static int joystick_port[SNDRV_CARDS];
  82 #else
  83 static int joystick[SNDRV_CARDS];
  84 #endif
  85 #endif
  86
  87 module_param_array(index, int, NULL, 0444);
  88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  89 module_param_array(id, charp, NULL, 0444);
  90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  91 module_param_array(enable, bool, NULL, 0444);
  92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  93 #ifdef SUPPORT_JOYSTICK
  94 #ifdef CHIP1371
  95 module_param_array(joystick_port, int, NULL, 0444);
  96 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  97 #else
  98 module_param_array(joystick, bool, NULL, 0444);
  99 MODULE_PARM_DESC(joystick, "Enable joystick.");
 100 #endif
 101 #endif /* SUPPORT_JOYSTICK */
 102
 103 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
 104 #define PCI_DEVICE_ID_ENSONIQ_CT5880    0x5880
 105 #endif
 106 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
 107 #define PCI_DEVICE_ID_ENSONIQ_ES1371    0x1371
 108 #endif
 109
 110 /* ES1371 chip ID */
 111 /* This is a little confusing because all ES1371 compatible chips have the
 112    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 113    This is only significant if you want to enable features on the later parts.
 114    Yes, I know it's stupid and why didn't we use the sub IDs?
 115 */
 116 #define ES1371REV_ES1373_A  0x04
 117 #define ES1371REV_ES1373_B  0x06
 118 #define ES1371REV_CT5880_A  0x07
 119 #define CT5880REV_CT5880_C  0x02
 120 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 121 #define CT5880REV_CT5880_E  0x04        /* mw */
 122 #define ES1371REV_ES1371_B  0x09
 123 #define EV1938REV_EV1938_A  0x00
 124 #define ES1371REV_ES1373_8  0x08
 125
 126 /*
 127  * Direct registers
 128  */
 129
 130 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 131
 132 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 133 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 134 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 135 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 136 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 137 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 138 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 139 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 140 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 141 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 142 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 143 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 144 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 145 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 146 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 147 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 148 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 149 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 150 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 151 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 152 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 153 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 154 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 155 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 156 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 157 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 158 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 159 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 160 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 161 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 162 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 163 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 164 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 165 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 166 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 167 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 168 #define   ES_UART_EN            (1<<3)          /* UART enable */
 169 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 170 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 171 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 172 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 173 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 174 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 175 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 176 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 177 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 178 #define   ES_1373_REAR_BIT26    (1<<26)
 179 #define   ES_1373_REAR_BIT24    (1<<24)
 180 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 181 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 182 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 183 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 184 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 185 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 186 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 187 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 188 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 189 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 190 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 191 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 192 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 193 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 194 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 195 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 196 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 197 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 198 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 199 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 200 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 201 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 202 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 203 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 204 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 205 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 206 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 207 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 208 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 209 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 210 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 211 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 212 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 213 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 214 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 215 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 216 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 217 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 218 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 219 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 220 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 221 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 222 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 223 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 224 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 225
 226 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 227 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 228 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 229 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 230 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 231 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 232 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 233 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 234 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 235 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 236 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 237 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 238 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 239
 240 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 241 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 242 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 243 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 244 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 245 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 246 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 247 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 248 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 249 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 250 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 251 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 252 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 253 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 254 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 255 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 256 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 257 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 258 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 259 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 260 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 261 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 262 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 263
 264 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 265
 266 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 267 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 268 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 269 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 270 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 271 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 272 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 273 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 274 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 275 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 276 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 277 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 278 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 279 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 280 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 281 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 282 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 283 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 284 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 285 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 286 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 287 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 288 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 289 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 290 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 291 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 292 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 293
 294 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 295 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 296 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 297 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 298 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 299 #define   ES_REG_COUNTM         (0xffff<<0)
 300 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 301
 302 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 303 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 304 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 305 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 306 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 307 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 308 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 309 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 310 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 311 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 312 #define   ES_REG_FSIZEM          (0xffff<<0)
 313 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 314 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 315 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 316
 317 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 318 #define   ES_REG_UF_VALID        (1<<8)
 319 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 320 #define   ES_REG_UF_BYTEM        (0xff<<0)
 321 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 322
 323
 324 /*
 325  *  Pages
 326  */
 327
 328 #define ES_PAGE_DAC     0x0c
 329 #define ES_PAGE_ADC     0x0d
 330 #define ES_PAGE_UART    0x0e
 331 #define ES_PAGE_UART1   0x0f
 332
 333 /*
 334  *  Sample rate converter addresses
 335  */
 336
 337 #define ES_SMPREG_DAC1          0x70
 338 #define ES_SMPREG_DAC2          0x74
 339 #define ES_SMPREG_ADC           0x78
 340 #define ES_SMPREG_VOL_ADC       0x6c
 341 #define ES_SMPREG_VOL_DAC1      0x7c
 342 #define ES_SMPREG_VOL_DAC2      0x7e
 343 #define ES_SMPREG_TRUNC_N       0x00
 344 #define ES_SMPREG_INT_REGS      0x01
 345 #define ES_SMPREG_ACCUM_FRAC    0x02
 346 #define ES_SMPREG_VFREQ_FRAC    0x03
 347
 348 /*
 349  *  Some contants
 350  */
 351
 352 #define ES_1370_SRCLOCK    1411200
 353 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 354
 355 /*
 356  *  Open modes
 357  */
 358
 359 #define ES_MODE_PLAY1   0x0001
 360 #define ES_MODE_PLAY2   0x0002
 361 #define ES_MODE_CAPTURE 0x0004
 362
 363 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 364 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 365
 366 /*
 367
 368  */
 369
 370 typedef struct _snd_ensoniq ensoniq_t;
 371
 372 struct _snd_ensoniq {
 373         spinlock_t reg_lock;
 374         struct semaphore src_mutex;
 375
 376         int irq;
 377
 378         unsigned long playback1size;
 379         unsigned long playback2size;
 380         unsigned long capture3size;
 381
 382         unsigned long port;
 383         unsigned int mode;
 384         unsigned int uartm;     /* UART mode */
 385
 386         unsigned int ctrl;      /* control register */
 387         unsigned int sctrl;     /* serial control register */
 388         unsigned int cssr;      /* control status register */
 389         unsigned int uartc;     /* uart control register */
 390         unsigned int rev;       /* chip revision */
 391
 392         union {
 393 #ifdef CHIP1371
 394                 struct {
 395                         ac97_t *ac97;
 396                 } es1371;
 397 #else
 398                 struct {
 399                         int pclkdiv_lock;
 400                         ak4531_t *ak4531;
 401                 } es1370;
 402 #endif
 403         } u;
 404
 405         struct pci_dev *pci;
 406         unsigned short subsystem_vendor_id;
 407         unsigned short subsystem_device_id;
 408         snd_card_t *card;
 409         snd_pcm_t *pcm1;        /* DAC1/ADC PCM */
 410         snd_pcm_t *pcm2;        /* DAC2 PCM */
 411         snd_pcm_substream_t *playback1_substream;
 412         snd_pcm_substream_t *playback2_substream;
 413         snd_pcm_substream_t *capture_substream;
 414         unsigned int p1_dma_size;
 415         unsigned int p2_dma_size;
 416         unsigned int c_dma_size;
 417         unsigned int p1_period_size;
 418         unsigned int p2_period_size;
 419         unsigned int c_period_size;
 420         snd_rawmidi_t *rmidi;
 421         snd_rawmidi_substream_t *midi_input;
 422         snd_rawmidi_substream_t *midi_output;
 423
 424         unsigned int spdif;
 425         unsigned int spdif_default;
 426         unsigned int spdif_stream;
 427
 428 #ifdef CHIP1370
 429         struct snd_dma_buffer dma_bug;
 430 #endif
 431
 432 #ifdef SUPPORT_JOYSTICK
 433         struct gameport *gameport;
 434 #endif
 435 };
 436
 437 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 438
 439 static struct pci_device_id snd_audiopci_ids[] = {
 440 #ifdef CHIP1370
 441         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 442 #endif
 443 #ifdef CHIP1371
 444         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 445         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 446         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 447 #endif
 448         { 0, }
 449 };
 450
 451 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 452
 453 /*
 454  *  constants
 455  */
 456
 457 #define POLL_COUNT      0xa000
 458
 459 #ifdef CHIP1370
 460 static unsigned int snd_es1370_fixed_rates[] =
 461         {5512, 11025, 22050, 44100};
 462 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
 463         .count = 4,
 464         .list = snd_es1370_fixed_rates,
 465         .mask = 0,
 466 };
 467 static ratnum_t es1370_clock = {
 468         .num = ES_1370_SRCLOCK,
 469         .den_min = 29,
 470         .den_max = 353,
 471         .den_step = 1,
 472 };
 473 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
 474         .nrats = 1,
 475         .rats = &es1370_clock,
 476 };
 477 #else
 478 static ratden_t es1371_dac_clock = {
 479         .num_min = 3000 * (1 << 15),
 480         .num_max = 48000 * (1 << 15),
 481         .num_step = 3000,
 482         .den = 1 << 15,
 483 };
 484 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
 485         .nrats = 1,
 486         .rats = &es1371_dac_clock,
 487 };
 488 static ratnum_t es1371_adc_clock = {
 489         .num = 48000 << 15,
 490         .den_min = 32768,
 491         .den_max = 393216,
 492         .den_step = 1,
 493 };
 494 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
 495         .nrats = 1,
 496         .rats = &es1371_adc_clock,
 497 };
 498 #endif
 499 static const unsigned int snd_ensoniq_sample_shift[] =
 500         {0, 1, 1, 2};
 501
 502 /*
 503  *  common I/O routines
 504  */
 505
 506 #ifdef CHIP1371
 507
 508 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
 509 {
 510         unsigned int t, r = 0;
 511
 512         for (t = 0; t < POLL_COUNT; t++) {
 513                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 514                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 515                         return r;
 516                 cond_resched();
 517         }
 518         snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
 519         return 0;
 520 }
 521
 522 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
 523 {
 524         unsigned int temp, i, orig, r;
 525
 526         /* wait for ready */
 527         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 528
 529         /* expose the SRC state bits */
 530         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 531                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 532         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 533         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 534
 535         /* now, wait for busy and the correct time to read */
 536         temp = snd_es1371_wait_src_ready(ensoniq);
 537
 538         if ((temp & 0x00870000) != 0x00010000) {
 539                 /* wait for the right state */
 540                 for (i = 0; i < POLL_COUNT; i++) {
 541                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 542                         if ((temp & 0x00870000) == 0x00010000)
 543                                 break;
 544                 }
 545         }
 546
 547         /* hide the state bits */
 548         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 549                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 550         r |= ES_1371_SRC_RAM_ADDRO(reg);
 551         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 552
 553         return temp;
 554 }
 555
 556 static void snd_es1371_src_write(ensoniq_t * ensoniq,
 557                                  unsigned short reg, unsigned short data)
 558 {
 559         unsigned int r;
 560
 561         r = snd_es1371_wait_src_ready(ensoniq) &
 562             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 563              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 564         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 565         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 566 }
 567
 568 #endif /* CHIP1371 */
 569
 570 #ifdef CHIP1370
 571
 572 static void snd_es1370_codec_write(ak4531_t *ak4531,
 573                                    unsigned short reg, unsigned short val)
 574 {
 575         ensoniq_t *ensoniq = ak4531->private_data;
 576         unsigned long end_time = jiffies + HZ / 10;
 577
 578 #if 0
 579         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 580 #endif
 581         do {
 582                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 583                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 584                         return;
 585                 }
 586                 set_current_state(TASK_UNINTERRUPTIBLE);
 587                 schedule_timeout(1);
 588         } while (time_after(end_time, jiffies));
 589         snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
 590 }
 591
 592 #endif /* CHIP1370 */
 593
 594 #ifdef CHIP1371
 595
 596 static void snd_es1371_codec_write(ac97_t *ac97,
 597                                    unsigned short reg, unsigned short val)
 598 {
 599         ensoniq_t *ensoniq = ac97->private_data;
 600         unsigned int t, x;
 601
 602         down(&ensoniq->src_mutex);
 603         for (t = 0; t < POLL_COUNT; t++) {
 604                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 605                         /* save the current state for latter */
 606                         x = snd_es1371_wait_src_ready(ensoniq);
 607                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 608                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 609                              ES_REG(ensoniq, 1371_SMPRATE));
 610                         /* wait for not busy (state 0) first to avoid
 611                            transition states */
 612                         for (t = 0; t < POLL_COUNT; t++) {
 613                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 614                                         break;
 615                         }
 616                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 617                         for (t = 0; t < POLL_COUNT; t++) {
 618                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 619                                         break;
 620                         }
 621                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 622                         /* restore SRC reg */
 623                         snd_es1371_wait_src_ready(ensoniq);
 624                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 625                         up(&ensoniq->src_mutex);
 626                         return;
 627                 }
 628         }
 629         up(&ensoniq->src_mutex);
 630         snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 631 }
 632
 633 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 634                                             unsigned short reg)
 635 {
 636         ensoniq_t *ensoniq = ac97->private_data;
 637         unsigned int t, x, fail = 0;
 638
 639       __again:
 640         down(&ensoniq->src_mutex);
 641         for (t = 0; t < POLL_COUNT; t++) {
 642                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 643                         /* save the current state for latter */
 644                         x = snd_es1371_wait_src_ready(ensoniq);
 645                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 646                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 647                              ES_REG(ensoniq, 1371_SMPRATE));
 648                         /* wait for not busy (state 0) first to avoid
 649                            transition states */
 650                         for (t = 0; t < POLL_COUNT; t++) {
 651                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 652                                         break;
 653                         }
 654                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 655                         for (t = 0; t < POLL_COUNT; t++) {
 656                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 657                                         break;
 658                         }
 659                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 660                         /* restore SRC reg */
 661                         snd_es1371_wait_src_ready(ensoniq);
 662                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 663                         /* wait for WIP again */
 664                         for (t = 0; t < POLL_COUNT; t++) {
 665                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 666                                         break;
 667                         }
 668                         /* now wait for the stinkin' data (RDY) */
 669                         for (t = 0; t < POLL_COUNT; t++) {
 670                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 671                                         up(&ensoniq->src_mutex);
 672                                         return ES_1371_CODEC_READ(x);
 673                                 }
 674                         }
 675                         up(&ensoniq->src_mutex);
 676                         if (++fail > 10) {
 677                                 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
 678                                 return 0;
 679                         }
 680                         goto __again;
 681                 }
 682         }
 683         up(&ensoniq->src_mutex);
 684         snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 685         return 0;
 686 }
 687
 688 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 689 {
 690         unsigned int n, truncm, freq, result;
 691
 692         down(&ensoniq->src_mutex);
 693         n = rate / 3000;
 694         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 695                 n--;
 696         truncm = (21 * n - 1) | 1;
 697         freq = ((48000UL << 15) / rate) * n;
 698         result = (48000UL << 15) / (freq / n);
 699         if (rate >= 24000) {
 700                 if (truncm > 239)
 701                         truncm = 239;
 702                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 703                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 704         } else {
 705                 if (truncm > 119)
 706                         truncm = 119;
 707                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 708                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 709         }
 710         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 711                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
 712                                      ((freq >> 5) & 0xfc00));
 713         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 714         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 715         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 716         up(&ensoniq->src_mutex);
 717 }
 718
 719 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
 720 {
 721         unsigned int freq, r;
 722
 723         down(&ensoniq->src_mutex);
 724         freq = ((rate << 15) + 1500) / 3000;
 725         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
 726         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 727         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 728                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
 729                              ((freq >> 5) & 0xfc00));
 730         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 731         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
 732         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 733         up(&ensoniq->src_mutex);
 734 }
 735
 736 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
 737 {
 738         unsigned int freq, r;
 739
 740         down(&ensoniq->src_mutex);
 741         freq = ((rate << 15) + 1500) / 3000;
 742         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
 743         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 744         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 745                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
 746                              ((freq >> 5) & 0xfc00));
 747         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 748         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
 749         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 750         up(&ensoniq->src_mutex);
 751 }
 752
 753 #endif /* CHIP1371 */
 754
 755 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
 756 {
 757         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 758         switch (cmd) {
 759         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 760         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 761         {
 762                 unsigned int what = 0;
 763                 struct list_head *pos;
 764                 snd_pcm_substream_t *s;
 765                 snd_pcm_group_for_each(pos, substream) {
 766                         s = snd_pcm_group_substream_entry(pos);
 767                         if (s == ensoniq->playback1_substream) {
 768                                 what |= ES_P1_PAUSE;
 769                                 snd_pcm_trigger_done(s, substream);
 770                         } else if (s == ensoniq->playback2_substream) {
 771                                 what |= ES_P2_PAUSE;
 772                                 snd_pcm_trigger_done(s, substream);
 773                         } else if (s == ensoniq->capture_substream)
 774                                 return -EINVAL;
 775                 }
 776                 spin_lock(&ensoniq->reg_lock);
 777                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 778                         ensoniq->sctrl |= what;
 779                 else
 780                         ensoniq->sctrl &= ~what;
 781                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 782                 spin_unlock(&ensoniq->reg_lock);
 783                 break;
 784         }
 785         case SNDRV_PCM_TRIGGER_START:
 786         case SNDRV_PCM_TRIGGER_STOP:
 787         {
 788                 unsigned int what = 0;
 789                 struct list_head *pos;
 790                 snd_pcm_substream_t *s;
 791                 snd_pcm_group_for_each(pos, substream) {
 792                         s = snd_pcm_group_substream_entry(pos);
 793                         if (s == ensoniq->playback1_substream) {
 794                                 what |= ES_DAC1_EN;
 795                                 snd_pcm_trigger_done(s, substream);
 796                         } else if (s == ensoniq->playback2_substream) {
 797                                 what |= ES_DAC2_EN;
 798                                 snd_pcm_trigger_done(s, substream);
 799                         } else if (s == ensoniq->capture_substream) {
 800                                 what |= ES_ADC_EN;
 801                                 snd_pcm_trigger_done(s, substream);
 802                         }
 803                 }
 804                 spin_lock(&ensoniq->reg_lock);
 805                 if (cmd == SNDRV_PCM_TRIGGER_START)
 806                         ensoniq->ctrl |= what;
 807                 else
 808                         ensoniq->ctrl &= ~what;
 809                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 810                 spin_unlock(&ensoniq->reg_lock);
 811                 break;
 812         }
 813         default:
 814                 return -EINVAL;
 815         }
 816         return 0;
 817 }
 818
 819 /*
 820  *  PCM part
 821  */
 822
 823 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
 824                                  snd_pcm_hw_params_t * hw_params)
 825 {
 826         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 827 }
 828
 829 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
 830 {
 831         return snd_pcm_lib_free_pages(substream);
 832 }
 833
 834 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
 835 {
 836         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 837         snd_pcm_runtime_t *runtime = substream->runtime;
 838         unsigned int mode = 0;
 839
 840         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 841         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 842         if (snd_pcm_format_width(runtime->format) == 16)
 843                 mode |= 0x02;
 844         if (runtime->channels > 1)
 845                 mode |= 0x01;
 846         spin_lock_irq(&ensoniq->reg_lock);
 847         ensoniq->ctrl &= ~ES_DAC1_EN;
 848 #ifdef CHIP1371
 849         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 850         if (runtime->rate == 48000)
 851                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 852         else
 853                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 854 #endif
 855         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 856         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 857         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 858         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 859         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 860         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 861         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 862         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
 863 #ifdef CHIP1370
 864         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 865         switch (runtime->rate) {
 866         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 867         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 868         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 869         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 870         default: snd_BUG();
 871         }
 872 #endif
 873         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 874         spin_unlock_irq(&ensoniq->reg_lock);
 875 #ifndef CHIP1370
 876         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 877 #endif
 878         return 0;
 879 }
 880
 881 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
 882 {
 883         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 884         snd_pcm_runtime_t *runtime = substream->runtime;
 885         unsigned int mode = 0;
 886
 887         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 888         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 889         if (snd_pcm_format_width(runtime->format) == 16)
 890                 mode |= 0x02;
 891         if (runtime->channels > 1)
 892                 mode |= 0x01;
 893         spin_lock_irq(&ensoniq->reg_lock);
 894         ensoniq->ctrl &= ~ES_DAC2_EN;
 895         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 896         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 897         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 898         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 899         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 900                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 901         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 902                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 903         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 904         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
 905 #ifdef CHIP1370
 906         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 907                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 908                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 909                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 910         }
 911 #endif
 912         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 913         spin_unlock_irq(&ensoniq->reg_lock);
 914 #ifndef CHIP1370
 915         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 916 #endif
 917         return 0;
 918 }
 919
 920 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
 921 {
 922         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 923         snd_pcm_runtime_t *runtime = substream->runtime;
 924         unsigned int mode = 0;
 925
 926         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 927         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 928         if (snd_pcm_format_width(runtime->format) == 16)
 929                 mode |= 0x02;
 930         if (runtime->channels > 1)
 931                 mode |= 0x01;
 932         spin_lock_irq(&ensoniq->reg_lock);
 933         ensoniq->ctrl &= ~ES_ADC_EN;
 934         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 935         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 936         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 937         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 938         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 939         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 940         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 941         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
 942 #ifdef CHIP1370
 943         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 944                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 945                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 946                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 947         }
 948 #endif
 949         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 950         spin_unlock_irq(&ensoniq->reg_lock);
 951 #ifndef CHIP1370
 952         snd_es1371_adc_rate(ensoniq, runtime->rate);
 953 #endif
 954         return 0;
 955 }
 956
 957 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
 958 {
 959         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 960         size_t ptr;
 961
 962         spin_lock(&ensoniq->reg_lock);
 963         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 964                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 965                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 966                 ptr = bytes_to_frames(substream->runtime, ptr);
 967         } else {
 968                 ptr = 0;
 969         }
 970         spin_unlock(&ensoniq->reg_lock);
 971         return ptr;
 972 }
 973
 974 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
 975 {
 976         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 977         size_t ptr;
 978
 979         spin_lock(&ensoniq->reg_lock);
 980         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
 981                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 982                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
 983                 ptr = bytes_to_frames(substream->runtime, ptr);
 984         } else {
 985                 ptr = 0;
 986         }
 987         spin_unlock(&ensoniq->reg_lock);
 988         return ptr;
 989 }
 990
 991 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
 992 {
 993         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 994         size_t ptr;
 995
 996         spin_lock(&ensoniq->reg_lock);
 997         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
 998                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 999                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1000                 ptr = bytes_to_frames(substream->runtime, ptr);
1001         } else {
1002                 ptr = 0;
1003         }
1004         spin_unlock(&ensoniq->reg_lock);
1005         return ptr;
1006 }
1007
1008 static snd_pcm_hardware_t snd_ensoniq_playback1 =
1009 {
1010         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1011                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1012                                  SNDRV_PCM_INFO_MMAP_VALID |
1013                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1014         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1015         .rates =
1016 #ifndef CHIP1370
1017                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1018 #else
1019                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1020                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1021                                  SNDRV_PCM_RATE_44100),
1022 #endif
1023         .rate_min =             4000,
1024         .rate_max =             48000,
1025         .channels_min =         1,
1026         .channels_max =         2,
1027         .buffer_bytes_max =     (128*1024),
1028         .period_bytes_min =     64,
1029         .period_bytes_max =     (128*1024),
1030         .periods_min =          1,
1031         .periods_max =          1024,
1032         .fifo_size =            0,
1033 };
1034
1035 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1036 {
1037         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1038                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1039                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1040                                  SNDRV_PCM_INFO_SYNC_START),
1041         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1042         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1043         .rate_min =             4000,
1044         .rate_max =             48000,
1045         .channels_min =         1,
1046         .channels_max =         2,
1047         .buffer_bytes_max =     (128*1024),
1048         .period_bytes_min =     64,
1049         .period_bytes_max =     (128*1024),
1050         .periods_min =          1,
1051         .periods_max =          1024,
1052         .fifo_size =            0,
1053 };
1054
1055 static snd_pcm_hardware_t snd_ensoniq_capture =
1056 {
1057         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1058                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1059                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1060         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1061         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1062         .rate_min =             4000,
1063         .rate_max =             48000,
1064         .channels_min =         1,
1065         .channels_max =         2,
1066         .buffer_bytes_max =     (128*1024),
1067         .period_bytes_min =     64,
1068         .period_bytes_max =     (128*1024),
1069         .periods_min =          1,
1070         .periods_max =          1024,
1071         .fifo_size =            0,
1072 };
1073
1074 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1075 {
1076         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1077         snd_pcm_runtime_t *runtime = substream->runtime;
1078
1079         ensoniq->mode |= ES_MODE_PLAY1;
1080         ensoniq->playback1_substream = substream;
1081         runtime->hw = snd_ensoniq_playback1;
1082         snd_pcm_set_sync(substream);
1083         spin_lock_irq(&ensoniq->reg_lock);
1084         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1085                 ensoniq->spdif_stream = ensoniq->spdif_default;
1086         spin_unlock_irq(&ensoniq->reg_lock);
1087 #ifdef CHIP1370
1088         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1089                                    &snd_es1370_hw_constraints_rates);
1090 #else
1091         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1092                                       &snd_es1371_hw_constraints_dac_clock);
1093 #endif
1094         return 0;
1095 }
1096
1097 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1098 {
1099         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1100         snd_pcm_runtime_t *runtime = substream->runtime;
1101
1102         ensoniq->mode |= ES_MODE_PLAY2;
1103         ensoniq->playback2_substream = substream;
1104         runtime->hw = snd_ensoniq_playback2;
1105         snd_pcm_set_sync(substream);
1106         spin_lock_irq(&ensoniq->reg_lock);
1107         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1108                 ensoniq->spdif_stream = ensoniq->spdif_default;
1109         spin_unlock_irq(&ensoniq->reg_lock);
1110 #ifdef CHIP1370
1111         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1112                                       &snd_es1370_hw_constraints_clock);
1113 #else
1114         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1115                                       &snd_es1371_hw_constraints_dac_clock);
1116 #endif
1117         return 0;
1118 }
1119
1120 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1121 {
1122         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1123         snd_pcm_runtime_t *runtime = substream->runtime;
1124
1125         ensoniq->mode |= ES_MODE_CAPTURE;
1126         ensoniq->capture_substream = substream;
1127         runtime->hw = snd_ensoniq_capture;
1128         snd_pcm_set_sync(substream);
1129 #ifdef CHIP1370
1130         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1131                                       &snd_es1370_hw_constraints_clock);
1132 #else
1133         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1134                                       &snd_es1371_hw_constraints_adc_clock);
1135 #endif
1136         return 0;
1137 }
1138
1139 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1140 {
1141         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1142
1143         ensoniq->playback1_substream = NULL;
1144         ensoniq->mode &= ~ES_MODE_PLAY1;
1145         return 0;
1146 }
1147
1148 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1149 {
1150         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1151
1152         ensoniq->playback2_substream = NULL;
1153         spin_lock_irq(&ensoniq->reg_lock);
1154 #ifdef CHIP1370
1155         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1156 #endif
1157         ensoniq->mode &= ~ES_MODE_PLAY2;
1158         spin_unlock_irq(&ensoniq->reg_lock);
1159         return 0;
1160 }
1161
1162 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1163 {
1164         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1165
1166         ensoniq->capture_substream = NULL;
1167         spin_lock_irq(&ensoniq->reg_lock);
1168 #ifdef CHIP1370
1169         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1170 #endif
1171         ensoniq->mode &= ~ES_MODE_CAPTURE;
1172         spin_unlock_irq(&ensoniq->reg_lock);
1173         return 0;
1174 }
1175
1176 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1177         .open =         snd_ensoniq_playback1_open,
1178         .close =        snd_ensoniq_playback1_close,
1179         .ioctl =        snd_pcm_lib_ioctl,
1180         .hw_params =    snd_ensoniq_hw_params,
1181         .hw_free =      snd_ensoniq_hw_free,
1182         .prepare =      snd_ensoniq_playback1_prepare,
1183         .trigger =      snd_ensoniq_trigger,
1184         .pointer =      snd_ensoniq_playback1_pointer,
1185 };
1186
1187 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1188         .open =         snd_ensoniq_playback2_open,
1189         .close =        snd_ensoniq_playback2_close,
1190         .ioctl =        snd_pcm_lib_ioctl,
1191         .hw_params =    snd_ensoniq_hw_params,
1192         .hw_free =      snd_ensoniq_hw_free,
1193         .prepare =      snd_ensoniq_playback2_prepare,
1194         .trigger =      snd_ensoniq_trigger,
1195         .pointer =      snd_ensoniq_playback2_pointer,
1196 };
1197
1198 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1199         .open =         snd_ensoniq_capture_open,
1200         .close =        snd_ensoniq_capture_close,
1201         .ioctl =        snd_pcm_lib_ioctl,
1202         .hw_params =    snd_ensoniq_hw_params,
1203         .hw_free =      snd_ensoniq_hw_free,
1204         .prepare =      snd_ensoniq_capture_prepare,
1205         .trigger =      snd_ensoniq_trigger,
1206         .pointer =      snd_ensoniq_capture_pointer,
1207 };
1208
1209 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1210 {
1211         ensoniq_t *ensoniq = pcm->private_data;
1212         ensoniq->pcm1 = NULL;
1213         snd_pcm_lib_preallocate_free_for_all(pcm);
1214 }
1215
1216 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1217 {
1218         snd_pcm_t *pcm;
1219         int err;
1220
1221         if (rpcm)
1222                 *rpcm = NULL;
1223 #ifdef CHIP1370
1224         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1225 #else
1226         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1227 #endif
1228         if (err < 0)
1229                 return err;
1230
1231 #ifdef CHIP1370
1232         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1233 #else
1234         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1235 #endif
1236         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1237
1238         pcm->private_data = ensoniq;
1239         pcm->private_free = snd_ensoniq_pcm_free;
1240         pcm->info_flags = 0;
1241 #ifdef CHIP1370
1242         strcpy(pcm->name, "ES1370 DAC2/ADC");
1243 #else
1244         strcpy(pcm->name, "ES1371 DAC2/ADC");
1245 #endif
1246         ensoniq->pcm1 = pcm;
1247
1248         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1249                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1250
1251         if (rpcm)
1252                 *rpcm = pcm;
1253         return 0;
1254 }
1255
1256 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1257 {
1258         ensoniq_t *ensoniq = pcm->private_data;
1259         ensoniq->pcm2 = NULL;
1260         snd_pcm_lib_preallocate_free_for_all(pcm);
1261 }
1262
1263 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1264 {
1265         snd_pcm_t *pcm;
1266         int err;
1267
1268         if (rpcm)
1269                 *rpcm = NULL;
1270 #ifdef CHIP1370
1271         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1272 #else
1273         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1274 #endif
1275         if (err < 0)
1276                 return err;
1277
1278 #ifdef CHIP1370
1279         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1280 #else
1281         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1282 #endif
1283         pcm->private_data = ensoniq;
1284         pcm->private_free = snd_ensoniq_pcm_free2;
1285         pcm->info_flags = 0;
1286 #ifdef CHIP1370
1287         strcpy(pcm->name, "ES1370 DAC1");
1288 #else
1289         strcpy(pcm->name, "ES1371 DAC1");
1290 #endif
1291         ensoniq->pcm2 = pcm;
1292
1293         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1294                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1295
1296         if (rpcm)
1297                 *rpcm = pcm;
1298         return 0;
1299 }
1300
1301 /*
1302  *  Mixer section
1303  */
1304
1305 /*
1306  * ENS1371 mixer (including SPDIF interface)
1307  */
1308 #ifdef CHIP1371
1309 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1310 {
1311         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1312         uinfo->count = 1;
1313         return 0;
1314 }
1315
1316 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1317                                          snd_ctl_elem_value_t * ucontrol)
1318 {
1319         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1320         spin_lock_irq(&ensoniq->reg_lock);
1321         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1322         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1323         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1324         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1325         spin_unlock_irq(&ensoniq->reg_lock);
1326         return 0;
1327 }
1328
1329 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1330                                          snd_ctl_elem_value_t * ucontrol)
1331 {
1332         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1333         unsigned int val;
1334         int change;
1335
1336         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1337               ((u32)ucontrol->value.iec958.status[1] << 8) |
1338               ((u32)ucontrol->value.iec958.status[2] << 16) |
1339               ((u32)ucontrol->value.iec958.status[3] << 24);
1340         spin_lock_irq(&ensoniq->reg_lock);
1341         change = ensoniq->spdif_default != val;
1342         ensoniq->spdif_default = val;
1343         if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1344                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1345         spin_unlock_irq(&ensoniq->reg_lock);
1346         return change;
1347 }
1348
1349 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1350                                          snd_ctl_elem_value_t * ucontrol)
1351 {
1352         ucontrol->value.iec958.status[0] = 0xff;
1353         ucontrol->value.iec958.status[1] = 0xff;
1354         ucontrol->value.iec958.status[2] = 0xff;
1355         ucontrol->value.iec958.status[3] = 0xff;
1356         return 0;
1357 }
1358
1359 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1360                                          snd_ctl_elem_value_t * ucontrol)
1361 {
1362         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1363         spin_lock_irq(&ensoniq->reg_lock);
1364         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1365         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1366         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1367         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1368         spin_unlock_irq(&ensoniq->reg_lock);
1369         return 0;
1370 }
1371
1372 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1373                                         snd_ctl_elem_value_t * ucontrol)
1374 {
1375         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1376         unsigned int val;
1377         int change;
1378
1379         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1380               ((u32)ucontrol->value.iec958.status[1] << 8) |
1381               ((u32)ucontrol->value.iec958.status[2] << 16) |
1382               ((u32)ucontrol->value.iec958.status[3] << 24);
1383         spin_lock_irq(&ensoniq->reg_lock);
1384         change = ensoniq->spdif_stream != val;
1385         ensoniq->spdif_stream = val;
1386         if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1387                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1388         spin_unlock_irq(&ensoniq->reg_lock);
1389         return change;
1390 }
1391
1392 #define ES1371_SPDIF(xname) \
1393 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1394   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1395
1396 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1397 {
1398         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1399         uinfo->count = 1;
1400         uinfo->value.integer.min = 0;
1401         uinfo->value.integer.max = 1;
1402         return 0;
1403 }
1404
1405 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1406 {
1407         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1408
1409         spin_lock_irq(&ensoniq->reg_lock);
1410         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1411         spin_unlock_irq(&ensoniq->reg_lock);
1412         return 0;
1413 }
1414
1415 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1416 {
1417         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1418         unsigned int nval1, nval2;
1419         int change;
1420
1421         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1422         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1423         spin_lock_irq(&ensoniq->reg_lock);
1424         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1425         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1426         ensoniq->ctrl |= nval1;
1427         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1428         ensoniq->cssr |= nval2;
1429         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1430         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1431         spin_unlock_irq(&ensoniq->reg_lock);
1432         return change;
1433 }
1434
1435
1436 /* spdif controls */
1437 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1438         ES1371_SPDIF("IEC958 Playback Switch"),
1439         {
1440                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1441                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1442                 .info =         snd_ens1373_spdif_info,
1443                 .get =          snd_ens1373_spdif_default_get,
1444                 .put =          snd_ens1373_spdif_default_put,
1445         },
1446         {
1447                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1448                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1449                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1450                 .info =         snd_ens1373_spdif_info,
1451                 .get =          snd_ens1373_spdif_mask_get
1452         },
1453         {
1454                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1455                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1456                 .info =         snd_ens1373_spdif_info,
1457                 .get =          snd_ens1373_spdif_stream_get,
1458                 .put =          snd_ens1373_spdif_stream_put
1459         },
1460 };
1461
1462
1463 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1464 {
1465         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1466         uinfo->count = 1;
1467         uinfo->value.integer.min = 0;
1468         uinfo->value.integer.max = 1;
1469         return 0;
1470 }
1471
1472 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1473 {
1474         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1475         int val = 0;
1476
1477         spin_lock_irq(&ensoniq->reg_lock);
1478         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1479                 val = 1;
1480         ucontrol->value.integer.value[0] = val;
1481         spin_unlock_irq(&ensoniq->reg_lock);
1482         return 0;
1483 }
1484
1485 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1486 {
1487         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1488         unsigned int nval1;
1489         int change;
1490
1491         nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1492         spin_lock_irq(&ensoniq->reg_lock);
1493         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1494         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1495         ensoniq->cssr |= nval1;
1496         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1497         spin_unlock_irq(&ensoniq->reg_lock);
1498         return change;
1499 }
1500
1501 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1502 {
1503         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1504         .name =         "AC97 2ch->4ch Copy Switch",
1505         .info =         snd_es1373_rear_info,
1506         .get =          snd_es1373_rear_get,
1507         .put =          snd_es1373_rear_put,
1508 };
1509
1510 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1511 {
1512         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1513         uinfo->count = 1;
1514         uinfo->value.integer.min = 0;
1515         uinfo->value.integer.max = 1;
1516         return 0;
1517 }
1518
1519 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1520 {
1521         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1522         int val = 0;
1523
1524         spin_lock_irq(&ensoniq->reg_lock);
1525         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1526                 val = 1;
1527         ucontrol->value.integer.value[0] = val;
1528         spin_unlock_irq(&ensoniq->reg_lock);
1529         return 0;
1530 }
1531
1532 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1533 {
1534         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1535         int changed;
1536         unsigned int ctrl;
1537
1538         spin_lock_irq(&ensoniq->reg_lock);
1539         ctrl = ensoniq->ctrl;
1540         if (ucontrol->value.integer.value[0])
1541                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1542         else
1543                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1544         changed = (ctrl != ensoniq->ctrl);
1545         if (changed)
1546                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1547         spin_unlock_irq(&ensoniq->reg_lock);
1548         return changed;
1549 }
1550
1551 static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1552 {
1553         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1554         .name =         "Line In->Rear Out Switch",
1555         .info =         snd_es1373_line_info,
1556         .get =          snd_es1373_line_get,
1557         .put =          snd_es1373_line_put,
1558 };
1559
1560 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1561 {
1562         ensoniq_t *ensoniq = ac97->private_data;
1563         ensoniq->u.es1371.ac97 = NULL;
1564 }
1565
1566 static struct {
1567         unsigned short vid;             /* vendor ID */
1568         unsigned short did;             /* device ID */
1569         unsigned char rev;              /* revision */
1570 } es1371_spdif_present[] __devinitdata = {
1571         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1572         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1573         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1574         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1575         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1576         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1577 };
1578
1579 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1580 {
1581         snd_card_t *card = ensoniq->card;
1582         ac97_bus_t *pbus;
1583         ac97_template_t ac97;
1584         int err, idx;
1585         static ac97_bus_ops_t ops = {
1586                 .write = snd_es1371_codec_write,
1587                 .read = snd_es1371_codec_read,
1588         };
1589
1590         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1591                 return err;
1592
1593         memset(&ac97, 0, sizeof(ac97));
1594         ac97.private_data = ensoniq;
1595         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1596         ac97.scaps = AC97_SCAP_AUDIO;
1597         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1598                 return err;
1599         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1600                 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1601                     ensoniq->pci->device == es1371_spdif_present[idx].did &&
1602                     ensoniq->rev == es1371_spdif_present[idx].rev) {
1603                         snd_kcontrol_t *kctl;
1604                         int i, index = 0;
1605
1606                         ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1607                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1608
1609                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1610                                 index++;
1611
1612                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1613                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1614                                 if (! kctl)
1615                                         return -ENOMEM;
1616                                 kctl->id.index = index;
1617                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1618                                         return err;
1619                         }
1620                         break;
1621                 }
1622         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1623                 /* mirror rear to front speakers */
1624                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1625                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1626                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1627                 if (err < 0)
1628                         return err;
1629         }
1630         if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1631             (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1632             ((ensoniq->subsystem_vendor_id == 0x1458) &&
1633             (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1634                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1635                  if (err < 0)
1636                          return err;
1637         }
1638
1639         return 0;
1640 }
1641
1642 #endif /* CHIP1371 */
1643
1644 /* generic control callbacks for ens1370 */
1645 #ifdef CHIP1370
1646 #define ENSONIQ_CONTROL(xname, mask) \
1647 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1648   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1649   .private_value = mask }
1650
1651 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1652 {
1653         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1654         uinfo->count = 1;
1655         uinfo->value.integer.min = 0;
1656         uinfo->value.integer.max = 1;
1657         return 0;
1658 }
1659
1660 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1661 {
1662         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1663         int mask = kcontrol->private_value;
1664
1665         spin_lock_irq(&ensoniq->reg_lock);
1666         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1667         spin_unlock_irq(&ensoniq->reg_lock);
1668         return 0;
1669 }
1670
1671 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1672 {
1673         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1674         int mask = kcontrol->private_value;
1675         unsigned int nval;
1676         int change;
1677
1678         nval = ucontrol->value.integer.value[0] ? mask : 0;
1679         spin_lock_irq(&ensoniq->reg_lock);
1680         change = (ensoniq->ctrl & mask) != nval;
1681         ensoniq->ctrl &= ~mask;
1682         ensoniq->ctrl |= nval;
1683         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1684         spin_unlock_irq(&ensoniq->reg_lock);
1685         return change;
1686 }
1687
1688 /*
1689  * ENS1370 mixer
1690  */
1691
1692 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1693 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1694 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1695 };
1696
1697 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1698
1699 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1700 {
1701         ensoniq_t *ensoniq = ak4531->private_data;
1702         ensoniq->u.es1370.ak4531 = NULL;
1703 }
1704
1705 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1706 {
1707         snd_card_t *card = ensoniq->card;
1708         ak4531_t ak4531;
1709         unsigned int idx;
1710         int err;
1711
1712         /* try reset AK4531 */
1713         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1714         inw(ES_REG(ensoniq, 1370_CODEC));
1715         udelay(100);
1716         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1717         inw(ES_REG(ensoniq, 1370_CODEC));
1718         udelay(100);
1719
1720         memset(&ak4531, 0, sizeof(ak4531));
1721         ak4531.write = snd_es1370_codec_write;
1722         ak4531.private_data = ensoniq;
1723         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1724         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1725                 return err;
1726         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1727                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1728                 if (err < 0)
1729                         return err;
1730         }
1731         return 0;
1732 }
1733
1734 #endif /* CHIP1370 */
1735
1736 #ifdef SUPPORT_JOYSTICK
1737
1738 #ifdef CHIP1371
1739 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1740 {
1741         switch (joystick_port[dev]) {
1742         case 0: /* disabled */
1743         case 1: /* auto-detect */
1744         case 0x200:
1745         case 0x208:
1746         case 0x210:
1747         case 0x218:
1748                 return joystick_port[dev];
1749
1750         default:
1751                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1752                 return 0;
1753         }
1754 }
1755 #else
1756 static inline int snd_ensoniq_get_joystick_port(int dev)
1757 {
1758         return joystick[dev] ? 0x200 : 0;
1759 }
1760 #endif
1761
1762 static int __devinit snd_ensoniq_create_gameport(ensoniq_t *ensoniq, int dev)
1763 {
1764         struct gameport *gp;
1765         int io_port;
1766
1767         io_port = snd_ensoniq_get_joystick_port(dev);
1768
1769         switch (io_port) {
1770         case 0:
1771                 return -ENOSYS;
1772
1773         case 1: /* auto_detect */
1774                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1775                         if (request_region(io_port, 8, "ens137x: gameport"))
1776                                 break;
1777                 if (io_port > 0x218) {
1778                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1779                         return -EBUSY;
1780                 }
1781                 break;
1782
1783         default:
1784                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1785                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", io_port);
1786                         return -EBUSY;
1787                 }
1788                 break;
1789         }
1790
1791         ensoniq->gameport = gp = gameport_allocate_port();
1792         if (!gp) {
1793                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1794                 release_region(io_port, 8);
1795                 return -ENOMEM;
1796         }
1797
1798         gameport_set_name(gp, "ES137x");
1799         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1800         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1801         gp->io = io_port;
1802
1803         ensoniq->ctrl |= ES_JYSTK_EN;
1804 #ifdef CHIP1371
1805         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1806         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1807 #endif
1808         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1809
1810         gameport_register_port(ensoniq->gameport);
1811
1812         return 0;
1813 }
1814
1815 static void snd_ensoniq_free_gameport(ensoniq_t *ensoniq)
1816 {
1817         if (ensoniq->gameport) {
1818                 int port = ensoniq->gameport->io;
1819
1820                 gameport_unregister_port(ensoniq->gameport);
1821                 ensoniq->gameport = NULL;
1822                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1823                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1824                 release_region(port, 8);
1825         }
1826 }
1827 #else
1828 static inline int snd_ensoniq_create_gameport(ensoniq_t *ensoniq, long port) { return -ENOSYS; }
1829 static inline void snd_ensoniq_free_gameport(ensoniq_t *ensoniq) { }
1830 #endif /* SUPPORT_JOYSTICK */
1831
1832 /*
1833
1834  */
1835
1836 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1837                                   snd_info_buffer_t * buffer)
1838 {
1839         ensoniq_t *ensoniq = entry->private_data;
1840
1841 #ifdef CHIP1370
1842         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1843 #else
1844         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1845 #endif
1846         snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1847 #ifdef CHIP1370
1848         snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1849         snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1850 #else
1851         snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1852 #endif
1853 }
1854
1855 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1856 {
1857         snd_info_entry_t *entry;
1858
1859         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1860                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1861 }
1862
1863 /*
1864
1865  */
1866
1867 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1868 {
1869         snd_ensoniq_free_gameport(ensoniq);
1870         if (ensoniq->irq < 0)
1871                 goto __hw_end;
1872 #ifdef CHIP1370
1873         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1874         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1875 #else
1876         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1877         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1878 #endif
1879         synchronize_irq(ensoniq->irq);
1880         pci_set_power_state(ensoniq->pci, 3);
1881       __hw_end:
1882 #ifdef CHIP1370
1883         if (ensoniq->dma_bug.area)
1884                 snd_dma_free_pages(&ensoniq->dma_bug);
1885 #endif
1886         if (ensoniq->irq >= 0)
1887                 free_irq(ensoniq->irq, (void *)ensoniq);
1888         pci_release_regions(ensoniq->pci);
1889         pci_disable_device(ensoniq->pci);
1890         kfree(ensoniq);
1891         return 0;
1892 }
1893
1894 static int snd_ensoniq_dev_free(snd_device_t *device)
1895 {
1896         ensoniq_t *ensoniq = device->device_data;
1897         return snd_ensoniq_free(ensoniq);
1898 }
1899
1900 #ifdef CHIP1371
1901 static struct {
1902         unsigned short svid;            /* subsystem vendor ID */
1903         unsigned short sdid;            /* subsystem device ID */
1904 } es1371_amplifier_hack[] = {
1905         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1906         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1907         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1908         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1909         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1910 };
1911 static struct {
1912         unsigned short vid;             /* vendor ID */
1913         unsigned short did;             /* device ID */
1914         unsigned char rev;              /* revision */
1915 } es1371_ac97_reset_hack[] = {
1916         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1917         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1918         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1919         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1920         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1921         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1922 };
1923 #endif
1924
1925 static int __devinit snd_ensoniq_create(snd_card_t * card,
1926                                      struct pci_dev *pci,
1927                                      ensoniq_t ** rensoniq)
1928 {
1929         ensoniq_t *ensoniq;
1930         unsigned short cmdw;
1931         unsigned char cmdb;
1932 #ifdef CHIP1371
1933         int idx;
1934 #endif
1935         int err;
1936         static snd_device_ops_t ops = {
1937                 .dev_free =     snd_ensoniq_dev_free,
1938         };
1939
1940         *rensoniq = NULL;
1941         if ((err = pci_enable_device(pci)) < 0)
1942                 return err;
1943         ensoniq = kcalloc(1, sizeof(*ensoniq), GFP_KERNEL);
1944         if (ensoniq == NULL) {
1945                 pci_disable_device(pci);
1946                 return -ENOMEM;
1947         }
1948         spin_lock_init(&ensoniq->reg_lock);
1949         init_MUTEX(&ensoniq->src_mutex);
1950         ensoniq->card = card;
1951         ensoniq->pci = pci;
1952         ensoniq->irq = -1;
1953         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
1954                 kfree(ensoniq);
1955                 pci_disable_device(pci);
1956                 return err;
1957         }
1958         ensoniq->port = pci_resource_start(pci, 0);
1959         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1960                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1961                 snd_ensoniq_free(ensoniq);
1962                 return -EBUSY;
1963         }
1964         ensoniq->irq = pci->irq;
1965 #ifdef CHIP1370
1966         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1967                                 16, &ensoniq->dma_bug) < 0) {
1968                 snd_printk("unable to allocate space for phantom area - dma_bug\n");
1969                 snd_ensoniq_free(ensoniq);
1970                 return -EBUSY;
1971         }
1972 #endif
1973         pci_set_master(pci);
1974         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1975         ensoniq->rev = cmdb;
1976         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1977         ensoniq->subsystem_vendor_id = cmdw;
1978         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1979         ensoniq->subsystem_device_id = cmdw;
1980 #ifdef CHIP1370
1981 #if 0
1982         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1983 #else   /* get microphone working */
1984         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1985 #endif
1986         ensoniq->sctrl = 0;
1987         /* initialize the chips */
1988         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1989         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1990         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1991         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1992         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1993 #else
1994         ensoniq->ctrl = 0;
1995         ensoniq->sctrl = 0;
1996         ensoniq->cssr = 0;
1997         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
1998                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
1999                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2000                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2001                         break;
2002                 }
2003         /* initialize the chips */
2004         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2005         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2006         outl(0, ES_REG(ensoniq, 1371_LEGACY));
2007         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2008                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2009                     pci->device == es1371_ac97_reset_hack[idx].did &&
2010                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2011                         unsigned long tmo;
2012                         signed long tmo2;
2013
2014                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
2015                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2016                         /* need to delay around 20ms(bleech) to give
2017                         some CODECs enough time to wakeup */
2018                         tmo = jiffies + (HZ / 50) + 1;
2019                         while (1) {
2020                                 tmo2 = tmo - jiffies;
2021                                 if (tmo2 <= 0)
2022                                         break;
2023                                 set_current_state(TASK_UNINTERRUPTIBLE);
2024                                 schedule_timeout(tmo2);
2025                         }
2026                         break;
2027                 }
2028         /* AC'97 warm reset to start the bitclk */
2029         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2030         inl(ES_REG(ensoniq, CONTROL));
2031         udelay(20);
2032         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2033         /* Init the sample rate converter */
2034         snd_es1371_wait_src_ready(ensoniq);
2035         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2036         for (idx = 0; idx < 0x80; idx++)
2037                 snd_es1371_src_write(ensoniq, idx, 0);
2038         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2039         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2040         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2041         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2042         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2043         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2044         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2045         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2046         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2047         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2048         snd_es1371_adc_rate(ensoniq, 22050);
2049         snd_es1371_dac1_rate(ensoniq, 22050);
2050         snd_es1371_dac2_rate(ensoniq, 22050);
2051         /* WARNING:
2052          * enabling the sample rate converter without properly programming
2053          * its parameters causes the chip to lock up (the SRC busy bit will
2054          * be stuck high, and I've found no way to rectify this other than
2055          * power cycle) - Thomas Sailer
2056          */
2057         snd_es1371_wait_src_ready(ensoniq);
2058         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2059         /* try reset codec directly */
2060         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2061 #endif
2062         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2063         outb(0x00, ES_REG(ensoniq, UART_RES));
2064         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2065         synchronize_irq(ensoniq->irq);
2066
2067         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2068                 snd_ensoniq_free(ensoniq);
2069                 return err;
2070         }
2071
2072         snd_ensoniq_proc_init(ensoniq);
2073
2074         snd_card_set_dev(card, &pci->dev);
2075
2076         *rensoniq = ensoniq;
2077         return 0;
2078 }
2079
2080 /*
2081  *  MIDI section
2082  */
2083
2084 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2085 {
2086         snd_rawmidi_t * rmidi = ensoniq->rmidi;
2087         unsigned char status, mask, byte;
2088
2089         if (rmidi == NULL)
2090                 return;
2091         /* do Rx at first */
2092         spin_lock(&ensoniq->reg_lock);
2093         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2094         while (mask) {
2095                 status = inb(ES_REG(ensoniq, UART_STATUS));
2096                 if ((status & mask) == 0)
2097                         break;
2098                 byte = inb(ES_REG(ensoniq, UART_DATA));
2099                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2100         }
2101         spin_unlock(&ensoniq->reg_lock);
2102
2103         /* do Tx at second */
2104         spin_lock(&ensoniq->reg_lock);
2105         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2106         while (mask) {
2107                 status = inb(ES_REG(ensoniq, UART_STATUS));
2108                 if ((status & mask) == 0)
2109                         break;
2110                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2111                         ensoniq->uartc &= ~ES_TXINTENM;
2112                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2113                         mask &= ~ES_TXRDY;
2114                 } else {
2115                         outb(byte, ES_REG(ensoniq, UART_DATA));
2116                 }
2117         }
2118         spin_unlock(&ensoniq->reg_lock);
2119 }
2120
2121 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2122 {
2123         ensoniq_t *ensoniq = substream->rmidi->private_data;
2124
2125         spin_lock_irq(&ensoniq->reg_lock);
2126         ensoniq->uartm |= ES_MODE_INPUT;
2127         ensoniq->midi_input = substream;
2128         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2129                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2130                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2131                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2132         }
2133         spin_unlock_irq(&ensoniq->reg_lock);
2134         return 0;
2135 }
2136
2137 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2138 {
2139         ensoniq_t *ensoniq = substream->rmidi->private_data;
2140
2141         spin_lock_irq(&ensoniq->reg_lock);
2142         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2143                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2144                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2145         } else {
2146                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2147         }
2148         ensoniq->midi_input = NULL;
2149         ensoniq->uartm &= ~ES_MODE_INPUT;
2150         spin_unlock_irq(&ensoniq->reg_lock);
2151         return 0;
2152 }
2153
2154 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2155 {
2156         ensoniq_t *ensoniq = substream->rmidi->private_data;
2157
2158         spin_lock_irq(&ensoniq->reg_lock);
2159         ensoniq->uartm |= ES_MODE_OUTPUT;
2160         ensoniq->midi_output = substream;
2161         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2162                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2163                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2164                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2165         }
2166         spin_unlock_irq(&ensoniq->reg_lock);
2167         return 0;
2168 }
2169
2170 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2171 {
2172         ensoniq_t *ensoniq = substream->rmidi->private_data;
2173
2174         spin_lock_irq(&ensoniq->reg_lock);
2175         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2176                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2177                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2178         } else {
2179                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2180         }
2181         ensoniq->midi_output = NULL;
2182         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2183         spin_unlock_irq(&ensoniq->reg_lock);
2184         return 0;
2185 }
2186
2187 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2188 {
2189         unsigned long flags;
2190         ensoniq_t *ensoniq = substream->rmidi->private_data;
2191         int idx;
2192
2193         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2194         if (up) {
2195                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2196                         /* empty input FIFO */
2197                         for (idx = 0; idx < 32; idx++)
2198                                 inb(ES_REG(ensoniq, UART_DATA));
2199                         ensoniq->uartc |= ES_RXINTEN;
2200                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2201                 }
2202         } else {
2203                 if (ensoniq->uartc & ES_RXINTEN) {
2204                         ensoniq->uartc &= ~ES_RXINTEN;
2205                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2206                 }
2207         }
2208         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2209 }
2210
2211 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2212 {
2213         unsigned long flags;
2214         ensoniq_t *ensoniq = substream->rmidi->private_data;
2215         unsigned char byte;
2216
2217         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2218         if (up) {
2219                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2220                         ensoniq->uartc |= ES_TXINTENO(1);
2221                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2222                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2223                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2224                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2225                                         ensoniq->uartc &= ~ES_TXINTENM;
2226                                 } else {
2227                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2228                                 }
2229                         }
2230                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2231                 }
2232         } else {
2233                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2234                         ensoniq->uartc &= ~ES_TXINTENM;
2235                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2236                 }
2237         }
2238         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2239 }
2240
2241 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2242 {
2243         .open =         snd_ensoniq_midi_output_open,
2244         .close =        snd_ensoniq_midi_output_close,
2245         .trigger =      snd_ensoniq_midi_output_trigger,
2246 };
2247
2248 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2249 {
2250         .open =         snd_ensoniq_midi_input_open,
2251         .close =        snd_ensoniq_midi_input_close,
2252         .trigger =      snd_ensoniq_midi_input_trigger,
2253 };
2254
2255 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2256 {
2257         snd_rawmidi_t *rmidi;
2258         int err;
2259
2260         if (rrawmidi)
2261                 *rrawmidi = NULL;
2262         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2263                 return err;
2264 #ifdef CHIP1370
2265         strcpy(rmidi->name, "ES1370");
2266 #else
2267         strcpy(rmidi->name, "ES1371");
2268 #endif
2269         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2270         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2271         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2272         rmidi->private_data = ensoniq;
2273         ensoniq->rmidi = rmidi;
2274         if (rrawmidi)
2275                 *rrawmidi = rmidi;
2276         return 0;
2277 }
2278
2279 /*
2280  *  Interrupt handler
2281  */
2282
2283 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2284 {
2285         ensoniq_t *ensoniq = dev_id;
2286         unsigned int status, sctrl;
2287
2288         if (ensoniq == NULL)
2289                 return IRQ_NONE;
2290
2291         status = inl(ES_REG(ensoniq, STATUS));
2292         if (!(status & ES_INTR))
2293                 return IRQ_NONE;
2294
2295         spin_lock(&ensoniq->reg_lock);
2296         sctrl = ensoniq->sctrl;
2297         if (status & ES_DAC1)
2298                 sctrl &= ~ES_P1_INT_EN;
2299         if (status & ES_DAC2)
2300                 sctrl &= ~ES_P2_INT_EN;
2301         if (status & ES_ADC)
2302                 sctrl &= ~ES_R1_INT_EN;
2303         outl(sctrl, ES_REG(ensoniq, SERIAL));
2304         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2305         spin_unlock(&ensoniq->reg_lock);
2306
2307         if (status & ES_UART)
2308                 snd_ensoniq_midi_interrupt(ensoniq);
2309         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2310                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2311         if ((status & ES_ADC) && ensoniq->capture_substream)
2312                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2313         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2314                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2315         return IRQ_HANDLED;
2316 }
2317
2318 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2319                                         const struct pci_device_id *pci_id)
2320 {
2321         static int dev;
2322         snd_card_t *card;
2323         ensoniq_t *ensoniq;
2324         int err, pcm_devs[2];
2325
2326         if (dev >= SNDRV_CARDS)
2327                 return -ENODEV;
2328         if (!enable[dev]) {
2329                 dev++;
2330                 return -ENOENT;
2331         }
2332
2333         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2334         if (card == NULL)
2335                 return -ENOMEM;
2336
2337         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2338                 snd_card_free(card);
2339                 return err;
2340         }
2341
2342         pcm_devs[0] = 0; pcm_devs[1] = 1;
2343 #ifdef CHIP1370
2344         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2345                 snd_card_free(card);
2346                 return err;
2347         }
2348 #endif
2349 #ifdef CHIP1371
2350         if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2351                 snd_card_free(card);
2352                 return err;
2353         }
2354 #endif
2355         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2356                 snd_card_free(card);
2357                 return err;
2358         }
2359         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2360                 snd_card_free(card);
2361                 return err;
2362         }
2363         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2364                 snd_card_free(card);
2365                 return err;
2366         }
2367
2368         snd_ensoniq_create_gameport(ensoniq, dev);
2369
2370         strcpy(card->driver, DRIVER_NAME);
2371
2372         strcpy(card->shortname, "Ensoniq AudioPCI");
2373         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2374                 card->shortname,
2375                 card->driver,
2376                 ensoniq->port,
2377                 ensoniq->irq);
2378
2379         if ((err = snd_card_register(card)) < 0) {
2380                 snd_card_free(card);
2381                 return err;
2382         }
2383
2384         pci_set_drvdata(pci, card);
2385         dev++;
2386         return 0;
2387 }
2388
2389 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2390 {
2391         snd_card_free(pci_get_drvdata(pci));
2392         pci_set_drvdata(pci, NULL);
2393 }
2394
2395 static struct pci_driver driver = {
2396         .name = DRIVER_NAME,
2397         .id_table = snd_audiopci_ids,
2398         .probe = snd_audiopci_probe,
2399         .remove = __devexit_p(snd_audiopci_remove),
2400 };
2401
2402 static int __init alsa_card_ens137x_init(void)
2403 {
2404         return pci_module_init(&driver);
2405 }
2406
2407 static void __exit alsa_card_ens137x_exit(void)
2408 {
2409         pci_unregister_driver(&driver);
2410 }
2411
2412 module_init(alsa_card_ens137x_init)
2413 module_exit(alsa_card_ens137x_exit)