2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SHUBIO_H
10 #define _ASM_IA64_SN_SHUBIO_H
12 #define HUB_WIDGET_ID_MAX 0xf
13 #define IIO_NUM_ITTES 7
14 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
16 #define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
17 /* This register is also accessible from
18 * Crosstalk at address 0x0. */
19 #define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
20 #define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
21 #define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
22 #define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
23 #define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
24 #define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
25 #define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
26 #define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
27 #define IIO_ILLR 0x00400130 /* IO LLP Log Register */
28 #define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
30 #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
31 #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
33 #define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
34 #define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
36 #define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
37 #define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
38 #define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
39 #define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
40 #define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
41 #define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
42 #define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
44 #define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
45 #define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
46 #define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
47 #define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
48 #define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
49 #define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
50 #define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
51 #define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
52 #define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
54 #define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
55 #define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
56 #define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
57 #define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
58 #define IIO_IBCR 0x00400200 /* IO BTE Control Register */
60 #define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
61 #define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
63 #define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
65 #define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
66 #define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
69 #define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
70 #define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
72 #define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
73 #define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
74 #define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
75 #define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
76 #define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
78 #define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
80 #define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
81 #define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
82 #define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
83 #define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
84 #define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
85 #define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
86 #define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
87 #define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
89 #define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
90 #define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
91 #define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
92 #define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
93 #define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
94 #define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
95 #define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
96 #define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
98 #define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
99 #define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
100 #define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
101 #define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
102 #define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
103 #define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
104 #define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
105 #define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
107 #define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
108 #define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
109 #define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
110 #define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
111 #define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
113 #define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
114 #define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
115 #define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
116 #define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
117 #define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
119 #define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
120 #define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
121 #define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
122 #define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
123 #define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
125 #define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
126 #define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
127 #define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
128 #define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
129 #define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
131 #define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
132 #define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
133 #define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
134 #define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
135 #define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
137 #define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
138 #define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
139 #define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
140 #define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
141 #define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
143 #define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
144 #define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
145 #define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
146 #define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
147 #define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
149 #define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
150 #define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
151 #define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
152 #define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
153 #define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
155 #define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
156 #define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
157 #define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
158 #define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
159 #define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
161 #define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
162 #define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
163 #define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
164 #define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
165 #define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
167 #define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
168 #define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
169 #define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
170 #define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
171 #define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
173 #define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
174 #define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
175 #define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
176 #define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
177 #define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
179 #define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
180 #define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
181 #define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
182 #define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
183 #define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
185 #define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
186 #define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
187 #define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
188 #define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
189 #define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
191 #define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
192 #define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
193 #define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
194 #define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
195 #define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
197 #define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
198 #define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
199 #define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
201 #define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
203 #define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
204 #define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
205 #define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
206 #define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
207 #define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
208 #define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
209 #define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
210 #define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
211 #define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
212 #define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
213 #define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
214 #define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
216 #define IIO_IPCR 0x00430000 /* IO Performance Control */
217 #define IIO_IPPR 0x00430008 /* IO Performance Profiling */
220 /************************************************************************
222 * Description: This register echoes some information from the *
223 * LB_REV_ID register. It is available through Crosstalk as described *
224 * above. The REV_NUM and MFG_NUM fields receive their values from *
225 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
226 * The PART_NUM field's value is the Crosstalk device ID number that *
227 * Steve Miller assigned to the SHub chip. *
229 ************************************************************************/
231 typedef union ii_wid_u {
232 uint64_t ii_wid_regval;
234 uint64_t w_rsvd_1 : 1;
235 uint64_t w_mfg_num : 11;
236 uint64_t w_part_num : 16;
237 uint64_t w_rev_num : 4;
238 uint64_t w_rsvd : 32;
243 /************************************************************************
245 * The fields in this register are set upon detection of an error *
246 * and cleared by various mechanisms, as explained in the *
249 ************************************************************************/
251 typedef union ii_wstat_u {
252 uint64_t ii_wstat_regval;
254 uint64_t w_pending : 4;
255 uint64_t w_xt_crd_to : 1;
256 uint64_t w_xt_tail_to : 1;
257 uint64_t w_rsvd_3 : 3;
258 uint64_t w_tx_mx_rty : 1;
259 uint64_t w_rsvd_2 : 6;
260 uint64_t w_llp_tx_cnt : 8;
261 uint64_t w_rsvd_1 : 8;
262 uint64_t w_crazy : 1;
263 uint64_t w_rsvd : 31;
268 /************************************************************************
270 * Description: This is a read-write enabled register. It controls *
271 * various aspects of the Crosstalk flow control. *
273 ************************************************************************/
275 typedef union ii_wcr_u {
276 uint64_t ii_wcr_regval;
280 uint64_t w_rsvd_1 : 8;
281 uint64_t w_dst_crd : 3;
282 uint64_t w_f_bad_pkt : 1;
283 uint64_t w_dir_con : 1;
284 uint64_t w_e_thresh : 5;
285 uint64_t w_rsvd : 41;
290 /************************************************************************
292 * Description: This register's value is a bit vector that guards *
293 * access to local registers within the II as well as to external *
294 * Crosstalk widgets. Each bit in the register corresponds to a *
295 * particular region in the system; a region consists of one, two or *
296 * four nodes (depending on the value of the REGION_SIZE field in the *
297 * LB_REV_ID register, which is documented in Section 8.3.1.1). The *
298 * protection provided by this register applies to PIO read *
299 * operations as well as PIO write operations. The II will perform a *
300 * PIO read or write request only if the bit for the requestor's *
301 * region is set; otherwise, the II will not perform the requested *
302 * operation and will return an error response. When a PIO read or *
303 * write request targets an external Crosstalk widget, then not only *
304 * must the bit for the requestor's region be set in the ILAPR, but *
305 * also the target widget's bit in the IOWA register must be set in *
306 * order for the II to perform the requested operation; otherwise, *
307 * the II will return an error response. Hence, the protection *
308 * provided by the IOWA register supplements the protection provided *
309 * by the ILAPR for requests that target external Crosstalk widgets. *
310 * This register itself can be accessed only by the nodes whose *
311 * region ID bits are enabled in this same register. It can also be *
312 * accessed through the IAlias space by the local processors. *
313 * The reset value of this register allows access by all nodes. *
315 ************************************************************************/
317 typedef union ii_ilapr_u {
318 uint64_t ii_ilapr_regval;
320 uint64_t i_region : 64;
327 /************************************************************************
329 * Description: A write to this register of the 64-bit value *
330 * "SGIrules" in ASCII, will cause the bit in the ILAPR register *
331 * corresponding to the region of the requestor to be set (allow *
332 * access). A write of any other value will be ignored. Access *
333 * protection for this register is "SGIrules". *
334 * This register can also be accessed through the IAlias space. *
335 * However, this access will not change the access permissions in the *
338 ************************************************************************/
340 typedef union ii_ilapo_u {
341 uint64_t ii_ilapo_regval;
343 uint64_t i_io_ovrride : 64;
349 /************************************************************************
351 * This register qualifies all the PIO and Graphics writes launched *
352 * from the SHUB towards a widget. *
354 ************************************************************************/
356 typedef union ii_iowa_u {
357 uint64_t ii_iowa_regval;
359 uint64_t i_w0_oac : 1;
360 uint64_t i_rsvd_1 : 7;
361 uint64_t i_wx_oac : 8;
362 uint64_t i_rsvd : 48;
367 /************************************************************************
369 * Description: This register qualifies all the requests launched *
370 * from a widget towards the Shub. This register is intended to be *
371 * used by software in case of misbehaving widgets. *
374 ************************************************************************/
376 typedef union ii_iiwa_u {
377 uint64_t ii_iiwa_regval;
379 uint64_t i_w0_iac : 1;
380 uint64_t i_rsvd_1 : 7;
381 uint64_t i_wx_iac : 8;
382 uint64_t i_rsvd : 48;
388 /************************************************************************
390 * Description: This register qualifies all the operations launched *
391 * from a widget towards the SHub. It allows individual access *
392 * control for up to 8 devices per widget. A device refers to *
393 * individual DMA master hosted by a widget. *
394 * The bits in each field of this register are cleared by the Shub *
395 * upon detection of an error which requires the device to be *
396 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
397 * Crosstalk). Whether or not a device has access rights to this *
398 * Shub is determined by an AND of the device enable bit in the *
399 * appropriate field of this register and the corresponding bit in *
400 * the Wx_IAC field (for the widget which this device belongs to). *
401 * The bits in this field are set by writing a 1 to them. Incoming *
402 * replies from Crosstalk are not subject to this access control *
405 ************************************************************************/
407 typedef union ii_iidem_u {
408 uint64_t ii_iidem_regval;
410 uint64_t i_w8_dxs : 8;
411 uint64_t i_w9_dxs : 8;
412 uint64_t i_wa_dxs : 8;
413 uint64_t i_wb_dxs : 8;
414 uint64_t i_wc_dxs : 8;
415 uint64_t i_wd_dxs : 8;
416 uint64_t i_we_dxs : 8;
417 uint64_t i_wf_dxs : 8;
422 /************************************************************************
424 * This register contains the various programmable fields necessary *
425 * for controlling and observing the LLP signals. *
427 ************************************************************************/
429 typedef union ii_ilcsr_u {
430 uint64_t ii_ilcsr_regval;
432 uint64_t i_nullto : 6;
433 uint64_t i_rsvd_4 : 2;
434 uint64_t i_wrmrst : 1;
435 uint64_t i_rsvd_3 : 1;
436 uint64_t i_llp_en : 1;
438 uint64_t i_llp_stat : 2;
439 uint64_t i_remote_power : 1;
440 uint64_t i_rsvd_2 : 1;
441 uint64_t i_maxrtry : 10;
442 uint64_t i_d_avail_sel : 2;
443 uint64_t i_rsvd_1 : 4;
444 uint64_t i_maxbrst : 10;
445 uint64_t i_rsvd : 22;
451 /************************************************************************
453 * This is simply a status registers that monitors the LLP error *
456 ************************************************************************/
458 typedef union ii_illr_u {
459 uint64_t ii_illr_regval;
461 uint64_t i_sn_cnt : 16;
462 uint64_t i_cb_cnt : 16;
463 uint64_t i_rsvd : 32;
468 /************************************************************************
470 * Description: All II-detected non-BTE error interrupts are *
471 * specified via this register. *
472 * NOTE: The PI interrupt register address is hardcoded in the II. If *
473 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
474 * packet) to address offset 0x0180_0090 within the local register *
475 * address space of PI0 on the node specified by the NODE field. If *
476 * PI_ID==1, then the II sends the interrupt request to address *
477 * offset 0x01A0_0090 within the local register address space of PI1 *
478 * on the node specified by the NODE field. *
480 ************************************************************************/
482 typedef union ii_iidsr_u {
483 uint64_t ii_iidsr_regval;
485 uint64_t i_level : 8;
486 uint64_t i_pi_id : 1;
487 uint64_t i_node : 11;
488 uint64_t i_rsvd_3 : 4;
489 uint64_t i_enable : 1;
490 uint64_t i_rsvd_2 : 3;
491 uint64_t i_int_sent : 2;
492 uint64_t i_rsvd_1 : 2;
493 uint64_t i_pi0_forward_int : 1;
494 uint64_t i_pi1_forward_int : 1;
495 uint64_t i_rsvd : 30;
501 /************************************************************************
503 * There are two instances of this register. This register is used *
504 * for matching up the incoming responses from the graphics widget to *
505 * the processor that initiated the graphics operation. The *
506 * write-responses are converted to graphics credits and returned to *
507 * the processor so that the processor interface can manage the flow *
510 ************************************************************************/
512 typedef union ii_igfx0_u {
513 uint64_t ii_igfx0_regval;
515 uint64_t i_w_num : 4;
516 uint64_t i_pi_id : 1;
517 uint64_t i_n_num : 12;
518 uint64_t i_p_num : 1;
519 uint64_t i_rsvd : 46;
524 /************************************************************************
526 * There are two instances of this register. This register is used *
527 * for matching up the incoming responses from the graphics widget to *
528 * the processor that initiated the graphics operation. The *
529 * write-responses are converted to graphics credits and returned to *
530 * the processor so that the processor interface can manage the flow *
533 ************************************************************************/
535 typedef union ii_igfx1_u {
536 uint64_t ii_igfx1_regval;
538 uint64_t i_w_num : 4;
539 uint64_t i_pi_id : 1;
540 uint64_t i_n_num : 12;
541 uint64_t i_p_num : 1;
542 uint64_t i_rsvd : 46;
547 /************************************************************************
549 * There are two instances of this registers. These registers are *
550 * used as scratch registers for software use. *
552 ************************************************************************/
554 typedef union ii_iscr0_u {
555 uint64_t ii_iscr0_regval;
557 uint64_t i_scratch : 64;
563 /************************************************************************
565 * There are two instances of this registers. These registers are *
566 * used as scratch registers for software use. *
568 ************************************************************************/
570 typedef union ii_iscr1_u {
571 uint64_t ii_iscr1_regval;
573 uint64_t i_scratch : 64;
578 /************************************************************************
580 * Description: There are seven instances of translation table entry *
581 * registers. Each register maps a Shub Big Window to a 48-bit *
582 * address on Crosstalk. *
583 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
584 * number) are used to select one of these 7 registers. The Widget *
585 * number field is then derived from the W_NUM field for synthesizing *
586 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
587 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
588 * are padded with zeros. Although the maximum Crosstalk space *
589 * addressable by the SHub is thus the lower 16 GBytes per widget *
590 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
591 * space can be accessed. *
592 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
593 * Window number) are used to select one of these 7 registers. The *
594 * Widget number field is then derived from the W_NUM field for *
595 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
596 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
597 * field is used as Crosstalk[47], and remainder of the Crosstalk *
598 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
599 * Crosstalk space addressable by the Shub is thus the lower *
600 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
601 * of this space can be accessed. *
603 ************************************************************************/
605 typedef union ii_itte1_u {
606 uint64_t ii_itte1_regval;
608 uint64_t i_offset : 5;
609 uint64_t i_rsvd_1 : 3;
610 uint64_t i_w_num : 4;
612 uint64_t i_rsvd : 51;
617 /************************************************************************
619 * Description: There are seven instances of translation table entry *
620 * registers. Each register maps a Shub Big Window to a 48-bit *
621 * address on Crosstalk. *
622 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
623 * number) are used to select one of these 7 registers. The Widget *
624 * number field is then derived from the W_NUM field for synthesizing *
625 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
626 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
627 * are padded with zeros. Although the maximum Crosstalk space *
628 * addressable by the Shub is thus the lower 16 GBytes per widget *
629 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
630 * space can be accessed. *
631 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
632 * Window number) are used to select one of these 7 registers. The *
633 * Widget number field is then derived from the W_NUM field for *
634 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
635 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
636 * field is used as Crosstalk[47], and remainder of the Crosstalk *
637 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
638 * Crosstalk space addressable by the Shub is thus the lower *
639 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
640 * of this space can be accessed. *
642 ************************************************************************/
644 typedef union ii_itte2_u {
645 uint64_t ii_itte2_regval;
647 uint64_t i_offset : 5;
648 uint64_t i_rsvd_1 : 3;
649 uint64_t i_w_num : 4;
651 uint64_t i_rsvd : 51;
656 /************************************************************************
658 * Description: There are seven instances of translation table entry *
659 * registers. Each register maps a Shub Big Window to a 48-bit *
660 * address on Crosstalk. *
661 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
662 * number) are used to select one of these 7 registers. The Widget *
663 * number field is then derived from the W_NUM field for synthesizing *
664 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
665 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
666 * are padded with zeros. Although the maximum Crosstalk space *
667 * addressable by the Shub is thus the lower 16 GBytes per widget *
668 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
669 * space can be accessed. *
670 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
671 * Window number) are used to select one of these 7 registers. The *
672 * Widget number field is then derived from the W_NUM field for *
673 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
674 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
675 * field is used as Crosstalk[47], and remainder of the Crosstalk *
676 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
677 * Crosstalk space addressable by the SHub is thus the lower *
678 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
679 * of this space can be accessed. *
681 ************************************************************************/
683 typedef union ii_itte3_u {
684 uint64_t ii_itte3_regval;
686 uint64_t i_offset : 5;
687 uint64_t i_rsvd_1 : 3;
688 uint64_t i_w_num : 4;
690 uint64_t i_rsvd : 51;
695 /************************************************************************
697 * Description: There are seven instances of translation table entry *
698 * registers. Each register maps a SHub Big Window to a 48-bit *
699 * address on Crosstalk. *
700 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
701 * number) are used to select one of these 7 registers. The Widget *
702 * number field is then derived from the W_NUM field for synthesizing *
703 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
704 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
705 * are padded with zeros. Although the maximum Crosstalk space *
706 * addressable by the SHub is thus the lower 16 GBytes per widget *
707 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
708 * space can be accessed. *
709 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
710 * Window number) are used to select one of these 7 registers. The *
711 * Widget number field is then derived from the W_NUM field for *
712 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
713 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
714 * field is used as Crosstalk[47], and remainder of the Crosstalk *
715 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
716 * Crosstalk space addressable by the SHub is thus the lower *
717 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
718 * of this space can be accessed. *
720 ************************************************************************/
722 typedef union ii_itte4_u {
723 uint64_t ii_itte4_regval;
725 uint64_t i_offset : 5;
726 uint64_t i_rsvd_1 : 3;
727 uint64_t i_w_num : 4;
729 uint64_t i_rsvd : 51;
734 /************************************************************************
736 * Description: There are seven instances of translation table entry *
737 * registers. Each register maps a SHub Big Window to a 48-bit *
738 * address on Crosstalk. *
739 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
740 * number) are used to select one of these 7 registers. The Widget *
741 * number field is then derived from the W_NUM field for synthesizing *
742 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
743 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
744 * are padded with zeros. Although the maximum Crosstalk space *
745 * addressable by the Shub is thus the lower 16 GBytes per widget *
746 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
747 * space can be accessed. *
748 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
749 * Window number) are used to select one of these 7 registers. The *
750 * Widget number field is then derived from the W_NUM field for *
751 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
752 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
753 * field is used as Crosstalk[47], and remainder of the Crosstalk *
754 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
755 * Crosstalk space addressable by the Shub is thus the lower *
756 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
757 * of this space can be accessed. *
759 ************************************************************************/
761 typedef union ii_itte5_u {
762 uint64_t ii_itte5_regval;
764 uint64_t i_offset : 5;
765 uint64_t i_rsvd_1 : 3;
766 uint64_t i_w_num : 4;
768 uint64_t i_rsvd : 51;
773 /************************************************************************
775 * Description: There are seven instances of translation table entry *
776 * registers. Each register maps a Shub Big Window to a 48-bit *
777 * address on Crosstalk. *
778 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
779 * number) are used to select one of these 7 registers. The Widget *
780 * number field is then derived from the W_NUM field for synthesizing *
781 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
782 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
783 * are padded with zeros. Although the maximum Crosstalk space *
784 * addressable by the Shub is thus the lower 16 GBytes per widget *
785 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
786 * space can be accessed. *
787 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
788 * Window number) are used to select one of these 7 registers. The *
789 * Widget number field is then derived from the W_NUM field for *
790 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
791 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
792 * field is used as Crosstalk[47], and remainder of the Crosstalk *
793 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
794 * Crosstalk space addressable by the Shub is thus the lower *
795 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
796 * of this space can be accessed. *
798 ************************************************************************/
800 typedef union ii_itte6_u {
801 uint64_t ii_itte6_regval;
803 uint64_t i_offset : 5;
804 uint64_t i_rsvd_1 : 3;
805 uint64_t i_w_num : 4;
807 uint64_t i_rsvd : 51;
812 /************************************************************************
814 * Description: There are seven instances of translation table entry *
815 * registers. Each register maps a Shub Big Window to a 48-bit *
816 * address on Crosstalk. *
817 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
818 * number) are used to select one of these 7 registers. The Widget *
819 * number field is then derived from the W_NUM field for synthesizing *
820 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
821 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
822 * are padded with zeros. Although the maximum Crosstalk space *
823 * addressable by the Shub is thus the lower 16 GBytes per widget *
824 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
825 * space can be accessed. *
826 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
827 * Window number) are used to select one of these 7 registers. The *
828 * Widget number field is then derived from the W_NUM field for *
829 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
830 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
831 * field is used as Crosstalk[47], and remainder of the Crosstalk *
832 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
833 * Crosstalk space addressable by the SHub is thus the lower *
834 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
835 * of this space can be accessed. *
837 ************************************************************************/
839 typedef union ii_itte7_u {
840 uint64_t ii_itte7_regval;
842 uint64_t i_offset : 5;
843 uint64_t i_rsvd_1 : 3;
844 uint64_t i_w_num : 4;
846 uint64_t i_rsvd : 51;
851 /************************************************************************
853 * Description: There are 9 instances of this register, one per *
854 * actual widget in this implementation of SHub and Crossbow. *
855 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
856 * refers to Crossbow's internal space. *
857 * This register contains the state elements per widget that are *
858 * necessary to manage the PIO flow control on Crosstalk and on the *
859 * Router Network. See the PIO Flow Control chapter for a complete *
860 * description of this register *
861 * The SPUR_WR bit requires some explanation. When this register is *
862 * written, the new value of the C field is captured in an internal *
863 * register so the hardware can remember what the programmer wrote *
864 * into the credit counter. The SPUR_WR bit sets whenever the C field *
865 * increments above this stored value, which indicates that there *
866 * have been more responses received than requests sent. The SPUR_WR *
867 * bit cannot be cleared until a value is written to the IPRBx *
868 * register; the write will correct the C field and capture its new *
869 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
870 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
873 ************************************************************************/
875 typedef union ii_iprb0_u {
876 uint64_t ii_iprb0_regval;
880 uint64_t i_rsvd_2 : 2;
882 uint64_t i_rsvd_1 : 2;
885 uint64_t i_of_cnt : 5;
886 uint64_t i_error : 1;
887 uint64_t i_rd_to : 1;
888 uint64_t i_spur_wr : 1;
889 uint64_t i_spur_rd : 1;
890 uint64_t i_rsvd : 11;
891 uint64_t i_mult_err : 1;
896 /************************************************************************
898 * Description: There are 9 instances of this register, one per *
899 * actual widget in this implementation of SHub and Crossbow. *
900 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
901 * refers to Crossbow's internal space. *
902 * This register contains the state elements per widget that are *
903 * necessary to manage the PIO flow control on Crosstalk and on the *
904 * Router Network. See the PIO Flow Control chapter for a complete *
905 * description of this register *
906 * The SPUR_WR bit requires some explanation. When this register is *
907 * written, the new value of the C field is captured in an internal *
908 * register so the hardware can remember what the programmer wrote *
909 * into the credit counter. The SPUR_WR bit sets whenever the C field *
910 * increments above this stored value, which indicates that there *
911 * have been more responses received than requests sent. The SPUR_WR *
912 * bit cannot be cleared until a value is written to the IPRBx *
913 * register; the write will correct the C field and capture its new *
914 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
915 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
918 ************************************************************************/
920 typedef union ii_iprb8_u {
921 uint64_t ii_iprb8_regval;
925 uint64_t i_rsvd_2 : 2;
927 uint64_t i_rsvd_1 : 2;
930 uint64_t i_of_cnt : 5;
931 uint64_t i_error : 1;
932 uint64_t i_rd_to : 1;
933 uint64_t i_spur_wr : 1;
934 uint64_t i_spur_rd : 1;
935 uint64_t i_rsvd : 11;
936 uint64_t i_mult_err : 1;
941 /************************************************************************
943 * Description: There are 9 instances of this register, one per *
944 * actual widget in this implementation of SHub and Crossbow. *
945 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
946 * refers to Crossbow's internal space. *
947 * This register contains the state elements per widget that are *
948 * necessary to manage the PIO flow control on Crosstalk and on the *
949 * Router Network. See the PIO Flow Control chapter for a complete *
950 * description of this register *
951 * The SPUR_WR bit requires some explanation. When this register is *
952 * written, the new value of the C field is captured in an internal *
953 * register so the hardware can remember what the programmer wrote *
954 * into the credit counter. The SPUR_WR bit sets whenever the C field *
955 * increments above this stored value, which indicates that there *
956 * have been more responses received than requests sent. The SPUR_WR *
957 * bit cannot be cleared until a value is written to the IPRBx *
958 * register; the write will correct the C field and capture its new *
959 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
960 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
963 ************************************************************************/
965 typedef union ii_iprb9_u {
966 uint64_t ii_iprb9_regval;
970 uint64_t i_rsvd_2 : 2;
972 uint64_t i_rsvd_1 : 2;
975 uint64_t i_of_cnt : 5;
976 uint64_t i_error : 1;
977 uint64_t i_rd_to : 1;
978 uint64_t i_spur_wr : 1;
979 uint64_t i_spur_rd : 1;
980 uint64_t i_rsvd : 11;
981 uint64_t i_mult_err : 1;
986 /************************************************************************
988 * Description: There are 9 instances of this register, one per *
989 * actual widget in this implementation of SHub and Crossbow. *
990 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
991 * refers to Crossbow's internal space. *
992 * This register contains the state elements per widget that are *
993 * necessary to manage the PIO flow control on Crosstalk and on the *
994 * Router Network. See the PIO Flow Control chapter for a complete *
995 * description of this register *
996 * The SPUR_WR bit requires some explanation. When this register is *
997 * written, the new value of the C field is captured in an internal *
998 * register so the hardware can remember what the programmer wrote *
999 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1000 * increments above this stored value, which indicates that there *
1001 * have been more responses received than requests sent. The SPUR_WR *
1002 * bit cannot be cleared until a value is written to the IPRBx *
1003 * register; the write will correct the C field and capture its new *
1004 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1005 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1008 ************************************************************************/
1010 typedef union ii_iprba_u {
1011 uint64_t ii_iprba_regval;
1015 uint64_t i_rsvd_2 : 2;
1017 uint64_t i_rsvd_1 : 2;
1020 uint64_t i_of_cnt : 5;
1021 uint64_t i_error : 1;
1022 uint64_t i_rd_to : 1;
1023 uint64_t i_spur_wr : 1;
1024 uint64_t i_spur_rd : 1;
1025 uint64_t i_rsvd : 11;
1026 uint64_t i_mult_err : 1;
1031 /************************************************************************
1033 * Description: There are 9 instances of this register, one per *
1034 * actual widget in this implementation of SHub and Crossbow. *
1035 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1036 * refers to Crossbow's internal space. *
1037 * This register contains the state elements per widget that are *
1038 * necessary to manage the PIO flow control on Crosstalk and on the *
1039 * Router Network. See the PIO Flow Control chapter for a complete *
1040 * description of this register *
1041 * The SPUR_WR bit requires some explanation. When this register is *
1042 * written, the new value of the C field is captured in an internal *
1043 * register so the hardware can remember what the programmer wrote *
1044 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1045 * increments above this stored value, which indicates that there *
1046 * have been more responses received than requests sent. The SPUR_WR *
1047 * bit cannot be cleared until a value is written to the IPRBx *
1048 * register; the write will correct the C field and capture its new *
1049 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1050 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1053 ************************************************************************/
1055 typedef union ii_iprbb_u {
1056 uint64_t ii_iprbb_regval;
1060 uint64_t i_rsvd_2 : 2;
1062 uint64_t i_rsvd_1 : 2;
1065 uint64_t i_of_cnt : 5;
1066 uint64_t i_error : 1;
1067 uint64_t i_rd_to : 1;
1068 uint64_t i_spur_wr : 1;
1069 uint64_t i_spur_rd : 1;
1070 uint64_t i_rsvd : 11;
1071 uint64_t i_mult_err : 1;
1076 /************************************************************************
1078 * Description: There are 9 instances of this register, one per *
1079 * actual widget in this implementation of SHub and Crossbow. *
1080 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1081 * refers to Crossbow's internal space. *
1082 * This register contains the state elements per widget that are *
1083 * necessary to manage the PIO flow control on Crosstalk and on the *
1084 * Router Network. See the PIO Flow Control chapter for a complete *
1085 * description of this register *
1086 * The SPUR_WR bit requires some explanation. When this register is *
1087 * written, the new value of the C field is captured in an internal *
1088 * register so the hardware can remember what the programmer wrote *
1089 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1090 * increments above this stored value, which indicates that there *
1091 * have been more responses received than requests sent. The SPUR_WR *
1092 * bit cannot be cleared until a value is written to the IPRBx *
1093 * register; the write will correct the C field and capture its new *
1094 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1095 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1098 ************************************************************************/
1100 typedef union ii_iprbc_u {
1101 uint64_t ii_iprbc_regval;
1105 uint64_t i_rsvd_2 : 2;
1107 uint64_t i_rsvd_1 : 2;
1110 uint64_t i_of_cnt : 5;
1111 uint64_t i_error : 1;
1112 uint64_t i_rd_to : 1;
1113 uint64_t i_spur_wr : 1;
1114 uint64_t i_spur_rd : 1;
1115 uint64_t i_rsvd : 11;
1116 uint64_t i_mult_err : 1;
1121 /************************************************************************
1123 * Description: There are 9 instances of this register, one per *
1124 * actual widget in this implementation of SHub and Crossbow. *
1125 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1126 * refers to Crossbow's internal space. *
1127 * This register contains the state elements per widget that are *
1128 * necessary to manage the PIO flow control on Crosstalk and on the *
1129 * Router Network. See the PIO Flow Control chapter for a complete *
1130 * description of this register *
1131 * The SPUR_WR bit requires some explanation. When this register is *
1132 * written, the new value of the C field is captured in an internal *
1133 * register so the hardware can remember what the programmer wrote *
1134 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1135 * increments above this stored value, which indicates that there *
1136 * have been more responses received than requests sent. The SPUR_WR *
1137 * bit cannot be cleared until a value is written to the IPRBx *
1138 * register; the write will correct the C field and capture its new *
1139 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1140 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1143 ************************************************************************/
1145 typedef union ii_iprbd_u {
1146 uint64_t ii_iprbd_regval;
1150 uint64_t i_rsvd_2 : 2;
1152 uint64_t i_rsvd_1 : 2;
1155 uint64_t i_of_cnt : 5;
1156 uint64_t i_error : 1;
1157 uint64_t i_rd_to : 1;
1158 uint64_t i_spur_wr : 1;
1159 uint64_t i_spur_rd : 1;
1160 uint64_t i_rsvd : 11;
1161 uint64_t i_mult_err : 1;
1166 /************************************************************************
1168 * Description: There are 9 instances of this register, one per *
1169 * actual widget in this implementation of SHub and Crossbow. *
1170 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1171 * refers to Crossbow's internal space. *
1172 * This register contains the state elements per widget that are *
1173 * necessary to manage the PIO flow control on Crosstalk and on the *
1174 * Router Network. See the PIO Flow Control chapter for a complete *
1175 * description of this register *
1176 * The SPUR_WR bit requires some explanation. When this register is *
1177 * written, the new value of the C field is captured in an internal *
1178 * register so the hardware can remember what the programmer wrote *
1179 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1180 * increments above this stored value, which indicates that there *
1181 * have been more responses received than requests sent. The SPUR_WR *
1182 * bit cannot be cleared until a value is written to the IPRBx *
1183 * register; the write will correct the C field and capture its new *
1184 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1185 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1188 ************************************************************************/
1190 typedef union ii_iprbe_u {
1191 uint64_t ii_iprbe_regval;
1195 uint64_t i_rsvd_2 : 2;
1197 uint64_t i_rsvd_1 : 2;
1200 uint64_t i_of_cnt : 5;
1201 uint64_t i_error : 1;
1202 uint64_t i_rd_to : 1;
1203 uint64_t i_spur_wr : 1;
1204 uint64_t i_spur_rd : 1;
1205 uint64_t i_rsvd : 11;
1206 uint64_t i_mult_err : 1;
1211 /************************************************************************
1213 * Description: There are 9 instances of this register, one per *
1214 * actual widget in this implementation of Shub and Crossbow. *
1215 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1216 * refers to Crossbow's internal space. *
1217 * This register contains the state elements per widget that are *
1218 * necessary to manage the PIO flow control on Crosstalk and on the *
1219 * Router Network. See the PIO Flow Control chapter for a complete *
1220 * description of this register *
1221 * The SPUR_WR bit requires some explanation. When this register is *
1222 * written, the new value of the C field is captured in an internal *
1223 * register so the hardware can remember what the programmer wrote *
1224 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1225 * increments above this stored value, which indicates that there *
1226 * have been more responses received than requests sent. The SPUR_WR *
1227 * bit cannot be cleared until a value is written to the IPRBx *
1228 * register; the write will correct the C field and capture its new *
1229 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1230 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1233 ************************************************************************/
1235 typedef union ii_iprbf_u {
1236 uint64_t ii_iprbf_regval;
1240 uint64_t i_rsvd_2 : 2;
1242 uint64_t i_rsvd_1 : 2;
1245 uint64_t i_of_cnt : 5;
1246 uint64_t i_error : 1;
1247 uint64_t i_rd_to : 1;
1248 uint64_t i_spur_wr : 1;
1249 uint64_t i_spur_rd : 1;
1250 uint64_t i_rsvd : 11;
1251 uint64_t i_mult_err : 1;
1256 /************************************************************************
1258 * This register specifies the timeout value to use for monitoring *
1259 * Crosstalk credits which are used outbound to Crosstalk. An *
1260 * internal counter called the Crosstalk Credit Timeout Counter *
1261 * increments every 128 II clocks. The counter starts counting *
1262 * anytime the credit count drops below a threshold, and resets to *
1263 * zero (stops counting) anytime the credit count is at or above the *
1264 * threshold. The threshold is 1 credit in direct connect mode and 2 *
1265 * in Crossbow connect mode. When the internal Crosstalk Credit *
1266 * Timeout Counter reaches the value programmed in this register, a *
1267 * Crosstalk Credit Timeout has occurred. The internal counter is not *
1268 * readable from software, and stops counting at its maximum value, *
1269 * so it cannot cause more than one interrupt. *
1271 ************************************************************************/
1273 typedef union ii_ixcc_u {
1274 uint64_t ii_ixcc_regval;
1276 uint64_t i_time_out : 26;
1277 uint64_t i_rsvd : 38;
1282 /************************************************************************
1284 * Description: This register qualifies all the PIO and DMA *
1285 * operations launched from widget 0 towards the SHub. In *
1286 * addition, it also qualifies accesses by the BTE streams. *
1287 * The bits in each field of this register are cleared by the SHub *
1288 * upon detection of an error which requires widget 0 or the BTE *
1289 * streams to be terminated. Whether or not widget x has access *
1290 * rights to this SHub is determined by an AND of the device *
1291 * enable bit in the appropriate field of this register and bit 0 in *
1292 * the Wx_IAC field. The bits in this field are set by writing a 1 to *
1293 * them. Incoming replies from Crosstalk are not subject to this *
1294 * access control mechanism. *
1296 ************************************************************************/
1298 typedef union ii_imem_u {
1299 uint64_t ii_imem_regval;
1301 uint64_t i_w0_esd : 1;
1302 uint64_t i_rsvd_3 : 3;
1303 uint64_t i_b0_esd : 1;
1304 uint64_t i_rsvd_2 : 3;
1305 uint64_t i_b1_esd : 1;
1306 uint64_t i_rsvd_1 : 3;
1307 uint64_t i_clr_precise : 1;
1308 uint64_t i_rsvd : 51;
1314 /************************************************************************
1316 * Description: This register specifies the timeout value to use for *
1317 * monitoring Crosstalk tail flits coming into the Shub in the *
1318 * TAIL_TO field. An internal counter associated with this register *
1319 * is incremented every 128 II internal clocks (7 bits). The counter *
1320 * starts counting anytime a header micropacket is received and stops *
1321 * counting (and resets to zero) any time a micropacket with a Tail *
1322 * bit is received. Once the counter reaches the threshold value *
1323 * programmed in this register, it generates an interrupt to the *
1324 * processor that is programmed into the IIDSR. The counter saturates *
1325 * (does not roll over) at its maximum value, so it cannot cause *
1326 * another interrupt until after it is cleared. *
1327 * The register also contains the Read Response Timeout values. The *
1328 * Prescalar is 23 bits, and counts II clocks. An internal counter *
1329 * increments on every II clock and when it reaches the value in the *
1330 * Prescalar field, all IPRTE registers with their valid bits set *
1331 * have their Read Response timers bumped. Whenever any of them match *
1332 * the value in the RRSP_TO field, a Read Response Timeout has *
1333 * occurred, and error handling occurs as described in the Error *
1334 * Handling section of this document. *
1336 ************************************************************************/
1338 typedef union ii_ixtt_u {
1339 uint64_t ii_ixtt_regval;
1341 uint64_t i_tail_to : 26;
1342 uint64_t i_rsvd_1 : 6;
1343 uint64_t i_rrsp_ps : 23;
1344 uint64_t i_rrsp_to : 5;
1345 uint64_t i_rsvd : 4;
1350 /************************************************************************
1352 * Writing a 1 to the fields of this register clears the appropriate *
1353 * error bits in other areas of SHub. Note that when the *
1354 * E_PRB_x bits are used to clear error bits in PRB registers, *
1355 * SPUR_RD and SPUR_WR may persist, because they require additional *
1356 * action to clear them. See the IPRBx and IXSS Register *
1359 ************************************************************************/
1361 typedef union ii_ieclr_u {
1362 uint64_t ii_ieclr_regval;
1364 uint64_t i_e_prb_0 : 1;
1365 uint64_t i_rsvd : 7;
1366 uint64_t i_e_prb_8 : 1;
1367 uint64_t i_e_prb_9 : 1;
1368 uint64_t i_e_prb_a : 1;
1369 uint64_t i_e_prb_b : 1;
1370 uint64_t i_e_prb_c : 1;
1371 uint64_t i_e_prb_d : 1;
1372 uint64_t i_e_prb_e : 1;
1373 uint64_t i_e_prb_f : 1;
1374 uint64_t i_e_crazy : 1;
1375 uint64_t i_e_bte_0 : 1;
1376 uint64_t i_e_bte_1 : 1;
1377 uint64_t i_reserved_1 : 10;
1378 uint64_t i_spur_rd_hdr : 1;
1379 uint64_t i_cam_intr_to : 1;
1380 uint64_t i_cam_overflow : 1;
1381 uint64_t i_cam_read_miss : 1;
1382 uint64_t i_ioq_rep_underflow : 1;
1383 uint64_t i_ioq_req_underflow : 1;
1384 uint64_t i_ioq_rep_overflow : 1;
1385 uint64_t i_ioq_req_overflow : 1;
1386 uint64_t i_iiq_rep_overflow : 1;
1387 uint64_t i_iiq_req_overflow : 1;
1388 uint64_t i_ii_xn_rep_cred_overflow : 1;
1389 uint64_t i_ii_xn_req_cred_overflow : 1;
1390 uint64_t i_ii_xn_invalid_cmd : 1;
1391 uint64_t i_xn_ii_invalid_cmd : 1;
1392 uint64_t i_reserved_2 : 21;
1397 /************************************************************************
1399 * This register controls both BTEs. SOFT_RESET is intended for *
1400 * recovery after an error. COUNT controls the total number of CRBs *
1401 * that both BTEs (combined) can use, which affects total BTE *
1404 ************************************************************************/
1406 typedef union ii_ibcr_u {
1407 uint64_t ii_ibcr_regval;
1409 uint64_t i_count : 4;
1410 uint64_t i_rsvd_1 : 4;
1411 uint64_t i_soft_reset : 1;
1412 uint64_t i_rsvd : 55;
1417 /************************************************************************
1419 * This register contains the header of a spurious read response *
1420 * received from Crosstalk. A spurious read response is defined as a *
1421 * read response received by II from a widget for which (1) the SIDN *
1422 * has a value between 1 and 7, inclusive (II never sends requests to *
1423 * these widgets (2) there is no valid IPRTE register which *
1424 * corresponds to the TNUM, or (3) the widget indicated in SIDN is *
1425 * not the same as the widget recorded in the IPRTE register *
1426 * referenced by the TNUM. If this condition is true, and if the *
1427 * IXSS[VALID] bit is clear, then the header of the spurious read *
1428 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
1429 * errant header is thereby captured, and no further spurious read *
1430 * respones are captured until IXSS[VALID] is cleared by setting the *
1431 * appropriate bit in IECLR.Everytime a spurious read response is *
1432 * detected, the SPUR_RD bit of the PRB corresponding to the incoming *
1433 * message's SIDN field is set. This always happens, regarless of *
1434 * whether a header is captured. The programmer should check *
1435 * IXSM[SIDN] to determine which widget sent the spurious response, *
1436 * because there may be more than one SPUR_RD bit set in the PRB *
1437 * registers. The widget indicated by IXSM[SIDN] was the first *
1438 * spurious read response to be received since the last time *
1439 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
1440 * will be set. Any SPUR_RD bits in any other PRB registers indicate *
1441 * spurious messages from other widets which were detected after the *
1442 * header was captured.. *
1444 ************************************************************************/
1446 typedef union ii_ixsm_u {
1447 uint64_t ii_ixsm_regval;
1449 uint64_t i_byte_en : 32;
1450 uint64_t i_reserved : 1;
1452 uint64_t i_alt_pactyp : 4;
1454 uint64_t i_error : 1;
1455 uint64_t i_vbpm : 1;
1459 uint64_t i_tnum : 5;
1460 uint64_t i_pactyp : 4;
1461 uint64_t i_sidn : 4;
1462 uint64_t i_didn : 4;
1467 /************************************************************************
1469 * This register contains the sideband bits of a spurious read *
1470 * response received from Crosstalk. *
1472 ************************************************************************/
1474 typedef union ii_ixss_u {
1475 uint64_t ii_ixss_regval;
1477 uint64_t i_sideband : 8;
1478 uint64_t i_rsvd : 55;
1479 uint64_t i_valid : 1;
1484 /************************************************************************
1486 * This register enables software to access the II LLP's test port. *
1487 * Refer to the LLP 2.5 documentation for an explanation of the test *
1488 * port. Software can write to this register to program the values *
1489 * for the control fields (TestErrCapture, TestClear, TestFlit, *
1490 * TestMask and TestSeed). Similarly, software can read from this *
1491 * register to obtain the values of the test port's status outputs *
1492 * (TestCBerr, TestValid and TestData). *
1494 ************************************************************************/
1496 typedef union ii_ilct_u {
1497 uint64_t ii_ilct_regval;
1499 uint64_t i_test_seed : 20;
1500 uint64_t i_test_mask : 8;
1501 uint64_t i_test_data : 20;
1502 uint64_t i_test_valid : 1;
1503 uint64_t i_test_cberr : 1;
1504 uint64_t i_test_flit : 3;
1505 uint64_t i_test_clear : 1;
1506 uint64_t i_test_err_capture : 1;
1507 uint64_t i_rsvd : 9;
1512 /************************************************************************
1514 * If the II detects an illegal incoming Duplonet packet (request or *
1515 * reply) when VALID==0 in the IIEPH1 register, then it saves the *
1516 * contents of the packet's header flit in the IIEPH1 and IIEPH2 *
1517 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
1518 * and assigns a value to the ERR_TYPE field which indicates the *
1519 * specific nature of the error. The II recognizes four different *
1520 * types of errors: short request packets (ERR_TYPE==2), short reply *
1521 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
1522 * reply packets (ERR_TYPE==5). The encodings for these types of *
1523 * errors were chosen to be consistent with the same types of errors *
1524 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
1525 * the LB unit). If the II detects an illegal incoming Duplonet *
1526 * packet when VALID==1 in the IIEPH1 register, then it merely sets *
1527 * the OVERRUN bit to indicate that a subsequent error has happened, *
1528 * and does nothing further. *
1530 ************************************************************************/
1532 typedef union ii_iieph1_u {
1533 uint64_t ii_iieph1_regval;
1535 uint64_t i_command : 7;
1536 uint64_t i_rsvd_5 : 1;
1537 uint64_t i_suppl : 14;
1538 uint64_t i_rsvd_4 : 1;
1539 uint64_t i_source : 14;
1540 uint64_t i_rsvd_3 : 1;
1541 uint64_t i_err_type : 4;
1542 uint64_t i_rsvd_2 : 4;
1543 uint64_t i_overrun : 1;
1544 uint64_t i_rsvd_1 : 3;
1545 uint64_t i_valid : 1;
1546 uint64_t i_rsvd : 13;
1551 /************************************************************************
1553 * This register holds the Address field from the header flit of an *
1554 * incoming erroneous Duplonet packet, along with the tail bit which *
1555 * accompanied this header flit. This register is essentially an *
1556 * extension of IIEPH1. Two registers were necessary because the 64 *
1557 * bits available in only a single register were insufficient to *
1558 * capture the entire header flit of an erroneous packet. *
1560 ************************************************************************/
1562 typedef union ii_iieph2_u {
1563 uint64_t ii_iieph2_regval;
1565 uint64_t i_rsvd_0 : 3;
1566 uint64_t i_address : 47;
1567 uint64_t i_rsvd_1 : 10;
1568 uint64_t i_tail : 1;
1569 uint64_t i_rsvd : 3;
1574 /******************************/
1578 /************************************************************************
1580 * This register's value is a bit vector that guards access from SXBs *
1581 * to local registers within the II as well as to external Crosstalk *
1584 ************************************************************************/
1586 typedef union ii_islapr_u {
1587 uint64_t ii_islapr_regval;
1589 uint64_t i_region : 64;
1594 /************************************************************************
1596 * A write to this register of the 56-bit value "Pup+Bun" will cause *
1597 * the bit in the ISLAPR register corresponding to the region of the *
1598 * requestor to be set (access allowed). (
1600 ************************************************************************/
1602 typedef union ii_islapo_u {
1603 uint64_t ii_islapo_regval;
1605 uint64_t i_io_sbx_ovrride : 56;
1606 uint64_t i_rsvd : 8;
1610 /************************************************************************
1612 * Determines how long the wrapper will wait aftr an interrupt is *
1613 * initially issued from the II before it times out the outstanding *
1614 * interrupt and drops it from the interrupt queue. *
1616 ************************************************************************/
1618 typedef union ii_iwi_u {
1619 uint64_t ii_iwi_regval;
1621 uint64_t i_prescale : 24;
1622 uint64_t i_rsvd : 8;
1623 uint64_t i_timeout : 8;
1624 uint64_t i_rsvd1 : 8;
1625 uint64_t i_intrpt_retry_period : 8;
1626 uint64_t i_rsvd2 : 8;
1630 /************************************************************************
1632 * Log errors which have occurred in the II wrapper. The errors are *
1633 * cleared by writing to the IECLR register. *
1635 ************************************************************************/
1637 typedef union ii_iwel_u {
1638 uint64_t ii_iwel_regval;
1640 uint64_t i_intr_timed_out : 1;
1641 uint64_t i_rsvd : 7;
1642 uint64_t i_cam_overflow : 1;
1643 uint64_t i_cam_read_miss : 1;
1644 uint64_t i_rsvd1 : 2;
1645 uint64_t i_ioq_rep_underflow : 1;
1646 uint64_t i_ioq_req_underflow : 1;
1647 uint64_t i_ioq_rep_overflow : 1;
1648 uint64_t i_ioq_req_overflow : 1;
1649 uint64_t i_iiq_rep_overflow : 1;
1650 uint64_t i_iiq_req_overflow : 1;
1651 uint64_t i_rsvd2 : 6;
1652 uint64_t i_ii_xn_rep_cred_over_under: 1;
1653 uint64_t i_ii_xn_req_cred_over_under: 1;
1654 uint64_t i_rsvd3 : 6;
1655 uint64_t i_ii_xn_invalid_cmd : 1;
1656 uint64_t i_xn_ii_invalid_cmd : 1;
1657 uint64_t i_rsvd4 : 30;
1661 /************************************************************************
1663 * Controls the II wrapper. *
1665 ************************************************************************/
1667 typedef union ii_iwc_u {
1668 uint64_t ii_iwc_regval;
1670 uint64_t i_dma_byte_swap : 1;
1671 uint64_t i_rsvd : 3;
1672 uint64_t i_cam_read_lines_reset : 1;
1673 uint64_t i_rsvd1 : 3;
1674 uint64_t i_ii_xn_cred_over_under_log: 1;
1675 uint64_t i_rsvd2 : 19;
1676 uint64_t i_xn_rep_iq_depth : 5;
1677 uint64_t i_rsvd3 : 3;
1678 uint64_t i_xn_req_iq_depth : 5;
1679 uint64_t i_rsvd4 : 3;
1680 uint64_t i_iiq_depth : 6;
1681 uint64_t i_rsvd5 : 12;
1682 uint64_t i_force_rep_cred : 1;
1683 uint64_t i_force_req_cred : 1;
1687 /************************************************************************
1689 * Status in the II wrapper. *
1691 ************************************************************************/
1693 typedef union ii_iws_u {
1694 uint64_t ii_iws_regval;
1696 uint64_t i_xn_rep_iq_credits : 5;
1697 uint64_t i_rsvd : 3;
1698 uint64_t i_xn_req_iq_credits : 5;
1699 uint64_t i_rsvd1 : 51;
1703 /************************************************************************
1705 * Masks errors in the IWEL register. *
1707 ************************************************************************/
1709 typedef union ii_iweim_u {
1710 uint64_t ii_iweim_regval;
1712 uint64_t i_intr_timed_out : 1;
1713 uint64_t i_rsvd : 7;
1714 uint64_t i_cam_overflow : 1;
1715 uint64_t i_cam_read_miss : 1;
1716 uint64_t i_rsvd1 : 2;
1717 uint64_t i_ioq_rep_underflow : 1;
1718 uint64_t i_ioq_req_underflow : 1;
1719 uint64_t i_ioq_rep_overflow : 1;
1720 uint64_t i_ioq_req_overflow : 1;
1721 uint64_t i_iiq_rep_overflow : 1;
1722 uint64_t i_iiq_req_overflow : 1;
1723 uint64_t i_rsvd2 : 6;
1724 uint64_t i_ii_xn_rep_cred_overflow : 1;
1725 uint64_t i_ii_xn_req_cred_overflow : 1;
1726 uint64_t i_rsvd3 : 6;
1727 uint64_t i_ii_xn_invalid_cmd : 1;
1728 uint64_t i_xn_ii_invalid_cmd : 1;
1729 uint64_t i_rsvd4 : 30;
1734 /************************************************************************
1736 * A write to this register causes a particular field in the *
1737 * corresponding widget's PRB entry to be adjusted up or down by 1. *
1738 * This counter should be used when recovering from error and reset *
1739 * conditions. Note that software would be capable of causing *
1740 * inadvertent overflow or underflow of these counters. *
1742 ************************************************************************/
1744 typedef union ii_ipca_u {
1745 uint64_t ii_ipca_regval;
1748 uint64_t i_adjust : 1;
1749 uint64_t i_rsvd_1 : 3;
1750 uint64_t i_field : 2;
1751 uint64_t i_rsvd : 54;
1756 /************************************************************************
1758 * There are 8 instances of this register. This register contains *
1759 * the information that the II has to remember once it has launched a *
1760 * PIO Read operation. The contents are used to form the correct *
1761 * Router Network packet and direct the Crosstalk reply to the *
1762 * appropriate processor. *
1764 ************************************************************************/
1767 typedef union ii_iprte0a_u {
1768 uint64_t ii_iprte0a_regval;
1770 uint64_t i_rsvd_1 : 54;
1771 uint64_t i_widget : 4;
1772 uint64_t i_to_cnt : 5;
1778 /************************************************************************
1780 * There are 8 instances of this register. This register contains *
1781 * the information that the II has to remember once it has launched a *
1782 * PIO Read operation. The contents are used to form the correct *
1783 * Router Network packet and direct the Crosstalk reply to the *
1784 * appropriate processor. *
1786 ************************************************************************/
1788 typedef union ii_iprte1a_u {
1789 uint64_t ii_iprte1a_regval;
1791 uint64_t i_rsvd_1 : 54;
1792 uint64_t i_widget : 4;
1793 uint64_t i_to_cnt : 5;
1799 /************************************************************************
1801 * There are 8 instances of this register. This register contains *
1802 * the information that the II has to remember once it has launched a *
1803 * PIO Read operation. The contents are used to form the correct *
1804 * Router Network packet and direct the Crosstalk reply to the *
1805 * appropriate processor. *
1807 ************************************************************************/
1809 typedef union ii_iprte2a_u {
1810 uint64_t ii_iprte2a_regval;
1812 uint64_t i_rsvd_1 : 54;
1813 uint64_t i_widget : 4;
1814 uint64_t i_to_cnt : 5;
1820 /************************************************************************
1822 * There are 8 instances of this register. This register contains *
1823 * the information that the II has to remember once it has launched a *
1824 * PIO Read operation. The contents are used to form the correct *
1825 * Router Network packet and direct the Crosstalk reply to the *
1826 * appropriate processor. *
1828 ************************************************************************/
1830 typedef union ii_iprte3a_u {
1831 uint64_t ii_iprte3a_regval;
1833 uint64_t i_rsvd_1 : 54;
1834 uint64_t i_widget : 4;
1835 uint64_t i_to_cnt : 5;
1841 /************************************************************************
1843 * There are 8 instances of this register. This register contains *
1844 * the information that the II has to remember once it has launched a *
1845 * PIO Read operation. The contents are used to form the correct *
1846 * Router Network packet and direct the Crosstalk reply to the *
1847 * appropriate processor. *
1849 ************************************************************************/
1851 typedef union ii_iprte4a_u {
1852 uint64_t ii_iprte4a_regval;
1854 uint64_t i_rsvd_1 : 54;
1855 uint64_t i_widget : 4;
1856 uint64_t i_to_cnt : 5;
1862 /************************************************************************
1864 * There are 8 instances of this register. This register contains *
1865 * the information that the II has to remember once it has launched a *
1866 * PIO Read operation. The contents are used to form the correct *
1867 * Router Network packet and direct the Crosstalk reply to the *
1868 * appropriate processor. *
1870 ************************************************************************/
1872 typedef union ii_iprte5a_u {
1873 uint64_t ii_iprte5a_regval;
1875 uint64_t i_rsvd_1 : 54;
1876 uint64_t i_widget : 4;
1877 uint64_t i_to_cnt : 5;
1883 /************************************************************************
1885 * There are 8 instances of this register. This register contains *
1886 * the information that the II has to remember once it has launched a *
1887 * PIO Read operation. The contents are used to form the correct *
1888 * Router Network packet and direct the Crosstalk reply to the *
1889 * appropriate processor. *
1891 ************************************************************************/
1893 typedef union ii_iprte6a_u {
1894 uint64_t ii_iprte6a_regval;
1896 uint64_t i_rsvd_1 : 54;
1897 uint64_t i_widget : 4;
1898 uint64_t i_to_cnt : 5;
1904 /************************************************************************
1906 * There are 8 instances of this register. This register contains *
1907 * the information that the II has to remember once it has launched a *
1908 * PIO Read operation. The contents are used to form the correct *
1909 * Router Network packet and direct the Crosstalk reply to the *
1910 * appropriate processor. *
1912 ************************************************************************/
1914 typedef union ii_iprte7a_u {
1915 uint64_t ii_iprte7a_regval;
1917 uint64_t i_rsvd_1 : 54;
1918 uint64_t i_widget : 4;
1919 uint64_t i_to_cnt : 5;
1926 /************************************************************************
1928 * There are 8 instances of this register. This register contains *
1929 * the information that the II has to remember once it has launched a *
1930 * PIO Read operation. The contents are used to form the correct *
1931 * Router Network packet and direct the Crosstalk reply to the *
1932 * appropriate processor. *
1934 ************************************************************************/
1937 typedef union ii_iprte0b_u {
1938 uint64_t ii_iprte0b_regval;
1940 uint64_t i_rsvd_1 : 3;
1941 uint64_t i_address : 47;
1942 uint64_t i_init : 3;
1943 uint64_t i_source : 11;
1948 /************************************************************************
1950 * There are 8 instances of this register. This register contains *
1951 * the information that the II has to remember once it has launched a *
1952 * PIO Read operation. The contents are used to form the correct *
1953 * Router Network packet and direct the Crosstalk reply to the *
1954 * appropriate processor. *
1956 ************************************************************************/
1958 typedef union ii_iprte1b_u {
1959 uint64_t ii_iprte1b_regval;
1961 uint64_t i_rsvd_1 : 3;
1962 uint64_t i_address : 47;
1963 uint64_t i_init : 3;
1964 uint64_t i_source : 11;
1969 /************************************************************************
1971 * There are 8 instances of this register. This register contains *
1972 * the information that the II has to remember once it has launched a *
1973 * PIO Read operation. The contents are used to form the correct *
1974 * Router Network packet and direct the Crosstalk reply to the *
1975 * appropriate processor. *
1977 ************************************************************************/
1979 typedef union ii_iprte2b_u {
1980 uint64_t ii_iprte2b_regval;
1982 uint64_t i_rsvd_1 : 3;
1983 uint64_t i_address : 47;
1984 uint64_t i_init : 3;
1985 uint64_t i_source : 11;
1990 /************************************************************************
1992 * There are 8 instances of this register. This register contains *
1993 * the information that the II has to remember once it has launched a *
1994 * PIO Read operation. The contents are used to form the correct *
1995 * Router Network packet and direct the Crosstalk reply to the *
1996 * appropriate processor. *
1998 ************************************************************************/
2000 typedef union ii_iprte3b_u {
2001 uint64_t ii_iprte3b_regval;
2003 uint64_t i_rsvd_1 : 3;
2004 uint64_t i_address : 47;
2005 uint64_t i_init : 3;
2006 uint64_t i_source : 11;
2011 /************************************************************************
2013 * There are 8 instances of this register. This register contains *
2014 * the information that the II has to remember once it has launched a *
2015 * PIO Read operation. The contents are used to form the correct *
2016 * Router Network packet and direct the Crosstalk reply to the *
2017 * appropriate processor. *
2019 ************************************************************************/
2021 typedef union ii_iprte4b_u {
2022 uint64_t ii_iprte4b_regval;
2024 uint64_t i_rsvd_1 : 3;
2025 uint64_t i_address : 47;
2026 uint64_t i_init : 3;
2027 uint64_t i_source : 11;
2032 /************************************************************************
2034 * There are 8 instances of this register. This register contains *
2035 * the information that the II has to remember once it has launched a *
2036 * PIO Read operation. The contents are used to form the correct *
2037 * Router Network packet and direct the Crosstalk reply to the *
2038 * appropriate processor. *
2040 ************************************************************************/
2042 typedef union ii_iprte5b_u {
2043 uint64_t ii_iprte5b_regval;
2045 uint64_t i_rsvd_1 : 3;
2046 uint64_t i_address : 47;
2047 uint64_t i_init : 3;
2048 uint64_t i_source : 11;
2053 /************************************************************************
2055 * There are 8 instances of this register. This register contains *
2056 * the information that the II has to remember once it has launched a *
2057 * PIO Read operation. The contents are used to form the correct *
2058 * Router Network packet and direct the Crosstalk reply to the *
2059 * appropriate processor. *
2061 ************************************************************************/
2063 typedef union ii_iprte6b_u {
2064 uint64_t ii_iprte6b_regval;
2066 uint64_t i_rsvd_1 : 3;
2067 uint64_t i_address : 47;
2068 uint64_t i_init : 3;
2069 uint64_t i_source : 11;
2075 /************************************************************************
2077 * There are 8 instances of this register. This register contains *
2078 * the information that the II has to remember once it has launched a *
2079 * PIO Read operation. The contents are used to form the correct *
2080 * Router Network packet and direct the Crosstalk reply to the *
2081 * appropriate processor. *
2083 ************************************************************************/
2085 typedef union ii_iprte7b_u {
2086 uint64_t ii_iprte7b_regval;
2088 uint64_t i_rsvd_1 : 3;
2089 uint64_t i_address : 47;
2090 uint64_t i_init : 3;
2091 uint64_t i_source : 11;
2096 /************************************************************************
2098 * Description: SHub II contains a feature which did not exist in *
2099 * the Hub which automatically cleans up after a Read Response *
2100 * timeout, including deallocation of the IPRTE and recovery of IBuf *
2101 * space. The inclusion of this register in SHub is for backward *
2103 * A write to this register causes an entry from the table of *
2104 * outstanding PIO Read Requests to be freed and returned to the *
2105 * stack of free entries. This register is used in handling the *
2106 * timeout errors that result in a PIO Reply never returning from *
2108 * Note that this register does not affect the contents of the IPRTE *
2109 * registers. The Valid bits in those registers have to be *
2110 * specifically turned off by software. *
2112 ************************************************************************/
2114 typedef union ii_ipdr_u {
2115 uint64_t ii_ipdr_regval;
2118 uint64_t i_rsvd_1 : 1;
2120 uint64_t i_init_rpcnt : 1;
2121 uint64_t i_rsvd : 58;
2126 /************************************************************************
2128 * A write to this register causes a CRB entry to be returned to the *
2129 * queue of free CRBs. The entry should have previously been cleared *
2130 * (mark bit) via backdoor access to the pertinent CRB entry. This *
2131 * register is used in the last step of handling the errors that are *
2132 * captured and marked in CRB entries. Briefly: 1) first error for *
2133 * DMA write from a particular device, and first error for a *
2134 * particular BTE stream, lead to a marked CRB entry, and processor *
2135 * interrupt, 2) software reads the error information captured in the *
2136 * CRB entry, and presumably takes some corrective action, 3) *
2137 * software clears the mark bit, and finally 4) software writes to *
2138 * the ICDR register to return the CRB entry to the list of free CRB *
2141 ************************************************************************/
2143 typedef union ii_icdr_u {
2144 uint64_t ii_icdr_regval;
2146 uint64_t i_crb_num : 4;
2148 uint64_t i_rsvd : 59;
2153 /************************************************************************
2155 * This register provides debug access to two FIFOs inside of II. *
2156 * Both IOQ_MAX* fields of this register contain the instantaneous *
2157 * depth (in units of the number of available entries) of the *
2158 * associated IOQ FIFO. A read of this register will return the *
2159 * number of free entries on each FIFO at the time of the read. So *
2160 * when a FIFO is idle, the associated field contains the maximum *
2161 * depth of the FIFO. This register is writable for debug reasons *
2162 * and is intended to be written with the maximum desired FIFO depth *
2163 * while the FIFO is idle. Software must assure that II is idle when *
2164 * this register is written. If there are any active entries in any *
2165 * of these FIFOs when this register is written, the results are *
2168 ************************************************************************/
2170 typedef union ii_ifdr_u {
2171 uint64_t ii_ifdr_regval;
2173 uint64_t i_ioq_max_rq : 7;
2174 uint64_t i_set_ioq_rq : 1;
2175 uint64_t i_ioq_max_rp : 7;
2176 uint64_t i_set_ioq_rp : 1;
2177 uint64_t i_rsvd : 48;
2182 /************************************************************************
2184 * This register allows the II to become sluggish in removing *
2185 * messages from its inbound queue (IIQ). This will cause messages to *
2186 * back up in either virtual channel. Disabling the "molasses" mode *
2187 * subsequently allows the II to be tested under stress. In the *
2188 * sluggish ("Molasses") mode, the localized effects of congestion *
2189 * can be observed. *
2191 ************************************************************************/
2193 typedef union ii_iiap_u {
2194 uint64_t ii_iiap_regval;
2196 uint64_t i_rq_mls : 6;
2197 uint64_t i_rsvd_1 : 2;
2198 uint64_t i_rp_mls : 6;
2199 uint64_t i_rsvd : 50;
2204 /************************************************************************
2206 * This register allows several parameters of CRB operation to be *
2207 * set. Note that writing to this register can have catastrophic side *
2208 * effects, if the CRB is not quiescent, i.e. if the CRB is *
2209 * processing protocol messages when the write occurs. *
2211 ************************************************************************/
2213 typedef union ii_icmr_u {
2214 uint64_t ii_icmr_regval;
2216 uint64_t i_sp_msg : 1;
2217 uint64_t i_rd_hdr : 1;
2218 uint64_t i_rsvd_4 : 2;
2219 uint64_t i_c_cnt : 4;
2220 uint64_t i_rsvd_3 : 4;
2221 uint64_t i_clr_rqpd : 1;
2222 uint64_t i_clr_rppd : 1;
2223 uint64_t i_rsvd_2 : 2;
2224 uint64_t i_fc_cnt : 4;
2225 uint64_t i_crb_vld : 15;
2226 uint64_t i_crb_mark : 15;
2227 uint64_t i_rsvd_1 : 2;
2228 uint64_t i_precise : 1;
2229 uint64_t i_rsvd : 11;
2234 /************************************************************************
2236 * This register allows control of the table portion of the CRB *
2237 * logic via software. Control operations from this register have *
2238 * priority over all incoming Crosstalk or BTE requests. *
2240 ************************************************************************/
2242 typedef union ii_iccr_u {
2243 uint64_t ii_iccr_regval;
2245 uint64_t i_crb_num : 4;
2246 uint64_t i_rsvd_1 : 4;
2248 uint64_t i_pending : 1;
2249 uint64_t i_rsvd : 47;
2254 /************************************************************************
2256 * This register allows the maximum timeout value to be programmed. *
2258 ************************************************************************/
2260 typedef union ii_icto_u {
2261 uint64_t ii_icto_regval;
2263 uint64_t i_timeout : 8;
2264 uint64_t i_rsvd : 56;
2269 /************************************************************************
2271 * This register allows the timeout prescalar to be programmed. An *
2272 * internal counter is associated with this register. When the *
2273 * internal counter reaches the value of the PRESCALE field, the *
2274 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
2275 * field). The internal counter resets to zero, and then continues *
2278 ************************************************************************/
2280 typedef union ii_ictp_u {
2281 uint64_t ii_ictp_regval;
2283 uint64_t i_prescale : 24;
2284 uint64_t i_rsvd : 40;
2289 /************************************************************************
2291 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2292 * used for Crosstalk operations (both cacheline and partial *
2293 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2294 * registers (_A to _E) are required to read and write each entry. *
2295 * The CRB Entry registers can be conceptualized as rows and columns *
2296 * (illustrated in the table above). Each row contains the 4 *
2297 * registers required for a single CRB Entry. The first doubleword *
2298 * (column) for each entry is labeled A, and the second doubleword *
2299 * (higher address) is labeled B, the third doubleword is labeled C, *
2300 * the fourth doubleword is labeled D and the fifth doubleword is *
2301 * labeled E. All CRB entries have their addresses on a quarter *
2302 * cacheline aligned boundary. *
2303 * Upon reset, only the following fields are initialized: valid *
2304 * (VLD), priority count, timeout, timeout valid, and context valid. *
2305 * All other bits should be cleared by software before use (after *
2306 * recovering any potential error state from before the reset). *
2307 * The following four tables summarize the format for the four *
2308 * registers that are used for each ICRB# Entry. *
2310 ************************************************************************/
2312 typedef union ii_icrb0_a_u {
2313 uint64_t ii_icrb0_a_regval;
2315 uint64_t ia_iow : 1;
2316 uint64_t ia_vld : 1;
2317 uint64_t ia_addr : 47;
2318 uint64_t ia_tnum : 5;
2319 uint64_t ia_sidn : 4;
2320 uint64_t ia_rsvd : 6;
2325 /************************************************************************
2327 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2328 * used for Crosstalk operations (both cacheline and partial *
2329 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2330 * registers (_A to _E) are required to read and write each entry. *
2332 ************************************************************************/
2334 typedef union ii_icrb0_b_u {
2335 uint64_t ii_icrb0_b_regval;
2337 uint64_t ib_xt_err : 1;
2338 uint64_t ib_mark : 1;
2339 uint64_t ib_ln_uce : 1;
2340 uint64_t ib_errcode : 3;
2341 uint64_t ib_error : 1;
2342 uint64_t ib_stall__bte_1 : 1;
2343 uint64_t ib_stall__bte_0 : 1;
2344 uint64_t ib_stall__intr : 1;
2345 uint64_t ib_stall_ib : 1;
2346 uint64_t ib_intvn : 1;
2348 uint64_t ib_hold : 1;
2349 uint64_t ib_ack : 1;
2350 uint64_t ib_resp : 1;
2351 uint64_t ib_ack_cnt : 11;
2352 uint64_t ib_rsvd : 7;
2353 uint64_t ib_exc : 5;
2354 uint64_t ib_init : 3;
2355 uint64_t ib_imsg : 8;
2356 uint64_t ib_imsgtype : 2;
2357 uint64_t ib_use_old : 1;
2358 uint64_t ib_rsvd_1 : 11;
2363 /************************************************************************
2365 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2366 * used for Crosstalk operations (both cacheline and partial *
2367 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2368 * registers (_A to _E) are required to read and write each entry. *
2370 ************************************************************************/
2372 typedef union ii_icrb0_c_u {
2373 uint64_t ii_icrb0_c_regval;
2375 uint64_t ic_source : 15;
2376 uint64_t ic_size : 2;
2378 uint64_t ic_bte_num : 1;
2379 uint64_t ic_gbr : 1;
2380 uint64_t ic_resprqd : 1;
2382 uint64_t ic_suppl : 15;
2383 uint64_t ic_rsvd : 27;
2388 /************************************************************************
2390 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2391 * used for Crosstalk operations (both cacheline and partial *
2392 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2393 * registers (_A to _E) are required to read and write each entry. *
2395 ************************************************************************/
2397 typedef union ii_icrb0_d_u {
2398 uint64_t ii_icrb0_d_regval;
2400 uint64_t id_pa_be : 43;
2401 uint64_t id_bte_op : 1;
2402 uint64_t id_pr_psc : 4;
2403 uint64_t id_pr_cnt : 4;
2404 uint64_t id_sleep : 1;
2405 uint64_t id_rsvd : 11;
2410 /************************************************************************
2412 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2413 * used for Crosstalk operations (both cacheline and partial *
2414 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2415 * registers (_A to _E) are required to read and write each entry. *
2417 ************************************************************************/
2419 typedef union ii_icrb0_e_u {
2420 uint64_t ii_icrb0_e_regval;
2422 uint64_t ie_timeout : 8;
2423 uint64_t ie_context : 15;
2424 uint64_t ie_rsvd : 1;
2425 uint64_t ie_tvld : 1;
2426 uint64_t ie_cvld : 1;
2427 uint64_t ie_rsvd_0 : 38;
2432 /************************************************************************
2434 * This register contains the lower 64 bits of the header of the *
2435 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2436 * register is set. *
2438 ************************************************************************/
2440 typedef union ii_icsml_u {
2441 uint64_t ii_icsml_regval;
2443 uint64_t i_tt_addr : 47;
2444 uint64_t i_newsuppl_ex : 14;
2445 uint64_t i_reserved : 2;
2446 uint64_t i_overflow : 1;
2451 /************************************************************************
2453 * This register contains the middle 64 bits of the header of the *
2454 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2455 * register is set. *
2457 ************************************************************************/
2459 typedef union ii_icsmm_u {
2460 uint64_t ii_icsmm_regval;
2462 uint64_t i_tt_ack_cnt : 11;
2463 uint64_t i_reserved : 53;
2468 /************************************************************************
2470 * This register contains the microscopic state, all the inputs to *
2471 * the protocol table, captured with the spurious message. Valid when *
2472 * the SP_MSG bit in the ICMR register is set. *
2474 ************************************************************************/
2476 typedef union ii_icsmh_u {
2477 uint64_t ii_icsmh_regval;
2479 uint64_t i_tt_vld : 1;
2480 uint64_t i_xerr : 1;
2481 uint64_t i_ft_cwact_o : 1;
2482 uint64_t i_ft_wact_o : 1;
2483 uint64_t i_ft_active_o : 1;
2484 uint64_t i_sync : 1;
2485 uint64_t i_mnusg : 1;
2486 uint64_t i_mnusz : 1;
2487 uint64_t i_plusz : 1;
2488 uint64_t i_plusg : 1;
2489 uint64_t i_tt_exc : 5;
2490 uint64_t i_tt_wb : 1;
2491 uint64_t i_tt_hold : 1;
2492 uint64_t i_tt_ack : 1;
2493 uint64_t i_tt_resp : 1;
2494 uint64_t i_tt_intvn : 1;
2495 uint64_t i_g_stall_bte1 : 1;
2496 uint64_t i_g_stall_bte0 : 1;
2497 uint64_t i_g_stall_il : 1;
2498 uint64_t i_g_stall_ib : 1;
2499 uint64_t i_tt_imsg : 8;
2500 uint64_t i_tt_imsgtype : 2;
2501 uint64_t i_tt_use_old : 1;
2502 uint64_t i_tt_respreqd : 1;
2503 uint64_t i_tt_bte_num : 1;
2505 uint64_t i_match : 1;
2506 uint64_t i_rpcnt_lt_34 : 1;
2507 uint64_t i_rpcnt_ge_34 : 1;
2508 uint64_t i_rpcnt_lt_18 : 1;
2509 uint64_t i_rpcnt_ge_18 : 1;
2510 uint64_t i_rpcnt_lt_2 : 1;
2511 uint64_t i_rpcnt_ge_2 : 1;
2512 uint64_t i_rqcnt_lt_18 : 1;
2513 uint64_t i_rqcnt_ge_18 : 1;
2514 uint64_t i_rqcnt_lt_2 : 1;
2515 uint64_t i_rqcnt_ge_2 : 1;
2516 uint64_t i_tt_device : 7;
2517 uint64_t i_tt_init : 3;
2518 uint64_t i_reserved : 5;
2523 /************************************************************************
2525 * The Shub DEBUG unit provides a 3-bit selection signal to the *
2526 * II core and a 3-bit selection signal to the fsbclk domain in the II *
2529 ************************************************************************/
2531 typedef union ii_idbss_u {
2532 uint64_t ii_idbss_regval;
2534 uint64_t i_iioclk_core_submenu : 3;
2535 uint64_t i_rsvd : 5;
2536 uint64_t i_fsbclk_wrapper_submenu : 3;
2537 uint64_t i_rsvd_1 : 5;
2538 uint64_t i_iioclk_menu : 5;
2539 uint64_t i_rsvd_2 : 43;
2544 /************************************************************************
2546 * Description: This register is used to set up the length for a *
2547 * transfer and then to monitor the progress of that transfer. This *
2548 * register needs to be initialized before a transfer is started. A *
2549 * legitimate write to this register will set the Busy bit, clear the *
2550 * Error bit, and initialize the length to the value desired. *
2551 * While the transfer is in progress, hardware will decrement the *
2552 * length field with each successful block that is copied. Once the *
2553 * transfer completes, hardware will clear the Busy bit. The length *
2554 * field will also contain the number of cache lines left to be *
2557 ************************************************************************/
2559 typedef union ii_ibls0_u {
2560 uint64_t ii_ibls0_regval;
2562 uint64_t i_length : 16;
2563 uint64_t i_error : 1;
2564 uint64_t i_rsvd_1 : 3;
2565 uint64_t i_busy : 1;
2566 uint64_t i_rsvd : 43;
2571 /************************************************************************
2573 * This register should be loaded before a transfer is started. The *
2574 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2575 * address as described in Section 1.3, Figure2 and Figure3. Since *
2576 * the bottom 7 bits of the address are always taken to be zero, BTE *
2577 * transfers are always cacheline-aligned. *
2579 ************************************************************************/
2581 typedef union ii_ibsa0_u {
2582 uint64_t ii_ibsa0_regval;
2584 uint64_t i_rsvd_1 : 7;
2585 uint64_t i_addr : 42;
2586 uint64_t i_rsvd : 15;
2591 /************************************************************************
2593 * This register should be loaded before a transfer is started. The *
2594 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2595 * address as described in Section 1.3, Figure2 and Figure3. Since *
2596 * the bottom 7 bits of the address are always taken to be zero, BTE *
2597 * transfers are always cacheline-aligned. *
2599 ************************************************************************/
2601 typedef union ii_ibda0_u {
2602 uint64_t ii_ibda0_regval;
2604 uint64_t i_rsvd_1 : 7;
2605 uint64_t i_addr : 42;
2606 uint64_t i_rsvd : 15;
2611 /************************************************************************
2613 * Writing to this register sets up the attributes of the transfer *
2614 * and initiates the transfer operation. Reading this register has *
2615 * the side effect of terminating any transfer in progress. Note: *
2616 * stopping a transfer midstream could have an adverse impact on the *
2617 * other BTE. If a BTE stream has to be stopped (due to error *
2618 * handling for example), both BTE streams should be stopped and *
2619 * their transfers discarded. *
2621 ************************************************************************/
2623 typedef union ii_ibct0_u {
2624 uint64_t ii_ibct0_regval;
2626 uint64_t i_zerofill : 1;
2627 uint64_t i_rsvd_2 : 3;
2628 uint64_t i_notify : 1;
2629 uint64_t i_rsvd_1 : 3;
2630 uint64_t i_poison : 1;
2631 uint64_t i_rsvd : 55;
2636 /************************************************************************
2638 * This register contains the address to which the WINV is sent. *
2639 * This address has to be cache line aligned. *
2641 ************************************************************************/
2643 typedef union ii_ibna0_u {
2644 uint64_t ii_ibna0_regval;
2646 uint64_t i_rsvd_1 : 7;
2647 uint64_t i_addr : 42;
2648 uint64_t i_rsvd : 15;
2653 /************************************************************************
2655 * This register contains the programmable level as well as the node *
2656 * ID and PI unit of the processor to which the interrupt will be *
2659 ************************************************************************/
2661 typedef union ii_ibia0_u {
2662 uint64_t ii_ibia0_regval;
2664 uint64_t i_rsvd_2 : 1;
2665 uint64_t i_node_id : 11;
2666 uint64_t i_rsvd_1 : 4;
2667 uint64_t i_level : 7;
2668 uint64_t i_rsvd : 41;
2673 /************************************************************************
2675 * Description: This register is used to set up the length for a *
2676 * transfer and then to monitor the progress of that transfer. This *
2677 * register needs to be initialized before a transfer is started. A *
2678 * legitimate write to this register will set the Busy bit, clear the *
2679 * Error bit, and initialize the length to the value desired. *
2680 * While the transfer is in progress, hardware will decrement the *
2681 * length field with each successful block that is copied. Once the *
2682 * transfer completes, hardware will clear the Busy bit. The length *
2683 * field will also contain the number of cache lines left to be *
2686 ************************************************************************/
2688 typedef union ii_ibls1_u {
2689 uint64_t ii_ibls1_regval;
2691 uint64_t i_length : 16;
2692 uint64_t i_error : 1;
2693 uint64_t i_rsvd_1 : 3;
2694 uint64_t i_busy : 1;
2695 uint64_t i_rsvd : 43;
2700 /************************************************************************
2702 * This register should be loaded before a transfer is started. The *
2703 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2704 * address as described in Section 1.3, Figure2 and Figure3. Since *
2705 * the bottom 7 bits of the address are always taken to be zero, BTE *
2706 * transfers are always cacheline-aligned. *
2708 ************************************************************************/
2710 typedef union ii_ibsa1_u {
2711 uint64_t ii_ibsa1_regval;
2713 uint64_t i_rsvd_1 : 7;
2714 uint64_t i_addr : 33;
2715 uint64_t i_rsvd : 24;
2720 /************************************************************************
2722 * This register should be loaded before a transfer is started. The *
2723 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2724 * address as described in Section 1.3, Figure2 and Figure3. Since *
2725 * the bottom 7 bits of the address are always taken to be zero, BTE *
2726 * transfers are always cacheline-aligned. *
2728 ************************************************************************/
2730 typedef union ii_ibda1_u {
2731 uint64_t ii_ibda1_regval;
2733 uint64_t i_rsvd_1 : 7;
2734 uint64_t i_addr : 33;
2735 uint64_t i_rsvd : 24;
2740 /************************************************************************
2742 * Writing to this register sets up the attributes of the transfer *
2743 * and initiates the transfer operation. Reading this register has *
2744 * the side effect of terminating any transfer in progress. Note: *
2745 * stopping a transfer midstream could have an adverse impact on the *
2746 * other BTE. If a BTE stream has to be stopped (due to error *
2747 * handling for example), both BTE streams should be stopped and *
2748 * their transfers discarded. *
2750 ************************************************************************/
2752 typedef union ii_ibct1_u {
2753 uint64_t ii_ibct1_regval;
2755 uint64_t i_zerofill : 1;
2756 uint64_t i_rsvd_2 : 3;
2757 uint64_t i_notify : 1;
2758 uint64_t i_rsvd_1 : 3;
2759 uint64_t i_poison : 1;
2760 uint64_t i_rsvd : 55;
2765 /************************************************************************
2767 * This register contains the address to which the WINV is sent. *
2768 * This address has to be cache line aligned. *
2770 ************************************************************************/
2772 typedef union ii_ibna1_u {
2773 uint64_t ii_ibna1_regval;
2775 uint64_t i_rsvd_1 : 7;
2776 uint64_t i_addr : 33;
2777 uint64_t i_rsvd : 24;
2782 /************************************************************************
2784 * This register contains the programmable level as well as the node *
2785 * ID and PI unit of the processor to which the interrupt will be *
2788 ************************************************************************/
2790 typedef union ii_ibia1_u {
2791 uint64_t ii_ibia1_regval;
2793 uint64_t i_pi_id : 1;
2794 uint64_t i_node_id : 8;
2795 uint64_t i_rsvd_1 : 7;
2796 uint64_t i_level : 7;
2797 uint64_t i_rsvd : 41;
2802 /************************************************************************
2804 * This register defines the resources that feed information into *
2805 * the two performance counters located in the IO Performance *
2806 * Profiling Register. There are 17 different quantities that can be *
2807 * measured. Given these 17 different options, the two performance *
2808 * counters have 15 of them in common; menu selections 0 through 0xE *
2809 * are identical for each performance counter. As for the other two *
2810 * options, one is available from one performance counter and the *
2811 * other is available from the other performance counter. Hence, the *
2812 * II supports all 17*16=272 possible combinations of quantities to *
2815 ************************************************************************/
2817 typedef union ii_ipcr_u {
2818 uint64_t ii_ipcr_regval;
2820 uint64_t i_ippr0_c : 4;
2821 uint64_t i_ippr1_c : 4;
2822 uint64_t i_icct : 8;
2823 uint64_t i_rsvd : 48;
2828 /************************************************************************
2832 ************************************************************************/
2834 typedef union ii_ippr_u {
2835 uint64_t ii_ippr_regval;
2837 uint64_t i_ippr0 : 32;
2838 uint64_t i_ippr1 : 32;
2844 /**************************************************************************
2846 * The following defines which were not formed into structures are *
2847 * probably indentical to another register, and the name of the *
2848 * register is provided against each of these registers. This *
2849 * information needs to be checked carefully *
2851 * IIO_ICRB1_A IIO_ICRB0_A *
2852 * IIO_ICRB1_B IIO_ICRB0_B *
2853 * IIO_ICRB1_C IIO_ICRB0_C *
2854 * IIO_ICRB1_D IIO_ICRB0_D *
2855 * IIO_ICRB1_E IIO_ICRB0_E *
2856 * IIO_ICRB2_A IIO_ICRB0_A *
2857 * IIO_ICRB2_B IIO_ICRB0_B *
2858 * IIO_ICRB2_C IIO_ICRB0_C *
2859 * IIO_ICRB2_D IIO_ICRB0_D *
2860 * IIO_ICRB2_E IIO_ICRB0_E *
2861 * IIO_ICRB3_A IIO_ICRB0_A *
2862 * IIO_ICRB3_B IIO_ICRB0_B *
2863 * IIO_ICRB3_C IIO_ICRB0_C *
2864 * IIO_ICRB3_D IIO_ICRB0_D *
2865 * IIO_ICRB3_E IIO_ICRB0_E *
2866 * IIO_ICRB4_A IIO_ICRB0_A *
2867 * IIO_ICRB4_B IIO_ICRB0_B *
2868 * IIO_ICRB4_C IIO_ICRB0_C *
2869 * IIO_ICRB4_D IIO_ICRB0_D *
2870 * IIO_ICRB4_E IIO_ICRB0_E *
2871 * IIO_ICRB5_A IIO_ICRB0_A *
2872 * IIO_ICRB5_B IIO_ICRB0_B *
2873 * IIO_ICRB5_C IIO_ICRB0_C *
2874 * IIO_ICRB5_D IIO_ICRB0_D *
2875 * IIO_ICRB5_E IIO_ICRB0_E *
2876 * IIO_ICRB6_A IIO_ICRB0_A *
2877 * IIO_ICRB6_B IIO_ICRB0_B *
2878 * IIO_ICRB6_C IIO_ICRB0_C *
2879 * IIO_ICRB6_D IIO_ICRB0_D *
2880 * IIO_ICRB6_E IIO_ICRB0_E *
2881 * IIO_ICRB7_A IIO_ICRB0_A *
2882 * IIO_ICRB7_B IIO_ICRB0_B *
2883 * IIO_ICRB7_C IIO_ICRB0_C *
2884 * IIO_ICRB7_D IIO_ICRB0_D *
2885 * IIO_ICRB7_E IIO_ICRB0_E *
2886 * IIO_ICRB8_A IIO_ICRB0_A *
2887 * IIO_ICRB8_B IIO_ICRB0_B *
2888 * IIO_ICRB8_C IIO_ICRB0_C *
2889 * IIO_ICRB8_D IIO_ICRB0_D *
2890 * IIO_ICRB8_E IIO_ICRB0_E *
2891 * IIO_ICRB9_A IIO_ICRB0_A *
2892 * IIO_ICRB9_B IIO_ICRB0_B *
2893 * IIO_ICRB9_C IIO_ICRB0_C *
2894 * IIO_ICRB9_D IIO_ICRB0_D *
2895 * IIO_ICRB9_E IIO_ICRB0_E *
2896 * IIO_ICRBA_A IIO_ICRB0_A *
2897 * IIO_ICRBA_B IIO_ICRB0_B *
2898 * IIO_ICRBA_C IIO_ICRB0_C *
2899 * IIO_ICRBA_D IIO_ICRB0_D *
2900 * IIO_ICRBA_E IIO_ICRB0_E *
2901 * IIO_ICRBB_A IIO_ICRB0_A *
2902 * IIO_ICRBB_B IIO_ICRB0_B *
2903 * IIO_ICRBB_C IIO_ICRB0_C *
2904 * IIO_ICRBB_D IIO_ICRB0_D *
2905 * IIO_ICRBB_E IIO_ICRB0_E *
2906 * IIO_ICRBC_A IIO_ICRB0_A *
2907 * IIO_ICRBC_B IIO_ICRB0_B *
2908 * IIO_ICRBC_C IIO_ICRB0_C *
2909 * IIO_ICRBC_D IIO_ICRB0_D *
2910 * IIO_ICRBC_E IIO_ICRB0_E *
2911 * IIO_ICRBD_A IIO_ICRB0_A *
2912 * IIO_ICRBD_B IIO_ICRB0_B *
2913 * IIO_ICRBD_C IIO_ICRB0_C *
2914 * IIO_ICRBD_D IIO_ICRB0_D *
2915 * IIO_ICRBD_E IIO_ICRB0_E *
2916 * IIO_ICRBE_A IIO_ICRB0_A *
2917 * IIO_ICRBE_B IIO_ICRB0_B *
2918 * IIO_ICRBE_C IIO_ICRB0_C *
2919 * IIO_ICRBE_D IIO_ICRB0_D *
2920 * IIO_ICRBE_E IIO_ICRB0_E *
2922 **************************************************************************/
2926 * Slightly friendlier names for some common registers.
2928 #define IIO_WIDGET IIO_WID /* Widget identification */
2929 #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
2930 #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
2931 #define IIO_PROTECT IIO_ILAPR /* IO interface protection */
2932 #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
2933 #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
2934 #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
2935 #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
2936 #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
2937 #define IIO_LLP_LOG IIO_ILLR /* LLP log */
2938 #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
2939 #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
2940 #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
2941 #define IIO_IGFX_0 IIO_IGFX0
2942 #define IIO_IGFX_1 IIO_IGFX1
2943 #define IIO_IBCT_0 IIO_IBCT0
2944 #define IIO_IBCT_1 IIO_IBCT1
2945 #define IIO_IBLS_0 IIO_IBLS0
2946 #define IIO_IBLS_1 IIO_IBLS1
2947 #define IIO_IBSA_0 IIO_IBSA0
2948 #define IIO_IBSA_1 IIO_IBSA1
2949 #define IIO_IBDA_0 IIO_IBDA0
2950 #define IIO_IBDA_1 IIO_IBDA1
2951 #define IIO_IBNA_0 IIO_IBNA0
2952 #define IIO_IBNA_1 IIO_IBNA1
2953 #define IIO_IBIA_0 IIO_IBIA0
2954 #define IIO_IBIA_1 IIO_IBIA1
2955 #define IIO_IOPRB_0 IIO_IPRB0
2957 #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
2958 #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
2959 #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
2960 #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
2961 #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
2963 #define IIO_NUM_IPRBS (9)
2965 #define IIO_LLP_CSR_IS_UP 0x00002000
2966 #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
2967 #define IIO_LLP_CSR_LLP_STAT_SHFT 12
2969 #define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
2970 #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
2972 /* key to IIO_PROTECT_OVRRD */
2973 #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
2975 /* BTE register names */
2976 #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
2977 #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
2978 #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
2979 #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
2980 #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
2981 #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
2982 #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
2983 #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
2985 /* BTE register offsets from base */
2986 #define BTEOFF_STAT 0
2987 #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
2988 #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
2989 #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
2990 #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
2991 #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
2994 /* names used in shub diags */
2995 #define IIO_BASE_BTE0 IIO_IBLS_0
2996 #define IIO_BASE_BTE1 IIO_IBLS_1
2999 * Macro which takes the widget number, and returns the
3000 * IO PRB address of that widget.
3001 * value _x is expected to be a widget number in the range
3004 #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
3006 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
3009 /* GFX Flow Control Node/Widget Register */
3010 #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
3011 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
3012 #define IIO_IGFX_W_NUM_SHIFT 0
3013 #define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
3014 #define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
3015 #define IIO_IGFX_PI_NUM_SHIFT 4
3016 #define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
3017 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
3018 #define IIO_IGFX_N_NUM_SHIFT 5
3019 #define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
3020 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
3021 #define IIO_IGFX_P_NUM_SHIFT 16
3022 #define IIO_IGFX_INIT(widget, pi, node, cpu) (\
3023 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
3024 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \
3025 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
3026 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
3029 /* Scratch registers (all bits available) */
3030 #define IIO_SCRATCH_REG0 IIO_ISCR0
3031 #define IIO_SCRATCH_REG1 IIO_ISCR1
3032 #define IIO_SCRATCH_MASK 0xffffffffffffffffUL
3034 #define IIO_SCRATCH_BIT0_0 0x0000000000000001UL
3035 #define IIO_SCRATCH_BIT0_1 0x0000000000000002UL
3036 #define IIO_SCRATCH_BIT0_2 0x0000000000000004UL
3037 #define IIO_SCRATCH_BIT0_3 0x0000000000000008UL
3038 #define IIO_SCRATCH_BIT0_4 0x0000000000000010UL
3039 #define IIO_SCRATCH_BIT0_5 0x0000000000000020UL
3040 #define IIO_SCRATCH_BIT0_6 0x0000000000000040UL
3041 #define IIO_SCRATCH_BIT0_7 0x0000000000000080UL
3042 #define IIO_SCRATCH_BIT0_8 0x0000000000000100UL
3043 #define IIO_SCRATCH_BIT0_9 0x0000000000000200UL
3044 #define IIO_SCRATCH_BIT0_A 0x0000000000000400UL
3046 #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL
3047 #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL
3048 /* IO Translation Table Entries */
3049 #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
3050 /* Hw manuals number them 1..7! */
3052 * IIO_IMEM Register fields.
3054 #define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */
3055 #define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */
3056 #define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */
3059 * As a permanent workaround for a bug in the PI side of the shub, we've
3060 * redefined big window 7 as small window 0.
3061 XXX does this still apply for SN1??
3063 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
3066 * Use the top big window as a surrogate for the first small window
3068 #define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
3070 #define ILCSR_WARM_RESET 0x100
3073 * CRB manipulation macros
3074 * The CRB macros are slightly complicated, since there are up to
3075 * four registers associated with each CRB entry.
3077 #define IIO_NUM_CRBS 15 /* Number of CRBs */
3078 #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
3079 #define IIO_ICRB_OFFSET 8
3080 #define IIO_ICRB_0 IIO_ICRB0_A
3081 #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
3082 /* XXX - This is now tuneable:
3083 #define IIO_FIRST_PC_ENTRY 12
3086 #define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
3087 #define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
3088 #define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
3089 #define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
3090 #define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
3092 #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
3095 * values for "ecode" field
3097 #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
3098 #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
3099 #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
3100 * e.g. WINV to a Read only line. */
3101 #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
3102 #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
3103 #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
3104 #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
3105 #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
3108 * Values for field imsgtype
3110 #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
3111 #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
3112 #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
3113 #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
3116 * values for field initiator.
3118 #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
3119 #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
3120 #define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
3121 #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
3122 #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
3125 * Number of credits Hub widget has while sending req/response to
3127 * Value of 3 is required by Xbow 1.1
3128 * We may be able to increase this to 4 with Xbow 1.2.
3130 #define HUBII_XBOW_CREDIT 3
3131 #define HUBII_XBOW_REV2_CREDIT 4
3134 * Number of credits that xtalk devices should use when communicating
3135 * with a SHub (depth of SHub's queue).
3137 #define HUB_CREDIT 4
3140 * Some IIO_PRB fields
3142 #define IIO_PRB_MULTI_ERR (1LL << 63)
3143 #define IIO_PRB_SPUR_RD (1LL << 51)
3144 #define IIO_PRB_SPUR_WR (1LL << 50)
3145 #define IIO_PRB_RD_TO (1LL << 49)
3146 #define IIO_PRB_ERROR (1LL << 48)
3148 /*************************************************************************
3150 Some of the IIO field masks and shifts are defined here.
3151 This is in order to maintain compatibility in SN0 and SN1 code
3153 **************************************************************************/
3156 * ICMR register fields
3157 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
3161 #define IIO_ICMR_CRB_VLD_SHFT 20
3162 #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
3164 #define IIO_ICMR_FC_CNT_SHFT 16
3165 #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
3167 #define IIO_ICMR_C_CNT_SHFT 4
3168 #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
3170 #define IIO_ICMR_PRECISE (1UL << 52)
3171 #define IIO_ICMR_CLR_RPPD (1UL << 13)
3172 #define IIO_ICMR_CLR_RQPD (1UL << 12)
3175 * IIO PIO Deallocation register field masks : (IIO_IPDR)
3176 XXX present but not needed in bedrock? See the manual.
3178 #define IIO_IPDR_PND (1 << 4)
3181 * IIO CRB deallocation register field masks: (IIO_ICDR)
3183 #define IIO_ICDR_PND (1 << 4)
3186 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
3188 #define IBLS_BUSY (0x1UL << 20)
3189 #define IBLS_ERROR_SHFT 16
3190 #define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT)
3191 #define IBLS_LENGTH_MASK 0xffff
3194 * IO BTE Control/Terminate register (IBCT) register bit field definitions
3196 #define IBCT_POISON (0x1UL << 8)
3197 #define IBCT_NOTIFY (0x1UL << 4)
3198 #define IBCT_ZFIL_MODE (0x1UL << 0)
3201 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
3203 #define IIEPH1_VALID (1UL << 44)
3204 #define IIEPH1_OVERRUN (1UL << 40)
3205 #define IIEPH1_ERR_TYPE_SHFT 32
3206 #define IIEPH1_ERR_TYPE_MASK 0xf
3207 #define IIEPH1_SOURCE_SHFT 20
3208 #define IIEPH1_SOURCE_MASK 11
3209 #define IIEPH1_SUPPL_SHFT 8
3210 #define IIEPH1_SUPPL_MASK 11
3211 #define IIEPH1_CMD_SHFT 0
3212 #define IIEPH1_CMD_MASK 7
3214 #define IIEPH2_TAIL (1UL << 40)
3215 #define IIEPH2_ADDRESS_SHFT 0
3216 #define IIEPH2_ADDRESS_MASK 38
3218 #define IIEPH1_ERR_SHORT_REQ 2
3219 #define IIEPH1_ERR_SHORT_REPLY 3
3220 #define IIEPH1_ERR_LONG_REQ 4
3221 #define IIEPH1_ERR_LONG_REPLY 5
3224 * IO Error Clear register bit field definitions
3226 #define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */
3227 #define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */
3228 #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
3229 #define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */
3230 #define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */
3231 #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
3232 #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
3233 #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
3234 #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
3235 #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
3236 #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
3237 #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
3238 #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
3239 #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
3240 #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
3243 * IIO CRB control register Fields: IIO_ICCR
3245 #define IIO_ICCR_PENDING (0x10000)
3246 #define IIO_ICCR_CMD_MASK (0xFF)
3247 #define IIO_ICCR_CMD_SHFT (7)
3248 #define IIO_ICCR_CMD_NOP (0x0) /* No Op */
3249 #define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
3250 #define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
3251 #define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
3254 #define IIO_ICCR_CMD_FLUSH (0x800)
3258 * CRB Register description.
3260 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3261 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3262 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3263 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3264 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3266 * Many of the fields in CRB are status bits used by hardware
3267 * for implementation of the protocol. It's very dangerous to
3268 * mess around with the CRB registers.
3270 * It's OK to read the CRB registers and try to make sense out of the
3273 * Updating CRB requires all activities in Hub IIO to be quiesced.
3274 * otherwise, a write to CRB could corrupt other CRB entries.
3275 * CRBs are here only as a back door peek to shub IIO's status.
3276 * Quiescing implies no dmas no PIOs
3277 * either directly from the cpu or from sn0net.
3278 * this is not something that can be done easily. So, AVOID updating
3283 * Easy access macros for CRBs, all 5 registers (A-E)
3285 typedef ii_icrb0_a_u_t icrba_t;
3286 #define a_sidn ii_icrb0_a_fld_s.ia_sidn
3287 #define a_tnum ii_icrb0_a_fld_s.ia_tnum
3288 #define a_addr ii_icrb0_a_fld_s.ia_addr
3289 #define a_valid ii_icrb0_a_fld_s.ia_vld
3290 #define a_iow ii_icrb0_a_fld_s.ia_iow
3291 #define a_regvalue ii_icrb0_a_regval
3293 typedef ii_icrb0_b_u_t icrbb_t;
3294 #define b_use_old ii_icrb0_b_fld_s.ib_use_old
3295 #define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
3296 #define b_imsg ii_icrb0_b_fld_s.ib_imsg
3297 #define b_initiator ii_icrb0_b_fld_s.ib_init
3298 #define b_exc ii_icrb0_b_fld_s.ib_exc
3299 #define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt
3300 #define b_resp ii_icrb0_b_fld_s.ib_resp
3301 #define b_ack ii_icrb0_b_fld_s.ib_ack
3302 #define b_hold ii_icrb0_b_fld_s.ib_hold
3303 #define b_wb ii_icrb0_b_fld_s.ib_wb
3304 #define b_intvn ii_icrb0_b_fld_s.ib_intvn
3305 #define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib
3306 #define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr
3307 #define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0
3308 #define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1
3309 #define b_error ii_icrb0_b_fld_s.ib_error
3310 #define b_ecode ii_icrb0_b_fld_s.ib_errcode
3311 #define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce
3312 #define b_mark ii_icrb0_b_fld_s.ib_mark
3313 #define b_xerr ii_icrb0_b_fld_s.ib_xt_err
3314 #define b_regvalue ii_icrb0_b_regval
3316 typedef ii_icrb0_c_u_t icrbc_t;
3317 #define c_suppl ii_icrb0_c_fld_s.ic_suppl
3318 #define c_barrop ii_icrb0_c_fld_s.ic_bo
3319 #define c_doresp ii_icrb0_c_fld_s.ic_resprqd
3320 #define c_gbr ii_icrb0_c_fld_s.ic_gbr
3321 #define c_btenum ii_icrb0_c_fld_s.ic_bte_num
3322 #define c_cohtrans ii_icrb0_c_fld_s.ic_ct
3323 #define c_xtsize ii_icrb0_c_fld_s.ic_size
3324 #define c_source ii_icrb0_c_fld_s.ic_source
3325 #define c_regvalue ii_icrb0_c_regval
3328 typedef ii_icrb0_d_u_t icrbd_t;
3329 #define d_sleep ii_icrb0_d_fld_s.id_sleep
3330 #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
3331 #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
3332 #define d_bteop ii_icrb0_d_fld_s.id_bte_op
3333 #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
3334 #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
3335 #define d_regvalue ii_icrb0_d_regval
3337 typedef ii_icrb0_e_u_t icrbe_t;
3338 #define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld
3339 #define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld
3340 #define icrbe_context ii_icrb0_e_fld_s.ie_context
3341 #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
3342 #define e_regvalue ii_icrb0_e_regval
3345 /* Number of widgets supported by shub */
3346 #define HUB_NUM_WIDGET 9
3347 #define HUB_WIDGET_ID_MIN 0x8
3348 #define HUB_WIDGET_ID_MAX 0xf
3350 #define HUB_WIDGET_PART_NUM 0xc120
3351 #define MAX_HUBS_PER_XBOW 2
3353 /* A few more #defines for backwards compatibility */
3354 #define iprb_t ii_iprb0_u_t
3355 #define iprb_regval ii_iprb0_regval
3356 #define iprb_mult_err ii_iprb0_fld_s.i_mult_err
3357 #define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
3358 #define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
3359 #define iprb_rd_to ii_iprb0_fld_s.i_rd_to
3360 #define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
3361 #define iprb_error ii_iprb0_fld_s.i_error
3362 #define iprb_ff ii_iprb0_fld_s.i_f
3363 #define iprb_mode ii_iprb0_fld_s.i_m
3364 #define iprb_bnakctr ii_iprb0_fld_s.i_nb
3365 #define iprb_anakctr ii_iprb0_fld_s.i_na
3366 #define iprb_xtalkctr ii_iprb0_fld_s.i_c
3368 #define LNK_STAT_WORKING 0x2 /* LLP is working */
3370 #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
3371 #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
3372 #define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */
3373 #define IIO_WSTAT_TXRETRY_SHFT (16)
3374 #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
3375 IIO_WSTAT_TXRETRY_MASK)
3377 /* Number of II perf. counters we can multiplex at once */
3379 #define IO_PERF_SETS 32
3381 /* Bit for the widget in inbound access register */
3382 #define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w))
3383 /* Bit for the widget in outbound access register */
3384 #define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w))
3386 /* NOTE: The following define assumes that we are going to get
3387 * widget numbers from 8 thru F and the device numbers within
3388 * widget from 0 thru 7.
3390 #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
3392 /* IO Interrupt Destination Register */
3393 #define IIO_IIDSR_SENT_SHIFT 28
3394 #define IIO_IIDSR_SENT_MASK 0x30000000
3395 #define IIO_IIDSR_ENB_SHIFT 24
3396 #define IIO_IIDSR_ENB_MASK 0x01000000
3397 #define IIO_IIDSR_NODE_SHIFT 9
3398 #define IIO_IIDSR_NODE_MASK 0x000ff700
3399 #define IIO_IIDSR_PI_ID_SHIFT 8
3400 #define IIO_IIDSR_PI_ID_MASK 0x00000100
3401 #define IIO_IIDSR_LVL_SHIFT 0
3402 #define IIO_IIDSR_LVL_MASK 0x000000ff
3404 /* Xtalk timeout threshhold register (IIO_IXTT) */
3405 #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
3406 #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
3407 #define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
3408 #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
3409 #define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
3410 #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
3413 * The IO LLP control status register and widget control register
3416 typedef union hubii_wcr_u {
3417 uint64_t wcr_reg_value;
3419 uint64_t wcr_widget_id: 4, /* LLP crossbar credit */
3420 wcr_tag_mode: 1, /* Tag mode */
3421 wcr_rsvd1: 8, /* Reserved */
3422 wcr_xbar_crd: 3, /* LLP crossbar credit */
3423 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
3424 wcr_dir_con: 1, /* widget direct connect */
3425 wcr_e_thresh: 5, /* elasticity threshold */
3426 wcr_rsvd: 41; /* unused */
3430 #define iwcr_dir_con wcr_fields_s.wcr_dir_con
3432 /* The structures below are defined to extract and modify the ii
3433 performance registers */
3435 /* io_perf_sel allows the caller to specify what tests will be
3438 typedef union io_perf_sel {
3439 uint64_t perf_sel_reg;
3441 uint64_t perf_ippr0 : 4,
3448 /* io_perf_cnt is to extract the count from the shub registers. Due to
3449 hardware problems there is only one counter, not two. */
3451 typedef union io_perf_cnt {
3454 uint64_t perf_cnt : 20,
3461 typedef union iprte_a {
3464 uint64_t i_rsvd_1 : 3;
3465 uint64_t i_addr : 38;
3466 uint64_t i_init : 3;
3467 uint64_t i_source : 8;
3468 uint64_t i_rsvd : 2;
3469 uint64_t i_widget : 4;
3470 uint64_t i_to_cnt : 5;
3475 #endif /* _ASM_IA64_SN_SHUBIO_H */
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