arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22
  23 #include <asm/head.h>
  24 #include <asm/system.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/oplib.h>
  29 #include <asm/iommu.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/dma.h>
  35 #include <asm/starfire.h>
  36 #include <asm/tlb.h>
  37 #include <asm/spitfire.h>
  38 #include <asm/sections.h>
  39
  40 extern void device_scan(void);
  41
  42 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
  43
  44 unsigned long *sparc64_valid_addr_bitmap;
  45
  46 /* Ugly, but necessary... -DaveM */
  47 unsigned long phys_base;
  48 unsigned long kern_base;
  49 unsigned long kern_size;
  50 unsigned long pfn_base;
  51
  52 /* This is even uglier. We have a problem where the kernel may not be
  53  * located at phys_base. However, initial __alloc_bootmem() calls need to
  54  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
  55  * those page mappings wont work. Things are ok after inherit_prom_mappings
  56  * is called though. Dave says he'll clean this up some other time.
  57  * -- BenC
  58  */
  59 static unsigned long bootmap_base;
  60
  61 /* get_new_mmu_context() uses "cache + 1".  */
  62 DEFINE_SPINLOCK(ctx_alloc_lock);
  63 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
  64 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
  65 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
  66
  67 /* References to special section boundaries */
  68 extern char  _start[], _end[];
  69
  70 /* Initial ramdisk setup */
  71 extern unsigned long sparc_ramdisk_image64;
  72 extern unsigned int sparc_ramdisk_image;
  73 extern unsigned int sparc_ramdisk_size;
  74
  75 struct page *mem_map_zero;
  76
  77 int bigkernel = 0;
  78
  79 /* XXX Tune this... */
  80 #define PGT_CACHE_LOW   25
  81 #define PGT_CACHE_HIGH  50
  82
  83 void check_pgt_cache(void)
  84 {
  85         preempt_disable();
  86         if (pgtable_cache_size > PGT_CACHE_HIGH) {
  87                 do {
  88                         if (pgd_quicklist)
  89                                 free_pgd_slow(get_pgd_fast());
  90                         if (pte_quicklist[0])
  91                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
  92                         if (pte_quicklist[1])
  93                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
  94                 } while (pgtable_cache_size > PGT_CACHE_LOW);
  95         }
  96         preempt_enable();
  97 }
  98
  99 #ifdef CONFIG_DEBUG_DCFLUSH
 100 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 101 #ifdef CONFIG_SMP
 102 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 103 #endif
 104 #endif
 105
 106 __inline__ void flush_dcache_page_impl(struct page *page)
 107 {
 108 #ifdef CONFIG_DEBUG_DCFLUSH
 109         atomic_inc(&dcpage_flushes);
 110 #endif
 111
 112 #ifdef DCACHE_ALIASING_POSSIBLE
 113         __flush_dcache_page(page_address(page),
 114                             ((tlb_type == spitfire) &&
 115                              page_mapping(page) != NULL));
 116 #else
 117         if (page_mapping(page) != NULL &&
 118             tlb_type == spitfire)
 119                 __flush_icache_page(__pa(page_address(page)));
 120 #endif
 121 }
 122
 123 #define PG_dcache_dirty         PG_arch_1
 124
 125 #define dcache_dirty_cpu(page) \
 126         (((page)->flags >> 24) & (NR_CPUS - 1UL))
 127
 128 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 129 {
 130         unsigned long mask = this_cpu;
 131         unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 132         mask = (mask << 24) | (1UL << PG_dcache_dirty);
 133         __asm__ __volatile__("1:\n\t"
 134                              "ldx       [%2], %%g7\n\t"
 135                              "and       %%g7, %1, %%g1\n\t"
 136                              "or        %%g1, %0, %%g1\n\t"
 137                              "casx      [%2], %%g7, %%g1\n\t"
 138                              "cmp       %%g7, %%g1\n\t"
 139                              "bne,pn    %%xcc, 1b\n\t"
 140                              " membar   #StoreLoad | #StoreStore"
 141                              : /* no outputs */
 142                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 143                              : "g1", "g7");
 144 }
 145
 146 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 147 {
 148         unsigned long mask = (1UL << PG_dcache_dirty);
 149
 150         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 151                              "1:\n\t"
 152                              "ldx       [%2], %%g7\n\t"
 153                              "srlx      %%g7, 24, %%g1\n\t"
 154                              "and       %%g1, %3, %%g1\n\t"
 155                              "cmp       %%g1, %0\n\t"
 156                              "bne,pn    %%icc, 2f\n\t"
 157                              " andn     %%g7, %1, %%g1\n\t"
 158                              "casx      [%2], %%g7, %%g1\n\t"
 159                              "cmp       %%g7, %%g1\n\t"
 160                              "bne,pn    %%xcc, 1b\n\t"
 161                              " membar   #StoreLoad | #StoreStore\n"
 162                              "2:"
 163                              : /* no outputs */
 164                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 165                                "i" (NR_CPUS - 1UL)
 166                              : "g1", "g7");
 167 }
 168
 169 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
 170
 171 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 172 {
 173         struct page *page;
 174         unsigned long pfn;
 175         unsigned long pg_flags;
 176
 177         pfn = pte_pfn(pte);
 178         if (pfn_valid(pfn) &&
 179             (page = pfn_to_page(pfn), page_mapping(page)) &&
 180             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 181                 int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 182                 int this_cpu = get_cpu();
 183
 184                 /* This is just to optimize away some function calls
 185                  * in the SMP case.
 186                  */
 187                 if (cpu == this_cpu)
 188                         flush_dcache_page_impl(page);
 189                 else
 190                         smp_flush_dcache_page_impl(page, cpu);
 191
 192                 clear_dcache_dirty_cpu(page, cpu);
 193
 194                 put_cpu();
 195         }
 196
 197         if (get_thread_fault_code())
 198                 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
 199                                    address, pte, get_thread_fault_code());
 200 }
 201
 202 void flush_dcache_page(struct page *page)
 203 {
 204         struct address_space *mapping = page_mapping(page);
 205         int dirty = test_bit(PG_dcache_dirty, &page->flags);
 206         int dirty_cpu = dcache_dirty_cpu(page);
 207         int this_cpu = get_cpu();
 208
 209         if (mapping && !mapping_mapped(mapping)) {
 210                 if (dirty) {
 211                         if (dirty_cpu == this_cpu)
 212                                 goto out;
 213                         smp_flush_dcache_page_impl(page, dirty_cpu);
 214                 }
 215                 set_dcache_dirty(page, this_cpu);
 216         } else {
 217                 /* We could delay the flush for the !page_mapping
 218                  * case too.  But that case is for exec env/arg
 219                  * pages and those are %99 certainly going to get
 220                  * faulted into the tlb (and thus flushed) anyways.
 221                  */
 222                 flush_dcache_page_impl(page);
 223         }
 224
 225 out:
 226         put_cpu();
 227 }
 228
 229 void flush_icache_range(unsigned long start, unsigned long end)
 230 {
 231         /* Cheetah has coherent I-cache. */
 232         if (tlb_type == spitfire) {
 233                 unsigned long kaddr;
 234
 235                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 236                         __flush_icache_page(__get_phys(kaddr));
 237         }
 238 }
 239
 240 unsigned long page_to_pfn(struct page *page)
 241 {
 242         return (unsigned long) ((page - mem_map) + pfn_base);
 243 }
 244
 245 struct page *pfn_to_page(unsigned long pfn)
 246 {
 247         return (mem_map + (pfn - pfn_base));
 248 }
 249
 250 void show_mem(void)
 251 {
 252         printk("Mem-info:\n");
 253         show_free_areas();
 254         printk("Free swap:       %6ldkB\n",
 255                nr_swap_pages << (PAGE_SHIFT-10));
 256         printk("%ld pages of RAM\n", num_physpages);
 257         printk("%d free pages\n", nr_free_pages());
 258         printk("%d pages in page table cache\n",pgtable_cache_size);
 259 }
 260
 261 void mmu_info(struct seq_file *m)
 262 {
 263         if (tlb_type == cheetah)
 264                 seq_printf(m, "MMU Type\t: Cheetah\n");
 265         else if (tlb_type == cheetah_plus)
 266                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 267         else if (tlb_type == spitfire)
 268                 seq_printf(m, "MMU Type\t: Spitfire\n");
 269         else
 270                 seq_printf(m, "MMU Type\t: ???\n");
 271
 272 #ifdef CONFIG_DEBUG_DCFLUSH
 273         seq_printf(m, "DCPageFlushes\t: %d\n",
 274                    atomic_read(&dcpage_flushes));
 275 #ifdef CONFIG_SMP
 276         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 277                    atomic_read(&dcpage_flushes_xcall));
 278 #endif /* CONFIG_SMP */
 279 #endif /* CONFIG_DEBUG_DCFLUSH */
 280 }
 281
 282 struct linux_prom_translation {
 283         unsigned long virt;
 284         unsigned long size;
 285         unsigned long data;
 286 };
 287
 288 extern unsigned long prom_boot_page;
 289 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 290 extern int prom_get_mmu_ihandle(void);
 291 extern void register_prom_callbacks(void);
 292
 293 /* Exported for SMP bootup purposes. */
 294 unsigned long kern_locked_tte_data;
 295
 296 void __init early_pgtable_allocfail(char *type)
 297 {
 298         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 299         prom_halt();
 300 }
 301
 302 #define BASE_PAGE_SIZE 8192
 303 static pmd_t *prompmd;
 304
 305 /*
 306  * Translate PROM's mapping we capture at boot time into physical address.
 307  * The second parameter is only set from prom_callback() invocations.
 308  */
 309 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 310 {
 311         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 312         pte_t *ptep;
 313         unsigned long base;
 314
 315         if (pmd_none(*pmdp)) {
 316                 if (error)
 317                         *error = 1;
 318                 return(0);
 319         }
 320         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 321         if (!pte_present(*ptep)) {
 322                 if (error)
 323                         *error = 1;
 324                 return(0);
 325         }
 326         if (error) {
 327                 *error = 0;
 328                 return(pte_val(*ptep));
 329         }
 330         base = pte_val(*ptep) & _PAGE_PADDR;
 331         return(base + (promva & (BASE_PAGE_SIZE - 1)));
 332 }
 333
 334 static void inherit_prom_mappings(void)
 335 {
 336         struct linux_prom_translation *trans;
 337         unsigned long phys_page, tte_vaddr, tte_data;
 338         void (*remap_func)(unsigned long, unsigned long, int);
 339         pmd_t *pmdp;
 340         pte_t *ptep;
 341         int node, n, i, tsz;
 342         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
 343
 344         node = prom_finddevice("/virtual-memory");
 345         n = prom_getproplen(node, "translations");
 346         if (n == 0 || n == -1) {
 347                 prom_printf("Couldn't get translation property\n");
 348                 prom_halt();
 349         }
 350         n += 5 * sizeof(struct linux_prom_translation);
 351         for (tsz = 1; tsz < n; tsz <<= 1)
 352                 /* empty */;
 353         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
 354         if (trans == NULL) {
 355                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
 356                 prom_halt();
 357         }
 358         memset(trans, 0, tsz);
 359
 360         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 361                 prom_printf("Couldn't get translation property\n");
 362                 prom_halt();
 363         }
 364         n = n / sizeof(*trans);
 365
 366         /*
 367          * The obp translations are saved based on 8k pagesize, since obp can
 368          * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
 369          * ie obp range, are handled in entry.S and do not use the vpte scheme
 370          * (see rant in inherit_locked_prom_mappings()).
 371          */
 372 #define OBP_PMD_SIZE 2048
 373         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
 374         if (prompmd == NULL)
 375                 early_pgtable_allocfail("pmd");
 376         memset(prompmd, 0, OBP_PMD_SIZE);
 377         for (i = 0; i < n; i++) {
 378                 unsigned long vaddr;
 379
 380                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
 381                         for (vaddr = trans[i].virt;
 382                              ((vaddr < trans[i].virt + trans[i].size) &&
 383                              (vaddr < HI_OBP_ADDRESS));
 384                              vaddr += BASE_PAGE_SIZE) {
 385                                 unsigned long val;
 386
 387                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
 388                                 if (pmd_none(*pmdp)) {
 389                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
 390                                                                BASE_PAGE_SIZE,
 391                                                                bootmap_base);
 392                                         if (ptep == NULL)
 393                                                 early_pgtable_allocfail("pte");
 394                                         memset(ptep, 0, BASE_PAGE_SIZE);
 395                                         pmd_set(pmdp, ptep);
 396                                 }
 397                                 ptep = (pte_t *)__pmd_page(*pmdp) +
 398                                                 ((vaddr >> 13) & 0x3ff);
 399
 400                                 val = trans[i].data;
 401
 402                                 /* Clear diag TTE bits. */
 403                                 if (tlb_type == spitfire)
 404                                         val &= ~0x0003fe0000000000UL;
 405
 406                                 set_pte_at(&init_mm, vaddr,
 407                                            ptep, __pte(val | _PAGE_MODIFIED));
 408                                 trans[i].data += BASE_PAGE_SIZE;
 409                         }
 410                 }
 411         }
 412         phys_page = __pa(prompmd);
 413         obp_iaddr_patch[0] |= (phys_page >> 10);
 414         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
 415         flushi((long)&obp_iaddr_patch[0]);
 416         obp_daddr_patch[0] |= (phys_page >> 10);
 417         obp_daddr_patch[1] |= (phys_page & 0x3ff);
 418         flushi((long)&obp_daddr_patch[0]);
 419
 420         /* Now fixup OBP's idea about where we really are mapped. */
 421         prom_printf("Remapping the kernel... ");
 422
 423         /* Spitfire Errata #32 workaround */
 424         /* NOTE: Using plain zero for the context value is
 425          *       correct here, we are not using the Linux trap
 426          *       tables yet so we should not use the special
 427          *       UltraSPARC-III+ page size encodings yet.
 428          */
 429         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 430                              "flush     %%g6"
 431                              : /* No outputs */
 432                              : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 433
 434         switch (tlb_type) {
 435         default:
 436         case spitfire:
 437                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 438                 break;
 439
 440         case cheetah:
 441         case cheetah_plus:
 442                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
 443                 break;
 444         };
 445
 446         phys_page &= _PAGE_PADDR;
 447         phys_page += ((unsigned long)&prom_boot_page -
 448                       (unsigned long)KERNBASE);
 449
 450         if (tlb_type == spitfire) {
 451                 /* Lock this into i/d tlb entry 59 */
 452                 __asm__ __volatile__(
 453                         "stxa   %%g0, [%2] %3\n\t"
 454                         "stxa   %0, [%1] %4\n\t"
 455                         "membar #Sync\n\t"
 456                         "flush  %%g6\n\t"
 457                         "stxa   %%g0, [%2] %5\n\t"
 458                         "stxa   %0, [%1] %6\n\t"
 459                         "membar #Sync\n\t"
 460                         "flush  %%g6"
 461                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 462                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 463                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
 464                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 465                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 466                         : "memory");
 467         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 468                 /* Lock this into i/d tlb-0 entry 11 */
 469                 __asm__ __volatile__(
 470                         "stxa   %%g0, [%2] %3\n\t"
 471                         "stxa   %0, [%1] %4\n\t"
 472                         "membar #Sync\n\t"
 473                         "flush  %%g6\n\t"
 474                         "stxa   %%g0, [%2] %5\n\t"
 475                         "stxa   %0, [%1] %6\n\t"
 476                         "membar #Sync\n\t"
 477                         "flush  %%g6"
 478                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
 479                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
 480                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
 481                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
 482                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
 483                         : "memory");
 484         } else {
 485                 /* Implement me :-) */
 486                 BUG();
 487         }
 488
 489         tte_vaddr = (unsigned long) KERNBASE;
 490
 491         /* Spitfire Errata #32 workaround */
 492         /* NOTE: Using plain zero for the context value is
 493          *       correct here, we are not using the Linux trap
 494          *       tables yet so we should not use the special
 495          *       UltraSPARC-III+ page size encodings yet.
 496          */
 497         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 498                              "flush     %%g6"
 499                              : /* No outputs */
 500                              : "r" (0),
 501                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 502
 503         if (tlb_type == spitfire)
 504                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
 505         else
 506                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
 507
 508         kern_locked_tte_data = tte_data;
 509
 510         remap_func = (void *)  ((unsigned long) &prom_remap -
 511                                 (unsigned long) &prom_boot_page);
 512
 513
 514         /* Spitfire Errata #32 workaround */
 515         /* NOTE: Using plain zero for the context value is
 516          *       correct here, we are not using the Linux trap
 517          *       tables yet so we should not use the special
 518          *       UltraSPARC-III+ page size encodings yet.
 519          */
 520         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 521                              "flush     %%g6"
 522                              : /* No outputs */
 523                              : "r" (0),
 524                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 525
 526         remap_func((tlb_type == spitfire ?
 527                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
 528                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
 529                    (unsigned long) KERNBASE,
 530                    prom_get_mmu_ihandle());
 531
 532         if (bigkernel)
 533                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
 534                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
 535
 536         /* Flush out that temporary mapping. */
 537         spitfire_flush_dtlb_nucleus_page(0x0);
 538         spitfire_flush_itlb_nucleus_page(0x0);
 539
 540         /* Now lock us back into the TLBs via OBP. */
 541         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 542         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
 543         if (bigkernel) {
 544                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 545                                                                 tte_vaddr + 0x400000);
 546                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
 547                                                                 tte_vaddr + 0x400000);
 548         }
 549
 550         /* Re-read translations property. */
 551         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
 552                 prom_printf("Couldn't get translation property\n");
 553                 prom_halt();
 554         }
 555         n = n / sizeof(*trans);
 556
 557         for (i = 0; i < n; i++) {
 558                 unsigned long vaddr = trans[i].virt;
 559                 unsigned long size = trans[i].size;
 560
 561                 if (vaddr < 0xf0000000UL) {
 562                         unsigned long avoid_start = (unsigned long) KERNBASE;
 563                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
 564
 565                         if (bigkernel)
 566                                 avoid_end += (4 * 1024 * 1024);
 567                         if (vaddr < avoid_start) {
 568                                 unsigned long top = vaddr + size;
 569
 570                                 if (top > avoid_start)
 571                                         top = avoid_start;
 572                                 prom_unmap(top - vaddr, vaddr);
 573                         }
 574                         if ((vaddr + size) > avoid_end) {
 575                                 unsigned long bottom = vaddr;
 576
 577                                 if (bottom < avoid_end)
 578                                         bottom = avoid_end;
 579                                 prom_unmap((vaddr + size) - bottom, bottom);
 580                         }
 581                 }
 582         }
 583
 584         prom_printf("done.\n");
 585
 586         register_prom_callbacks();
 587 }
 588
 589 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 590  * upwards as reserved for use by the firmware (I wonder if this
 591  * will be the same on Cheetah...).  We use this virtual address
 592  * range for the VPTE table mappings of the nucleus so we need
 593  * to zap them when we enter the PROM.  -DaveM
 594  */
 595 static void __flush_nucleus_vptes(void)
 596 {
 597         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 598         int i;
 599
 600         /* Only DTLB must be checked for VPTE entries. */
 601         if (tlb_type == spitfire) {
 602                 for (i = 0; i < 63; i++) {
 603                         unsigned long tag;
 604
 605                         /* Spitfire Errata #32 workaround */
 606                         /* NOTE: Always runs on spitfire, so no cheetah+
 607                          *       page size encodings.
 608                          */
 609                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 610                                              "flush     %%g6"
 611                                              : /* No outputs */
 612                                              : "r" (0),
 613                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 614
 615                         tag = spitfire_get_dtlb_tag(i);
 616                         if (((tag & ~(PAGE_MASK)) == 0) &&
 617                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 618                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 619                                                      "membar #Sync"
 620                                                      : /* no outputs */
 621                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 622                                 spitfire_put_dtlb_data(i, 0x0UL);
 623                         }
 624                 }
 625         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 626                 for (i = 0; i < 512; i++) {
 627                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 628
 629                         if ((tag & ~PAGE_MASK) == 0 &&
 630                             (tag & PAGE_MASK) >= prom_reserved_base) {
 631                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 632                                                      "membar #Sync"
 633                                                      : /* no outputs */
 634                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 635                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 636                         }
 637
 638                         if (tlb_type != cheetah_plus)
 639                                 continue;
 640
 641                         tag = cheetah_get_dtlb_tag(i, 3);
 642
 643                         if ((tag & ~PAGE_MASK) == 0 &&
 644                             (tag & PAGE_MASK) >= prom_reserved_base) {
 645                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 646                                                      "membar #Sync"
 647                                                      : /* no outputs */
 648                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 649                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 650                         }
 651                 }
 652         } else {
 653                 /* Implement me :-) */
 654                 BUG();
 655         }
 656 }
 657
 658 static int prom_ditlb_set;
 659 struct prom_tlb_entry {
 660         int             tlb_ent;
 661         unsigned long   tlb_tag;
 662         unsigned long   tlb_data;
 663 };
 664 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 665
 666 void prom_world(int enter)
 667 {
 668         unsigned long pstate;
 669         int i;
 670
 671         if (!enter)
 672                 set_fs((mm_segment_t) { get_thread_current_ds() });
 673
 674         if (!prom_ditlb_set)
 675                 return;
 676
 677         /* Make sure the following runs atomically. */
 678         __asm__ __volatile__("flushw\n\t"
 679                              "rdpr      %%pstate, %0\n\t"
 680                              "wrpr      %0, %1, %%pstate"
 681                              : "=r" (pstate)
 682                              : "i" (PSTATE_IE));
 683
 684         if (enter) {
 685                 /* Kick out nucleus VPTEs. */
 686                 __flush_nucleus_vptes();
 687
 688                 /* Install PROM world. */
 689                 for (i = 0; i < 16; i++) {
 690                         if (prom_dtlb[i].tlb_ent != -1) {
 691                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 692                                                      "membar #Sync"
 693                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 694                                         "i" (ASI_DMMU));
 695                                 if (tlb_type == spitfire)
 696                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 697                                                                prom_dtlb[i].tlb_data);
 698                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 699                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 700                                                                prom_dtlb[i].tlb_data);
 701                         }
 702                         if (prom_itlb[i].tlb_ent != -1) {
 703                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 704                                                      "membar #Sync"
 705                                                      : : "r" (prom_itlb[i].tlb_tag),
 706                                                      "r" (TLB_TAG_ACCESS),
 707                                                      "i" (ASI_IMMU));
 708                                 if (tlb_type == spitfire)
 709                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 710                                                                prom_itlb[i].tlb_data);
 711                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 712                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 713                                                                prom_itlb[i].tlb_data);
 714                         }
 715                 }
 716         } else {
 717                 for (i = 0; i < 16; i++) {
 718                         if (prom_dtlb[i].tlb_ent != -1) {
 719                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 720                                                      "membar #Sync"
 721                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 722                                 if (tlb_type == spitfire)
 723                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 724                                 else
 725                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 726                         }
 727                         if (prom_itlb[i].tlb_ent != -1) {
 728                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 729                                                      "membar #Sync"
 730                                                      : : "r" (TLB_TAG_ACCESS),
 731                                                      "i" (ASI_IMMU));
 732                                 if (tlb_type == spitfire)
 733                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 734                                 else
 735                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 736                         }
 737                 }
 738         }
 739         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 740                              : : "r" (pstate));
 741 }
 742
 743 void inherit_locked_prom_mappings(int save_p)
 744 {
 745         int i;
 746         int dtlb_seen = 0;
 747         int itlb_seen = 0;
 748
 749         /* Fucking losing PROM has more mappings in the TLB, but
 750          * it (conveniently) fails to mention any of these in the
 751          * translations property.  The only ones that matter are
 752          * the locked PROM tlb entries, so we impose the following
 753          * irrecovable rule on the PROM, it is allowed 8 locked
 754          * entries in the ITLB and 8 in the DTLB.
 755          *
 756          * Supposedly the upper 16GB of the address space is
 757          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 758          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 759          * used between the client program and the firmware on sun5
 760          * systems to coordinate mmu mappings is also COMPLETELY
 761          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 762          */
 763         if (save_p) {
 764                 for (i = 0; i < 16; i++) {
 765                         prom_itlb[i].tlb_ent = -1;
 766                         prom_dtlb[i].tlb_ent = -1;
 767                 }
 768         }
 769         if (tlb_type == spitfire) {
 770                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
 771                 for (i = 0; i < high; i++) {
 772                         unsigned long data;
 773
 774                         /* Spitfire Errata #32 workaround */
 775                         /* NOTE: Always runs on spitfire, so no cheetah+
 776                          *       page size encodings.
 777                          */
 778                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 779                                              "flush     %%g6"
 780                                              : /* No outputs */
 781                                              : "r" (0),
 782                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 783
 784                         data = spitfire_get_dtlb_data(i);
 785                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 786                                 unsigned long tag;
 787
 788                                 /* Spitfire Errata #32 workaround */
 789                                 /* NOTE: Always runs on spitfire, so no
 790                                  *       cheetah+ page size encodings.
 791                                  */
 792                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 793                                                      "flush     %%g6"
 794                                                      : /* No outputs */
 795                                                      : "r" (0),
 796                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 797
 798                                 tag = spitfire_get_dtlb_tag(i);
 799                                 if (save_p) {
 800                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 801                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 802                                         prom_dtlb[dtlb_seen].tlb_data = data;
 803                                 }
 804                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 805                                                      "membar #Sync"
 806                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 807                                 spitfire_put_dtlb_data(i, 0x0UL);
 808
 809                                 dtlb_seen++;
 810                                 if (dtlb_seen > 15)
 811                                         break;
 812                         }
 813                 }
 814
 815                 for (i = 0; i < high; i++) {
 816                         unsigned long data;
 817
 818                         /* Spitfire Errata #32 workaround */
 819                         /* NOTE: Always runs on spitfire, so no
 820                          *       cheetah+ page size encodings.
 821                          */
 822                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 823                                              "flush     %%g6"
 824                                              : /* No outputs */
 825                                              : "r" (0),
 826                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 827
 828                         data = spitfire_get_itlb_data(i);
 829                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 830                                 unsigned long tag;
 831
 832                                 /* Spitfire Errata #32 workaround */
 833                                 /* NOTE: Always runs on spitfire, so no
 834                                  *       cheetah+ page size encodings.
 835                                  */
 836                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 837                                                      "flush     %%g6"
 838                                                      : /* No outputs */
 839                                                      : "r" (0),
 840                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 841
 842                                 tag = spitfire_get_itlb_tag(i);
 843                                 if (save_p) {
 844                                         prom_itlb[itlb_seen].tlb_ent = i;
 845                                         prom_itlb[itlb_seen].tlb_tag = tag;
 846                                         prom_itlb[itlb_seen].tlb_data = data;
 847                                 }
 848                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 849                                                      "membar #Sync"
 850                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 851                                 spitfire_put_itlb_data(i, 0x0UL);
 852
 853                                 itlb_seen++;
 854                                 if (itlb_seen > 15)
 855                                         break;
 856                         }
 857                 }
 858         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 859                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
 860
 861                 for (i = 0; i < high; i++) {
 862                         unsigned long data;
 863
 864                         data = cheetah_get_ldtlb_data(i);
 865                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 866                                 unsigned long tag;
 867
 868                                 tag = cheetah_get_ldtlb_tag(i);
 869                                 if (save_p) {
 870                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 871                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 872                                         prom_dtlb[dtlb_seen].tlb_data = data;
 873                                 }
 874                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 875                                                      "membar #Sync"
 876                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 877                                 cheetah_put_ldtlb_data(i, 0x0UL);
 878
 879                                 dtlb_seen++;
 880                                 if (dtlb_seen > 15)
 881                                         break;
 882                         }
 883                 }
 884
 885                 for (i = 0; i < high; i++) {
 886                         unsigned long data;
 887
 888                         data = cheetah_get_litlb_data(i);
 889                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 890                                 unsigned long tag;
 891
 892                                 tag = cheetah_get_litlb_tag(i);
 893                                 if (save_p) {
 894                                         prom_itlb[itlb_seen].tlb_ent = i;
 895                                         prom_itlb[itlb_seen].tlb_tag = tag;
 896                                         prom_itlb[itlb_seen].tlb_data = data;
 897                                 }
 898                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 899                                                      "membar #Sync"
 900                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 901                                 cheetah_put_litlb_data(i, 0x0UL);
 902
 903                                 itlb_seen++;
 904                                 if (itlb_seen > 15)
 905                                         break;
 906                         }
 907                 }
 908         } else {
 909                 /* Implement me :-) */
 910                 BUG();
 911         }
 912         if (save_p)
 913                 prom_ditlb_set = 1;
 914 }
 915
 916 /* Give PROM back his world, done during reboots... */
 917 void prom_reload_locked(void)
 918 {
 919         int i;
 920
 921         for (i = 0; i < 16; i++) {
 922                 if (prom_dtlb[i].tlb_ent != -1) {
 923                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 924                                              "membar #Sync"
 925                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 926                                 "i" (ASI_DMMU));
 927                         if (tlb_type == spitfire)
 928                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 929                                                        prom_dtlb[i].tlb_data);
 930                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 931                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 932                                                       prom_dtlb[i].tlb_data);
 933                 }
 934
 935                 if (prom_itlb[i].tlb_ent != -1) {
 936                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 937                                              "membar #Sync"
 938                                              : : "r" (prom_itlb[i].tlb_tag),
 939                                              "r" (TLB_TAG_ACCESS),
 940                                              "i" (ASI_IMMU));
 941                         if (tlb_type == spitfire)
 942                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 943                                                        prom_itlb[i].tlb_data);
 944                         else
 945                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 946                                                        prom_itlb[i].tlb_data);
 947                 }
 948         }
 949 }
 950
 951 #ifdef DCACHE_ALIASING_POSSIBLE
 952 void __flush_dcache_range(unsigned long start, unsigned long end)
 953 {
 954         unsigned long va;
 955
 956         if (tlb_type == spitfire) {
 957                 int n = 0;
 958
 959                 for (va = start; va < end; va += 32) {
 960                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 961                         if (++n >= 512)
 962                                 break;
 963                 }
 964         } else {
 965                 start = __pa(start);
 966                 end = __pa(end);
 967                 for (va = start; va < end; va += 32)
 968                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 969                                              "membar #Sync"
 970                                              : /* no outputs */
 971                                              : "r" (va),
 972                                                "i" (ASI_DCACHE_INVALIDATE));
 973         }
 974 }
 975 #endif /* DCACHE_ALIASING_POSSIBLE */
 976
 977 /* If not locked, zap it. */
 978 void __flush_tlb_all(void)
 979 {
 980         unsigned long pstate;
 981         int i;
 982
 983         __asm__ __volatile__("flushw\n\t"
 984                              "rdpr      %%pstate, %0\n\t"
 985                              "wrpr      %0, %1, %%pstate"
 986                              : "=r" (pstate)
 987                              : "i" (PSTATE_IE));
 988         if (tlb_type == spitfire) {
 989                 for (i = 0; i < 64; i++) {
 990                         /* Spitfire Errata #32 workaround */
 991                         /* NOTE: Always runs on spitfire, so no
 992                          *       cheetah+ page size encodings.
 993                          */
 994                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 995                                              "flush     %%g6"
 996                                              : /* No outputs */
 997                                              : "r" (0),
 998                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 999
1000                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1001                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1002                                                      "membar #Sync"
1003                                                      : /* no outputs */
1004                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1005                                 spitfire_put_dtlb_data(i, 0x0UL);
1006                         }
1007
1008                         /* Spitfire Errata #32 workaround */
1009                         /* NOTE: Always runs on spitfire, so no
1010                          *       cheetah+ page size encodings.
1011                          */
1012                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1013                                              "flush     %%g6"
1014                                              : /* No outputs */
1015                                              : "r" (0),
1016                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1017
1018                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1019                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1020                                                      "membar #Sync"
1021                                                      : /* no outputs */
1022                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1023                                 spitfire_put_itlb_data(i, 0x0UL);
1024                         }
1025                 }
1026         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1027                 cheetah_flush_dtlb_all();
1028                 cheetah_flush_itlb_all();
1029         }
1030         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1031                              : : "r" (pstate));
1032 }
1033
1034 /* Caller does TLB context flushing on local CPU if necessary.
1035  * The caller also ensures that CTX_VALID(mm->context) is false.
1036  *
1037  * We must be careful about boundary cases so that we never
1038  * let the user have CTX 0 (nucleus) or we ever use a CTX
1039  * version of zero (and thus NO_CONTEXT would not be caught
1040  * by version mis-match tests in mmu_context.h).
1041  */
1042 void get_new_mmu_context(struct mm_struct *mm)
1043 {
1044         unsigned long ctx, new_ctx;
1045         unsigned long orig_pgsz_bits;
1046
1047
1048         spin_lock(&ctx_alloc_lock);
1049         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1050         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1051         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1052         if (new_ctx >= (1 << CTX_NR_BITS)) {
1053                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1054                 if (new_ctx >= ctx) {
1055                         int i;
1056                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1057                                 CTX_FIRST_VERSION;
1058                         if (new_ctx == 1)
1059                                 new_ctx = CTX_FIRST_VERSION;
1060
1061                         /* Don't call memset, for 16 entries that's just
1062                          * plain silly...
1063                          */
1064                         mmu_context_bmap[0] = 3;
1065                         mmu_context_bmap[1] = 0;
1066                         mmu_context_bmap[2] = 0;
1067                         mmu_context_bmap[3] = 0;
1068                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1069                                 mmu_context_bmap[i + 0] = 0;
1070                                 mmu_context_bmap[i + 1] = 0;
1071                                 mmu_context_bmap[i + 2] = 0;
1072                                 mmu_context_bmap[i + 3] = 0;
1073                         }
1074                         goto out;
1075                 }
1076         }
1077         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1078         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1079 out:
1080         tlb_context_cache = new_ctx;
1081         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1082         spin_unlock(&ctx_alloc_lock);
1083 }
1084
1085 #ifndef CONFIG_SMP
1086 struct pgtable_cache_struct pgt_quicklists;
1087 #endif
1088
1089 /* OK, we have to color these pages. The page tables are accessed
1090  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1091  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1092  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1093  * fast handlers do not get data from old/garbage dcache lines that
1094  * correspond to an old/stale virtual address (user/kernel) that
1095  * previously mapped the pagetable page while accessing vpte range
1096  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1097  * color is the same, then when the kernel initializes the pagetable
1098  * using the later address range, accesses with the first address
1099  * range will see the newly initialized data rather than the garbage.
1100  */
1101 #ifdef DCACHE_ALIASING_POSSIBLE
1102 #define DC_ALIAS_SHIFT  1
1103 #else
1104 #define DC_ALIAS_SHIFT  0
1105 #endif
1106 pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1107 {
1108         struct page *page;
1109         unsigned long color;
1110
1111         {
1112                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1113
1114                 if (ptep)
1115                         return ptep;
1116         }
1117
1118         color = VPTE_COLOR(address);
1119         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1120         if (page) {
1121                 unsigned long *to_free;
1122                 unsigned long paddr;
1123                 pte_t *pte;
1124
1125 #ifdef DCACHE_ALIASING_POSSIBLE
1126                 set_page_count(page, 1);
1127                 ClearPageCompound(page);
1128
1129                 set_page_count((page + 1), 1);
1130                 ClearPageCompound(page + 1);
1131 #endif
1132                 paddr = (unsigned long) page_address(page);
1133                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1134
1135                 if (!color) {
1136                         pte = (pte_t *) paddr;
1137                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1138                 } else {
1139                         pte = (pte_t *) (paddr + PAGE_SIZE);
1140                         to_free = (unsigned long *) paddr;
1141                 }
1142
1143 #ifdef DCACHE_ALIASING_POSSIBLE
1144                 /* Now free the other one up, adjust cache size. */
1145                 preempt_disable();
1146                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1147                 pte_quicklist[color ^ 0x1] = to_free;
1148                 pgtable_cache_size++;
1149                 preempt_enable();
1150 #endif
1151
1152                 return pte;
1153         }
1154         return NULL;
1155 }
1156
1157 void sparc_ultra_dump_itlb(void)
1158 {
1159         int slot;
1160
1161         if (tlb_type == spitfire) {
1162                 printk ("Contents of itlb: ");
1163                 for (slot = 0; slot < 14; slot++) printk ("    ");
1164                 printk ("%2x:%016lx,%016lx\n",
1165                         0,
1166                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1167                 for (slot = 1; slot < 64; slot+=3) {
1168                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1169                                 slot,
1170                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1171                                 slot+1,
1172                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1173                                 slot+2,
1174                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1175                 }
1176         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1177                 printk ("Contents of itlb0:\n");
1178                 for (slot = 0; slot < 16; slot+=2) {
1179                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1180                                 slot,
1181                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1182                                 slot+1,
1183                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1184                 }
1185                 printk ("Contents of itlb2:\n");
1186                 for (slot = 0; slot < 128; slot+=2) {
1187                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1188                                 slot,
1189                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1190                                 slot+1,
1191                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1192                 }
1193         }
1194 }
1195
1196 void sparc_ultra_dump_dtlb(void)
1197 {
1198         int slot;
1199
1200         if (tlb_type == spitfire) {
1201                 printk ("Contents of dtlb: ");
1202                 for (slot = 0; slot < 14; slot++) printk ("    ");
1203                 printk ("%2x:%016lx,%016lx\n", 0,
1204                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1205                 for (slot = 1; slot < 64; slot+=3) {
1206                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1207                                 slot,
1208                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1209                                 slot+1,
1210                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1211                                 slot+2,
1212                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1213                 }
1214         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1215                 printk ("Contents of dtlb0:\n");
1216                 for (slot = 0; slot < 16; slot+=2) {
1217                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1218                                 slot,
1219                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1220                                 slot+1,
1221                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1222                 }
1223                 printk ("Contents of dtlb2:\n");
1224                 for (slot = 0; slot < 512; slot+=2) {
1225                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1226                                 slot,
1227                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1228                                 slot+1,
1229                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1230                 }
1231                 if (tlb_type == cheetah_plus) {
1232                         printk ("Contents of dtlb3:\n");
1233                         for (slot = 0; slot < 512; slot+=2) {
1234                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1235                                         slot,
1236                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1237                                         slot+1,
1238                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1239                         }
1240                 }
1241         }
1242 }
1243
1244 extern unsigned long cmdline_memory_size;
1245
1246 unsigned long __init bootmem_init(unsigned long *pages_avail)
1247 {
1248         unsigned long bootmap_size, start_pfn, end_pfn;
1249         unsigned long end_of_phys_memory = 0UL;
1250         unsigned long bootmap_pfn, bytes_avail, size;
1251         int i;
1252
1253 #ifdef CONFIG_DEBUG_BOOTMEM
1254         prom_printf("bootmem_init: Scan sp_banks, ");
1255 #endif
1256
1257         bytes_avail = 0UL;
1258         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1259                 end_of_phys_memory = sp_banks[i].base_addr +
1260                         sp_banks[i].num_bytes;
1261                 bytes_avail += sp_banks[i].num_bytes;
1262                 if (cmdline_memory_size) {
1263                         if (bytes_avail > cmdline_memory_size) {
1264                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1265
1266                                 bytes_avail -= slack;
1267                                 end_of_phys_memory -= slack;
1268
1269                                 sp_banks[i].num_bytes -= slack;
1270                                 if (sp_banks[i].num_bytes == 0) {
1271                                         sp_banks[i].base_addr = 0xdeadbeef;
1272                                 } else {
1273                                         sp_banks[i+1].num_bytes = 0;
1274                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1275                                 }
1276                                 break;
1277                         }
1278                 }
1279         }
1280
1281         *pages_avail = bytes_avail >> PAGE_SHIFT;
1282
1283         /* Start with page aligned address of last symbol in kernel
1284          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1285          * 4MB locked TLB translation.
1286          */
1287         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1288
1289         bootmap_pfn = start_pfn;
1290
1291         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1292
1293 #ifdef CONFIG_BLK_DEV_INITRD
1294         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1295         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1296                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1297                         sparc_ramdisk_image : sparc_ramdisk_image64;
1298                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1299                         ramdisk_image -= KERNBASE;
1300                 initrd_start = ramdisk_image + phys_base;
1301                 initrd_end = initrd_start + sparc_ramdisk_size;
1302                 if (initrd_end > end_of_phys_memory) {
1303                         printk(KERN_CRIT "initrd extends beyond end of memory "
1304                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1305                                initrd_end, end_of_phys_memory);
1306                         initrd_start = 0;
1307                 }
1308                 if (initrd_start) {
1309                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1310                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1311                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1312                 }
1313         }
1314 #endif
1315         /* Initialize the boot-time allocator. */
1316         max_pfn = max_low_pfn = end_pfn;
1317         min_low_pfn = pfn_base;
1318
1319 #ifdef CONFIG_DEBUG_BOOTMEM
1320         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1321                     min_low_pfn, bootmap_pfn, max_low_pfn);
1322 #endif
1323         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1324
1325         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1326
1327         /* Now register the available physical memory with the
1328          * allocator.
1329          */
1330         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1331 #ifdef CONFIG_DEBUG_BOOTMEM
1332                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1333                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1334 #endif
1335                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1336         }
1337
1338 #ifdef CONFIG_BLK_DEV_INITRD
1339         if (initrd_start) {
1340                 size = initrd_end - initrd_start;
1341
1342                 /* Resert the initrd image area. */
1343 #ifdef CONFIG_DEBUG_BOOTMEM
1344                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1345                         initrd_start, initrd_end);
1346 #endif
1347                 reserve_bootmem(initrd_start, size);
1348                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1349
1350                 initrd_start += PAGE_OFFSET;
1351                 initrd_end += PAGE_OFFSET;
1352         }
1353 #endif
1354         /* Reserve the kernel text/data/bss. */
1355 #ifdef CONFIG_DEBUG_BOOTMEM
1356         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1357 #endif
1358         reserve_bootmem(kern_base, kern_size);
1359         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1360
1361         /* Reserve the bootmem map.   We do not account for it
1362          * in pages_avail because we will release that memory
1363          * in free_all_bootmem.
1364          */
1365         size = bootmap_size;
1366 #ifdef CONFIG_DEBUG_BOOTMEM
1367         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1368                     (bootmap_pfn << PAGE_SHIFT), size);
1369 #endif
1370         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1371         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1372
1373         return end_pfn;
1374 }
1375
1376 /* paging_init() sets up the page tables */
1377
1378 extern void cheetah_ecache_flush_init(void);
1379
1380 static unsigned long last_valid_pfn;
1381
1382 void __init paging_init(void)
1383 {
1384         extern pmd_t swapper_pmd_dir[1024];
1385         extern unsigned int sparc64_vpte_patchme1[1];
1386         extern unsigned int sparc64_vpte_patchme2[1];
1387         unsigned long alias_base = kern_base + PAGE_OFFSET;
1388         unsigned long second_alias_page = 0;
1389         unsigned long pt, flags, end_pfn, pages_avail;
1390         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1391         unsigned long real_end;
1392
1393         set_bit(0, mmu_context_bmap);
1394
1395         real_end = (unsigned long)_end;
1396         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1397                 bigkernel = 1;
1398 #ifdef CONFIG_BLK_DEV_INITRD
1399         if (sparc_ramdisk_image || sparc_ramdisk_image64)
1400                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1401 #endif
1402
1403         /* We assume physical memory starts at some 4mb multiple,
1404          * if this were not true we wouldn't boot up to this point
1405          * anyways.
1406          */
1407         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1408         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1409         local_irq_save(flags);
1410         if (tlb_type == spitfire) {
1411                 __asm__ __volatile__(
1412         "       stxa    %1, [%0] %3\n"
1413         "       stxa    %2, [%5] %4\n"
1414         "       membar  #Sync\n"
1415         "       flush   %%g6\n"
1416         "       nop\n"
1417         "       nop\n"
1418         "       nop\n"
1419                 : /* No outputs */
1420                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1421                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1422                 : "memory");
1423                 if (real_end >= KERNBASE + 0x340000) {
1424                         second_alias_page = alias_base + 0x400000;
1425                         __asm__ __volatile__(
1426                 "       stxa    %1, [%0] %3\n"
1427                 "       stxa    %2, [%5] %4\n"
1428                 "       membar  #Sync\n"
1429                 "       flush   %%g6\n"
1430                 "       nop\n"
1431                 "       nop\n"
1432                 "       nop\n"
1433                         : /* No outputs */
1434                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1435                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1436                         : "memory");
1437                 }
1438         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1439                 __asm__ __volatile__(
1440         "       stxa    %1, [%0] %3\n"
1441         "       stxa    %2, [%5] %4\n"
1442         "       membar  #Sync\n"
1443         "       flush   %%g6\n"
1444         "       nop\n"
1445         "       nop\n"
1446         "       nop\n"
1447                 : /* No outputs */
1448                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1449                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1450                 : "memory");
1451                 if (real_end >= KERNBASE + 0x340000) {
1452                         second_alias_page = alias_base + 0x400000;
1453                         __asm__ __volatile__(
1454                 "       stxa    %1, [%0] %3\n"
1455                 "       stxa    %2, [%5] %4\n"
1456                 "       membar  #Sync\n"
1457                 "       flush   %%g6\n"
1458                 "       nop\n"
1459                 "       nop\n"
1460                 "       nop\n"
1461                         : /* No outputs */
1462                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1463                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1464                         : "memory");
1465                 }
1466         }
1467         local_irq_restore(flags);
1468
1469         /* Now set kernel pgd to upper alias so physical page computations
1470          * work.
1471          */
1472         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1473
1474         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1475
1476         /* Now can init the kernel/bad page tables. */
1477         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1478                 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1479
1480         sparc64_vpte_patchme1[0] |=
1481                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1482         sparc64_vpte_patchme2[0] |=
1483                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1484         flushi((long)&sparc64_vpte_patchme1[0]);
1485
1486         /* Setup bootmem... */
1487         pages_avail = 0;
1488         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1489
1490         /* Inherit non-locked OBP mappings. */
1491         inherit_prom_mappings();
1492
1493         /* Ok, we can use our TLB miss and window trap handlers safely.
1494          * We need to do a quick peek here to see if we are on StarFire
1495          * or not, so setup_tba can setup the IRQ globals correctly (it
1496          * needs to get the hard smp processor id correctly).
1497          */
1498         {
1499                 extern void setup_tba(int);
1500                 setup_tba(this_is_starfire);
1501         }
1502
1503         inherit_locked_prom_mappings(1);
1504
1505         /* We only created DTLB mapping of this stuff. */
1506         spitfire_flush_dtlb_nucleus_page(alias_base);
1507         if (second_alias_page)
1508                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1509
1510         __flush_tlb_all();
1511
1512         {
1513                 unsigned long zones_size[MAX_NR_ZONES];
1514                 unsigned long zholes_size[MAX_NR_ZONES];
1515                 unsigned long npages;
1516                 int znum;
1517
1518                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1519                         zones_size[znum] = zholes_size[znum] = 0;
1520
1521                 npages = end_pfn - pfn_base;
1522                 zones_size[ZONE_DMA] = npages;
1523                 zholes_size[ZONE_DMA] = npages - pages_avail;
1524
1525                 free_area_init_node(0, &contig_page_data, zones_size,
1526                                     phys_base >> PAGE_SHIFT, zholes_size);
1527         }
1528
1529         device_scan();
1530 }
1531
1532 /* Ok, it seems that the prom can allocate some more memory chunks
1533  * as a side effect of some prom calls we perform during the
1534  * boot sequence.  My most likely theory is that it is from the
1535  * prom_set_traptable() call, and OBP is allocating a scratchpad
1536  * for saving client program register state etc.
1537  */
1538 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1539 {
1540         int swapi = 0;
1541         int i, mitr;
1542         unsigned long tmpaddr, tmpsize;
1543         unsigned long lowest;
1544
1545         for (i = 0; thislist[i].theres_more != 0; i++) {
1546                 lowest = thislist[i].start_adr;
1547                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1548                         if (thislist[mitr].start_adr < lowest) {
1549                                 lowest = thislist[mitr].start_adr;
1550                                 swapi = mitr;
1551                         }
1552                 if (lowest == thislist[i].start_adr)
1553                         continue;
1554                 tmpaddr = thislist[swapi].start_adr;
1555                 tmpsize = thislist[swapi].num_bytes;
1556                 for (mitr = swapi; mitr > i; mitr--) {
1557                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1558                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1559                 }
1560                 thislist[i].start_adr = tmpaddr;
1561                 thislist[i].num_bytes = tmpsize;
1562         }
1563 }
1564
1565 void __init rescan_sp_banks(void)
1566 {
1567         struct linux_prom64_registers memlist[64];
1568         struct linux_mlist_p1275 avail[64], *mlist;
1569         unsigned long bytes, base_paddr;
1570         int num_regs, node = prom_finddevice("/memory");
1571         int i;
1572
1573         num_regs = prom_getproperty(node, "available",
1574                                     (char *) memlist, sizeof(memlist));
1575         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1576         for (i = 0; i < num_regs; i++) {
1577                 avail[i].start_adr = memlist[i].phys_addr;
1578                 avail[i].num_bytes = memlist[i].reg_size;
1579                 avail[i].theres_more = &avail[i + 1];
1580         }
1581         avail[i - 1].theres_more = NULL;
1582         sort_memlist(avail);
1583
1584         mlist = &avail[0];
1585         i = 0;
1586         bytes = mlist->num_bytes;
1587         base_paddr = mlist->start_adr;
1588
1589         sp_banks[0].base_addr = base_paddr;
1590         sp_banks[0].num_bytes = bytes;
1591
1592         while (mlist->theres_more != NULL){
1593                 i++;
1594                 mlist = mlist->theres_more;
1595                 bytes = mlist->num_bytes;
1596                 if (i >= SPARC_PHYS_BANKS-1) {
1597                         printk ("The machine has more banks than "
1598                                 "this kernel can support\n"
1599                                 "Increase the SPARC_PHYS_BANKS "
1600                                 "setting (currently %d)\n",
1601                                 SPARC_PHYS_BANKS);
1602                         i = SPARC_PHYS_BANKS-1;
1603                         break;
1604                 }
1605
1606                 sp_banks[i].base_addr = mlist->start_adr;
1607                 sp_banks[i].num_bytes = mlist->num_bytes;
1608         }
1609
1610         i++;
1611         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1612         sp_banks[i].num_bytes = 0;
1613
1614         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1615                 sp_banks[i].num_bytes &= PAGE_MASK;
1616 }
1617
1618 static void __init taint_real_pages(void)
1619 {
1620         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1621         int i;
1622
1623         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1624                 saved_sp_banks[i].base_addr =
1625                         sp_banks[i].base_addr;
1626                 saved_sp_banks[i].num_bytes =
1627                         sp_banks[i].num_bytes;
1628         }
1629
1630         rescan_sp_banks();
1631
1632         /* Find changes discovered in the sp_bank rescan and
1633          * reserve the lost portions in the bootmem maps.
1634          */
1635         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1636                 unsigned long old_start, old_end;
1637
1638                 old_start = saved_sp_banks[i].base_addr;
1639                 old_end = old_start +
1640                         saved_sp_banks[i].num_bytes;
1641                 while (old_start < old_end) {
1642                         int n;
1643
1644                         for (n = 0; sp_banks[n].num_bytes; n++) {
1645                                 unsigned long new_start, new_end;
1646
1647                                 new_start = sp_banks[n].base_addr;
1648                                 new_end = new_start + sp_banks[n].num_bytes;
1649
1650                                 if (new_start <= old_start &&
1651                                     new_end >= (old_start + PAGE_SIZE)) {
1652                                         set_bit (old_start >> 22,
1653                                                  sparc64_valid_addr_bitmap);
1654                                         goto do_next_page;
1655                                 }
1656                         }
1657                         reserve_bootmem(old_start, PAGE_SIZE);
1658
1659                 do_next_page:
1660                         old_start += PAGE_SIZE;
1661                 }
1662         }
1663 }
1664
1665 void __init mem_init(void)
1666 {
1667         unsigned long codepages, datapages, initpages;
1668         unsigned long addr, last;
1669         int i;
1670
1671         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1672         i += 1;
1673         sparc64_valid_addr_bitmap = (unsigned long *)
1674                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1675         if (sparc64_valid_addr_bitmap == NULL) {
1676                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1677                 prom_halt();
1678         }
1679         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1680
1681         addr = PAGE_OFFSET + kern_base;
1682         last = PAGE_ALIGN(kern_size) + addr;
1683         while (addr < last) {
1684                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1685                 addr += PAGE_SIZE;
1686         }
1687
1688         taint_real_pages();
1689
1690         max_mapnr = last_valid_pfn - pfn_base;
1691         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1692
1693 #ifdef CONFIG_DEBUG_BOOTMEM
1694         prom_printf("mem_init: Calling free_all_bootmem().\n");
1695 #endif
1696         totalram_pages = num_physpages = free_all_bootmem() - 1;
1697
1698         /*
1699          * Set up the zero page, mark it reserved, so that page count
1700          * is not manipulated when freeing the page from user ptes.
1701          */
1702         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1703         if (mem_map_zero == NULL) {
1704                 prom_printf("paging_init: Cannot alloc zero page.\n");
1705                 prom_halt();
1706         }
1707         SetPageReserved(mem_map_zero);
1708
1709         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1710         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1711         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1712         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1713         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1714         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1715
1716         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1717                nr_free_pages() << (PAGE_SHIFT-10),
1718                codepages << (PAGE_SHIFT-10),
1719                datapages << (PAGE_SHIFT-10),
1720                initpages << (PAGE_SHIFT-10),
1721                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1722
1723         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1724                 cheetah_ecache_flush_init();
1725 }
1726
1727 void free_initmem (void)
1728 {
1729         unsigned long addr, initend;
1730
1731         /*
1732          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1733          */
1734         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1735         initend = (unsigned long)(__init_end) & PAGE_MASK;
1736         for (; addr < initend; addr += PAGE_SIZE) {
1737                 unsigned long page;
1738                 struct page *p;
1739
1740                 page = (addr +
1741                         ((unsigned long) __va(kern_base)) -
1742                         ((unsigned long) KERNBASE));
1743                 memset((void *)addr, 0xcc, PAGE_SIZE);
1744                 p = virt_to_page(page);
1745
1746                 ClearPageReserved(p);
1747                 set_page_count(p, 1);
1748                 __free_page(p);
1749                 num_physpages++;
1750                 totalram_pages++;
1751         }
1752 }
1753
1754 #ifdef CONFIG_BLK_DEV_INITRD
1755 void free_initrd_mem(unsigned long start, unsigned long end)
1756 {
1757         if (start < end)
1758                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1759         for (; start < end; start += PAGE_SIZE) {
1760                 struct page *p = virt_to_page(start);
1761
1762                 ClearPageReserved(p);
1763                 set_page_count(p, 1);
1764                 __free_page(p);
1765                 num_physpages++;
1766                 totalram_pages++;
1767         }
1768 }
1769 #endif