arch/ppc64/kernel/pmac_smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24
  25 #undef DEBUG
  26
  27 #include <linux/config.h>
  28 #include <linux/kernel.h>
  29 #include <linux/sched.h>
  30 #include <linux/smp.h>
  31 #include <linux/smp_lock.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kernel_stat.h>
  34 #include <linux/init.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/errno.h>
  37 #include <linux/irq.h>
  38
  39 #include <asm/ptrace.h>
  40 #include <asm/atomic.h>
  41 #include <asm/irq.h>
  42 #include <asm/page.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/sections.h>
  45 #include <asm/io.h>
  46 #include <asm/prom.h>
  47 #include <asm/smp.h>
  48 #include <asm/machdep.h>
  49 #include <asm/pmac_feature.h>
  50 #include <asm/time.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/keylargo.h>
  53 #include <asm/pmac_low_i2c.h>
  54
  55 #include "mpic.h"
  56
  57 #ifdef DEBUG
  58 #define DBG(fmt...) udbg_printf(fmt)
  59 #else
  60 #define DBG(fmt...)
  61 #endif
  62
  63 extern void pmac_secondary_start_1(void);
  64 extern void pmac_secondary_start_2(void);
  65 extern void pmac_secondary_start_3(void);
  66
  67 extern struct smp_ops_t *smp_ops;
  68
  69 static void (*pmac_tb_freeze)(int freeze);
  70 static struct device_node *pmac_tb_clock_chip_host;
  71 static DEFINE_SPINLOCK(timebase_lock);
  72 static unsigned long timebase;
  73
  74 static void smp_core99_cypress_tb_freeze(int freeze)
  75 {
  76         u8 data;
  77         int rc;
  78
  79         /* Strangely, the device-tree says address is 0xd2, but darwin
  80          * accesses 0xd0 ...
  81          */
  82         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
  83         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
  84                                0xd0 | pmac_low_i2c_read,
  85                                0x81, &data, 1);
  86         if (rc != 0)
  87                 goto bail;
  88
  89         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
  90
  91         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
  92         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
  93                                0xd0 | pmac_low_i2c_write,
  94                                0x81, &data, 1);
  95
  96  bail:
  97         if (rc != 0) {
  98                 printk("Cypress Timebase %s rc: %d\n",
  99                        freeze ? "freeze" : "unfreeze", rc);
 100                 panic("Timebase freeze failed !\n");
 101         }
 102 }
 103
 104 static void smp_core99_pulsar_tb_freeze(int freeze)
 105 {
 106         u8 data;
 107         int rc;
 108
 109         /* Strangely, the device-tree says address is 0xd2, but darwin
 110          * accesses 0xd0 ...
 111          */
 112         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
 113         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
 114                                0xd4 | pmac_low_i2c_read,
 115                                0x2e, &data, 1);
 116         if (rc != 0)
 117                 goto bail;
 118
 119         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
 120
 121         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
 122         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
 123                                0xd4 | pmac_low_i2c_write,
 124                                0x2e, &data, 1);
 125  bail:
 126         if (rc != 0) {
 127                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
 128                        freeze ? "freeze" : "unfreeze", rc);
 129                 panic("Timebase freeze failed !\n");
 130         }
 131 }
 132
 133
 134 static void smp_core99_give_timebase(void)
 135 {
 136         /* Open i2c bus for synchronous access */
 137         if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
 138                 panic("Can't open i2c for TB sync !\n");
 139
 140         spin_lock(&timebase_lock);
 141         (*pmac_tb_freeze)(1);
 142         mb();
 143         timebase = get_tb();
 144         spin_unlock(&timebase_lock);
 145
 146         while (timebase)
 147                 barrier();
 148
 149         spin_lock(&timebase_lock);
 150         (*pmac_tb_freeze)(0);
 151         spin_unlock(&timebase_lock);
 152
 153         /* Close i2c bus */
 154         pmac_low_i2c_close(pmac_tb_clock_chip_host);
 155 }
 156
 157
 158 static void __devinit smp_core99_take_timebase(void)
 159 {
 160         while (!timebase)
 161                 barrier();
 162         spin_lock(&timebase_lock);
 163         set_tb(timebase >> 32, timebase & 0xffffffff);
 164         timebase = 0;
 165         spin_unlock(&timebase_lock);
 166 }
 167
 168
 169 static int __init smp_core99_probe(void)
 170 {
 171         struct device_node *cpus;
 172         struct device_node *cc;
 173         int ncpus = 0;
 174
 175         /* Maybe use systemconfiguration here ? */
 176         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 177
 178         /* Count CPUs in the device-tree */
 179         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
 180                 ++ncpus;
 181
 182         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
 183
 184         /* Nothing more to do if less than 2 of them */
 185         if (ncpus <= 1)
 186                 return 1;
 187
 188         /* Look for the clock chip */
 189         for (cc = NULL; (cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL;) {
 190                 struct device_node *p = of_get_parent(cc);
 191                 u32 *reg;
 192                 int ok;
 193                 ok = p && device_is_compatible(p, "uni-n-i2c");
 194                 if (!ok)
 195                         goto next;
 196                 reg = (u32 *)get_property(cc, "reg", NULL);
 197                 if (reg == NULL)
 198                         goto next;
 199                 switch (*reg) {
 200                 case 0xd2:
 201                         pmac_tb_freeze = smp_core99_cypress_tb_freeze;
 202                         printk(KERN_INFO "Timebase clock is Cypress chip\n");
 203                         break;
 204                 case 0xd4:
 205                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 206                         printk(KERN_INFO "Timebase clock is Pulsar chip\n");
 207                         break;
 208                 }
 209                 if (pmac_tb_freeze != NULL) {
 210                         pmac_tb_clock_chip_host = p;
 211                         smp_ops->give_timebase = smp_core99_give_timebase;
 212                         smp_ops->take_timebase = smp_core99_take_timebase;
 213                         break;
 214                 }
 215         next:
 216                 of_node_put(p);
 217         }
 218
 219         mpic_request_ipis();
 220
 221         return ncpus;
 222 }
 223
 224 static void __init smp_core99_kick_cpu(int nr)
 225 {
 226         int save_vector, j;
 227         unsigned long new_vector;
 228         unsigned long flags;
 229         volatile unsigned int *vector
 230                  = ((volatile unsigned int *)(KERNELBASE+0x100));
 231
 232         if (nr < 1 || nr > 3)
 233                 return;
 234         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
 235
 236         local_irq_save(flags);
 237         local_irq_disable();
 238
 239         /* Save reset vector */
 240         save_vector = *vector;
 241
 242         /* Setup fake reset vector that does
 243          *   b .pmac_secondary_start - KERNELBASE
 244          */
 245         switch(nr) {
 246         case 1:
 247                 new_vector = (unsigned long)pmac_secondary_start_1;
 248                 break;
 249         case 2:
 250                 new_vector = (unsigned long)pmac_secondary_start_2;
 251                 break;
 252         case 3:
 253         default:
 254                 new_vector = (unsigned long)pmac_secondary_start_3;
 255                 break;
 256         }
 257         *vector = 0x48000002 + (new_vector - KERNELBASE);
 258
 259         /* flush data cache and inval instruction cache */
 260         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 261
 262         /* Put some life in our friend */
 263         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 264         paca[nr].cpu_start = 1;
 265
 266         /* FIXME: We wait a bit for the CPU to take the exception, I should
 267          * instead wait for the entry code to set something for me. Well,
 268          * ideally, all that crap will be done in prom.c and the CPU left
 269          * in a RAM-based wait loop like CHRP.
 270          */
 271         for (j = 1; j < 1000000; j++)
 272                 mb();
 273
 274         /* Restore our exception vector */
 275         *vector = save_vector;
 276         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 277
 278         local_irq_restore(flags);
 279         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 280 }
 281
 282 static void __init smp_core99_setup_cpu(int cpu_nr)
 283 {
 284         /* Setup MPIC */
 285         mpic_setup_this_cpu();
 286
 287         if (cpu_nr == 0) {
 288                 extern void g5_phy_disable_cpu1(void);
 289
 290                 /* If we didn't start the second CPU, we must take
 291                  * it off the bus
 292                  */
 293                 if (num_online_cpus() < 2)
 294                         g5_phy_disable_cpu1();
 295                 if (ppc_md.progress) ppc_md.progress("smp_core99_setup_cpu 0 done", 0x349);
 296         }
 297 }
 298
 299 struct smp_ops_t core99_smp_ops __pmacdata = {
 300         .message_pass   = smp_mpic_message_pass,
 301         .probe          = smp_core99_probe,
 302         .kick_cpu       = smp_core99_kick_cpu,
 303         .setup_cpu      = smp_core99_setup_cpu,
 304         .give_timebase  = smp_generic_give_timebase,
 305         .take_timebase  = smp_generic_take_timebase,
 306 };
 307
 308 void __init pmac_setup_smp(void)
 309 {
 310         smp_ops = &core99_smp_ops;
 311 #ifdef CONFIG_HOTPLUG_CPU
 312         smp_ops->cpu_enable = generic_cpu_enable;
 313         smp_ops->cpu_disable = generic_cpu_disable;
 314         smp_ops->cpu_die = generic_cpu_die;
 315 #endif
 316 }