arch/ppc/syslib/open_pic2.c

   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  *
  10  *  This is a duplicate of open_pic.c that deals with U3s MPIC on
  11  *  G5 PowerMacs. It's the same file except it's using big endian
  12  *  register accesses
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/init.h>
  20 #include <linux/irq.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/sysdev.h>
  23 #include <linux/errno.h>
  24 #include <asm/ptrace.h>
  25 #include <asm/signal.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28 #include <asm/prom.h>
  29 #include <asm/sections.h>
  30 #include <asm/open_pic.h>
  31 #include <asm/i8259.h>
  32
  33 #include "open_pic_defs.h"
  34
  35 void *OpenPIC2_Addr;
  36 static volatile struct OpenPIC *OpenPIC2 = NULL;
  37 /*
  38  * We define OpenPIC_InitSenses table thusly:
  39  * bit 0x1: sense, 0 for edge and 1 for level.
  40  * bit 0x2: polarity, 0 for negative, 1 for positive.
  41  */
  42 extern  u_int OpenPIC_NumInitSenses;
  43 extern u_char *OpenPIC_InitSenses;
  44 extern int use_of_interrupt_tree;
  45
  46 static u_int NumProcessors;
  47 static u_int NumSources;
  48 static int open_pic2_irq_offset;
  49 static volatile OpenPIC_Source *ISR[NR_IRQS];
  50
  51 /* Global Operations */
  52 static void openpic2_disable_8259_pass_through(void);
  53 static void openpic2_set_priority(u_int pri);
  54 static void openpic2_set_spurious(u_int vector);
  55
  56 /* Timer Interrupts */
  57 static void openpic2_inittimer(u_int timer, u_int pri, u_int vector);
  58 static void openpic2_maptimer(u_int timer, u_int cpumask);
  59
  60 /* Interrupt Sources */
  61 static void openpic2_enable_irq(u_int irq);
  62 static void openpic2_disable_irq(u_int irq);
  63 static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  64                             int is_level);
  65 static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask);
  66
  67 /*
  68  * These functions are not used but the code is kept here
  69  * for completeness and future reference.
  70  */
  71 static void openpic2_reset(void);
  72 #ifdef notused
  73 static void openpic2_enable_8259_pass_through(void);
  74 static u_int openpic2_get_priority(void);
  75 static u_int openpic2_get_spurious(void);
  76 static void openpic2_set_sense(u_int irq, int sense);
  77 #endif /* notused */
  78
  79 /*
  80  * Description of the openpic for the higher-level irq code
  81  */
  82 static void openpic2_end_irq(unsigned int irq_nr);
  83 static void openpic2_ack_irq(unsigned int irq_nr);
  84
  85 struct hw_interrupt_type open_pic2 = {
  86         " OpenPIC2 ",
  87         NULL,
  88         NULL,
  89         openpic2_enable_irq,
  90         openpic2_disable_irq,
  91         openpic2_ack_irq,
  92         openpic2_end_irq,
  93 };
  94
  95 /*
  96  *  Accesses to the current processor's openpic registers
  97  *  On cascaded controller, this is only CPU 0
  98  */
  99 #define THIS_CPU                Processor[0]
 100 #define DECL_THIS_CPU
 101 #define CHECK_THIS_CPU
 102
 103 #if 1
 104 #define check_arg_ipi(ipi) \
 105     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 106         printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi);
 107 #define check_arg_timer(timer) \
 108     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 109         printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer);
 110 #define check_arg_vec(vec) \
 111     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 112         printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec);
 113 #define check_arg_pri(pri) \
 114     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 115         printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri);
 116 /*
 117  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 118  * data has probably been corrupted and we're going to panic or deadlock later
 119  * anyway --Troy
 120  */
 121 extern unsigned long* _get_SP(void);
 122 #define check_arg_irq(irq) \
 123     if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \
 124         || ISR[irq - open_pic2_irq_offset] == 0) { \
 125       printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \
 126       /*print_backtrace(_get_SP());*/ }
 127 #define check_arg_cpu(cpu) \
 128     if (cpu < 0 || cpu >= NumProcessors){ \
 129         printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \
 130         /*print_backtrace(_get_SP());*/ }
 131 #else
 132 #define check_arg_ipi(ipi)      do {} while (0)
 133 #define check_arg_timer(timer)  do {} while (0)
 134 #define check_arg_vec(vec)      do {} while (0)
 135 #define check_arg_pri(pri)      do {} while (0)
 136 #define check_arg_irq(irq)      do {} while (0)
 137 #define check_arg_cpu(cpu)      do {} while (0)
 138 #endif
 139
 140 static u_int openpic2_read(volatile u_int *addr)
 141 {
 142         u_int val;
 143
 144         val = in_be32(addr);
 145         return val;
 146 }
 147
 148 static inline void openpic2_write(volatile u_int *addr, u_int val)
 149 {
 150         out_be32(addr, val);
 151 }
 152
 153 static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask)
 154 {
 155         u_int val = openpic2_read(addr);
 156         return val & mask;
 157 }
 158
 159 inline void openpic2_writefield(volatile u_int *addr, u_int mask,
 160                                u_int field)
 161 {
 162         u_int val = openpic2_read(addr);
 163         openpic2_write(addr, (val & ~mask) | (field & mask));
 164 }
 165
 166 static inline void openpic2_clearfield(volatile u_int *addr, u_int mask)
 167 {
 168         openpic2_writefield(addr, mask, 0);
 169 }
 170
 171 static inline void openpic2_setfield(volatile u_int *addr, u_int mask)
 172 {
 173         openpic2_writefield(addr, mask, mask);
 174 }
 175
 176 static void openpic2_safe_writefield(volatile u_int *addr, u_int mask,
 177                                     u_int field)
 178 {
 179         openpic2_setfield(addr, OPENPIC_MASK);
 180         while (openpic2_read(addr) & OPENPIC_ACTIVITY);
 181         openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 182 }
 183
 184 static void openpic2_reset(void)
 185 {
 186         openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
 187                          OPENPIC_CONFIG_RESET);
 188         while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0,
 189                                  OPENPIC_CONFIG_RESET))
 190                 mb();
 191 }
 192
 193 void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR)
 194 {
 195         volatile OpenPIC_Source *src = first_ISR;
 196         int i, last_irq;
 197
 198         last_irq = first_irq + num_irqs;
 199         if (last_irq > NumSources)
 200                 NumSources = last_irq;
 201         if (src == 0)
 202                 src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq];
 203         for (i = first_irq; i < last_irq; ++i, ++src)
 204                 ISR[i] = src;
 205 }
 206
 207 /*
 208  * The `offset' parameter defines where the interrupts handled by the
 209  * OpenPIC start in the space of interrupt numbers that the kernel knows
 210  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 211  * kernel's interrupt numbering scheme.
 212  * We assume there is only one OpenPIC.
 213  */
 214 void __init openpic2_init(int offset)
 215 {
 216         u_int t, i;
 217         u_int timerfreq;
 218         const char *version;
 219
 220         if (!OpenPIC2_Addr) {
 221                 printk("No OpenPIC2 found !\n");
 222                 return;
 223         }
 224         OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr;
 225
 226         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 227
 228         t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0);
 229         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 230         case 1:
 231                 version = "1.0";
 232                 break;
 233         case 2:
 234                 version = "1.2";
 235                 break;
 236         case 3:
 237                 version = "1.3";
 238                 break;
 239         default:
 240                 version = "?";
 241                 break;
 242         }
 243         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 244                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 245         if (NumSources == 0)
 246                 openpic2_set_sources(0,
 247                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 248                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 249                                     NULL);
 250         printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n",
 251                version, NumProcessors, NumSources, OpenPIC2);
 252         timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency);
 253         if (timerfreq)
 254                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 255                        timerfreq / 1000000, timerfreq % 1000000);
 256
 257         open_pic2_irq_offset = offset;
 258
 259         /* Initialize timer interrupts */
 260         if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba);
 261         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 262                 /* Disabled, Priority 0 */
 263                 openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset);
 264                 /* No processor */
 265                 openpic2_maptimer(i, 0);
 266         }
 267
 268         /* Initialize external interrupts */
 269         if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc);
 270
 271         openpic2_set_priority(0xf);
 272
 273         /* Init all external sources, including possibly the cascade. */
 274         for (i = 0; i < NumSources; i++) {
 275                 int sense;
 276
 277                 if (ISR[i] == 0)
 278                         continue;
 279
 280                 /* the bootloader may have left it enabled (bad !) */
 281                 openpic2_disable_irq(i+offset);
 282
 283                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 284                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 285
 286                 if (sense & IRQ_SENSE_MASK)
 287                         irq_desc[i+offset].status = IRQ_LEVEL;
 288
 289                 /* Enabled, Priority 8 */
 290                 openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
 291                                 (sense & IRQ_SENSE_MASK));
 292                 /* Processor 0 */
 293                 openpic2_mapirq(i, 1<<0, 0);
 294         }
 295
 296         /* Init descriptors */
 297         for (i = offset; i < NumSources + offset; i++)
 298                 irq_desc[i].handler = &open_pic2;
 299
 300         /* Initialize the spurious interrupt */
 301         if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd);
 302         openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset);
 303
 304         openpic2_disable_8259_pass_through();
 305         openpic2_set_priority(0);
 306
 307         if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222);
 308 }
 309
 310 #ifdef notused
 311 static void openpic2_enable_8259_pass_through(void)
 312 {
 313         openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0,
 314                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 315 }
 316 #endif /* notused */
 317
 318 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
 319 static void openpic2_disable_8259_pass_through(void)
 320 {
 321         openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
 322                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 323 }
 324
 325 /*
 326  *  Find out the current interrupt
 327  */
 328 u_int openpic2_irq(void)
 329 {
 330         u_int vec;
 331         DECL_THIS_CPU;
 332
 333         CHECK_THIS_CPU;
 334         vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge,
 335                                 OPENPIC_VECTOR_MASK);
 336         return vec;
 337 }
 338
 339 void openpic2_eoi(void)
 340 {
 341         DECL_THIS_CPU;
 342
 343         CHECK_THIS_CPU;
 344         openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0);
 345         /* Handle PCI write posting */
 346         (void)openpic2_read(&OpenPIC2->THIS_CPU.EOI);
 347 }
 348
 349 #ifdef notused
 350 static u_int openpic2_get_priority(void)
 351 {
 352         DECL_THIS_CPU;
 353
 354         CHECK_THIS_CPU;
 355         return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
 356                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 357 }
 358 #endif /* notused */
 359
 360 static void __init openpic2_set_priority(u_int pri)
 361 {
 362         DECL_THIS_CPU;
 363
 364         CHECK_THIS_CPU;
 365         check_arg_pri(pri);
 366         openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
 367                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 368 }
 369
 370 /*
 371  *  Get/set the spurious vector
 372  */
 373 #ifdef notused
 374 static u_int openpic2_get_spurious(void)
 375 {
 376         return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector,
 377                                  OPENPIC_VECTOR_MASK);
 378 }
 379 #endif /* notused */
 380
 381 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
 382 static void openpic2_set_spurious(u_int vec)
 383 {
 384         check_arg_vec(vec);
 385         openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 386                            vec);
 387 }
 388
 389 static DEFINE_SPINLOCK(openpic2_setup_lock);
 390
 391 /*
 392  *  Initialize a timer interrupt (and disable it)
 393  *
 394  *  timer: OpenPIC timer number
 395  *  pri: interrupt source priority
 396  *  vec: the vector it will produce
 397  */
 398 static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec)
 399 {
 400         check_arg_timer(timer);
 401         check_arg_pri(pri);
 402         check_arg_vec(vec);
 403         openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority,
 404                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 405                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 406 }
 407
 408 /*
 409  *  Map a timer interrupt to one or more CPUs
 410  */
 411 static void __init openpic2_maptimer(u_int timer, u_int cpumask)
 412 {
 413         check_arg_timer(timer);
 414         openpic2_write(&OpenPIC2->Global.Timer[timer].Destination,
 415                       cpumask);
 416 }
 417
 418 /*
 419  * Initalize the interrupt source which will generate an NMI.
 420  * This raises the interrupt's priority from 8 to 9.
 421  *
 422  * irq: The logical IRQ which generates an NMI.
 423  */
 424 void __init
 425 openpic2_init_nmi_irq(u_int irq)
 426 {
 427         check_arg_irq(irq);
 428         openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority,
 429                                 OPENPIC_PRIORITY_MASK,
 430                                 9 << OPENPIC_PRIORITY_SHIFT);
 431 }
 432
 433 /*
 434  *
 435  * All functions below take an offset'ed irq argument
 436  *
 437  */
 438
 439
 440 /*
 441  *  Enable/disable an external interrupt source
 442  *
 443  *  Externally called, irq is an offseted system-wide interrupt number
 444  */
 445 static void openpic2_enable_irq(u_int irq)
 446 {
 447         volatile u_int *vpp;
 448
 449         check_arg_irq(irq);
 450         vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
 451         openpic2_clearfield(vpp, OPENPIC_MASK);
 452         /* make sure mask gets to controller before we return to user */
 453         do {
 454                 mb(); /* sync is probably useless here */
 455         } while (openpic2_readfield(vpp, OPENPIC_MASK));
 456 }
 457
 458 static void openpic2_disable_irq(u_int irq)
 459 {
 460         volatile u_int *vpp;
 461         u32 vp;
 462
 463         check_arg_irq(irq);
 464         vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
 465         openpic2_setfield(vpp, OPENPIC_MASK);
 466         /* make sure mask gets to controller before we return to user */
 467         do {
 468                 mb();  /* sync is probably useless here */
 469                 vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 470         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 471 }
 472
 473
 474 /*
 475  *  Initialize an interrupt source (and disable it!)
 476  *
 477  *  irq: OpenPIC interrupt number
 478  *  pri: interrupt source priority
 479  *  vec: the vector it will produce
 480  *  pol: polarity (1 for positive, 0 for negative)
 481  *  sense: 1 for level, 0 for edge
 482  */
 483 static void __init
 484 openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 485 {
 486         openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
 487                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 488                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 489                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 490                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 491                                         OPENPIC_POLARITY_NEGATIVE) |
 492                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 493 }
 494
 495 /*
 496  *  Map an interrupt source to one or more CPUs
 497  */
 498 static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask)
 499 {
 500         if (ISR[irq] == 0)
 501                 return;
 502         if (keepmask != 0)
 503                 physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask;
 504         openpic2_write(&ISR[irq]->Destination, physmask);
 505 }
 506
 507 #ifdef notused
 508 /*
 509  *  Set the sense for an interrupt source (and disable it!)
 510  *
 511  *  sense: 1 for level, 0 for edge
 512  */
 513 static void openpic2_set_sense(u_int irq, int sense)
 514 {
 515         if (ISR[irq] != 0)
 516                 openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
 517                                         OPENPIC_SENSE_LEVEL,
 518                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 519 }
 520 #endif /* notused */
 521
 522 /* No spinlocks, should not be necessary with the OpenPIC
 523  * (1 register = 1 interrupt and we have the desc lock).
 524  */
 525 static void openpic2_ack_irq(unsigned int irq_nr)
 526 {
 527         openpic2_disable_irq(irq_nr);
 528         openpic2_eoi();
 529 }
 530
 531 static void openpic2_end_irq(unsigned int irq_nr)
 532 {
 533         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 534                 openpic2_enable_irq(irq_nr);
 535 }
 536
 537 int
 538 openpic2_get_irq(struct pt_regs *regs)
 539 {
 540         int irq = openpic2_irq();
 541
 542         if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset))
 543                 irq = -1;
 544         return irq;
 545 }
 546
 547 #ifdef CONFIG_PM
 548
 549 /*
 550  * We implement the IRQ controller as a sysdev and put it
 551  * to sleep at powerdown stage (the callback is named suspend,
 552  * but it's old semantics, for the Device Model, it's really
 553  * powerdown). The possible problem is that another sysdev that
 554  * happens to be suspend after this one will have interrupts off,
 555  * that may be an issue... For now, this isn't an issue on pmac
 556  * though...
 557  */
 558
 559 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 560 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 561 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 562 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 563 static int openpic_suspend_count;
 564
 565 static void openpic2_cached_enable_irq(u_int irq)
 566 {
 567         check_arg_irq(irq);
 568         save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK;
 569 }
 570
 571 static void openpic2_cached_disable_irq(u_int irq)
 572 {
 573         check_arg_irq(irq);
 574         save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK;
 575 }
 576
 577 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 578  * we need something better to deal with that... Maybe switch to S1 for
 579  * cpufreq changes
 580  */
 581 int openpic2_suspend(struct sys_device *sysdev, u32 state)
 582 {
 583         int     i;
 584         unsigned long flags;
 585
 586         spin_lock_irqsave(&openpic2_setup_lock, flags);
 587
 588         if (openpic_suspend_count++ > 0) {
 589                 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 590                 return 0;
 591         }
 592
 593         open_pic2.enable = openpic2_cached_enable_irq;
 594         open_pic2.disable = openpic2_cached_disable_irq;
 595
 596         for (i=0; i<NumProcessors; i++) {
 597                 save_cpu_task_pri[i] = openpic2_read(&OpenPIC2->Processor[i].Current_Task_Priority);
 598                 openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority,
 599                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 600         }
 601
 602         for (i=0; i<OPENPIC_NUM_IPI; i++)
 603                 save_ipi_vp[i] = openpic2_read(&OpenPIC2->Global.IPI_Vector_Priority(i));
 604         for (i=0; i<NumSources; i++) {
 605                 if (ISR[i] == 0)
 606                         continue;
 607                 save_irq_src_vp[i] = openpic2_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 608                 save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination);
 609         }
 610
 611         spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 612
 613         return 0;
 614 }
 615
 616 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 617  * we need something better to deal with that... Maybe switch to S1 for
 618  * cpufreq changes
 619  */
 620 int openpic2_resume(struct sys_device *sysdev)
 621 {
 622         int             i;
 623         unsigned long   flags;
 624         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 625                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 626                                         OPENPIC_MASK;
 627
 628         spin_lock_irqsave(&openpic2_setup_lock, flags);
 629
 630         if ((--openpic_suspend_count) > 0) {
 631                 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 632                 return 0;
 633         }
 634
 635         openpic2_reset();
 636
 637         /* OpenPIC sometimes seem to need some time to be fully back up... */
 638         do {
 639                 openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset);
 640         } while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
 641                         != (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset));
 642
 643         openpic2_disable_8259_pass_through();
 644
 645         for (i=0; i<OPENPIC_NUM_IPI; i++)
 646                 openpic2_write(&OpenPIC2->Global.IPI_Vector_Priority(i),
 647                               save_ipi_vp[i]);
 648         for (i=0; i<NumSources; i++) {
 649                 if (ISR[i] == 0)
 650                         continue;
 651                 openpic2_write(&ISR[i]->Destination, save_irq_src_dest[i]);
 652                 openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
 653                 /* make sure mask gets to controller before we return to user */
 654                 do {
 655                         openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
 656                 } while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask)
 657                          != (save_irq_src_vp[i] & vppmask));
 658         }
 659         for (i=0; i<NumProcessors; i++)
 660                 openpic2_write(&OpenPIC2->Processor[i].Current_Task_Priority,
 661                               save_cpu_task_pri[i]);
 662
 663         open_pic2.enable = openpic2_enable_irq;
 664         open_pic2.disable = openpic2_disable_irq;
 665
 666         spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 667
 668         return 0;
 669 }
 670
 671 #endif /* CONFIG_PM */
 672
 673 /* HACK ALERT */
 674 static struct sysdev_class openpic2_sysclass = {
 675         set_kset_name("openpic2"),
 676 };
 677
 678 static struct sys_device device_openpic2 = {
 679         .id             = 0,
 680         .cls            = &openpic2_sysclass,
 681 };
 682
 683 static struct sysdev_driver driver_openpic2 = {
 684 #ifdef CONFIG_PM
 685         .suspend        = &openpic2_suspend,
 686         .resume         = &openpic2_resume,
 687 #endif /* CONFIG_PM */
 688 };
 689
 690 static int __init init_openpic2_sysfs(void)
 691 {
 692         int rc;
 693
 694         if (!OpenPIC2_Addr)
 695                 return -ENODEV;
 696         printk(KERN_DEBUG "Registering openpic2 with sysfs...\n");
 697         rc = sysdev_class_register(&openpic2_sysclass);
 698         if (rc) {
 699                 printk(KERN_ERR "Failed registering openpic sys class\n");
 700                 return -ENODEV;
 701         }
 702         rc = sysdev_register(&device_openpic2);
 703         if (rc) {
 704                 printk(KERN_ERR "Failed registering openpic sys device\n");
 705                 return -ENODEV;
 706         }
 707         rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2);
 708         if (rc) {
 709                 printk(KERN_ERR "Failed registering openpic sys driver\n");
 710                 return -ENODEV;
 711         }
 712         return 0;
 713 }
 714
 715 subsys_initcall(init_openpic2_sysfs);
 716