2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
23 int mindelta, int main_rssi_avg,
24 int alt_rssi_avg, int pkt_count)
26 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
27 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
28 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
33 return sc->ps_enabled &&
34 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
38 struct ieee80211_hdr *hdr)
40 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
43 spin_lock_bh(&sc->wiphy_lock);
44 for (i = 0; i < sc->num_sec_wiphy; i++) {
45 struct ath_wiphy *aphy = sc->sec_wiphy[i];
48 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
54 spin_unlock_bh(&sc->wiphy_lock);
59 * Setup and link descriptors.
61 * 11N: we can no longer afford to self link the last descriptor.
62 * MAC acknowledges BA status as long as it copies frames to host
63 * buffer (or rx fifo). This can incorrectly acknowledge packets
64 * to a sender if last desc is self-linked.
66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
68 struct ath_hw *ah = sc->sc_ah;
69 struct ath_common *common = ath9k_hw_common(ah);
76 ds->ds_link = 0; /* link to null */
77 ds->ds_data = bf->bf_buf_addr;
79 /* virtual addr of the beginning of the buffer. */
82 ds->ds_vdata = skb->data;
85 * setup rx descriptors. The rx_bufsize here tells the hardware
86 * how much data it can DMA to us and that we are prepared
89 ath9k_hw_setuprxdesc(ah, ds,
93 if (sc->rx.rxlink == NULL)
94 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
96 *sc->rx.rxlink = bf->bf_daddr;
98 sc->rx.rxlink = &ds->ds_link;
102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
104 /* XXX block beacon interrupts */
105 ath9k_hw_setantenna(sc->sc_ah, antenna);
106 sc->rx.defant = antenna;
107 sc->rx.rxotherant = 0;
110 static void ath_opmode_init(struct ath_softc *sc)
112 struct ath_hw *ah = sc->sc_ah;
113 struct ath_common *common = ath9k_hw_common(ah);
117 /* configure rx filter */
118 rfilt = ath_calcrxfilter(sc);
119 ath9k_hw_setrxfilter(ah, rfilt);
121 /* configure bssid mask */
122 ath_hw_setbssidmask(common);
124 /* configure operational mode */
125 ath9k_hw_setopmode(ah);
127 /* calculate and install multicast filter */
128 mfilt[0] = mfilt[1] = ~0;
129 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
132 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
133 enum ath9k_rx_qtype qtype)
135 struct ath_hw *ah = sc->sc_ah;
136 struct ath_rx_edma *rx_edma;
140 rx_edma = &sc->rx.rx_edma[qtype];
141 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
144 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
145 list_del_init(&bf->list);
150 memset(skb->data, 0, ah->caps.rx_status_len);
151 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
152 ah->caps.rx_status_len, DMA_TO_DEVICE);
154 SKB_CB_ATHBUF(skb) = bf;
155 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
156 skb_queue_tail(&rx_edma->rx_fifo, skb);
161 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
162 enum ath9k_rx_qtype qtype, int size)
164 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
167 if (list_empty(&sc->rx.rxbuf)) {
168 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
172 while (!list_empty(&sc->rx.rxbuf)) {
175 if (!ath_rx_edma_buf_link(sc, qtype))
183 static void ath_rx_remove_buffer(struct ath_softc *sc,
184 enum ath9k_rx_qtype qtype)
187 struct ath_rx_edma *rx_edma;
190 rx_edma = &sc->rx.rx_edma[qtype];
192 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
193 bf = SKB_CB_ATHBUF(skb);
195 list_add_tail(&bf->list, &sc->rx.rxbuf);
199 static void ath_rx_edma_cleanup(struct ath_softc *sc)
203 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
204 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
206 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
208 dev_kfree_skb_any(bf->bf_mpdu);
211 INIT_LIST_HEAD(&sc->rx.rxbuf);
213 kfree(sc->rx.rx_bufptr);
214 sc->rx.rx_bufptr = NULL;
217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
219 skb_queue_head_init(&rx_edma->rx_fifo);
220 skb_queue_head_init(&rx_edma->rx_buffers);
221 rx_edma->rx_fifo_hwsize = size;
224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
226 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
227 struct ath_hw *ah = sc->sc_ah;
233 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
234 ah->caps.rx_status_len);
236 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
237 ah->caps.rx_lp_qdepth);
238 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
239 ah->caps.rx_hp_qdepth);
241 size = sizeof(struct ath_buf) * nbufs;
242 bf = kzalloc(size, GFP_KERNEL);
246 INIT_LIST_HEAD(&sc->rx.rxbuf);
247 sc->rx.rx_bufptr = bf;
249 for (i = 0; i < nbufs; i++, bf++) {
250 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
256 memset(skb->data, 0, common->rx_bufsize);
259 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
262 if (unlikely(dma_mapping_error(sc->dev,
264 dev_kfree_skb_any(skb);
268 "dma_mapping_error() on RX init\n");
273 list_add_tail(&bf->list, &sc->rx.rxbuf);
279 ath_rx_edma_cleanup(sc);
283 static void ath_edma_start_recv(struct ath_softc *sc)
285 spin_lock_bh(&sc->rx.rxbuflock);
287 ath9k_hw_rxena(sc->sc_ah);
289 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
290 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
292 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
293 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
297 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
299 spin_unlock_bh(&sc->rx.rxbuflock);
302 static void ath_edma_stop_recv(struct ath_softc *sc)
304 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
305 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
308 int ath_rx_init(struct ath_softc *sc, int nbufs)
310 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
315 spin_lock_init(&sc->sc_pcu_lock);
316 sc->sc_flags &= ~SC_OP_RXFLUSH;
317 spin_lock_init(&sc->rx.rxbuflock);
319 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
320 sc->sc_ah->caps.rx_status_len;
322 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
323 return ath_rx_edma_init(sc, nbufs);
325 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
326 common->cachelsz, common->rx_bufsize);
328 /* Initialize rx descriptors */
330 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
334 "failed to allocate rx descriptors: %d\n",
339 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
340 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
348 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
351 if (unlikely(dma_mapping_error(sc->dev,
353 dev_kfree_skb_any(skb);
357 "dma_mapping_error() on RX init\n");
362 sc->rx.rxlink = NULL;
372 void ath_rx_cleanup(struct ath_softc *sc)
374 struct ath_hw *ah = sc->sc_ah;
375 struct ath_common *common = ath9k_hw_common(ah);
379 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
380 ath_rx_edma_cleanup(sc);
383 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
386 dma_unmap_single(sc->dev, bf->bf_buf_addr,
395 if (sc->rx.rxdma.dd_desc_len != 0)
396 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
401 * Calculate the receive filter according to the
402 * operating mode and state:
404 * o always accept unicast, broadcast, and multicast traffic
405 * o maintain current state of phy error reception (the hal
406 * may enable phy error frames for noise immunity work)
407 * o probe request frames are accepted only when operating in
408 * hostap, adhoc, or monitor modes
409 * o enable promiscuous mode according to the interface state
411 * - when operating in adhoc mode so the 802.11 layer creates
412 * node table entries for peers,
413 * - when operating in station mode for collecting rssi data when
414 * the station is otherwise quiet, or
415 * - when operating as a repeater so we see repeater-sta beacons
419 u32 ath_calcrxfilter(struct ath_softc *sc)
421 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
425 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
426 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
427 | ATH9K_RX_FILTER_MCAST;
429 if (sc->rx.rxfilter & FIF_PROBE_REQ)
430 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
433 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
434 * mode interface or when in monitor mode. AP mode does not need this
435 * since it receives all in-BSS frames anyway.
437 if (sc->sc_ah->is_monitoring)
438 rfilt |= ATH9K_RX_FILTER_PROM;
440 if (sc->rx.rxfilter & FIF_CONTROL)
441 rfilt |= ATH9K_RX_FILTER_CONTROL;
443 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
445 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
446 rfilt |= ATH9K_RX_FILTER_MYBEACON;
448 rfilt |= ATH9K_RX_FILTER_BEACON;
450 if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) ||
451 AR_SREV_9285_12_OR_LATER(sc->sc_ah)) &&
452 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
453 (sc->rx.rxfilter & FIF_PSPOLL))
454 rfilt |= ATH9K_RX_FILTER_PSPOLL;
456 if (conf_is_ht(&sc->hw->conf))
457 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
459 if (sc->sec_wiphy || (sc->nvifs > 1) ||
460 (sc->rx.rxfilter & FIF_OTHER_BSS)) {
461 /* The following may also be needed for other older chips */
462 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
463 rfilt |= ATH9K_RX_FILTER_PROM;
464 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
469 #undef RX_FILTER_PRESERVE
472 int ath_startrecv(struct ath_softc *sc)
474 struct ath_hw *ah = sc->sc_ah;
475 struct ath_buf *bf, *tbf;
477 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
478 ath_edma_start_recv(sc);
482 spin_lock_bh(&sc->rx.rxbuflock);
483 if (list_empty(&sc->rx.rxbuf))
486 sc->rx.rxlink = NULL;
487 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
488 ath_rx_buf_link(sc, bf);
491 /* We could have deleted elements so the list may be empty now */
492 if (list_empty(&sc->rx.rxbuf))
495 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
496 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
501 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
503 spin_unlock_bh(&sc->rx.rxbuflock);
508 bool ath_stoprecv(struct ath_softc *sc)
510 struct ath_hw *ah = sc->sc_ah;
511 bool stopped, reset = false;
513 spin_lock_bh(&sc->rx.rxbuflock);
514 ath9k_hw_abortpcurecv(ah);
515 ath9k_hw_setrxfilter(ah, 0);
516 stopped = ath9k_hw_stopdmarecv(ah, &reset);
518 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
519 ath_edma_stop_recv(sc);
521 sc->rx.rxlink = NULL;
522 spin_unlock_bh(&sc->rx.rxbuflock);
524 if (!(ah->ah_flags & AH_UNPLUGGED) &&
525 unlikely(!stopped)) {
526 ath_err(ath9k_hw_common(sc->sc_ah),
527 "Could not stop RX, we could be "
528 "confusing the DMA engine when we start RX up\n");
529 ATH_DBG_WARN_ON_ONCE(!stopped);
531 return stopped && !reset;
534 void ath_flushrecv(struct ath_softc *sc)
536 sc->sc_flags |= SC_OP_RXFLUSH;
537 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
538 ath_rx_tasklet(sc, 1, true);
539 ath_rx_tasklet(sc, 1, false);
540 sc->sc_flags &= ~SC_OP_RXFLUSH;
543 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
545 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
546 struct ieee80211_mgmt *mgmt;
547 u8 *pos, *end, id, elen;
548 struct ieee80211_tim_ie *tim;
550 mgmt = (struct ieee80211_mgmt *)skb->data;
551 pos = mgmt->u.beacon.variable;
552 end = skb->data + skb->len;
554 while (pos + 2 < end) {
557 if (pos + elen > end)
560 if (id == WLAN_EID_TIM) {
561 if (elen < sizeof(*tim))
563 tim = (struct ieee80211_tim_ie *) pos;
564 if (tim->dtim_count != 0)
566 return tim->bitmap_ctrl & 0x01;
575 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
577 struct ieee80211_mgmt *mgmt;
578 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
580 if (skb->len < 24 + 8 + 2 + 2)
583 mgmt = (struct ieee80211_mgmt *)skb->data;
584 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
585 return; /* not from our current AP */
587 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
589 if (sc->ps_flags & PS_BEACON_SYNC) {
590 sc->ps_flags &= ~PS_BEACON_SYNC;
591 ath_dbg(common, ATH_DBG_PS,
592 "Reconfigure Beacon timers based on timestamp from the AP\n");
593 ath_beacon_config(sc, NULL);
596 if (ath_beacon_dtim_pending_cab(skb)) {
598 * Remain awake waiting for buffered broadcast/multicast
599 * frames. If the last broadcast/multicast frame is not
600 * received properly, the next beacon frame will work as
601 * a backup trigger for returning into NETWORK SLEEP state,
602 * so we are waiting for it as well.
604 ath_dbg(common, ATH_DBG_PS,
605 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
606 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
610 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
612 * This can happen if a broadcast frame is dropped or the AP
613 * fails to send a frame indicating that all CAB frames have
616 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
617 ath_dbg(common, ATH_DBG_PS,
618 "PS wait for CAB frames timed out\n");
622 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
624 struct ieee80211_hdr *hdr;
625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
627 hdr = (struct ieee80211_hdr *)skb->data;
629 /* Process Beacon and CAB receive in PS state */
630 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
631 && ieee80211_is_beacon(hdr->frame_control))
632 ath_rx_ps_beacon(sc, skb);
633 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
634 (ieee80211_is_data(hdr->frame_control) ||
635 ieee80211_is_action(hdr->frame_control)) &&
636 is_multicast_ether_addr(hdr->addr1) &&
637 !ieee80211_has_moredata(hdr->frame_control)) {
639 * No more broadcast/multicast frames to be received at this
642 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
643 ath_dbg(common, ATH_DBG_PS,
644 "All PS CAB frames received, back to sleep\n");
645 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
646 !is_multicast_ether_addr(hdr->addr1) &&
647 !ieee80211_has_morefrags(hdr->frame_control)) {
648 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
649 ath_dbg(common, ATH_DBG_PS,
650 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
651 sc->ps_flags & (PS_WAIT_FOR_BEACON |
653 PS_WAIT_FOR_PSPOLL_DATA |
654 PS_WAIT_FOR_TX_ACK));
658 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
659 struct ath_softc *sc, struct sk_buff *skb)
661 struct ieee80211_hdr *hdr;
663 hdr = (struct ieee80211_hdr *)skb->data;
665 /* Send the frame to mac80211 */
666 if (is_multicast_ether_addr(hdr->addr1)) {
669 * Deliver broadcast/multicast frames to all suitable
672 /* TODO: filter based on channel configuration */
673 for (i = 0; i < sc->num_sec_wiphy; i++) {
674 struct ath_wiphy *aphy = sc->sec_wiphy[i];
675 struct sk_buff *nskb;
678 nskb = skb_copy(skb, GFP_ATOMIC);
681 ieee80211_rx(aphy->hw, nskb);
683 ieee80211_rx(sc->hw, skb);
685 /* Deliver unicast frames based on receiver address */
686 ieee80211_rx(hw, skb);
689 static bool ath_edma_get_buffers(struct ath_softc *sc,
690 enum ath9k_rx_qtype qtype)
692 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
693 struct ath_hw *ah = sc->sc_ah;
694 struct ath_common *common = ath9k_hw_common(ah);
699 skb = skb_peek(&rx_edma->rx_fifo);
703 bf = SKB_CB_ATHBUF(skb);
706 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
707 common->rx_bufsize, DMA_FROM_DEVICE);
709 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
710 if (ret == -EINPROGRESS) {
711 /*let device gain the buffer again*/
712 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
713 common->rx_bufsize, DMA_FROM_DEVICE);
717 __skb_unlink(skb, &rx_edma->rx_fifo);
718 if (ret == -EINVAL) {
719 /* corrupt descriptor, skip this one and the following one */
720 list_add_tail(&bf->list, &sc->rx.rxbuf);
721 ath_rx_edma_buf_link(sc, qtype);
722 skb = skb_peek(&rx_edma->rx_fifo);
726 bf = SKB_CB_ATHBUF(skb);
729 __skb_unlink(skb, &rx_edma->rx_fifo);
730 list_add_tail(&bf->list, &sc->rx.rxbuf);
731 ath_rx_edma_buf_link(sc, qtype);
734 skb_queue_tail(&rx_edma->rx_buffers, skb);
739 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
740 struct ath_rx_status *rs,
741 enum ath9k_rx_qtype qtype)
743 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
747 while (ath_edma_get_buffers(sc, qtype));
748 skb = __skb_dequeue(&rx_edma->rx_buffers);
752 bf = SKB_CB_ATHBUF(skb);
753 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
757 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
758 struct ath_rx_status *rs)
760 struct ath_hw *ah = sc->sc_ah;
761 struct ath_common *common = ath9k_hw_common(ah);
766 if (list_empty(&sc->rx.rxbuf)) {
767 sc->rx.rxlink = NULL;
771 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
775 * Must provide the virtual address of the current
776 * descriptor, the physical address, and the virtual
777 * address of the next descriptor in the h/w chain.
778 * This allows the HAL to look ahead to see if the
779 * hardware is done with a descriptor by checking the
780 * done bit in the following descriptor and the address
781 * of the current descriptor the DMA engine is working
782 * on. All this is necessary because of our use of
783 * a self-linked list to avoid rx overruns.
785 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
786 if (ret == -EINPROGRESS) {
787 struct ath_rx_status trs;
789 struct ath_desc *tds;
791 memset(&trs, 0, sizeof(trs));
792 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
793 sc->rx.rxlink = NULL;
797 tbf = list_entry(bf->list.next, struct ath_buf, list);
800 * On some hardware the descriptor status words could
801 * get corrupted, including the done bit. Because of
802 * this, check if the next descriptor's done bit is
805 * If the next descriptor's done bit is set, the current
806 * descriptor has been corrupted. Force s/w to discard
807 * this descriptor and continue...
811 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
812 if (ret == -EINPROGRESS)
820 * Synchronize the DMA transfer with CPU before
821 * 1. accessing the frame
822 * 2. requeueing the same buffer to h/w
824 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
831 /* Assumes you've already done the endian to CPU conversion */
832 static bool ath9k_rx_accept(struct ath_common *common,
833 struct ieee80211_hdr *hdr,
834 struct ieee80211_rx_status *rxs,
835 struct ath_rx_status *rx_stats,
838 #define is_mc_or_valid_tkip_keyix ((is_mc || \
839 (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
840 test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
842 struct ath_hw *ah = common->ah;
844 u8 rx_status_len = ah->caps.rx_status_len;
846 fc = hdr->frame_control;
848 if (!rx_stats->rs_datalen)
851 * rs_status follows rs_datalen so if rs_datalen is too large
852 * we can take a hint that hardware corrupted it, so ignore
855 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
858 /* Only use error bits from the last fragment */
859 if (rx_stats->rs_more)
863 * The rx_stats->rs_status will not be set until the end of the
864 * chained descriptors so it can be ignored if rs_more is set. The
865 * rs_more will be false at the last element of the chained
868 if (rx_stats->rs_status != 0) {
869 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
870 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
871 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
874 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
875 *decrypt_error = true;
876 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
879 * The MIC error bit is only valid if the frame
880 * is not a control frame or fragment, and it was
881 * decrypted using a valid TKIP key.
883 is_mc = !!is_multicast_ether_addr(hdr->addr1);
885 if (!ieee80211_is_ctl(fc) &&
886 !ieee80211_has_morefrags(fc) &&
887 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
888 is_mc_or_valid_tkip_keyix)
889 rxs->flag |= RX_FLAG_MMIC_ERROR;
891 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
894 * Reject error frames with the exception of
895 * decryption and MIC failures. For monitor mode,
896 * we also ignore the CRC error.
898 if (ah->is_monitoring) {
899 if (rx_stats->rs_status &
900 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
904 if (rx_stats->rs_status &
905 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
913 static int ath9k_process_rate(struct ath_common *common,
914 struct ieee80211_hw *hw,
915 struct ath_rx_status *rx_stats,
916 struct ieee80211_rx_status *rxs)
918 struct ieee80211_supported_band *sband;
919 enum ieee80211_band band;
922 band = hw->conf.channel->band;
923 sband = hw->wiphy->bands[band];
925 if (rx_stats->rs_rate & 0x80) {
927 rxs->flag |= RX_FLAG_HT;
928 if (rx_stats->rs_flags & ATH9K_RX_2040)
929 rxs->flag |= RX_FLAG_40MHZ;
930 if (rx_stats->rs_flags & ATH9K_RX_GI)
931 rxs->flag |= RX_FLAG_SHORT_GI;
932 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
936 for (i = 0; i < sband->n_bitrates; i++) {
937 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
941 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
942 rxs->flag |= RX_FLAG_SHORTPRE;
949 * No valid hardware bitrate found -- we should not get here
950 * because hardware has already validated this frame as OK.
952 ath_dbg(common, ATH_DBG_XMIT,
953 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
959 static void ath9k_process_rssi(struct ath_common *common,
960 struct ieee80211_hw *hw,
961 struct ieee80211_hdr *hdr,
962 struct ath_rx_status *rx_stats)
964 struct ath_wiphy *aphy = hw->priv;
965 struct ath_hw *ah = common->ah;
969 if (ah->opmode != NL80211_IFTYPE_STATION)
972 fc = hdr->frame_control;
973 if (!ieee80211_is_beacon(fc) ||
974 compare_ether_addr(hdr->addr3, common->curbssid))
977 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
978 ATH_RSSI_LPF(aphy->last_rssi, rx_stats->rs_rssi);
980 last_rssi = aphy->last_rssi;
981 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
982 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
983 ATH_RSSI_EP_MULTIPLIER);
984 if (rx_stats->rs_rssi < 0)
985 rx_stats->rs_rssi = 0;
987 /* Update Beacon RSSI, this is used by ANI. */
988 ah->stats.avgbrssi = rx_stats->rs_rssi;
992 * For Decrypt or Demic errors, we only mark packet status here and always push
993 * up the frame up to let mac80211 handle the actual error case, be it no
994 * decryption key or real decryption error. This let us keep statistics there.
996 static int ath9k_rx_skb_preprocess(struct ath_common *common,
997 struct ieee80211_hw *hw,
998 struct ieee80211_hdr *hdr,
999 struct ath_rx_status *rx_stats,
1000 struct ieee80211_rx_status *rx_status,
1001 bool *decrypt_error)
1003 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1006 * everything but the rate is checked here, the rate check is done
1007 * separately to avoid doing two lookups for a rate for each frame.
1009 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1012 /* Only use status info from the last fragment */
1013 if (rx_stats->rs_more)
1016 ath9k_process_rssi(common, hw, hdr, rx_stats);
1018 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1021 rx_status->band = hw->conf.channel->band;
1022 rx_status->freq = hw->conf.channel->center_freq;
1023 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1024 rx_status->antenna = rx_stats->rs_antenna;
1025 rx_status->flag |= RX_FLAG_TSFT;
1030 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1031 struct sk_buff *skb,
1032 struct ath_rx_status *rx_stats,
1033 struct ieee80211_rx_status *rxs,
1036 struct ath_hw *ah = common->ah;
1037 struct ieee80211_hdr *hdr;
1038 int hdrlen, padpos, padsize;
1042 /* see if any padding is done by the hw and remove it */
1043 hdr = (struct ieee80211_hdr *) skb->data;
1044 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1045 fc = hdr->frame_control;
1046 padpos = ath9k_cmn_padpos(hdr->frame_control);
1048 /* The MAC header is padded to have 32-bit boundary if the
1049 * packet payload is non-zero. The general calculation for
1050 * padsize would take into account odd header lengths:
1051 * padsize = (4 - padpos % 4) % 4; However, since only
1052 * even-length headers are used, padding can only be 0 or 2
1053 * bytes and we can optimize this a bit. In addition, we must
1054 * not try to remove padding from short control frames that do
1055 * not have payload. */
1056 padsize = padpos & 3;
1057 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1058 memmove(skb->data + padsize, skb->data, padpos);
1059 skb_pull(skb, padsize);
1062 keyix = rx_stats->rs_keyix;
1064 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1065 ieee80211_has_protected(fc)) {
1066 rxs->flag |= RX_FLAG_DECRYPTED;
1067 } else if (ieee80211_has_protected(fc)
1068 && !decrypt_error && skb->len >= hdrlen + 4) {
1069 keyix = skb->data[hdrlen + 3] >> 6;
1071 if (test_bit(keyix, common->keymap))
1072 rxs->flag |= RX_FLAG_DECRYPTED;
1074 if (ah->sw_mgmt_crypto &&
1075 (rxs->flag & RX_FLAG_DECRYPTED) &&
1076 ieee80211_is_mgmt(fc))
1077 /* Use software decrypt for management frames. */
1078 rxs->flag &= ~RX_FLAG_DECRYPTED;
1081 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1082 struct ath_hw_antcomb_conf ant_conf,
1085 antcomb->quick_scan_cnt = 0;
1087 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1088 antcomb->rssi_lna2 = main_rssi_avg;
1089 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1090 antcomb->rssi_lna1 = main_rssi_avg;
1092 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1093 case (0x10): /* LNA2 A-B */
1094 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1095 antcomb->first_quick_scan_conf =
1096 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1097 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1099 case (0x20): /* LNA1 A-B */
1100 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1101 antcomb->first_quick_scan_conf =
1102 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1103 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1105 case (0x21): /* LNA1 LNA2 */
1106 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1107 antcomb->first_quick_scan_conf =
1108 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1109 antcomb->second_quick_scan_conf =
1110 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1112 case (0x12): /* LNA2 LNA1 */
1113 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1114 antcomb->first_quick_scan_conf =
1115 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1116 antcomb->second_quick_scan_conf =
1117 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1119 case (0x13): /* LNA2 A+B */
1120 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1121 antcomb->first_quick_scan_conf =
1122 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1123 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1125 case (0x23): /* LNA1 A+B */
1126 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1127 antcomb->first_quick_scan_conf =
1128 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1129 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1136 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1137 struct ath_hw_antcomb_conf *div_ant_conf,
1138 int main_rssi_avg, int alt_rssi_avg,
1142 switch (antcomb->quick_scan_cnt) {
1144 /* set alt to main, and alt to first conf */
1145 div_ant_conf->main_lna_conf = antcomb->main_conf;
1146 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1149 /* set alt to main, and alt to first conf */
1150 div_ant_conf->main_lna_conf = antcomb->main_conf;
1151 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1152 antcomb->rssi_first = main_rssi_avg;
1153 antcomb->rssi_second = alt_rssi_avg;
1155 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1157 if (ath_is_alt_ant_ratio_better(alt_ratio,
1158 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1159 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1160 main_rssi_avg, alt_rssi_avg,
1161 antcomb->total_pkt_count))
1162 antcomb->first_ratio = true;
1164 antcomb->first_ratio = false;
1165 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1166 if (ath_is_alt_ant_ratio_better(alt_ratio,
1167 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1168 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1169 main_rssi_avg, alt_rssi_avg,
1170 antcomb->total_pkt_count))
1171 antcomb->first_ratio = true;
1173 antcomb->first_ratio = false;
1175 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1176 (alt_rssi_avg > main_rssi_avg +
1177 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1178 (alt_rssi_avg > main_rssi_avg)) &&
1179 (antcomb->total_pkt_count > 50))
1180 antcomb->first_ratio = true;
1182 antcomb->first_ratio = false;
1186 antcomb->alt_good = false;
1187 antcomb->scan_not_start = false;
1188 antcomb->scan = false;
1189 antcomb->rssi_first = main_rssi_avg;
1190 antcomb->rssi_third = alt_rssi_avg;
1192 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1193 antcomb->rssi_lna1 = alt_rssi_avg;
1194 else if (antcomb->second_quick_scan_conf ==
1195 ATH_ANT_DIV_COMB_LNA2)
1196 antcomb->rssi_lna2 = alt_rssi_avg;
1197 else if (antcomb->second_quick_scan_conf ==
1198 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1199 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1200 antcomb->rssi_lna2 = main_rssi_avg;
1201 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1202 antcomb->rssi_lna1 = main_rssi_avg;
1205 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1206 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1207 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1209 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1211 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1212 if (ath_is_alt_ant_ratio_better(alt_ratio,
1213 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1214 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1215 main_rssi_avg, alt_rssi_avg,
1216 antcomb->total_pkt_count))
1217 antcomb->second_ratio = true;
1219 antcomb->second_ratio = false;
1220 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1221 if (ath_is_alt_ant_ratio_better(alt_ratio,
1222 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1223 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1224 main_rssi_avg, alt_rssi_avg,
1225 antcomb->total_pkt_count))
1226 antcomb->second_ratio = true;
1228 antcomb->second_ratio = false;
1230 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1231 (alt_rssi_avg > main_rssi_avg +
1232 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1233 (alt_rssi_avg > main_rssi_avg)) &&
1234 (antcomb->total_pkt_count > 50))
1235 antcomb->second_ratio = true;
1237 antcomb->second_ratio = false;
1240 /* set alt to the conf with maximun ratio */
1241 if (antcomb->first_ratio && antcomb->second_ratio) {
1242 if (antcomb->rssi_second > antcomb->rssi_third) {
1244 if ((antcomb->first_quick_scan_conf ==
1245 ATH_ANT_DIV_COMB_LNA1) ||
1246 (antcomb->first_quick_scan_conf ==
1247 ATH_ANT_DIV_COMB_LNA2))
1248 /* Set alt LNA1 or LNA2*/
1249 if (div_ant_conf->main_lna_conf ==
1250 ATH_ANT_DIV_COMB_LNA2)
1251 div_ant_conf->alt_lna_conf =
1252 ATH_ANT_DIV_COMB_LNA1;
1254 div_ant_conf->alt_lna_conf =
1255 ATH_ANT_DIV_COMB_LNA2;
1257 /* Set alt to A+B or A-B */
1258 div_ant_conf->alt_lna_conf =
1259 antcomb->first_quick_scan_conf;
1260 } else if ((antcomb->second_quick_scan_conf ==
1261 ATH_ANT_DIV_COMB_LNA1) ||
1262 (antcomb->second_quick_scan_conf ==
1263 ATH_ANT_DIV_COMB_LNA2)) {
1264 /* Set alt LNA1 or LNA2 */
1265 if (div_ant_conf->main_lna_conf ==
1266 ATH_ANT_DIV_COMB_LNA2)
1267 div_ant_conf->alt_lna_conf =
1268 ATH_ANT_DIV_COMB_LNA1;
1270 div_ant_conf->alt_lna_conf =
1271 ATH_ANT_DIV_COMB_LNA2;
1273 /* Set alt to A+B or A-B */
1274 div_ant_conf->alt_lna_conf =
1275 antcomb->second_quick_scan_conf;
1277 } else if (antcomb->first_ratio) {
1279 if ((antcomb->first_quick_scan_conf ==
1280 ATH_ANT_DIV_COMB_LNA1) ||
1281 (antcomb->first_quick_scan_conf ==
1282 ATH_ANT_DIV_COMB_LNA2))
1283 /* Set alt LNA1 or LNA2 */
1284 if (div_ant_conf->main_lna_conf ==
1285 ATH_ANT_DIV_COMB_LNA2)
1286 div_ant_conf->alt_lna_conf =
1287 ATH_ANT_DIV_COMB_LNA1;
1289 div_ant_conf->alt_lna_conf =
1290 ATH_ANT_DIV_COMB_LNA2;
1292 /* Set alt to A+B or A-B */
1293 div_ant_conf->alt_lna_conf =
1294 antcomb->first_quick_scan_conf;
1295 } else if (antcomb->second_ratio) {
1297 if ((antcomb->second_quick_scan_conf ==
1298 ATH_ANT_DIV_COMB_LNA1) ||
1299 (antcomb->second_quick_scan_conf ==
1300 ATH_ANT_DIV_COMB_LNA2))
1301 /* Set alt LNA1 or LNA2 */
1302 if (div_ant_conf->main_lna_conf ==
1303 ATH_ANT_DIV_COMB_LNA2)
1304 div_ant_conf->alt_lna_conf =
1305 ATH_ANT_DIV_COMB_LNA1;
1307 div_ant_conf->alt_lna_conf =
1308 ATH_ANT_DIV_COMB_LNA2;
1310 /* Set alt to A+B or A-B */
1311 div_ant_conf->alt_lna_conf =
1312 antcomb->second_quick_scan_conf;
1314 /* main is largest */
1315 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1316 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1317 /* Set alt LNA1 or LNA2 */
1318 if (div_ant_conf->main_lna_conf ==
1319 ATH_ANT_DIV_COMB_LNA2)
1320 div_ant_conf->alt_lna_conf =
1321 ATH_ANT_DIV_COMB_LNA1;
1323 div_ant_conf->alt_lna_conf =
1324 ATH_ANT_DIV_COMB_LNA2;
1326 /* Set alt to A+B or A-B */
1327 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1335 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1337 /* Adjust the fast_div_bias based on main and alt lna conf */
1338 switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1339 case (0x01): /* A-B LNA2 */
1340 ant_conf->fast_div_bias = 0x3b;
1342 case (0x02): /* A-B LNA1 */
1343 ant_conf->fast_div_bias = 0x3d;
1345 case (0x03): /* A-B A+B */
1346 ant_conf->fast_div_bias = 0x1;
1348 case (0x10): /* LNA2 A-B */
1349 ant_conf->fast_div_bias = 0x7;
1351 case (0x12): /* LNA2 LNA1 */
1352 ant_conf->fast_div_bias = 0x2;
1354 case (0x13): /* LNA2 A+B */
1355 ant_conf->fast_div_bias = 0x7;
1357 case (0x20): /* LNA1 A-B */
1358 ant_conf->fast_div_bias = 0x6;
1360 case (0x21): /* LNA1 LNA2 */
1361 ant_conf->fast_div_bias = 0x0;
1363 case (0x23): /* LNA1 A+B */
1364 ant_conf->fast_div_bias = 0x6;
1366 case (0x30): /* A+B A-B */
1367 ant_conf->fast_div_bias = 0x1;
1369 case (0x31): /* A+B LNA2 */
1370 ant_conf->fast_div_bias = 0x3b;
1372 case (0x32): /* A+B LNA1 */
1373 ant_conf->fast_div_bias = 0x3d;
1380 /* Antenna diversity and combining */
1381 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1383 struct ath_hw_antcomb_conf div_ant_conf;
1384 struct ath_ant_comb *antcomb = &sc->ant_comb;
1385 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1386 int curr_main_set, curr_bias;
1387 int main_rssi = rs->rs_rssi_ctl0;
1388 int alt_rssi = rs->rs_rssi_ctl1;
1389 int rx_ant_conf, main_ant_conf;
1390 bool short_scan = false;
1392 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1394 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1397 /* Record packet only when alt_rssi is positive */
1399 antcomb->total_pkt_count++;
1400 antcomb->main_total_rssi += main_rssi;
1401 antcomb->alt_total_rssi += alt_rssi;
1402 if (main_ant_conf == rx_ant_conf)
1403 antcomb->main_recv_cnt++;
1405 antcomb->alt_recv_cnt++;
1408 /* Short scan check */
1409 if (antcomb->scan && antcomb->alt_good) {
1410 if (time_after(jiffies, antcomb->scan_start_time +
1411 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1414 if (antcomb->total_pkt_count ==
1415 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1416 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1417 antcomb->total_pkt_count);
1418 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1423 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1424 rs->rs_moreaggr) && !short_scan)
1427 if (antcomb->total_pkt_count) {
1428 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1429 antcomb->total_pkt_count);
1430 main_rssi_avg = (antcomb->main_total_rssi /
1431 antcomb->total_pkt_count);
1432 alt_rssi_avg = (antcomb->alt_total_rssi /
1433 antcomb->total_pkt_count);
1437 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1438 curr_alt_set = div_ant_conf.alt_lna_conf;
1439 curr_main_set = div_ant_conf.main_lna_conf;
1440 curr_bias = div_ant_conf.fast_div_bias;
1444 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1445 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1446 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1448 antcomb->alt_good = true;
1450 antcomb->alt_good = false;
1454 antcomb->scan = true;
1455 antcomb->scan_not_start = true;
1458 if (!antcomb->scan) {
1459 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1460 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1461 /* Switch main and alt LNA */
1462 div_ant_conf.main_lna_conf =
1463 ATH_ANT_DIV_COMB_LNA2;
1464 div_ant_conf.alt_lna_conf =
1465 ATH_ANT_DIV_COMB_LNA1;
1466 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1467 div_ant_conf.main_lna_conf =
1468 ATH_ANT_DIV_COMB_LNA1;
1469 div_ant_conf.alt_lna_conf =
1470 ATH_ANT_DIV_COMB_LNA2;
1474 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1475 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1476 /* Set alt to another LNA */
1477 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1478 div_ant_conf.alt_lna_conf =
1479 ATH_ANT_DIV_COMB_LNA1;
1480 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1481 div_ant_conf.alt_lna_conf =
1482 ATH_ANT_DIV_COMB_LNA2;
1487 if ((alt_rssi_avg < (main_rssi_avg +
1488 ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1492 if (!antcomb->scan_not_start) {
1493 switch (curr_alt_set) {
1494 case ATH_ANT_DIV_COMB_LNA2:
1495 antcomb->rssi_lna2 = alt_rssi_avg;
1496 antcomb->rssi_lna1 = main_rssi_avg;
1497 antcomb->scan = true;
1499 div_ant_conf.main_lna_conf =
1500 ATH_ANT_DIV_COMB_LNA1;
1501 div_ant_conf.alt_lna_conf =
1502 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1504 case ATH_ANT_DIV_COMB_LNA1:
1505 antcomb->rssi_lna1 = alt_rssi_avg;
1506 antcomb->rssi_lna2 = main_rssi_avg;
1507 antcomb->scan = true;
1509 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1510 div_ant_conf.alt_lna_conf =
1511 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1513 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1514 antcomb->rssi_add = alt_rssi_avg;
1515 antcomb->scan = true;
1517 div_ant_conf.alt_lna_conf =
1518 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1520 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1521 antcomb->rssi_sub = alt_rssi_avg;
1522 antcomb->scan = false;
1523 if (antcomb->rssi_lna2 >
1524 (antcomb->rssi_lna1 +
1525 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1526 /* use LNA2 as main LNA */
1527 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1528 (antcomb->rssi_add > antcomb->rssi_sub)) {
1530 div_ant_conf.main_lna_conf =
1531 ATH_ANT_DIV_COMB_LNA2;
1532 div_ant_conf.alt_lna_conf =
1533 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1534 } else if (antcomb->rssi_sub >
1535 antcomb->rssi_lna1) {
1537 div_ant_conf.main_lna_conf =
1538 ATH_ANT_DIV_COMB_LNA2;
1539 div_ant_conf.alt_lna_conf =
1540 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1543 div_ant_conf.main_lna_conf =
1544 ATH_ANT_DIV_COMB_LNA2;
1545 div_ant_conf.alt_lna_conf =
1546 ATH_ANT_DIV_COMB_LNA1;
1549 /* use LNA1 as main LNA */
1550 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1551 (antcomb->rssi_add > antcomb->rssi_sub)) {
1553 div_ant_conf.main_lna_conf =
1554 ATH_ANT_DIV_COMB_LNA1;
1555 div_ant_conf.alt_lna_conf =
1556 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1557 } else if (antcomb->rssi_sub >
1558 antcomb->rssi_lna1) {
1560 div_ant_conf.main_lna_conf =
1561 ATH_ANT_DIV_COMB_LNA1;
1562 div_ant_conf.alt_lna_conf =
1563 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1566 div_ant_conf.main_lna_conf =
1567 ATH_ANT_DIV_COMB_LNA1;
1568 div_ant_conf.alt_lna_conf =
1569 ATH_ANT_DIV_COMB_LNA2;
1577 if (!antcomb->alt_good) {
1578 antcomb->scan_not_start = false;
1579 /* Set alt to another LNA */
1580 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1581 div_ant_conf.main_lna_conf =
1582 ATH_ANT_DIV_COMB_LNA2;
1583 div_ant_conf.alt_lna_conf =
1584 ATH_ANT_DIV_COMB_LNA1;
1585 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1586 div_ant_conf.main_lna_conf =
1587 ATH_ANT_DIV_COMB_LNA1;
1588 div_ant_conf.alt_lna_conf =
1589 ATH_ANT_DIV_COMB_LNA2;
1595 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1596 main_rssi_avg, alt_rssi_avg,
1599 antcomb->quick_scan_cnt++;
1602 ath_ant_div_conf_fast_divbias(&div_ant_conf);
1604 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1606 antcomb->scan_start_time = jiffies;
1607 antcomb->total_pkt_count = 0;
1608 antcomb->main_total_rssi = 0;
1609 antcomb->alt_total_rssi = 0;
1610 antcomb->main_recv_cnt = 0;
1611 antcomb->alt_recv_cnt = 0;
1614 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1617 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1618 struct ieee80211_rx_status *rxs;
1619 struct ath_hw *ah = sc->sc_ah;
1620 struct ath_common *common = ath9k_hw_common(ah);
1622 * The hw can technically differ from common->hw when using ath9k
1623 * virtual wiphy so to account for that we iterate over the active
1624 * wiphys and find the appropriate wiphy and therefore hw.
1626 struct ieee80211_hw *hw = NULL;
1627 struct ieee80211_hdr *hdr;
1629 bool decrypt_error = false;
1630 struct ath_rx_status rs;
1631 enum ath9k_rx_qtype qtype;
1632 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1634 u8 rx_status_len = ah->caps.rx_status_len;
1637 unsigned long flags;
1640 dma_type = DMA_BIDIRECTIONAL;
1642 dma_type = DMA_FROM_DEVICE;
1644 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1645 spin_lock_bh(&sc->rx.rxbuflock);
1647 tsf = ath9k_hw_gettsf64(ah);
1648 tsf_lower = tsf & 0xffffffff;
1651 /* If handling rx interrupt and flush is in progress => exit */
1652 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1655 memset(&rs, 0, sizeof(rs));
1657 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1659 bf = ath_get_next_rx_buf(sc, &rs);
1669 * Take frame header from the first fragment and RX status from
1673 hdr_skb = sc->rx.frag;
1677 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1678 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1680 hw = ath_get_virt_hw(sc, hdr);
1682 ath_debug_stat_rx(sc, &rs);
1685 * If we're asked to flush receive queue, directly
1686 * chain it back at the queue without processing it.
1689 goto requeue_drop_frag;
1691 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1692 rxs, &decrypt_error);
1694 goto requeue_drop_frag;
1696 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1697 if (rs.rs_tstamp > tsf_lower &&
1698 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1699 rxs->mactime -= 0x100000000ULL;
1701 if (rs.rs_tstamp < tsf_lower &&
1702 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1703 rxs->mactime += 0x100000000ULL;
1705 /* Ensure we always have an skb to requeue once we are done
1706 * processing the current buffer's skb */
1707 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1709 /* If there is no memory we ignore the current RX'd frame,
1710 * tell hardware it can give us a new frame using the old
1711 * skb and put it at the tail of the sc->rx.rxbuf list for
1714 goto requeue_drop_frag;
1716 /* Unmap the frame */
1717 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1721 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1722 if (ah->caps.rx_status_len)
1723 skb_pull(skb, ah->caps.rx_status_len);
1726 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1727 rxs, decrypt_error);
1729 /* We will now give hardware our shiny new allocated skb */
1730 bf->bf_mpdu = requeue_skb;
1731 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1734 if (unlikely(dma_mapping_error(sc->dev,
1735 bf->bf_buf_addr))) {
1736 dev_kfree_skb_any(requeue_skb);
1738 bf->bf_buf_addr = 0;
1739 ath_err(common, "dma_mapping_error() on RX\n");
1740 ath_rx_send_to_mac80211(hw, sc, skb);
1746 * rs_more indicates chained descriptors which can be
1747 * used to link buffers together for a sort of
1748 * scatter-gather operation.
1751 /* too many fragments - cannot handle frame */
1752 dev_kfree_skb_any(sc->rx.frag);
1753 dev_kfree_skb_any(skb);
1761 int space = skb->len - skb_tailroom(hdr_skb);
1765 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1767 goto requeue_drop_frag;
1770 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1772 dev_kfree_skb_any(skb);
1777 * change the default rx antenna if rx diversity chooses the
1778 * other antenna 3 times in a row.
1780 if (sc->rx.defant != rs.rs_antenna) {
1781 if (++sc->rx.rxotherant >= 3)
1782 ath_setdefantenna(sc, rs.rs_antenna);
1784 sc->rx.rxotherant = 0;
1787 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1789 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1791 PS_WAIT_FOR_PSPOLL_DATA)) ||
1792 unlikely(ath9k_check_auto_sleep(sc)))
1794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1796 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1797 ath_ant_comb_scan(sc, &rs);
1799 ath_rx_send_to_mac80211(hw, sc, skb);
1803 dev_kfree_skb_any(sc->rx.frag);
1808 list_add_tail(&bf->list, &sc->rx.rxbuf);
1809 ath_rx_edma_buf_link(sc, qtype);
1811 list_move_tail(&bf->list, &sc->rx.rxbuf);
1812 ath_rx_buf_link(sc, bf);
1816 spin_unlock_bh(&sc->rx.rxbuflock);