drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 {
1063         struct drm_device *dev = crtc->dev;
1064         struct drm_i915_private *dev_priv = dev->dev_private;
1065         struct drm_framebuffer *fb = crtc->fb;
1066         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1067         struct drm_i915_gem_object *obj = intel_fb->obj;
1068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069         int plane, i;
1070         u32 fbc_ctl, fbc_ctl2;
1071
1072         if (fb->pitch == dev_priv->cfb_pitch &&
1073             obj->fence_reg == dev_priv->cfb_fence &&
1074             intel_crtc->plane == dev_priv->cfb_plane &&
1075             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1076                 return;
1077
1078         i8xx_disable_fbc(dev);
1079
1080         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1081
1082         if (fb->pitch < dev_priv->cfb_pitch)
1083                 dev_priv->cfb_pitch = fb->pitch;
1084
1085         /* FBC_CTL wants 64B units */
1086         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1087         dev_priv->cfb_fence = obj->fence_reg;
1088         dev_priv->cfb_plane = intel_crtc->plane;
1089         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1090
1091         /* Clear old tags */
1092         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1093                 I915_WRITE(FBC_TAG + (i * 4), 0);
1094
1095         /* Set it up... */
1096         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1097         if (obj->tiling_mode != I915_TILING_NONE)
1098                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1099         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1100         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1101
1102         /* enable it... */
1103         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1104         if (IS_I945GM(dev))
1105                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1106         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1107         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1108         if (obj->tiling_mode != I915_TILING_NONE)
1109                 fbc_ctl |= dev_priv->cfb_fence;
1110         I915_WRITE(FBC_CONTROL, fbc_ctl);
1111
1112         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1113                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1114 }
1115
1116 void i8xx_disable_fbc(struct drm_device *dev)
1117 {
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119         u32 fbc_ctl;
1120
1121         /* Disable compression */
1122         fbc_ctl = I915_READ(FBC_CONTROL);
1123         if ((fbc_ctl & FBC_CTL_EN) == 0)
1124                 return;
1125
1126         fbc_ctl &= ~FBC_CTL_EN;
1127         I915_WRITE(FBC_CONTROL, fbc_ctl);
1128
1129         /* Wait for compressing bit to clear */
1130         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1131                 DRM_DEBUG_KMS("FBC idle timed out\n");
1132                 return;
1133         }
1134
1135         DRM_DEBUG_KMS("disabled FBC\n");
1136 }
1137
1138 static bool i8xx_fbc_enabled(struct drm_device *dev)
1139 {
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1143 }
1144
1145 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1146 {
1147         struct drm_device *dev = crtc->dev;
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149         struct drm_framebuffer *fb = crtc->fb;
1150         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1151         struct drm_i915_gem_object *obj = intel_fb->obj;
1152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1153         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1154         unsigned long stall_watermark = 200;
1155         u32 dpfc_ctl;
1156
1157         dpfc_ctl = I915_READ(DPFC_CONTROL);
1158         if (dpfc_ctl & DPFC_CTL_EN) {
1159                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1160                     dev_priv->cfb_fence == obj->fence_reg &&
1161                     dev_priv->cfb_plane == intel_crtc->plane &&
1162                     dev_priv->cfb_y == crtc->y)
1163                         return;
1164
1165                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1166                 POSTING_READ(DPFC_CONTROL);
1167                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1168         }
1169
1170         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1171         dev_priv->cfb_fence = obj->fence_reg;
1172         dev_priv->cfb_plane = intel_crtc->plane;
1173         dev_priv->cfb_y = crtc->y;
1174
1175         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1176         if (obj->tiling_mode != I915_TILING_NONE) {
1177                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1178                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1179         } else {
1180                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1181         }
1182
1183         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1184                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1185                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1186         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1187
1188         /* enable it... */
1189         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1190
1191         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1192 }
1193
1194 void g4x_disable_fbc(struct drm_device *dev)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         u32 dpfc_ctl;
1198
1199         /* Disable compression */
1200         dpfc_ctl = I915_READ(DPFC_CONTROL);
1201         if (dpfc_ctl & DPFC_CTL_EN) {
1202                 dpfc_ctl &= ~DPFC_CTL_EN;
1203                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1204
1205                 DRM_DEBUG_KMS("disabled FBC\n");
1206         }
1207 }
1208
1209 static bool g4x_fbc_enabled(struct drm_device *dev)
1210 {
1211         struct drm_i915_private *dev_priv = dev->dev_private;
1212
1213         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1214 }
1215
1216 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1217 {
1218         struct drm_device *dev = crtc->dev;
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220         struct drm_framebuffer *fb = crtc->fb;
1221         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1222         struct drm_i915_gem_object *obj = intel_fb->obj;
1223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1224         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1225         unsigned long stall_watermark = 200;
1226         u32 dpfc_ctl;
1227
1228         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1229         if (dpfc_ctl & DPFC_CTL_EN) {
1230                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1231                     dev_priv->cfb_fence == obj->fence_reg &&
1232                     dev_priv->cfb_plane == intel_crtc->plane &&
1233                     dev_priv->cfb_offset == obj->gtt_offset &&
1234                     dev_priv->cfb_y == crtc->y)
1235                         return;
1236
1237                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1238                 POSTING_READ(ILK_DPFC_CONTROL);
1239                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1240         }
1241
1242         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1243         dev_priv->cfb_fence = obj->fence_reg;
1244         dev_priv->cfb_plane = intel_crtc->plane;
1245         dev_priv->cfb_offset = obj->gtt_offset;
1246         dev_priv->cfb_y = crtc->y;
1247
1248         dpfc_ctl &= DPFC_RESERVED;
1249         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1250         if (obj->tiling_mode != I915_TILING_NONE) {
1251                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1252                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1253         } else {
1254                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1255         }
1256
1257         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1258                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1259                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1260         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1261         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1262         /* enable it... */
1263         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1264
1265         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1266 }
1267
1268 void ironlake_disable_fbc(struct drm_device *dev)
1269 {
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         u32 dpfc_ctl;
1272
1273         /* Disable compression */
1274         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1275         if (dpfc_ctl & DPFC_CTL_EN) {
1276                 dpfc_ctl &= ~DPFC_CTL_EN;
1277                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1278
1279                 DRM_DEBUG_KMS("disabled FBC\n");
1280         }
1281 }
1282
1283 static bool ironlake_fbc_enabled(struct drm_device *dev)
1284 {
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286
1287         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1288 }
1289
1290 bool intel_fbc_enabled(struct drm_device *dev)
1291 {
1292         struct drm_i915_private *dev_priv = dev->dev_private;
1293
1294         if (!dev_priv->display.fbc_enabled)
1295                 return false;
1296
1297         return dev_priv->display.fbc_enabled(dev);
1298 }
1299
1300 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1301 {
1302         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1303
1304         if (!dev_priv->display.enable_fbc)
1305                 return;
1306
1307         dev_priv->display.enable_fbc(crtc, interval);
1308 }
1309
1310 void intel_disable_fbc(struct drm_device *dev)
1311 {
1312         struct drm_i915_private *dev_priv = dev->dev_private;
1313
1314         if (!dev_priv->display.disable_fbc)
1315                 return;
1316
1317         dev_priv->display.disable_fbc(dev);
1318 }
1319
1320 /**
1321  * intel_update_fbc - enable/disable FBC as needed
1322  * @dev: the drm_device
1323  *
1324  * Set up the framebuffer compression hardware at mode set time.  We
1325  * enable it if possible:
1326  *   - plane A only (on pre-965)
1327  *   - no pixel mulitply/line duplication
1328  *   - no alpha buffer discard
1329  *   - no dual wide
1330  *   - framebuffer <= 2048 in width, 1536 in height
1331  *
1332  * We can't assume that any compression will take place (worst case),
1333  * so the compressed buffer has to be the same size as the uncompressed
1334  * one.  It also must reside (along with the line length buffer) in
1335  * stolen memory.
1336  *
1337  * We need to enable/disable FBC on a global basis.
1338  */
1339 static void intel_update_fbc(struct drm_device *dev)
1340 {
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         struct drm_crtc *crtc = NULL, *tmp_crtc;
1343         struct intel_crtc *intel_crtc;
1344         struct drm_framebuffer *fb;
1345         struct intel_framebuffer *intel_fb;
1346         struct drm_i915_gem_object *obj;
1347
1348         DRM_DEBUG_KMS("\n");
1349
1350         if (!i915_powersave)
1351                 return;
1352
1353         if (!I915_HAS_FBC(dev))
1354                 return;
1355
1356         /*
1357          * If FBC is already on, we just have to verify that we can
1358          * keep it that way...
1359          * Need to disable if:
1360          *   - more than one pipe is active
1361          *   - changing FBC params (stride, fence, mode)
1362          *   - new fb is too large to fit in compressed buffer
1363          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1364          */
1365         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1366                 if (tmp_crtc->enabled) {
1367                         if (crtc) {
1368                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1369                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1370                                 goto out_disable;
1371                         }
1372                         crtc = tmp_crtc;
1373                 }
1374         }
1375
1376         if (!crtc || crtc->fb == NULL) {
1377                 DRM_DEBUG_KMS("no output, disabling\n");
1378                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1379                 goto out_disable;
1380         }
1381
1382         intel_crtc = to_intel_crtc(crtc);
1383         fb = crtc->fb;
1384         intel_fb = to_intel_framebuffer(fb);
1385         obj = intel_fb->obj;
1386
1387         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1388                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1389                               "compression\n");
1390                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1391                 goto out_disable;
1392         }
1393         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1394             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1395                 DRM_DEBUG_KMS("mode incompatible with compression, "
1396                               "disabling\n");
1397                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1398                 goto out_disable;
1399         }
1400         if ((crtc->mode.hdisplay > 2048) ||
1401             (crtc->mode.vdisplay > 1536)) {
1402                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1403                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1404                 goto out_disable;
1405         }
1406         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1407                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1408                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1409                 goto out_disable;
1410         }
1411         if (obj->tiling_mode != I915_TILING_X) {
1412                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1413                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1414                 goto out_disable;
1415         }
1416
1417         /* If the kernel debugger is active, always disable compression */
1418         if (in_dbg_master())
1419                 goto out_disable;
1420
1421         intel_enable_fbc(crtc, 500);
1422         return;
1423
1424 out_disable:
1425         /* Multiple disables should be harmless */
1426         if (intel_fbc_enabled(dev)) {
1427                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1428                 intel_disable_fbc(dev);
1429         }
1430 }
1431
1432 int
1433 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1434                            struct drm_i915_gem_object *obj,
1435                            struct intel_ring_buffer *pipelined)
1436 {
1437         u32 alignment;
1438         int ret;
1439
1440         switch (obj->tiling_mode) {
1441         case I915_TILING_NONE:
1442                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1443                         alignment = 128 * 1024;
1444                 else if (INTEL_INFO(dev)->gen >= 4)
1445                         alignment = 4 * 1024;
1446                 else
1447                         alignment = 64 * 1024;
1448                 break;
1449         case I915_TILING_X:
1450                 /* pin() will align the object as required by fence */
1451                 alignment = 0;
1452                 break;
1453         case I915_TILING_Y:
1454                 /* FIXME: Is this true? */
1455                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1456                 return -EINVAL;
1457         default:
1458                 BUG();
1459         }
1460
1461         ret = i915_gem_object_pin(obj, alignment, true);
1462         if (ret)
1463                 return ret;
1464
1465         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1466         if (ret)
1467                 goto err_unpin;
1468
1469         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1470          * fence, whereas 965+ only requires a fence if using
1471          * framebuffer compression.  For simplicity, we always install
1472          * a fence as the cost is not that onerous.
1473          */
1474         if (obj->tiling_mode != I915_TILING_NONE) {
1475                 ret = i915_gem_object_get_fence(obj, pipelined, false);
1476                 if (ret)
1477                         goto err_unpin;
1478         }
1479
1480         return 0;
1481
1482 err_unpin:
1483         i915_gem_object_unpin(obj);
1484         return ret;
1485 }
1486
1487 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1488 static int
1489 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1490                            int x, int y, enum mode_set_atomic state)
1491 {
1492         struct drm_device *dev = crtc->dev;
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495         struct intel_framebuffer *intel_fb;
1496         struct drm_i915_gem_object *obj;
1497         int plane = intel_crtc->plane;
1498         unsigned long Start, Offset;
1499         u32 dspcntr;
1500         u32 reg;
1501
1502         switch (plane) {
1503         case 0:
1504         case 1:
1505                 break;
1506         default:
1507                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1508                 return -EINVAL;
1509         }
1510
1511         intel_fb = to_intel_framebuffer(fb);
1512         obj = intel_fb->obj;
1513
1514         reg = DSPCNTR(plane);
1515         dspcntr = I915_READ(reg);
1516         /* Mask out pixel format bits in case we change it */
1517         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1518         switch (fb->bits_per_pixel) {
1519         case 8:
1520                 dspcntr |= DISPPLANE_8BPP;
1521                 break;
1522         case 16:
1523                 if (fb->depth == 15)
1524                         dspcntr |= DISPPLANE_15_16BPP;
1525                 else
1526                         dspcntr |= DISPPLANE_16BPP;
1527                 break;
1528         case 24:
1529         case 32:
1530                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1531                 break;
1532         default:
1533                 DRM_ERROR("Unknown color depth\n");
1534                 return -EINVAL;
1535         }
1536         if (INTEL_INFO(dev)->gen >= 4) {
1537                 if (obj->tiling_mode != I915_TILING_NONE)
1538                         dspcntr |= DISPPLANE_TILED;
1539                 else
1540                         dspcntr &= ~DISPPLANE_TILED;
1541         }
1542
1543         if (HAS_PCH_SPLIT(dev))
1544                 /* must disable */
1545                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1546
1547         I915_WRITE(reg, dspcntr);
1548
1549         Start = obj->gtt_offset;
1550         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1551
1552         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1553                       Start, Offset, x, y, fb->pitch);
1554         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1555         if (INTEL_INFO(dev)->gen >= 4) {
1556                 I915_WRITE(DSPSURF(plane), Start);
1557                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1558                 I915_WRITE(DSPADDR(plane), Offset);
1559         } else
1560                 I915_WRITE(DSPADDR(plane), Start + Offset);
1561         POSTING_READ(reg);
1562
1563         intel_update_fbc(dev);
1564         intel_increase_pllclock(crtc);
1565
1566         return 0;
1567 }
1568
1569 static int
1570 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1571                     struct drm_framebuffer *old_fb)
1572 {
1573         struct drm_device *dev = crtc->dev;
1574         struct drm_i915_master_private *master_priv;
1575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1576         int ret;
1577
1578         /* no fb bound */
1579         if (!crtc->fb) {
1580                 DRM_DEBUG_KMS("No FB bound\n");
1581                 return 0;
1582         }
1583
1584         switch (intel_crtc->plane) {
1585         case 0:
1586         case 1:
1587                 break;
1588         default:
1589                 return -EINVAL;
1590         }
1591
1592         mutex_lock(&dev->struct_mutex);
1593         ret = intel_pin_and_fence_fb_obj(dev,
1594                                          to_intel_framebuffer(crtc->fb)->obj,
1595                                          NULL);
1596         if (ret != 0) {
1597                 mutex_unlock(&dev->struct_mutex);
1598                 return ret;
1599         }
1600
1601         if (old_fb) {
1602                 struct drm_i915_private *dev_priv = dev->dev_private;
1603                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1604
1605                 wait_event(dev_priv->pending_flip_queue,
1606                            atomic_read(&obj->pending_flip) == 0);
1607
1608                 /* Big Hammer, we also need to ensure that any pending
1609                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1610                  * current scanout is retired before unpinning the old
1611                  * framebuffer.
1612                  */
1613                 ret = i915_gem_object_flush_gpu(obj, false);
1614                 if (ret) {
1615                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1616                         mutex_unlock(&dev->struct_mutex);
1617                         return ret;
1618                 }
1619         }
1620
1621         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1622                                          LEAVE_ATOMIC_MODE_SET);
1623         if (ret) {
1624                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1625                 mutex_unlock(&dev->struct_mutex);
1626                 return ret;
1627         }
1628
1629         if (old_fb) {
1630                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1631                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1632         }
1633
1634         mutex_unlock(&dev->struct_mutex);
1635
1636         if (!dev->primary->master)
1637                 return 0;
1638
1639         master_priv = dev->primary->master->driver_priv;
1640         if (!master_priv->sarea_priv)
1641                 return 0;
1642
1643         if (intel_crtc->pipe) {
1644                 master_priv->sarea_priv->pipeB_x = x;
1645                 master_priv->sarea_priv->pipeB_y = y;
1646         } else {
1647                 master_priv->sarea_priv->pipeA_x = x;
1648                 master_priv->sarea_priv->pipeA_y = y;
1649         }
1650
1651         return 0;
1652 }
1653
1654 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1655 {
1656         struct drm_device *dev = crtc->dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         u32 dpa_ctl;
1659
1660         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1661         dpa_ctl = I915_READ(DP_A);
1662         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1663
1664         if (clock < 200000) {
1665                 u32 temp;
1666                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1667                 /* workaround for 160Mhz:
1668                    1) program 0x4600c bits 15:0 = 0x8124
1669                    2) program 0x46010 bit 0 = 1
1670                    3) program 0x46034 bit 24 = 1
1671                    4) program 0x64000 bit 14 = 1
1672                    */
1673                 temp = I915_READ(0x4600c);
1674                 temp &= 0xffff0000;
1675                 I915_WRITE(0x4600c, temp | 0x8124);
1676
1677                 temp = I915_READ(0x46010);
1678                 I915_WRITE(0x46010, temp | 1);
1679
1680                 temp = I915_READ(0x46034);
1681                 I915_WRITE(0x46034, temp | (1 << 24));
1682         } else {
1683                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1684         }
1685         I915_WRITE(DP_A, dpa_ctl);
1686
1687         POSTING_READ(DP_A);
1688         udelay(500);
1689 }
1690
1691 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1692 {
1693         struct drm_device *dev = crtc->dev;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1696         int pipe = intel_crtc->pipe;
1697         u32 reg, temp;
1698
1699         /* enable normal train */
1700         reg = FDI_TX_CTL(pipe);
1701         temp = I915_READ(reg);
1702         temp &= ~FDI_LINK_TRAIN_NONE;
1703         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1704         I915_WRITE(reg, temp);
1705
1706         reg = FDI_RX_CTL(pipe);
1707         temp = I915_READ(reg);
1708         if (HAS_PCH_CPT(dev)) {
1709                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1710                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1711         } else {
1712                 temp &= ~FDI_LINK_TRAIN_NONE;
1713                 temp |= FDI_LINK_TRAIN_NONE;
1714         }
1715         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1716
1717         /* wait one idle pattern time */
1718         POSTING_READ(reg);
1719         udelay(1000);
1720 }
1721
1722 /* The FDI link training functions for ILK/Ibexpeak. */
1723 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1724 {
1725         struct drm_device *dev = crtc->dev;
1726         struct drm_i915_private *dev_priv = dev->dev_private;
1727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1728         int pipe = intel_crtc->pipe;
1729         u32 reg, temp, tries;
1730
1731         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1732            for train result */
1733         reg = FDI_RX_IMR(pipe);
1734         temp = I915_READ(reg);
1735         temp &= ~FDI_RX_SYMBOL_LOCK;
1736         temp &= ~FDI_RX_BIT_LOCK;
1737         I915_WRITE(reg, temp);
1738         I915_READ(reg);
1739         udelay(150);
1740
1741         /* enable CPU FDI TX and PCH FDI RX */
1742         reg = FDI_TX_CTL(pipe);
1743         temp = I915_READ(reg);
1744         temp &= ~(7 << 19);
1745         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1746         temp &= ~FDI_LINK_TRAIN_NONE;
1747         temp |= FDI_LINK_TRAIN_PATTERN_1;
1748         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1749
1750         reg = FDI_RX_CTL(pipe);
1751         temp = I915_READ(reg);
1752         temp &= ~FDI_LINK_TRAIN_NONE;
1753         temp |= FDI_LINK_TRAIN_PATTERN_1;
1754         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1755
1756         POSTING_READ(reg);
1757         udelay(150);
1758
1759         /* Ironlake workaround, enable clock pointer after FDI enable*/
1760         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1761
1762         reg = FDI_RX_IIR(pipe);
1763         for (tries = 0; tries < 5; tries++) {
1764                 temp = I915_READ(reg);
1765                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1766
1767                 if ((temp & FDI_RX_BIT_LOCK)) {
1768                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1769                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1770                         break;
1771                 }
1772         }
1773         if (tries == 5)
1774                 DRM_ERROR("FDI train 1 fail!\n");
1775
1776         /* Train 2 */
1777         reg = FDI_TX_CTL(pipe);
1778         temp = I915_READ(reg);
1779         temp &= ~FDI_LINK_TRAIN_NONE;
1780         temp |= FDI_LINK_TRAIN_PATTERN_2;
1781         I915_WRITE(reg, temp);
1782
1783         reg = FDI_RX_CTL(pipe);
1784         temp = I915_READ(reg);
1785         temp &= ~FDI_LINK_TRAIN_NONE;
1786         temp |= FDI_LINK_TRAIN_PATTERN_2;
1787         I915_WRITE(reg, temp);
1788
1789         POSTING_READ(reg);
1790         udelay(150);
1791
1792         reg = FDI_RX_IIR(pipe);
1793         for (tries = 0; tries < 5; tries++) {
1794                 temp = I915_READ(reg);
1795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1796
1797                 if (temp & FDI_RX_SYMBOL_LOCK) {
1798                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1799                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1800                         break;
1801                 }
1802         }
1803         if (tries == 5)
1804                 DRM_ERROR("FDI train 2 fail!\n");
1805
1806         DRM_DEBUG_KMS("FDI train done\n");
1807
1808 }
1809
1810 static const int const snb_b_fdi_train_param [] = {
1811         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1812         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1813         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1814         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1815 };
1816
1817 /* The FDI link training functions for SNB/Cougarpoint. */
1818 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1819 {
1820         struct drm_device *dev = crtc->dev;
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823         int pipe = intel_crtc->pipe;
1824         u32 reg, temp, i;
1825
1826         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1827            for train result */
1828         reg = FDI_RX_IMR(pipe);
1829         temp = I915_READ(reg);
1830         temp &= ~FDI_RX_SYMBOL_LOCK;
1831         temp &= ~FDI_RX_BIT_LOCK;
1832         I915_WRITE(reg, temp);
1833
1834         POSTING_READ(reg);
1835         udelay(150);
1836
1837         /* enable CPU FDI TX and PCH FDI RX */
1838         reg = FDI_TX_CTL(pipe);
1839         temp = I915_READ(reg);
1840         temp &= ~(7 << 19);
1841         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1842         temp &= ~FDI_LINK_TRAIN_NONE;
1843         temp |= FDI_LINK_TRAIN_PATTERN_1;
1844         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1845         /* SNB-B */
1846         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1847         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1848
1849         reg = FDI_RX_CTL(pipe);
1850         temp = I915_READ(reg);
1851         if (HAS_PCH_CPT(dev)) {
1852                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1853                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1854         } else {
1855                 temp &= ~FDI_LINK_TRAIN_NONE;
1856                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1857         }
1858         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1859
1860         POSTING_READ(reg);
1861         udelay(150);
1862
1863         for (i = 0; i < 4; i++ ) {
1864                 reg = FDI_TX_CTL(pipe);
1865                 temp = I915_READ(reg);
1866                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1867                 temp |= snb_b_fdi_train_param[i];
1868                 I915_WRITE(reg, temp);
1869
1870                 POSTING_READ(reg);
1871                 udelay(500);
1872
1873                 reg = FDI_RX_IIR(pipe);
1874                 temp = I915_READ(reg);
1875                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1876
1877                 if (temp & FDI_RX_BIT_LOCK) {
1878                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1879                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1880                         break;
1881                 }
1882         }
1883         if (i == 4)
1884                 DRM_ERROR("FDI train 1 fail!\n");
1885
1886         /* Train 2 */
1887         reg = FDI_TX_CTL(pipe);
1888         temp = I915_READ(reg);
1889         temp &= ~FDI_LINK_TRAIN_NONE;
1890         temp |= FDI_LINK_TRAIN_PATTERN_2;
1891         if (IS_GEN6(dev)) {
1892                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1893                 /* SNB-B */
1894                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1895         }
1896         I915_WRITE(reg, temp);
1897
1898         reg = FDI_RX_CTL(pipe);
1899         temp = I915_READ(reg);
1900         if (HAS_PCH_CPT(dev)) {
1901                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1902                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1903         } else {
1904                 temp &= ~FDI_LINK_TRAIN_NONE;
1905                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1906         }
1907         I915_WRITE(reg, temp);
1908
1909         POSTING_READ(reg);
1910         udelay(150);
1911
1912         for (i = 0; i < 4; i++ ) {
1913                 reg = FDI_TX_CTL(pipe);
1914                 temp = I915_READ(reg);
1915                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1916                 temp |= snb_b_fdi_train_param[i];
1917                 I915_WRITE(reg, temp);
1918
1919                 POSTING_READ(reg);
1920                 udelay(500);
1921
1922                 reg = FDI_RX_IIR(pipe);
1923                 temp = I915_READ(reg);
1924                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1925
1926                 if (temp & FDI_RX_SYMBOL_LOCK) {
1927                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1928                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1929                         break;
1930                 }
1931         }
1932         if (i == 4)
1933                 DRM_ERROR("FDI train 2 fail!\n");
1934
1935         DRM_DEBUG_KMS("FDI train done.\n");
1936 }
1937
1938 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1939 {
1940         struct drm_device *dev = crtc->dev;
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1943         int pipe = intel_crtc->pipe;
1944         u32 reg, temp;
1945
1946         /* Write the TU size bits so error detection works */
1947         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1948                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1949
1950         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1951         reg = FDI_RX_CTL(pipe);
1952         temp = I915_READ(reg);
1953         temp &= ~((0x7 << 19) | (0x7 << 16));
1954         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1955         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1956         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1957
1958         POSTING_READ(reg);
1959         udelay(200);
1960
1961         /* Switch from Rawclk to PCDclk */
1962         temp = I915_READ(reg);
1963         I915_WRITE(reg, temp | FDI_PCDCLK);
1964
1965         POSTING_READ(reg);
1966         udelay(200);
1967
1968         /* Enable CPU FDI TX PLL, always on for Ironlake */
1969         reg = FDI_TX_CTL(pipe);
1970         temp = I915_READ(reg);
1971         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1972                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1973
1974                 POSTING_READ(reg);
1975                 udelay(100);
1976         }
1977 }
1978
1979 static void intel_flush_display_plane(struct drm_device *dev,
1980                                       int plane)
1981 {
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         u32 reg = DSPADDR(plane);
1984         I915_WRITE(reg, I915_READ(reg));
1985 }
1986
1987 /*
1988  * When we disable a pipe, we need to clear any pending scanline wait events
1989  * to avoid hanging the ring, which we assume we are waiting on.
1990  */
1991 static void intel_clear_scanline_wait(struct drm_device *dev)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         struct intel_ring_buffer *ring;
1995         u32 tmp;
1996
1997         if (IS_GEN2(dev))
1998                 /* Can't break the hang on i8xx */
1999                 return;
2000
2001         ring = LP_RING(dev_priv);
2002         tmp = I915_READ_CTL(ring);
2003         if (tmp & RING_WAIT)
2004                 I915_WRITE_CTL(ring, tmp);
2005 }
2006
2007 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2008 {
2009         struct drm_i915_gem_object *obj;
2010         struct drm_i915_private *dev_priv;
2011
2012         if (crtc->fb == NULL)
2013                 return;
2014
2015         obj = to_intel_framebuffer(crtc->fb)->obj;
2016         dev_priv = crtc->dev->dev_private;
2017         wait_event(dev_priv->pending_flip_queue,
2018                    atomic_read(&obj->pending_flip) == 0);
2019 }
2020
2021 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2022 {
2023         struct drm_device *dev = crtc->dev;
2024         struct drm_i915_private *dev_priv = dev->dev_private;
2025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2026         int pipe = intel_crtc->pipe;
2027         int plane = intel_crtc->plane;
2028         u32 reg, temp;
2029
2030         if (intel_crtc->active)
2031                 return;
2032
2033         intel_crtc->active = true;
2034         intel_update_watermarks(dev);
2035
2036         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2037                 temp = I915_READ(PCH_LVDS);
2038                 if ((temp & LVDS_PORT_EN) == 0)
2039                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2040         }
2041
2042         ironlake_fdi_enable(crtc);
2043
2044         /* Enable panel fitting for LVDS */
2045         if (dev_priv->pch_pf_size &&
2046             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2047                 /* Force use of hard-coded filter coefficients
2048                  * as some pre-programmed values are broken,
2049                  * e.g. x201.
2050                  */
2051                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2052                            PF_ENABLE | PF_FILTER_MED_3x3);
2053                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2054                            dev_priv->pch_pf_pos);
2055                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2056                            dev_priv->pch_pf_size);
2057         }
2058
2059         /* Enable CPU pipe */
2060         reg = PIPECONF(pipe);
2061         temp = I915_READ(reg);
2062         if ((temp & PIPECONF_ENABLE) == 0) {
2063                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2064                 POSTING_READ(reg);
2065                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2066         }
2067
2068         /* configure and enable CPU plane */
2069         reg = DSPCNTR(plane);
2070         temp = I915_READ(reg);
2071         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2072                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2073                 intel_flush_display_plane(dev, plane);
2074         }
2075
2076         /* For PCH output, training FDI link */
2077         if (IS_GEN6(dev))
2078                 gen6_fdi_link_train(crtc);
2079         else
2080                 ironlake_fdi_link_train(crtc);
2081
2082         /* enable PCH DPLL */
2083         reg = PCH_DPLL(pipe);
2084         temp = I915_READ(reg);
2085         if ((temp & DPLL_VCO_ENABLE) == 0) {
2086                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2087                 POSTING_READ(reg);
2088                 udelay(200);
2089         }
2090
2091         if (HAS_PCH_CPT(dev)) {
2092                 /* Be sure PCH DPLL SEL is set */
2093                 temp = I915_READ(PCH_DPLL_SEL);
2094                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2095                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2096                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2097                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2098                 I915_WRITE(PCH_DPLL_SEL, temp);
2099         }
2100
2101         /* set transcoder timing */
2102         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2103         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2104         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2105
2106         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2107         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2108         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2109
2110         intel_fdi_normal_train(crtc);
2111
2112         /* For PCH DP, enable TRANS_DP_CTL */
2113         if (HAS_PCH_CPT(dev) &&
2114             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2115                 reg = TRANS_DP_CTL(pipe);
2116                 temp = I915_READ(reg);
2117                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2118                           TRANS_DP_SYNC_MASK |
2119                           TRANS_DP_BPC_MASK);
2120                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2121                          TRANS_DP_ENH_FRAMING);
2122                 temp |= TRANS_DP_8BPC;
2123
2124                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2125                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2126                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2127                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2128
2129                 switch (intel_trans_dp_port_sel(crtc)) {
2130                 case PCH_DP_B:
2131                         temp |= TRANS_DP_PORT_SEL_B;
2132                         break;
2133                 case PCH_DP_C:
2134                         temp |= TRANS_DP_PORT_SEL_C;
2135                         break;
2136                 case PCH_DP_D:
2137                         temp |= TRANS_DP_PORT_SEL_D;
2138                         break;
2139                 default:
2140                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2141                         temp |= TRANS_DP_PORT_SEL_B;
2142                         break;
2143                 }
2144
2145                 I915_WRITE(reg, temp);
2146         }
2147
2148         /* enable PCH transcoder */
2149         reg = TRANSCONF(pipe);
2150         temp = I915_READ(reg);
2151         /*
2152          * make the BPC in transcoder be consistent with
2153          * that in pipeconf reg.
2154          */
2155         temp &= ~PIPE_BPC_MASK;
2156         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2157         I915_WRITE(reg, temp | TRANS_ENABLE);
2158         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2159                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2160
2161         intel_crtc_load_lut(crtc);
2162         intel_update_fbc(dev);
2163         intel_crtc_update_cursor(crtc, true);
2164 }
2165
2166 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2167 {
2168         struct drm_device *dev = crtc->dev;
2169         struct drm_i915_private *dev_priv = dev->dev_private;
2170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171         int pipe = intel_crtc->pipe;
2172         int plane = intel_crtc->plane;
2173         u32 reg, temp;
2174
2175         if (!intel_crtc->active)
2176                 return;
2177
2178         intel_crtc_wait_for_pending_flips(crtc);
2179         drm_vblank_off(dev, pipe);
2180         intel_crtc_update_cursor(crtc, false);
2181
2182         /* Disable display plane */
2183         reg = DSPCNTR(plane);
2184         temp = I915_READ(reg);
2185         if (temp & DISPLAY_PLANE_ENABLE) {
2186                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2187                 intel_flush_display_plane(dev, plane);
2188         }
2189
2190         if (dev_priv->cfb_plane == plane &&
2191             dev_priv->display.disable_fbc)
2192                 dev_priv->display.disable_fbc(dev);
2193
2194         /* disable cpu pipe, disable after all planes disabled */
2195         reg = PIPECONF(pipe);
2196         temp = I915_READ(reg);
2197         if (temp & PIPECONF_ENABLE) {
2198                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2199                 POSTING_READ(reg);
2200                 /* wait for cpu pipe off, pipe state */
2201                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2202         }
2203
2204         /* Disable PF */
2205         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2206         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2207
2208         /* disable CPU FDI tx and PCH FDI rx */
2209         reg = FDI_TX_CTL(pipe);
2210         temp = I915_READ(reg);
2211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2212         POSTING_READ(reg);
2213
2214         reg = FDI_RX_CTL(pipe);
2215         temp = I915_READ(reg);
2216         temp &= ~(0x7 << 16);
2217         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2219
2220         POSTING_READ(reg);
2221         udelay(100);
2222
2223         /* Ironlake workaround, disable clock pointer after downing FDI */
2224         if (HAS_PCH_IBX(dev))
2225                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2226                            I915_READ(FDI_RX_CHICKEN(pipe) &
2227                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2228
2229         /* still set train pattern 1 */
2230         reg = FDI_TX_CTL(pipe);
2231         temp = I915_READ(reg);
2232         temp &= ~FDI_LINK_TRAIN_NONE;
2233         temp |= FDI_LINK_TRAIN_PATTERN_1;
2234         I915_WRITE(reg, temp);
2235
2236         reg = FDI_RX_CTL(pipe);
2237         temp = I915_READ(reg);
2238         if (HAS_PCH_CPT(dev)) {
2239                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2240                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2241         } else {
2242                 temp &= ~FDI_LINK_TRAIN_NONE;
2243                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2244         }
2245         /* BPC in FDI rx is consistent with that in PIPECONF */
2246         temp &= ~(0x07 << 16);
2247         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2248         I915_WRITE(reg, temp);
2249
2250         POSTING_READ(reg);
2251         udelay(100);
2252
2253         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2254                 temp = I915_READ(PCH_LVDS);
2255                 if (temp & LVDS_PORT_EN) {
2256                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2257                         POSTING_READ(PCH_LVDS);
2258                         udelay(100);
2259                 }
2260         }
2261
2262         /* disable PCH transcoder */
2263         reg = TRANSCONF(plane);
2264         temp = I915_READ(reg);
2265         if (temp & TRANS_ENABLE) {
2266                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2267                 /* wait for PCH transcoder off, transcoder state */
2268                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2269                         DRM_ERROR("failed to disable transcoder\n");
2270         }
2271
2272         if (HAS_PCH_CPT(dev)) {
2273                 /* disable TRANS_DP_CTL */
2274                 reg = TRANS_DP_CTL(pipe);
2275                 temp = I915_READ(reg);
2276                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2277                 I915_WRITE(reg, temp);
2278
2279                 /* disable DPLL_SEL */
2280                 temp = I915_READ(PCH_DPLL_SEL);
2281                 if (pipe == 0)
2282                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2283                 else
2284                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2285                 I915_WRITE(PCH_DPLL_SEL, temp);
2286         }
2287
2288         /* disable PCH DPLL */
2289         reg = PCH_DPLL(pipe);
2290         temp = I915_READ(reg);
2291         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2292
2293         /* Switch from PCDclk to Rawclk */
2294         reg = FDI_RX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2297
2298         /* Disable CPU FDI TX PLL */
2299         reg = FDI_TX_CTL(pipe);
2300         temp = I915_READ(reg);
2301         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2302
2303         POSTING_READ(reg);
2304         udelay(100);
2305
2306         reg = FDI_RX_CTL(pipe);
2307         temp = I915_READ(reg);
2308         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2309
2310         /* Wait for the clocks to turn off. */
2311         POSTING_READ(reg);
2312         udelay(100);
2313
2314         intel_crtc->active = false;
2315         intel_update_watermarks(dev);
2316         intel_update_fbc(dev);
2317         intel_clear_scanline_wait(dev);
2318 }
2319
2320 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2321 {
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         int plane = intel_crtc->plane;
2325
2326         /* XXX: When our outputs are all unaware of DPMS modes other than off
2327          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2328          */
2329         switch (mode) {
2330         case DRM_MODE_DPMS_ON:
2331         case DRM_MODE_DPMS_STANDBY:
2332         case DRM_MODE_DPMS_SUSPEND:
2333                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2334                 ironlake_crtc_enable(crtc);
2335                 break;
2336
2337         case DRM_MODE_DPMS_OFF:
2338                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2339                 ironlake_crtc_disable(crtc);
2340                 break;
2341         }
2342 }
2343
2344 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2345 {
2346         if (!enable && intel_crtc->overlay) {
2347                 struct drm_device *dev = intel_crtc->base.dev;
2348
2349                 mutex_lock(&dev->struct_mutex);
2350                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2351                 mutex_unlock(&dev->struct_mutex);
2352         }
2353
2354         /* Let userspace switch the overlay on again. In most cases userspace
2355          * has to recompute where to put it anyway.
2356          */
2357 }
2358
2359 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2360 {
2361         struct drm_device *dev = crtc->dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364         int pipe = intel_crtc->pipe;
2365         int plane = intel_crtc->plane;
2366         u32 reg, temp;
2367
2368         if (intel_crtc->active)
2369                 return;
2370
2371         intel_crtc->active = true;
2372         intel_update_watermarks(dev);
2373
2374         /* Enable the DPLL */
2375         reg = DPLL(pipe);
2376         temp = I915_READ(reg);
2377         if ((temp & DPLL_VCO_ENABLE) == 0) {
2378                 I915_WRITE(reg, temp);
2379
2380                 /* Wait for the clocks to stabilize. */
2381                 POSTING_READ(reg);
2382                 udelay(150);
2383
2384                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2385
2386                 /* Wait for the clocks to stabilize. */
2387                 POSTING_READ(reg);
2388                 udelay(150);
2389
2390                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2391
2392                 /* Wait for the clocks to stabilize. */
2393                 POSTING_READ(reg);
2394                 udelay(150);
2395         }
2396
2397         /* Enable the pipe */
2398         reg = PIPECONF(pipe);
2399         temp = I915_READ(reg);
2400         if ((temp & PIPECONF_ENABLE) == 0)
2401                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2402
2403         /* Enable the plane */
2404         reg = DSPCNTR(plane);
2405         temp = I915_READ(reg);
2406         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2407                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2408                 intel_flush_display_plane(dev, plane);
2409         }
2410
2411         intel_crtc_load_lut(crtc);
2412         intel_update_fbc(dev);
2413
2414         /* Give the overlay scaler a chance to enable if it's on this pipe */
2415         intel_crtc_dpms_overlay(intel_crtc, true);
2416         intel_crtc_update_cursor(crtc, true);
2417 }
2418
2419 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2420 {
2421         struct drm_device *dev = crtc->dev;
2422         struct drm_i915_private *dev_priv = dev->dev_private;
2423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2424         int pipe = intel_crtc->pipe;
2425         int plane = intel_crtc->plane;
2426         u32 reg, temp;
2427
2428         if (!intel_crtc->active)
2429                 return;
2430
2431         /* Give the overlay scaler a chance to disable if it's on this pipe */
2432         intel_crtc_wait_for_pending_flips(crtc);
2433         drm_vblank_off(dev, pipe);
2434         intel_crtc_dpms_overlay(intel_crtc, false);
2435         intel_crtc_update_cursor(crtc, false);
2436
2437         if (dev_priv->cfb_plane == plane &&
2438             dev_priv->display.disable_fbc)
2439                 dev_priv->display.disable_fbc(dev);
2440
2441         /* Disable display plane */
2442         reg = DSPCNTR(plane);
2443         temp = I915_READ(reg);
2444         if (temp & DISPLAY_PLANE_ENABLE) {
2445                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2446                 /* Flush the plane changes */
2447                 intel_flush_display_plane(dev, plane);
2448
2449                 /* Wait for vblank for the disable to take effect */
2450                 if (IS_GEN2(dev))
2451                         intel_wait_for_vblank(dev, pipe);
2452         }
2453
2454         /* Don't disable pipe A or pipe A PLLs if needed */
2455         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2456                 goto done;
2457
2458         /* Next, disable display pipes */
2459         reg = PIPECONF(pipe);
2460         temp = I915_READ(reg);
2461         if (temp & PIPECONF_ENABLE) {
2462                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2463
2464                 /* Wait for the pipe to turn off */
2465                 POSTING_READ(reg);
2466                 intel_wait_for_pipe_off(dev, pipe);
2467         }
2468
2469         reg = DPLL(pipe);
2470         temp = I915_READ(reg);
2471         if (temp & DPLL_VCO_ENABLE) {
2472                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2473
2474                 /* Wait for the clocks to turn off. */
2475                 POSTING_READ(reg);
2476                 udelay(150);
2477         }
2478
2479 done:
2480         intel_crtc->active = false;
2481         intel_update_fbc(dev);
2482         intel_update_watermarks(dev);
2483         intel_clear_scanline_wait(dev);
2484 }
2485
2486 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2487 {
2488         /* XXX: When our outputs are all unaware of DPMS modes other than off
2489          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2490          */
2491         switch (mode) {
2492         case DRM_MODE_DPMS_ON:
2493         case DRM_MODE_DPMS_STANDBY:
2494         case DRM_MODE_DPMS_SUSPEND:
2495                 i9xx_crtc_enable(crtc);
2496                 break;
2497         case DRM_MODE_DPMS_OFF:
2498                 i9xx_crtc_disable(crtc);
2499                 break;
2500         }
2501 }
2502
2503 /**
2504  * Sets the power management mode of the pipe and plane.
2505  */
2506 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct drm_i915_master_private *master_priv;
2511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2512         int pipe = intel_crtc->pipe;
2513         bool enabled;
2514
2515         if (intel_crtc->dpms_mode == mode)
2516                 return;
2517
2518         intel_crtc->dpms_mode = mode;
2519
2520         dev_priv->display.dpms(crtc, mode);
2521
2522         if (!dev->primary->master)
2523                 return;
2524
2525         master_priv = dev->primary->master->driver_priv;
2526         if (!master_priv->sarea_priv)
2527                 return;
2528
2529         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2530
2531         switch (pipe) {
2532         case 0:
2533                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2534                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2535                 break;
2536         case 1:
2537                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2538                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2539                 break;
2540         default:
2541                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2542                 break;
2543         }
2544 }
2545
2546 static void intel_crtc_disable(struct drm_crtc *crtc)
2547 {
2548         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2549         struct drm_device *dev = crtc->dev;
2550
2551         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2552
2553         if (crtc->fb) {
2554                 mutex_lock(&dev->struct_mutex);
2555                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2556                 mutex_unlock(&dev->struct_mutex);
2557         }
2558 }
2559
2560 /* Prepare for a mode set.
2561  *
2562  * Note we could be a lot smarter here.  We need to figure out which outputs
2563  * will be enabled, which disabled (in short, how the config will changes)
2564  * and perform the minimum necessary steps to accomplish that, e.g. updating
2565  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2566  * panel fitting is in the proper state, etc.
2567  */
2568 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2569 {
2570         i9xx_crtc_disable(crtc);
2571 }
2572
2573 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2574 {
2575         i9xx_crtc_enable(crtc);
2576 }
2577
2578 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2579 {
2580         ironlake_crtc_disable(crtc);
2581 }
2582
2583 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2584 {
2585         ironlake_crtc_enable(crtc);
2586 }
2587
2588 void intel_encoder_prepare (struct drm_encoder *encoder)
2589 {
2590         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2591         /* lvds has its own version of prepare see intel_lvds_prepare */
2592         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2593 }
2594
2595 void intel_encoder_commit (struct drm_encoder *encoder)
2596 {
2597         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2598         /* lvds has its own version of commit see intel_lvds_commit */
2599         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2600 }
2601
2602 void intel_encoder_destroy(struct drm_encoder *encoder)
2603 {
2604         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2605
2606         drm_encoder_cleanup(encoder);
2607         kfree(intel_encoder);
2608 }
2609
2610 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2611                                   struct drm_display_mode *mode,
2612                                   struct drm_display_mode *adjusted_mode)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615
2616         if (HAS_PCH_SPLIT(dev)) {
2617                 /* FDI link clock is fixed at 2.7G */
2618                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2619                         return false;
2620         }
2621
2622         /* XXX some encoders set the crtcinfo, others don't.
2623          * Obviously we need some form of conflict resolution here...
2624          */
2625         if (adjusted_mode->crtc_htotal == 0)
2626                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2627
2628         return true;
2629 }
2630
2631 static int i945_get_display_clock_speed(struct drm_device *dev)
2632 {
2633         return 400000;
2634 }
2635
2636 static int i915_get_display_clock_speed(struct drm_device *dev)
2637 {
2638         return 333000;
2639 }
2640
2641 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2642 {
2643         return 200000;
2644 }
2645
2646 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2647 {
2648         u16 gcfgc = 0;
2649
2650         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2651
2652         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2653                 return 133000;
2654         else {
2655                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2656                 case GC_DISPLAY_CLOCK_333_MHZ:
2657                         return 333000;
2658                 default:
2659                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2660                         return 190000;
2661                 }
2662         }
2663 }
2664
2665 static int i865_get_display_clock_speed(struct drm_device *dev)
2666 {
2667         return 266000;
2668 }
2669
2670 static int i855_get_display_clock_speed(struct drm_device *dev)
2671 {
2672         u16 hpllcc = 0;
2673         /* Assume that the hardware is in the high speed state.  This
2674          * should be the default.
2675          */
2676         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2677         case GC_CLOCK_133_200:
2678         case GC_CLOCK_100_200:
2679                 return 200000;
2680         case GC_CLOCK_166_250:
2681                 return 250000;
2682         case GC_CLOCK_100_133:
2683                 return 133000;
2684         }
2685
2686         /* Shouldn't happen */
2687         return 0;
2688 }
2689
2690 static int i830_get_display_clock_speed(struct drm_device *dev)
2691 {
2692         return 133000;
2693 }
2694
2695 struct fdi_m_n {
2696         u32        tu;
2697         u32        gmch_m;
2698         u32        gmch_n;
2699         u32        link_m;
2700         u32        link_n;
2701 };
2702
2703 static void
2704 fdi_reduce_ratio(u32 *num, u32 *den)
2705 {
2706         while (*num > 0xffffff || *den > 0xffffff) {
2707                 *num >>= 1;
2708                 *den >>= 1;
2709         }
2710 }
2711
2712 static void
2713 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2714                      int link_clock, struct fdi_m_n *m_n)
2715 {
2716         m_n->tu = 64; /* default size */
2717
2718         /* BUG_ON(pixel_clock > INT_MAX / 36); */
2719         m_n->gmch_m = bits_per_pixel * pixel_clock;
2720         m_n->gmch_n = link_clock * nlanes * 8;
2721         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2722
2723         m_n->link_m = pixel_clock;
2724         m_n->link_n = link_clock;
2725         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2726 }
2727
2728
2729 struct intel_watermark_params {
2730         unsigned long fifo_size;
2731         unsigned long max_wm;
2732         unsigned long default_wm;
2733         unsigned long guard_size;
2734         unsigned long cacheline_size;
2735 };
2736
2737 /* Pineview has different values for various configs */
2738 static struct intel_watermark_params pineview_display_wm = {
2739         PINEVIEW_DISPLAY_FIFO,
2740         PINEVIEW_MAX_WM,
2741         PINEVIEW_DFT_WM,
2742         PINEVIEW_GUARD_WM,
2743         PINEVIEW_FIFO_LINE_SIZE
2744 };
2745 static struct intel_watermark_params pineview_display_hplloff_wm = {
2746         PINEVIEW_DISPLAY_FIFO,
2747         PINEVIEW_MAX_WM,
2748         PINEVIEW_DFT_HPLLOFF_WM,
2749         PINEVIEW_GUARD_WM,
2750         PINEVIEW_FIFO_LINE_SIZE
2751 };
2752 static struct intel_watermark_params pineview_cursor_wm = {
2753         PINEVIEW_CURSOR_FIFO,
2754         PINEVIEW_CURSOR_MAX_WM,
2755         PINEVIEW_CURSOR_DFT_WM,
2756         PINEVIEW_CURSOR_GUARD_WM,
2757         PINEVIEW_FIFO_LINE_SIZE,
2758 };
2759 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2760         PINEVIEW_CURSOR_FIFO,
2761         PINEVIEW_CURSOR_MAX_WM,
2762         PINEVIEW_CURSOR_DFT_WM,
2763         PINEVIEW_CURSOR_GUARD_WM,
2764         PINEVIEW_FIFO_LINE_SIZE
2765 };
2766 static struct intel_watermark_params g4x_wm_info = {
2767         G4X_FIFO_SIZE,
2768         G4X_MAX_WM,
2769         G4X_MAX_WM,
2770         2,
2771         G4X_FIFO_LINE_SIZE,
2772 };
2773 static struct intel_watermark_params g4x_cursor_wm_info = {
2774         I965_CURSOR_FIFO,
2775         I965_CURSOR_MAX_WM,
2776         I965_CURSOR_DFT_WM,
2777         2,
2778         G4X_FIFO_LINE_SIZE,
2779 };
2780 static struct intel_watermark_params i965_cursor_wm_info = {
2781         I965_CURSOR_FIFO,
2782         I965_CURSOR_MAX_WM,
2783         I965_CURSOR_DFT_WM,
2784         2,
2785         I915_FIFO_LINE_SIZE,
2786 };
2787 static struct intel_watermark_params i945_wm_info = {
2788         I945_FIFO_SIZE,
2789         I915_MAX_WM,
2790         1,
2791         2,
2792         I915_FIFO_LINE_SIZE
2793 };
2794 static struct intel_watermark_params i915_wm_info = {
2795         I915_FIFO_SIZE,
2796         I915_MAX_WM,
2797         1,
2798         2,
2799         I915_FIFO_LINE_SIZE
2800 };
2801 static struct intel_watermark_params i855_wm_info = {
2802         I855GM_FIFO_SIZE,
2803         I915_MAX_WM,
2804         1,
2805         2,
2806         I830_FIFO_LINE_SIZE
2807 };
2808 static struct intel_watermark_params i830_wm_info = {
2809         I830_FIFO_SIZE,
2810         I915_MAX_WM,
2811         1,
2812         2,
2813         I830_FIFO_LINE_SIZE
2814 };
2815
2816 static struct intel_watermark_params ironlake_display_wm_info = {
2817         ILK_DISPLAY_FIFO,
2818         ILK_DISPLAY_MAXWM,
2819         ILK_DISPLAY_DFTWM,
2820         2,
2821         ILK_FIFO_LINE_SIZE
2822 };
2823
2824 static struct intel_watermark_params ironlake_cursor_wm_info = {
2825         ILK_CURSOR_FIFO,
2826         ILK_CURSOR_MAXWM,
2827         ILK_CURSOR_DFTWM,
2828         2,
2829         ILK_FIFO_LINE_SIZE
2830 };
2831
2832 static struct intel_watermark_params ironlake_display_srwm_info = {
2833         ILK_DISPLAY_SR_FIFO,
2834         ILK_DISPLAY_MAX_SRWM,
2835         ILK_DISPLAY_DFT_SRWM,
2836         2,
2837         ILK_FIFO_LINE_SIZE
2838 };
2839
2840 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2841         ILK_CURSOR_SR_FIFO,
2842         ILK_CURSOR_MAX_SRWM,
2843         ILK_CURSOR_DFT_SRWM,
2844         2,
2845         ILK_FIFO_LINE_SIZE
2846 };
2847
2848 static struct intel_watermark_params sandybridge_display_wm_info = {
2849         SNB_DISPLAY_FIFO,
2850         SNB_DISPLAY_MAXWM,
2851         SNB_DISPLAY_DFTWM,
2852         2,
2853         SNB_FIFO_LINE_SIZE
2854 };
2855
2856 static struct intel_watermark_params sandybridge_cursor_wm_info = {
2857         SNB_CURSOR_FIFO,
2858         SNB_CURSOR_MAXWM,
2859         SNB_CURSOR_DFTWM,
2860         2,
2861         SNB_FIFO_LINE_SIZE
2862 };
2863
2864 static struct intel_watermark_params sandybridge_display_srwm_info = {
2865         SNB_DISPLAY_SR_FIFO,
2866         SNB_DISPLAY_MAX_SRWM,
2867         SNB_DISPLAY_DFT_SRWM,
2868         2,
2869         SNB_FIFO_LINE_SIZE
2870 };
2871
2872 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2873         SNB_CURSOR_SR_FIFO,
2874         SNB_CURSOR_MAX_SRWM,
2875         SNB_CURSOR_DFT_SRWM,
2876         2,
2877         SNB_FIFO_LINE_SIZE
2878 };
2879
2880
2881 /**
2882  * intel_calculate_wm - calculate watermark level
2883  * @clock_in_khz: pixel clock
2884  * @wm: chip FIFO params
2885  * @pixel_size: display pixel size
2886  * @latency_ns: memory latency for the platform
2887  *
2888  * Calculate the watermark level (the level at which the display plane will
2889  * start fetching from memory again).  Each chip has a different display
2890  * FIFO size and allocation, so the caller needs to figure that out and pass
2891  * in the correct intel_watermark_params structure.
2892  *
2893  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2894  * on the pixel size.  When it reaches the watermark level, it'll start
2895  * fetching FIFO line sized based chunks from memory until the FIFO fills
2896  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2897  * will occur, and a display engine hang could result.
2898  */
2899 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2900                                         struct intel_watermark_params *wm,
2901                                         int pixel_size,
2902                                         unsigned long latency_ns)
2903 {
2904         long entries_required, wm_size;
2905
2906         /*
2907          * Note: we need to make sure we don't overflow for various clock &
2908          * latency values.
2909          * clocks go from a few thousand to several hundred thousand.
2910          * latency is usually a few thousand
2911          */
2912         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2913                 1000;
2914         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2915
2916         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2917
2918         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2919
2920         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2921
2922         /* Don't promote wm_size to unsigned... */
2923         if (wm_size > (long)wm->max_wm)
2924                 wm_size = wm->max_wm;
2925         if (wm_size <= 0)
2926                 wm_size = wm->default_wm;
2927         return wm_size;
2928 }
2929
2930 struct cxsr_latency {
2931         int is_desktop;
2932         int is_ddr3;
2933         unsigned long fsb_freq;
2934         unsigned long mem_freq;
2935         unsigned long display_sr;
2936         unsigned long display_hpll_disable;
2937         unsigned long cursor_sr;
2938         unsigned long cursor_hpll_disable;
2939 };
2940
2941 static const struct cxsr_latency cxsr_latency_table[] = {
2942         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2943         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2944         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2945         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2946         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2947
2948         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2949         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2950         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2951         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2952         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2953
2954         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2955         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2956         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2957         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2958         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2959
2960         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2961         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2962         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2963         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2964         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2965
2966         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2967         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2968         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2969         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2970         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2971
2972         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2973         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2974         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2975         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2976         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2977 };
2978
2979 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2980                                                          int is_ddr3,
2981                                                          int fsb,
2982                                                          int mem)
2983 {
2984         const struct cxsr_latency *latency;
2985         int i;
2986
2987         if (fsb == 0 || mem == 0)
2988                 return NULL;
2989
2990         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2991                 latency = &cxsr_latency_table[i];
2992                 if (is_desktop == latency->is_desktop &&
2993                     is_ddr3 == latency->is_ddr3 &&
2994                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2995                         return latency;
2996         }
2997
2998         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2999
3000         return NULL;
3001 }
3002
3003 static void pineview_disable_cxsr(struct drm_device *dev)
3004 {
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006
3007         /* deactivate cxsr */
3008         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3009 }
3010
3011 /*
3012  * Latency for FIFO fetches is dependent on several factors:
3013  *   - memory configuration (speed, channels)
3014  *   - chipset
3015  *   - current MCH state
3016  * It can be fairly high in some situations, so here we assume a fairly
3017  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3018  * set this value too high, the FIFO will fetch frequently to stay full)
3019  * and power consumption (set it too low to save power and we might see
3020  * FIFO underruns and display "flicker").
3021  *
3022  * A value of 5us seems to be a good balance; safe for very low end
3023  * platforms but not overly aggressive on lower latency configs.
3024  */
3025 static const int latency_ns = 5000;
3026
3027 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3028 {
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         uint32_t dsparb = I915_READ(DSPARB);
3031         int size;
3032
3033         size = dsparb & 0x7f;
3034         if (plane)
3035                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3036
3037         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3038                       plane ? "B" : "A", size);
3039
3040         return size;
3041 }
3042
3043 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3044 {
3045         struct drm_i915_private *dev_priv = dev->dev_private;
3046         uint32_t dsparb = I915_READ(DSPARB);
3047         int size;
3048
3049         size = dsparb & 0x1ff;
3050         if (plane)
3051                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3052         size >>= 1; /* Convert to cachelines */
3053
3054         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3055                       plane ? "B" : "A", size);
3056
3057         return size;
3058 }
3059
3060 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3061 {
3062         struct drm_i915_private *dev_priv = dev->dev_private;
3063         uint32_t dsparb = I915_READ(DSPARB);
3064         int size;
3065
3066         size = dsparb & 0x7f;
3067         size >>= 2; /* Convert to cachelines */
3068
3069         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3070                       plane ? "B" : "A",
3071                       size);
3072
3073         return size;
3074 }
3075
3076 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3077 {
3078         struct drm_i915_private *dev_priv = dev->dev_private;
3079         uint32_t dsparb = I915_READ(DSPARB);
3080         int size;
3081
3082         size = dsparb & 0x7f;
3083         size >>= 1; /* Convert to cachelines */
3084
3085         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3086                       plane ? "B" : "A", size);
3087
3088         return size;
3089 }
3090
3091 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3092                                int planeb_clock, int sr_hdisplay, int unused,
3093                                int pixel_size)
3094 {
3095         struct drm_i915_private *dev_priv = dev->dev_private;
3096         const struct cxsr_latency *latency;
3097         u32 reg;
3098         unsigned long wm;
3099         int sr_clock;
3100
3101         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3102                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3103         if (!latency) {
3104                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3105                 pineview_disable_cxsr(dev);
3106                 return;
3107         }
3108
3109         if (!planea_clock || !planeb_clock) {
3110                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3111
3112                 /* Display SR */
3113                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3114                                         pixel_size, latency->display_sr);
3115                 reg = I915_READ(DSPFW1);
3116                 reg &= ~DSPFW_SR_MASK;
3117                 reg |= wm << DSPFW_SR_SHIFT;
3118                 I915_WRITE(DSPFW1, reg);
3119                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3120
3121                 /* cursor SR */
3122                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3123                                         pixel_size, latency->cursor_sr);
3124                 reg = I915_READ(DSPFW3);
3125                 reg &= ~DSPFW_CURSOR_SR_MASK;
3126                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3127                 I915_WRITE(DSPFW3, reg);
3128
3129                 /* Display HPLL off SR */
3130                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3131                                         pixel_size, latency->display_hpll_disable);
3132                 reg = I915_READ(DSPFW3);
3133                 reg &= ~DSPFW_HPLL_SR_MASK;
3134                 reg |= wm & DSPFW_HPLL_SR_MASK;
3135                 I915_WRITE(DSPFW3, reg);
3136
3137                 /* cursor HPLL off SR */
3138                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3139                                         pixel_size, latency->cursor_hpll_disable);
3140                 reg = I915_READ(DSPFW3);
3141                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3142                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3143                 I915_WRITE(DSPFW3, reg);
3144                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3145
3146                 /* activate cxsr */
3147                 I915_WRITE(DSPFW3,
3148                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3149                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3150         } else {
3151                 pineview_disable_cxsr(dev);
3152                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3153         }
3154 }
3155
3156 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3157                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3158                           int pixel_size)
3159 {
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161         int total_size, cacheline_size;
3162         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3163         struct intel_watermark_params planea_params, planeb_params;
3164         unsigned long line_time_us;
3165         int sr_clock, sr_entries = 0, entries_required;
3166
3167         /* Create copies of the base settings for each pipe */
3168         planea_params = planeb_params = g4x_wm_info;
3169
3170         /* Grab a couple of global values before we overwrite them */
3171         total_size = planea_params.fifo_size;
3172         cacheline_size = planea_params.cacheline_size;
3173
3174         /*
3175          * Note: we need to make sure we don't overflow for various clock &
3176          * latency values.
3177          * clocks go from a few thousand to several hundred thousand.
3178          * latency is usually a few thousand
3179          */
3180         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3181                 1000;
3182         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3183         planea_wm = entries_required + planea_params.guard_size;
3184
3185         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3186                 1000;
3187         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3188         planeb_wm = entries_required + planeb_params.guard_size;
3189
3190         cursora_wm = cursorb_wm = 16;
3191         cursor_sr = 32;
3192
3193         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3194
3195         /* Calc sr entries for one plane configs */
3196         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3197                 /* self-refresh has much higher latency */
3198                 static const int sr_latency_ns = 12000;
3199
3200                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3201                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3202
3203                 /* Use ns/us then divide to preserve precision */
3204                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3205                         pixel_size * sr_hdisplay;
3206                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3207
3208                 entries_required = (((sr_latency_ns / line_time_us) +
3209                                      1000) / 1000) * pixel_size * 64;
3210                 entries_required = DIV_ROUND_UP(entries_required,
3211                                                 g4x_cursor_wm_info.cacheline_size);
3212                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3213
3214                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3215                         cursor_sr = g4x_cursor_wm_info.max_wm;
3216                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3217                               "cursor %d\n", sr_entries, cursor_sr);
3218
3219                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3220         } else {
3221                 /* Turn off self refresh if both pipes are enabled */
3222                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3223                            & ~FW_BLC_SELF_EN);
3224         }
3225
3226         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3227                   planea_wm, planeb_wm, sr_entries);
3228
3229         planea_wm &= 0x3f;
3230         planeb_wm &= 0x3f;
3231
3232         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3233                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3234                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3235         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3236                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3237         /* HPLL off in SR has some issues on G4x... disable it */
3238         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3239                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3240 }
3241
3242 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3243                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3244                            int pixel_size)
3245 {
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         unsigned long line_time_us;
3248         int sr_clock, sr_entries, srwm = 1;
3249         int cursor_sr = 16;
3250
3251         /* Calc sr entries for one plane configs */
3252         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3253                 /* self-refresh has much higher latency */
3254                 static const int sr_latency_ns = 12000;
3255
3256                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3257                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3258
3259                 /* Use ns/us then divide to preserve precision */
3260                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3261                         pixel_size * sr_hdisplay;
3262                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3263                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3264                 srwm = I965_FIFO_SIZE - sr_entries;
3265                 if (srwm < 0)
3266                         srwm = 1;
3267                 srwm &= 0x1ff;
3268
3269                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3270                         pixel_size * 64;
3271                 sr_entries = DIV_ROUND_UP(sr_entries,
3272                                           i965_cursor_wm_info.cacheline_size);
3273                 cursor_sr = i965_cursor_wm_info.fifo_size -
3274                         (sr_entries + i965_cursor_wm_info.guard_size);
3275
3276                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3277                         cursor_sr = i965_cursor_wm_info.max_wm;
3278
3279                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3280                               "cursor %d\n", srwm, cursor_sr);
3281
3282                 if (IS_CRESTLINE(dev))
3283                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3284         } else {
3285                 /* Turn off self refresh if both pipes are enabled */
3286                 if (IS_CRESTLINE(dev))
3287                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3288                                    & ~FW_BLC_SELF_EN);
3289         }
3290
3291         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3292                       srwm);
3293
3294         /* 965 has limitations... */
3295         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3296                    (8 << 0));
3297         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3298         /* update cursor SR watermark */
3299         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3300 }
3301
3302 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3303                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3304                            int pixel_size)
3305 {
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         uint32_t fwater_lo;
3308         uint32_t fwater_hi;
3309         int total_size, cacheline_size, cwm, srwm = 1;
3310         int planea_wm, planeb_wm;
3311         struct intel_watermark_params planea_params, planeb_params;
3312         unsigned long line_time_us;
3313         int sr_clock, sr_entries = 0;
3314
3315         /* Create copies of the base settings for each pipe */
3316         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3317                 planea_params = planeb_params = i945_wm_info;
3318         else if (!IS_GEN2(dev))
3319                 planea_params = planeb_params = i915_wm_info;
3320         else
3321                 planea_params = planeb_params = i855_wm_info;
3322
3323         /* Grab a couple of global values before we overwrite them */
3324         total_size = planea_params.fifo_size;
3325         cacheline_size = planea_params.cacheline_size;
3326
3327         /* Update per-plane FIFO sizes */
3328         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3329         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3330
3331         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3332                                        pixel_size, latency_ns);
3333         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3334                                        pixel_size, latency_ns);
3335         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3336
3337         /*
3338          * Overlay gets an aggressive default since video jitter is bad.
3339          */
3340         cwm = 2;
3341
3342         /* Calc sr entries for one plane configs */
3343         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3344             (!planea_clock || !planeb_clock)) {
3345                 /* self-refresh has much higher latency */
3346                 static const int sr_latency_ns = 6000;
3347
3348                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3349                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3350
3351                 /* Use ns/us then divide to preserve precision */
3352                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3353                         pixel_size * sr_hdisplay;
3354                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3355                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3356                 srwm = total_size - sr_entries;
3357                 if (srwm < 0)
3358                         srwm = 1;
3359
3360                 if (IS_I945G(dev) || IS_I945GM(dev))
3361                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3362                 else if (IS_I915GM(dev)) {
3363                         /* 915M has a smaller SRWM field */
3364                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3365                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3366                 }
3367         } else {
3368                 /* Turn off self refresh if both pipes are enabled */
3369                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3370                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3371                                    & ~FW_BLC_SELF_EN);
3372                 } else if (IS_I915GM(dev)) {
3373                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3374                 }
3375         }
3376
3377         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3378                       planea_wm, planeb_wm, cwm, srwm);
3379
3380         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3381         fwater_hi = (cwm & 0x1f);
3382
3383         /* Set request length to 8 cachelines per fetch */
3384         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3385         fwater_hi = fwater_hi | (1 << 8);
3386
3387         I915_WRITE(FW_BLC, fwater_lo);
3388         I915_WRITE(FW_BLC2, fwater_hi);
3389 }
3390
3391 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3392                            int unused2, int unused3, int pixel_size)
3393 {
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3396         int planea_wm;
3397
3398         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3399
3400         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3401                                        pixel_size, latency_ns);
3402         fwater_lo |= (3<<8) | planea_wm;
3403
3404         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3405
3406         I915_WRITE(FW_BLC, fwater_lo);
3407 }
3408
3409 #define ILK_LP0_PLANE_LATENCY           700
3410 #define ILK_LP0_CURSOR_LATENCY          1300
3411
3412 static bool ironlake_compute_wm0(struct drm_device *dev,
3413                                  int pipe,
3414                                  const struct intel_watermark_params *display,
3415                                  int display_latency,
3416                                  const struct intel_watermark_params *cursor,
3417                                  int cursor_latency,
3418                                  int *plane_wm,
3419                                  int *cursor_wm)
3420 {
3421         struct drm_crtc *crtc;
3422         int htotal, hdisplay, clock, pixel_size = 0;
3423         int line_time_us, line_count, entries;
3424
3425         crtc = intel_get_crtc_for_pipe(dev, pipe);
3426         if (crtc->fb == NULL || !crtc->enabled)
3427                 return false;
3428
3429         htotal = crtc->mode.htotal;
3430         hdisplay = crtc->mode.hdisplay;
3431         clock = crtc->mode.clock;
3432         pixel_size = crtc->fb->bits_per_pixel / 8;
3433
3434         /* Use the small buffer method to calculate plane watermark */
3435         entries = ((clock * pixel_size / 1000) * display_latency * 100) / 1000;
3436         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3437         *plane_wm = entries + display->guard_size;
3438         if (*plane_wm > (int)display->max_wm)
3439                 *plane_wm = display->max_wm;
3440
3441         /* Use the large buffer method to calculate cursor watermark */
3442         line_time_us = ((htotal * 1000) / clock);
3443         line_count = (cursor_latency * 100 / line_time_us + 1000) / 1000;
3444         entries = line_count * 64 * pixel_size;
3445         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3446         *cursor_wm = entries + cursor->guard_size;
3447         if (*cursor_wm > (int)cursor->max_wm)
3448                 *cursor_wm = (int)cursor->max_wm;
3449
3450         return true;
3451 }
3452
3453 static void ironlake_update_wm(struct drm_device *dev,
3454                                int planea_clock, int planeb_clock,
3455                                int sr_hdisplay, int sr_htotal,
3456                                int pixel_size)
3457 {
3458         struct drm_i915_private *dev_priv = dev->dev_private;
3459         int plane_wm, cursor_wm, enabled;
3460         int tmp;
3461
3462         enabled = 0;
3463         if (ironlake_compute_wm0(dev, 0,
3464                                  &ironlake_display_wm_info,
3465                                  ILK_LP0_PLANE_LATENCY,
3466                                  &ironlake_cursor_wm_info,
3467                                  ILK_LP0_CURSOR_LATENCY,
3468                                  &plane_wm, &cursor_wm)) {
3469                 I915_WRITE(WM0_PIPEA_ILK,
3470                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3471                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3472                               " plane %d, " "cursor: %d\n",
3473                               plane_wm, cursor_wm);
3474                 enabled++;
3475         }
3476
3477         if (ironlake_compute_wm0(dev, 1,
3478                                  &ironlake_display_wm_info,
3479                                  ILK_LP0_PLANE_LATENCY,
3480                                  &ironlake_cursor_wm_info,
3481                                  ILK_LP0_CURSOR_LATENCY,
3482                                  &plane_wm, &cursor_wm)) {
3483                 I915_WRITE(WM0_PIPEB_ILK,
3484                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3485                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3486                               " plane %d, cursor: %d\n",
3487                               plane_wm, cursor_wm);
3488                 enabled++;
3489         }
3490
3491         /*
3492          * Calculate and update the self-refresh watermark only when one
3493          * display plane is used.
3494          */
3495         tmp = 0;
3496         if (enabled == 1) {
3497                 unsigned long line_time_us;
3498                 int small, large, plane_fbc;
3499                 int sr_clock, entries;
3500                 int line_count, line_size;
3501                 /* Read the self-refresh latency. The unit is 0.5us */
3502                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3503
3504                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3505                 line_time_us = (sr_htotal * 1000) / sr_clock;
3506
3507                 /* Use ns/us then divide to preserve precision */
3508                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3509                         / 1000;
3510                 line_size = sr_hdisplay * pixel_size;
3511
3512                 /* Use the minimum of the small and large buffer method for primary */
3513                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3514                 large = line_count * line_size;
3515
3516                 entries = DIV_ROUND_UP(min(small, large),
3517                                        ironlake_display_srwm_info.cacheline_size);
3518
3519                 plane_fbc = entries * 64;
3520                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3521
3522                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3523                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3524                         plane_wm = ironlake_display_srwm_info.max_wm;
3525
3526                 /* calculate the self-refresh watermark for display cursor */
3527                 entries = line_count * pixel_size * 64;
3528                 entries = DIV_ROUND_UP(entries,
3529                                        ironlake_cursor_srwm_info.cacheline_size);
3530
3531                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3532                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3533                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3534
3535                 /* configure watermark and enable self-refresh */
3536                 tmp = (WM1_LP_SR_EN |
3537                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3538                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3539                        (plane_wm << WM1_LP_SR_SHIFT) |
3540                        cursor_wm);
3541                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3542                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3543         }
3544         I915_WRITE(WM1_LP_ILK, tmp);
3545         /* XXX setup WM2 and WM3 */
3546 }
3547
3548 /*
3549  * Check the wm result.
3550  *
3551  * If any calculated watermark values is larger than the maximum value that
3552  * can be programmed into the associated watermark register, that watermark
3553  * must be disabled.
3554  *
3555  * Also return true if all of those watermark values is 0, which is set by
3556  * sandybridge_compute_srwm, to indicate the latency is ZERO.
3557  */
3558 static bool sandybridge_check_srwm(struct drm_device *dev, int level,
3559                                    int fbc_wm, int display_wm, int cursor_wm)
3560 {
3561         struct drm_i915_private *dev_priv = dev->dev_private;
3562
3563         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3564                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3565
3566         if (fbc_wm > SNB_FBC_MAX_SRWM) {
3567                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3568                                 fbc_wm, SNB_FBC_MAX_SRWM, level);
3569
3570                 /* fbc has it's own way to disable FBC WM */
3571                 I915_WRITE(DISP_ARB_CTL,
3572                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3573                 return false;
3574         }
3575
3576         if (display_wm > SNB_DISPLAY_MAX_SRWM) {
3577                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3578                                 display_wm, SNB_DISPLAY_MAX_SRWM, level);
3579                 return false;
3580         }
3581
3582         if (cursor_wm > SNB_CURSOR_MAX_SRWM) {
3583                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3584                                 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3585                 return false;
3586         }
3587
3588         if (!(fbc_wm || display_wm || cursor_wm)) {
3589                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3590                 return false;
3591         }
3592
3593         return true;
3594 }
3595
3596 /*
3597  * Compute watermark values of WM[1-3],
3598  */
3599 static bool sandybridge_compute_srwm(struct drm_device *dev, int level,
3600                                      int hdisplay, int htotal, int pixel_size,
3601                                      int clock, int latency_ns, int *fbc_wm,
3602                                      int *display_wm, int *cursor_wm)
3603 {
3604
3605         unsigned long line_time_us;
3606         int small, large;
3607         int entries;
3608         int line_count, line_size;
3609
3610         if (!latency_ns) {
3611                 *fbc_wm = *display_wm = *cursor_wm = 0;
3612                 return false;
3613         }
3614
3615         line_time_us = (htotal * 1000) / clock;
3616         line_count = (latency_ns / line_time_us + 1000) / 1000;
3617         line_size = hdisplay * pixel_size;
3618
3619         /* Use the minimum of the small and large buffer method for primary */
3620         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3621         large = line_count * line_size;
3622
3623         entries = DIV_ROUND_UP(min(small, large),
3624                                 sandybridge_display_srwm_info.cacheline_size);
3625         *display_wm = entries + sandybridge_display_srwm_info.guard_size;
3626
3627         /*
3628          * Spec said:
3629          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3630          */
3631         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3632
3633         /* calculate the self-refresh watermark for display cursor */
3634         entries = line_count * pixel_size * 64;
3635         entries = DIV_ROUND_UP(entries,
3636                                sandybridge_cursor_srwm_info.cacheline_size);
3637         *cursor_wm = entries + sandybridge_cursor_srwm_info.guard_size;
3638
3639         return sandybridge_check_srwm(dev, level,
3640                                       *fbc_wm, *display_wm, *cursor_wm);
3641 }
3642
3643 static void sandybridge_update_wm(struct drm_device *dev,
3644                                int planea_clock, int planeb_clock,
3645                                int hdisplay, int htotal,
3646                                int pixel_size)
3647 {
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         int latency = SNB_READ_WM0_LATENCY();
3650         int fbc_wm, plane_wm, cursor_wm, enabled;
3651         int clock;
3652
3653         enabled = 0;
3654         if (ironlake_compute_wm0(dev, 0,
3655                                  &sandybridge_display_wm_info, latency,
3656                                  &sandybridge_cursor_wm_info, latency,
3657                                  &plane_wm, &cursor_wm)) {
3658                 I915_WRITE(WM0_PIPEA_ILK,
3659                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3660                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3661                               " plane %d, " "cursor: %d\n",
3662                               plane_wm, cursor_wm);
3663                 enabled++;
3664         }
3665
3666         if (ironlake_compute_wm0(dev, 1,
3667                                  &sandybridge_display_wm_info, latency,
3668                                  &sandybridge_cursor_wm_info, latency,
3669                                  &plane_wm, &cursor_wm)) {
3670                 I915_WRITE(WM0_PIPEB_ILK,
3671                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3672                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3673                               " plane %d, cursor: %d\n",
3674                               plane_wm, cursor_wm);
3675                 enabled++;
3676         }
3677
3678         /*
3679          * Calculate and update the self-refresh watermark only when one
3680          * display plane is used.
3681          *
3682          * SNB support 3 levels of watermark.
3683          *
3684          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3685          * and disabled in the descending order
3686          *
3687          */
3688         I915_WRITE(WM3_LP_ILK, 0);
3689         I915_WRITE(WM2_LP_ILK, 0);
3690         I915_WRITE(WM1_LP_ILK, 0);
3691
3692         if (enabled != 1)
3693                 return;
3694
3695         clock = planea_clock ? planea_clock : planeb_clock;
3696
3697         /* WM1 */
3698         if (!sandybridge_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3699                                       clock, SNB_READ_WM1_LATENCY() * 500,
3700                                       &fbc_wm, &plane_wm, &cursor_wm))
3701                 return;
3702
3703         I915_WRITE(WM1_LP_ILK,
3704                    WM1_LP_SR_EN |
3705                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3706                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3707                    (plane_wm << WM1_LP_SR_SHIFT) |
3708                    cursor_wm);
3709
3710         /* WM2 */
3711         if (!sandybridge_compute_srwm(dev, 2,
3712                                       hdisplay, htotal, pixel_size,
3713                                       clock, SNB_READ_WM2_LATENCY() * 500,
3714                                       &fbc_wm, &plane_wm, &cursor_wm))
3715                 return;
3716
3717         I915_WRITE(WM2_LP_ILK,
3718                    WM2_LP_EN |
3719                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3720                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3721                    (plane_wm << WM1_LP_SR_SHIFT) |
3722                    cursor_wm);
3723
3724         /* WM3 */
3725         if (!sandybridge_compute_srwm(dev, 3,
3726                                       hdisplay, htotal, pixel_size,
3727                                       clock, SNB_READ_WM3_LATENCY() * 500,
3728                                       &fbc_wm, &plane_wm, &cursor_wm))
3729                 return;
3730
3731         I915_WRITE(WM3_LP_ILK,
3732                    WM3_LP_EN |
3733                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3734                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3735                    (plane_wm << WM1_LP_SR_SHIFT) |
3736                    cursor_wm);
3737 }
3738
3739 /**
3740  * intel_update_watermarks - update FIFO watermark values based on current modes
3741  *
3742  * Calculate watermark values for the various WM regs based on current mode
3743  * and plane configuration.
3744  *
3745  * There are several cases to deal with here:
3746  *   - normal (i.e. non-self-refresh)
3747  *   - self-refresh (SR) mode
3748  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3749  *   - lines are small relative to FIFO size (buffer can hold more than 2
3750  *     lines), so need to account for TLB latency
3751  *
3752  *   The normal calculation is:
3753  *     watermark = dotclock * bytes per pixel * latency
3754  *   where latency is platform & configuration dependent (we assume pessimal
3755  *   values here).
3756  *
3757  *   The SR calculation is:
3758  *     watermark = (trunc(latency/line time)+1) * surface width *
3759  *       bytes per pixel
3760  *   where
3761  *     line time = htotal / dotclock
3762  *     surface width = hdisplay for normal plane and 64 for cursor
3763  *   and latency is assumed to be high, as above.
3764  *
3765  * The final value programmed to the register should always be rounded up,
3766  * and include an extra 2 entries to account for clock crossings.
3767  *
3768  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3769  * to set the non-SR watermarks to 8.
3770  */
3771 static void intel_update_watermarks(struct drm_device *dev)
3772 {
3773         struct drm_i915_private *dev_priv = dev->dev_private;
3774         struct drm_crtc *crtc;
3775         int sr_hdisplay = 0;
3776         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3777         int enabled = 0, pixel_size = 0;
3778         int sr_htotal = 0;
3779
3780         if (!dev_priv->display.update_wm)
3781                 return;
3782
3783         /* Get the clock config from both planes */
3784         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3785                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3786                 if (intel_crtc->active) {
3787                         enabled++;
3788                         if (intel_crtc->plane == 0) {
3789                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3790                                               intel_crtc->pipe, crtc->mode.clock);
3791                                 planea_clock = crtc->mode.clock;
3792                         } else {
3793                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3794                                               intel_crtc->pipe, crtc->mode.clock);
3795                                 planeb_clock = crtc->mode.clock;
3796                         }
3797                         sr_hdisplay = crtc->mode.hdisplay;
3798                         sr_clock = crtc->mode.clock;
3799                         sr_htotal = crtc->mode.htotal;
3800                         if (crtc->fb)
3801                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3802                         else
3803                                 pixel_size = 4; /* by default */
3804                 }
3805         }
3806
3807         if (enabled <= 0)
3808                 return;
3809
3810         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3811                                     sr_hdisplay, sr_htotal, pixel_size);
3812 }
3813
3814 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3815                                struct drm_display_mode *mode,
3816                                struct drm_display_mode *adjusted_mode,
3817                                int x, int y,
3818                                struct drm_framebuffer *old_fb)
3819 {
3820         struct drm_device *dev = crtc->dev;
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3823         int pipe = intel_crtc->pipe;
3824         int plane = intel_crtc->plane;
3825         u32 fp_reg, dpll_reg;
3826         int refclk, num_connectors = 0;
3827         intel_clock_t clock, reduced_clock;
3828         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3829         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3830         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3831         struct intel_encoder *has_edp_encoder = NULL;
3832         struct drm_mode_config *mode_config = &dev->mode_config;
3833         struct intel_encoder *encoder;
3834         const intel_limit_t *limit;
3835         int ret;
3836         struct fdi_m_n m_n = {0};
3837         u32 reg, temp;
3838         int target_clock;
3839
3840         drm_vblank_pre_modeset(dev, pipe);
3841
3842         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3843                 if (encoder->base.crtc != crtc)
3844                         continue;
3845
3846                 switch (encoder->type) {
3847                 case INTEL_OUTPUT_LVDS:
3848                         is_lvds = true;
3849                         break;
3850                 case INTEL_OUTPUT_SDVO:
3851                 case INTEL_OUTPUT_HDMI:
3852                         is_sdvo = true;
3853                         if (encoder->needs_tv_clock)
3854                                 is_tv = true;
3855                         break;
3856                 case INTEL_OUTPUT_DVO:
3857                         is_dvo = true;
3858                         break;
3859                 case INTEL_OUTPUT_TVOUT:
3860                         is_tv = true;
3861                         break;
3862                 case INTEL_OUTPUT_ANALOG:
3863                         is_crt = true;
3864                         break;
3865                 case INTEL_OUTPUT_DISPLAYPORT:
3866                         is_dp = true;
3867                         break;
3868                 case INTEL_OUTPUT_EDP:
3869                         has_edp_encoder = encoder;
3870                         break;
3871                 }
3872
3873                 num_connectors++;
3874         }
3875
3876         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3877                 refclk = dev_priv->lvds_ssc_freq * 1000;
3878                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3879                               refclk / 1000);
3880         } else if (!IS_GEN2(dev)) {
3881                 refclk = 96000;
3882                 if (HAS_PCH_SPLIT(dev) &&
3883                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3884                         refclk = 120000; /* 120Mhz refclk */
3885         } else {
3886                 refclk = 48000;
3887         }
3888
3889         /*
3890          * Returns a set of divisors for the desired target clock with the given
3891          * refclk, or FALSE.  The returned values represent the clock equation:
3892          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3893          */
3894         limit = intel_limit(crtc, refclk);
3895         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3896         if (!ok) {
3897                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3898                 drm_vblank_post_modeset(dev, pipe);
3899                 return -EINVAL;
3900         }
3901
3902         /* Ensure that the cursor is valid for the new mode before changing... */
3903         intel_crtc_update_cursor(crtc, true);
3904
3905         if (is_lvds && dev_priv->lvds_downclock_avail) {
3906                 has_reduced_clock = limit->find_pll(limit, crtc,
3907                                                     dev_priv->lvds_downclock,
3908                                                     refclk,
3909                                                     &reduced_clock);
3910                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3911                         /*
3912                          * If the different P is found, it means that we can't
3913                          * switch the display clock by using the FP0/FP1.
3914                          * In such case we will disable the LVDS downclock
3915                          * feature.
3916                          */
3917                         DRM_DEBUG_KMS("Different P is found for "
3918                                       "LVDS clock/downclock\n");
3919                         has_reduced_clock = 0;
3920                 }
3921         }
3922         /* SDVO TV has fixed PLL values depend on its clock range,
3923            this mirrors vbios setting. */
3924         if (is_sdvo && is_tv) {
3925                 if (adjusted_mode->clock >= 100000
3926                     && adjusted_mode->clock < 140500) {
3927                         clock.p1 = 2;
3928                         clock.p2 = 10;
3929                         clock.n = 3;
3930                         clock.m1 = 16;
3931                         clock.m2 = 8;
3932                 } else if (adjusted_mode->clock >= 140500
3933                            && adjusted_mode->clock <= 200000) {
3934                         clock.p1 = 1;
3935                         clock.p2 = 10;
3936                         clock.n = 6;
3937                         clock.m1 = 12;
3938                         clock.m2 = 8;
3939                 }
3940         }
3941
3942         /* FDI link */
3943         if (HAS_PCH_SPLIT(dev)) {
3944                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3945                 int lane = 0, link_bw, bpp;
3946                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3947                    according to current link config */
3948                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3949                         target_clock = mode->clock;
3950                         intel_edp_link_config(has_edp_encoder,
3951                                               &lane, &link_bw);
3952                 } else {
3953                         /* [e]DP over FDI requires target mode clock
3954                            instead of link clock */
3955                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3956                                 target_clock = mode->clock;
3957                         else
3958                                 target_clock = adjusted_mode->clock;
3959
3960                         /* FDI is a binary signal running at ~2.7GHz, encoding
3961                          * each output octet as 10 bits. The actual frequency
3962                          * is stored as a divider into a 100MHz clock, and the
3963                          * mode pixel clock is stored in units of 1KHz.
3964                          * Hence the bw of each lane in terms of the mode signal
3965                          * is:
3966                          */
3967                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3968                 }
3969
3970                 /* determine panel color depth */
3971                 temp = I915_READ(PIPECONF(pipe));
3972                 temp &= ~PIPE_BPC_MASK;
3973                 if (is_lvds) {
3974                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3975                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3976                                 temp |= PIPE_8BPC;
3977                         else
3978                                 temp |= PIPE_6BPC;
3979                 } else if (has_edp_encoder) {
3980                         switch (dev_priv->edp.bpp/3) {
3981                         case 8:
3982                                 temp |= PIPE_8BPC;
3983                                 break;
3984                         case 10:
3985                                 temp |= PIPE_10BPC;
3986                                 break;
3987                         case 6:
3988                                 temp |= PIPE_6BPC;
3989                                 break;
3990                         case 12:
3991                                 temp |= PIPE_12BPC;
3992                                 break;
3993                         }
3994                 } else
3995                         temp |= PIPE_8BPC;
3996                 I915_WRITE(PIPECONF(pipe), temp);
3997
3998                 switch (temp & PIPE_BPC_MASK) {
3999                 case PIPE_8BPC:
4000                         bpp = 24;
4001                         break;
4002                 case PIPE_10BPC:
4003                         bpp = 30;
4004                         break;
4005                 case PIPE_6BPC:
4006                         bpp = 18;
4007                         break;
4008                 case PIPE_12BPC:
4009                         bpp = 36;
4010                         break;
4011                 default:
4012                         DRM_ERROR("unknown pipe bpc value\n");
4013                         bpp = 24;
4014                 }
4015
4016                 if (!lane) {
4017                         /*
4018                          * Account for spread spectrum to avoid
4019                          * oversubscribing the link. Max center spread
4020                          * is 2.5%; use 5% for safety's sake.
4021                          */
4022                         u32 bps = target_clock * bpp * 21 / 20;
4023                         lane = bps / (link_bw * 8) + 1;
4024                 }
4025
4026                 intel_crtc->fdi_lanes = lane;
4027
4028                 if (pixel_multiplier > 1)
4029                         link_bw *= pixel_multiplier;
4030                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4031         }
4032
4033         /* Ironlake: try to setup display ref clock before DPLL
4034          * enabling. This is only under driver's control after
4035          * PCH B stepping, previous chipset stepping should be
4036          * ignoring this setting.
4037          */
4038         if (HAS_PCH_SPLIT(dev)) {
4039                 temp = I915_READ(PCH_DREF_CONTROL);
4040                 /* Always enable nonspread source */
4041                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4042                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4043                 temp &= ~DREF_SSC_SOURCE_MASK;
4044                 temp |= DREF_SSC_SOURCE_ENABLE;
4045                 I915_WRITE(PCH_DREF_CONTROL, temp);
4046
4047                 POSTING_READ(PCH_DREF_CONTROL);
4048                 udelay(200);
4049
4050                 if (has_edp_encoder) {
4051                         if (dev_priv->lvds_use_ssc) {
4052                                 temp |= DREF_SSC1_ENABLE;
4053                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4054
4055                                 POSTING_READ(PCH_DREF_CONTROL);
4056                                 udelay(200);
4057                         }
4058                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4059
4060                         /* Enable CPU source on CPU attached eDP */
4061                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4062                                 if (dev_priv->lvds_use_ssc)
4063                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4064                                 else
4065                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4066                         } else {
4067                                 /* Enable SSC on PCH eDP if needed */
4068                                 if (dev_priv->lvds_use_ssc) {
4069                                         DRM_ERROR("enabling SSC on PCH\n");
4070                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4071                                 }
4072                         }
4073                         I915_WRITE(PCH_DREF_CONTROL, temp);
4074                         POSTING_READ(PCH_DREF_CONTROL);
4075                         udelay(200);
4076                 }
4077         }
4078
4079         if (IS_PINEVIEW(dev)) {
4080                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4081                 if (has_reduced_clock)
4082                         fp2 = (1 << reduced_clock.n) << 16 |
4083                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4084         } else {
4085                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4086                 if (has_reduced_clock)
4087                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4088                                 reduced_clock.m2;
4089         }
4090
4091         /* Enable autotuning of the PLL clock (if permissible) */
4092         if (HAS_PCH_SPLIT(dev)) {
4093                 int factor = 21;
4094
4095                 if (is_lvds) {
4096                         if ((dev_priv->lvds_use_ssc &&
4097                              dev_priv->lvds_ssc_freq == 100) ||
4098                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4099                                 factor = 25;
4100                 } else if (is_sdvo && is_tv)
4101                         factor = 20;
4102
4103                 if (clock.m1 < factor * clock.n)
4104                         fp |= FP_CB_TUNE;
4105         }
4106
4107         dpll = 0;
4108         if (!HAS_PCH_SPLIT(dev))
4109                 dpll = DPLL_VGA_MODE_DIS;
4110
4111         if (!IS_GEN2(dev)) {
4112                 if (is_lvds)
4113                         dpll |= DPLLB_MODE_LVDS;
4114                 else
4115                         dpll |= DPLLB_MODE_DAC_SERIAL;
4116                 if (is_sdvo) {
4117                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4118                         if (pixel_multiplier > 1) {
4119                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4120                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4121                                 else if (HAS_PCH_SPLIT(dev))
4122                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4123                         }
4124                         dpll |= DPLL_DVO_HIGH_SPEED;
4125                 }
4126                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4127                         dpll |= DPLL_DVO_HIGH_SPEED;
4128
4129                 /* compute bitmask from p1 value */
4130                 if (IS_PINEVIEW(dev))
4131                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4132                 else {
4133                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4134                         /* also FPA1 */
4135                         if (HAS_PCH_SPLIT(dev))
4136                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4137                         if (IS_G4X(dev) && has_reduced_clock)
4138                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4139                 }
4140                 switch (clock.p2) {
4141                 case 5:
4142                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4143                         break;
4144                 case 7:
4145                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4146                         break;
4147                 case 10:
4148                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4149                         break;
4150                 case 14:
4151                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4152                         break;
4153                 }
4154                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4155                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4156         } else {
4157                 if (is_lvds) {
4158                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4159                 } else {
4160                         if (clock.p1 == 2)
4161                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4162                         else
4163                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4164                         if (clock.p2 == 4)
4165                                 dpll |= PLL_P2_DIVIDE_BY_4;
4166                 }
4167         }
4168
4169         if (is_sdvo && is_tv)
4170                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4171         else if (is_tv)
4172                 /* XXX: just matching BIOS for now */
4173                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4174                 dpll |= 3;
4175         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
4176                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4177         else
4178                 dpll |= PLL_REF_INPUT_DREFCLK;
4179
4180         /* setup pipeconf */
4181         pipeconf = I915_READ(PIPECONF(pipe));
4182
4183         /* Set up the display plane register */
4184         dspcntr = DISPPLANE_GAMMA_ENABLE;
4185
4186         /* Ironlake's plane is forced to pipe, bit 24 is to
4187            enable color space conversion */
4188         if (!HAS_PCH_SPLIT(dev)) {
4189                 if (pipe == 0)
4190                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4191                 else
4192                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4193         }
4194
4195         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4196                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4197                  * core speed.
4198                  *
4199                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4200                  * pipe == 0 check?
4201                  */
4202                 if (mode->clock >
4203                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4204                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4205                 else
4206                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4207         }
4208
4209         dspcntr |= DISPLAY_PLANE_ENABLE;
4210         pipeconf |= PIPECONF_ENABLE;
4211         dpll |= DPLL_VCO_ENABLE;
4212
4213         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4214         drm_mode_debug_printmodeline(mode);
4215
4216         /* assign to Ironlake registers */
4217         if (HAS_PCH_SPLIT(dev)) {
4218                 fp_reg = PCH_FP0(pipe);
4219                 dpll_reg = PCH_DPLL(pipe);
4220         } else {
4221                 fp_reg = FP0(pipe);
4222                 dpll_reg = DPLL(pipe);
4223         }
4224
4225         /* PCH eDP needs FDI, but CPU eDP does not */
4226         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4227                 I915_WRITE(fp_reg, fp);
4228                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4229
4230                 POSTING_READ(dpll_reg);
4231                 udelay(150);
4232         }
4233
4234         /* enable transcoder DPLL */
4235         if (HAS_PCH_CPT(dev)) {
4236                 temp = I915_READ(PCH_DPLL_SEL);
4237                 if (pipe == 0)
4238                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4239                 else
4240                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4241                 I915_WRITE(PCH_DPLL_SEL, temp);
4242
4243                 POSTING_READ(PCH_DPLL_SEL);
4244                 udelay(150);
4245         }
4246
4247         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4248          * This is an exception to the general rule that mode_set doesn't turn
4249          * things on.
4250          */
4251         if (is_lvds) {
4252                 reg = LVDS;
4253                 if (HAS_PCH_SPLIT(dev))
4254                         reg = PCH_LVDS;
4255
4256                 temp = I915_READ(reg);
4257                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4258                 if (pipe == 1) {
4259                         if (HAS_PCH_CPT(dev))
4260                                 temp |= PORT_TRANS_B_SEL_CPT;
4261                         else
4262                                 temp |= LVDS_PIPEB_SELECT;
4263                 } else {
4264                         if (HAS_PCH_CPT(dev))
4265                                 temp &= ~PORT_TRANS_SEL_MASK;
4266                         else
4267                                 temp &= ~LVDS_PIPEB_SELECT;
4268                 }
4269                 /* set the corresponsding LVDS_BORDER bit */
4270                 temp |= dev_priv->lvds_border_bits;
4271                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4272                  * set the DPLLs for dual-channel mode or not.
4273                  */
4274                 if (clock.p2 == 7)
4275                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4276                 else
4277                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4278
4279                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4280                  * appropriately here, but we need to look more thoroughly into how
4281                  * panels behave in the two modes.
4282                  */
4283                 /* set the dithering flag on non-PCH LVDS as needed */
4284                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4285                         if (dev_priv->lvds_dither)
4286                                 temp |= LVDS_ENABLE_DITHER;
4287                         else
4288                                 temp &= ~LVDS_ENABLE_DITHER;
4289                 }
4290                 I915_WRITE(reg, temp);
4291         }
4292
4293         /* set the dithering flag and clear for anything other than a panel. */
4294         if (HAS_PCH_SPLIT(dev)) {
4295                 pipeconf &= ~PIPECONF_DITHER_EN;
4296                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4297                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4298                         pipeconf |= PIPECONF_DITHER_EN;
4299                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4300                 }
4301         }
4302
4303         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4304                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4305         } else if (HAS_PCH_SPLIT(dev)) {
4306                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4307                 if (pipe == 0) {
4308                         I915_WRITE(TRANSA_DATA_M1, 0);
4309                         I915_WRITE(TRANSA_DATA_N1, 0);
4310                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4311                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4312                 } else {
4313                         I915_WRITE(TRANSB_DATA_M1, 0);
4314                         I915_WRITE(TRANSB_DATA_N1, 0);
4315                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4316                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4317                 }
4318         }
4319
4320         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4321                 I915_WRITE(dpll_reg, dpll);
4322
4323                 /* Wait for the clocks to stabilize. */
4324                 POSTING_READ(dpll_reg);
4325                 udelay(150);
4326
4327                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4328                         temp = 0;
4329                         if (is_sdvo) {
4330                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4331                                 if (temp > 1)
4332                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4333                                 else
4334                                         temp = 0;
4335                         }
4336                         I915_WRITE(DPLL_MD(pipe), temp);
4337                 } else {
4338                         /* The pixel multiplier can only be updated once the
4339                          * DPLL is enabled and the clocks are stable.
4340                          *
4341                          * So write it again.
4342                          */
4343                         I915_WRITE(dpll_reg, dpll);
4344                 }
4345         }
4346
4347         intel_crtc->lowfreq_avail = false;
4348         if (is_lvds && has_reduced_clock && i915_powersave) {
4349                 I915_WRITE(fp_reg + 4, fp2);
4350                 intel_crtc->lowfreq_avail = true;
4351                 if (HAS_PIPE_CXSR(dev)) {
4352                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4353                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4354                 }
4355         } else {
4356                 I915_WRITE(fp_reg + 4, fp);
4357                 if (HAS_PIPE_CXSR(dev)) {
4358                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4359                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4360                 }
4361         }
4362
4363         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4364                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4365                 /* the chip adds 2 halflines automatically */
4366                 adjusted_mode->crtc_vdisplay -= 1;
4367                 adjusted_mode->crtc_vtotal -= 1;
4368                 adjusted_mode->crtc_vblank_start -= 1;
4369                 adjusted_mode->crtc_vblank_end -= 1;
4370                 adjusted_mode->crtc_vsync_end -= 1;
4371                 adjusted_mode->crtc_vsync_start -= 1;
4372         } else
4373                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4374
4375         I915_WRITE(HTOTAL(pipe),
4376                    (adjusted_mode->crtc_hdisplay - 1) |
4377                    ((adjusted_mode->crtc_htotal - 1) << 16));
4378         I915_WRITE(HBLANK(pipe),
4379                    (adjusted_mode->crtc_hblank_start - 1) |
4380                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4381         I915_WRITE(HSYNC(pipe),
4382                    (adjusted_mode->crtc_hsync_start - 1) |
4383                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4384
4385         I915_WRITE(VTOTAL(pipe),
4386                    (adjusted_mode->crtc_vdisplay - 1) |
4387                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4388         I915_WRITE(VBLANK(pipe),
4389                    (adjusted_mode->crtc_vblank_start - 1) |
4390                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4391         I915_WRITE(VSYNC(pipe),
4392                    (adjusted_mode->crtc_vsync_start - 1) |
4393                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4394
4395         /* pipesrc and dspsize control the size that is scaled from,
4396          * which should always be the user's requested size.
4397          */
4398         if (!HAS_PCH_SPLIT(dev)) {
4399                 I915_WRITE(DSPSIZE(plane),
4400                            ((mode->vdisplay - 1) << 16) |
4401                            (mode->hdisplay - 1));
4402                 I915_WRITE(DSPPOS(plane), 0);
4403         }
4404         I915_WRITE(PIPESRC(pipe),
4405                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4406
4407         if (HAS_PCH_SPLIT(dev)) {
4408                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4409                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4410                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4411                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4412
4413                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4414                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4415                 }
4416         }
4417
4418         I915_WRITE(PIPECONF(pipe), pipeconf);
4419         POSTING_READ(PIPECONF(pipe));
4420
4421         intel_wait_for_vblank(dev, pipe);
4422
4423         if (IS_GEN5(dev)) {
4424                 /* enable address swizzle for tiling buffer */
4425                 temp = I915_READ(DISP_ARB_CTL);
4426                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4427         }
4428
4429         I915_WRITE(DSPCNTR(plane), dspcntr);
4430
4431         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4432
4433         intel_update_watermarks(dev);
4434
4435         drm_vblank_post_modeset(dev, pipe);
4436
4437         return ret;
4438 }
4439
4440 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4441 void intel_crtc_load_lut(struct drm_crtc *crtc)
4442 {
4443         struct drm_device *dev = crtc->dev;
4444         struct drm_i915_private *dev_priv = dev->dev_private;
4445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4446         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4447         int i;
4448
4449         /* The clocks have to be on to load the palette. */
4450         if (!crtc->enabled)
4451                 return;
4452
4453         /* use legacy palette for Ironlake */
4454         if (HAS_PCH_SPLIT(dev))
4455                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4456                                                    LGC_PALETTE_B;
4457
4458         for (i = 0; i < 256; i++) {
4459                 I915_WRITE(palreg + 4 * i,
4460                            (intel_crtc->lut_r[i] << 16) |
4461                            (intel_crtc->lut_g[i] << 8) |
4462                            intel_crtc->lut_b[i]);
4463         }
4464 }
4465
4466 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4467 {
4468         struct drm_device *dev = crtc->dev;
4469         struct drm_i915_private *dev_priv = dev->dev_private;
4470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4471         bool visible = base != 0;
4472         u32 cntl;
4473
4474         if (intel_crtc->cursor_visible == visible)
4475                 return;
4476
4477         cntl = I915_READ(CURACNTR);
4478         if (visible) {
4479                 /* On these chipsets we can only modify the base whilst
4480                  * the cursor is disabled.
4481                  */
4482                 I915_WRITE(CURABASE, base);
4483
4484                 cntl &= ~(CURSOR_FORMAT_MASK);
4485                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4486                 cntl |= CURSOR_ENABLE |
4487                         CURSOR_GAMMA_ENABLE |
4488                         CURSOR_FORMAT_ARGB;
4489         } else
4490                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4491         I915_WRITE(CURACNTR, cntl);
4492
4493         intel_crtc->cursor_visible = visible;
4494 }
4495
4496 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4497 {
4498         struct drm_device *dev = crtc->dev;
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4501         int pipe = intel_crtc->pipe;
4502         bool visible = base != 0;
4503
4504         if (intel_crtc->cursor_visible != visible) {
4505                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4506                 if (base) {
4507                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4508                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4509                         cntl |= pipe << 28; /* Connect to correct pipe */
4510                 } else {
4511                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4512                         cntl |= CURSOR_MODE_DISABLE;
4513                 }
4514                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4515
4516                 intel_crtc->cursor_visible = visible;
4517         }
4518         /* and commit changes on next vblank */
4519         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4520 }
4521
4522 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4523 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4524                                      bool on)
4525 {
4526         struct drm_device *dev = crtc->dev;
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4529         int pipe = intel_crtc->pipe;
4530         int x = intel_crtc->cursor_x;
4531         int y = intel_crtc->cursor_y;
4532         u32 base, pos;
4533         bool visible;
4534
4535         pos = 0;
4536
4537         if (on && crtc->enabled && crtc->fb) {
4538                 base = intel_crtc->cursor_addr;
4539                 if (x > (int) crtc->fb->width)
4540                         base = 0;
4541
4542                 if (y > (int) crtc->fb->height)
4543                         base = 0;
4544         } else
4545                 base = 0;
4546
4547         if (x < 0) {
4548                 if (x + intel_crtc->cursor_width < 0)
4549                         base = 0;
4550
4551                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4552                 x = -x;
4553         }
4554         pos |= x << CURSOR_X_SHIFT;
4555
4556         if (y < 0) {
4557                 if (y + intel_crtc->cursor_height < 0)
4558                         base = 0;
4559
4560                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4561                 y = -y;
4562         }
4563         pos |= y << CURSOR_Y_SHIFT;
4564
4565         visible = base != 0;
4566         if (!visible && !intel_crtc->cursor_visible)
4567                 return;
4568
4569         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4570         if (IS_845G(dev) || IS_I865G(dev))
4571                 i845_update_cursor(crtc, base);
4572         else
4573                 i9xx_update_cursor(crtc, base);
4574
4575         if (visible)
4576                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4577 }
4578
4579 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4580                                  struct drm_file *file,
4581                                  uint32_t handle,
4582                                  uint32_t width, uint32_t height)
4583 {
4584         struct drm_device *dev = crtc->dev;
4585         struct drm_i915_private *dev_priv = dev->dev_private;
4586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4587         struct drm_i915_gem_object *obj;
4588         uint32_t addr;
4589         int ret;
4590
4591         DRM_DEBUG_KMS("\n");
4592
4593         /* if we want to turn off the cursor ignore width and height */
4594         if (!handle) {
4595                 DRM_DEBUG_KMS("cursor off\n");
4596                 addr = 0;
4597                 obj = NULL;
4598                 mutex_lock(&dev->struct_mutex);
4599                 goto finish;
4600         }
4601
4602         /* Currently we only support 64x64 cursors */
4603         if (width != 64 || height != 64) {
4604                 DRM_ERROR("we currently only support 64x64 cursors\n");
4605                 return -EINVAL;
4606         }
4607
4608         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4609         if (!obj)
4610                 return -ENOENT;
4611
4612         if (obj->base.size < width * height * 4) {
4613                 DRM_ERROR("buffer is to small\n");
4614                 ret = -ENOMEM;
4615                 goto fail;
4616         }
4617
4618         /* we only need to pin inside GTT if cursor is non-phy */
4619         mutex_lock(&dev->struct_mutex);
4620         if (!dev_priv->info->cursor_needs_physical) {
4621                 if (obj->tiling_mode) {
4622                         DRM_ERROR("cursor cannot be tiled\n");
4623                         ret = -EINVAL;
4624                         goto fail_locked;
4625                 }
4626
4627                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4628                 if (ret) {
4629                         DRM_ERROR("failed to pin cursor bo\n");
4630                         goto fail_locked;
4631                 }
4632
4633                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4634                 if (ret) {
4635                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4636                         goto fail_unpin;
4637                 }
4638
4639                 ret = i915_gem_object_put_fence(obj);
4640                 if (ret) {
4641                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4642                         goto fail_unpin;
4643                 }
4644
4645                 addr = obj->gtt_offset;
4646         } else {
4647                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4648                 ret = i915_gem_attach_phys_object(dev, obj,
4649                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4650                                                   align);
4651                 if (ret) {
4652                         DRM_ERROR("failed to attach phys object\n");
4653                         goto fail_locked;
4654                 }
4655                 addr = obj->phys_obj->handle->busaddr;
4656         }
4657
4658         if (IS_GEN2(dev))
4659                 I915_WRITE(CURSIZE, (height << 12) | width);
4660
4661  finish:
4662         if (intel_crtc->cursor_bo) {
4663                 if (dev_priv->info->cursor_needs_physical) {
4664                         if (intel_crtc->cursor_bo != obj)
4665                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4666                 } else
4667                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4668                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4669         }
4670
4671         mutex_unlock(&dev->struct_mutex);
4672
4673         intel_crtc->cursor_addr = addr;
4674         intel_crtc->cursor_bo = obj;
4675         intel_crtc->cursor_width = width;
4676         intel_crtc->cursor_height = height;
4677
4678         intel_crtc_update_cursor(crtc, true);
4679
4680         return 0;
4681 fail_unpin:
4682         i915_gem_object_unpin(obj);
4683 fail_locked:
4684         mutex_unlock(&dev->struct_mutex);
4685 fail:
4686         drm_gem_object_unreference_unlocked(&obj->base);
4687         return ret;
4688 }
4689
4690 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4691 {
4692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4693
4694         intel_crtc->cursor_x = x;
4695         intel_crtc->cursor_y = y;
4696
4697         intel_crtc_update_cursor(crtc, true);
4698
4699         return 0;
4700 }
4701
4702 /** Sets the color ramps on behalf of RandR */
4703 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4704                                  u16 blue, int regno)
4705 {
4706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707
4708         intel_crtc->lut_r[regno] = red >> 8;
4709         intel_crtc->lut_g[regno] = green >> 8;
4710         intel_crtc->lut_b[regno] = blue >> 8;
4711 }
4712
4713 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4714                              u16 *blue, int regno)
4715 {
4716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717
4718         *red = intel_crtc->lut_r[regno] << 8;
4719         *green = intel_crtc->lut_g[regno] << 8;
4720         *blue = intel_crtc->lut_b[regno] << 8;
4721 }
4722
4723 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4724                                  u16 *blue, uint32_t start, uint32_t size)
4725 {
4726         int end = (start + size > 256) ? 256 : start + size, i;
4727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4728
4729         for (i = start; i < end; i++) {
4730                 intel_crtc->lut_r[i] = red[i] >> 8;
4731                 intel_crtc->lut_g[i] = green[i] >> 8;
4732                 intel_crtc->lut_b[i] = blue[i] >> 8;
4733         }
4734
4735         intel_crtc_load_lut(crtc);
4736 }
4737
4738 /**
4739  * Get a pipe with a simple mode set on it for doing load-based monitor
4740  * detection.
4741  *
4742  * It will be up to the load-detect code to adjust the pipe as appropriate for
4743  * its requirements.  The pipe will be connected to no other encoders.
4744  *
4745  * Currently this code will only succeed if there is a pipe with no encoders
4746  * configured for it.  In the future, it could choose to temporarily disable
4747  * some outputs to free up a pipe for its use.
4748  *
4749  * \return crtc, or NULL if no pipes are available.
4750  */
4751
4752 /* VESA 640x480x72Hz mode to set on the pipe */
4753 static struct drm_display_mode load_detect_mode = {
4754         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4755                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4756 };
4757
4758 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4759                                             struct drm_connector *connector,
4760                                             struct drm_display_mode *mode,
4761                                             int *dpms_mode)
4762 {
4763         struct intel_crtc *intel_crtc;
4764         struct drm_crtc *possible_crtc;
4765         struct drm_crtc *supported_crtc =NULL;
4766         struct drm_encoder *encoder = &intel_encoder->base;
4767         struct drm_crtc *crtc = NULL;
4768         struct drm_device *dev = encoder->dev;
4769         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4770         struct drm_crtc_helper_funcs *crtc_funcs;
4771         int i = -1;
4772
4773         /*
4774          * Algorithm gets a little messy:
4775          *   - if the connector already has an assigned crtc, use it (but make
4776          *     sure it's on first)
4777          *   - try to find the first unused crtc that can drive this connector,
4778          *     and use that if we find one
4779          *   - if there are no unused crtcs available, try to use the first
4780          *     one we found that supports the connector
4781          */
4782
4783         /* See if we already have a CRTC for this connector */
4784         if (encoder->crtc) {
4785                 crtc = encoder->crtc;
4786                 /* Make sure the crtc and connector are running */
4787                 intel_crtc = to_intel_crtc(crtc);
4788                 *dpms_mode = intel_crtc->dpms_mode;
4789                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4790                         crtc_funcs = crtc->helper_private;
4791                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4792                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4793                 }
4794                 return crtc;
4795         }
4796
4797         /* Find an unused one (if possible) */
4798         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4799                 i++;
4800                 if (!(encoder->possible_crtcs & (1 << i)))
4801                         continue;
4802                 if (!possible_crtc->enabled) {
4803                         crtc = possible_crtc;
4804                         break;
4805                 }
4806                 if (!supported_crtc)
4807                         supported_crtc = possible_crtc;
4808         }
4809
4810         /*
4811          * If we didn't find an unused CRTC, don't use any.
4812          */
4813         if (!crtc) {
4814                 return NULL;
4815         }
4816
4817         encoder->crtc = crtc;
4818         connector->encoder = encoder;
4819         intel_encoder->load_detect_temp = true;
4820
4821         intel_crtc = to_intel_crtc(crtc);
4822         *dpms_mode = intel_crtc->dpms_mode;
4823
4824         if (!crtc->enabled) {
4825                 if (!mode)
4826                         mode = &load_detect_mode;
4827                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4828         } else {
4829                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4830                         crtc_funcs = crtc->helper_private;
4831                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4832                 }
4833
4834                 /* Add this connector to the crtc */
4835                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4836                 encoder_funcs->commit(encoder);
4837         }
4838         /* let the connector get through one full cycle before testing */
4839         intel_wait_for_vblank(dev, intel_crtc->pipe);
4840
4841         return crtc;
4842 }
4843
4844 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4845                                     struct drm_connector *connector, int dpms_mode)
4846 {
4847         struct drm_encoder *encoder = &intel_encoder->base;
4848         struct drm_device *dev = encoder->dev;
4849         struct drm_crtc *crtc = encoder->crtc;
4850         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4851         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4852
4853         if (intel_encoder->load_detect_temp) {
4854                 encoder->crtc = NULL;
4855                 connector->encoder = NULL;
4856                 intel_encoder->load_detect_temp = false;
4857                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4858                 drm_helper_disable_unused_functions(dev);
4859         }
4860
4861         /* Switch crtc and encoder back off if necessary */
4862         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4863                 if (encoder->crtc == crtc)
4864                         encoder_funcs->dpms(encoder, dpms_mode);
4865                 crtc_funcs->dpms(crtc, dpms_mode);
4866         }
4867 }
4868
4869 /* Returns the clock of the currently programmed mode of the given pipe. */
4870 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4871 {
4872         struct drm_i915_private *dev_priv = dev->dev_private;
4873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4874         int pipe = intel_crtc->pipe;
4875         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4876         u32 fp;
4877         intel_clock_t clock;
4878
4879         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4880                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4881         else
4882                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4883
4884         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4885         if (IS_PINEVIEW(dev)) {
4886                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4887                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4888         } else {
4889                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4890                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4891         }
4892
4893         if (!IS_GEN2(dev)) {
4894                 if (IS_PINEVIEW(dev))
4895                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4896                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4897                 else
4898                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4899                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4900
4901                 switch (dpll & DPLL_MODE_MASK) {
4902                 case DPLLB_MODE_DAC_SERIAL:
4903                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4904                                 5 : 10;
4905                         break;
4906                 case DPLLB_MODE_LVDS:
4907                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4908                                 7 : 14;
4909                         break;
4910                 default:
4911                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4912                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4913                         return 0;
4914                 }
4915
4916                 /* XXX: Handle the 100Mhz refclk */
4917                 intel_clock(dev, 96000, &clock);
4918         } else {
4919                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4920
4921                 if (is_lvds) {
4922                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4923                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4924                         clock.p2 = 14;
4925
4926                         if ((dpll & PLL_REF_INPUT_MASK) ==
4927                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4928                                 /* XXX: might not be 66MHz */
4929                                 intel_clock(dev, 66000, &clock);
4930                         } else
4931                                 intel_clock(dev, 48000, &clock);
4932                 } else {
4933                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4934                                 clock.p1 = 2;
4935                         else {
4936                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4937                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4938                         }
4939                         if (dpll & PLL_P2_DIVIDE_BY_4)
4940                                 clock.p2 = 4;
4941                         else
4942                                 clock.p2 = 2;
4943
4944                         intel_clock(dev, 48000, &clock);
4945                 }
4946         }
4947
4948         /* XXX: It would be nice to validate the clocks, but we can't reuse
4949          * i830PllIsValid() because it relies on the xf86_config connector
4950          * configuration being accurate, which it isn't necessarily.
4951          */
4952
4953         return clock.dot;
4954 }
4955
4956 /** Returns the currently programmed mode of the given pipe. */
4957 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4958                                              struct drm_crtc *crtc)
4959 {
4960         struct drm_i915_private *dev_priv = dev->dev_private;
4961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962         int pipe = intel_crtc->pipe;
4963         struct drm_display_mode *mode;
4964         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4965         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4966         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4967         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4968
4969         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4970         if (!mode)
4971                 return NULL;
4972
4973         mode->clock = intel_crtc_clock_get(dev, crtc);
4974         mode->hdisplay = (htot & 0xffff) + 1;
4975         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4976         mode->hsync_start = (hsync & 0xffff) + 1;
4977         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4978         mode->vdisplay = (vtot & 0xffff) + 1;
4979         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4980         mode->vsync_start = (vsync & 0xffff) + 1;
4981         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4982
4983         drm_mode_set_name(mode);
4984         drm_mode_set_crtcinfo(mode, 0);
4985
4986         return mode;
4987 }
4988
4989 #define GPU_IDLE_TIMEOUT 500 /* ms */
4990
4991 /* When this timer fires, we've been idle for awhile */
4992 static void intel_gpu_idle_timer(unsigned long arg)
4993 {
4994         struct drm_device *dev = (struct drm_device *)arg;
4995         drm_i915_private_t *dev_priv = dev->dev_private;
4996
4997         if (!list_empty(&dev_priv->mm.active_list)) {
4998                 /* Still processing requests, so just re-arm the timer. */
4999                 mod_timer(&dev_priv->idle_timer, jiffies +
5000                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5001                 return;
5002         }
5003
5004         dev_priv->busy = false;
5005         queue_work(dev_priv->wq, &dev_priv->idle_work);
5006 }
5007
5008 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5009
5010 static void intel_crtc_idle_timer(unsigned long arg)
5011 {
5012         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5013         struct drm_crtc *crtc = &intel_crtc->base;
5014         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5015         struct intel_framebuffer *intel_fb;
5016
5017         intel_fb = to_intel_framebuffer(crtc->fb);
5018         if (intel_fb && intel_fb->obj->active) {
5019                 /* The framebuffer is still being accessed by the GPU. */
5020                 mod_timer(&intel_crtc->idle_timer, jiffies +
5021                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5022                 return;
5023         }
5024
5025         intel_crtc->busy = false;
5026         queue_work(dev_priv->wq, &dev_priv->idle_work);
5027 }
5028
5029 static void intel_increase_pllclock(struct drm_crtc *crtc)
5030 {
5031         struct drm_device *dev = crtc->dev;
5032         drm_i915_private_t *dev_priv = dev->dev_private;
5033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5034         int pipe = intel_crtc->pipe;
5035         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5036         int dpll = I915_READ(dpll_reg);
5037
5038         if (HAS_PCH_SPLIT(dev))
5039                 return;
5040
5041         if (!dev_priv->lvds_downclock_avail)
5042                 return;
5043
5044         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5045                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5046
5047                 /* Unlock panel regs */
5048                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5049                            PANEL_UNLOCK_REGS);
5050
5051                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5052                 I915_WRITE(dpll_reg, dpll);
5053                 dpll = I915_READ(dpll_reg);
5054                 intel_wait_for_vblank(dev, pipe);
5055                 dpll = I915_READ(dpll_reg);
5056                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5057                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5058
5059                 /* ...and lock them again */
5060                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5061         }
5062
5063         /* Schedule downclock */
5064         mod_timer(&intel_crtc->idle_timer, jiffies +
5065                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5066 }
5067
5068 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5069 {
5070         struct drm_device *dev = crtc->dev;
5071         drm_i915_private_t *dev_priv = dev->dev_private;
5072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5073         int pipe = intel_crtc->pipe;
5074         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5075         int dpll = I915_READ(dpll_reg);
5076
5077         if (HAS_PCH_SPLIT(dev))
5078                 return;
5079
5080         if (!dev_priv->lvds_downclock_avail)
5081                 return;
5082
5083         /*
5084          * Since this is called by a timer, we should never get here in
5085          * the manual case.
5086          */
5087         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5088                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5089
5090                 /* Unlock panel regs */
5091                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5092                            PANEL_UNLOCK_REGS);
5093
5094                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5095                 I915_WRITE(dpll_reg, dpll);
5096                 dpll = I915_READ(dpll_reg);
5097                 intel_wait_for_vblank(dev, pipe);
5098                 dpll = I915_READ(dpll_reg);
5099                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5100                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5101
5102                 /* ...and lock them again */
5103                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5104         }
5105
5106 }
5107
5108 /**
5109  * intel_idle_update - adjust clocks for idleness
5110  * @work: work struct
5111  *
5112  * Either the GPU or display (or both) went idle.  Check the busy status
5113  * here and adjust the CRTC and GPU clocks as necessary.
5114  */
5115 static void intel_idle_update(struct work_struct *work)
5116 {
5117         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5118                                                     idle_work);
5119         struct drm_device *dev = dev_priv->dev;
5120         struct drm_crtc *crtc;
5121         struct intel_crtc *intel_crtc;
5122         int enabled = 0;
5123
5124         if (!i915_powersave)
5125                 return;
5126
5127         mutex_lock(&dev->struct_mutex);
5128
5129         i915_update_gfx_val(dev_priv);
5130
5131         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5132                 /* Skip inactive CRTCs */
5133                 if (!crtc->fb)
5134                         continue;
5135
5136                 enabled++;
5137                 intel_crtc = to_intel_crtc(crtc);
5138                 if (!intel_crtc->busy)
5139                         intel_decrease_pllclock(crtc);
5140         }
5141
5142         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5143                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5144                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5145         }
5146
5147         mutex_unlock(&dev->struct_mutex);
5148 }
5149
5150 /**
5151  * intel_mark_busy - mark the GPU and possibly the display busy
5152  * @dev: drm device
5153  * @obj: object we're operating on
5154  *
5155  * Callers can use this function to indicate that the GPU is busy processing
5156  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5157  * buffer), we'll also mark the display as busy, so we know to increase its
5158  * clock frequency.
5159  */
5160 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5161 {
5162         drm_i915_private_t *dev_priv = dev->dev_private;
5163         struct drm_crtc *crtc = NULL;
5164         struct intel_framebuffer *intel_fb;
5165         struct intel_crtc *intel_crtc;
5166
5167         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5168                 return;
5169
5170         if (!dev_priv->busy) {
5171                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5172                         u32 fw_blc_self;
5173
5174                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5175                         fw_blc_self = I915_READ(FW_BLC_SELF);
5176                         fw_blc_self &= ~FW_BLC_SELF_EN;
5177                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5178                 }
5179                 dev_priv->busy = true;
5180         } else
5181                 mod_timer(&dev_priv->idle_timer, jiffies +
5182                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5183
5184         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5185                 if (!crtc->fb)
5186                         continue;
5187
5188                 intel_crtc = to_intel_crtc(crtc);
5189                 intel_fb = to_intel_framebuffer(crtc->fb);
5190                 if (intel_fb->obj == obj) {
5191                         if (!intel_crtc->busy) {
5192                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5193                                         u32 fw_blc_self;
5194
5195                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5196                                         fw_blc_self = I915_READ(FW_BLC_SELF);
5197                                         fw_blc_self &= ~FW_BLC_SELF_EN;
5198                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5199                                 }
5200                                 /* Non-busy -> busy, upclock */
5201                                 intel_increase_pllclock(crtc);
5202                                 intel_crtc->busy = true;
5203                         } else {
5204                                 /* Busy -> busy, put off timer */
5205                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5206                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5207                         }
5208                 }
5209         }
5210 }
5211
5212 static void intel_crtc_destroy(struct drm_crtc *crtc)
5213 {
5214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5215         struct drm_device *dev = crtc->dev;
5216         struct intel_unpin_work *work;
5217         unsigned long flags;
5218
5219         spin_lock_irqsave(&dev->event_lock, flags);
5220         work = intel_crtc->unpin_work;
5221         intel_crtc->unpin_work = NULL;
5222         spin_unlock_irqrestore(&dev->event_lock, flags);
5223
5224         if (work) {
5225                 cancel_work_sync(&work->work);
5226                 kfree(work);
5227         }
5228
5229         drm_crtc_cleanup(crtc);
5230
5231         kfree(intel_crtc);
5232 }
5233
5234 static void intel_unpin_work_fn(struct work_struct *__work)
5235 {
5236         struct intel_unpin_work *work =
5237                 container_of(__work, struct intel_unpin_work, work);
5238
5239         mutex_lock(&work->dev->struct_mutex);
5240         i915_gem_object_unpin(work->old_fb_obj);
5241         drm_gem_object_unreference(&work->pending_flip_obj->base);
5242         drm_gem_object_unreference(&work->old_fb_obj->base);
5243
5244         mutex_unlock(&work->dev->struct_mutex);
5245         kfree(work);
5246 }
5247
5248 static void do_intel_finish_page_flip(struct drm_device *dev,
5249                                       struct drm_crtc *crtc)
5250 {
5251         drm_i915_private_t *dev_priv = dev->dev_private;
5252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5253         struct intel_unpin_work *work;
5254         struct drm_i915_gem_object *obj;
5255         struct drm_pending_vblank_event *e;
5256         struct timeval now;
5257         unsigned long flags;
5258
5259         /* Ignore early vblank irqs */
5260         if (intel_crtc == NULL)
5261                 return;
5262
5263         spin_lock_irqsave(&dev->event_lock, flags);
5264         work = intel_crtc->unpin_work;
5265         if (work == NULL || !work->pending) {
5266                 spin_unlock_irqrestore(&dev->event_lock, flags);
5267                 return;
5268         }
5269
5270         intel_crtc->unpin_work = NULL;
5271         drm_vblank_put(dev, intel_crtc->pipe);
5272
5273         if (work->event) {
5274                 e = work->event;
5275                 do_gettimeofday(&now);
5276                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5277                 e->event.tv_sec = now.tv_sec;
5278                 e->event.tv_usec = now.tv_usec;
5279                 list_add_tail(&e->base.link,
5280                               &e->base.file_priv->event_list);
5281                 wake_up_interruptible(&e->base.file_priv->event_wait);
5282         }
5283
5284         spin_unlock_irqrestore(&dev->event_lock, flags);
5285
5286         obj = work->old_fb_obj;
5287
5288         atomic_clear_mask(1 << intel_crtc->plane,
5289                           &obj->pending_flip.counter);
5290         if (atomic_read(&obj->pending_flip) == 0)
5291                 wake_up(&dev_priv->pending_flip_queue);
5292
5293         schedule_work(&work->work);
5294
5295         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5296 }
5297
5298 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5299 {
5300         drm_i915_private_t *dev_priv = dev->dev_private;
5301         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5302
5303         do_intel_finish_page_flip(dev, crtc);
5304 }
5305
5306 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5307 {
5308         drm_i915_private_t *dev_priv = dev->dev_private;
5309         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5310
5311         do_intel_finish_page_flip(dev, crtc);
5312 }
5313
5314 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5315 {
5316         drm_i915_private_t *dev_priv = dev->dev_private;
5317         struct intel_crtc *intel_crtc =
5318                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5319         unsigned long flags;
5320
5321         spin_lock_irqsave(&dev->event_lock, flags);
5322         if (intel_crtc->unpin_work) {
5323                 if ((++intel_crtc->unpin_work->pending) > 1)
5324                         DRM_ERROR("Prepared flip multiple times\n");
5325         } else {
5326                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5327         }
5328         spin_unlock_irqrestore(&dev->event_lock, flags);
5329 }
5330
5331 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5332                                 struct drm_framebuffer *fb,
5333                                 struct drm_pending_vblank_event *event)
5334 {
5335         struct drm_device *dev = crtc->dev;
5336         struct drm_i915_private *dev_priv = dev->dev_private;
5337         struct intel_framebuffer *intel_fb;
5338         struct drm_i915_gem_object *obj;
5339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5340         struct intel_unpin_work *work;
5341         unsigned long flags, offset;
5342         int pipe = intel_crtc->pipe;
5343         u32 pf, pipesrc;
5344         int ret;
5345
5346         work = kzalloc(sizeof *work, GFP_KERNEL);
5347         if (work == NULL)
5348                 return -ENOMEM;
5349
5350         work->event = event;
5351         work->dev = crtc->dev;
5352         intel_fb = to_intel_framebuffer(crtc->fb);
5353         work->old_fb_obj = intel_fb->obj;
5354         INIT_WORK(&work->work, intel_unpin_work_fn);
5355
5356         /* We borrow the event spin lock for protecting unpin_work */
5357         spin_lock_irqsave(&dev->event_lock, flags);
5358         if (intel_crtc->unpin_work) {
5359                 spin_unlock_irqrestore(&dev->event_lock, flags);
5360                 kfree(work);
5361
5362                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5363                 return -EBUSY;
5364         }
5365         intel_crtc->unpin_work = work;
5366         spin_unlock_irqrestore(&dev->event_lock, flags);
5367
5368         intel_fb = to_intel_framebuffer(fb);
5369         obj = intel_fb->obj;
5370
5371         mutex_lock(&dev->struct_mutex);
5372         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5373         if (ret)
5374                 goto cleanup_work;
5375
5376         /* Reference the objects for the scheduled work. */
5377         drm_gem_object_reference(&work->old_fb_obj->base);
5378         drm_gem_object_reference(&obj->base);
5379
5380         crtc->fb = fb;
5381
5382         ret = drm_vblank_get(dev, intel_crtc->pipe);
5383         if (ret)
5384                 goto cleanup_objs;
5385
5386         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5387                 u32 flip_mask;
5388
5389                 /* Can't queue multiple flips, so wait for the previous
5390                  * one to finish before executing the next.
5391                  */
5392                 ret = BEGIN_LP_RING(2);
5393                 if (ret)
5394                         goto cleanup_objs;
5395
5396                 if (intel_crtc->plane)
5397                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5398                 else
5399                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5400                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5401                 OUT_RING(MI_NOOP);
5402                 ADVANCE_LP_RING();
5403         }
5404
5405         work->pending_flip_obj = obj;
5406
5407         work->enable_stall_check = true;
5408
5409         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5410         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5411
5412         ret = BEGIN_LP_RING(4);
5413         if (ret)
5414                 goto cleanup_objs;
5415
5416         /* Block clients from rendering to the new back buffer until
5417          * the flip occurs and the object is no longer visible.
5418          */
5419         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5420
5421         switch (INTEL_INFO(dev)->gen) {
5422         case 2:
5423                 OUT_RING(MI_DISPLAY_FLIP |
5424                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5425                 OUT_RING(fb->pitch);
5426                 OUT_RING(obj->gtt_offset + offset);
5427                 OUT_RING(MI_NOOP);
5428                 break;
5429
5430         case 3:
5431                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5432                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5433                 OUT_RING(fb->pitch);
5434                 OUT_RING(obj->gtt_offset + offset);
5435                 OUT_RING(MI_NOOP);
5436                 break;
5437
5438         case 4:
5439         case 5:
5440                 /* i965+ uses the linear or tiled offsets from the
5441                  * Display Registers (which do not change across a page-flip)
5442                  * so we need only reprogram the base address.
5443                  */
5444                 OUT_RING(MI_DISPLAY_FLIP |
5445                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5446                 OUT_RING(fb->pitch);
5447                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5448
5449                 /* XXX Enabling the panel-fitter across page-flip is so far
5450                  * untested on non-native modes, so ignore it for now.
5451                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5452                  */
5453                 pf = 0;
5454                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5455                 OUT_RING(pf | pipesrc);
5456                 break;
5457
5458         case 6:
5459                 OUT_RING(MI_DISPLAY_FLIP |
5460                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5461                 OUT_RING(fb->pitch | obj->tiling_mode);
5462                 OUT_RING(obj->gtt_offset);
5463
5464                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5465                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5466                 OUT_RING(pf | pipesrc);
5467                 break;
5468         }
5469         ADVANCE_LP_RING();
5470
5471         mutex_unlock(&dev->struct_mutex);
5472
5473         trace_i915_flip_request(intel_crtc->plane, obj);
5474
5475         return 0;
5476
5477 cleanup_objs:
5478         drm_gem_object_unreference(&work->old_fb_obj->base);
5479         drm_gem_object_unreference(&obj->base);
5480 cleanup_work:
5481         mutex_unlock(&dev->struct_mutex);
5482
5483         spin_lock_irqsave(&dev->event_lock, flags);
5484         intel_crtc->unpin_work = NULL;
5485         spin_unlock_irqrestore(&dev->event_lock, flags);
5486
5487         kfree(work);
5488
5489         return ret;
5490 }
5491
5492 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5493         .dpms = intel_crtc_dpms,
5494         .mode_fixup = intel_crtc_mode_fixup,
5495         .mode_set = intel_crtc_mode_set,
5496         .mode_set_base = intel_pipe_set_base,
5497         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5498         .load_lut = intel_crtc_load_lut,
5499         .disable = intel_crtc_disable,
5500 };
5501
5502 static const struct drm_crtc_funcs intel_crtc_funcs = {
5503         .cursor_set = intel_crtc_cursor_set,
5504         .cursor_move = intel_crtc_cursor_move,
5505         .gamma_set = intel_crtc_gamma_set,
5506         .set_config = drm_crtc_helper_set_config,
5507         .destroy = intel_crtc_destroy,
5508         .page_flip = intel_crtc_page_flip,
5509 };
5510
5511 static void intel_sanitize_modesetting(struct drm_device *dev,
5512                                        int pipe, int plane)
5513 {
5514         struct drm_i915_private *dev_priv = dev->dev_private;
5515         u32 reg, val;
5516
5517         if (HAS_PCH_SPLIT(dev))
5518                 return;
5519
5520         /* Who knows what state these registers were left in by the BIOS or
5521          * grub?
5522          *
5523          * If we leave the registers in a conflicting state (e.g. with the
5524          * display plane reading from the other pipe than the one we intend
5525          * to use) then when we attempt to teardown the active mode, we will
5526          * not disable the pipes and planes in the correct order -- leaving
5527          * a plane reading from a disabled pipe and possibly leading to
5528          * undefined behaviour.
5529          */
5530
5531         reg = DSPCNTR(plane);
5532         val = I915_READ(reg);
5533
5534         if ((val & DISPLAY_PLANE_ENABLE) == 0)
5535                 return;
5536         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5537                 return;
5538
5539         /* This display plane is active and attached to the other CPU pipe. */
5540         pipe = !pipe;
5541
5542         /* Disable the plane and wait for it to stop reading from the pipe. */
5543         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5544         intel_flush_display_plane(dev, plane);
5545
5546         if (IS_GEN2(dev))
5547                 intel_wait_for_vblank(dev, pipe);
5548
5549         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5550                 return;
5551
5552         /* Switch off the pipe. */
5553         reg = PIPECONF(pipe);
5554         val = I915_READ(reg);
5555         if (val & PIPECONF_ENABLE) {
5556                 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5557                 intel_wait_for_pipe_off(dev, pipe);
5558         }
5559 }
5560
5561 static void intel_crtc_init(struct drm_device *dev, int pipe)
5562 {
5563         drm_i915_private_t *dev_priv = dev->dev_private;
5564         struct intel_crtc *intel_crtc;
5565         int i;
5566
5567         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5568         if (intel_crtc == NULL)
5569                 return;
5570
5571         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5572
5573         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5574         for (i = 0; i < 256; i++) {
5575                 intel_crtc->lut_r[i] = i;
5576                 intel_crtc->lut_g[i] = i;
5577                 intel_crtc->lut_b[i] = i;
5578         }
5579
5580         /* Swap pipes & planes for FBC on pre-965 */
5581         intel_crtc->pipe = pipe;
5582         intel_crtc->plane = pipe;
5583         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5584                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5585                 intel_crtc->plane = !pipe;
5586         }
5587
5588         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5589                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5590         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5591         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5592
5593         intel_crtc->cursor_addr = 0;
5594         intel_crtc->dpms_mode = -1;
5595         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5596
5597         if (HAS_PCH_SPLIT(dev)) {
5598                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5599                 intel_helper_funcs.commit = ironlake_crtc_commit;
5600         } else {
5601                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5602                 intel_helper_funcs.commit = i9xx_crtc_commit;
5603         }
5604
5605         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5606
5607         intel_crtc->busy = false;
5608
5609         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5610                     (unsigned long)intel_crtc);
5611
5612         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5613 }
5614
5615 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5616                                 struct drm_file *file)
5617 {
5618         drm_i915_private_t *dev_priv = dev->dev_private;
5619         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5620         struct drm_mode_object *drmmode_obj;
5621         struct intel_crtc *crtc;
5622
5623         if (!dev_priv) {
5624                 DRM_ERROR("called with no initialization\n");
5625                 return -EINVAL;
5626         }
5627
5628         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5629                         DRM_MODE_OBJECT_CRTC);
5630
5631         if (!drmmode_obj) {
5632                 DRM_ERROR("no such CRTC id\n");
5633                 return -EINVAL;
5634         }
5635
5636         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5637         pipe_from_crtc_id->pipe = crtc->pipe;
5638
5639         return 0;
5640 }
5641
5642 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5643 {
5644         struct intel_encoder *encoder;
5645         int index_mask = 0;
5646         int entry = 0;
5647
5648         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5649                 if (type_mask & encoder->clone_mask)
5650                         index_mask |= (1 << entry);
5651                 entry++;
5652         }
5653
5654         return index_mask;
5655 }
5656
5657 static void intel_setup_outputs(struct drm_device *dev)
5658 {
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660         struct intel_encoder *encoder;
5661         bool dpd_is_edp = false;
5662         bool has_lvds = false;
5663
5664         if (IS_MOBILE(dev) && !IS_I830(dev))
5665                 has_lvds = intel_lvds_init(dev);
5666         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5667                 /* disable the panel fitter on everything but LVDS */
5668                 I915_WRITE(PFIT_CONTROL, 0);
5669         }
5670
5671         if (HAS_PCH_SPLIT(dev)) {
5672                 dpd_is_edp = intel_dpd_is_edp(dev);
5673
5674                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5675                         intel_dp_init(dev, DP_A);
5676
5677                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5678                         intel_dp_init(dev, PCH_DP_D);
5679         }
5680
5681         intel_crt_init(dev);
5682
5683         if (HAS_PCH_SPLIT(dev)) {
5684                 int found;
5685
5686                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5687                         /* PCH SDVOB multiplex with HDMIB */
5688                         found = intel_sdvo_init(dev, PCH_SDVOB);
5689                         if (!found)
5690                                 intel_hdmi_init(dev, HDMIB);
5691                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5692                                 intel_dp_init(dev, PCH_DP_B);
5693                 }
5694
5695                 if (I915_READ(HDMIC) & PORT_DETECTED)
5696                         intel_hdmi_init(dev, HDMIC);
5697
5698                 if (I915_READ(HDMID) & PORT_DETECTED)
5699                         intel_hdmi_init(dev, HDMID);
5700
5701                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5702                         intel_dp_init(dev, PCH_DP_C);
5703
5704                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5705                         intel_dp_init(dev, PCH_DP_D);
5706
5707         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5708                 bool found = false;
5709
5710                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5711                         DRM_DEBUG_KMS("probing SDVOB\n");
5712                         found = intel_sdvo_init(dev, SDVOB);
5713                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5714                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5715                                 intel_hdmi_init(dev, SDVOB);
5716                         }
5717
5718                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5719                                 DRM_DEBUG_KMS("probing DP_B\n");
5720                                 intel_dp_init(dev, DP_B);
5721                         }
5722                 }
5723
5724                 /* Before G4X SDVOC doesn't have its own detect register */
5725
5726                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5727                         DRM_DEBUG_KMS("probing SDVOC\n");
5728                         found = intel_sdvo_init(dev, SDVOC);
5729                 }
5730
5731                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5732
5733                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5734                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5735                                 intel_hdmi_init(dev, SDVOC);
5736                         }
5737                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5738                                 DRM_DEBUG_KMS("probing DP_C\n");
5739                                 intel_dp_init(dev, DP_C);
5740                         }
5741                 }
5742
5743                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5744                     (I915_READ(DP_D) & DP_DETECTED)) {
5745                         DRM_DEBUG_KMS("probing DP_D\n");
5746                         intel_dp_init(dev, DP_D);
5747                 }
5748         } else if (IS_GEN2(dev))
5749                 intel_dvo_init(dev);
5750
5751         if (SUPPORTS_TV(dev))
5752                 intel_tv_init(dev);
5753
5754         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5755                 encoder->base.possible_crtcs = encoder->crtc_mask;
5756                 encoder->base.possible_clones =
5757                         intel_encoder_clones(dev, encoder->clone_mask);
5758         }
5759 }
5760
5761 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5762 {
5763         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5764
5765         drm_framebuffer_cleanup(fb);
5766         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5767
5768         kfree(intel_fb);
5769 }
5770
5771 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5772                                                 struct drm_file *file,
5773                                                 unsigned int *handle)
5774 {
5775         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5776         struct drm_i915_gem_object *obj = intel_fb->obj;
5777
5778         return drm_gem_handle_create(file, &obj->base, handle);
5779 }
5780
5781 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5782         .destroy = intel_user_framebuffer_destroy,
5783         .create_handle = intel_user_framebuffer_create_handle,
5784 };
5785
5786 int intel_framebuffer_init(struct drm_device *dev,
5787                            struct intel_framebuffer *intel_fb,
5788                            struct drm_mode_fb_cmd *mode_cmd,
5789                            struct drm_i915_gem_object *obj)
5790 {
5791         int ret;
5792
5793         if (obj->tiling_mode == I915_TILING_Y)
5794                 return -EINVAL;
5795
5796         if (mode_cmd->pitch & 63)
5797                 return -EINVAL;
5798
5799         switch (mode_cmd->bpp) {
5800         case 8:
5801         case 16:
5802         case 24:
5803         case 32:
5804                 break;
5805         default:
5806                 return -EINVAL;
5807         }
5808
5809         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5810         if (ret) {
5811                 DRM_ERROR("framebuffer init failed %d\n", ret);
5812                 return ret;
5813         }
5814
5815         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5816         intel_fb->obj = obj;
5817         return 0;
5818 }
5819
5820 static struct drm_framebuffer *
5821 intel_user_framebuffer_create(struct drm_device *dev,
5822                               struct drm_file *filp,
5823                               struct drm_mode_fb_cmd *mode_cmd)
5824 {
5825         struct drm_i915_gem_object *obj;
5826         struct intel_framebuffer *intel_fb;
5827         int ret;
5828
5829         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
5830         if (!obj)
5831                 return ERR_PTR(-ENOENT);
5832
5833         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5834         if (!intel_fb)
5835                 return ERR_PTR(-ENOMEM);
5836
5837         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5838         if (ret) {
5839                 drm_gem_object_unreference_unlocked(&obj->base);
5840                 kfree(intel_fb);
5841                 return ERR_PTR(ret);
5842         }
5843
5844         return &intel_fb->base;
5845 }
5846
5847 static const struct drm_mode_config_funcs intel_mode_funcs = {
5848         .fb_create = intel_user_framebuffer_create,
5849         .output_poll_changed = intel_fb_output_poll_changed,
5850 };
5851
5852 static struct drm_i915_gem_object *
5853 intel_alloc_context_page(struct drm_device *dev)
5854 {
5855         struct drm_i915_gem_object *ctx;
5856         int ret;
5857
5858         ctx = i915_gem_alloc_object(dev, 4096);
5859         if (!ctx) {
5860                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5861                 return NULL;
5862         }
5863
5864         mutex_lock(&dev->struct_mutex);
5865         ret = i915_gem_object_pin(ctx, 4096, true);
5866         if (ret) {
5867                 DRM_ERROR("failed to pin power context: %d\n", ret);
5868                 goto err_unref;
5869         }
5870
5871         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5872         if (ret) {
5873                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5874                 goto err_unpin;
5875         }
5876         mutex_unlock(&dev->struct_mutex);
5877
5878         return ctx;
5879
5880 err_unpin:
5881         i915_gem_object_unpin(ctx);
5882 err_unref:
5883         drm_gem_object_unreference(&ctx->base);
5884         mutex_unlock(&dev->struct_mutex);
5885         return NULL;
5886 }
5887
5888 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5889 {
5890         struct drm_i915_private *dev_priv = dev->dev_private;
5891         u16 rgvswctl;
5892
5893         rgvswctl = I915_READ16(MEMSWCTL);
5894         if (rgvswctl & MEMCTL_CMD_STS) {
5895                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5896                 return false; /* still busy with another command */
5897         }
5898
5899         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5900                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5901         I915_WRITE16(MEMSWCTL, rgvswctl);
5902         POSTING_READ16(MEMSWCTL);
5903
5904         rgvswctl |= MEMCTL_CMD_STS;
5905         I915_WRITE16(MEMSWCTL, rgvswctl);
5906
5907         return true;
5908 }
5909
5910 void ironlake_enable_drps(struct drm_device *dev)
5911 {
5912         struct drm_i915_private *dev_priv = dev->dev_private;
5913         u32 rgvmodectl = I915_READ(MEMMODECTL);
5914         u8 fmax, fmin, fstart, vstart;
5915
5916         /* Enable temp reporting */
5917         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5918         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5919
5920         /* 100ms RC evaluation intervals */
5921         I915_WRITE(RCUPEI, 100000);
5922         I915_WRITE(RCDNEI, 100000);
5923
5924         /* Set max/min thresholds to 90ms and 80ms respectively */
5925         I915_WRITE(RCBMAXAVG, 90000);
5926         I915_WRITE(RCBMINAVG, 80000);
5927
5928         I915_WRITE(MEMIHYST, 1);
5929
5930         /* Set up min, max, and cur for interrupt handling */
5931         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5932         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5933         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5934                 MEMMODE_FSTART_SHIFT;
5935
5936         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5937                 PXVFREQ_PX_SHIFT;
5938
5939         dev_priv->fmax = fmax; /* IPS callback will increase this */
5940         dev_priv->fstart = fstart;
5941
5942         dev_priv->max_delay = fstart;
5943         dev_priv->min_delay = fmin;
5944         dev_priv->cur_delay = fstart;
5945
5946         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5947                          fmax, fmin, fstart);
5948
5949         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5950
5951         /*
5952          * Interrupts will be enabled in ironlake_irq_postinstall
5953          */
5954
5955         I915_WRITE(VIDSTART, vstart);
5956         POSTING_READ(VIDSTART);
5957
5958         rgvmodectl |= MEMMODE_SWMODE_EN;
5959         I915_WRITE(MEMMODECTL, rgvmodectl);
5960
5961         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5962                 DRM_ERROR("stuck trying to change perf mode\n");
5963         msleep(1);
5964
5965         ironlake_set_drps(dev, fstart);
5966
5967         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5968                 I915_READ(0x112e0);
5969         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5970         dev_priv->last_count2 = I915_READ(0x112f4);
5971         getrawmonotonic(&dev_priv->last_time2);
5972 }
5973
5974 void ironlake_disable_drps(struct drm_device *dev)
5975 {
5976         struct drm_i915_private *dev_priv = dev->dev_private;
5977         u16 rgvswctl = I915_READ16(MEMSWCTL);
5978
5979         /* Ack interrupts, disable EFC interrupt */
5980         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5981         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5982         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5983         I915_WRITE(DEIIR, DE_PCU_EVENT);
5984         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5985
5986         /* Go back to the starting frequency */
5987         ironlake_set_drps(dev, dev_priv->fstart);
5988         msleep(1);
5989         rgvswctl |= MEMCTL_CMD_STS;
5990         I915_WRITE(MEMSWCTL, rgvswctl);
5991         msleep(1);
5992
5993 }
5994
5995 static unsigned long intel_pxfreq(u32 vidfreq)
5996 {
5997         unsigned long freq;
5998         int div = (vidfreq & 0x3f0000) >> 16;
5999         int post = (vidfreq & 0x3000) >> 12;
6000         int pre = (vidfreq & 0x7);
6001
6002         if (!pre)
6003                 return 0;
6004
6005         freq = ((div * 133333) / ((1<<post) * pre));
6006
6007         return freq;
6008 }
6009
6010 void intel_init_emon(struct drm_device *dev)
6011 {
6012         struct drm_i915_private *dev_priv = dev->dev_private;
6013         u32 lcfuse;
6014         u8 pxw[16];
6015         int i;
6016
6017         /* Disable to program */
6018         I915_WRITE(ECR, 0);
6019         POSTING_READ(ECR);
6020
6021         /* Program energy weights for various events */
6022         I915_WRITE(SDEW, 0x15040d00);
6023         I915_WRITE(CSIEW0, 0x007f0000);
6024         I915_WRITE(CSIEW1, 0x1e220004);
6025         I915_WRITE(CSIEW2, 0x04000004);
6026
6027         for (i = 0; i < 5; i++)
6028                 I915_WRITE(PEW + (i * 4), 0);
6029         for (i = 0; i < 3; i++)
6030                 I915_WRITE(DEW + (i * 4), 0);
6031
6032         /* Program P-state weights to account for frequency power adjustment */
6033         for (i = 0; i < 16; i++) {
6034                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6035                 unsigned long freq = intel_pxfreq(pxvidfreq);
6036                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6037                         PXVFREQ_PX_SHIFT;
6038                 unsigned long val;
6039
6040                 val = vid * vid;
6041                 val *= (freq / 1000);
6042                 val *= 255;
6043                 val /= (127*127*900);
6044                 if (val > 0xff)
6045                         DRM_ERROR("bad pxval: %ld\n", val);
6046                 pxw[i] = val;
6047         }
6048         /* Render standby states get 0 weight */
6049         pxw[14] = 0;
6050         pxw[15] = 0;
6051
6052         for (i = 0; i < 4; i++) {
6053                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6054                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6055                 I915_WRITE(PXW + (i * 4), val);
6056         }
6057
6058         /* Adjust magic regs to magic values (more experimental results) */
6059         I915_WRITE(OGW0, 0);
6060         I915_WRITE(OGW1, 0);
6061         I915_WRITE(EG0, 0x00007f00);
6062         I915_WRITE(EG1, 0x0000000e);
6063         I915_WRITE(EG2, 0x000e0000);
6064         I915_WRITE(EG3, 0x68000300);
6065         I915_WRITE(EG4, 0x42000000);
6066         I915_WRITE(EG5, 0x00140031);
6067         I915_WRITE(EG6, 0);
6068         I915_WRITE(EG7, 0);
6069
6070         for (i = 0; i < 8; i++)
6071                 I915_WRITE(PXWL + (i * 4), 0);
6072
6073         /* Enable PMON + select events */
6074         I915_WRITE(ECR, 0x80000019);
6075
6076         lcfuse = I915_READ(LCFUSE02);
6077
6078         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6079 }
6080
6081 static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
6082 {
6083         int i;
6084
6085         /* Here begins a magic sequence of register writes to enable
6086          * auto-downclocking.
6087          *
6088          * Perhaps there might be some value in exposing these to
6089          * userspace...
6090          */
6091         I915_WRITE(GEN6_RC_STATE, 0);
6092         __gen6_force_wake_get(dev_priv);
6093
6094         /* disable the counters and set determistic thresholds */
6095         I915_WRITE(GEN6_RC_CONTROL, 0);
6096
6097         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6098         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6099         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6100         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6101         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6102
6103         for (i = 0; i < I915_NUM_RINGS; i++)
6104                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6105
6106         I915_WRITE(GEN6_RC_SLEEP, 0);
6107         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6108         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6109         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6110         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6111
6112         I915_WRITE(GEN6_RC_CONTROL,
6113                    GEN6_RC_CTL_RC6p_ENABLE |
6114                    GEN6_RC_CTL_RC6_ENABLE |
6115                    GEN6_RC_CTL_HW_ENABLE);
6116
6117         I915_WRITE(GEN6_RC_NORMAL_FREQ,
6118                    GEN6_FREQUENCY(10) |
6119                    GEN6_OFFSET(0) |
6120                    GEN6_AGGRESSIVE_TURBO);
6121         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6122                    GEN6_FREQUENCY(12));
6123
6124         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6125         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6126                    18 << 24 |
6127                    6 << 16);
6128         I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6129         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6130         I915_WRITE(GEN6_RP_UP_EI, 100000);
6131         I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6132         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6133         I915_WRITE(GEN6_RP_CONTROL,
6134                    GEN6_RP_MEDIA_TURBO |
6135                    GEN6_RP_USE_NORMAL_FREQ |
6136                    GEN6_RP_MEDIA_IS_GFX |
6137                    GEN6_RP_ENABLE |
6138                    GEN6_RP_UP_BUSY_MAX |
6139                    GEN6_RP_DOWN_BUSY_MIN);
6140
6141         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6142                      500))
6143                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6144
6145         I915_WRITE(GEN6_PCODE_DATA, 0);
6146         I915_WRITE(GEN6_PCODE_MAILBOX,
6147                    GEN6_PCODE_READY |
6148                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6149         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6150                      500))
6151                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6152
6153         /* requires MSI enabled */
6154         I915_WRITE(GEN6_PMIER,
6155                    GEN6_PM_MBOX_EVENT |
6156                    GEN6_PM_THERMAL_EVENT |
6157                    GEN6_PM_RP_DOWN_TIMEOUT |
6158                    GEN6_PM_RP_UP_THRESHOLD |
6159                    GEN6_PM_RP_DOWN_THRESHOLD |
6160                    GEN6_PM_RP_UP_EI_EXPIRED |
6161                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6162
6163         __gen6_force_wake_put(dev_priv);
6164 }
6165
6166 void intel_enable_clock_gating(struct drm_device *dev)
6167 {
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169
6170         /*
6171          * Disable clock gating reported to work incorrectly according to the
6172          * specs, but enable as much else as we can.
6173          */
6174         if (HAS_PCH_SPLIT(dev)) {
6175                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6176
6177                 if (IS_GEN5(dev)) {
6178                         /* Required for FBC */
6179                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
6180                         /* Required for CxSR */
6181                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6182
6183                         I915_WRITE(PCH_3DCGDIS0,
6184                                    MARIUNIT_CLOCK_GATE_DISABLE |
6185                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6186                 }
6187
6188                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6189
6190                 /*
6191                  * On Ibex Peak and Cougar Point, we need to disable clock
6192                  * gating for the panel power sequencer or it will fail to
6193                  * start up when no ports are active.
6194                  */
6195                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6196
6197                 /*
6198                  * According to the spec the following bits should be set in
6199                  * order to enable memory self-refresh
6200                  * The bit 22/21 of 0x42004
6201                  * The bit 5 of 0x42020
6202                  * The bit 15 of 0x45000
6203                  */
6204                 if (IS_GEN5(dev)) {
6205                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6206                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
6207                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6208                         I915_WRITE(ILK_DSPCLK_GATE,
6209                                         (I915_READ(ILK_DSPCLK_GATE) |
6210                                                 ILK_DPARB_CLK_GATE));
6211                         I915_WRITE(DISP_ARB_CTL,
6212                                         (I915_READ(DISP_ARB_CTL) |
6213                                                 DISP_FBC_WM_DIS));
6214                         I915_WRITE(WM3_LP_ILK, 0);
6215                         I915_WRITE(WM2_LP_ILK, 0);
6216                         I915_WRITE(WM1_LP_ILK, 0);
6217                 }
6218                 /*
6219                  * Based on the document from hardware guys the following bits
6220                  * should be set unconditionally in order to enable FBC.
6221                  * The bit 22 of 0x42000
6222                  * The bit 22 of 0x42004
6223                  * The bit 7,8,9 of 0x42020.
6224                  */
6225                 if (IS_IRONLAKE_M(dev)) {
6226                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6227                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6228                                    ILK_FBCQ_DIS);
6229                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6230                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6231                                    ILK_DPARB_GATE);
6232                         I915_WRITE(ILK_DSPCLK_GATE,
6233                                    I915_READ(ILK_DSPCLK_GATE) |
6234                                    ILK_DPFC_DIS1 |
6235                                    ILK_DPFC_DIS2 |
6236                                    ILK_CLK_FBC);
6237                 }
6238
6239                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6240                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6241                            ILK_ELPIN_409_SELECT);
6242
6243                 if (IS_GEN5(dev)) {
6244                         I915_WRITE(_3D_CHICKEN2,
6245                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6246                                    _3D_CHICKEN2_WM_READ_PIPELINED);
6247                 }
6248
6249                 if (IS_GEN6(dev)) {
6250                         I915_WRITE(WM3_LP_ILK, 0);
6251                         I915_WRITE(WM2_LP_ILK, 0);
6252                         I915_WRITE(WM1_LP_ILK, 0);
6253
6254                         /*
6255                          * According to the spec the following bits should be
6256                          * set in order to enable memory self-refresh and fbc:
6257                          * The bit21 and bit22 of 0x42000
6258                          * The bit21 and bit22 of 0x42004
6259                          * The bit5 and bit7 of 0x42020
6260                          * The bit14 of 0x70180
6261                          * The bit14 of 0x71180
6262                          */
6263                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6264                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6265                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6266                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6267                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6268                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6269                         I915_WRITE(ILK_DSPCLK_GATE,
6270                                    I915_READ(ILK_DSPCLK_GATE) |
6271                                    ILK_DPARB_CLK_GATE  |
6272                                    ILK_DPFD_CLK_GATE);
6273
6274                         I915_WRITE(DSPACNTR,
6275                                    I915_READ(DSPACNTR) |
6276                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6277                         I915_WRITE(DSPBCNTR,
6278                                    I915_READ(DSPBCNTR) |
6279                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6280                 }
6281         } else if (IS_G4X(dev)) {
6282                 uint32_t dspclk_gate;
6283                 I915_WRITE(RENCLK_GATE_D1, 0);
6284                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6285                        GS_UNIT_CLOCK_GATE_DISABLE |
6286                        CL_UNIT_CLOCK_GATE_DISABLE);
6287                 I915_WRITE(RAMCLK_GATE_D, 0);
6288                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6289                         OVRUNIT_CLOCK_GATE_DISABLE |
6290                         OVCUNIT_CLOCK_GATE_DISABLE;
6291                 if (IS_GM45(dev))
6292                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6293                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6294         } else if (IS_CRESTLINE(dev)) {
6295                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6296                 I915_WRITE(RENCLK_GATE_D2, 0);
6297                 I915_WRITE(DSPCLK_GATE_D, 0);
6298                 I915_WRITE(RAMCLK_GATE_D, 0);
6299                 I915_WRITE16(DEUC, 0);
6300         } else if (IS_BROADWATER(dev)) {
6301                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6302                        I965_RCC_CLOCK_GATE_DISABLE |
6303                        I965_RCPB_CLOCK_GATE_DISABLE |
6304                        I965_ISC_CLOCK_GATE_DISABLE |
6305                        I965_FBC_CLOCK_GATE_DISABLE);
6306                 I915_WRITE(RENCLK_GATE_D2, 0);
6307         } else if (IS_GEN3(dev)) {
6308                 u32 dstate = I915_READ(D_STATE);
6309
6310                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6311                         DSTATE_DOT_CLOCK_GATING;
6312                 I915_WRITE(D_STATE, dstate);
6313         } else if (IS_I85X(dev) || IS_I865G(dev)) {
6314                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6315         } else if (IS_I830(dev)) {
6316                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6317         }
6318
6319         /*
6320          * GPU can automatically power down the render unit if given a page
6321          * to save state.
6322          */
6323         if (IS_IRONLAKE_M(dev) && 0) { /* XXX causes a failure during suspend */
6324                 if (dev_priv->renderctx == NULL)
6325                         dev_priv->renderctx = intel_alloc_context_page(dev);
6326                 if (dev_priv->renderctx) {
6327                         struct drm_i915_gem_object *obj = dev_priv->renderctx;
6328                         if (BEGIN_LP_RING(4) == 0) {
6329                                 OUT_RING(MI_SET_CONTEXT);
6330                                 OUT_RING(obj->gtt_offset |
6331                                          MI_MM_SPACE_GTT |
6332                                          MI_SAVE_EXT_STATE_EN |
6333                                          MI_RESTORE_EXT_STATE_EN |
6334                                          MI_RESTORE_INHIBIT);
6335                                 OUT_RING(MI_NOOP);
6336                                 OUT_RING(MI_FLUSH);
6337                                 ADVANCE_LP_RING();
6338                         }
6339                 } else
6340                         DRM_DEBUG_KMS("Failed to allocate render context."
6341                                        "Disable RC6\n");
6342         }
6343
6344         if (IS_GEN4(dev) && IS_MOBILE(dev)) {
6345                 if (dev_priv->pwrctx == NULL)
6346                         dev_priv->pwrctx = intel_alloc_context_page(dev);
6347                 if (dev_priv->pwrctx) {
6348                         struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6349                         I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
6350                         I915_WRITE(MCHBAR_RENDER_STANDBY,
6351                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
6352                 }
6353         }
6354
6355         if (IS_GEN6(dev))
6356                 gen6_enable_rc6(dev_priv);
6357 }
6358
6359 void intel_disable_clock_gating(struct drm_device *dev)
6360 {
6361         struct drm_i915_private *dev_priv = dev->dev_private;
6362
6363         if (dev_priv->renderctx) {
6364                 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6365
6366                 I915_WRITE(CCID, 0);
6367                 POSTING_READ(CCID);
6368
6369                 i915_gem_object_unpin(obj);
6370                 drm_gem_object_unreference(&obj->base);
6371                 dev_priv->renderctx = NULL;
6372         }
6373
6374         if (dev_priv->pwrctx) {
6375                 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6376
6377                 I915_WRITE(PWRCTXA, 0);
6378                 POSTING_READ(PWRCTXA);
6379
6380                 i915_gem_object_unpin(obj);
6381                 drm_gem_object_unreference(&obj->base);
6382                 dev_priv->pwrctx = NULL;
6383         }
6384 }
6385
6386 /* Set up chip specific display functions */
6387 static void intel_init_display(struct drm_device *dev)
6388 {
6389         struct drm_i915_private *dev_priv = dev->dev_private;
6390
6391         /* We always want a DPMS function */
6392         if (HAS_PCH_SPLIT(dev))
6393                 dev_priv->display.dpms = ironlake_crtc_dpms;
6394         else
6395                 dev_priv->display.dpms = i9xx_crtc_dpms;
6396
6397         if (I915_HAS_FBC(dev)) {
6398                 if (IS_IRONLAKE_M(dev)) {
6399                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6400                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6401                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6402                 } else if (IS_GM45(dev)) {
6403                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6404                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6405                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6406                 } else if (IS_CRESTLINE(dev)) {
6407                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6408                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6409                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6410                 }
6411                 /* 855GM needs testing */
6412         }
6413
6414         /* Returns the core display clock speed */
6415         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6416                 dev_priv->display.get_display_clock_speed =
6417                         i945_get_display_clock_speed;
6418         else if (IS_I915G(dev))
6419                 dev_priv->display.get_display_clock_speed =
6420                         i915_get_display_clock_speed;
6421         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6422                 dev_priv->display.get_display_clock_speed =
6423                         i9xx_misc_get_display_clock_speed;
6424         else if (IS_I915GM(dev))
6425                 dev_priv->display.get_display_clock_speed =
6426                         i915gm_get_display_clock_speed;
6427         else if (IS_I865G(dev))
6428                 dev_priv->display.get_display_clock_speed =
6429                         i865_get_display_clock_speed;
6430         else if (IS_I85X(dev))
6431                 dev_priv->display.get_display_clock_speed =
6432                         i855_get_display_clock_speed;
6433         else /* 852, 830 */
6434                 dev_priv->display.get_display_clock_speed =
6435                         i830_get_display_clock_speed;
6436
6437         /* For FIFO watermark updates */
6438         if (HAS_PCH_SPLIT(dev)) {
6439                 if (IS_GEN5(dev)) {
6440                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6441                                 dev_priv->display.update_wm = ironlake_update_wm;
6442                         else {
6443                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6444                                               "Disable CxSR\n");
6445                                 dev_priv->display.update_wm = NULL;
6446                         }
6447                 } else if (IS_GEN6(dev)) {
6448                         if (SNB_READ_WM0_LATENCY()) {
6449                                 dev_priv->display.update_wm = sandybridge_update_wm;
6450                         } else {
6451                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6452                                               "Disable CxSR\n");
6453                                 dev_priv->display.update_wm = NULL;
6454                         }
6455                 } else
6456                         dev_priv->display.update_wm = NULL;
6457         } else if (IS_PINEVIEW(dev)) {
6458                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6459                                             dev_priv->is_ddr3,
6460                                             dev_priv->fsb_freq,
6461                                             dev_priv->mem_freq)) {
6462                         DRM_INFO("failed to find known CxSR latency "
6463                                  "(found ddr%s fsb freq %d, mem freq %d), "
6464                                  "disabling CxSR\n",
6465                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6466                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6467                         /* Disable CxSR and never update its watermark again */
6468                         pineview_disable_cxsr(dev);
6469                         dev_priv->display.update_wm = NULL;
6470                 } else
6471                         dev_priv->display.update_wm = pineview_update_wm;
6472         } else if (IS_G4X(dev))
6473                 dev_priv->display.update_wm = g4x_update_wm;
6474         else if (IS_GEN4(dev))
6475                 dev_priv->display.update_wm = i965_update_wm;
6476         else if (IS_GEN3(dev)) {
6477                 dev_priv->display.update_wm = i9xx_update_wm;
6478                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6479         } else if (IS_I85X(dev)) {
6480                 dev_priv->display.update_wm = i9xx_update_wm;
6481                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6482         } else {
6483                 dev_priv->display.update_wm = i830_update_wm;
6484                 if (IS_845G(dev))
6485                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6486                 else
6487                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6488         }
6489 }
6490
6491 /*
6492  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6493  * resume, or other times.  This quirk makes sure that's the case for
6494  * affected systems.
6495  */
6496 static void quirk_pipea_force (struct drm_device *dev)
6497 {
6498         struct drm_i915_private *dev_priv = dev->dev_private;
6499
6500         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6501         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6502 }
6503
6504 struct intel_quirk {
6505         int device;
6506         int subsystem_vendor;
6507         int subsystem_device;
6508         void (*hook)(struct drm_device *dev);
6509 };
6510
6511 struct intel_quirk intel_quirks[] = {
6512         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6513         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6514         /* HP Mini needs pipe A force quirk (LP: #322104) */
6515         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6516
6517         /* Thinkpad R31 needs pipe A force quirk */
6518         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6519         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6520         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6521
6522         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6523         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6524         /* ThinkPad X40 needs pipe A force quirk */
6525
6526         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6527         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6528
6529         /* 855 & before need to leave pipe A & dpll A up */
6530         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6531         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6532 };
6533
6534 static void intel_init_quirks(struct drm_device *dev)
6535 {
6536         struct pci_dev *d = dev->pdev;
6537         int i;
6538
6539         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6540                 struct intel_quirk *q = &intel_quirks[i];
6541
6542                 if (d->device == q->device &&
6543                     (d->subsystem_vendor == q->subsystem_vendor ||
6544                      q->subsystem_vendor == PCI_ANY_ID) &&
6545                     (d->subsystem_device == q->subsystem_device ||
6546                      q->subsystem_device == PCI_ANY_ID))
6547                         q->hook(dev);
6548         }
6549 }
6550
6551 /* Disable the VGA plane that we never use */
6552 static void i915_disable_vga(struct drm_device *dev)
6553 {
6554         struct drm_i915_private *dev_priv = dev->dev_private;
6555         u8 sr1;
6556         u32 vga_reg;
6557
6558         if (HAS_PCH_SPLIT(dev))
6559                 vga_reg = CPU_VGACNTRL;
6560         else
6561                 vga_reg = VGACNTRL;
6562
6563         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6564         outb(1, VGA_SR_INDEX);
6565         sr1 = inb(VGA_SR_DATA);
6566         outb(sr1 | 1<<5, VGA_SR_DATA);
6567         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6568         udelay(300);
6569
6570         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6571         POSTING_READ(vga_reg);
6572 }
6573
6574 void intel_modeset_init(struct drm_device *dev)
6575 {
6576         struct drm_i915_private *dev_priv = dev->dev_private;
6577         int i;
6578
6579         drm_mode_config_init(dev);
6580
6581         dev->mode_config.min_width = 0;
6582         dev->mode_config.min_height = 0;
6583
6584         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6585
6586         intel_init_quirks(dev);
6587
6588         intel_init_display(dev);
6589
6590         if (IS_GEN2(dev)) {
6591                 dev->mode_config.max_width = 2048;
6592                 dev->mode_config.max_height = 2048;
6593         } else if (IS_GEN3(dev)) {
6594                 dev->mode_config.max_width = 4096;
6595                 dev->mode_config.max_height = 4096;
6596         } else {
6597                 dev->mode_config.max_width = 8192;
6598                 dev->mode_config.max_height = 8192;
6599         }
6600
6601         /* set memory base */
6602         if (IS_GEN2(dev))
6603                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6604         else
6605                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6606
6607         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6608                 dev_priv->num_pipe = 2;
6609         else
6610                 dev_priv->num_pipe = 1;
6611         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6612                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6613
6614         for (i = 0; i < dev_priv->num_pipe; i++) {
6615                 intel_crtc_init(dev, i);
6616         }
6617
6618         intel_setup_outputs(dev);
6619
6620         intel_enable_clock_gating(dev);
6621
6622         /* Just disable it once at startup */
6623         i915_disable_vga(dev);
6624
6625         if (IS_IRONLAKE_M(dev)) {
6626                 ironlake_enable_drps(dev);
6627                 intel_init_emon(dev);
6628         }
6629
6630         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6631         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6632                     (unsigned long)dev);
6633
6634         intel_setup_overlay(dev);
6635 }
6636
6637 void intel_modeset_cleanup(struct drm_device *dev)
6638 {
6639         struct drm_i915_private *dev_priv = dev->dev_private;
6640         struct drm_crtc *crtc;
6641         struct intel_crtc *intel_crtc;
6642
6643         drm_kms_helper_poll_fini(dev);
6644         mutex_lock(&dev->struct_mutex);
6645
6646         intel_unregister_dsm_handler();
6647
6648
6649         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6650                 /* Skip inactive CRTCs */
6651                 if (!crtc->fb)
6652                         continue;
6653
6654                 intel_crtc = to_intel_crtc(crtc);
6655                 intel_increase_pllclock(crtc);
6656         }
6657
6658         if (dev_priv->display.disable_fbc)
6659                 dev_priv->display.disable_fbc(dev);
6660
6661         if (IS_IRONLAKE_M(dev))
6662                 ironlake_disable_drps(dev);
6663
6664         intel_disable_clock_gating(dev);
6665
6666         mutex_unlock(&dev->struct_mutex);
6667
6668         /* Disable the irq before mode object teardown, for the irq might
6669          * enqueue unpin/hotplug work. */
6670         drm_irq_uninstall(dev);
6671         cancel_work_sync(&dev_priv->hotplug_work);
6672
6673         /* Shut off idle work before the crtcs get freed. */
6674         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6675                 intel_crtc = to_intel_crtc(crtc);
6676                 del_timer_sync(&intel_crtc->idle_timer);
6677         }
6678         del_timer_sync(&dev_priv->idle_timer);
6679         cancel_work_sync(&dev_priv->idle_work);
6680
6681         drm_mode_config_cleanup(dev);
6682 }
6683
6684 /*
6685  * Return which encoder is currently attached for connector.
6686  */
6687 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6688 {
6689         return &intel_attached_encoder(connector)->base;
6690 }
6691
6692 void intel_connector_attach_encoder(struct intel_connector *connector,
6693                                     struct intel_encoder *encoder)
6694 {
6695         connector->encoder = encoder;
6696         drm_mode_connector_attach_encoder(&connector->base,
6697                                           &encoder->base);
6698 }
6699
6700 /*
6701  * set vga decode state - true == enable VGA decode
6702  */
6703 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6704 {
6705         struct drm_i915_private *dev_priv = dev->dev_private;
6706         u16 gmch_ctrl;
6707
6708         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6709         if (state)
6710                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6711         else
6712                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6713         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6714         return 0;
6715 }
6716
6717 #ifdef CONFIG_DEBUG_FS
6718 #include <linux/seq_file.h>
6719
6720 struct intel_display_error_state {
6721         struct intel_cursor_error_state {
6722                 u32 control;
6723                 u32 position;
6724                 u32 base;
6725                 u32 size;
6726         } cursor[2];
6727
6728         struct intel_pipe_error_state {
6729                 u32 conf;
6730                 u32 source;
6731
6732                 u32 htotal;
6733                 u32 hblank;
6734                 u32 hsync;
6735                 u32 vtotal;
6736                 u32 vblank;
6737                 u32 vsync;
6738         } pipe[2];
6739
6740         struct intel_plane_error_state {
6741                 u32 control;
6742                 u32 stride;
6743                 u32 size;
6744                 u32 pos;
6745                 u32 addr;
6746                 u32 surface;
6747                 u32 tile_offset;
6748         } plane[2];
6749 };
6750
6751 struct intel_display_error_state *
6752 intel_display_capture_error_state(struct drm_device *dev)
6753 {
6754         drm_i915_private_t *dev_priv = dev->dev_private;
6755         struct intel_display_error_state *error;
6756         int i;
6757
6758         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6759         if (error == NULL)
6760                 return NULL;
6761
6762         for (i = 0; i < 2; i++) {
6763                 error->cursor[i].control = I915_READ(CURCNTR(i));
6764                 error->cursor[i].position = I915_READ(CURPOS(i));
6765                 error->cursor[i].base = I915_READ(CURBASE(i));
6766
6767                 error->plane[i].control = I915_READ(DSPCNTR(i));
6768                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6769                 error->plane[i].size = I915_READ(DSPSIZE(i));
6770                 error->plane[i].pos= I915_READ(DSPPOS(i));
6771                 error->plane[i].addr = I915_READ(DSPADDR(i));
6772                 if (INTEL_INFO(dev)->gen >= 4) {
6773                         error->plane[i].surface = I915_READ(DSPSURF(i));
6774                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6775                 }
6776
6777                 error->pipe[i].conf = I915_READ(PIPECONF(i));
6778                 error->pipe[i].source = I915_READ(PIPESRC(i));
6779                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6780                 error->pipe[i].hblank = I915_READ(HBLANK(i));
6781                 error->pipe[i].hsync = I915_READ(HSYNC(i));
6782                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6783                 error->pipe[i].vblank = I915_READ(VBLANK(i));
6784                 error->pipe[i].vsync = I915_READ(VSYNC(i));
6785         }
6786
6787         return error;
6788 }
6789
6790 void
6791 intel_display_print_error_state(struct seq_file *m,
6792                                 struct drm_device *dev,
6793                                 struct intel_display_error_state *error)
6794 {
6795         int i;
6796
6797         for (i = 0; i < 2; i++) {
6798                 seq_printf(m, "Pipe [%d]:\n", i);
6799                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
6800                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
6801                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
6802                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
6803                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
6804                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
6805                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
6806                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
6807
6808                 seq_printf(m, "Plane [%d]:\n", i);
6809                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
6810                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
6811                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
6812                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
6813                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
6814                 if (INTEL_INFO(dev)->gen >= 4) {
6815                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
6816                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
6817                 }
6818
6819                 seq_printf(m, "Cursor [%d]:\n", i);
6820                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
6821                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
6822                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
6823         }
6824 }
6825 #endif