2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
8 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
20 #include <linux/config.h>
22 #include <asm/asmmacro.h>
24 #include <asm/kregs.h>
25 #include <asm/mmu_context.h>
26 #include <asm/offsets.h>
28 #include <asm/pgtable.h>
29 #include <asm/processor.h>
30 #include <asm/ptrace.h>
31 #include <asm/system.h>
33 .section __special_page_section,"ax"
35 .global empty_zero_page
39 .global swapper_pg_dir
45 stringz "Halting kernel\n"
52 * Start the kernel. When the bootloader passes control to _start(), r28
53 * points to the address of the boot parameter area. Execution reaches
54 * here in physical mode.
59 .save rp, r4 // terminate unwind chain with a NULL rp
64 * Initialize the region register for region 7 and install a translation register
65 * that maps the kernel's text and data:
68 mov r16=((ia64_rid(IA64_REGION_ID_KERNEL, PAGE_OFFSET) << 8) | (IA64_GRANULE_SHIFT << 2))
71 mov r18=KERNEL_TR_PAGE_SHIFT<<2
77 mov r16=IA64_TR_KERNEL
78 movl r18=((1 << KERNEL_TR_PAGE_SHIFT) | PAGE_KERNEL)
89 * Switch into virtual mode:
91 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
102 1: // now we are in virtual mode
104 // set IVT entry point---can't access I/O ports without it
116 #ifdef CONFIG_IA64_EARLY_PRINTK
117 mov r3=(6<<8) | (IA64_GRANULE_SHIFT<<2)
126 #define isAP p2 // are we an Application Processor?
127 #define isBP p3 // are we the Bootstrap Processor?
131 * Find the init_task for the currently booting CPU. At poweron, and in
132 * UP mode, task_for_booting_cpu is NULL.
134 movl r3=task_for_booting_cpu
137 movl r2=init_thread_union
139 cmp.eq isBP,isAP=r3,r0
143 movl r2=init_thread_union
144 cmp.eq isBP,isAP=r0,r0
146 mov r16=KERNEL_TR_PAGE_NUM
149 // load the "current" pointer (r13) and ar.k6 with the current task
150 mov IA64_KR(CURRENT)=r2 // virtual address
151 // initialize k4 to a safe value (64-128MB is mapped by TR_KERNEL)
152 mov IA64_KR(CURRENT_STACK)=r16
155 * Reserve space at the top of the stack for "struct pt_regs". Kernel threads
156 * don't store interesting values in that structure, but the space still needs
157 * to be there because time-critical stuff such as the context switching can
158 * be implemented more efficiently (for example, __switch_to()
159 * always sets the psr.dfh bit of the task it is switching to).
161 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
162 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
163 mov ar.rsc=0 // place RSE in enforced lazy mode
165 loadrs // clear the dirty partition
167 mov ar.bspstore=r2 // establish the new RSE stack
169 mov ar.rsc=0x3 // place RSE in eager mode
171 (isBP) dep r28=-1,r28,61,3 // make address virtual
172 (isBP) movl r2=ia64_boot_param
174 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
176 #ifdef CONFIG_IA64_EARLY_PRINTK
179 stringz "I'm alive and well\n"
183 alloc r2=ar.pfs,0,0,2,0
185 movl out1=alive_msg_end-alive_msg-1
187 br.call.sptk.many rp=early_printk
188 1: // force new bundle
189 #endif /* CONFIG_IA64_EARLY_PRINTK */
192 (isAP) br.call.sptk.many rp=start_secondary
194 (isAP) br.cond.sptk self
197 // This is executed by the bootstrap processor (bsp) only:
199 #ifdef CONFIG_IA64_FW_EMU
200 // initialize PAL & SAL emulator:
201 br.call.sptk.many rp=sys_fw_init
204 br.call.sptk.many rp=start_kernel
205 .ret2: addl r3=@ltoff(halt_msg),gp
207 alloc r2=ar.pfs,8,0,2,0
210 br.call.sptk.many b0=console_print
211 self: br.sptk.many self // endless loop
214 GLOBAL_ENTRY(ia64_save_debug_regs)
215 alloc r16=ar.pfs,1,0,0,0
216 mov r20=ar.lc // preserve ar.lc
217 mov ar.lc=IA64_NUM_DBG_REGS-1
219 add r19=IA64_NUM_DBG_REGS*8,in0
222 #ifdef CONFIG_ITANIUM
231 br.cloop.sptk.many 1b
233 mov ar.lc=r20 // restore ar.lc
235 END(ia64_save_debug_regs)
237 GLOBAL_ENTRY(ia64_load_debug_regs)
238 alloc r16=ar.pfs,1,0,0,0
240 mov r20=ar.lc // preserve ar.lc
241 add r19=IA64_NUM_DBG_REGS*8,in0
242 mov ar.lc=IA64_NUM_DBG_REGS-1
245 1: ld8.nta r16=[in0],8
250 #ifdef CONFIG_ITANIUM
252 srlz.d // Errata 132 (NoFix status)
255 br.cloop.sptk.many 1b
257 mov ar.lc=r20 // restore ar.lc
259 END(ia64_load_debug_regs)
261 GLOBAL_ENTRY(__ia64_save_fpu)
262 alloc r2=ar.pfs,1,4,0,0
263 adds loc0=96*16-16,in0
264 adds loc1=96*16-16-128,in0
266 stf.spill.nta [loc0]=f127,-256
267 stf.spill.nta [loc1]=f119,-256
269 stf.spill.nta [loc0]=f111,-256
270 stf.spill.nta [loc1]=f103,-256
272 stf.spill.nta [loc0]=f95,-256
273 stf.spill.nta [loc1]=f87,-256
275 stf.spill.nta [loc0]=f79,-256
276 stf.spill.nta [loc1]=f71,-256
278 stf.spill.nta [loc0]=f63,-256
279 stf.spill.nta [loc1]=f55,-256
280 adds loc2=96*16-32,in0
282 stf.spill.nta [loc0]=f47,-256
283 stf.spill.nta [loc1]=f39,-256
284 adds loc3=96*16-32-128,in0
286 stf.spill.nta [loc2]=f126,-256
287 stf.spill.nta [loc3]=f118,-256
289 stf.spill.nta [loc2]=f110,-256
290 stf.spill.nta [loc3]=f102,-256
292 stf.spill.nta [loc2]=f94,-256
293 stf.spill.nta [loc3]=f86,-256
295 stf.spill.nta [loc2]=f78,-256
296 stf.spill.nta [loc3]=f70,-256
298 stf.spill.nta [loc2]=f62,-256
299 stf.spill.nta [loc3]=f54,-256
300 adds loc0=96*16-48,in0
302 stf.spill.nta [loc2]=f46,-256
303 stf.spill.nta [loc3]=f38,-256
304 adds loc1=96*16-48-128,in0
306 stf.spill.nta [loc0]=f125,-256
307 stf.spill.nta [loc1]=f117,-256
309 stf.spill.nta [loc0]=f109,-256
310 stf.spill.nta [loc1]=f101,-256
312 stf.spill.nta [loc0]=f93,-256
313 stf.spill.nta [loc1]=f85,-256
315 stf.spill.nta [loc0]=f77,-256
316 stf.spill.nta [loc1]=f69,-256
318 stf.spill.nta [loc0]=f61,-256
319 stf.spill.nta [loc1]=f53,-256
320 adds loc2=96*16-64,in0
322 stf.spill.nta [loc0]=f45,-256
323 stf.spill.nta [loc1]=f37,-256
324 adds loc3=96*16-64-128,in0
326 stf.spill.nta [loc2]=f124,-256
327 stf.spill.nta [loc3]=f116,-256
329 stf.spill.nta [loc2]=f108,-256
330 stf.spill.nta [loc3]=f100,-256
332 stf.spill.nta [loc2]=f92,-256
333 stf.spill.nta [loc3]=f84,-256
335 stf.spill.nta [loc2]=f76,-256
336 stf.spill.nta [loc3]=f68,-256
338 stf.spill.nta [loc2]=f60,-256
339 stf.spill.nta [loc3]=f52,-256
340 adds loc0=96*16-80,in0
342 stf.spill.nta [loc2]=f44,-256
343 stf.spill.nta [loc3]=f36,-256
344 adds loc1=96*16-80-128,in0
346 stf.spill.nta [loc0]=f123,-256
347 stf.spill.nta [loc1]=f115,-256
349 stf.spill.nta [loc0]=f107,-256
350 stf.spill.nta [loc1]=f99,-256
352 stf.spill.nta [loc0]=f91,-256
353 stf.spill.nta [loc1]=f83,-256
355 stf.spill.nta [loc0]=f75,-256
356 stf.spill.nta [loc1]=f67,-256
358 stf.spill.nta [loc0]=f59,-256
359 stf.spill.nta [loc1]=f51,-256
360 adds loc2=96*16-96,in0
362 stf.spill.nta [loc0]=f43,-256
363 stf.spill.nta [loc1]=f35,-256
364 adds loc3=96*16-96-128,in0
366 stf.spill.nta [loc2]=f122,-256
367 stf.spill.nta [loc3]=f114,-256
369 stf.spill.nta [loc2]=f106,-256
370 stf.spill.nta [loc3]=f98,-256
372 stf.spill.nta [loc2]=f90,-256
373 stf.spill.nta [loc3]=f82,-256
375 stf.spill.nta [loc2]=f74,-256
376 stf.spill.nta [loc3]=f66,-256
378 stf.spill.nta [loc2]=f58,-256
379 stf.spill.nta [loc3]=f50,-256
380 adds loc0=96*16-112,in0
382 stf.spill.nta [loc2]=f42,-256
383 stf.spill.nta [loc3]=f34,-256
384 adds loc1=96*16-112-128,in0
386 stf.spill.nta [loc0]=f121,-256
387 stf.spill.nta [loc1]=f113,-256
389 stf.spill.nta [loc0]=f105,-256
390 stf.spill.nta [loc1]=f97,-256
392 stf.spill.nta [loc0]=f89,-256
393 stf.spill.nta [loc1]=f81,-256
395 stf.spill.nta [loc0]=f73,-256
396 stf.spill.nta [loc1]=f65,-256
398 stf.spill.nta [loc0]=f57,-256
399 stf.spill.nta [loc1]=f49,-256
400 adds loc2=96*16-128,in0
402 stf.spill.nta [loc0]=f41,-256
403 stf.spill.nta [loc1]=f33,-256
404 adds loc3=96*16-128-128,in0
406 stf.spill.nta [loc2]=f120,-256
407 stf.spill.nta [loc3]=f112,-256
409 stf.spill.nta [loc2]=f104,-256
410 stf.spill.nta [loc3]=f96,-256
412 stf.spill.nta [loc2]=f88,-256
413 stf.spill.nta [loc3]=f80,-256
415 stf.spill.nta [loc2]=f72,-256
416 stf.spill.nta [loc3]=f64,-256
418 stf.spill.nta [loc2]=f56,-256
419 stf.spill.nta [loc3]=f48,-256
421 stf.spill.nta [loc2]=f40
422 stf.spill.nta [loc3]=f32
426 GLOBAL_ENTRY(__ia64_load_fpu)
427 alloc r2=ar.pfs,1,2,0,0
434 ldf.fill.nta f32=[in0],loc0
435 ldf.fill.nta f40=[ r3],loc0
436 ldf.fill.nta f48=[r14],loc0
437 ldf.fill.nta f56=[r15],loc0
439 ldf.fill.nta f64=[in0],loc0
440 ldf.fill.nta f72=[ r3],loc0
441 ldf.fill.nta f80=[r14],loc0
442 ldf.fill.nta f88=[r15],loc0
444 ldf.fill.nta f96=[in0],loc1
445 ldf.fill.nta f104=[ r3],loc1
446 ldf.fill.nta f112=[r14],loc1
447 ldf.fill.nta f120=[r15],loc1
449 ldf.fill.nta f33=[in0],loc0
450 ldf.fill.nta f41=[ r3],loc0
451 ldf.fill.nta f49=[r14],loc0
452 ldf.fill.nta f57=[r15],loc0
454 ldf.fill.nta f65=[in0],loc0
455 ldf.fill.nta f73=[ r3],loc0
456 ldf.fill.nta f81=[r14],loc0
457 ldf.fill.nta f89=[r15],loc0
459 ldf.fill.nta f97=[in0],loc1
460 ldf.fill.nta f105=[ r3],loc1
461 ldf.fill.nta f113=[r14],loc1
462 ldf.fill.nta f121=[r15],loc1
464 ldf.fill.nta f34=[in0],loc0
465 ldf.fill.nta f42=[ r3],loc0
466 ldf.fill.nta f50=[r14],loc0
467 ldf.fill.nta f58=[r15],loc0
469 ldf.fill.nta f66=[in0],loc0
470 ldf.fill.nta f74=[ r3],loc0
471 ldf.fill.nta f82=[r14],loc0
472 ldf.fill.nta f90=[r15],loc0
474 ldf.fill.nta f98=[in0],loc1
475 ldf.fill.nta f106=[ r3],loc1
476 ldf.fill.nta f114=[r14],loc1
477 ldf.fill.nta f122=[r15],loc1
479 ldf.fill.nta f35=[in0],loc0
480 ldf.fill.nta f43=[ r3],loc0
481 ldf.fill.nta f51=[r14],loc0
482 ldf.fill.nta f59=[r15],loc0
484 ldf.fill.nta f67=[in0],loc0
485 ldf.fill.nta f75=[ r3],loc0
486 ldf.fill.nta f83=[r14],loc0
487 ldf.fill.nta f91=[r15],loc0
489 ldf.fill.nta f99=[in0],loc1
490 ldf.fill.nta f107=[ r3],loc1
491 ldf.fill.nta f115=[r14],loc1
492 ldf.fill.nta f123=[r15],loc1
494 ldf.fill.nta f36=[in0],loc0
495 ldf.fill.nta f44=[ r3],loc0
496 ldf.fill.nta f52=[r14],loc0
497 ldf.fill.nta f60=[r15],loc0
499 ldf.fill.nta f68=[in0],loc0
500 ldf.fill.nta f76=[ r3],loc0
501 ldf.fill.nta f84=[r14],loc0
502 ldf.fill.nta f92=[r15],loc0
504 ldf.fill.nta f100=[in0],loc1
505 ldf.fill.nta f108=[ r3],loc1
506 ldf.fill.nta f116=[r14],loc1
507 ldf.fill.nta f124=[r15],loc1
509 ldf.fill.nta f37=[in0],loc0
510 ldf.fill.nta f45=[ r3],loc0
511 ldf.fill.nta f53=[r14],loc0
512 ldf.fill.nta f61=[r15],loc0
514 ldf.fill.nta f69=[in0],loc0
515 ldf.fill.nta f77=[ r3],loc0
516 ldf.fill.nta f85=[r14],loc0
517 ldf.fill.nta f93=[r15],loc0
519 ldf.fill.nta f101=[in0],loc1
520 ldf.fill.nta f109=[ r3],loc1
521 ldf.fill.nta f117=[r14],loc1
522 ldf.fill.nta f125=[r15],loc1
524 ldf.fill.nta f38 =[in0],loc0
525 ldf.fill.nta f46 =[ r3],loc0
526 ldf.fill.nta f54 =[r14],loc0
527 ldf.fill.nta f62 =[r15],loc0
529 ldf.fill.nta f70 =[in0],loc0
530 ldf.fill.nta f78 =[ r3],loc0
531 ldf.fill.nta f86 =[r14],loc0
532 ldf.fill.nta f94 =[r15],loc0
534 ldf.fill.nta f102=[in0],loc1
535 ldf.fill.nta f110=[ r3],loc1
536 ldf.fill.nta f118=[r14],loc1
537 ldf.fill.nta f126=[r15],loc1
539 ldf.fill.nta f39 =[in0],loc0
540 ldf.fill.nta f47 =[ r3],loc0
541 ldf.fill.nta f55 =[r14],loc0
542 ldf.fill.nta f63 =[r15],loc0
544 ldf.fill.nta f71 =[in0],loc0
545 ldf.fill.nta f79 =[ r3],loc0
546 ldf.fill.nta f87 =[r14],loc0
547 ldf.fill.nta f95 =[r15],loc0
549 ldf.fill.nta f103=[in0]
550 ldf.fill.nta f111=[ r3]
551 ldf.fill.nta f119=[r14]
552 ldf.fill.nta f127=[r15]
556 GLOBAL_ENTRY(__ia64_init_fpu)
557 stf.spill [sp]=f0 // M3
561 ldfps f33,f34=[sp] // M0
562 ldfps f35,f36=[sp] // M1
570 ldfps f41,f42=[sp] // M0
571 ldfps f43,f44=[sp] // M1
578 ldfps f49,f50=[sp] // M0
579 ldfps f51,f52=[sp] // M1
586 ldfps f57,f58=[sp] // M0
587 ldfps f59,f60=[sp] // M1
594 ldfps f65,f66=[sp] // M0
595 ldfps f67,f68=[sp] // M1
602 ldfps f73,f74=[sp] // M0
603 ldfps f75,f76=[sp] // M1
610 ldfps f81,f82=[sp] // M0
611 ldfps f83,f84=[sp] // M1
619 * When the instructions are cached, it would be faster to initialize
620 * the remaining registers with simply mov instructions (F-unit).
621 * This gets the time down to ~29 cycles. However, this would use up
622 * 33 bundles, whereas continuing with the above pattern yields
623 * 10 bundles and ~30 cycles.
626 ldfps f89,f90=[sp] // M0
627 ldfps f91,f92=[sp] // M1
634 ldfps f97,f98=[sp] // M0
635 ldfps f99,f100=[sp] // M1
642 ldfps f105,f106=[sp] // M0
643 ldfps f107,f108=[sp] // M1
650 ldfps f113,f114=[sp] // M0
651 ldfps f115,f116=[sp] // M1
658 ldfps f121,f122=[sp] // M0
659 ldfps f123,f124=[sp] // M1
664 br.ret.sptk.many rp // F
668 * Switch execution mode from virtual to physical or vice versa.
671 * r16 = new psr to establish
673 * Note: RSE must already be in enforced lazy mode
675 GLOBAL_ENTRY(ia64_switch_mode)
677 alloc r2=ar.pfs,0,0,0,0
678 rsm psr.i | psr.ic // disable interrupts and interrupt collection
683 flushrs // must be first insn in group
685 shr.u r19=r15,61 // r19 <- top 3 bits of current IP
688 mov cr.ipsr=r16 // set new PSR
689 add r3=1f-ia64_switch_mode,r15
690 xor r15=0x7,r19 // flip the region bits
693 mov r14=rp // get return address into a general register
695 // switch RSE backing store:
697 dep r17=r15,r17,61,3 // make ar.bsp physical or virtual
698 mov r18=ar.rnat // save ar.rnat
700 mov ar.bspstore=r17 // this steps on ar.rnat
701 dep r3=r15,r3,61,3 // make rfi return address physical or virtual
705 dep sp=r15,sp,61,3 // make stack pointer physical or virtual
707 mov ar.rnat=r18 // restore ar.rnat
708 dep r14=r15,r14,61,3 // make function return address physical or virtual
709 rfi // must be last insn in group
713 END(ia64_switch_mode)
715 #ifdef CONFIG_IA64_BRL_EMU
718 * Assembly routines used by brl_emu.c to set preserved register state.
721 #define SET_REG(reg) \
722 GLOBAL_ENTRY(ia64_set_##reg); \
723 alloc r16=ar.pfs,1,0,0,0; \
726 br.ret.sptk.many rp; \
735 #endif /* CONFIG_IA64_BRL_EMU */
739 * This routine handles spinlock contention. It uses a non-standard calling
740 * convention to avoid converting leaf routines into interior routines. Because
741 * of this special convention, there are several restrictions:
743 * - do not use gp relative variables, this code is called from the kernel
744 * and from modules, r1 is undefined.
745 * - do not use stacked registers, the caller owns them.
746 * - do not use the scratch stack space, the caller owns it.
747 * - do not use any registers other than the ones listed below
750 * ar.pfs - saved CFM of caller
751 * ar.ccv - 0 (and available for use)
752 * r28 - available for use.
753 * r29 - available for use.
754 * r30 - available for use.
755 * r31 - address of lock, available for use.
756 * b7 - return address
757 * p14 - available for use.
759 * If you patch this code to use more registers, do not forget to update
760 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
763 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 4)
765 GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
767 .save ar.pfs, r0 // this code effectively has a zero frame size
772 .restore sp // pop existing prologue after next insn
779 // exponential backoff, kdb, lockmeter etc. go in here
784 cmp4.eq p14,p0=r30,r0
785 (p14) br.cond.sptk.few b6 // lock is now free, try to acquire
786 br.cond.sptk.few .wait
787 END(ia64_spinlock_contention_pre3_4)
791 GLOBAL_ENTRY(ia64_spinlock_contention)
796 // exponential backoff, kdb, lockmeter etc. go in here
800 cmp4.ne p14,p0=r30,r0
802 (p14) br.cond.sptk.few .wait
804 cmpxchg4.acq r30=[r31], r30, ar.ccv
806 cmp4.ne p14,p0=r0,r30
807 (p14) br.cond.sptk.few .wait
809 br.ret.sptk.many b6 // lock is now taken
810 END(ia64_spinlock_contention)
814 #endif /* CONFIG_SMP */