arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #ifdef  CONFIG_KDB
  31 #include <linux/kdb.h>
  32 #endif  /* CONFIG_KDB */
  33 #include <linux/smp_lock.h>
  34 #include <linux/mc146818rtc.h>
  35 #include <linux/compiler.h>
  36 #include <linux/acpi.h>
  37
  38 #include <linux/sysdev.h>
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/timer.h>
  43
  44 #include <mach_apic.h>
  45
  46 #include "io_ports.h"
  47
  48 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  49
  50 /*
  51  *      Is the SiS APIC rmw bug present ?
  52  *      -1 = don't know, 0 = no, 1 = yes
  53  */
  54 int sis_apic_bug = -1;
  55
  56 /*
  57  * # of IRQ routing registers
  58  */
  59 int nr_ioapic_registers[MAX_IO_APICS];
  60
  61 /*
  62  * Rough estimation of how many shared IRQs there are, can
  63  * be changed anytime.
  64  */
  65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  67
  68 /*
  69  * This is performance-critical, we want to do it O(1)
  70  *
  71  * the indexing order of this array favors 1:1 mappings
  72  * between pins and IRQs.
  73  */
  74
  75 static struct irq_pin_list {
  76         int apic, pin, next;
  77 } irq_2_pin[PIN_MAP_SIZE];
  78
  79 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  80 #ifdef CONFIG_PCI_MSI
  81 #define vector_to_irq(vector)   \
  82         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  83 #else
  84 #define vector_to_irq(vector)   (vector)
  85 #endif
  86
  87 /*
  88  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  89  * shared ISA-space IRQs, so we have to support them. We are super
  90  * fast in the common case, and fast for shared ISA-space IRQs.
  91  */
  92 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  93 {
  94         static int first_free_entry = NR_IRQS;
  95         struct irq_pin_list *entry = irq_2_pin + irq;
  96
  97         while (entry->next)
  98                 entry = irq_2_pin + entry->next;
  99
 100         if (entry->pin != -1) {
 101                 entry->next = first_free_entry;
 102                 entry = irq_2_pin + entry->next;
 103                 if (++first_free_entry >= PIN_MAP_SIZE)
 104                         panic("io_apic.c: whoops");
 105         }
 106         entry->apic = apic;
 107         entry->pin = pin;
 108 }
 109
 110 /*
 111  * Reroute an IRQ to a different pin.
 112  */
 113 static void __init replace_pin_at_irq(unsigned int irq,
 114                                       int oldapic, int oldpin,
 115                                       int newapic, int newpin)
 116 {
 117         struct irq_pin_list *entry = irq_2_pin + irq;
 118
 119         while (1) {
 120                 if (entry->apic == oldapic && entry->pin == oldpin) {
 121                         entry->apic = newapic;
 122                         entry->pin = newpin;
 123                 }
 124                 if (!entry->next)
 125                         break;
 126                 entry = irq_2_pin + entry->next;
 127         }
 128 }
 129
 130 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 131 {
 132         struct irq_pin_list *entry = irq_2_pin + irq;
 133         unsigned int pin, reg;
 134
 135         for (;;) {
 136                 pin = entry->pin;
 137                 if (pin == -1)
 138                         break;
 139                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 140                 reg &= ~disable;
 141                 reg |= enable;
 142                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 143                 if (!entry->next)
 144                         break;
 145                 entry = irq_2_pin + entry->next;
 146         }
 147 }
 148
 149 /* mask = 1 */
 150 static void __mask_IO_APIC_irq (unsigned int irq)
 151 {
 152         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 153 }
 154
 155 /* mask = 0 */
 156 static void __unmask_IO_APIC_irq (unsigned int irq)
 157 {
 158         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 159 }
 160
 161 /* mask = 1, trigger = 0 */
 162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 163 {
 164         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 165 }
 166
 167 /* mask = 0, trigger = 1 */
 168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 169 {
 170         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 171 }
 172
 173 static void mask_IO_APIC_irq (unsigned int irq)
 174 {
 175         unsigned long flags;
 176
 177         spin_lock_irqsave(&ioapic_lock, flags);
 178         __mask_IO_APIC_irq(irq);
 179         spin_unlock_irqrestore(&ioapic_lock, flags);
 180 }
 181
 182 static void unmask_IO_APIC_irq (unsigned int irq)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         __unmask_IO_APIC_irq(irq);
 188         spin_unlock_irqrestore(&ioapic_lock, flags);
 189 }
 190
 191 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 192 {
 193         struct IO_APIC_route_entry entry;
 194         unsigned long flags;
 195
 196         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 199         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         if (entry.delivery_mode == dest_SMI)
 202                 return;
 203
 204         /*
 205          * Disable it in the IO-APIC irq-routing table:
 206          */
 207         memset(&entry, 0, sizeof(entry));
 208         entry.mask = 1;
 209         spin_lock_irqsave(&ioapic_lock, flags);
 210         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 211         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 212         spin_unlock_irqrestore(&ioapic_lock, flags);
 213 }
 214
 215 static void clear_IO_APIC (void)
 216 {
 217         int apic, pin;
 218
 219         for (apic = 0; apic < nr_ioapics; apic++)
 220                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 221                         clear_IO_APIC_pin(apic, pin);
 222 }
 223
 224 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 225 {
 226         unsigned long flags;
 227         int pin;
 228         struct irq_pin_list *entry = irq_2_pin + irq;
 229         unsigned int apicid_value;
 230
 231         apicid_value = cpu_mask_to_apicid(cpumask);
 232         /* Prepare to do the io_apic_write */
 233         apicid_value = apicid_value << 24;
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         for (;;) {
 236                 pin = entry->pin;
 237                 if (pin == -1)
 238                         break;
 239                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 240                 if (!entry->next)
 241                         break;
 242                 entry = irq_2_pin + entry->next;
 243         }
 244         spin_unlock_irqrestore(&ioapic_lock, flags);
 245 }
 246
 247 #if defined(CONFIG_IRQBALANCE)
 248 # include <asm/processor.h>     /* kernel_thread() */
 249 # include <linux/kernel_stat.h> /* kstat */
 250 # include <linux/slab.h>                /* kmalloc() */
 251 # include <linux/timer.h>       /* time_after() */
 252
 253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 254 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 255 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 256 # else
 257 #  define TDprintk(x...)
 258 #  define Dprintk(x...)
 259 # endif
 260
 261 extern cpumask_t irq_affinity[NR_IRQS];
 262
 263 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
 264
 265 #define IRQBALANCE_CHECK_ARCH -999
 266 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 267 static int physical_balance = 0;
 268
 269 struct irq_cpu_info {
 270         unsigned long * last_irq;
 271         unsigned long * irq_delta;
 272         unsigned long irq;
 273 } irq_cpu_data[NR_CPUS];
 274
 275 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 276 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 277 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 278
 279 #define IDLE_ENOUGH(cpu,now) \
 280                 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
 281
 282 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 283
 284 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 285
 286 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 287 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 288 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 289 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 290
 291 long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 292
 293 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 294                         unsigned long now, int direction)
 295 {
 296         int search_idle = 1;
 297         int cpu = curr_cpu;
 298
 299         goto inside;
 300
 301         do {
 302                 if (unlikely(cpu == curr_cpu))
 303                         search_idle = 0;
 304 inside:
 305                 if (direction == 1) {
 306                         cpu++;
 307                         if (cpu >= NR_CPUS)
 308                                 cpu = 0;
 309                 } else {
 310                         cpu--;
 311                         if (cpu == -1)
 312                                 cpu = NR_CPUS-1;
 313                 }
 314         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 315                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 316
 317         return cpu;
 318 }
 319
 320 static inline void balance_irq(int cpu, int irq)
 321 {
 322         unsigned long now = jiffies;
 323         cpumask_t allowed_mask;
 324         unsigned int new_cpu;
 325
 326         if (irqbalance_disabled)
 327                 return;
 328
 329         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 330         new_cpu = move(cpu, allowed_mask, now, 1);
 331         if (cpu != new_cpu) {
 332                 irq_desc_t *desc = irq_desc + irq;
 333                 unsigned long flags;
 334
 335                 spin_lock_irqsave(&desc->lock, flags);
 336                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
 337                 spin_unlock_irqrestore(&desc->lock, flags);
 338         }
 339 }
 340
 341 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 342 {
 343         int i, j;
 344         Dprintk("Rotating IRQs among CPUs.\n");
 345         for (i = 0; i < NR_CPUS; i++) {
 346                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 347                         if (!irq_desc[j].action)
 348                                 continue;
 349                         /* Is it a significant load ?  */
 350                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 351                                                 useful_load_threshold)
 352                                 continue;
 353                         balance_irq(i, j);
 354                 }
 355         }
 356         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 357                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 358         return;
 359 }
 360
 361 static void do_irq_balance(void)
 362 {
 363         int i, j;
 364         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 365         unsigned long move_this_load = 0;
 366         int max_loaded = 0, min_loaded = 0;
 367         int load;
 368         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 369         int selected_irq;
 370         int tmp_loaded, first_attempt = 1;
 371         unsigned long tmp_cpu_irq;
 372         unsigned long imbalance = 0;
 373         cpumask_t allowed_mask, target_cpu_mask, tmp;
 374
 375         for (i = 0; i < NR_CPUS; i++) {
 376                 int package_index;
 377                 CPU_IRQ(i) = 0;
 378                 if (!cpu_online(i))
 379                         continue;
 380                 package_index = CPU_TO_PACKAGEINDEX(i);
 381                 for (j = 0; j < NR_IRQS; j++) {
 382                         unsigned long value_now, delta;
 383                         /* Is this an active IRQ? */
 384                         if (!irq_desc[j].action)
 385                                 continue;
 386                         if ( package_index == i )
 387                                 IRQ_DELTA(package_index,j) = 0;
 388                         /* Determine the total count per processor per IRQ */
 389                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 390
 391                         /* Determine the activity per processor per IRQ */
 392                         delta = value_now - LAST_CPU_IRQ(i,j);
 393
 394                         /* Update last_cpu_irq[][] for the next time */
 395                         LAST_CPU_IRQ(i,j) = value_now;
 396
 397                         /* Ignore IRQs whose rate is less than the clock */
 398                         if (delta < useful_load_threshold)
 399                                 continue;
 400                         /* update the load for the processor or package total */
 401                         IRQ_DELTA(package_index,j) += delta;
 402
 403                         /* Keep track of the higher numbered sibling as well */
 404                         if (i != package_index)
 405                                 CPU_IRQ(i) += delta;
 406                         /*
 407                          * We have sibling A and sibling B in the package
 408                          *
 409                          * cpu_irq[A] = load for cpu A + load for cpu B
 410                          * cpu_irq[B] = load for cpu B
 411                          */
 412                         CPU_IRQ(package_index) += delta;
 413                 }
 414         }
 415         /* Find the least loaded processor package */
 416         for (i = 0; i < NR_CPUS; i++) {
 417                 if (!cpu_online(i))
 418                         continue;
 419                 if (i != CPU_TO_PACKAGEINDEX(i))
 420                         continue;
 421                 if (min_cpu_irq > CPU_IRQ(i)) {
 422                         min_cpu_irq = CPU_IRQ(i);
 423                         min_loaded = i;
 424                 }
 425         }
 426         max_cpu_irq = ULONG_MAX;
 427
 428 tryanothercpu:
 429         /* Look for heaviest loaded processor.
 430          * We may come back to get the next heaviest loaded processor.
 431          * Skip processors with trivial loads.
 432          */
 433         tmp_cpu_irq = 0;
 434         tmp_loaded = -1;
 435         for (i = 0; i < NR_CPUS; i++) {
 436                 if (!cpu_online(i))
 437                         continue;
 438                 if (i != CPU_TO_PACKAGEINDEX(i))
 439                         continue;
 440                 if (max_cpu_irq <= CPU_IRQ(i))
 441                         continue;
 442                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 443                         tmp_cpu_irq = CPU_IRQ(i);
 444                         tmp_loaded = i;
 445                 }
 446         }
 447
 448         if (tmp_loaded == -1) {
 449          /* In the case of small number of heavy interrupt sources,
 450           * loading some of the cpus too much. We use Ingo's original
 451           * approach to rotate them around.
 452           */
 453                 if (!first_attempt && imbalance >= useful_load_threshold) {
 454                         rotate_irqs_among_cpus(useful_load_threshold);
 455                         return;
 456                 }
 457                 goto not_worth_the_effort;
 458         }
 459
 460         first_attempt = 0;              /* heaviest search */
 461         max_cpu_irq = tmp_cpu_irq;      /* load */
 462         max_loaded = tmp_loaded;        /* processor */
 463         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 464
 465         Dprintk("max_loaded cpu = %d\n", max_loaded);
 466         Dprintk("min_loaded cpu = %d\n", min_loaded);
 467         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 468         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 469         Dprintk("load imbalance = %lu\n", imbalance);
 470
 471         /* if imbalance is less than approx 10% of max load, then
 472          * observe diminishing returns action. - quit
 473          */
 474         if (imbalance < (max_cpu_irq >> 3)) {
 475                 Dprintk("Imbalance too trivial\n");
 476                 goto not_worth_the_effort;
 477         }
 478
 479 tryanotherirq:
 480         /* if we select an IRQ to move that can't go where we want, then
 481          * see if there is another one to try.
 482          */
 483         move_this_load = 0;
 484         selected_irq = -1;
 485         for (j = 0; j < NR_IRQS; j++) {
 486                 /* Is this an active IRQ? */
 487                 if (!irq_desc[j].action)
 488                         continue;
 489                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 490                         continue;
 491                 /* Try to find the IRQ that is closest to the imbalance
 492                  * without going over.
 493                  */
 494                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 495                         move_this_load = IRQ_DELTA(max_loaded,j);
 496                         selected_irq = j;
 497                 }
 498         }
 499         if (selected_irq == -1) {
 500                 goto tryanothercpu;
 501         }
 502
 503         imbalance = move_this_load;
 504
 505         /* For physical_balance case, we accumlated both load
 506          * values in the one of the siblings cpu_irq[],
 507          * to use the same code for physical and logical processors
 508          * as much as possible.
 509          *
 510          * NOTE: the cpu_irq[] array holds the sum of the load for
 511          * sibling A and sibling B in the slot for the lowest numbered
 512          * sibling (A), _AND_ the load for sibling B in the slot for
 513          * the higher numbered sibling.
 514          *
 515          * We seek the least loaded sibling by making the comparison
 516          * (A+B)/2 vs B
 517          */
 518         load = CPU_IRQ(min_loaded) >> 1;
 519         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 520                 if (load > CPU_IRQ(j)) {
 521                         /* This won't change cpu_sibling_map[min_loaded] */
 522                         load = CPU_IRQ(j);
 523                         min_loaded = j;
 524                 }
 525         }
 526
 527         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 528         target_cpu_mask = cpumask_of_cpu(min_loaded);
 529         cpus_and(tmp, target_cpu_mask, allowed_mask);
 530
 531         if (!cpus_empty(tmp)) {
 532                 irq_desc_t *desc = irq_desc + selected_irq;
 533                 unsigned long flags;
 534
 535                 Dprintk("irq = %d moved to cpu = %d\n",
 536                                 selected_irq, min_loaded);
 537                 /* mark for change destination */
 538                 spin_lock_irqsave(&desc->lock, flags);
 539                 pending_irq_balance_cpumask[selected_irq] =
 540                                         cpumask_of_cpu(min_loaded);
 541                 spin_unlock_irqrestore(&desc->lock, flags);
 542                 /* Since we made a change, come back sooner to
 543                  * check for more variation.
 544                  */
 545                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 546                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 547                 return;
 548         }
 549         goto tryanotherirq;
 550
 551 not_worth_the_effort:
 552         /*
 553          * if we did not find an IRQ to move, then adjust the time interval
 554          * upward
 555          */
 556         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 557                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 558         Dprintk("IRQ worth rotating not found\n");
 559         return;
 560 }
 561
 562 static int balanced_irq(void *unused)
 563 {
 564         int i;
 565         unsigned long prev_balance_time = jiffies;
 566         long time_remaining = balanced_irq_interval;
 567
 568         daemonize("kirqd");
 569
 570         /* push everything to CPU 0 to give us a starting point.  */
 571         for (i = 0 ; i < NR_IRQS ; i++) {
 572                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
 573         }
 574
 575         for ( ; ; ) {
 576                 set_current_state(TASK_INTERRUPTIBLE);
 577                 time_remaining = schedule_timeout(time_remaining);
 578                 if (time_after(jiffies,
 579                                 prev_balance_time+balanced_irq_interval)) {
 580                         do_irq_balance();
 581                         prev_balance_time = jiffies;
 582                         time_remaining = balanced_irq_interval;
 583                 }
 584         }
 585         return 0;
 586 }
 587
 588 static int __init balanced_irq_init(void)
 589 {
 590         int i;
 591         struct cpuinfo_x86 *c;
 592         cpumask_t tmp;
 593
 594         cpus_shift_right(tmp, cpu_online_map, 2);
 595         c = &boot_cpu_data;
 596         /* When not overwritten by the command line ask subarchitecture. */
 597         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 598                 irqbalance_disabled = NO_BALANCE_IRQ;
 599         if (irqbalance_disabled)
 600                 return 0;
 601
 602          /* disable irqbalance completely if there is only one processor online */
 603         if (num_online_cpus() < 2) {
 604                 irqbalance_disabled = 1;
 605                 return 0;
 606         }
 607         /*
 608          * Enable physical balance only if more than 1 physical processor
 609          * is present
 610          */
 611         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 612                 physical_balance = 1;
 613
 614         for (i = 0; i < NR_CPUS; i++) {
 615                 if (!cpu_online(i))
 616                         continue;
 617                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 618                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 619                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 620                         printk(KERN_ERR "balanced_irq_init: out of memory");
 621                         goto failed;
 622                 }
 623                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 624                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 625         }
 626
 627         printk(KERN_INFO "Starting balanced_irq\n");
 628         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 629                 return 0;
 630         else
 631                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 632 failed:
 633         for (i = 0; i < NR_CPUS; i++) {
 634                 if(irq_cpu_data[i].irq_delta)
 635                         kfree(irq_cpu_data[i].irq_delta);
 636                 if(irq_cpu_data[i].last_irq)
 637                         kfree(irq_cpu_data[i].last_irq);
 638         }
 639         return 0;
 640 }
 641
 642 static int __init irqbalance_disable(char *str)
 643 {
 644         irqbalance_disabled = 1;
 645         return 0;
 646 }
 647
 648 __setup("noirqbalance", irqbalance_disable);
 649
 650 static inline void move_irq(int irq)
 651 {
 652         /* note - we hold the desc->lock */
 653         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
 654                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
 655                 cpus_clear(pending_irq_balance_cpumask[irq]);
 656         }
 657 }
 658
 659 __initcall(balanced_irq_init);
 660
 661 #else /* !CONFIG_IRQBALANCE */
 662 static inline void move_irq(int irq) { }
 663 #endif /* CONFIG_IRQBALANCE */
 664
 665 #ifndef CONFIG_SMP
 666 void fastcall send_IPI_self(int vector)
 667 {
 668         unsigned int cfg;
 669
 670         /*
 671          * Wait for idle.
 672          */
 673         apic_wait_icr_idle();
 674         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 675         /*
 676          * Send the IPI. The write to APIC_ICR fires this off.
 677          */
 678         apic_write_around(APIC_ICR, cfg);
 679 }
 680 #endif /* !CONFIG_SMP */
 681
 682
 683 /*
 684  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 685  * specific CPU-side IRQs.
 686  */
 687
 688 #define MAX_PIRQS 8
 689 int pirq_entries [MAX_PIRQS];
 690 int pirqs_enabled;
 691 #ifdef CONFIG_SMP
 692 int skip_ioapic_setup = 0;
 693 #else
 694 int skip_ioapic_setup = 1;
 695 #endif
 696
 697 static int __init ioapic_setup(char *str)
 698 {
 699         skip_ioapic_setup = 1;
 700         return 1;
 701 }
 702
 703 __setup("noapic", ioapic_setup);
 704
 705 static int __init ioapic_pirq_setup(char *str)
 706 {
 707         int i, max;
 708         int ints[MAX_PIRQS+1];
 709
 710         get_options(str, ARRAY_SIZE(ints), ints);
 711
 712         for (i = 0; i < MAX_PIRQS; i++)
 713                 pirq_entries[i] = -1;
 714
 715         pirqs_enabled = 1;
 716         printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
 717         max = MAX_PIRQS;
 718         if (ints[0] < MAX_PIRQS)
 719                 max = ints[0];
 720
 721         for (i = 0; i < max; i++) {
 722                 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 723                 /*
 724                  * PIRQs are mapped upside down, usually.
 725                  */
 726                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 727         }
 728         return 1;
 729 }
 730
 731 __setup("pirq=", ioapic_pirq_setup);
 732
 733 /*
 734  * Find the IRQ entry number of a certain pin.
 735  */
 736 static int __init find_irq_entry(int apic, int pin, int type)
 737 {
 738         int i;
 739
 740         for (i = 0; i < mp_irq_entries; i++)
 741                 if (mp_irqs[i].mpc_irqtype == type &&
 742                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 743                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 744                     mp_irqs[i].mpc_dstirq == pin)
 745                         return i;
 746
 747         return -1;
 748 }
 749
 750 /*
 751  * Find the pin to which IRQ[irq] (ISA) is connected
 752  */
 753 static int __init find_isa_irq_pin(int irq, int type)
 754 {
 755         int i;
 756
 757         for (i = 0; i < mp_irq_entries; i++) {
 758                 int lbus = mp_irqs[i].mpc_srcbus;
 759
 760                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 761                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 762                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 763                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 764                     ) &&
 765                     (mp_irqs[i].mpc_irqtype == type) &&
 766                     (mp_irqs[i].mpc_srcbusirq == irq))
 767
 768                         return mp_irqs[i].mpc_dstirq;
 769         }
 770         return -1;
 771 }
 772
 773 /*
 774  * Find a specific PCI IRQ entry.
 775  * Not an __init, possibly needed by modules
 776  */
 777 static int pin_2_irq(int idx, int apic, int pin);
 778
 779 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 780 {
 781         int apic, i, best_guess = -1;
 782
 783         Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 784                 bus, slot, pin);
 785         if (mp_bus_id_to_pci_bus[bus] == -1) {
 786                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 787                 return -1;
 788         }
 789         for (i = 0; i < mp_irq_entries; i++) {
 790                 int lbus = mp_irqs[i].mpc_srcbus;
 791
 792                 for (apic = 0; apic < nr_ioapics; apic++)
 793                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 794                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 795                                 break;
 796
 797                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 798                     !mp_irqs[i].mpc_irqtype &&
 799                     (bus == lbus) &&
 800                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 801                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 802
 803                         if (!(apic || IO_APIC_IRQ(irq)))
 804                                 continue;
 805
 806                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 807                                 return irq;
 808                         /*
 809                          * Use the first all-but-pin matching entry as a
 810                          * best-guess fuzzy result for broken mptables.
 811                          */
 812                         if (best_guess < 0)
 813                                 best_guess = irq;
 814                 }
 815         }
 816         return best_guess;
 817 }
 818
 819 /*
 820  * This function currently is only a helper for the i386 smp boot process where
 821  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 822  * so mask in all cases should simply be TARGET_CPUS
 823  */
 824 void __init setup_ioapic_dest(void)
 825 {
 826         int pin, ioapic, irq, irq_entry;
 827
 828         if (skip_ioapic_setup == 1)
 829                 return;
 830
 831         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 832                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 833                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 834                         if (irq_entry == -1)
 835                                 continue;
 836                         irq = pin_2_irq(irq_entry, ioapic, pin);
 837                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 838                 }
 839
 840         }
 841 }
 842
 843 /*
 844  * EISA Edge/Level control register, ELCR
 845  */
 846 static int __init EISA_ELCR(unsigned int irq)
 847 {
 848         if (irq < 16) {
 849                 unsigned int port = 0x4d0 + (irq >> 3);
 850                 return (inb(port) >> (irq & 7)) & 1;
 851         }
 852         printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
 853         return 0;
 854 }
 855
 856 /* EISA interrupts are always polarity zero and can be edge or level
 857  * trigger depending on the ELCR value.  If an interrupt is listed as
 858  * EISA conforming in the MP table, that means its trigger type must
 859  * be read in from the ELCR */
 860
 861 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 862 #define default_EISA_polarity(idx)      (0)
 863
 864 /* ISA interrupts are always polarity zero edge triggered,
 865  * when listed as conforming in the MP table. */
 866
 867 #define default_ISA_trigger(idx)        (0)
 868 #define default_ISA_polarity(idx)       (0)
 869
 870 /* PCI interrupts are always polarity one level triggered,
 871  * when listed as conforming in the MP table. */
 872
 873 #define default_PCI_trigger(idx)        (1)
 874 #define default_PCI_polarity(idx)       (1)
 875
 876 /* MCA interrupts are always polarity zero level triggered,
 877  * when listed as conforming in the MP table. */
 878
 879 #define default_MCA_trigger(idx)        (1)
 880 #define default_MCA_polarity(idx)       (0)
 881
 882 /* NEC98 interrupts are always polarity zero edge triggered,
 883  * when listed as conforming in the MP table. */
 884
 885 #define default_NEC98_trigger(idx)     (0)
 886 #define default_NEC98_polarity(idx)    (0)
 887
 888 static int __init MPBIOS_polarity(int idx)
 889 {
 890         int bus = mp_irqs[idx].mpc_srcbus;
 891         int polarity;
 892
 893         /*
 894          * Determine IRQ line polarity (high active or low active):
 895          */
 896         switch (mp_irqs[idx].mpc_irqflag & 3)
 897         {
 898                 case 0: /* conforms, ie. bus-type dependent polarity */
 899                 {
 900                         switch (mp_bus_id_to_type[bus])
 901                         {
 902                                 case MP_BUS_ISA: /* ISA pin */
 903                                 {
 904                                         polarity = default_ISA_polarity(idx);
 905                                         break;
 906                                 }
 907                                 case MP_BUS_EISA: /* EISA pin */
 908                                 {
 909                                         polarity = default_EISA_polarity(idx);
 910                                         break;
 911                                 }
 912                                 case MP_BUS_PCI: /* PCI pin */
 913                                 {
 914                                         polarity = default_PCI_polarity(idx);
 915                                         break;
 916                                 }
 917                                 case MP_BUS_MCA: /* MCA pin */
 918                                 {
 919                                         polarity = default_MCA_polarity(idx);
 920                                         break;
 921                                 }
 922                                 case MP_BUS_NEC98: /* NEC 98 pin */
 923                                 {
 924                                         polarity = default_NEC98_polarity(idx);
 925                                         break;
 926                                 }
 927                                 default:
 928                                 {
 929                                         printk(KERN_WARNING "broken BIOS!!\n");
 930                                         polarity = 1;
 931                                         break;
 932                                 }
 933                         }
 934                         break;
 935                 }
 936                 case 1: /* high active */
 937                 {
 938                         polarity = 0;
 939                         break;
 940                 }
 941                 case 2: /* reserved */
 942                 {
 943                         printk(KERN_WARNING "broken BIOS!!\n");
 944                         polarity = 1;
 945                         break;
 946                 }
 947                 case 3: /* low active */
 948                 {
 949                         polarity = 1;
 950                         break;
 951                 }
 952                 default: /* invalid */
 953                 {
 954                         printk(KERN_WARNING "broken BIOS!!\n");
 955                         polarity = 1;
 956                         break;
 957                 }
 958         }
 959         return polarity;
 960 }
 961
 962 static int __init MPBIOS_trigger(int idx)
 963 {
 964         int bus = mp_irqs[idx].mpc_srcbus;
 965         int trigger;
 966
 967         /*
 968          * Determine IRQ trigger mode (edge or level sensitive):
 969          */
 970         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 971         {
 972                 case 0: /* conforms, ie. bus-type dependent */
 973                 {
 974                         switch (mp_bus_id_to_type[bus])
 975                         {
 976                                 case MP_BUS_ISA: /* ISA pin */
 977                                 {
 978                                         trigger = default_ISA_trigger(idx);
 979                                         break;
 980                                 }
 981                                 case MP_BUS_EISA: /* EISA pin */
 982                                 {
 983                                         trigger = default_EISA_trigger(idx);
 984                                         break;
 985                                 }
 986                                 case MP_BUS_PCI: /* PCI pin */
 987                                 {
 988                                         trigger = default_PCI_trigger(idx);
 989                                         break;
 990                                 }
 991                                 case MP_BUS_MCA: /* MCA pin */
 992                                 {
 993                                         trigger = default_MCA_trigger(idx);
 994                                         break;
 995                                 }
 996                                 case MP_BUS_NEC98: /* NEC 98 pin */
 997                                 {
 998                                         trigger = default_NEC98_trigger(idx);
 999                                         break;
1000                                 }
1001                                 default:
1002                                 {
1003                                         printk(KERN_WARNING "broken BIOS!!\n");
1004                                         trigger = 1;
1005                                         break;
1006                                 }
1007                         }
1008                         break;
1009                 }
1010                 case 1: /* edge */
1011                 {
1012                         trigger = 0;
1013                         break;
1014                 }
1015                 case 2: /* reserved */
1016                 {
1017                         printk(KERN_WARNING "broken BIOS!!\n");
1018                         trigger = 1;
1019                         break;
1020                 }
1021                 case 3: /* level */
1022                 {
1023                         trigger = 1;
1024                         break;
1025                 }
1026                 default: /* invalid */
1027                 {
1028                         printk(KERN_WARNING "broken BIOS!!\n");
1029                         trigger = 0;
1030                         break;
1031                 }
1032         }
1033         return trigger;
1034 }
1035
1036 static inline int irq_polarity(int idx)
1037 {
1038         return MPBIOS_polarity(idx);
1039 }
1040
1041 static inline int irq_trigger(int idx)
1042 {
1043         return MPBIOS_trigger(idx);
1044 }
1045
1046 static int pin_2_irq(int idx, int apic, int pin)
1047 {
1048         int irq, i;
1049         int bus = mp_irqs[idx].mpc_srcbus;
1050
1051         /*
1052          * Debugging check, we are in big trouble if this message pops up!
1053          */
1054         if (mp_irqs[idx].mpc_dstirq != pin)
1055                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1056
1057         switch (mp_bus_id_to_type[bus])
1058         {
1059                 case MP_BUS_ISA: /* ISA pin */
1060                 case MP_BUS_EISA:
1061                 case MP_BUS_MCA:
1062                 case MP_BUS_NEC98:
1063                 {
1064                         irq = mp_irqs[idx].mpc_srcbusirq;
1065                         break;
1066                 }
1067                 case MP_BUS_PCI: /* PCI pin */
1068                 {
1069                         /*
1070                          * PCI IRQs are mapped in order
1071                          */
1072                         i = irq = 0;
1073                         while (i < apic)
1074                                 irq += nr_ioapic_registers[i++];
1075                         irq += pin;
1076                         if ((!apic) && (irq < 16))
1077                                 irq += 16;
1078                         break;
1079                 }
1080                 default:
1081                 {
1082                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1083                         irq = 0;
1084                         break;
1085                 }
1086         }
1087
1088         /*
1089          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1090          */
1091         if ((pin >= 16) && (pin <= 23)) {
1092                 if (pirq_entries[pin-16] != -1) {
1093                         if (!pirq_entries[pin-16]) {
1094                                 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
1095                         } else {
1096                                 irq = pirq_entries[pin-16];
1097                                 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
1098                                                 pin-16, irq);
1099                         }
1100                 }
1101         }
1102         return irq;
1103 }
1104
1105 static inline int IO_APIC_irq_trigger(int irq)
1106 {
1107         int apic, idx, pin;
1108
1109         for (apic = 0; apic < nr_ioapics; apic++) {
1110                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1111                         idx = find_irq_entry(apic,pin,mp_INT);
1112                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1113                                 return irq_trigger(idx);
1114                 }
1115         }
1116         /*
1117          * nonexistent IRQs are edge default
1118          */
1119         return 0;
1120 }
1121
1122 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1123 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1124
1125 #ifdef CONFIG_PCI_MSI
1126 int assign_irq_vector(int irq)
1127 #else
1128 int __init assign_irq_vector(int irq)
1129 #endif
1130 {
1131         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1132
1133         BUG_ON(irq >= NR_IRQ_VECTORS);
1134         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1135                 return IO_APIC_VECTOR(irq);
1136 next:
1137         current_vector += 8;
1138         if (current_vector == SYSCALL_VECTOR)
1139                 goto next;
1140 #ifdef  CONFIG_KDB
1141         if (current_vector == KDBENTER_VECTOR)
1142                 goto next;
1143 #endif  /* CONFIG_KDB */
1144
1145         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1146                 offset++;
1147                 if (!(offset%8))
1148                         return -ENOSPC;
1149                 current_vector = FIRST_DEVICE_VECTOR + offset;
1150         }
1151
1152         vector_irq[current_vector] = irq;
1153         if (irq != AUTO_ASSIGN)
1154                 IO_APIC_VECTOR(irq) = current_vector;
1155
1156         return current_vector;
1157 }
1158
1159 static struct hw_interrupt_type ioapic_level_type;
1160 static struct hw_interrupt_type ioapic_edge_type;
1161
1162 #define IOAPIC_AUTO     -1
1163 #define IOAPIC_EDGE     0
1164 #define IOAPIC_LEVEL    1
1165
1166 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1167 {
1168         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1169                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1170                                 trigger == IOAPIC_LEVEL)
1171                         irq_desc[vector].handler = &ioapic_level_type;
1172                 else
1173                         irq_desc[vector].handler = &ioapic_edge_type;
1174                 set_intr_gate(vector, interrupt[vector]);
1175         } else  {
1176                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1177                                 trigger == IOAPIC_LEVEL)
1178                         irq_desc[irq].handler = &ioapic_level_type;
1179                 else
1180                         irq_desc[irq].handler = &ioapic_edge_type;
1181                 set_intr_gate(vector, interrupt[irq]);
1182         }
1183 }
1184
1185 void __init setup_IO_APIC_irqs(void)
1186 {
1187         struct IO_APIC_route_entry entry;
1188         int apic, pin, idx, irq, first_notcon = 1, vector;
1189         unsigned long flags;
1190
1191         printk(KERN_DEBUG "init IO_APIC IRQs\n");
1192
1193         for (apic = 0; apic < nr_ioapics; apic++) {
1194         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1195
1196                 /*
1197                  * add it to the IO-APIC irq-routing table:
1198                  */
1199                 memset(&entry,0,sizeof(entry));
1200
1201                 entry.delivery_mode = INT_DELIVERY_MODE;
1202                 entry.dest_mode = INT_DEST_MODE;
1203                 entry.mask = 0;                         /* enable IRQ */
1204                 entry.dest.logical.logical_dest =
1205                                         cpu_mask_to_apicid(TARGET_CPUS);
1206
1207                 idx = find_irq_entry(apic,pin,mp_INT);
1208                 if (idx == -1) {
1209                         if (first_notcon) {
1210                                 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
1211                                 first_notcon = 0;
1212                         } else
1213                                 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
1214                         continue;
1215                 }
1216
1217                 entry.trigger = irq_trigger(idx);
1218                 entry.polarity = irq_polarity(idx);
1219
1220                 if (irq_trigger(idx)) {
1221                         entry.trigger = 1;
1222                         entry.mask = 1;
1223                 }
1224
1225                 irq = pin_2_irq(idx, apic, pin);
1226                 /*
1227                  * skip adding the timer int on secondary nodes, which causes
1228                  * a small but painful rift in the time-space continuum
1229                  */
1230                 if (multi_timer_check(apic, irq))
1231                         continue;
1232                 else
1233                         add_pin_to_irq(irq, apic, pin);
1234
1235                 if (!apic && !IO_APIC_IRQ(irq))
1236                         continue;
1237
1238                 if (IO_APIC_IRQ(irq)) {
1239                         vector = assign_irq_vector(irq);
1240                         entry.vector = vector;
1241                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1242
1243                         if (!apic && (irq < 16))
1244                                 disable_8259A_irq(irq);
1245                 }
1246                 spin_lock_irqsave(&ioapic_lock, flags);
1247                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1248                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1249                 spin_unlock_irqrestore(&ioapic_lock, flags);
1250         }
1251         }
1252
1253         if (!first_notcon)
1254                 printk(" not connected.\n");
1255 }
1256
1257 /*
1258  * Set up the 8259A-master output pin:
1259  */
1260 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1261 {
1262         struct IO_APIC_route_entry entry;
1263         unsigned long flags;
1264
1265         memset(&entry,0,sizeof(entry));
1266
1267         disable_8259A_irq(0);
1268
1269         /* mask LVT0 */
1270         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1271
1272         /*
1273          * We use logical delivery to get the timer IRQ
1274          * to the first CPU.
1275          */
1276         entry.dest_mode = INT_DEST_MODE;
1277         entry.mask = 0;                                 /* unmask IRQ now */
1278         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1279         entry.delivery_mode = INT_DELIVERY_MODE;
1280         entry.polarity = 0;
1281         entry.trigger = 0;
1282         entry.vector = vector;
1283
1284         /*
1285          * The timer IRQ doesn't have to know that behind the
1286          * scene we have a 8259A-master in AEOI mode ...
1287          */
1288         irq_desc[0].handler = &ioapic_edge_type;
1289
1290         /*
1291          * Add it to the IO-APIC irq-routing table:
1292          */
1293         spin_lock_irqsave(&ioapic_lock, flags);
1294         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1295         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1296         spin_unlock_irqrestore(&ioapic_lock, flags);
1297
1298         enable_8259A_irq(0);
1299 }
1300
1301 static inline void UNEXPECTED_IO_APIC(void)
1302 {
1303 }
1304
1305 void __init print_IO_APIC(void)
1306 {
1307         int apic, i;
1308         union IO_APIC_reg_00 reg_00;
1309         union IO_APIC_reg_01 reg_01;
1310         union IO_APIC_reg_02 reg_02;
1311         union IO_APIC_reg_03 reg_03;
1312         unsigned long flags;
1313
1314         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1315         for (i = 0; i < nr_ioapics; i++)
1316                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1317                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1318
1319         /*
1320          * We are a bit conservative about what we expect.  We have to
1321          * know about every hardware change ASAP.
1322          */
1323         printk(KERN_INFO "testing the IO APIC.......................\n");
1324
1325         for (apic = 0; apic < nr_ioapics; apic++) {
1326
1327         spin_lock_irqsave(&ioapic_lock, flags);
1328         reg_00.raw = io_apic_read(apic, 0);
1329         reg_01.raw = io_apic_read(apic, 1);
1330         if (reg_01.bits.version >= 0x10)
1331                 reg_02.raw = io_apic_read(apic, 2);
1332         if (reg_01.bits.version >= 0x20)
1333                 reg_03.raw = io_apic_read(apic, 3);
1334         spin_unlock_irqrestore(&ioapic_lock, flags);
1335
1336         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1337         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1338         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1339         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1340         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1341         if (reg_00.bits.ID >= get_physical_broadcast())
1342                 UNEXPECTED_IO_APIC();
1343         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1344                 UNEXPECTED_IO_APIC();
1345
1346         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1347         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1348         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1349                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1350                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1351                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1352                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1353                 (reg_01.bits.entries != 0x2E) &&
1354                 (reg_01.bits.entries != 0x3F)
1355         )
1356                 UNEXPECTED_IO_APIC();
1357
1358         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1359         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1360         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1361                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1362                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1363                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1364                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1365         )
1366                 UNEXPECTED_IO_APIC();
1367         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1368                 UNEXPECTED_IO_APIC();
1369
1370         /*
1371          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1372          * but the value of reg_02 is read as the previous read register
1373          * value, so ignore it if reg_02 == reg_01.
1374          */
1375         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1376                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1377                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1378                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1379                         UNEXPECTED_IO_APIC();
1380         }
1381
1382         /*
1383          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1384          * or reg_03, but the value of reg_0[23] is read as the previous read
1385          * register value, so ignore it if reg_03 == reg_0[12].
1386          */
1387         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1388             reg_03.raw != reg_01.raw) {
1389                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1390                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1391                 if (reg_03.bits.__reserved_1)
1392                         UNEXPECTED_IO_APIC();
1393         }
1394
1395         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1396
1397         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1398                           " Stat Dest Deli Vect:   \n");
1399
1400         for (i = 0; i <= reg_01.bits.entries; i++) {
1401                 struct IO_APIC_route_entry entry;
1402
1403                 spin_lock_irqsave(&ioapic_lock, flags);
1404                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1405                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1406                 spin_unlock_irqrestore(&ioapic_lock, flags);
1407
1408                 printk(KERN_DEBUG " %02x %03X %02X  ",
1409                         i,
1410                         entry.dest.logical.logical_dest,
1411                         entry.dest.physical.physical_dest
1412                 );
1413
1414                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1415                         entry.mask,
1416                         entry.trigger,
1417                         entry.irr,
1418                         entry.polarity,
1419                         entry.delivery_status,
1420                         entry.dest_mode,
1421                         entry.delivery_mode,
1422                         entry.vector
1423                 );
1424         }
1425         }
1426         if (use_pci_vector())
1427                 printk(KERN_INFO "Using vector-based indexing\n");
1428         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1429         for (i = 0; i < NR_IRQS; i++) {
1430                 struct irq_pin_list *entry = irq_2_pin + i;
1431                 if (entry->pin < 0)
1432                         continue;
1433                 if (use_pci_vector() && !platform_legacy_irq(i))
1434                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1435                 else
1436                         printk(KERN_DEBUG "IRQ%d ", i);
1437                 for (;;) {
1438                         printk("-> %d:%d", entry->apic, entry->pin);
1439                         if (!entry->next)
1440                                 break;
1441                         entry = irq_2_pin + entry->next;
1442                 }
1443                 printk("\n");
1444         }
1445
1446         printk(KERN_INFO ".................................... done.\n");
1447
1448         return;
1449 }
1450
1451 static void print_APIC_bitfield (int base)
1452 {
1453         unsigned int v;
1454         int i, j;
1455
1456         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1457         for (i = 0; i < 8; i++) {
1458                 v = apic_read(base + i*0x10);
1459                 for (j = 0; j < 32; j++) {
1460                         if (v & (1<<j))
1461                                 printk("1");
1462                         else
1463                                 printk("0");
1464                 }
1465                 printk("\n");
1466         }
1467 }
1468
1469 void /*__init*/ print_local_APIC(void * dummy)
1470 {
1471         unsigned int v, ver, maxlvt;
1472
1473         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1474                 smp_processor_id(), hard_smp_processor_id());
1475         v = apic_read(APIC_ID);
1476         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1477         v = apic_read(APIC_LVR);
1478         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1479         ver = GET_APIC_VERSION(v);
1480         maxlvt = get_maxlvt();
1481
1482         v = apic_read(APIC_TASKPRI);
1483         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1484
1485         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1486                 v = apic_read(APIC_ARBPRI);
1487                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1488                         v & APIC_ARBPRI_MASK);
1489                 v = apic_read(APIC_PROCPRI);
1490                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1491         }
1492
1493         v = apic_read(APIC_EOI);
1494         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1495         v = apic_read(APIC_RRR);
1496         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1497         v = apic_read(APIC_LDR);
1498         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1499         v = apic_read(APIC_DFR);
1500         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1501         v = apic_read(APIC_SPIV);
1502         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1503
1504         printk(KERN_DEBUG "... APIC ISR field:\n");
1505         print_APIC_bitfield(APIC_ISR);
1506         printk(KERN_DEBUG "... APIC TMR field:\n");
1507         print_APIC_bitfield(APIC_TMR);
1508         printk(KERN_DEBUG "... APIC IRR field:\n");
1509         print_APIC_bitfield(APIC_IRR);
1510
1511         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1512                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1513                         apic_write(APIC_ESR, 0);
1514                 v = apic_read(APIC_ESR);
1515                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1516         }
1517
1518         v = apic_read(APIC_ICR);
1519         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1520         v = apic_read(APIC_ICR2);
1521         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1522
1523         v = apic_read(APIC_LVTT);
1524         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1525
1526         if (maxlvt > 3) {                       /* PC is LVT#4. */
1527                 v = apic_read(APIC_LVTPC);
1528                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1529         }
1530         v = apic_read(APIC_LVT0);
1531         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1532         v = apic_read(APIC_LVT1);
1533         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1534
1535         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1536                 v = apic_read(APIC_LVTERR);
1537                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1538         }
1539
1540         v = apic_read(APIC_TMICT);
1541         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1542         v = apic_read(APIC_TMCCT);
1543         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1544         v = apic_read(APIC_TDCR);
1545         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1546         printk("\n");
1547 }
1548
1549 void print_all_local_APICs (void)
1550 {
1551         on_each_cpu(print_local_APIC, NULL, 1, 1);
1552 }
1553
1554 void /*__init*/ print_PIC(void)
1555 {
1556         extern spinlock_t i8259A_lock;
1557         unsigned int v;
1558         unsigned long flags;
1559
1560         printk(KERN_DEBUG "\nprinting PIC contents\n");
1561
1562         spin_lock_irqsave(&i8259A_lock, flags);
1563
1564         v = inb(0xa1) << 8 | inb(0x21);
1565         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1566
1567         v = inb(0xa0) << 8 | inb(0x20);
1568         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1569
1570         outb(0x0b,0xa0);
1571         outb(0x0b,0x20);
1572         v = inb(0xa0) << 8 | inb(0x20);
1573         outb(0x0a,0xa0);
1574         outb(0x0a,0x20);
1575
1576         spin_unlock_irqrestore(&i8259A_lock, flags);
1577
1578         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1579
1580         v = inb(0x4d1) << 8 | inb(0x4d0);
1581         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1582 }
1583
1584 static void __init enable_IO_APIC(void)
1585 {
1586         union IO_APIC_reg_01 reg_01;
1587         int i;
1588         unsigned long flags;
1589
1590         for (i = 0; i < PIN_MAP_SIZE; i++) {
1591                 irq_2_pin[i].pin = -1;
1592                 irq_2_pin[i].next = 0;
1593         }
1594         if (!pirqs_enabled)
1595                 for (i = 0; i < MAX_PIRQS; i++)
1596                         pirq_entries[i] = -1;
1597
1598         /*
1599          * The number of IO-APIC IRQ registers (== #pins):
1600          */
1601         for (i = 0; i < nr_ioapics; i++) {
1602                 spin_lock_irqsave(&ioapic_lock, flags);
1603                 reg_01.raw = io_apic_read(i, 1);
1604                 spin_unlock_irqrestore(&ioapic_lock, flags);
1605                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1606         }
1607
1608         /*
1609          * Do not trust the IO-APIC being empty at bootup
1610          */
1611         clear_IO_APIC();
1612 }
1613
1614 /*
1615  * Not an __init, needed by the reboot code
1616  */
1617 void disable_IO_APIC(void)
1618 {
1619         /*
1620          * Clear the IO-APIC before rebooting:
1621          */
1622         clear_IO_APIC();
1623
1624         disconnect_bsp_APIC();
1625 }
1626
1627 /*
1628  * function to set the IO-APIC physical IDs based on the
1629  * values stored in the MPC table.
1630  *
1631  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1632  */
1633
1634 #ifndef CONFIG_X86_NUMAQ
1635 static void __init setup_ioapic_ids_from_mpc(void)
1636 {
1637         union IO_APIC_reg_00 reg_00;
1638         physid_mask_t phys_id_present_map;
1639         int apic;
1640         int i;
1641         unsigned char old_id;
1642         unsigned long flags;
1643
1644         /*
1645          * This is broken; anything with a real cpu count has to
1646          * circumvent this idiocy regardless.
1647          */
1648         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1649
1650         /*
1651          * Set the IOAPIC ID to the value stored in the MPC table.
1652          */
1653         for (apic = 0; apic < nr_ioapics; apic++) {
1654
1655                 /* Read the register 0 value */
1656                 spin_lock_irqsave(&ioapic_lock, flags);
1657                 reg_00.raw = io_apic_read(apic, 0);
1658                 spin_unlock_irqrestore(&ioapic_lock, flags);
1659
1660                 old_id = mp_ioapics[apic].mpc_apicid;
1661
1662                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1663                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1664                                 apic, mp_ioapics[apic].mpc_apicid);
1665                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1666                                 reg_00.bits.ID);
1667                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1668                 }
1669
1670                 /* Don't check I/O APIC IDs for some xAPIC systems.  They have
1671                  * no meaning without the serial APIC bus. */
1672                 if (NO_IOAPIC_CHECK)
1673                         continue;
1674                 /*
1675                  * Sanity check, is the ID really free? Every APIC in a
1676                  * system must have a unique ID or we get lots of nice
1677                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1678                  */
1679                 if (check_apicid_used(phys_id_present_map,
1680                                         mp_ioapics[apic].mpc_apicid)) {
1681                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1682                                 apic, mp_ioapics[apic].mpc_apicid);
1683                         for (i = 0; i < get_physical_broadcast(); i++)
1684                                 if (!physid_isset(i, phys_id_present_map))
1685                                         break;
1686                         if (i >= get_physical_broadcast())
1687                                 panic("Max APIC ID exceeded!\n");
1688                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1689                                 i);
1690                         physid_set(i, phys_id_present_map);
1691                         mp_ioapics[apic].mpc_apicid = i;
1692                 } else {
1693                         physid_mask_t tmp;
1694                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1695                         printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1696                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1697                 }
1698
1699
1700                 /*
1701                  * We need to adjust the IRQ routing table
1702                  * if the ID changed.
1703                  */
1704                 if (old_id != mp_ioapics[apic].mpc_apicid)
1705                         for (i = 0; i < mp_irq_entries; i++)
1706                                 if (mp_irqs[i].mpc_dstapic == old_id)
1707                                         mp_irqs[i].mpc_dstapic
1708                                                 = mp_ioapics[apic].mpc_apicid;
1709
1710                 /*
1711                  * Read the right value from the MPC table and
1712                  * write it into the ID register.
1713                  */
1714                 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1715                                         mp_ioapics[apic].mpc_apicid);
1716
1717                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1718                 spin_lock_irqsave(&ioapic_lock, flags);
1719                 io_apic_write(apic, 0, reg_00.raw);
1720                 spin_unlock_irqrestore(&ioapic_lock, flags);
1721
1722                 /*
1723                  * Sanity check
1724                  */
1725                 spin_lock_irqsave(&ioapic_lock, flags);
1726                 reg_00.raw = io_apic_read(apic, 0);
1727                 spin_unlock_irqrestore(&ioapic_lock, flags);
1728                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1729                         printk("could not set ID!\n");
1730                 else
1731                         printk(" ok.\n");
1732         }
1733 }
1734 #else
1735 static void __init setup_ioapic_ids_from_mpc(void) { }
1736 #endif
1737
1738 /*
1739  * There is a nasty bug in some older SMP boards, their mptable lies
1740  * about the timer IRQ. We do the following to work around the situation:
1741  *
1742  *      - timer IRQ defaults to IO-APIC IRQ
1743  *      - if this function detects that timer IRQs are defunct, then we fall
1744  *        back to ISA timer IRQs
1745  */
1746 static int __init timer_irq_works(void)
1747 {
1748         unsigned long t1 = jiffies;
1749
1750         local_irq_enable();
1751         /* Let ten ticks pass... */
1752         mdelay((10 * 1000) / HZ);
1753
1754         /*
1755          * Expect a few ticks at least, to be sure some possible
1756          * glue logic does not lock up after one or two first
1757          * ticks in a non-ExtINT mode.  Also the local APIC
1758          * might have cached one ExtINT interrupt.  Finally, at
1759          * least one tick may be lost due to delays.
1760          */
1761         if (jiffies - t1 > 4)
1762                 return 1;
1763
1764         return 0;
1765 }
1766
1767 /*
1768  * In the SMP+IOAPIC case it might happen that there are an unspecified
1769  * number of pending IRQ events unhandled. These cases are very rare,
1770  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1771  * better to do it this way as thus we do not have to be aware of
1772  * 'pending' interrupts in the IRQ path, except at this point.
1773  */
1774 /*
1775  * Edge triggered needs to resend any interrupt
1776  * that was delayed but this is now handled in the device
1777  * independent code.
1778  */
1779
1780 /*
1781  * Starting up a edge-triggered IO-APIC interrupt is
1782  * nasty - we need to make sure that we get the edge.
1783  * If it is already asserted for some reason, we need
1784  * return 1 to indicate that is was pending.
1785  *
1786  * This is not complete - we should be able to fake
1787  * an edge even if it isn't on the 8259A...
1788  */
1789 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1790 {
1791         int was_pending = 0;
1792         unsigned long flags;
1793
1794         spin_lock_irqsave(&ioapic_lock, flags);
1795         if (irq < 16) {
1796                 disable_8259A_irq(irq);
1797                 if (i8259A_irq_pending(irq))
1798                         was_pending = 1;
1799         }
1800         __unmask_IO_APIC_irq(irq);
1801         spin_unlock_irqrestore(&ioapic_lock, flags);
1802
1803         return was_pending;
1804 }
1805
1806 /*
1807  * Once we have recorded IRQ_PENDING already, we can mask the
1808  * interrupt for real. This prevents IRQ storms from unhandled
1809  * devices.
1810  */
1811 static void ack_edge_ioapic_irq(unsigned int irq)
1812 {
1813         move_irq(irq);
1814         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1815                                         == (IRQ_PENDING | IRQ_DISABLED))
1816                 mask_IO_APIC_irq(irq);
1817         ack_APIC_irq();
1818 }
1819
1820 /*
1821  * Level triggered interrupts can just be masked,
1822  * and shutting down and starting up the interrupt
1823  * is the same as enabling and disabling them -- except
1824  * with a startup need to return a "was pending" value.
1825  *
1826  * Level triggered interrupts are special because we
1827  * do not touch any IO-APIC register while handling
1828  * them. We ack the APIC in the end-IRQ handler, not
1829  * in the start-IRQ-handler. Protection against reentrance
1830  * from the same interrupt is still provided, both by the
1831  * generic IRQ layer and by the fact that an unacked local
1832  * APIC does not accept IRQs.
1833  */
1834 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1835 {
1836         unmask_IO_APIC_irq(irq);
1837
1838         return 0; /* don't check for pending */
1839 }
1840
1841 static void end_level_ioapic_irq (unsigned int irq)
1842 {
1843         unsigned long v;
1844         int i;
1845
1846         move_irq(irq);
1847 /*
1848  * It appears there is an erratum which affects at least version 0x11
1849  * of I/O APIC (that's the 82093AA and cores integrated into various
1850  * chipsets).  Under certain conditions a level-triggered interrupt is
1851  * erroneously delivered as edge-triggered one but the respective IRR
1852  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1853  * message but it will never arrive and further interrupts are blocked
1854  * from the source.  The exact reason is so far unknown, but the
1855  * phenomenon was observed when two consecutive interrupt requests
1856  * from a given source get delivered to the same CPU and the source is
1857  * temporarily disabled in between.
1858  *
1859  * A workaround is to simulate an EOI message manually.  We achieve it
1860  * by setting the trigger mode to edge and then to level when the edge
1861  * trigger mode gets detected in the TMR of a local APIC for a
1862  * level-triggered interrupt.  We mask the source for the time of the
1863  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1864  * The idea is from Manfred Spraul.  --macro
1865  */
1866         i = IO_APIC_VECTOR(irq);
1867
1868         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1869
1870         ack_APIC_irq();
1871
1872         if (!(v & (1 << (i & 0x1f)))) {
1873 #ifdef APIC_MISMATCH_DEBUG
1874                 atomic_inc(&irq_mis_count);
1875 #endif
1876                 spin_lock(&ioapic_lock);
1877                 __mask_and_edge_IO_APIC_irq(irq);
1878                 __unmask_and_level_IO_APIC_irq(irq);
1879                 spin_unlock(&ioapic_lock);
1880         }
1881 }
1882
1883 #ifdef CONFIG_PCI_MSI
1884 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1885 {
1886         int irq = vector_to_irq(vector);
1887
1888         return startup_edge_ioapic_irq(irq);
1889 }
1890
1891 static void ack_edge_ioapic_vector(unsigned int vector)
1892 {
1893         int irq = vector_to_irq(vector);
1894
1895         ack_edge_ioapic_irq(irq);
1896 }
1897
1898 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1899 {
1900         int irq = vector_to_irq(vector);
1901
1902         return startup_level_ioapic_irq (irq);
1903 }
1904
1905 static void end_level_ioapic_vector (unsigned int vector)
1906 {
1907         int irq = vector_to_irq(vector);
1908
1909         end_level_ioapic_irq(irq);
1910 }
1911
1912 static void mask_IO_APIC_vector (unsigned int vector)
1913 {
1914         int irq = vector_to_irq(vector);
1915
1916         mask_IO_APIC_irq(irq);
1917 }
1918
1919 static void unmask_IO_APIC_vector (unsigned int vector)
1920 {
1921         int irq = vector_to_irq(vector);
1922
1923         unmask_IO_APIC_irq(irq);
1924 }
1925
1926 static void set_ioapic_affinity_vector (unsigned int vector,
1927                                         cpumask_t cpu_mask)
1928 {
1929         int irq = vector_to_irq(vector);
1930
1931         set_ioapic_affinity_irq(irq, cpu_mask);
1932 }
1933 #endif
1934
1935 /*
1936  * Level and edge triggered IO-APIC interrupts need different handling,
1937  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1938  * handled with the level-triggered descriptor, but that one has slightly
1939  * more overhead. Level-triggered interrupts cannot be handled with the
1940  * edge-triggered handler, without risking IRQ storms and other ugly
1941  * races.
1942  */
1943 static struct hw_interrupt_type ioapic_edge_type = {
1944         .typename       = "IO-APIC-edge",
1945         .startup        = startup_edge_ioapic,
1946         .shutdown       = shutdown_edge_ioapic,
1947         .enable         = enable_edge_ioapic,
1948         .disable        = disable_edge_ioapic,
1949         .ack            = ack_edge_ioapic,
1950         .end            = end_edge_ioapic,
1951         .set_affinity   = set_ioapic_affinity,
1952 };
1953
1954 static struct hw_interrupt_type ioapic_level_type = {
1955         .typename       = "IO-APIC-level",
1956         .startup        = startup_level_ioapic,
1957         .shutdown       = shutdown_level_ioapic,
1958         .enable         = enable_level_ioapic,
1959         .disable        = disable_level_ioapic,
1960         .ack            = mask_and_ack_level_ioapic,
1961         .end            = end_level_ioapic,
1962         .set_affinity   = set_ioapic_affinity,
1963 };
1964
1965 static inline void init_IO_APIC_traps(void)
1966 {
1967         int irq;
1968
1969         /*
1970          * NOTE! The local APIC isn't very good at handling
1971          * multiple interrupts at the same interrupt level.
1972          * As the interrupt level is determined by taking the
1973          * vector number and shifting that right by 4, we
1974          * want to spread these out a bit so that they don't
1975          * all fall in the same interrupt level.
1976          *
1977          * Also, we've got to be careful not to trash gate
1978          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1979          */
1980         for (irq = 0; irq < NR_IRQS ; irq++) {
1981                 int tmp = irq;
1982                 if (use_pci_vector()) {
1983                         if (!platform_legacy_irq(tmp))
1984                                 if ((tmp = vector_to_irq(tmp)) == -1)
1985                                         continue;
1986                 }
1987                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1988                         /*
1989                          * Hmm.. We don't have an entry for this,
1990                          * so default to an old-fashioned 8259
1991                          * interrupt if we can..
1992                          */
1993                         if (irq < 16)
1994                                 make_8259A_irq(irq);
1995                         else
1996                                 /* Strange. Oh, well.. */
1997                                 irq_desc[irq].handler = &no_irq_type;
1998                 }
1999         }
2000 }
2001
2002 static void enable_lapic_irq (unsigned int irq)
2003 {
2004         unsigned long v;
2005
2006         v = apic_read(APIC_LVT0);
2007         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2008 }
2009
2010 static void disable_lapic_irq (unsigned int irq)
2011 {
2012         unsigned long v;
2013
2014         v = apic_read(APIC_LVT0);
2015         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2016 }
2017
2018 static void ack_lapic_irq (unsigned int irq)
2019 {
2020         ack_APIC_irq();
2021 }
2022
2023 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2024
2025 static struct hw_interrupt_type lapic_irq_type = {
2026         .typename       = "local-APIC-edge",
2027         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2028         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2029         .enable         = enable_lapic_irq,
2030         .disable        = disable_lapic_irq,
2031         .ack            = ack_lapic_irq,
2032         .end            = end_lapic_irq
2033 };
2034
2035 static void setup_nmi (void)
2036 {
2037         /*
2038          * Dirty trick to enable the NMI watchdog ...
2039          * We put the 8259A master into AEOI mode and
2040          * unmask on all local APICs LVT0 as NMI.
2041          *
2042          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2043          * is from Maciej W. Rozycki - so we do not have to EOI from
2044          * the NMI handler or the timer interrupt.
2045          */
2046         printk(KERN_INFO "activating NMI Watchdog ...");
2047
2048         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2049
2050         printk(" done.\n");
2051 }
2052
2053 /*
2054  * This looks a bit hackish but it's about the only one way of sending
2055  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2056  * not support the ExtINT mode, unfortunately.  We need to send these
2057  * cycles as some i82489DX-based boards have glue logic that keeps the
2058  * 8259A interrupt line asserted until INTA.  --macro
2059  */
2060 static inline void unlock_ExtINT_logic(void)
2061 {
2062         int pin, i;
2063         struct IO_APIC_route_entry entry0, entry1;
2064         unsigned char save_control, save_freq_select;
2065         unsigned long flags;
2066
2067         pin = find_isa_irq_pin(8, mp_INT);
2068         if (pin == -1)
2069                 return;
2070
2071         spin_lock_irqsave(&ioapic_lock, flags);
2072         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2073         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2074         spin_unlock_irqrestore(&ioapic_lock, flags);
2075         clear_IO_APIC_pin(0, pin);
2076
2077         memset(&entry1, 0, sizeof(entry1));
2078
2079         entry1.dest_mode = 0;                   /* physical delivery */
2080         entry1.mask = 0;                        /* unmask IRQ now */
2081         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2082         entry1.delivery_mode = dest_ExtINT;
2083         entry1.polarity = entry0.polarity;
2084         entry1.trigger = 0;
2085         entry1.vector = 0;
2086
2087         spin_lock_irqsave(&ioapic_lock, flags);
2088         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2089         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2090         spin_unlock_irqrestore(&ioapic_lock, flags);
2091
2092         save_control = CMOS_READ(RTC_CONTROL);
2093         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2094         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2095                    RTC_FREQ_SELECT);
2096         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2097
2098         i = 100;
2099         while (i-- > 0) {
2100                 mdelay(10);
2101                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2102                         i -= 10;
2103         }
2104
2105         CMOS_WRITE(save_control, RTC_CONTROL);
2106         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2107         clear_IO_APIC_pin(0, pin);
2108
2109         spin_lock_irqsave(&ioapic_lock, flags);
2110         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2111         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2112         spin_unlock_irqrestore(&ioapic_lock, flags);
2113 }
2114
2115 /*
2116  * This code may look a bit paranoid, but it's supposed to cooperate with
2117  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2118  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2119  * fanatically on his truly buggy board.
2120  */
2121 static inline void check_timer(void)
2122 {
2123         int pin1, pin2;
2124         int vector;
2125
2126         /*
2127          * get/set the timer IRQ vector:
2128          */
2129         disable_8259A_irq(0);
2130         vector = assign_irq_vector(0);
2131         set_intr_gate(vector, interrupt[0]);
2132
2133         /*
2134          * Subtle, code in do_timer_interrupt() expects an AEOI
2135          * mode for the 8259A whenever interrupts are routed
2136          * through I/O APICs.  Also IRQ0 has to be enabled in
2137          * the 8259A which implies the virtual wire has to be
2138          * disabled in the local APIC.
2139          */
2140         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2141         init_8259A(1);
2142         timer_ack = 1;
2143         enable_8259A_irq(0);
2144
2145         pin1 = find_isa_irq_pin(0, mp_INT);
2146         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2147
2148         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2149
2150         if (pin1 != -1) {
2151                 /*
2152                  * Ok, does IRQ0 through the IOAPIC work?
2153                  */
2154                 unmask_IO_APIC_irq(0);
2155                 if (timer_irq_works()) {
2156                         if (nmi_watchdog == NMI_IO_APIC) {
2157                                 disable_8259A_irq(0);
2158                                 setup_nmi();
2159                                 enable_8259A_irq(0);
2160                                 check_nmi_watchdog();
2161                         }
2162                         return;
2163                 }
2164                 clear_IO_APIC_pin(0, pin1);
2165                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2166         }
2167
2168         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2169         if (pin2 != -1) {
2170                 printk("\n..... (found pin %d) ...", pin2);
2171                 /*
2172                  * legacy devices should be connected to IO APIC #0
2173                  */
2174                 setup_ExtINT_IRQ0_pin(pin2, vector);
2175                 if (timer_irq_works()) {
2176                         printk("works.\n");
2177                         if (pin1 != -1)
2178                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2179                         else
2180                                 add_pin_to_irq(0, 0, pin2);
2181                         if (nmi_watchdog == NMI_IO_APIC) {
2182                                 setup_nmi();
2183                                 check_nmi_watchdog();
2184                         }
2185                         return;
2186                 }
2187                 /*
2188                  * Cleanup, just in case ...
2189                  */
2190                 clear_IO_APIC_pin(0, pin2);
2191         }
2192         printk(" failed.\n");
2193
2194         if (nmi_watchdog == NMI_IO_APIC) {
2195                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2196                 nmi_watchdog = 0;
2197         }
2198
2199         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2200
2201         disable_8259A_irq(0);
2202         irq_desc[0].handler = &lapic_irq_type;
2203         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2204         enable_8259A_irq(0);
2205
2206         if (timer_irq_works()) {
2207                 printk(" works.\n");
2208                 return;
2209         }
2210         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2211         printk(" failed.\n");
2212
2213         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2214
2215         timer_ack = 0;
2216         init_8259A(0);
2217         make_8259A_irq(0);
2218         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2219
2220         unlock_ExtINT_logic();
2221
2222         if (timer_irq_works()) {
2223                 printk(" works.\n");
2224                 return;
2225         }
2226         printk(" failed :(.\n");
2227         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
2228 }
2229
2230 /*
2231  *
2232  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2233  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2234  *   Linux doesn't really care, as it's not actually used
2235  *   for any interrupt handling anyway.
2236  */
2237 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2238
2239 void __init setup_IO_APIC(void)
2240 {
2241         enable_IO_APIC();
2242
2243         if (acpi_ioapic)
2244                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2245         else
2246                 io_apic_irqs = ~PIC_IRQS;
2247
2248         printk("ENABLING IO-APIC IRQs\n");
2249
2250         /*
2251          * Set up IO-APIC IRQ routing.
2252          */
2253         if (!acpi_ioapic)
2254                 setup_ioapic_ids_from_mpc();
2255         sync_Arb_IDs();
2256         setup_IO_APIC_irqs();
2257         init_IO_APIC_traps();
2258         check_timer();
2259         if (!acpi_ioapic)
2260                 print_IO_APIC();
2261 }
2262
2263 /*
2264  *      Called after all the initialization is done. If we didnt find any
2265  *      APIC bugs then we can allow the modify fast path
2266  */
2267
2268 static int __init io_apic_bug_finalize(void)
2269 {
2270         if(sis_apic_bug == -1)
2271                 sis_apic_bug = 0;
2272         return 0;
2273 }
2274
2275 late_initcall(io_apic_bug_finalize);
2276
2277 struct sysfs_ioapic_data {
2278         struct sys_device dev;
2279         struct IO_APIC_route_entry entry[0];
2280 };
2281 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2282
2283 static int ioapic_suspend(struct sys_device *dev, u32 state)
2284 {
2285         struct IO_APIC_route_entry *entry;
2286         struct sysfs_ioapic_data *data;
2287         unsigned long flags;
2288         int i;
2289
2290         data = container_of(dev, struct sysfs_ioapic_data, dev);
2291         entry = data->entry;
2292         spin_lock_irqsave(&ioapic_lock, flags);
2293         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2294                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2295                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2296         }
2297         spin_unlock_irqrestore(&ioapic_lock, flags);
2298
2299         return 0;
2300 }
2301
2302 static int ioapic_resume(struct sys_device *dev)
2303 {
2304         struct IO_APIC_route_entry *entry;
2305         struct sysfs_ioapic_data *data;
2306         unsigned long flags;
2307         union IO_APIC_reg_00 reg_00;
2308         int i;
2309
2310         data = container_of(dev, struct sysfs_ioapic_data, dev);
2311         entry = data->entry;
2312
2313         spin_lock_irqsave(&ioapic_lock, flags);
2314         reg_00.raw = io_apic_read(dev->id, 0);
2315         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2316                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2317                 io_apic_write(dev->id, 0, reg_00.raw);
2318         }
2319         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2320                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2321                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2322         }
2323         spin_unlock_irqrestore(&ioapic_lock, flags);
2324
2325         return 0;
2326 }
2327
2328 static struct sysdev_class ioapic_sysdev_class = {
2329         set_kset_name("ioapic"),
2330         .suspend = ioapic_suspend,
2331         .resume = ioapic_resume,
2332 };
2333
2334 static int __init ioapic_init_sysfs(void)
2335 {
2336         struct sys_device * dev;
2337         int i, size, error = 0;
2338
2339         error = sysdev_class_register(&ioapic_sysdev_class);
2340         if (error)
2341                 return error;
2342
2343         for (i = 0; i < nr_ioapics; i++ ) {
2344                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2345                         * sizeof(struct IO_APIC_route_entry);
2346                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2347                 if (!mp_ioapic_data[i]) {
2348                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2349                         continue;
2350                 }
2351                 memset(mp_ioapic_data[i], 0, size);
2352                 dev = &mp_ioapic_data[i]->dev;
2353                 dev->id = i;
2354                 dev->cls = &ioapic_sysdev_class;
2355                 error = sysdev_register(dev);
2356                 if (error) {
2357                         kfree(mp_ioapic_data[i]);
2358                         mp_ioapic_data[i] = NULL;
2359                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2360                         continue;
2361                 }
2362         }
2363
2364         return 0;
2365 }
2366
2367 device_initcall(ioapic_init_sysfs);
2368
2369 /* --------------------------------------------------------------------------
2370                           ACPI-based IOAPIC Configuration
2371    -------------------------------------------------------------------------- */
2372
2373 #ifdef CONFIG_ACPI_BOOT
2374
2375 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2376 {
2377         union IO_APIC_reg_00 reg_00;
2378         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2379         physid_mask_t tmp;
2380         unsigned long flags;
2381         int i = 0;
2382
2383         /*
2384          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2385          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2386          * supports up to 16 on one shared APIC bus.
2387          *
2388          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2389          *      advantage of new APIC bus architecture.
2390          */
2391
2392         if (physids_empty(apic_id_map))
2393                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2394
2395         spin_lock_irqsave(&ioapic_lock, flags);
2396         reg_00.raw = io_apic_read(ioapic, 0);
2397         spin_unlock_irqrestore(&ioapic_lock, flags);
2398
2399         if (apic_id >= get_physical_broadcast()) {
2400                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2401                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2402                 apic_id = reg_00.bits.ID;
2403         }
2404
2405         /*
2406          * Every APIC in a system must have a unique ID or we get lots of nice
2407          * 'stuck on smp_invalidate_needed IPI wait' messages.
2408          */
2409         if (check_apicid_used(apic_id_map, apic_id)) {
2410
2411                 for (i = 0; i < get_physical_broadcast(); i++) {
2412                         if (!check_apicid_used(apic_id_map, i))
2413                                 break;
2414                 }
2415
2416                 if (i == get_physical_broadcast())
2417                         panic("Max apic_id exceeded!\n");
2418
2419                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2420                         "trying %d\n", ioapic, apic_id, i);
2421
2422                 apic_id = i;
2423         }
2424
2425         tmp = apicid_to_cpu_present(apic_id);
2426         physids_or(apic_id_map, apic_id_map, tmp);
2427
2428         if (reg_00.bits.ID != apic_id) {
2429                 reg_00.bits.ID = apic_id;
2430
2431                 spin_lock_irqsave(&ioapic_lock, flags);
2432                 io_apic_write(ioapic, 0, reg_00.raw);
2433                 reg_00.raw = io_apic_read(ioapic, 0);
2434                 spin_unlock_irqrestore(&ioapic_lock, flags);
2435
2436                 /* Sanity check */
2437                 if (reg_00.bits.ID != apic_id)
2438                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2439         }
2440
2441         printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2442
2443         return apic_id;
2444 }
2445
2446
2447 int __init io_apic_get_version (int ioapic)
2448 {
2449         union IO_APIC_reg_01    reg_01;
2450         unsigned long flags;
2451
2452         spin_lock_irqsave(&ioapic_lock, flags);
2453         reg_01.raw = io_apic_read(ioapic, 1);
2454         spin_unlock_irqrestore(&ioapic_lock, flags);
2455
2456         return reg_01.bits.version;
2457 }
2458
2459
2460 int __init io_apic_get_redir_entries (int ioapic)
2461 {
2462         union IO_APIC_reg_01    reg_01;
2463         unsigned long flags;
2464
2465         spin_lock_irqsave(&ioapic_lock, flags);
2466         reg_01.raw = io_apic_read(ioapic, 1);
2467         spin_unlock_irqrestore(&ioapic_lock, flags);
2468
2469         return reg_01.bits.entries;
2470 }
2471
2472
2473 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2474 {
2475         struct IO_APIC_route_entry entry;
2476         unsigned long flags;
2477
2478         if (!IO_APIC_IRQ(irq)) {
2479                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2480                         ioapic);
2481                 return -EINVAL;
2482         }
2483
2484         /*
2485          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2486          * Note that we mask (disable) IRQs now -- these get enabled when the
2487          * corresponding device driver registers for this IRQ.
2488          */
2489
2490         memset(&entry,0,sizeof(entry));
2491
2492         entry.delivery_mode = INT_DELIVERY_MODE;
2493         entry.dest_mode = INT_DEST_MODE;
2494         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2495         entry.trigger = edge_level;
2496         entry.polarity = active_high_low;
2497         entry.mask  = 1;
2498
2499         /*
2500          * IRQs < 16 are already in the irq_2_pin[] map
2501          */
2502         if (irq >= 16)
2503                 add_pin_to_irq(irq, ioapic, pin);
2504
2505         entry.vector = assign_irq_vector(irq);
2506
2507         Dprintk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2508                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2509                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
2510
2511         if (use_pci_vector() && !platform_legacy_irq(irq))
2512                 irq = IO_APIC_VECTOR(irq);
2513         if (edge_level) {
2514                 irq_desc[irq].handler = &ioapic_level_type;
2515         } else {
2516                 irq_desc[irq].handler = &ioapic_edge_type;
2517         }
2518
2519         set_intr_gate(entry.vector, interrupt[irq]);
2520
2521         if (!ioapic && (irq < 16))
2522                 disable_8259A_irq(irq);
2523
2524         spin_lock_irqsave(&ioapic_lock, flags);
2525         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2526         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2527         spin_unlock_irqrestore(&ioapic_lock, flags);
2528
2529         return 0;
2530 }
2531
2532 #endif /*CONFIG_ACPI_BOOT*/