drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *best_clock);
  90
  91 static bool
  92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  93                       int target, int refclk, intel_clock_t *best_clock);
  94 static bool
  95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                            int target, int refclk, intel_clock_t *best_clock);
  97
  98 static inline u32 /* units of 100MHz */
  99 intel_fdi_link_freq(struct drm_device *dev)
 100 {
 101         if (IS_GEN5(dev)) {
 102                 struct drm_i915_private *dev_priv = dev->dev_private;
 103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 104         } else
 105                 return 27;
 106 }
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 2 },
 119         .find_pll = intel_find_best_PLL,
 120 };
 121
 122 static const intel_limit_t intel_limits_i8xx_lvds = {
 123         .dot = { .min = 25000, .max = 350000 },
 124         .vco = { .min = 930000, .max = 1400000 },
 125         .n = { .min = 3, .max = 16 },
 126         .m = { .min = 96, .max = 140 },
 127         .m1 = { .min = 18, .max = 26 },
 128         .m2 = { .min = 6, .max = 16 },
 129         .p = { .min = 4, .max = 128 },
 130         .p1 = { .min = 1, .max = 6 },
 131         .p2 = { .dot_limit = 165000,
 132                 .p2_slow = 14, .p2_fast = 7 },
 133         .find_pll = intel_find_best_PLL,
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 10, .max = 22 },
 142         .m2 = { .min = 5, .max = 9 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147         .find_pll = intel_find_best_PLL,
 148 };
 149
 150 static const intel_limit_t intel_limits_i9xx_lvds = {
 151         .dot = { .min = 20000, .max = 400000 },
 152         .vco = { .min = 1400000, .max = 2800000 },
 153         .n = { .min = 1, .max = 6 },
 154         .m = { .min = 70, .max = 120 },
 155         .m1 = { .min = 10, .max = 22 },
 156         .m2 = { .min = 5, .max = 9 },
 157         .p = { .min = 7, .max = 98 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 112000,
 160                 .p2_slow = 14, .p2_fast = 7 },
 161         .find_pll = intel_find_best_PLL,
 162 };
 163
 164
 165 static const intel_limit_t intel_limits_g4x_sdvo = {
 166         .dot = { .min = 25000, .max = 270000 },
 167         .vco = { .min = 1750000, .max = 3500000},
 168         .n = { .min = 1, .max = 4 },
 169         .m = { .min = 104, .max = 138 },
 170         .m1 = { .min = 17, .max = 23 },
 171         .m2 = { .min = 5, .max = 11 },
 172         .p = { .min = 10, .max = 30 },
 173         .p1 = { .min = 1, .max = 3},
 174         .p2 = { .dot_limit = 270000,
 175                 .p2_slow = 10,
 176                 .p2_fast = 10
 177         },
 178         .find_pll = intel_g4x_find_best_PLL,
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192         .find_pll = intel_g4x_find_best_PLL,
 193 };
 194
 195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 196         .dot = { .min = 20000, .max = 115000 },
 197         .vco = { .min = 1750000, .max = 3500000 },
 198         .n = { .min = 1, .max = 3 },
 199         .m = { .min = 104, .max = 138 },
 200         .m1 = { .min = 17, .max = 23 },
 201         .m2 = { .min = 5, .max = 11 },
 202         .p = { .min = 28, .max = 112 },
 203         .p1 = { .min = 2, .max = 8 },
 204         .p2 = { .dot_limit = 0,
 205                 .p2_slow = 14, .p2_fast = 14
 206         },
 207         .find_pll = intel_g4x_find_best_PLL,
 208 };
 209
 210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 211         .dot = { .min = 80000, .max = 224000 },
 212         .vco = { .min = 1750000, .max = 3500000 },
 213         .n = { .min = 1, .max = 3 },
 214         .m = { .min = 104, .max = 138 },
 215         .m1 = { .min = 17, .max = 23 },
 216         .m2 = { .min = 5, .max = 11 },
 217         .p = { .min = 14, .max = 42 },
 218         .p1 = { .min = 2, .max = 6 },
 219         .p2 = { .dot_limit = 0,
 220                 .p2_slow = 7, .p2_fast = 7
 221         },
 222         .find_pll = intel_g4x_find_best_PLL,
 223 };
 224
 225 static const intel_limit_t intel_limits_g4x_display_port = {
 226         .dot = { .min = 161670, .max = 227000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 2 },
 229         .m = { .min = 97, .max = 108 },
 230         .m1 = { .min = 0x10, .max = 0x12 },
 231         .m2 = { .min = 0x05, .max = 0x06 },
 232         .p = { .min = 10, .max = 20 },
 233         .p1 = { .min = 1, .max = 2},
 234         .p2 = { .dot_limit = 0,
 235                 .p2_slow = 10, .p2_fast = 10 },
 236         .find_pll = intel_find_pll_g4x_dp,
 237 };
 238
 239 static const intel_limit_t intel_limits_pineview_sdvo = {
 240         .dot = { .min = 20000, .max = 400000},
 241         .vco = { .min = 1700000, .max = 3500000 },
 242         /* Pineview's Ncounter is a ring counter */
 243         .n = { .min = 3, .max = 6 },
 244         .m = { .min = 2, .max = 256 },
 245         /* Pineview only has one combined m divider, which we treat as m2. */
 246         .m1 = { .min = 0, .max = 0 },
 247         .m2 = { .min = 0, .max = 254 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8 },
 250         .p2 = { .dot_limit = 200000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252         .find_pll = intel_find_best_PLL,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         .n = { .min = 3, .max = 6 },
 259         .m = { .min = 2, .max = 256 },
 260         .m1 = { .min = 0, .max = 0 },
 261         .m2 = { .min = 0, .max = 254 },
 262         .p = { .min = 7, .max = 112 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 14 },
 266         .find_pll = intel_find_best_PLL,
 267 };
 268
 269 /* Ironlake / Sandybridge
 270  *
 271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 272  * the range value for them is (actual_value - 2).
 273  */
 274 static const intel_limit_t intel_limits_ironlake_dac = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 5 },
 278         .m = { .min = 79, .max = 127 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285         .find_pll = intel_g4x_find_best_PLL,
 286 };
 287
 288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 1760000, .max = 3510000 },
 291         .n = { .min = 1, .max = 3 },
 292         .m = { .min = 79, .max = 118 },
 293         .m1 = { .min = 12, .max = 22 },
 294         .m2 = { .min = 5, .max = 9 },
 295         .p = { .min = 28, .max = 112 },
 296         .p1 = { .min = 2, .max = 8 },
 297         .p2 = { .dot_limit = 225000,
 298                 .p2_slow = 14, .p2_fast = 14 },
 299         .find_pll = intel_g4x_find_best_PLL,
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 56 },
 310         .p1 = { .min = 2, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313         .find_pll = intel_g4x_find_best_PLL,
 314 };
 315
 316 /* LVDS 100mhz refclk limits. */
 317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 2 },
 321         .m = { .min = 79, .max = 126 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328         .find_pll = intel_g4x_find_best_PLL,
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 126 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 42 },
 339         .p1 = { .min = 2, .max = 6 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342         .find_pll = intel_g4x_find_best_PLL,
 343 };
 344
 345 static const intel_limit_t intel_limits_ironlake_display_port = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000},
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 81, .max = 90 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 10, .max = 20 },
 353         .p1 = { .min = 1, .max = 2},
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 10, .p2_fast = 10 },
 356         .find_pll = intel_find_pll_ironlake_dp,
 357 };
 358
 359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 360                                                 int refclk)
 361 {
 362         struct drm_device *dev = crtc->dev;
 363         struct drm_i915_private *dev_priv = dev->dev_private;
 364         const intel_limit_t *limit;
 365
 366         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 367                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 368                     LVDS_CLKB_POWER_UP) {
 369                         /* LVDS dual channel */
 370                         if (refclk == 100000)
 371                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 372                         else
 373                                 limit = &intel_limits_ironlake_dual_lvds;
 374                 } else {
 375                         if (refclk == 100000)
 376                                 limit = &intel_limits_ironlake_single_lvds_100m;
 377                         else
 378                                 limit = &intel_limits_ironlake_single_lvds;
 379                 }
 380         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 381                         HAS_eDP)
 382                 limit = &intel_limits_ironlake_display_port;
 383         else
 384                 limit = &intel_limits_ironlake_dac;
 385
 386         return limit;
 387 }
 388
 389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 397                     LVDS_CLKB_POWER_UP)
 398                         /* LVDS with dual channel */
 399                         limit = &intel_limits_g4x_dual_channel_lvds;
 400                 else
 401                         /* LVDS with dual channel */
 402                         limit = &intel_limits_g4x_single_channel_lvds;
 403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 405                 limit = &intel_limits_g4x_hdmi;
 406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 407                 limit = &intel_limits_g4x_sdvo;
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 409                 limit = &intel_limits_g4x_display_port;
 410         } else /* The option is for other outputs */
 411                 limit = &intel_limits_i9xx_sdvo;
 412
 413         return limit;
 414 }
 415
 416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 417 {
 418         struct drm_device *dev = crtc->dev;
 419         const intel_limit_t *limit;
 420
 421         if (HAS_PCH_SPLIT(dev))
 422                 limit = intel_ironlake_limit(crtc, refclk);
 423         else if (IS_G4X(dev)) {
 424                 limit = intel_g4x_limit(crtc);
 425         } else if (IS_PINEVIEW(dev)) {
 426                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 427                         limit = &intel_limits_pineview_lvds;
 428                 else
 429                         limit = &intel_limits_pineview_sdvo;
 430         } else if (!IS_GEN2(dev)) {
 431                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 432                         limit = &intel_limits_i9xx_lvds;
 433                 else
 434                         limit = &intel_limits_i9xx_sdvo;
 435         } else {
 436                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 437                         limit = &intel_limits_i8xx_lvds;
 438                 else
 439                         limit = &intel_limits_i8xx_dvo;
 440         }
 441         return limit;
 442 }
 443
 444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 445 static void pineview_clock(int refclk, intel_clock_t *clock)
 446 {
 447         clock->m = clock->m2 + 2;
 448         clock->p = clock->p1 * clock->p2;
 449         clock->vco = refclk * clock->m / clock->n;
 450         clock->dot = clock->vco / clock->p;
 451 }
 452
 453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 454 {
 455         if (IS_PINEVIEW(dev)) {
 456                 pineview_clock(refclk, clock);
 457                 return;
 458         }
 459         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 460         clock->p = clock->p1 * clock->p2;
 461         clock->vco = refclk * clock->m / (clock->n + 2);
 462         clock->dot = clock->vco / clock->p;
 463 }
 464
 465 /**
 466  * Returns whether any output on the specified pipe is of the specified type
 467  */
 468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 469 {
 470         struct drm_device *dev = crtc->dev;
 471         struct drm_mode_config *mode_config = &dev->mode_config;
 472         struct intel_encoder *encoder;
 473
 474         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 475                 if (encoder->base.crtc == crtc && encoder->type == type)
 476                         return true;
 477
 478         return false;
 479 }
 480
 481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 482 /**
 483  * Returns whether the given set of divisors are valid for a given refclk with
 484  * the given connectors.
 485  */
 486
 487 static bool intel_PLL_is_valid(struct drm_device *dev,
 488                                const intel_limit_t *limit,
 489                                const intel_clock_t *clock)
 490 {
 491         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 492                 INTELPllInvalid("p1 out of range\n");
 493         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 494                 INTELPllInvalid("p out of range\n");
 495         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 496                 INTELPllInvalid("m2 out of range\n");
 497         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 498                 INTELPllInvalid("m1 out of range\n");
 499         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 500                 INTELPllInvalid("m1 <= m2\n");
 501         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 502                 INTELPllInvalid("m out of range\n");
 503         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 504                 INTELPllInvalid("n out of range\n");
 505         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 506                 INTELPllInvalid("vco out of range\n");
 507         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 508          * connector, etc., rather than just a single range.
 509          */
 510         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 511                 INTELPllInvalid("dot out of range\n");
 512
 513         return true;
 514 }
 515
 516 static bool
 517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 518                     int target, int refclk, intel_clock_t *best_clock)
 519
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         intel_clock_t clock;
 524         int err = target;
 525
 526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 527             (I915_READ(LVDS)) != 0) {
 528                 /*
 529                  * For LVDS, if the panel is on, just rely on its current
 530                  * settings for dual-channel.  We haven't figured out how to
 531                  * reliably set up different single/dual channel state, if we
 532                  * even can.
 533                  */
 534                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 535                     LVDS_CLKB_POWER_UP)
 536                         clock.p2 = limit->p2.p2_fast;
 537                 else
 538                         clock.p2 = limit->p2.p2_slow;
 539         } else {
 540                 if (target < limit->p2.dot_limit)
 541                         clock.p2 = limit->p2.p2_slow;
 542                 else
 543                         clock.p2 = limit->p2.p2_fast;
 544         }
 545
 546         memset(best_clock, 0, sizeof(*best_clock));
 547
 548         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 549              clock.m1++) {
 550                 for (clock.m2 = limit->m2.min;
 551                      clock.m2 <= limit->m2.max; clock.m2++) {
 552                         /* m1 is always 0 in Pineview */
 553                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 554                                 break;
 555                         for (clock.n = limit->n.min;
 556                              clock.n <= limit->n.max; clock.n++) {
 557                                 for (clock.p1 = limit->p1.min;
 558                                         clock.p1 <= limit->p1.max; clock.p1++) {
 559                                         int this_err;
 560
 561                                         intel_clock(dev, refclk, &clock);
 562                                         if (!intel_PLL_is_valid(dev, limit,
 563                                                                 &clock))
 564                                                 continue;
 565
 566                                         this_err = abs(clock.dot - target);
 567                                         if (this_err < err) {
 568                                                 *best_clock = clock;
 569                                                 err = this_err;
 570                                         }
 571                                 }
 572                         }
 573                 }
 574         }
 575
 576         return (err != target);
 577 }
 578
 579 static bool
 580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 581                         int target, int refclk, intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct drm_i915_private *dev_priv = dev->dev_private;
 585         intel_clock_t clock;
 586         int max_n;
 587         bool found;
 588         /* approximately equals target * 0.00585 */
 589         int err_most = (target >> 8) + (target >> 9);
 590         found = false;
 591
 592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 593                 int lvds_reg;
 594
 595                 if (HAS_PCH_SPLIT(dev))
 596                         lvds_reg = PCH_LVDS;
 597                 else
 598                         lvds_reg = LVDS;
 599                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 600                     LVDS_CLKB_POWER_UP)
 601                         clock.p2 = limit->p2.p2_fast;
 602                 else
 603                         clock.p2 = limit->p2.p2_slow;
 604         } else {
 605                 if (target < limit->p2.dot_limit)
 606                         clock.p2 = limit->p2.p2_slow;
 607                 else
 608                         clock.p2 = limit->p2.p2_fast;
 609         }
 610
 611         memset(best_clock, 0, sizeof(*best_clock));
 612         max_n = limit->n.max;
 613         /* based on hardware requirement, prefer smaller n to precision */
 614         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 615                 /* based on hardware requirement, prefere larger m1,m2 */
 616                 for (clock.m1 = limit->m1.max;
 617                      clock.m1 >= limit->m1.min; clock.m1--) {
 618                         for (clock.m2 = limit->m2.max;
 619                              clock.m2 >= limit->m2.min; clock.m2--) {
 620                                 for (clock.p1 = limit->p1.max;
 621                                      clock.p1 >= limit->p1.min; clock.p1--) {
 622                                         int this_err;
 623
 624                                         intel_clock(dev, refclk, &clock);
 625                                         if (!intel_PLL_is_valid(dev, limit,
 626                                                                 &clock))
 627                                                 continue;
 628
 629                                         this_err = abs(clock.dot - target);
 630                                         if (this_err < err_most) {
 631                                                 *best_clock = clock;
 632                                                 err_most = this_err;
 633                                                 max_n = clock.n;
 634                                                 found = true;
 635                                         }
 636                                 }
 637                         }
 638                 }
 639         }
 640         return found;
 641 }
 642
 643 static bool
 644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 645                            int target, int refclk, intel_clock_t *best_clock)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         intel_clock_t clock;
 649
 650         if (target < 200000) {
 651                 clock.n = 1;
 652                 clock.p1 = 2;
 653                 clock.p2 = 10;
 654                 clock.m1 = 12;
 655                 clock.m2 = 9;
 656         } else {
 657                 clock.n = 2;
 658                 clock.p1 = 1;
 659                 clock.p2 = 10;
 660                 clock.m1 = 14;
 661                 clock.m2 = 8;
 662         }
 663         intel_clock(dev, refclk, &clock);
 664         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 665         return true;
 666 }
 667
 668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 669 static bool
 670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 671                       int target, int refclk, intel_clock_t *best_clock)
 672 {
 673         intel_clock_t clock;
 674         if (target < 200000) {
 675                 clock.p1 = 2;
 676                 clock.p2 = 10;
 677                 clock.n = 2;
 678                 clock.m1 = 23;
 679                 clock.m2 = 8;
 680         } else {
 681                 clock.p1 = 1;
 682                 clock.p2 = 10;
 683                 clock.n = 1;
 684                 clock.m1 = 14;
 685                 clock.m2 = 2;
 686         }
 687         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 688         clock.p = (clock.p1 * clock.p2);
 689         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 690         clock.vco = 0;
 691         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 692         return true;
 693 }
 694
 695 /**
 696  * intel_wait_for_vblank - wait for vblank on a given pipe
 697  * @dev: drm device
 698  * @pipe: pipe to wait for
 699  *
 700  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 701  * mode setting code.
 702  */
 703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         int pipestat_reg = PIPESTAT(pipe);
 707
 708         /* Clear existing vblank status. Note this will clear any other
 709          * sticky status fields as well.
 710          *
 711          * This races with i915_driver_irq_handler() with the result
 712          * that either function could miss a vblank event.  Here it is not
 713          * fatal, as we will either wait upon the next vblank interrupt or
 714          * timeout.  Generally speaking intel_wait_for_vblank() is only
 715          * called during modeset at which time the GPU should be idle and
 716          * should *not* be performing page flips and thus not waiting on
 717          * vblanks...
 718          * Currently, the result of us stealing a vblank from the irq
 719          * handler is that a single frame will be skipped during swapbuffers.
 720          */
 721         I915_WRITE(pipestat_reg,
 722                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 723
 724         /* Wait for vblank interrupt bit to set */
 725         if (wait_for(I915_READ(pipestat_reg) &
 726                      PIPE_VBLANK_INTERRUPT_STATUS,
 727                      50))
 728                 DRM_DEBUG_KMS("vblank wait timed out\n");
 729 }
 730
 731 /*
 732  * intel_wait_for_pipe_off - wait for pipe to turn off
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * After disabling a pipe, we can't wait for vblank in the usual way,
 737  * spinning on the vblank interrupt status bit, since we won't actually
 738  * see an interrupt when the pipe is disabled.
 739  *
 740  * On Gen4 and above:
 741  *   wait for the pipe register state bit to turn off
 742  *
 743  * Otherwise:
 744  *   wait for the display line value to settle (it usually
 745  *   ends up stopping at the start of the next frame).
 746  *
 747  */
 748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 749 {
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751
 752         if (INTEL_INFO(dev)->gen >= 4) {
 753                 int reg = PIPECONF(pipe);
 754
 755                 /* Wait for the Pipe State to go off */
 756                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 757                              100))
 758                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 759         } else {
 760                 u32 last_line;
 761                 int reg = PIPEDSL(pipe);
 762                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 763
 764                 /* Wait for the display line to settle */
 765                 do {
 766                         last_line = I915_READ(reg) & DSL_LINEMASK;
 767                         mdelay(5);
 768                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 769                          time_after(timeout, jiffies));
 770                 if (time_after(jiffies, timeout))
 771                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 772         }
 773 }
 774
 775 static const char *state_string(bool enabled)
 776 {
 777         return enabled ? "on" : "off";
 778 }
 779
 780 /* Only for pre-ILK configs */
 781 static void assert_pll(struct drm_i915_private *dev_priv,
 782                        enum pipe pipe, bool state)
 783 {
 784         int reg;
 785         u32 val;
 786         bool cur_state;
 787
 788         reg = DPLL(pipe);
 789         val = I915_READ(reg);
 790         cur_state = !!(val & DPLL_VCO_ENABLE);
 791         WARN(cur_state != state,
 792              "PLL state assertion failure (expected %s, current %s)\n",
 793              state_string(state), state_string(cur_state));
 794 }
 795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 797
 798 /* For ILK+ */
 799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 800                            enum pipe pipe, bool state)
 801 {
 802         int reg;
 803         u32 val;
 804         bool cur_state;
 805
 806         if (HAS_PCH_CPT(dev_priv->dev)) {
 807                 u32 pch_dpll;
 808
 809                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 810
 811                 /* Make sure the selected PLL is enabled to the transcoder */
 812                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 813                      "transcoder %d PLL not enabled\n", pipe);
 814
 815                 /* Convert the transcoder pipe number to a pll pipe number */
 816                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 817         }
 818
 819         reg = PCH_DPLL(pipe);
 820         val = I915_READ(reg);
 821         cur_state = !!(val & DPLL_VCO_ENABLE);
 822         WARN(cur_state != state,
 823              "PCH PLL state assertion failure (expected %s, current %s)\n",
 824              state_string(state), state_string(cur_state));
 825 }
 826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 828
 829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 830                           enum pipe pipe, bool state)
 831 {
 832         int reg;
 833         u32 val;
 834         bool cur_state;
 835
 836         reg = FDI_TX_CTL(pipe);
 837         val = I915_READ(reg);
 838         cur_state = !!(val & FDI_TX_ENABLE);
 839         WARN(cur_state != state,
 840              "FDI TX state assertion failure (expected %s, current %s)\n",
 841              state_string(state), state_string(cur_state));
 842 }
 843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 845
 846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 847                           enum pipe pipe, bool state)
 848 {
 849         int reg;
 850         u32 val;
 851         bool cur_state;
 852
 853         reg = FDI_RX_CTL(pipe);
 854         val = I915_READ(reg);
 855         cur_state = !!(val & FDI_RX_ENABLE);
 856         WARN(cur_state != state,
 857              "FDI RX state assertion failure (expected %s, current %s)\n",
 858              state_string(state), state_string(cur_state));
 859 }
 860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 862
 863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         /* ILK FDI PLL is always enabled */
 870         if (dev_priv->info->gen == 5)
 871                 return;
 872
 873         reg = FDI_TX_CTL(pipe);
 874         val = I915_READ(reg);
 875         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 876 }
 877
 878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 879                                       enum pipe pipe)
 880 {
 881         int reg;
 882         u32 val;
 883
 884         reg = FDI_RX_CTL(pipe);
 885         val = I915_READ(reg);
 886         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 887 }
 888
 889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 890                                   enum pipe pipe)
 891 {
 892         int pp_reg, lvds_reg;
 893         u32 val;
 894         enum pipe panel_pipe = PIPE_A;
 895         bool locked = true;
 896
 897         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 898                 pp_reg = PCH_PP_CONTROL;
 899                 lvds_reg = PCH_LVDS;
 900         } else {
 901                 pp_reg = PP_CONTROL;
 902                 lvds_reg = LVDS;
 903         }
 904
 905         val = I915_READ(pp_reg);
 906         if (!(val & PANEL_POWER_ON) ||
 907             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 908                 locked = false;
 909
 910         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 911                 panel_pipe = PIPE_B;
 912
 913         WARN(panel_pipe == pipe && locked,
 914              "panel assertion failure, pipe %c regs locked\n",
 915              pipe_name(pipe));
 916 }
 917
 918 void assert_pipe(struct drm_i915_private *dev_priv,
 919                  enum pipe pipe, bool state)
 920 {
 921         int reg;
 922         u32 val;
 923         bool cur_state;
 924
 925         reg = PIPECONF(pipe);
 926         val = I915_READ(reg);
 927         cur_state = !!(val & PIPECONF_ENABLE);
 928         WARN(cur_state != state,
 929              "pipe %c assertion failure (expected %s, current %s)\n",
 930              pipe_name(pipe), state_string(state), state_string(cur_state));
 931 }
 932
 933 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 934                                  enum plane plane)
 935 {
 936         int reg;
 937         u32 val;
 938
 939         reg = DSPCNTR(plane);
 940         val = I915_READ(reg);
 941         WARN(!(val & DISPLAY_PLANE_ENABLE),
 942              "plane %c assertion failure, should be active but is disabled\n",
 943              plane_name(plane));
 944 }
 945
 946 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 947                                    enum pipe pipe)
 948 {
 949         int reg, i;
 950         u32 val;
 951         int cur_pipe;
 952
 953         /* Planes are fixed to pipes on ILK+ */
 954         if (HAS_PCH_SPLIT(dev_priv->dev))
 955                 return;
 956
 957         /* Need to check both planes against the pipe */
 958         for (i = 0; i < 2; i++) {
 959                 reg = DSPCNTR(i);
 960                 val = I915_READ(reg);
 961                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 962                         DISPPLANE_SEL_PIPE_SHIFT;
 963                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 964                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 965                      plane_name(i), pipe_name(pipe));
 966         }
 967 }
 968
 969 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 970 {
 971         u32 val;
 972         bool enabled;
 973
 974         val = I915_READ(PCH_DREF_CONTROL);
 975         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 976                             DREF_SUPERSPREAD_SOURCE_MASK));
 977         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 978 }
 979
 980 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 981                                        enum pipe pipe)
 982 {
 983         int reg;
 984         u32 val;
 985         bool enabled;
 986
 987         reg = TRANSCONF(pipe);
 988         val = I915_READ(reg);
 989         enabled = !!(val & TRANS_ENABLE);
 990         WARN(enabled,
 991              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 992              pipe_name(pipe));
 993 }
 994
 995 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 996                             enum pipe pipe, u32 port_sel, u32 val)
 997 {
 998         if ((val & DP_PORT_EN) == 0)
 999                 return false;
1000
1001         if (HAS_PCH_CPT(dev_priv->dev)) {
1002                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1003                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1004                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1005                         return false;
1006         } else {
1007                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1008                         return false;
1009         }
1010         return true;
1011 }
1012
1013 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1014                               enum pipe pipe, u32 val)
1015 {
1016         if ((val & PORT_ENABLE) == 0)
1017                 return false;
1018
1019         if (HAS_PCH_CPT(dev_priv->dev)) {
1020                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1021                         return false;
1022         } else {
1023                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1024                         return false;
1025         }
1026         return true;
1027 }
1028
1029 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1030                               enum pipe pipe, u32 val)
1031 {
1032         if ((val & LVDS_PORT_EN) == 0)
1033                 return false;
1034
1035         if (HAS_PCH_CPT(dev_priv->dev)) {
1036                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1037                         return false;
1038         } else {
1039                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1040                         return false;
1041         }
1042         return true;
1043 }
1044
1045 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1046                               enum pipe pipe, u32 val)
1047 {
1048         if ((val & ADPA_DAC_ENABLE) == 0)
1049                 return false;
1050         if (HAS_PCH_CPT(dev_priv->dev)) {
1051                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1052                         return false;
1053         } else {
1054                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1055                         return false;
1056         }
1057         return true;
1058 }
1059
1060 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1061                                    enum pipe pipe, int reg, u32 port_sel)
1062 {
1063         u32 val = I915_READ(reg);
1064         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1065              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1066              reg, pipe_name(pipe));
1067 }
1068
1069 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1070                                      enum pipe pipe, int reg)
1071 {
1072         u32 val = I915_READ(reg);
1073         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1074              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1075              reg, pipe_name(pipe));
1076 }
1077
1078 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1079                                       enum pipe pipe)
1080 {
1081         int reg;
1082         u32 val;
1083
1084         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1085         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1086         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1087
1088         reg = PCH_ADPA;
1089         val = I915_READ(reg);
1090         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1091              "PCH VGA enabled on transcoder %c, should be disabled\n",
1092              pipe_name(pipe));
1093
1094         reg = PCH_LVDS;
1095         val = I915_READ(reg);
1096         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1097              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1098              pipe_name(pipe));
1099
1100         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1101         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1102         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1103 }
1104
1105 /**
1106  * intel_enable_pll - enable a PLL
1107  * @dev_priv: i915 private structure
1108  * @pipe: pipe PLL to enable
1109  *
1110  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1111  * make sure the PLL reg is writable first though, since the panel write
1112  * protect mechanism may be enabled.
1113  *
1114  * Note!  This is for pre-ILK only.
1115  */
1116 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1117 {
1118         int reg;
1119         u32 val;
1120
1121         /* No really, not for ILK+ */
1122         BUG_ON(dev_priv->info->gen >= 5);
1123
1124         /* PLL is protected by panel, make sure we can write it */
1125         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1126                 assert_panel_unlocked(dev_priv, pipe);
1127
1128         reg = DPLL(pipe);
1129         val = I915_READ(reg);
1130         val |= DPLL_VCO_ENABLE;
1131
1132         /* We do this three times for luck */
1133         I915_WRITE(reg, val);
1134         POSTING_READ(reg);
1135         udelay(150); /* wait for warmup */
1136         I915_WRITE(reg, val);
1137         POSTING_READ(reg);
1138         udelay(150); /* wait for warmup */
1139         I915_WRITE(reg, val);
1140         POSTING_READ(reg);
1141         udelay(150); /* wait for warmup */
1142 }
1143
1144 /**
1145  * intel_disable_pll - disable a PLL
1146  * @dev_priv: i915 private structure
1147  * @pipe: pipe PLL to disable
1148  *
1149  * Disable the PLL for @pipe, making sure the pipe is off first.
1150  *
1151  * Note!  This is for pre-ILK only.
1152  */
1153 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1154 {
1155         int reg;
1156         u32 val;
1157
1158         /* Don't disable pipe A or pipe A PLLs if needed */
1159         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1160                 return;
1161
1162         /* Make sure the pipe isn't still relying on us */
1163         assert_pipe_disabled(dev_priv, pipe);
1164
1165         reg = DPLL(pipe);
1166         val = I915_READ(reg);
1167         val &= ~DPLL_VCO_ENABLE;
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170 }
1171
1172 /**
1173  * intel_enable_pch_pll - enable PCH PLL
1174  * @dev_priv: i915 private structure
1175  * @pipe: pipe PLL to enable
1176  *
1177  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1178  * drives the transcoder clock.
1179  */
1180 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1181                                  enum pipe pipe)
1182 {
1183         int reg;
1184         u32 val;
1185
1186         if (pipe > 1)
1187                 return;
1188
1189         /* PCH only available on ILK+ */
1190         BUG_ON(dev_priv->info->gen < 5);
1191
1192         /* PCH refclock must be enabled first */
1193         assert_pch_refclk_enabled(dev_priv);
1194
1195         reg = PCH_DPLL(pipe);
1196         val = I915_READ(reg);
1197         val |= DPLL_VCO_ENABLE;
1198         I915_WRITE(reg, val);
1199         POSTING_READ(reg);
1200         udelay(200);
1201 }
1202
1203 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int reg;
1207         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1208                 pll_sel = TRANSC_DPLL_ENABLE;
1209
1210         if (pipe > 1)
1211                 return;
1212
1213         /* PCH only available on ILK+ */
1214         BUG_ON(dev_priv->info->gen < 5);
1215
1216         /* Make sure transcoder isn't still depending on us */
1217         assert_transcoder_disabled(dev_priv, pipe);
1218
1219         if (pipe == 0)
1220                 pll_sel |= TRANSC_DPLLA_SEL;
1221         else if (pipe == 1)
1222                 pll_sel |= TRANSC_DPLLB_SEL;
1223
1224
1225         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1226                 return;
1227
1228         reg = PCH_DPLL(pipe);
1229         val = I915_READ(reg);
1230         val &= ~DPLL_VCO_ENABLE;
1231         I915_WRITE(reg, val);
1232         POSTING_READ(reg);
1233         udelay(200);
1234 }
1235
1236 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1237                                     enum pipe pipe)
1238 {
1239         int reg;
1240         u32 val;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure PCH DPLL is enabled */
1246         assert_pch_pll_enabled(dev_priv, pipe);
1247
1248         /* FDI must be feeding us bits for PCH ports */
1249         assert_fdi_tx_enabled(dev_priv, pipe);
1250         assert_fdi_rx_enabled(dev_priv, pipe);
1251
1252         reg = TRANSCONF(pipe);
1253         val = I915_READ(reg);
1254
1255         if (HAS_PCH_IBX(dev_priv->dev)) {
1256                 /*
1257                  * make the BPC in transcoder be consistent with
1258                  * that in pipeconf reg.
1259                  */
1260                 val &= ~PIPE_BPC_MASK;
1261                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1262         }
1263         I915_WRITE(reg, val | TRANS_ENABLE);
1264         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1265                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1266 }
1267
1268 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1269                                      enum pipe pipe)
1270 {
1271         int reg;
1272         u32 val;
1273
1274         /* FDI relies on the transcoder */
1275         assert_fdi_tx_disabled(dev_priv, pipe);
1276         assert_fdi_rx_disabled(dev_priv, pipe);
1277
1278         /* Ports must be off as well */
1279         assert_pch_ports_disabled(dev_priv, pipe);
1280
1281         reg = TRANSCONF(pipe);
1282         val = I915_READ(reg);
1283         val &= ~TRANS_ENABLE;
1284         I915_WRITE(reg, val);
1285         /* wait for PCH transcoder off, transcoder state */
1286         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1287                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1288 }
1289
1290 /**
1291  * intel_enable_pipe - enable a pipe, asserting requirements
1292  * @dev_priv: i915 private structure
1293  * @pipe: pipe to enable
1294  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1295  *
1296  * Enable @pipe, making sure that various hardware specific requirements
1297  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1298  *
1299  * @pipe should be %PIPE_A or %PIPE_B.
1300  *
1301  * Will wait until the pipe is actually running (i.e. first vblank) before
1302  * returning.
1303  */
1304 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1305                               bool pch_port)
1306 {
1307         int reg;
1308         u32 val;
1309
1310         /*
1311          * A pipe without a PLL won't actually be able to drive bits from
1312          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1313          * need the check.
1314          */
1315         if (!HAS_PCH_SPLIT(dev_priv->dev))
1316                 assert_pll_enabled(dev_priv, pipe);
1317         else {
1318                 if (pch_port) {
1319                         /* if driving the PCH, we need FDI enabled */
1320                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1321                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1322                 }
1323                 /* FIXME: assert CPU port conditions for SNB+ */
1324         }
1325
1326         reg = PIPECONF(pipe);
1327         val = I915_READ(reg);
1328         if (val & PIPECONF_ENABLE)
1329                 return;
1330
1331         I915_WRITE(reg, val | PIPECONF_ENABLE);
1332         intel_wait_for_vblank(dev_priv->dev, pipe);
1333 }
1334
1335 /**
1336  * intel_disable_pipe - disable a pipe, asserting requirements
1337  * @dev_priv: i915 private structure
1338  * @pipe: pipe to disable
1339  *
1340  * Disable @pipe, making sure that various hardware specific requirements
1341  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1342  *
1343  * @pipe should be %PIPE_A or %PIPE_B.
1344  *
1345  * Will wait until the pipe has shut down before returning.
1346  */
1347 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1348                                enum pipe pipe)
1349 {
1350         int reg;
1351         u32 val;
1352
1353         /*
1354          * Make sure planes won't keep trying to pump pixels to us,
1355          * or we might hang the display.
1356          */
1357         assert_planes_disabled(dev_priv, pipe);
1358
1359         /* Don't disable pipe A or pipe A PLLs if needed */
1360         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361                 return;
1362
1363         reg = PIPECONF(pipe);
1364         val = I915_READ(reg);
1365         if ((val & PIPECONF_ENABLE) == 0)
1366                 return;
1367
1368         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1369         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1370 }
1371
1372 /*
1373  * Plane regs are double buffered, going from enabled->disabled needs a
1374  * trigger in order to latch.  The display address reg provides this.
1375  */
1376 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1377                                       enum plane plane)
1378 {
1379         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1380         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1381 }
1382
1383 /**
1384  * intel_enable_plane - enable a display plane on a given pipe
1385  * @dev_priv: i915 private structure
1386  * @plane: plane to enable
1387  * @pipe: pipe being fed
1388  *
1389  * Enable @plane on @pipe, making sure that @pipe is running first.
1390  */
1391 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1392                                enum plane plane, enum pipe pipe)
1393 {
1394         int reg;
1395         u32 val;
1396
1397         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1398         assert_pipe_enabled(dev_priv, pipe);
1399
1400         reg = DSPCNTR(plane);
1401         val = I915_READ(reg);
1402         if (val & DISPLAY_PLANE_ENABLE)
1403                 return;
1404
1405         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1406         intel_flush_display_plane(dev_priv, plane);
1407         intel_wait_for_vblank(dev_priv->dev, pipe);
1408 }
1409
1410 /**
1411  * intel_disable_plane - disable a display plane
1412  * @dev_priv: i915 private structure
1413  * @plane: plane to disable
1414  * @pipe: pipe consuming the data
1415  *
1416  * Disable @plane; should be an independent operation.
1417  */
1418 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1419                                 enum plane plane, enum pipe pipe)
1420 {
1421         int reg;
1422         u32 val;
1423
1424         reg = DSPCNTR(plane);
1425         val = I915_READ(reg);
1426         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1427                 return;
1428
1429         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1430         intel_flush_display_plane(dev_priv, plane);
1431         intel_wait_for_vblank(dev_priv->dev, pipe);
1432 }
1433
1434 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1435                            enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1439                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1440                 I915_WRITE(reg, val & ~DP_PORT_EN);
1441         }
1442 }
1443
1444 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1445                              enum pipe pipe, int reg)
1446 {
1447         u32 val = I915_READ(reg);
1448         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1449                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1450                               reg, pipe);
1451                 I915_WRITE(reg, val & ~PORT_ENABLE);
1452         }
1453 }
1454
1455 /* Disable any ports connected to this transcoder */
1456 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1457                                     enum pipe pipe)
1458 {
1459         u32 reg, val;
1460
1461         val = I915_READ(PCH_PP_CONTROL);
1462         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1463
1464         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1465         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1466         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1467
1468         reg = PCH_ADPA;
1469         val = I915_READ(reg);
1470         if (adpa_pipe_enabled(dev_priv, val, pipe))
1471                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1472
1473         reg = PCH_LVDS;
1474         val = I915_READ(reg);
1475         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1476                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1477                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1478                 POSTING_READ(reg);
1479                 udelay(100);
1480         }
1481
1482         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1483         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1484         disable_pch_hdmi(dev_priv, pipe, HDMID);
1485 }
1486
1487 static void i8xx_disable_fbc(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         u32 fbc_ctl;
1491
1492         /* Disable compression */
1493         fbc_ctl = I915_READ(FBC_CONTROL);
1494         if ((fbc_ctl & FBC_CTL_EN) == 0)
1495                 return;
1496
1497         fbc_ctl &= ~FBC_CTL_EN;
1498         I915_WRITE(FBC_CONTROL, fbc_ctl);
1499
1500         /* Wait for compressing bit to clear */
1501         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1502                 DRM_DEBUG_KMS("FBC idle timed out\n");
1503                 return;
1504         }
1505
1506         DRM_DEBUG_KMS("disabled FBC\n");
1507 }
1508
1509 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1510 {
1511         struct drm_device *dev = crtc->dev;
1512         struct drm_i915_private *dev_priv = dev->dev_private;
1513         struct drm_framebuffer *fb = crtc->fb;
1514         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1515         struct drm_i915_gem_object *obj = intel_fb->obj;
1516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1517         int cfb_pitch;
1518         int plane, i;
1519         u32 fbc_ctl, fbc_ctl2;
1520
1521         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1522         if (fb->pitches[0] < cfb_pitch)
1523                 cfb_pitch = fb->pitches[0];
1524
1525         /* FBC_CTL wants 64B units */
1526         cfb_pitch = (cfb_pitch / 64) - 1;
1527         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1528
1529         /* Clear old tags */
1530         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1531                 I915_WRITE(FBC_TAG + (i * 4), 0);
1532
1533         /* Set it up... */
1534         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1535         fbc_ctl2 |= plane;
1536         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1537         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1538
1539         /* enable it... */
1540         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1541         if (IS_I945GM(dev))
1542                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1543         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1544         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1545         fbc_ctl |= obj->fence_reg;
1546         I915_WRITE(FBC_CONTROL, fbc_ctl);
1547
1548         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1549                       cfb_pitch, crtc->y, intel_crtc->plane);
1550 }
1551
1552 static bool i8xx_fbc_enabled(struct drm_device *dev)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555
1556         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1557 }
1558
1559 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1560 {
1561         struct drm_device *dev = crtc->dev;
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         struct drm_framebuffer *fb = crtc->fb;
1564         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1565         struct drm_i915_gem_object *obj = intel_fb->obj;
1566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1567         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1568         unsigned long stall_watermark = 200;
1569         u32 dpfc_ctl;
1570
1571         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1572         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1573         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1574
1575         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1576                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1577                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1578         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1579
1580         /* enable it... */
1581         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1582
1583         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1584 }
1585
1586 static void g4x_disable_fbc(struct drm_device *dev)
1587 {
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589         u32 dpfc_ctl;
1590
1591         /* Disable compression */
1592         dpfc_ctl = I915_READ(DPFC_CONTROL);
1593         if (dpfc_ctl & DPFC_CTL_EN) {
1594                 dpfc_ctl &= ~DPFC_CTL_EN;
1595                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1596
1597                 DRM_DEBUG_KMS("disabled FBC\n");
1598         }
1599 }
1600
1601 static bool g4x_fbc_enabled(struct drm_device *dev)
1602 {
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1606 }
1607
1608 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1609 {
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         u32 blt_ecoskpd;
1612
1613         /* Make sure blitter notifies FBC of writes */
1614         gen6_gt_force_wake_get(dev_priv);
1615         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1616         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1617                 GEN6_BLITTER_LOCK_SHIFT;
1618         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1619         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1620         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1621         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1622                          GEN6_BLITTER_LOCK_SHIFT);
1623         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1624         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1625         gen6_gt_force_wake_put(dev_priv);
1626 }
1627
1628 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1629 {
1630         struct drm_device *dev = crtc->dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct drm_framebuffer *fb = crtc->fb;
1633         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1634         struct drm_i915_gem_object *obj = intel_fb->obj;
1635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1637         unsigned long stall_watermark = 200;
1638         u32 dpfc_ctl;
1639
1640         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1641         dpfc_ctl &= DPFC_RESERVED;
1642         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1643         /* Set persistent mode for front-buffer rendering, ala X. */
1644         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1645         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1646         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1647
1648         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1649                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1650                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1651         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1652         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1653         /* enable it... */
1654         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1655
1656         if (IS_GEN6(dev)) {
1657                 I915_WRITE(SNB_DPFC_CTL_SA,
1658                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1659                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1660                 sandybridge_blit_fbc_update(dev);
1661         }
1662
1663         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1664 }
1665
1666 static void ironlake_disable_fbc(struct drm_device *dev)
1667 {
1668         struct drm_i915_private *dev_priv = dev->dev_private;
1669         u32 dpfc_ctl;
1670
1671         /* Disable compression */
1672         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1673         if (dpfc_ctl & DPFC_CTL_EN) {
1674                 dpfc_ctl &= ~DPFC_CTL_EN;
1675                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1676
1677                 DRM_DEBUG_KMS("disabled FBC\n");
1678         }
1679 }
1680
1681 static bool ironlake_fbc_enabled(struct drm_device *dev)
1682 {
1683         struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1686 }
1687
1688 bool intel_fbc_enabled(struct drm_device *dev)
1689 {
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691
1692         if (!dev_priv->display.fbc_enabled)
1693                 return false;
1694
1695         return dev_priv->display.fbc_enabled(dev);
1696 }
1697
1698 static void intel_fbc_work_fn(struct work_struct *__work)
1699 {
1700         struct intel_fbc_work *work =
1701                 container_of(to_delayed_work(__work),
1702                              struct intel_fbc_work, work);
1703         struct drm_device *dev = work->crtc->dev;
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705
1706         mutex_lock(&dev->struct_mutex);
1707         if (work == dev_priv->fbc_work) {
1708                 /* Double check that we haven't switched fb without cancelling
1709                  * the prior work.
1710                  */
1711                 if (work->crtc->fb == work->fb) {
1712                         dev_priv->display.enable_fbc(work->crtc,
1713                                                      work->interval);
1714
1715                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1716                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1717                         dev_priv->cfb_y = work->crtc->y;
1718                 }
1719
1720                 dev_priv->fbc_work = NULL;
1721         }
1722         mutex_unlock(&dev->struct_mutex);
1723
1724         kfree(work);
1725 }
1726
1727 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1728 {
1729         if (dev_priv->fbc_work == NULL)
1730                 return;
1731
1732         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1733
1734         /* Synchronisation is provided by struct_mutex and checking of
1735          * dev_priv->fbc_work, so we can perform the cancellation
1736          * entirely asynchronously.
1737          */
1738         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1739                 /* tasklet was killed before being run, clean up */
1740                 kfree(dev_priv->fbc_work);
1741
1742         /* Mark the work as no longer wanted so that if it does
1743          * wake-up (because the work was already running and waiting
1744          * for our mutex), it will discover that is no longer
1745          * necessary to run.
1746          */
1747         dev_priv->fbc_work = NULL;
1748 }
1749
1750 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1751 {
1752         struct intel_fbc_work *work;
1753         struct drm_device *dev = crtc->dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755
1756         if (!dev_priv->display.enable_fbc)
1757                 return;
1758
1759         intel_cancel_fbc_work(dev_priv);
1760
1761         work = kzalloc(sizeof *work, GFP_KERNEL);
1762         if (work == NULL) {
1763                 dev_priv->display.enable_fbc(crtc, interval);
1764                 return;
1765         }
1766
1767         work->crtc = crtc;
1768         work->fb = crtc->fb;
1769         work->interval = interval;
1770         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1771
1772         dev_priv->fbc_work = work;
1773
1774         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1775
1776         /* Delay the actual enabling to let pageflipping cease and the
1777          * display to settle before starting the compression. Note that
1778          * this delay also serves a second purpose: it allows for a
1779          * vblank to pass after disabling the FBC before we attempt
1780          * to modify the control registers.
1781          *
1782          * A more complicated solution would involve tracking vblanks
1783          * following the termination of the page-flipping sequence
1784          * and indeed performing the enable as a co-routine and not
1785          * waiting synchronously upon the vblank.
1786          */
1787         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1788 }
1789
1790 void intel_disable_fbc(struct drm_device *dev)
1791 {
1792         struct drm_i915_private *dev_priv = dev->dev_private;
1793
1794         intel_cancel_fbc_work(dev_priv);
1795
1796         if (!dev_priv->display.disable_fbc)
1797                 return;
1798
1799         dev_priv->display.disable_fbc(dev);
1800         dev_priv->cfb_plane = -1;
1801 }
1802
1803 /**
1804  * intel_update_fbc - enable/disable FBC as needed
1805  * @dev: the drm_device
1806  *
1807  * Set up the framebuffer compression hardware at mode set time.  We
1808  * enable it if possible:
1809  *   - plane A only (on pre-965)
1810  *   - no pixel mulitply/line duplication
1811  *   - no alpha buffer discard
1812  *   - no dual wide
1813  *   - framebuffer <= 2048 in width, 1536 in height
1814  *
1815  * We can't assume that any compression will take place (worst case),
1816  * so the compressed buffer has to be the same size as the uncompressed
1817  * one.  It also must reside (along with the line length buffer) in
1818  * stolen memory.
1819  *
1820  * We need to enable/disable FBC on a global basis.
1821  */
1822 static void intel_update_fbc(struct drm_device *dev)
1823 {
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         struct drm_crtc *crtc = NULL, *tmp_crtc;
1826         struct intel_crtc *intel_crtc;
1827         struct drm_framebuffer *fb;
1828         struct intel_framebuffer *intel_fb;
1829         struct drm_i915_gem_object *obj;
1830         int enable_fbc;
1831
1832         DRM_DEBUG_KMS("\n");
1833
1834         if (!i915_powersave)
1835                 return;
1836
1837         if (!I915_HAS_FBC(dev))
1838                 return;
1839
1840         /*
1841          * If FBC is already on, we just have to verify that we can
1842          * keep it that way...
1843          * Need to disable if:
1844          *   - more than one pipe is active
1845          *   - changing FBC params (stride, fence, mode)
1846          *   - new fb is too large to fit in compressed buffer
1847          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1848          */
1849         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1850                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1851                         if (crtc) {
1852                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1853                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1854                                 goto out_disable;
1855                         }
1856                         crtc = tmp_crtc;
1857                 }
1858         }
1859
1860         if (!crtc || crtc->fb == NULL) {
1861                 DRM_DEBUG_KMS("no output, disabling\n");
1862                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1863                 goto out_disable;
1864         }
1865
1866         intel_crtc = to_intel_crtc(crtc);
1867         fb = crtc->fb;
1868         intel_fb = to_intel_framebuffer(fb);
1869         obj = intel_fb->obj;
1870
1871         enable_fbc = i915_enable_fbc;
1872         if (enable_fbc < 0) {
1873                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1874                 enable_fbc = 1;
1875                 if (INTEL_INFO(dev)->gen <= 6)
1876                         enable_fbc = 0;
1877         }
1878         if (!enable_fbc) {
1879                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1880                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1881                 goto out_disable;
1882         }
1883         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1884                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1885                               "compression\n");
1886                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1887                 goto out_disable;
1888         }
1889         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1890             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1891                 DRM_DEBUG_KMS("mode incompatible with compression, "
1892                               "disabling\n");
1893                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1894                 goto out_disable;
1895         }
1896         if ((crtc->mode.hdisplay > 2048) ||
1897             (crtc->mode.vdisplay > 1536)) {
1898                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1899                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1900                 goto out_disable;
1901         }
1902         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1903                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1904                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1905                 goto out_disable;
1906         }
1907
1908         /* The use of a CPU fence is mandatory in order to detect writes
1909          * by the CPU to the scanout and trigger updates to the FBC.
1910          */
1911         if (obj->tiling_mode != I915_TILING_X ||
1912             obj->fence_reg == I915_FENCE_REG_NONE) {
1913                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1914                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1915                 goto out_disable;
1916         }
1917
1918         /* If the kernel debugger is active, always disable compression */
1919         if (in_dbg_master())
1920                 goto out_disable;
1921
1922         /* If the scanout has not changed, don't modify the FBC settings.
1923          * Note that we make the fundamental assumption that the fb->obj
1924          * cannot be unpinned (and have its GTT offset and fence revoked)
1925          * without first being decoupled from the scanout and FBC disabled.
1926          */
1927         if (dev_priv->cfb_plane == intel_crtc->plane &&
1928             dev_priv->cfb_fb == fb->base.id &&
1929             dev_priv->cfb_y == crtc->y)
1930                 return;
1931
1932         if (intel_fbc_enabled(dev)) {
1933                 /* We update FBC along two paths, after changing fb/crtc
1934                  * configuration (modeswitching) and after page-flipping
1935                  * finishes. For the latter, we know that not only did
1936                  * we disable the FBC at the start of the page-flip
1937                  * sequence, but also more than one vblank has passed.
1938                  *
1939                  * For the former case of modeswitching, it is possible
1940                  * to switch between two FBC valid configurations
1941                  * instantaneously so we do need to disable the FBC
1942                  * before we can modify its control registers. We also
1943                  * have to wait for the next vblank for that to take
1944                  * effect. However, since we delay enabling FBC we can
1945                  * assume that a vblank has passed since disabling and
1946                  * that we can safely alter the registers in the deferred
1947                  * callback.
1948                  *
1949                  * In the scenario that we go from a valid to invalid
1950                  * and then back to valid FBC configuration we have
1951                  * no strict enforcement that a vblank occurred since
1952                  * disabling the FBC. However, along all current pipe
1953                  * disabling paths we do need to wait for a vblank at
1954                  * some point. And we wait before enabling FBC anyway.
1955                  */
1956                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1957                 intel_disable_fbc(dev);
1958         }
1959
1960         intel_enable_fbc(crtc, 500);
1961         return;
1962
1963 out_disable:
1964         /* Multiple disables should be harmless */
1965         if (intel_fbc_enabled(dev)) {
1966                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1967                 intel_disable_fbc(dev);
1968         }
1969 }
1970
1971 int
1972 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1973                            struct drm_i915_gem_object *obj,
1974                            struct intel_ring_buffer *pipelined)
1975 {
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         u32 alignment;
1978         int ret;
1979
1980         switch (obj->tiling_mode) {
1981         case I915_TILING_NONE:
1982                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1983                         alignment = 128 * 1024;
1984                 else if (INTEL_INFO(dev)->gen >= 4)
1985                         alignment = 4 * 1024;
1986                 else
1987                         alignment = 64 * 1024;
1988                 break;
1989         case I915_TILING_X:
1990                 /* pin() will align the object as required by fence */
1991                 alignment = 0;
1992                 break;
1993         case I915_TILING_Y:
1994                 /* FIXME: Is this true? */
1995                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1996                 return -EINVAL;
1997         default:
1998                 BUG();
1999         }
2000
2001         dev_priv->mm.interruptible = false;
2002         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2003         if (ret)
2004                 goto err_interruptible;
2005
2006         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2007          * fence, whereas 965+ only requires a fence if using
2008          * framebuffer compression.  For simplicity, we always install
2009          * a fence as the cost is not that onerous.
2010          */
2011         if (obj->tiling_mode != I915_TILING_NONE) {
2012                 ret = i915_gem_object_get_fence(obj, pipelined);
2013                 if (ret)
2014                         goto err_unpin;
2015         }
2016
2017         dev_priv->mm.interruptible = true;
2018         return 0;
2019
2020 err_unpin:
2021         i915_gem_object_unpin(obj);
2022 err_interruptible:
2023         dev_priv->mm.interruptible = true;
2024         return ret;
2025 }
2026
2027 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2028                              int x, int y)
2029 {
2030         struct drm_device *dev = crtc->dev;
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2033         struct intel_framebuffer *intel_fb;
2034         struct drm_i915_gem_object *obj;
2035         int plane = intel_crtc->plane;
2036         unsigned long Start, Offset;
2037         u32 dspcntr;
2038         u32 reg;
2039
2040         switch (plane) {
2041         case 0:
2042         case 1:
2043                 break;
2044         default:
2045                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046                 return -EINVAL;
2047         }
2048
2049         intel_fb = to_intel_framebuffer(fb);
2050         obj = intel_fb->obj;
2051
2052         reg = DSPCNTR(plane);
2053         dspcntr = I915_READ(reg);
2054         /* Mask out pixel format bits in case we change it */
2055         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056         switch (fb->bits_per_pixel) {
2057         case 8:
2058                 dspcntr |= DISPPLANE_8BPP;
2059                 break;
2060         case 16:
2061                 if (fb->depth == 15)
2062                         dspcntr |= DISPPLANE_15_16BPP;
2063                 else
2064                         dspcntr |= DISPPLANE_16BPP;
2065                 break;
2066         case 24:
2067         case 32:
2068                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2069                 break;
2070         default:
2071                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2072                 return -EINVAL;
2073         }
2074         if (INTEL_INFO(dev)->gen >= 4) {
2075                 if (obj->tiling_mode != I915_TILING_NONE)
2076                         dspcntr |= DISPPLANE_TILED;
2077                 else
2078                         dspcntr &= ~DISPPLANE_TILED;
2079         }
2080
2081         I915_WRITE(reg, dspcntr);
2082
2083         Start = obj->gtt_offset;
2084         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2085
2086         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2087                       Start, Offset, x, y, fb->pitches[0]);
2088         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2089         if (INTEL_INFO(dev)->gen >= 4) {
2090                 I915_WRITE(DSPSURF(plane), Start);
2091                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2092                 I915_WRITE(DSPADDR(plane), Offset);
2093         } else
2094                 I915_WRITE(DSPADDR(plane), Start + Offset);
2095         POSTING_READ(reg);
2096
2097         return 0;
2098 }
2099
2100 static int ironlake_update_plane(struct drm_crtc *crtc,
2101                                  struct drm_framebuffer *fb, int x, int y)
2102 {
2103         struct drm_device *dev = crtc->dev;
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106         struct intel_framebuffer *intel_fb;
2107         struct drm_i915_gem_object *obj;
2108         int plane = intel_crtc->plane;
2109         unsigned long Start, Offset;
2110         u32 dspcntr;
2111         u32 reg;
2112
2113         switch (plane) {
2114         case 0:
2115         case 1:
2116         case 2:
2117                 break;
2118         default:
2119                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2120                 return -EINVAL;
2121         }
2122
2123         intel_fb = to_intel_framebuffer(fb);
2124         obj = intel_fb->obj;
2125
2126         reg = DSPCNTR(plane);
2127         dspcntr = I915_READ(reg);
2128         /* Mask out pixel format bits in case we change it */
2129         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2130         switch (fb->bits_per_pixel) {
2131         case 8:
2132                 dspcntr |= DISPPLANE_8BPP;
2133                 break;
2134         case 16:
2135                 if (fb->depth != 16)
2136                         return -EINVAL;
2137
2138                 dspcntr |= DISPPLANE_16BPP;
2139                 break;
2140         case 24:
2141         case 32:
2142                 if (fb->depth == 24)
2143                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2144                 else if (fb->depth == 30)
2145                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2146                 else
2147                         return -EINVAL;
2148                 break;
2149         default:
2150                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2151                 return -EINVAL;
2152         }
2153
2154         if (obj->tiling_mode != I915_TILING_NONE)
2155                 dspcntr |= DISPPLANE_TILED;
2156         else
2157                 dspcntr &= ~DISPPLANE_TILED;
2158
2159         /* must disable */
2160         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2161
2162         I915_WRITE(reg, dspcntr);
2163
2164         Start = obj->gtt_offset;
2165         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2166
2167         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2168                       Start, Offset, x, y, fb->pitches[0]);
2169         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2170         I915_WRITE(DSPSURF(plane), Start);
2171         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2172         I915_WRITE(DSPADDR(plane), Offset);
2173         POSTING_READ(reg);
2174
2175         return 0;
2176 }
2177
2178 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2179 static int
2180 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2181                            int x, int y, enum mode_set_atomic state)
2182 {
2183         struct drm_device *dev = crtc->dev;
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         int ret;
2186
2187         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2188         if (ret)
2189                 return ret;
2190
2191         intel_update_fbc(dev);
2192         intel_increase_pllclock(crtc);
2193
2194         return 0;
2195 }
2196
2197 static int
2198 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2199                     struct drm_framebuffer *old_fb)
2200 {
2201         struct drm_device *dev = crtc->dev;
2202         struct drm_i915_master_private *master_priv;
2203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2204         int ret;
2205
2206         /* no fb bound */
2207         if (!crtc->fb) {
2208                 DRM_ERROR("No FB bound\n");
2209                 return 0;
2210         }
2211
2212         switch (intel_crtc->plane) {
2213         case 0:
2214         case 1:
2215                 break;
2216         case 2:
2217                 if (IS_IVYBRIDGE(dev))
2218                         break;
2219                 /* fall through otherwise */
2220         default:
2221                 DRM_ERROR("no plane for crtc\n");
2222                 return -EINVAL;
2223         }
2224
2225         mutex_lock(&dev->struct_mutex);
2226         ret = intel_pin_and_fence_fb_obj(dev,
2227                                          to_intel_framebuffer(crtc->fb)->obj,
2228                                          NULL);
2229         if (ret != 0) {
2230                 mutex_unlock(&dev->struct_mutex);
2231                 DRM_ERROR("pin & fence failed\n");
2232                 return ret;
2233         }
2234
2235         if (old_fb) {
2236                 struct drm_i915_private *dev_priv = dev->dev_private;
2237                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2238
2239                 wait_event(dev_priv->pending_flip_queue,
2240                            atomic_read(&dev_priv->mm.wedged) ||
2241                            atomic_read(&obj->pending_flip) == 0);
2242
2243                 /* Big Hammer, we also need to ensure that any pending
2244                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2245                  * current scanout is retired before unpinning the old
2246                  * framebuffer.
2247                  *
2248                  * This should only fail upon a hung GPU, in which case we
2249                  * can safely continue.
2250                  */
2251                 ret = i915_gem_object_finish_gpu(obj);
2252                 (void) ret;
2253         }
2254
2255         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2256                                          LEAVE_ATOMIC_MODE_SET);
2257         if (ret) {
2258                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("failed to update base address\n");
2261                 return ret;
2262         }
2263
2264         if (old_fb) {
2265                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2266                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2267         }
2268
2269         mutex_unlock(&dev->struct_mutex);
2270
2271         if (!dev->primary->master)
2272                 return 0;
2273
2274         master_priv = dev->primary->master->driver_priv;
2275         if (!master_priv->sarea_priv)
2276                 return 0;
2277
2278         if (intel_crtc->pipe) {
2279                 master_priv->sarea_priv->pipeB_x = x;
2280                 master_priv->sarea_priv->pipeB_y = y;
2281         } else {
2282                 master_priv->sarea_priv->pipeA_x = x;
2283                 master_priv->sarea_priv->pipeA_y = y;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         u32 dpa_ctl;
2294
2295         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2296         dpa_ctl = I915_READ(DP_A);
2297         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2298
2299         if (clock < 200000) {
2300                 u32 temp;
2301                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2302                 /* workaround for 160Mhz:
2303                    1) program 0x4600c bits 15:0 = 0x8124
2304                    2) program 0x46010 bit 0 = 1
2305                    3) program 0x46034 bit 24 = 1
2306                    4) program 0x64000 bit 14 = 1
2307                    */
2308                 temp = I915_READ(0x4600c);
2309                 temp &= 0xffff0000;
2310                 I915_WRITE(0x4600c, temp | 0x8124);
2311
2312                 temp = I915_READ(0x46010);
2313                 I915_WRITE(0x46010, temp | 1);
2314
2315                 temp = I915_READ(0x46034);
2316                 I915_WRITE(0x46034, temp | (1 << 24));
2317         } else {
2318                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2319         }
2320         I915_WRITE(DP_A, dpa_ctl);
2321
2322         POSTING_READ(DP_A);
2323         udelay(500);
2324 }
2325
2326 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2327 {
2328         struct drm_device *dev = crtc->dev;
2329         struct drm_i915_private *dev_priv = dev->dev_private;
2330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2331         int pipe = intel_crtc->pipe;
2332         u32 reg, temp;
2333
2334         /* enable normal train */
2335         reg = FDI_TX_CTL(pipe);
2336         temp = I915_READ(reg);
2337         if (IS_IVYBRIDGE(dev)) {
2338                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2339                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2340         } else {
2341                 temp &= ~FDI_LINK_TRAIN_NONE;
2342                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2343         }
2344         I915_WRITE(reg, temp);
2345
2346         reg = FDI_RX_CTL(pipe);
2347         temp = I915_READ(reg);
2348         if (HAS_PCH_CPT(dev)) {
2349                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2351         } else {
2352                 temp &= ~FDI_LINK_TRAIN_NONE;
2353                 temp |= FDI_LINK_TRAIN_NONE;
2354         }
2355         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2356
2357         /* wait one idle pattern time */
2358         POSTING_READ(reg);
2359         udelay(1000);
2360
2361         /* IVB wants error correction enabled */
2362         if (IS_IVYBRIDGE(dev))
2363                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2364                            FDI_FE_ERRC_ENABLE);
2365 }
2366
2367 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2368 {
2369         struct drm_i915_private *dev_priv = dev->dev_private;
2370         u32 flags = I915_READ(SOUTH_CHICKEN1);
2371
2372         flags |= FDI_PHASE_SYNC_OVR(pipe);
2373         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2374         flags |= FDI_PHASE_SYNC_EN(pipe);
2375         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2376         POSTING_READ(SOUTH_CHICKEN1);
2377 }
2378
2379 /* The FDI link training functions for ILK/Ibexpeak. */
2380 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2381 {
2382         struct drm_device *dev = crtc->dev;
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385         int pipe = intel_crtc->pipe;
2386         int plane = intel_crtc->plane;
2387         u32 reg, temp, tries;
2388
2389         /* FDI needs bits from pipe & plane first */
2390         assert_pipe_enabled(dev_priv, pipe);
2391         assert_plane_enabled(dev_priv, plane);
2392
2393         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2394            for train result */
2395         reg = FDI_RX_IMR(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_RX_SYMBOL_LOCK;
2398         temp &= ~FDI_RX_BIT_LOCK;
2399         I915_WRITE(reg, temp);
2400         I915_READ(reg);
2401         udelay(150);
2402
2403         /* enable CPU FDI TX and PCH FDI RX */
2404         reg = FDI_TX_CTL(pipe);
2405         temp = I915_READ(reg);
2406         temp &= ~(7 << 19);
2407         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2408         temp &= ~FDI_LINK_TRAIN_NONE;
2409         temp |= FDI_LINK_TRAIN_PATTERN_1;
2410         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2411
2412         reg = FDI_RX_CTL(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~FDI_LINK_TRAIN_NONE;
2415         temp |= FDI_LINK_TRAIN_PATTERN_1;
2416         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2417
2418         POSTING_READ(reg);
2419         udelay(150);
2420
2421         /* Ironlake workaround, enable clock pointer after FDI enable*/
2422         if (HAS_PCH_IBX(dev)) {
2423                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2424                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2425                            FDI_RX_PHASE_SYNC_POINTER_EN);
2426         }
2427
2428         reg = FDI_RX_IIR(pipe);
2429         for (tries = 0; tries < 5; tries++) {
2430                 temp = I915_READ(reg);
2431                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2432
2433                 if ((temp & FDI_RX_BIT_LOCK)) {
2434                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2435                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2436                         break;
2437                 }
2438         }
2439         if (tries == 5)
2440                 DRM_ERROR("FDI train 1 fail!\n");
2441
2442         /* Train 2 */
2443         reg = FDI_TX_CTL(pipe);
2444         temp = I915_READ(reg);
2445         temp &= ~FDI_LINK_TRAIN_NONE;
2446         temp |= FDI_LINK_TRAIN_PATTERN_2;
2447         I915_WRITE(reg, temp);
2448
2449         reg = FDI_RX_CTL(pipe);
2450         temp = I915_READ(reg);
2451         temp &= ~FDI_LINK_TRAIN_NONE;
2452         temp |= FDI_LINK_TRAIN_PATTERN_2;
2453         I915_WRITE(reg, temp);
2454
2455         POSTING_READ(reg);
2456         udelay(150);
2457
2458         reg = FDI_RX_IIR(pipe);
2459         for (tries = 0; tries < 5; tries++) {
2460                 temp = I915_READ(reg);
2461                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2462
2463                 if (temp & FDI_RX_SYMBOL_LOCK) {
2464                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2465                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2466                         break;
2467                 }
2468         }
2469         if (tries == 5)
2470                 DRM_ERROR("FDI train 2 fail!\n");
2471
2472         DRM_DEBUG_KMS("FDI train done\n");
2473
2474 }
2475
2476 static const int snb_b_fdi_train_param[] = {
2477         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2478         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2479         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2480         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2481 };
2482
2483 /* The FDI link training functions for SNB/Cougarpoint. */
2484 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2485 {
2486         struct drm_device *dev = crtc->dev;
2487         struct drm_i915_private *dev_priv = dev->dev_private;
2488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2489         int pipe = intel_crtc->pipe;
2490         u32 reg, temp, i;
2491
2492         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2493            for train result */
2494         reg = FDI_RX_IMR(pipe);
2495         temp = I915_READ(reg);
2496         temp &= ~FDI_RX_SYMBOL_LOCK;
2497         temp &= ~FDI_RX_BIT_LOCK;
2498         I915_WRITE(reg, temp);
2499
2500         POSTING_READ(reg);
2501         udelay(150);
2502
2503         /* enable CPU FDI TX and PCH FDI RX */
2504         reg = FDI_TX_CTL(pipe);
2505         temp = I915_READ(reg);
2506         temp &= ~(7 << 19);
2507         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2508         temp &= ~FDI_LINK_TRAIN_NONE;
2509         temp |= FDI_LINK_TRAIN_PATTERN_1;
2510         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511         /* SNB-B */
2512         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2513         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2514
2515         reg = FDI_RX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         if (HAS_PCH_CPT(dev)) {
2518                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2519                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2520         } else {
2521                 temp &= ~FDI_LINK_TRAIN_NONE;
2522                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2523         }
2524         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2525
2526         POSTING_READ(reg);
2527         udelay(150);
2528
2529         if (HAS_PCH_CPT(dev))
2530                 cpt_phase_pointer_enable(dev, pipe);
2531
2532         for (i = 0; i < 4; i++) {
2533                 reg = FDI_TX_CTL(pipe);
2534                 temp = I915_READ(reg);
2535                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536                 temp |= snb_b_fdi_train_param[i];
2537                 I915_WRITE(reg, temp);
2538
2539                 POSTING_READ(reg);
2540                 udelay(500);
2541
2542                 reg = FDI_RX_IIR(pipe);
2543                 temp = I915_READ(reg);
2544                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546                 if (temp & FDI_RX_BIT_LOCK) {
2547                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2548                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2549                         break;
2550                 }
2551         }
2552         if (i == 4)
2553                 DRM_ERROR("FDI train 1 fail!\n");
2554
2555         /* Train 2 */
2556         reg = FDI_TX_CTL(pipe);
2557         temp = I915_READ(reg);
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_2;
2560         if (IS_GEN6(dev)) {
2561                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2562                 /* SNB-B */
2563                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2564         }
2565         I915_WRITE(reg, temp);
2566
2567         reg = FDI_RX_CTL(pipe);
2568         temp = I915_READ(reg);
2569         if (HAS_PCH_CPT(dev)) {
2570                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2571                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2572         } else {
2573                 temp &= ~FDI_LINK_TRAIN_NONE;
2574                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2575         }
2576         I915_WRITE(reg, temp);
2577
2578         POSTING_READ(reg);
2579         udelay(150);
2580
2581         for (i = 0; i < 4; i++) {
2582                 reg = FDI_TX_CTL(pipe);
2583                 temp = I915_READ(reg);
2584                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585                 temp |= snb_b_fdi_train_param[i];
2586                 I915_WRITE(reg, temp);
2587
2588                 POSTING_READ(reg);
2589                 udelay(500);
2590
2591                 reg = FDI_RX_IIR(pipe);
2592                 temp = I915_READ(reg);
2593                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2594
2595                 if (temp & FDI_RX_SYMBOL_LOCK) {
2596                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2597                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2598                         break;
2599                 }
2600         }
2601         if (i == 4)
2602                 DRM_ERROR("FDI train 2 fail!\n");
2603
2604         DRM_DEBUG_KMS("FDI train done.\n");
2605 }
2606
2607 /* Manual link training for Ivy Bridge A0 parts */
2608 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2609 {
2610         struct drm_device *dev = crtc->dev;
2611         struct drm_i915_private *dev_priv = dev->dev_private;
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2613         int pipe = intel_crtc->pipe;
2614         u32 reg, temp, i;
2615
2616         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2617            for train result */
2618         reg = FDI_RX_IMR(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_RX_SYMBOL_LOCK;
2621         temp &= ~FDI_RX_BIT_LOCK;
2622         I915_WRITE(reg, temp);
2623
2624         POSTING_READ(reg);
2625         udelay(150);
2626
2627         /* enable CPU FDI TX and PCH FDI RX */
2628         reg = FDI_TX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~(7 << 19);
2631         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2632         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2633         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2634         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2636         temp |= FDI_COMPOSITE_SYNC;
2637         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2638
2639         reg = FDI_RX_CTL(pipe);
2640         temp = I915_READ(reg);
2641         temp &= ~FDI_LINK_TRAIN_AUTO;
2642         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2643         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2644         temp |= FDI_COMPOSITE_SYNC;
2645         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2646
2647         POSTING_READ(reg);
2648         udelay(150);
2649
2650         if (HAS_PCH_CPT(dev))
2651                 cpt_phase_pointer_enable(dev, pipe);
2652
2653         for (i = 0; i < 4; i++) {
2654                 reg = FDI_TX_CTL(pipe);
2655                 temp = I915_READ(reg);
2656                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657                 temp |= snb_b_fdi_train_param[i];
2658                 I915_WRITE(reg, temp);
2659
2660                 POSTING_READ(reg);
2661                 udelay(500);
2662
2663                 reg = FDI_RX_IIR(pipe);
2664                 temp = I915_READ(reg);
2665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667                 if (temp & FDI_RX_BIT_LOCK ||
2668                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2671                         break;
2672                 }
2673         }
2674         if (i == 4)
2675                 DRM_ERROR("FDI train 1 fail!\n");
2676
2677         /* Train 2 */
2678         reg = FDI_TX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684         I915_WRITE(reg, temp);
2685
2686         reg = FDI_RX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690         I915_WRITE(reg, temp);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         for (i = 0; i < 4; i++) {
2696                 reg = FDI_TX_CTL(pipe);
2697                 temp = I915_READ(reg);
2698                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699                 temp |= snb_b_fdi_train_param[i];
2700                 I915_WRITE(reg, temp);
2701
2702                 POSTING_READ(reg);
2703                 udelay(500);
2704
2705                 reg = FDI_RX_IIR(pipe);
2706                 temp = I915_READ(reg);
2707                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708
2709                 if (temp & FDI_RX_SYMBOL_LOCK) {
2710                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2712                         break;
2713                 }
2714         }
2715         if (i == 4)
2716                 DRM_ERROR("FDI train 2 fail!\n");
2717
2718         DRM_DEBUG_KMS("FDI train done.\n");
2719 }
2720
2721 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int pipe = intel_crtc->pipe;
2727         u32 reg, temp;
2728
2729         /* Write the TU size bits so error detection works */
2730         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2732
2733         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2734         reg = FDI_RX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         temp &= ~((0x7 << 19) | (0x7 << 16));
2737         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2738         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2740
2741         POSTING_READ(reg);
2742         udelay(200);
2743
2744         /* Switch from Rawclk to PCDclk */
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp | FDI_PCDCLK);
2747
2748         POSTING_READ(reg);
2749         udelay(200);
2750
2751         /* Enable CPU FDI TX PLL, always on for Ironlake */
2752         reg = FDI_TX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2755                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2756
2757                 POSTING_READ(reg);
2758                 udelay(100);
2759         }
2760 }
2761
2762 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2763 {
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         u32 flags = I915_READ(SOUTH_CHICKEN1);
2766
2767         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2768         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2769         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2770         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2771         POSTING_READ(SOUTH_CHICKEN1);
2772 }
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int pipe = intel_crtc->pipe;
2779         u32 reg, temp;
2780
2781         /* disable CPU FDI tx and PCH FDI rx */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785         POSTING_READ(reg);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~(0x7 << 16);
2790         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2791         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         /* Ironlake workaround, disable clock pointer after downing FDI */
2797         if (HAS_PCH_IBX(dev)) {
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2800                            I915_READ(FDI_RX_CHICKEN(pipe) &
2801                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2802         } else if (HAS_PCH_CPT(dev)) {
2803                 cpt_phase_pointer_disable(dev, pipe);
2804         }
2805
2806         /* still set train pattern 1 */
2807         reg = FDI_TX_CTL(pipe);
2808         temp = I915_READ(reg);
2809         temp &= ~FDI_LINK_TRAIN_NONE;
2810         temp |= FDI_LINK_TRAIN_PATTERN_1;
2811         I915_WRITE(reg, temp);
2812
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         if (HAS_PCH_CPT(dev)) {
2816                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2818         } else {
2819                 temp &= ~FDI_LINK_TRAIN_NONE;
2820                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2821         }
2822         /* BPC in FDI rx is consistent with that in PIPECONF */
2823         temp &= ~(0x07 << 16);
2824         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825         I915_WRITE(reg, temp);
2826
2827         POSTING_READ(reg);
2828         udelay(100);
2829 }
2830
2831 /*
2832  * When we disable a pipe, we need to clear any pending scanline wait events
2833  * to avoid hanging the ring, which we assume we are waiting on.
2834  */
2835 static void intel_clear_scanline_wait(struct drm_device *dev)
2836 {
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_ring_buffer *ring;
2839         u32 tmp;
2840
2841         if (IS_GEN2(dev))
2842                 /* Can't break the hang on i8xx */
2843                 return;
2844
2845         ring = LP_RING(dev_priv);
2846         tmp = I915_READ_CTL(ring);
2847         if (tmp & RING_WAIT)
2848                 I915_WRITE_CTL(ring, tmp);
2849 }
2850
2851 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2852 {
2853         struct drm_i915_gem_object *obj;
2854         struct drm_i915_private *dev_priv;
2855
2856         if (crtc->fb == NULL)
2857                 return;
2858
2859         obj = to_intel_framebuffer(crtc->fb)->obj;
2860         dev_priv = crtc->dev->dev_private;
2861         wait_event(dev_priv->pending_flip_queue,
2862                    atomic_read(&obj->pending_flip) == 0);
2863 }
2864
2865 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_mode_config *mode_config = &dev->mode_config;
2869         struct intel_encoder *encoder;
2870
2871         /*
2872          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873          * must be driven by its own crtc; no sharing is possible.
2874          */
2875         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2876                 if (encoder->base.crtc != crtc)
2877                         continue;
2878
2879                 switch (encoder->type) {
2880                 case INTEL_OUTPUT_EDP:
2881                         if (!intel_encoder_is_pch_edp(&encoder->base))
2882                                 return false;
2883                         continue;
2884                 }
2885         }
2886
2887         return true;
2888 }
2889
2890 /*
2891  * Enable PCH resources required for PCH ports:
2892  *   - PCH PLLs
2893  *   - FDI training & RX/TX
2894  *   - update transcoder timings
2895  *   - DP transcoding bits
2896  *   - transcoder
2897  */
2898 static void ironlake_pch_enable(struct drm_crtc *crtc)
2899 {
2900         struct drm_device *dev = crtc->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903         int pipe = intel_crtc->pipe;
2904         u32 reg, temp, transc_sel;
2905
2906         /* For PCH output, training FDI link */
2907         dev_priv->display.fdi_link_train(crtc);
2908
2909         intel_enable_pch_pll(dev_priv, pipe);
2910
2911         if (HAS_PCH_CPT(dev)) {
2912                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2913                         TRANSC_DPLLB_SEL;
2914
2915                 /* Be sure PCH DPLL SEL is set */
2916                 temp = I915_READ(PCH_DPLL_SEL);
2917                 if (pipe == 0) {
2918                         temp &= ~(TRANSA_DPLLB_SEL);
2919                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2920                 } else if (pipe == 1) {
2921                         temp &= ~(TRANSB_DPLLB_SEL);
2922                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2923                 } else if (pipe == 2) {
2924                         temp &= ~(TRANSC_DPLLB_SEL);
2925                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2926                 }
2927                 I915_WRITE(PCH_DPLL_SEL, temp);
2928         }
2929
2930         /* set transcoder timing, panel must allow it */
2931         assert_panel_unlocked(dev_priv, pipe);
2932         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2933         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2934         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2935
2936         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2937         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2938         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2939
2940         intel_fdi_normal_train(crtc);
2941
2942         /* For PCH DP, enable TRANS_DP_CTL */
2943         if (HAS_PCH_CPT(dev) &&
2944             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2945              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2946                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2947                 reg = TRANS_DP_CTL(pipe);
2948                 temp = I915_READ(reg);
2949                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2950                           TRANS_DP_SYNC_MASK |
2951                           TRANS_DP_BPC_MASK);
2952                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2953                          TRANS_DP_ENH_FRAMING);
2954                 temp |= bpc << 9; /* same format but at 11:9 */
2955
2956                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2957                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2958                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2959                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2960
2961                 switch (intel_trans_dp_port_sel(crtc)) {
2962                 case PCH_DP_B:
2963                         temp |= TRANS_DP_PORT_SEL_B;
2964                         break;
2965                 case PCH_DP_C:
2966                         temp |= TRANS_DP_PORT_SEL_C;
2967                         break;
2968                 case PCH_DP_D:
2969                         temp |= TRANS_DP_PORT_SEL_D;
2970                         break;
2971                 default:
2972                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2973                         temp |= TRANS_DP_PORT_SEL_B;
2974                         break;
2975                 }
2976
2977                 I915_WRITE(reg, temp);
2978         }
2979
2980         intel_enable_transcoder(dev_priv, pipe);
2981 }
2982
2983 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2984 {
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2987         u32 temp;
2988
2989         temp = I915_READ(dslreg);
2990         udelay(500);
2991         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2992                 /* Without this, mode sets may fail silently on FDI */
2993                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2994                 udelay(250);
2995                 I915_WRITE(tc2reg, 0);
2996                 if (wait_for(I915_READ(dslreg) != temp, 5))
2997                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2998         }
2999 }
3000
3001 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3002 {
3003         struct drm_device *dev = crtc->dev;
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006         int pipe = intel_crtc->pipe;
3007         int plane = intel_crtc->plane;
3008         u32 temp;
3009         bool is_pch_port;
3010
3011         if (intel_crtc->active)
3012                 return;
3013
3014         intel_crtc->active = true;
3015         intel_update_watermarks(dev);
3016
3017         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3018                 temp = I915_READ(PCH_LVDS);
3019                 if ((temp & LVDS_PORT_EN) == 0)
3020                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3021         }
3022
3023         is_pch_port = intel_crtc_driving_pch(crtc);
3024
3025         if (is_pch_port)
3026                 ironlake_fdi_pll_enable(crtc);
3027         else
3028                 ironlake_fdi_disable(crtc);
3029
3030         /* Enable panel fitting for LVDS */
3031         if (dev_priv->pch_pf_size &&
3032             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3033                 /* Force use of hard-coded filter coefficients
3034                  * as some pre-programmed values are broken,
3035                  * e.g. x201.
3036                  */
3037                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3038                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3039                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3040         }
3041
3042         /*
3043          * On ILK+ LUT must be loaded before the pipe is running but with
3044          * clocks enabled
3045          */
3046         intel_crtc_load_lut(crtc);
3047
3048         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3049         intel_enable_plane(dev_priv, plane, pipe);
3050
3051         if (is_pch_port)
3052                 ironlake_pch_enable(crtc);
3053
3054         mutex_lock(&dev->struct_mutex);
3055         intel_update_fbc(dev);
3056         mutex_unlock(&dev->struct_mutex);
3057
3058         intel_crtc_update_cursor(crtc, true);
3059 }
3060
3061 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3062 {
3063         struct drm_device *dev = crtc->dev;
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066         int pipe = intel_crtc->pipe;
3067         int plane = intel_crtc->plane;
3068         u32 reg, temp;
3069
3070         if (!intel_crtc->active)
3071                 return;
3072
3073         intel_crtc_wait_for_pending_flips(crtc);
3074         drm_vblank_off(dev, pipe);
3075         intel_crtc_update_cursor(crtc, false);
3076
3077         intel_disable_plane(dev_priv, plane, pipe);
3078
3079         if (dev_priv->cfb_plane == plane)
3080                 intel_disable_fbc(dev);
3081
3082         intel_disable_pipe(dev_priv, pipe);
3083
3084         /* Disable PF */
3085         I915_WRITE(PF_CTL(pipe), 0);
3086         I915_WRITE(PF_WIN_SZ(pipe), 0);
3087
3088         ironlake_fdi_disable(crtc);
3089
3090         /* This is a horrible layering violation; we should be doing this in
3091          * the connector/encoder ->prepare instead, but we don't always have
3092          * enough information there about the config to know whether it will
3093          * actually be necessary or just cause undesired flicker.
3094          */
3095         intel_disable_pch_ports(dev_priv, pipe);
3096
3097         intel_disable_transcoder(dev_priv, pipe);
3098
3099         if (HAS_PCH_CPT(dev)) {
3100                 /* disable TRANS_DP_CTL */
3101                 reg = TRANS_DP_CTL(pipe);
3102                 temp = I915_READ(reg);
3103                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3104                 temp |= TRANS_DP_PORT_SEL_NONE;
3105                 I915_WRITE(reg, temp);
3106
3107                 /* disable DPLL_SEL */
3108                 temp = I915_READ(PCH_DPLL_SEL);
3109                 switch (pipe) {
3110                 case 0:
3111                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3112                         break;
3113                 case 1:
3114                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3115                         break;
3116                 case 2:
3117                         /* C shares PLL A or B */
3118                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3119                         break;
3120                 default:
3121                         BUG(); /* wtf */
3122                 }
3123                 I915_WRITE(PCH_DPLL_SEL, temp);
3124         }
3125
3126         /* disable PCH DPLL */
3127         if (!intel_crtc->no_pll)
3128                 intel_disable_pch_pll(dev_priv, pipe);
3129
3130         /* Switch from PCDclk to Rawclk */
3131         reg = FDI_RX_CTL(pipe);
3132         temp = I915_READ(reg);
3133         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3134
3135         /* Disable CPU FDI TX PLL */
3136         reg = FDI_TX_CTL(pipe);
3137         temp = I915_READ(reg);
3138         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3139
3140         POSTING_READ(reg);
3141         udelay(100);
3142
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3146
3147         /* Wait for the clocks to turn off. */
3148         POSTING_READ(reg);
3149         udelay(100);
3150
3151         intel_crtc->active = false;
3152         intel_update_watermarks(dev);
3153
3154         mutex_lock(&dev->struct_mutex);
3155         intel_update_fbc(dev);
3156         intel_clear_scanline_wait(dev);
3157         mutex_unlock(&dev->struct_mutex);
3158 }
3159
3160 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3161 {
3162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163         int pipe = intel_crtc->pipe;
3164         int plane = intel_crtc->plane;
3165
3166         /* XXX: When our outputs are all unaware of DPMS modes other than off
3167          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3168          */
3169         switch (mode) {
3170         case DRM_MODE_DPMS_ON:
3171         case DRM_MODE_DPMS_STANDBY:
3172         case DRM_MODE_DPMS_SUSPEND:
3173                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3174                 ironlake_crtc_enable(crtc);
3175                 break;
3176
3177         case DRM_MODE_DPMS_OFF:
3178                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3179                 ironlake_crtc_disable(crtc);
3180                 break;
3181         }
3182 }
3183
3184 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3185 {
3186         if (!enable && intel_crtc->overlay) {
3187                 struct drm_device *dev = intel_crtc->base.dev;
3188                 struct drm_i915_private *dev_priv = dev->dev_private;
3189
3190                 mutex_lock(&dev->struct_mutex);
3191                 dev_priv->mm.interruptible = false;
3192                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3193                 dev_priv->mm.interruptible = true;
3194                 mutex_unlock(&dev->struct_mutex);
3195         }
3196
3197         /* Let userspace switch the overlay on again. In most cases userspace
3198          * has to recompute where to put it anyway.
3199          */
3200 }
3201
3202 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3203 {
3204         struct drm_device *dev = crtc->dev;
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207         int pipe = intel_crtc->pipe;
3208         int plane = intel_crtc->plane;
3209
3210         if (intel_crtc->active)
3211                 return;
3212
3213         intel_crtc->active = true;
3214         intel_update_watermarks(dev);
3215
3216         intel_enable_pll(dev_priv, pipe);
3217         intel_enable_pipe(dev_priv, pipe, false);
3218         intel_enable_plane(dev_priv, plane, pipe);
3219
3220         intel_crtc_load_lut(crtc);
3221         intel_update_fbc(dev);
3222
3223         /* Give the overlay scaler a chance to enable if it's on this pipe */
3224         intel_crtc_dpms_overlay(intel_crtc, true);
3225         intel_crtc_update_cursor(crtc, true);
3226 }
3227
3228 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3229 {
3230         struct drm_device *dev = crtc->dev;
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3233         int pipe = intel_crtc->pipe;
3234         int plane = intel_crtc->plane;
3235
3236         if (!intel_crtc->active)
3237                 return;
3238
3239         /* Give the overlay scaler a chance to disable if it's on this pipe */
3240         intel_crtc_wait_for_pending_flips(crtc);
3241         drm_vblank_off(dev, pipe);
3242         intel_crtc_dpms_overlay(intel_crtc, false);
3243         intel_crtc_update_cursor(crtc, false);
3244
3245         if (dev_priv->cfb_plane == plane)
3246                 intel_disable_fbc(dev);
3247
3248         intel_disable_plane(dev_priv, plane, pipe);
3249         intel_disable_pipe(dev_priv, pipe);
3250         intel_disable_pll(dev_priv, pipe);
3251
3252         intel_crtc->active = false;
3253         intel_update_fbc(dev);
3254         intel_update_watermarks(dev);
3255         intel_clear_scanline_wait(dev);
3256 }
3257
3258 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3259 {
3260         /* XXX: When our outputs are all unaware of DPMS modes other than off
3261          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3262          */
3263         switch (mode) {
3264         case DRM_MODE_DPMS_ON:
3265         case DRM_MODE_DPMS_STANDBY:
3266         case DRM_MODE_DPMS_SUSPEND:
3267                 i9xx_crtc_enable(crtc);
3268                 break;
3269         case DRM_MODE_DPMS_OFF:
3270                 i9xx_crtc_disable(crtc);
3271                 break;
3272         }
3273 }
3274
3275 /**
3276  * Sets the power management mode of the pipe and plane.
3277  */
3278 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3279 {
3280         struct drm_device *dev = crtc->dev;
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct drm_i915_master_private *master_priv;
3283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284         int pipe = intel_crtc->pipe;
3285         bool enabled;
3286
3287         if (intel_crtc->dpms_mode == mode)
3288                 return;
3289
3290         intel_crtc->dpms_mode = mode;
3291
3292         dev_priv->display.dpms(crtc, mode);
3293
3294         if (!dev->primary->master)
3295                 return;
3296
3297         master_priv = dev->primary->master->driver_priv;
3298         if (!master_priv->sarea_priv)
3299                 return;
3300
3301         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3302
3303         switch (pipe) {
3304         case 0:
3305                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3306                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3307                 break;
3308         case 1:
3309                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3310                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3311                 break;
3312         default:
3313                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3314                 break;
3315         }
3316 }
3317
3318 static void intel_crtc_disable(struct drm_crtc *crtc)
3319 {
3320         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3321         struct drm_device *dev = crtc->dev;
3322
3323         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3324
3325         if (crtc->fb) {
3326                 mutex_lock(&dev->struct_mutex);
3327                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3328                 mutex_unlock(&dev->struct_mutex);
3329         }
3330 }
3331
3332 /* Prepare for a mode set.
3333  *
3334  * Note we could be a lot smarter here.  We need to figure out which outputs
3335  * will be enabled, which disabled (in short, how the config will changes)
3336  * and perform the minimum necessary steps to accomplish that, e.g. updating
3337  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3338  * panel fitting is in the proper state, etc.
3339  */
3340 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3341 {
3342         i9xx_crtc_disable(crtc);
3343 }
3344
3345 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3346 {
3347         i9xx_crtc_enable(crtc);
3348 }
3349
3350 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3351 {
3352         ironlake_crtc_disable(crtc);
3353 }
3354
3355 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3356 {
3357         ironlake_crtc_enable(crtc);
3358 }
3359
3360 void intel_encoder_prepare(struct drm_encoder *encoder)
3361 {
3362         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3363         /* lvds has its own version of prepare see intel_lvds_prepare */
3364         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3365 }
3366
3367 void intel_encoder_commit(struct drm_encoder *encoder)
3368 {
3369         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3370         struct drm_device *dev = encoder->dev;
3371         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3372         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3373
3374         /* lvds has its own version of commit see intel_lvds_commit */
3375         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3376
3377         if (HAS_PCH_CPT(dev))
3378                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3379 }
3380
3381 void intel_encoder_destroy(struct drm_encoder *encoder)
3382 {
3383         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3384
3385         drm_encoder_cleanup(encoder);
3386         kfree(intel_encoder);
3387 }
3388
3389 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3390                                   struct drm_display_mode *mode,
3391                                   struct drm_display_mode *adjusted_mode)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394
3395         if (HAS_PCH_SPLIT(dev)) {
3396                 /* FDI link clock is fixed at 2.7G */
3397                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3398                         return false;
3399         }
3400
3401         /* XXX some encoders set the crtcinfo, others don't.
3402          * Obviously we need some form of conflict resolution here...
3403          */
3404         if (adjusted_mode->crtc_htotal == 0)
3405                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3406
3407         return true;
3408 }
3409
3410 static int i945_get_display_clock_speed(struct drm_device *dev)
3411 {
3412         return 400000;
3413 }
3414
3415 static int i915_get_display_clock_speed(struct drm_device *dev)
3416 {
3417         return 333000;
3418 }
3419
3420 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3421 {
3422         return 200000;
3423 }
3424
3425 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3426 {
3427         u16 gcfgc = 0;
3428
3429         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3430
3431         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3432                 return 133000;
3433         else {
3434                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3435                 case GC_DISPLAY_CLOCK_333_MHZ:
3436                         return 333000;
3437                 default:
3438                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3439                         return 190000;
3440                 }
3441         }
3442 }
3443
3444 static int i865_get_display_clock_speed(struct drm_device *dev)
3445 {
3446         return 266000;
3447 }
3448
3449 static int i855_get_display_clock_speed(struct drm_device *dev)
3450 {
3451         u16 hpllcc = 0;
3452         /* Assume that the hardware is in the high speed state.  This
3453          * should be the default.
3454          */
3455         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3456         case GC_CLOCK_133_200:
3457         case GC_CLOCK_100_200:
3458                 return 200000;
3459         case GC_CLOCK_166_250:
3460                 return 250000;
3461         case GC_CLOCK_100_133:
3462                 return 133000;
3463         }
3464
3465         /* Shouldn't happen */
3466         return 0;
3467 }
3468
3469 static int i830_get_display_clock_speed(struct drm_device *dev)
3470 {
3471         return 133000;
3472 }
3473
3474 struct fdi_m_n {
3475         u32        tu;
3476         u32        gmch_m;
3477         u32        gmch_n;
3478         u32        link_m;
3479         u32        link_n;
3480 };
3481
3482 static void
3483 fdi_reduce_ratio(u32 *num, u32 *den)
3484 {
3485         while (*num > 0xffffff || *den > 0xffffff) {
3486                 *num >>= 1;
3487                 *den >>= 1;
3488         }
3489 }
3490
3491 static void
3492 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3493                      int link_clock, struct fdi_m_n *m_n)
3494 {
3495         m_n->tu = 64; /* default size */
3496
3497         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3498         m_n->gmch_m = bits_per_pixel * pixel_clock;
3499         m_n->gmch_n = link_clock * nlanes * 8;
3500         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3501
3502         m_n->link_m = pixel_clock;
3503         m_n->link_n = link_clock;
3504         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3505 }
3506
3507
3508 struct intel_watermark_params {
3509         unsigned long fifo_size;
3510         unsigned long max_wm;
3511         unsigned long default_wm;
3512         unsigned long guard_size;
3513         unsigned long cacheline_size;
3514 };
3515
3516 /* Pineview has different values for various configs */
3517 static const struct intel_watermark_params pineview_display_wm = {
3518         PINEVIEW_DISPLAY_FIFO,
3519         PINEVIEW_MAX_WM,
3520         PINEVIEW_DFT_WM,
3521         PINEVIEW_GUARD_WM,
3522         PINEVIEW_FIFO_LINE_SIZE
3523 };
3524 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3525         PINEVIEW_DISPLAY_FIFO,
3526         PINEVIEW_MAX_WM,
3527         PINEVIEW_DFT_HPLLOFF_WM,
3528         PINEVIEW_GUARD_WM,
3529         PINEVIEW_FIFO_LINE_SIZE
3530 };
3531 static const struct intel_watermark_params pineview_cursor_wm = {
3532         PINEVIEW_CURSOR_FIFO,
3533         PINEVIEW_CURSOR_MAX_WM,
3534         PINEVIEW_CURSOR_DFT_WM,
3535         PINEVIEW_CURSOR_GUARD_WM,
3536         PINEVIEW_FIFO_LINE_SIZE,
3537 };
3538 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3539         PINEVIEW_CURSOR_FIFO,
3540         PINEVIEW_CURSOR_MAX_WM,
3541         PINEVIEW_CURSOR_DFT_WM,
3542         PINEVIEW_CURSOR_GUARD_WM,
3543         PINEVIEW_FIFO_LINE_SIZE
3544 };
3545 static const struct intel_watermark_params g4x_wm_info = {
3546         G4X_FIFO_SIZE,
3547         G4X_MAX_WM,
3548         G4X_MAX_WM,
3549         2,
3550         G4X_FIFO_LINE_SIZE,
3551 };
3552 static const struct intel_watermark_params g4x_cursor_wm_info = {
3553         I965_CURSOR_FIFO,
3554         I965_CURSOR_MAX_WM,
3555         I965_CURSOR_DFT_WM,
3556         2,
3557         G4X_FIFO_LINE_SIZE,
3558 };
3559 static const struct intel_watermark_params i965_cursor_wm_info = {
3560         I965_CURSOR_FIFO,
3561         I965_CURSOR_MAX_WM,
3562         I965_CURSOR_DFT_WM,
3563         2,
3564         I915_FIFO_LINE_SIZE,
3565 };
3566 static const struct intel_watermark_params i945_wm_info = {
3567         I945_FIFO_SIZE,
3568         I915_MAX_WM,
3569         1,
3570         2,
3571         I915_FIFO_LINE_SIZE
3572 };
3573 static const struct intel_watermark_params i915_wm_info = {
3574         I915_FIFO_SIZE,
3575         I915_MAX_WM,
3576         1,
3577         2,
3578         I915_FIFO_LINE_SIZE
3579 };
3580 static const struct intel_watermark_params i855_wm_info = {
3581         I855GM_FIFO_SIZE,
3582         I915_MAX_WM,
3583         1,
3584         2,
3585         I830_FIFO_LINE_SIZE
3586 };
3587 static const struct intel_watermark_params i830_wm_info = {
3588         I830_FIFO_SIZE,
3589         I915_MAX_WM,
3590         1,
3591         2,
3592         I830_FIFO_LINE_SIZE
3593 };
3594
3595 static const struct intel_watermark_params ironlake_display_wm_info = {
3596         ILK_DISPLAY_FIFO,
3597         ILK_DISPLAY_MAXWM,
3598         ILK_DISPLAY_DFTWM,
3599         2,
3600         ILK_FIFO_LINE_SIZE
3601 };
3602 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3603         ILK_CURSOR_FIFO,
3604         ILK_CURSOR_MAXWM,
3605         ILK_CURSOR_DFTWM,
3606         2,
3607         ILK_FIFO_LINE_SIZE
3608 };
3609 static const struct intel_watermark_params ironlake_display_srwm_info = {
3610         ILK_DISPLAY_SR_FIFO,
3611         ILK_DISPLAY_MAX_SRWM,
3612         ILK_DISPLAY_DFT_SRWM,
3613         2,
3614         ILK_FIFO_LINE_SIZE
3615 };
3616 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3617         ILK_CURSOR_SR_FIFO,
3618         ILK_CURSOR_MAX_SRWM,
3619         ILK_CURSOR_DFT_SRWM,
3620         2,
3621         ILK_FIFO_LINE_SIZE
3622 };
3623
3624 static const struct intel_watermark_params sandybridge_display_wm_info = {
3625         SNB_DISPLAY_FIFO,
3626         SNB_DISPLAY_MAXWM,
3627         SNB_DISPLAY_DFTWM,
3628         2,
3629         SNB_FIFO_LINE_SIZE
3630 };
3631 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3632         SNB_CURSOR_FIFO,
3633         SNB_CURSOR_MAXWM,
3634         SNB_CURSOR_DFTWM,
3635         2,
3636         SNB_FIFO_LINE_SIZE
3637 };
3638 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3639         SNB_DISPLAY_SR_FIFO,
3640         SNB_DISPLAY_MAX_SRWM,
3641         SNB_DISPLAY_DFT_SRWM,
3642         2,
3643         SNB_FIFO_LINE_SIZE
3644 };
3645 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3646         SNB_CURSOR_SR_FIFO,
3647         SNB_CURSOR_MAX_SRWM,
3648         SNB_CURSOR_DFT_SRWM,
3649         2,
3650         SNB_FIFO_LINE_SIZE
3651 };
3652
3653
3654 /**
3655  * intel_calculate_wm - calculate watermark level
3656  * @clock_in_khz: pixel clock
3657  * @wm: chip FIFO params
3658  * @pixel_size: display pixel size
3659  * @latency_ns: memory latency for the platform
3660  *
3661  * Calculate the watermark level (the level at which the display plane will
3662  * start fetching from memory again).  Each chip has a different display
3663  * FIFO size and allocation, so the caller needs to figure that out and pass
3664  * in the correct intel_watermark_params structure.
3665  *
3666  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3667  * on the pixel size.  When it reaches the watermark level, it'll start
3668  * fetching FIFO line sized based chunks from memory until the FIFO fills
3669  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3670  * will occur, and a display engine hang could result.
3671  */
3672 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3673                                         const struct intel_watermark_params *wm,
3674                                         int fifo_size,
3675                                         int pixel_size,
3676                                         unsigned long latency_ns)
3677 {
3678         long entries_required, wm_size;
3679
3680         /*
3681          * Note: we need to make sure we don't overflow for various clock &
3682          * latency values.
3683          * clocks go from a few thousand to several hundred thousand.
3684          * latency is usually a few thousand
3685          */
3686         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3687                 1000;
3688         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3689
3690         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3691
3692         wm_size = fifo_size - (entries_required + wm->guard_size);
3693
3694         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3695
3696         /* Don't promote wm_size to unsigned... */
3697         if (wm_size > (long)wm->max_wm)
3698                 wm_size = wm->max_wm;
3699         if (wm_size <= 0)
3700                 wm_size = wm->default_wm;
3701         return wm_size;
3702 }
3703
3704 struct cxsr_latency {
3705         int is_desktop;
3706         int is_ddr3;
3707         unsigned long fsb_freq;
3708         unsigned long mem_freq;
3709         unsigned long display_sr;
3710         unsigned long display_hpll_disable;
3711         unsigned long cursor_sr;
3712         unsigned long cursor_hpll_disable;
3713 };
3714
3715 static const struct cxsr_latency cxsr_latency_table[] = {
3716         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3717         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3718         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3719         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3720         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3721
3722         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3723         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3724         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3725         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3726         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3727
3728         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3729         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3730         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3731         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3732         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3733
3734         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3735         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3736         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3737         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3738         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3739
3740         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3741         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3742         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3743         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3744         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3745
3746         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3747         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3748         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3749         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3750         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3751 };
3752
3753 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3754                                                          int is_ddr3,
3755                                                          int fsb,
3756                                                          int mem)
3757 {
3758         const struct cxsr_latency *latency;
3759         int i;
3760
3761         if (fsb == 0 || mem == 0)
3762                 return NULL;
3763
3764         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3765                 latency = &cxsr_latency_table[i];
3766                 if (is_desktop == latency->is_desktop &&
3767                     is_ddr3 == latency->is_ddr3 &&
3768                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3769                         return latency;
3770         }
3771
3772         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3773
3774         return NULL;
3775 }
3776
3777 static void pineview_disable_cxsr(struct drm_device *dev)
3778 {
3779         struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781         /* deactivate cxsr */
3782         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3783 }
3784
3785 /*
3786  * Latency for FIFO fetches is dependent on several factors:
3787  *   - memory configuration (speed, channels)
3788  *   - chipset
3789  *   - current MCH state
3790  * It can be fairly high in some situations, so here we assume a fairly
3791  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3792  * set this value too high, the FIFO will fetch frequently to stay full)
3793  * and power consumption (set it too low to save power and we might see
3794  * FIFO underruns and display "flicker").
3795  *
3796  * A value of 5us seems to be a good balance; safe for very low end
3797  * platforms but not overly aggressive on lower latency configs.
3798  */
3799 static const int latency_ns = 5000;
3800
3801 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3802 {
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         uint32_t dsparb = I915_READ(DSPARB);
3805         int size;
3806
3807         size = dsparb & 0x7f;
3808         if (plane)
3809                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3810
3811         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3812                       plane ? "B" : "A", size);
3813
3814         return size;
3815 }
3816
3817 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3818 {
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         uint32_t dsparb = I915_READ(DSPARB);
3821         int size;
3822
3823         size = dsparb & 0x1ff;
3824         if (plane)
3825                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3826         size >>= 1; /* Convert to cachelines */
3827
3828         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3829                       plane ? "B" : "A", size);
3830
3831         return size;
3832 }
3833
3834 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3835 {
3836         struct drm_i915_private *dev_priv = dev->dev_private;
3837         uint32_t dsparb = I915_READ(DSPARB);
3838         int size;
3839
3840         size = dsparb & 0x7f;
3841         size >>= 2; /* Convert to cachelines */
3842
3843         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3844                       plane ? "B" : "A",
3845                       size);
3846
3847         return size;
3848 }
3849
3850 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3851 {
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         uint32_t dsparb = I915_READ(DSPARB);
3854         int size;
3855
3856         size = dsparb & 0x7f;
3857         size >>= 1; /* Convert to cachelines */
3858
3859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3860                       plane ? "B" : "A", size);
3861
3862         return size;
3863 }
3864
3865 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3866 {
3867         struct drm_crtc *crtc, *enabled = NULL;
3868
3869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3870                 if (crtc->enabled && crtc->fb) {
3871                         if (enabled)
3872                                 return NULL;
3873                         enabled = crtc;
3874                 }
3875         }
3876
3877         return enabled;
3878 }
3879
3880 static void pineview_update_wm(struct drm_device *dev)
3881 {
3882         struct drm_i915_private *dev_priv = dev->dev_private;
3883         struct drm_crtc *crtc;
3884         const struct cxsr_latency *latency;
3885         u32 reg;
3886         unsigned long wm;
3887
3888         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3889                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3890         if (!latency) {
3891                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3892                 pineview_disable_cxsr(dev);
3893                 return;
3894         }
3895
3896         crtc = single_enabled_crtc(dev);
3897         if (crtc) {
3898                 int clock = crtc->mode.clock;
3899                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3900
3901                 /* Display SR */
3902                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3903                                         pineview_display_wm.fifo_size,
3904                                         pixel_size, latency->display_sr);
3905                 reg = I915_READ(DSPFW1);
3906                 reg &= ~DSPFW_SR_MASK;
3907                 reg |= wm << DSPFW_SR_SHIFT;
3908                 I915_WRITE(DSPFW1, reg);
3909                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3910
3911                 /* cursor SR */
3912                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3913                                         pineview_display_wm.fifo_size,
3914                                         pixel_size, latency->cursor_sr);
3915                 reg = I915_READ(DSPFW3);
3916                 reg &= ~DSPFW_CURSOR_SR_MASK;
3917                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3918                 I915_WRITE(DSPFW3, reg);
3919
3920                 /* Display HPLL off SR */
3921                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3922                                         pineview_display_hplloff_wm.fifo_size,
3923                                         pixel_size, latency->display_hpll_disable);
3924                 reg = I915_READ(DSPFW3);
3925                 reg &= ~DSPFW_HPLL_SR_MASK;
3926                 reg |= wm & DSPFW_HPLL_SR_MASK;
3927                 I915_WRITE(DSPFW3, reg);
3928
3929                 /* cursor HPLL off SR */
3930                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3931                                         pineview_display_hplloff_wm.fifo_size,
3932                                         pixel_size, latency->cursor_hpll_disable);
3933                 reg = I915_READ(DSPFW3);
3934                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3935                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3936                 I915_WRITE(DSPFW3, reg);
3937                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3938
3939                 /* activate cxsr */
3940                 I915_WRITE(DSPFW3,
3941                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3942                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3943         } else {
3944                 pineview_disable_cxsr(dev);
3945                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3946         }
3947 }
3948
3949 static bool g4x_compute_wm0(struct drm_device *dev,
3950                             int plane,
3951                             const struct intel_watermark_params *display,
3952                             int display_latency_ns,
3953                             const struct intel_watermark_params *cursor,
3954                             int cursor_latency_ns,
3955                             int *plane_wm,
3956                             int *cursor_wm)
3957 {
3958         struct drm_crtc *crtc;
3959         int htotal, hdisplay, clock, pixel_size;
3960         int line_time_us, line_count;
3961         int entries, tlb_miss;
3962
3963         crtc = intel_get_crtc_for_plane(dev, plane);
3964         if (crtc->fb == NULL || !crtc->enabled) {
3965                 *cursor_wm = cursor->guard_size;
3966                 *plane_wm = display->guard_size;
3967                 return false;
3968         }
3969
3970         htotal = crtc->mode.htotal;
3971         hdisplay = crtc->mode.hdisplay;
3972         clock = crtc->mode.clock;
3973         pixel_size = crtc->fb->bits_per_pixel / 8;
3974
3975         /* Use the small buffer method to calculate plane watermark */
3976         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3977         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3978         if (tlb_miss > 0)
3979                 entries += tlb_miss;
3980         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3981         *plane_wm = entries + display->guard_size;
3982         if (*plane_wm > (int)display->max_wm)
3983                 *plane_wm = display->max_wm;
3984
3985         /* Use the large buffer method to calculate cursor watermark */
3986         line_time_us = ((htotal * 1000) / clock);
3987         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3988         entries = line_count * 64 * pixel_size;
3989         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3990         if (tlb_miss > 0)
3991                 entries += tlb_miss;
3992         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3993         *cursor_wm = entries + cursor->guard_size;
3994         if (*cursor_wm > (int)cursor->max_wm)
3995                 *cursor_wm = (int)cursor->max_wm;
3996
3997         return true;
3998 }
3999
4000 /*
4001  * Check the wm result.
4002  *
4003  * If any calculated watermark values is larger than the maximum value that
4004  * can be programmed into the associated watermark register, that watermark
4005  * must be disabled.
4006  */
4007 static bool g4x_check_srwm(struct drm_device *dev,
4008                            int display_wm, int cursor_wm,
4009                            const struct intel_watermark_params *display,
4010                            const struct intel_watermark_params *cursor)
4011 {
4012         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4013                       display_wm, cursor_wm);
4014
4015         if (display_wm > display->max_wm) {
4016                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4017                               display_wm, display->max_wm);
4018                 return false;
4019         }
4020
4021         if (cursor_wm > cursor->max_wm) {
4022                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4023                               cursor_wm, cursor->max_wm);
4024                 return false;
4025         }
4026
4027         if (!(display_wm || cursor_wm)) {
4028                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4029                 return false;
4030         }
4031
4032         return true;
4033 }
4034
4035 static bool g4x_compute_srwm(struct drm_device *dev,
4036                              int plane,
4037                              int latency_ns,
4038                              const struct intel_watermark_params *display,
4039                              const struct intel_watermark_params *cursor,
4040                              int *display_wm, int *cursor_wm)
4041 {
4042         struct drm_crtc *crtc;
4043         int hdisplay, htotal, pixel_size, clock;
4044         unsigned long line_time_us;
4045         int line_count, line_size;
4046         int small, large;
4047         int entries;
4048
4049         if (!latency_ns) {
4050                 *display_wm = *cursor_wm = 0;
4051                 return false;
4052         }
4053
4054         crtc = intel_get_crtc_for_plane(dev, plane);
4055         hdisplay = crtc->mode.hdisplay;
4056         htotal = crtc->mode.htotal;
4057         clock = crtc->mode.clock;
4058         pixel_size = crtc->fb->bits_per_pixel / 8;
4059
4060         line_time_us = (htotal * 1000) / clock;
4061         line_count = (latency_ns / line_time_us + 1000) / 1000;
4062         line_size = hdisplay * pixel_size;
4063
4064         /* Use the minimum of the small and large buffer method for primary */
4065         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066         large = line_count * line_size;
4067
4068         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069         *display_wm = entries + display->guard_size;
4070
4071         /* calculate the self-refresh watermark for display cursor */
4072         entries = line_count * pixel_size * 64;
4073         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4074         *cursor_wm = entries + cursor->guard_size;
4075
4076         return g4x_check_srwm(dev,
4077                               *display_wm, *cursor_wm,
4078                               display, cursor);
4079 }
4080
4081 #define single_plane_enabled(mask) is_power_of_2(mask)
4082
4083 static void g4x_update_wm(struct drm_device *dev)
4084 {
4085         static const int sr_latency_ns = 12000;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4088         int plane_sr, cursor_sr;
4089         unsigned int enabled = 0;
4090
4091         if (g4x_compute_wm0(dev, 0,
4092                             &g4x_wm_info, latency_ns,
4093                             &g4x_cursor_wm_info, latency_ns,
4094                             &planea_wm, &cursora_wm))
4095                 enabled |= 1;
4096
4097         if (g4x_compute_wm0(dev, 1,
4098                             &g4x_wm_info, latency_ns,
4099                             &g4x_cursor_wm_info, latency_ns,
4100                             &planeb_wm, &cursorb_wm))
4101                 enabled |= 2;
4102
4103         plane_sr = cursor_sr = 0;
4104         if (single_plane_enabled(enabled) &&
4105             g4x_compute_srwm(dev, ffs(enabled) - 1,
4106                              sr_latency_ns,
4107                              &g4x_wm_info,
4108                              &g4x_cursor_wm_info,
4109                              &plane_sr, &cursor_sr))
4110                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4111         else
4112                 I915_WRITE(FW_BLC_SELF,
4113                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4114
4115         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4116                       planea_wm, cursora_wm,
4117                       planeb_wm, cursorb_wm,
4118                       plane_sr, cursor_sr);
4119
4120         I915_WRITE(DSPFW1,
4121                    (plane_sr << DSPFW_SR_SHIFT) |
4122                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4123                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4124                    planea_wm);
4125         I915_WRITE(DSPFW2,
4126                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4127                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4128         /* HPLL off in SR has some issues on G4x... disable it */
4129         I915_WRITE(DSPFW3,
4130                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4131                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4132 }
4133
4134 static void i965_update_wm(struct drm_device *dev)
4135 {
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137         struct drm_crtc *crtc;
4138         int srwm = 1;
4139         int cursor_sr = 16;
4140
4141         /* Calc sr entries for one plane configs */
4142         crtc = single_enabled_crtc(dev);
4143         if (crtc) {
4144                 /* self-refresh has much higher latency */
4145                 static const int sr_latency_ns = 12000;
4146                 int clock = crtc->mode.clock;
4147                 int htotal = crtc->mode.htotal;
4148                 int hdisplay = crtc->mode.hdisplay;
4149                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4150                 unsigned long line_time_us;
4151                 int entries;
4152
4153                 line_time_us = ((htotal * 1000) / clock);
4154
4155                 /* Use ns/us then divide to preserve precision */
4156                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4157                         pixel_size * hdisplay;
4158                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4159                 srwm = I965_FIFO_SIZE - entries;
4160                 if (srwm < 0)
4161                         srwm = 1;
4162                 srwm &= 0x1ff;
4163                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4164                               entries, srwm);
4165
4166                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4167                         pixel_size * 64;
4168                 entries = DIV_ROUND_UP(entries,
4169                                           i965_cursor_wm_info.cacheline_size);
4170                 cursor_sr = i965_cursor_wm_info.fifo_size -
4171                         (entries + i965_cursor_wm_info.guard_size);
4172
4173                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4174                         cursor_sr = i965_cursor_wm_info.max_wm;
4175
4176                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4177                               "cursor %d\n", srwm, cursor_sr);
4178
4179                 if (IS_CRESTLINE(dev))
4180                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4181         } else {
4182                 /* Turn off self refresh if both pipes are enabled */
4183                 if (IS_CRESTLINE(dev))
4184                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4185                                    & ~FW_BLC_SELF_EN);
4186         }
4187
4188         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4189                       srwm);
4190
4191         /* 965 has limitations... */
4192         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4193                    (8 << 16) | (8 << 8) | (8 << 0));
4194         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4195         /* update cursor SR watermark */
4196         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4197 }
4198
4199 static void i9xx_update_wm(struct drm_device *dev)
4200 {
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         const struct intel_watermark_params *wm_info;
4203         uint32_t fwater_lo;
4204         uint32_t fwater_hi;
4205         int cwm, srwm = 1;
4206         int fifo_size;
4207         int planea_wm, planeb_wm;
4208         struct drm_crtc *crtc, *enabled = NULL;
4209
4210         if (IS_I945GM(dev))
4211                 wm_info = &i945_wm_info;
4212         else if (!IS_GEN2(dev))
4213                 wm_info = &i915_wm_info;
4214         else
4215                 wm_info = &i855_wm_info;
4216
4217         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4218         crtc = intel_get_crtc_for_plane(dev, 0);
4219         if (crtc->enabled && crtc->fb) {
4220                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4221                                                wm_info, fifo_size,
4222                                                crtc->fb->bits_per_pixel / 8,
4223                                                latency_ns);
4224                 enabled = crtc;
4225         } else
4226                 planea_wm = fifo_size - wm_info->guard_size;
4227
4228         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4229         crtc = intel_get_crtc_for_plane(dev, 1);
4230         if (crtc->enabled && crtc->fb) {
4231                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4232                                                wm_info, fifo_size,
4233                                                crtc->fb->bits_per_pixel / 8,
4234                                                latency_ns);
4235                 if (enabled == NULL)
4236                         enabled = crtc;
4237                 else
4238                         enabled = NULL;
4239         } else
4240                 planeb_wm = fifo_size - wm_info->guard_size;
4241
4242         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4243
4244         /*
4245          * Overlay gets an aggressive default since video jitter is bad.
4246          */
4247         cwm = 2;
4248
4249         /* Play safe and disable self-refresh before adjusting watermarks. */
4250         if (IS_I945G(dev) || IS_I945GM(dev))
4251                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4252         else if (IS_I915GM(dev))
4253                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4254
4255         /* Calc sr entries for one plane configs */
4256         if (HAS_FW_BLC(dev) && enabled) {
4257                 /* self-refresh has much higher latency */
4258                 static const int sr_latency_ns = 6000;
4259                 int clock = enabled->mode.clock;
4260                 int htotal = enabled->mode.htotal;
4261                 int hdisplay = enabled->mode.hdisplay;
4262                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4263                 unsigned long line_time_us;
4264                 int entries;
4265
4266                 line_time_us = (htotal * 1000) / clock;
4267
4268                 /* Use ns/us then divide to preserve precision */
4269                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4270                         pixel_size * hdisplay;
4271                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4272                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4273                 srwm = wm_info->fifo_size - entries;
4274                 if (srwm < 0)
4275                         srwm = 1;
4276
4277                 if (IS_I945G(dev) || IS_I945GM(dev))
4278                         I915_WRITE(FW_BLC_SELF,
4279                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4280                 else if (IS_I915GM(dev))
4281                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4282         }
4283
4284         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4285                       planea_wm, planeb_wm, cwm, srwm);
4286
4287         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4288         fwater_hi = (cwm & 0x1f);
4289
4290         /* Set request length to 8 cachelines per fetch */
4291         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4292         fwater_hi = fwater_hi | (1 << 8);
4293
4294         I915_WRITE(FW_BLC, fwater_lo);
4295         I915_WRITE(FW_BLC2, fwater_hi);
4296
4297         if (HAS_FW_BLC(dev)) {
4298                 if (enabled) {
4299                         if (IS_I945G(dev) || IS_I945GM(dev))
4300                                 I915_WRITE(FW_BLC_SELF,
4301                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4302                         else if (IS_I915GM(dev))
4303                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4304                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4305                 } else
4306                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4307         }
4308 }
4309
4310 static void i830_update_wm(struct drm_device *dev)
4311 {
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         struct drm_crtc *crtc;
4314         uint32_t fwater_lo;
4315         int planea_wm;
4316
4317         crtc = single_enabled_crtc(dev);
4318         if (crtc == NULL)
4319                 return;
4320
4321         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4322                                        dev_priv->display.get_fifo_size(dev, 0),
4323                                        crtc->fb->bits_per_pixel / 8,
4324                                        latency_ns);
4325         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4326         fwater_lo |= (3<<8) | planea_wm;
4327
4328         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4329
4330         I915_WRITE(FW_BLC, fwater_lo);
4331 }
4332
4333 #define ILK_LP0_PLANE_LATENCY           700
4334 #define ILK_LP0_CURSOR_LATENCY          1300
4335
4336 /*
4337  * Check the wm result.
4338  *
4339  * If any calculated watermark values is larger than the maximum value that
4340  * can be programmed into the associated watermark register, that watermark
4341  * must be disabled.
4342  */
4343 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4344                                 int fbc_wm, int display_wm, int cursor_wm,
4345                                 const struct intel_watermark_params *display,
4346                                 const struct intel_watermark_params *cursor)
4347 {
4348         struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4351                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4352
4353         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4354                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4355                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4356
4357                 /* fbc has it's own way to disable FBC WM */
4358                 I915_WRITE(DISP_ARB_CTL,
4359                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4360                 return false;
4361         }
4362
4363         if (display_wm > display->max_wm) {
4364                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4365                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4366                 return false;
4367         }
4368
4369         if (cursor_wm > cursor->max_wm) {
4370                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4371                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4372                 return false;
4373         }
4374
4375         if (!(fbc_wm || display_wm || cursor_wm)) {
4376                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4377                 return false;
4378         }
4379
4380         return true;
4381 }
4382
4383 /*
4384  * Compute watermark values of WM[1-3],
4385  */
4386 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4387                                   int latency_ns,
4388                                   const struct intel_watermark_params *display,
4389                                   const struct intel_watermark_params *cursor,
4390                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4391 {
4392         struct drm_crtc *crtc;
4393         unsigned long line_time_us;
4394         int hdisplay, htotal, pixel_size, clock;
4395         int line_count, line_size;
4396         int small, large;
4397         int entries;
4398
4399         if (!latency_ns) {
4400                 *fbc_wm = *display_wm = *cursor_wm = 0;
4401                 return false;
4402         }
4403
4404         crtc = intel_get_crtc_for_plane(dev, plane);
4405         hdisplay = crtc->mode.hdisplay;
4406         htotal = crtc->mode.htotal;
4407         clock = crtc->mode.clock;
4408         pixel_size = crtc->fb->bits_per_pixel / 8;
4409
4410         line_time_us = (htotal * 1000) / clock;
4411         line_count = (latency_ns / line_time_us + 1000) / 1000;
4412         line_size = hdisplay * pixel_size;
4413
4414         /* Use the minimum of the small and large buffer method for primary */
4415         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4416         large = line_count * line_size;
4417
4418         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4419         *display_wm = entries + display->guard_size;
4420
4421         /*
4422          * Spec says:
4423          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4424          */
4425         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4426
4427         /* calculate the self-refresh watermark for display cursor */
4428         entries = line_count * pixel_size * 64;
4429         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4430         *cursor_wm = entries + cursor->guard_size;
4431
4432         return ironlake_check_srwm(dev, level,
4433                                    *fbc_wm, *display_wm, *cursor_wm,
4434                                    display, cursor);
4435 }
4436
4437 static void ironlake_update_wm(struct drm_device *dev)
4438 {
4439         struct drm_i915_private *dev_priv = dev->dev_private;
4440         int fbc_wm, plane_wm, cursor_wm;
4441         unsigned int enabled;
4442
4443         enabled = 0;
4444         if (g4x_compute_wm0(dev, 0,
4445                             &ironlake_display_wm_info,
4446                             ILK_LP0_PLANE_LATENCY,
4447                             &ironlake_cursor_wm_info,
4448                             ILK_LP0_CURSOR_LATENCY,
4449                             &plane_wm, &cursor_wm)) {
4450                 I915_WRITE(WM0_PIPEA_ILK,
4451                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4452                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4453                               " plane %d, " "cursor: %d\n",
4454                               plane_wm, cursor_wm);
4455                 enabled |= 1;
4456         }
4457
4458         if (g4x_compute_wm0(dev, 1,
4459                             &ironlake_display_wm_info,
4460                             ILK_LP0_PLANE_LATENCY,
4461                             &ironlake_cursor_wm_info,
4462                             ILK_LP0_CURSOR_LATENCY,
4463                             &plane_wm, &cursor_wm)) {
4464                 I915_WRITE(WM0_PIPEB_ILK,
4465                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4466                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4467                               " plane %d, cursor: %d\n",
4468                               plane_wm, cursor_wm);
4469                 enabled |= 2;
4470         }
4471
4472         /*
4473          * Calculate and update the self-refresh watermark only when one
4474          * display plane is used.
4475          */
4476         I915_WRITE(WM3_LP_ILK, 0);
4477         I915_WRITE(WM2_LP_ILK, 0);
4478         I915_WRITE(WM1_LP_ILK, 0);
4479
4480         if (!single_plane_enabled(enabled))
4481                 return;
4482         enabled = ffs(enabled) - 1;
4483
4484         /* WM1 */
4485         if (!ironlake_compute_srwm(dev, 1, enabled,
4486                                    ILK_READ_WM1_LATENCY() * 500,
4487                                    &ironlake_display_srwm_info,
4488                                    &ironlake_cursor_srwm_info,
4489                                    &fbc_wm, &plane_wm, &cursor_wm))
4490                 return;
4491
4492         I915_WRITE(WM1_LP_ILK,
4493                    WM1_LP_SR_EN |
4494                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4495                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4496                    (plane_wm << WM1_LP_SR_SHIFT) |
4497                    cursor_wm);
4498
4499         /* WM2 */
4500         if (!ironlake_compute_srwm(dev, 2, enabled,
4501                                    ILK_READ_WM2_LATENCY() * 500,
4502                                    &ironlake_display_srwm_info,
4503                                    &ironlake_cursor_srwm_info,
4504                                    &fbc_wm, &plane_wm, &cursor_wm))
4505                 return;
4506
4507         I915_WRITE(WM2_LP_ILK,
4508                    WM2_LP_EN |
4509                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4510                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4511                    (plane_wm << WM1_LP_SR_SHIFT) |
4512                    cursor_wm);
4513
4514         /*
4515          * WM3 is unsupported on ILK, probably because we don't have latency
4516          * data for that power state
4517          */
4518 }
4519
4520 void sandybridge_update_wm(struct drm_device *dev)
4521 {
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4524         int fbc_wm, plane_wm, cursor_wm;
4525         unsigned int enabled;
4526
4527         enabled = 0;
4528         if (g4x_compute_wm0(dev, 0,
4529                             &sandybridge_display_wm_info, latency,
4530                             &sandybridge_cursor_wm_info, latency,
4531                             &plane_wm, &cursor_wm)) {
4532                 I915_WRITE(WM0_PIPEA_ILK,
4533                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4534                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4535                               " plane %d, " "cursor: %d\n",
4536                               plane_wm, cursor_wm);
4537                 enabled |= 1;
4538         }
4539
4540         if (g4x_compute_wm0(dev, 1,
4541                             &sandybridge_display_wm_info, latency,
4542                             &sandybridge_cursor_wm_info, latency,
4543                             &plane_wm, &cursor_wm)) {
4544                 I915_WRITE(WM0_PIPEB_ILK,
4545                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547                               " plane %d, cursor: %d\n",
4548                               plane_wm, cursor_wm);
4549                 enabled |= 2;
4550         }
4551
4552         /* IVB has 3 pipes */
4553         if (IS_IVYBRIDGE(dev) &&
4554             g4x_compute_wm0(dev, 2,
4555                             &sandybridge_display_wm_info, latency,
4556                             &sandybridge_cursor_wm_info, latency,
4557                             &plane_wm, &cursor_wm)) {
4558                 I915_WRITE(WM0_PIPEC_IVB,
4559                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4560                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4561                               " plane %d, cursor: %d\n",
4562                               plane_wm, cursor_wm);
4563                 enabled |= 3;
4564         }
4565
4566         /*
4567          * Calculate and update the self-refresh watermark only when one
4568          * display plane is used.
4569          *
4570          * SNB support 3 levels of watermark.
4571          *
4572          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4573          * and disabled in the descending order
4574          *
4575          */
4576         I915_WRITE(WM3_LP_ILK, 0);
4577         I915_WRITE(WM2_LP_ILK, 0);
4578         I915_WRITE(WM1_LP_ILK, 0);
4579
4580         if (!single_plane_enabled(enabled) ||
4581             dev_priv->sprite_scaling_enabled)
4582                 return;
4583         enabled = ffs(enabled) - 1;
4584
4585         /* WM1 */
4586         if (!ironlake_compute_srwm(dev, 1, enabled,
4587                                    SNB_READ_WM1_LATENCY() * 500,
4588                                    &sandybridge_display_srwm_info,
4589                                    &sandybridge_cursor_srwm_info,
4590                                    &fbc_wm, &plane_wm, &cursor_wm))
4591                 return;
4592
4593         I915_WRITE(WM1_LP_ILK,
4594                    WM1_LP_SR_EN |
4595                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4596                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4597                    (plane_wm << WM1_LP_SR_SHIFT) |
4598                    cursor_wm);
4599
4600         /* WM2 */
4601         if (!ironlake_compute_srwm(dev, 2, enabled,
4602                                    SNB_READ_WM2_LATENCY() * 500,
4603                                    &sandybridge_display_srwm_info,
4604                                    &sandybridge_cursor_srwm_info,
4605                                    &fbc_wm, &plane_wm, &cursor_wm))
4606                 return;
4607
4608         I915_WRITE(WM2_LP_ILK,
4609                    WM2_LP_EN |
4610                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4611                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4612                    (plane_wm << WM1_LP_SR_SHIFT) |
4613                    cursor_wm);
4614
4615         /* WM3 */
4616         if (!ironlake_compute_srwm(dev, 3, enabled,
4617                                    SNB_READ_WM3_LATENCY() * 500,
4618                                    &sandybridge_display_srwm_info,
4619                                    &sandybridge_cursor_srwm_info,
4620                                    &fbc_wm, &plane_wm, &cursor_wm))
4621                 return;
4622
4623         I915_WRITE(WM3_LP_ILK,
4624                    WM3_LP_EN |
4625                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4626                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4627                    (plane_wm << WM1_LP_SR_SHIFT) |
4628                    cursor_wm);
4629 }
4630
4631 static bool
4632 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4633                               uint32_t sprite_width, int pixel_size,
4634                               const struct intel_watermark_params *display,
4635                               int display_latency_ns, int *sprite_wm)
4636 {
4637         struct drm_crtc *crtc;
4638         int clock;
4639         int entries, tlb_miss;
4640
4641         crtc = intel_get_crtc_for_plane(dev, plane);
4642         if (crtc->fb == NULL || !crtc->enabled) {
4643                 *sprite_wm = display->guard_size;
4644                 return false;
4645         }
4646
4647         clock = crtc->mode.clock;
4648
4649         /* Use the small buffer method to calculate the sprite watermark */
4650         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4651         tlb_miss = display->fifo_size*display->cacheline_size -
4652                 sprite_width * 8;
4653         if (tlb_miss > 0)
4654                 entries += tlb_miss;
4655         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4656         *sprite_wm = entries + display->guard_size;
4657         if (*sprite_wm > (int)display->max_wm)
4658                 *sprite_wm = display->max_wm;
4659
4660         return true;
4661 }
4662
4663 static bool
4664 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4665                                 uint32_t sprite_width, int pixel_size,
4666                                 const struct intel_watermark_params *display,
4667                                 int latency_ns, int *sprite_wm)
4668 {
4669         struct drm_crtc *crtc;
4670         unsigned long line_time_us;
4671         int clock;
4672         int line_count, line_size;
4673         int small, large;
4674         int entries;
4675
4676         if (!latency_ns) {
4677                 *sprite_wm = 0;
4678                 return false;
4679         }
4680
4681         crtc = intel_get_crtc_for_plane(dev, plane);
4682         clock = crtc->mode.clock;
4683
4684         line_time_us = (sprite_width * 1000) / clock;
4685         line_count = (latency_ns / line_time_us + 1000) / 1000;
4686         line_size = sprite_width * pixel_size;
4687
4688         /* Use the minimum of the small and large buffer method for primary */
4689         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4690         large = line_count * line_size;
4691
4692         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4693         *sprite_wm = entries + display->guard_size;
4694
4695         return *sprite_wm > 0x3ff ? false : true;
4696 }
4697
4698 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4699                                          uint32_t sprite_width, int pixel_size)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4703         int sprite_wm, reg;
4704         int ret;
4705
4706         switch (pipe) {
4707         case 0:
4708                 reg = WM0_PIPEA_ILK;
4709                 break;
4710         case 1:
4711                 reg = WM0_PIPEB_ILK;
4712                 break;
4713         case 2:
4714                 reg = WM0_PIPEC_IVB;
4715                 break;
4716         default:
4717                 return; /* bad pipe */
4718         }
4719
4720         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4721                                             &sandybridge_display_wm_info,
4722                                             latency, &sprite_wm);
4723         if (!ret) {
4724                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4725                               pipe);
4726                 return;
4727         }
4728
4729         I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4730         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4731
4732
4733         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4734                                               pixel_size,
4735                                               &sandybridge_display_srwm_info,
4736                                               SNB_READ_WM1_LATENCY() * 500,
4737                                               &sprite_wm);
4738         if (!ret) {
4739                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4740                               pipe);
4741                 return;
4742         }
4743         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4744
4745         /* Only IVB has two more LP watermarks for sprite */
4746         if (!IS_IVYBRIDGE(dev))
4747                 return;
4748
4749         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4750                                               pixel_size,
4751                                               &sandybridge_display_srwm_info,
4752                                               SNB_READ_WM2_LATENCY() * 500,
4753                                               &sprite_wm);
4754         if (!ret) {
4755                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4756                               pipe);
4757                 return;
4758         }
4759         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4760
4761         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4762                                               pixel_size,
4763                                               &sandybridge_display_srwm_info,
4764                                               SNB_READ_WM3_LATENCY() * 500,
4765                                               &sprite_wm);
4766         if (!ret) {
4767                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4768                               pipe);
4769                 return;
4770         }
4771         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4772 }
4773
4774 /**
4775  * intel_update_watermarks - update FIFO watermark values based on current modes
4776  *
4777  * Calculate watermark values for the various WM regs based on current mode
4778  * and plane configuration.
4779  *
4780  * There are several cases to deal with here:
4781  *   - normal (i.e. non-self-refresh)
4782  *   - self-refresh (SR) mode
4783  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4784  *   - lines are small relative to FIFO size (buffer can hold more than 2
4785  *     lines), so need to account for TLB latency
4786  *
4787  *   The normal calculation is:
4788  *     watermark = dotclock * bytes per pixel * latency
4789  *   where latency is platform & configuration dependent (we assume pessimal
4790  *   values here).
4791  *
4792  *   The SR calculation is:
4793  *     watermark = (trunc(latency/line time)+1) * surface width *
4794  *       bytes per pixel
4795  *   where
4796  *     line time = htotal / dotclock
4797  *     surface width = hdisplay for normal plane and 64 for cursor
4798  *   and latency is assumed to be high, as above.
4799  *
4800  * The final value programmed to the register should always be rounded up,
4801  * and include an extra 2 entries to account for clock crossings.
4802  *
4803  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4804  * to set the non-SR watermarks to 8.
4805  */
4806 static void intel_update_watermarks(struct drm_device *dev)
4807 {
4808         struct drm_i915_private *dev_priv = dev->dev_private;
4809
4810         if (dev_priv->display.update_wm)
4811                 dev_priv->display.update_wm(dev);
4812 }
4813
4814 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4815                                     uint32_t sprite_width, int pixel_size)
4816 {
4817         struct drm_i915_private *dev_priv = dev->dev_private;
4818
4819         if (dev_priv->display.update_sprite_wm)
4820                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4821                                                    pixel_size);
4822 }
4823
4824 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4825 {
4826         if (i915_panel_use_ssc >= 0)
4827                 return i915_panel_use_ssc != 0;
4828         return dev_priv->lvds_use_ssc
4829                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4830 }
4831
4832 /**
4833  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4834  * @crtc: CRTC structure
4835  * @mode: requested mode
4836  *
4837  * A pipe may be connected to one or more outputs.  Based on the depth of the
4838  * attached framebuffer, choose a good color depth to use on the pipe.
4839  *
4840  * If possible, match the pipe depth to the fb depth.  In some cases, this
4841  * isn't ideal, because the connected output supports a lesser or restricted
4842  * set of depths.  Resolve that here:
4843  *    LVDS typically supports only 6bpc, so clamp down in that case
4844  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4845  *    Displays may support a restricted set as well, check EDID and clamp as
4846  *      appropriate.
4847  *    DP may want to dither down to 6bpc to fit larger modes
4848  *
4849  * RETURNS:
4850  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4851  * true if they don't match).
4852  */
4853 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4854                                          unsigned int *pipe_bpp,
4855                                          struct drm_display_mode *mode)
4856 {
4857         struct drm_device *dev = crtc->dev;
4858         struct drm_i915_private *dev_priv = dev->dev_private;
4859         struct drm_encoder *encoder;
4860         struct drm_connector *connector;
4861         unsigned int display_bpc = UINT_MAX, bpc;
4862
4863         /* Walk the encoders & connectors on this crtc, get min bpc */
4864         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4865                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4866
4867                 if (encoder->crtc != crtc)
4868                         continue;
4869
4870                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4871                         unsigned int lvds_bpc;
4872
4873                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4874                             LVDS_A3_POWER_UP)
4875                                 lvds_bpc = 8;
4876                         else
4877                                 lvds_bpc = 6;
4878
4879                         if (lvds_bpc < display_bpc) {
4880                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4881                                 display_bpc = lvds_bpc;
4882                         }
4883                         continue;
4884                 }
4885
4886                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4887                         /* Use VBT settings if we have an eDP panel */
4888                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4889
4890                         if (edp_bpc < display_bpc) {
4891                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4892                                 display_bpc = edp_bpc;
4893                         }
4894                         continue;
4895                 }
4896
4897                 /* Not one of the known troublemakers, check the EDID */
4898                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4899                                     head) {
4900                         if (connector->encoder != encoder)
4901                                 continue;
4902
4903                         /* Don't use an invalid EDID bpc value */
4904                         if (connector->display_info.bpc &&
4905                             connector->display_info.bpc < display_bpc) {
4906                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4907                                 display_bpc = connector->display_info.bpc;
4908                         }
4909                 }
4910
4911                 /*
4912                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4913                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4914                  */
4915                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4916                         if (display_bpc > 8 && display_bpc < 12) {
4917                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4918                                 display_bpc = 12;
4919                         } else {
4920                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4921                                 display_bpc = 8;
4922                         }
4923                 }
4924         }
4925
4926         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4927                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4928                 display_bpc = 6;
4929         }
4930
4931         /*
4932          * We could just drive the pipe at the highest bpc all the time and
4933          * enable dithering as needed, but that costs bandwidth.  So choose
4934          * the minimum value that expresses the full color range of the fb but
4935          * also stays within the max display bpc discovered above.
4936          */
4937
4938         switch (crtc->fb->depth) {
4939         case 8:
4940                 bpc = 8; /* since we go through a colormap */
4941                 break;
4942         case 15:
4943         case 16:
4944                 bpc = 6; /* min is 18bpp */
4945                 break;
4946         case 24:
4947                 bpc = 8;
4948                 break;
4949         case 30:
4950                 bpc = 10;
4951                 break;
4952         case 48:
4953                 bpc = 12;
4954                 break;
4955         default:
4956                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4957                 bpc = min((unsigned int)8, display_bpc);
4958                 break;
4959         }
4960
4961         display_bpc = min(display_bpc, bpc);
4962
4963         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4964                       bpc, display_bpc);
4965
4966         *pipe_bpp = display_bpc * 3;
4967
4968         return display_bpc != bpc;
4969 }
4970
4971 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4972                               struct drm_display_mode *mode,
4973                               struct drm_display_mode *adjusted_mode,
4974                               int x, int y,
4975                               struct drm_framebuffer *old_fb)
4976 {
4977         struct drm_device *dev = crtc->dev;
4978         struct drm_i915_private *dev_priv = dev->dev_private;
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         int pipe = intel_crtc->pipe;
4981         int plane = intel_crtc->plane;
4982         int refclk, num_connectors = 0;
4983         intel_clock_t clock, reduced_clock;
4984         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4985         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4986         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4987         struct drm_mode_config *mode_config = &dev->mode_config;
4988         struct intel_encoder *encoder;
4989         const intel_limit_t *limit;
4990         int ret;
4991         u32 temp;
4992         u32 lvds_sync = 0;
4993
4994         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4995                 if (encoder->base.crtc != crtc)
4996                         continue;
4997
4998                 switch (encoder->type) {
4999                 case INTEL_OUTPUT_LVDS:
5000                         is_lvds = true;
5001                         break;
5002                 case INTEL_OUTPUT_SDVO:
5003                 case INTEL_OUTPUT_HDMI:
5004                         is_sdvo = true;
5005                         if (encoder->needs_tv_clock)
5006                                 is_tv = true;
5007                         break;
5008                 case INTEL_OUTPUT_DVO:
5009                         is_dvo = true;
5010                         break;
5011                 case INTEL_OUTPUT_TVOUT:
5012                         is_tv = true;
5013                         break;
5014                 case INTEL_OUTPUT_ANALOG:
5015                         is_crt = true;
5016                         break;
5017                 case INTEL_OUTPUT_DISPLAYPORT:
5018                         is_dp = true;
5019                         break;
5020                 }
5021
5022                 num_connectors++;
5023         }
5024
5025         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5026                 refclk = dev_priv->lvds_ssc_freq * 1000;
5027                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5028                               refclk / 1000);
5029         } else if (!IS_GEN2(dev)) {
5030                 refclk = 96000;
5031         } else {
5032                 refclk = 48000;
5033         }
5034
5035         /*
5036          * Returns a set of divisors for the desired target clock with the given
5037          * refclk, or FALSE.  The returned values represent the clock equation:
5038          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5039          */
5040         limit = intel_limit(crtc, refclk);
5041         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5042         if (!ok) {
5043                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5044                 return -EINVAL;
5045         }
5046
5047         /* Ensure that the cursor is valid for the new mode before changing... */
5048         intel_crtc_update_cursor(crtc, true);
5049
5050         if (is_lvds && dev_priv->lvds_downclock_avail) {
5051                 has_reduced_clock = limit->find_pll(limit, crtc,
5052                                                     dev_priv->lvds_downclock,
5053                                                     refclk,
5054                                                     &reduced_clock);
5055                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5056                         /*
5057                          * If the different P is found, it means that we can't
5058                          * switch the display clock by using the FP0/FP1.
5059                          * In such case we will disable the LVDS downclock
5060                          * feature.
5061                          */
5062                         DRM_DEBUG_KMS("Different P is found for "
5063                                       "LVDS clock/downclock\n");
5064                         has_reduced_clock = 0;
5065                 }
5066         }
5067         /* SDVO TV has fixed PLL values depend on its clock range,
5068            this mirrors vbios setting. */
5069         if (is_sdvo && is_tv) {
5070                 if (adjusted_mode->clock >= 100000
5071                     && adjusted_mode->clock < 140500) {
5072                         clock.p1 = 2;
5073                         clock.p2 = 10;
5074                         clock.n = 3;
5075                         clock.m1 = 16;
5076                         clock.m2 = 8;
5077                 } else if (adjusted_mode->clock >= 140500
5078                            && adjusted_mode->clock <= 200000) {
5079                         clock.p1 = 1;
5080                         clock.p2 = 10;
5081                         clock.n = 6;
5082                         clock.m1 = 12;
5083                         clock.m2 = 8;
5084                 }
5085         }
5086
5087         if (IS_PINEVIEW(dev)) {
5088                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
5089                 if (has_reduced_clock)
5090                         fp2 = (1 << reduced_clock.n) << 16 |
5091                                 reduced_clock.m1 << 8 | reduced_clock.m2;
5092         } else {
5093                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5094                 if (has_reduced_clock)
5095                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5096                                 reduced_clock.m2;
5097         }
5098
5099         dpll = DPLL_VGA_MODE_DIS;
5100
5101         if (!IS_GEN2(dev)) {
5102                 if (is_lvds)
5103                         dpll |= DPLLB_MODE_LVDS;
5104                 else
5105                         dpll |= DPLLB_MODE_DAC_SERIAL;
5106                 if (is_sdvo) {
5107                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5108                         if (pixel_multiplier > 1) {
5109                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5110                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5111                         }
5112                         dpll |= DPLL_DVO_HIGH_SPEED;
5113                 }
5114                 if (is_dp)
5115                         dpll |= DPLL_DVO_HIGH_SPEED;
5116
5117                 /* compute bitmask from p1 value */
5118                 if (IS_PINEVIEW(dev))
5119                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5120                 else {
5121                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5122                         if (IS_G4X(dev) && has_reduced_clock)
5123                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5124                 }
5125                 switch (clock.p2) {
5126                 case 5:
5127                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5128                         break;
5129                 case 7:
5130                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5131                         break;
5132                 case 10:
5133                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5134                         break;
5135                 case 14:
5136                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5137                         break;
5138                 }
5139                 if (INTEL_INFO(dev)->gen >= 4)
5140                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5141         } else {
5142                 if (is_lvds) {
5143                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5144                 } else {
5145                         if (clock.p1 == 2)
5146                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5147                         else
5148                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5149                         if (clock.p2 == 4)
5150                                 dpll |= PLL_P2_DIVIDE_BY_4;
5151                 }
5152         }
5153
5154         if (is_sdvo && is_tv)
5155                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5156         else if (is_tv)
5157                 /* XXX: just matching BIOS for now */
5158                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5159                 dpll |= 3;
5160         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5161                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5162         else
5163                 dpll |= PLL_REF_INPUT_DREFCLK;
5164
5165         /* setup pipeconf */
5166         pipeconf = I915_READ(PIPECONF(pipe));
5167
5168         /* Set up the display plane register */
5169         dspcntr = DISPPLANE_GAMMA_ENABLE;
5170
5171         /* Ironlake's plane is forced to pipe, bit 24 is to
5172            enable color space conversion */
5173         if (pipe == 0)
5174                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5175         else
5176                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5177
5178         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5179                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5180                  * core speed.
5181                  *
5182                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5183                  * pipe == 0 check?
5184                  */
5185                 if (mode->clock >
5186                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5187                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5188                 else
5189                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5190         }
5191
5192         /* default to 8bpc */
5193         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5194         if (is_dp) {
5195                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5196                         pipeconf |= PIPECONF_BPP_6 |
5197                                     PIPECONF_DITHER_EN |
5198                                     PIPECONF_DITHER_TYPE_SP;
5199                 }
5200         }
5201
5202         dpll |= DPLL_VCO_ENABLE;
5203
5204         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5205         drm_mode_debug_printmodeline(mode);
5206
5207         I915_WRITE(FP0(pipe), fp);
5208         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5209
5210         POSTING_READ(DPLL(pipe));
5211         udelay(150);
5212
5213         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5214          * This is an exception to the general rule that mode_set doesn't turn
5215          * things on.
5216          */
5217         if (is_lvds) {
5218                 temp = I915_READ(LVDS);
5219                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5220                 if (pipe == 1) {
5221                         temp |= LVDS_PIPEB_SELECT;
5222                 } else {
5223                         temp &= ~LVDS_PIPEB_SELECT;
5224                 }
5225                 /* set the corresponsding LVDS_BORDER bit */
5226                 temp |= dev_priv->lvds_border_bits;
5227                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5228                  * set the DPLLs for dual-channel mode or not.
5229                  */
5230                 if (clock.p2 == 7)
5231                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5232                 else
5233                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5234
5235                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5236                  * appropriately here, but we need to look more thoroughly into how
5237                  * panels behave in the two modes.
5238                  */
5239                 /* set the dithering flag on LVDS as needed */
5240                 if (INTEL_INFO(dev)->gen >= 4) {
5241                         if (dev_priv->lvds_dither)
5242                                 temp |= LVDS_ENABLE_DITHER;
5243                         else
5244                                 temp &= ~LVDS_ENABLE_DITHER;
5245                 }
5246                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5247                         lvds_sync |= LVDS_HSYNC_POLARITY;
5248                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5249                         lvds_sync |= LVDS_VSYNC_POLARITY;
5250                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5251                     != lvds_sync) {
5252                         char flags[2] = "-+";
5253                         DRM_INFO("Changing LVDS panel from "
5254                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5255                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5256                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5257                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5258                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5259                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5260                         temp |= lvds_sync;
5261                 }
5262                 I915_WRITE(LVDS, temp);
5263         }
5264
5265         if (is_dp) {
5266                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5267         }
5268
5269         I915_WRITE(DPLL(pipe), dpll);
5270
5271         /* Wait for the clocks to stabilize. */
5272         POSTING_READ(DPLL(pipe));
5273         udelay(150);
5274
5275         if (INTEL_INFO(dev)->gen >= 4) {
5276                 temp = 0;
5277                 if (is_sdvo) {
5278                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5279                         if (temp > 1)
5280                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5281                         else
5282                                 temp = 0;
5283                 }
5284                 I915_WRITE(DPLL_MD(pipe), temp);
5285         } else {
5286                 /* The pixel multiplier can only be updated once the
5287                  * DPLL is enabled and the clocks are stable.
5288                  *
5289                  * So write it again.
5290                  */
5291                 I915_WRITE(DPLL(pipe), dpll);
5292         }
5293
5294         intel_crtc->lowfreq_avail = false;
5295         if (is_lvds && has_reduced_clock && i915_powersave) {
5296                 I915_WRITE(FP1(pipe), fp2);
5297                 intel_crtc->lowfreq_avail = true;
5298                 if (HAS_PIPE_CXSR(dev)) {
5299                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5300                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5301                 }
5302         } else {
5303                 I915_WRITE(FP1(pipe), fp);
5304                 if (HAS_PIPE_CXSR(dev)) {
5305                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5306                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5307                 }
5308         }
5309
5310         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5311         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5312                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5313                 /* the chip adds 2 halflines automatically */
5314                 adjusted_mode->crtc_vdisplay -= 1;
5315                 adjusted_mode->crtc_vtotal -= 1;
5316                 adjusted_mode->crtc_vblank_start -= 1;
5317                 adjusted_mode->crtc_vblank_end -= 1;
5318                 adjusted_mode->crtc_vsync_end -= 1;
5319                 adjusted_mode->crtc_vsync_start -= 1;
5320         } else
5321                 pipeconf |= PIPECONF_PROGRESSIVE;
5322
5323         I915_WRITE(HTOTAL(pipe),
5324                    (adjusted_mode->crtc_hdisplay - 1) |
5325                    ((adjusted_mode->crtc_htotal - 1) << 16));
5326         I915_WRITE(HBLANK(pipe),
5327                    (adjusted_mode->crtc_hblank_start - 1) |
5328                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5329         I915_WRITE(HSYNC(pipe),
5330                    (adjusted_mode->crtc_hsync_start - 1) |
5331                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5332
5333         I915_WRITE(VTOTAL(pipe),
5334                    (adjusted_mode->crtc_vdisplay - 1) |
5335                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5336         I915_WRITE(VBLANK(pipe),
5337                    (adjusted_mode->crtc_vblank_start - 1) |
5338                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5339         I915_WRITE(VSYNC(pipe),
5340                    (adjusted_mode->crtc_vsync_start - 1) |
5341                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5342
5343         /* pipesrc and dspsize control the size that is scaled from,
5344          * which should always be the user's requested size.
5345          */
5346         I915_WRITE(DSPSIZE(plane),
5347                    ((mode->vdisplay - 1) << 16) |
5348                    (mode->hdisplay - 1));
5349         I915_WRITE(DSPPOS(plane), 0);
5350         I915_WRITE(PIPESRC(pipe),
5351                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5352
5353         I915_WRITE(PIPECONF(pipe), pipeconf);
5354         POSTING_READ(PIPECONF(pipe));
5355         intel_enable_pipe(dev_priv, pipe, false);
5356
5357         intel_wait_for_vblank(dev, pipe);
5358
5359         I915_WRITE(DSPCNTR(plane), dspcntr);
5360         POSTING_READ(DSPCNTR(plane));
5361         intel_enable_plane(dev_priv, plane, pipe);
5362
5363         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5364
5365         intel_update_watermarks(dev);
5366
5367         return ret;
5368 }
5369
5370 /*
5371  * Initialize reference clocks when the driver loads
5372  */
5373 void ironlake_init_pch_refclk(struct drm_device *dev)
5374 {
5375         struct drm_i915_private *dev_priv = dev->dev_private;
5376         struct drm_mode_config *mode_config = &dev->mode_config;
5377         struct intel_encoder *encoder;
5378         u32 temp;
5379         bool has_lvds = false;
5380         bool has_cpu_edp = false;
5381         bool has_pch_edp = false;
5382         bool has_panel = false;
5383         bool has_ck505 = false;
5384         bool can_ssc = false;
5385
5386         /* We need to take the global config into account */
5387         list_for_each_entry(encoder, &mode_config->encoder_list,
5388                             base.head) {
5389                 switch (encoder->type) {
5390                 case INTEL_OUTPUT_LVDS:
5391                         has_panel = true;
5392                         has_lvds = true;
5393                         break;
5394                 case INTEL_OUTPUT_EDP:
5395                         has_panel = true;
5396                         if (intel_encoder_is_pch_edp(&encoder->base))
5397                                 has_pch_edp = true;
5398                         else
5399                                 has_cpu_edp = true;
5400                         break;
5401                 }
5402         }
5403
5404         if (HAS_PCH_IBX(dev)) {
5405                 has_ck505 = dev_priv->display_clock_mode;
5406                 can_ssc = has_ck505;
5407         } else {
5408                 has_ck505 = false;
5409                 can_ssc = true;
5410         }
5411
5412         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5413                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5414                       has_ck505);
5415
5416         /* Ironlake: try to setup display ref clock before DPLL
5417          * enabling. This is only under driver's control after
5418          * PCH B stepping, previous chipset stepping should be
5419          * ignoring this setting.
5420          */
5421         temp = I915_READ(PCH_DREF_CONTROL);
5422         /* Always enable nonspread source */
5423         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5424
5425         if (has_ck505)
5426                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5427         else
5428                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5429
5430         if (has_panel) {
5431                 temp &= ~DREF_SSC_SOURCE_MASK;
5432                 temp |= DREF_SSC_SOURCE_ENABLE;
5433
5434                 /* SSC must be turned on before enabling the CPU output  */
5435                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5436                         DRM_DEBUG_KMS("Using SSC on panel\n");
5437                         temp |= DREF_SSC1_ENABLE;
5438                 }
5439
5440                 /* Get SSC going before enabling the outputs */
5441                 I915_WRITE(PCH_DREF_CONTROL, temp);
5442                 POSTING_READ(PCH_DREF_CONTROL);
5443                 udelay(200);
5444
5445                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5446
5447                 /* Enable CPU source on CPU attached eDP */
5448                 if (has_cpu_edp) {
5449                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5450                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5451                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5452                         }
5453                         else
5454                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5455                 } else
5456                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5457
5458                 I915_WRITE(PCH_DREF_CONTROL, temp);
5459                 POSTING_READ(PCH_DREF_CONTROL);
5460                 udelay(200);
5461         } else {
5462                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5463
5464                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5465
5466                 /* Turn off CPU output */
5467                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5468
5469                 I915_WRITE(PCH_DREF_CONTROL, temp);
5470                 POSTING_READ(PCH_DREF_CONTROL);
5471                 udelay(200);
5472
5473                 /* Turn off the SSC source */
5474                 temp &= ~DREF_SSC_SOURCE_MASK;
5475                 temp |= DREF_SSC_SOURCE_DISABLE;
5476
5477                 /* Turn off SSC1 */
5478                 temp &= ~ DREF_SSC1_ENABLE;
5479
5480                 I915_WRITE(PCH_DREF_CONTROL, temp);
5481                 POSTING_READ(PCH_DREF_CONTROL);
5482                 udelay(200);
5483         }
5484 }
5485
5486 static int ironlake_get_refclk(struct drm_crtc *crtc)
5487 {
5488         struct drm_device *dev = crtc->dev;
5489         struct drm_i915_private *dev_priv = dev->dev_private;
5490         struct intel_encoder *encoder;
5491         struct drm_mode_config *mode_config = &dev->mode_config;
5492         struct intel_encoder *edp_encoder = NULL;
5493         int num_connectors = 0;
5494         bool is_lvds = false;
5495
5496         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5497                 if (encoder->base.crtc != crtc)
5498                         continue;
5499
5500                 switch (encoder->type) {
5501                 case INTEL_OUTPUT_LVDS:
5502                         is_lvds = true;
5503                         break;
5504                 case INTEL_OUTPUT_EDP:
5505                         edp_encoder = encoder;
5506                         break;
5507                 }
5508                 num_connectors++;
5509         }
5510
5511         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5512                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5513                               dev_priv->lvds_ssc_freq);
5514                 return dev_priv->lvds_ssc_freq * 1000;
5515         }
5516
5517         return 120000;
5518 }
5519
5520 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5521                                   struct drm_display_mode *mode,
5522                                   struct drm_display_mode *adjusted_mode,
5523                                   int x, int y,
5524                                   struct drm_framebuffer *old_fb)
5525 {
5526         struct drm_device *dev = crtc->dev;
5527         struct drm_i915_private *dev_priv = dev->dev_private;
5528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5529         int pipe = intel_crtc->pipe;
5530         int plane = intel_crtc->plane;
5531         int refclk, num_connectors = 0;
5532         intel_clock_t clock, reduced_clock;
5533         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5534         bool ok, has_reduced_clock = false, is_sdvo = false;
5535         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5536         struct intel_encoder *has_edp_encoder = NULL;
5537         struct drm_mode_config *mode_config = &dev->mode_config;
5538         struct intel_encoder *encoder;
5539         const intel_limit_t *limit;
5540         int ret;
5541         struct fdi_m_n m_n = {0};
5542         u32 temp;
5543         u32 lvds_sync = 0;
5544         int target_clock, pixel_multiplier, lane, link_bw, factor;
5545         unsigned int pipe_bpp;
5546         bool dither;
5547
5548         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5549                 if (encoder->base.crtc != crtc)
5550                         continue;
5551
5552                 switch (encoder->type) {
5553                 case INTEL_OUTPUT_LVDS:
5554                         is_lvds = true;
5555                         break;
5556                 case INTEL_OUTPUT_SDVO:
5557                 case INTEL_OUTPUT_HDMI:
5558                         is_sdvo = true;
5559                         if (encoder->needs_tv_clock)
5560                                 is_tv = true;
5561                         break;
5562                 case INTEL_OUTPUT_TVOUT:
5563                         is_tv = true;
5564                         break;
5565                 case INTEL_OUTPUT_ANALOG:
5566                         is_crt = true;
5567                         break;
5568                 case INTEL_OUTPUT_DISPLAYPORT:
5569                         is_dp = true;
5570                         break;
5571                 case INTEL_OUTPUT_EDP:
5572                         has_edp_encoder = encoder;
5573                         break;
5574                 }
5575
5576                 num_connectors++;
5577         }
5578
5579         refclk = ironlake_get_refclk(crtc);
5580
5581         /*
5582          * Returns a set of divisors for the desired target clock with the given
5583          * refclk, or FALSE.  The returned values represent the clock equation:
5584          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5585          */
5586         limit = intel_limit(crtc, refclk);
5587         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5588         if (!ok) {
5589                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5590                 return -EINVAL;
5591         }
5592
5593         /* Ensure that the cursor is valid for the new mode before changing... */
5594         intel_crtc_update_cursor(crtc, true);
5595
5596         if (is_lvds && dev_priv->lvds_downclock_avail) {
5597                 has_reduced_clock = limit->find_pll(limit, crtc,
5598                                                     dev_priv->lvds_downclock,
5599                                                     refclk,
5600                                                     &reduced_clock);
5601                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5602                         /*
5603                          * If the different P is found, it means that we can't
5604                          * switch the display clock by using the FP0/FP1.
5605                          * In such case we will disable the LVDS downclock
5606                          * feature.
5607                          */
5608                         DRM_DEBUG_KMS("Different P is found for "
5609                                       "LVDS clock/downclock\n");
5610                         has_reduced_clock = 0;
5611                 }
5612         }
5613         /* SDVO TV has fixed PLL values depend on its clock range,
5614            this mirrors vbios setting. */
5615         if (is_sdvo && is_tv) {
5616                 if (adjusted_mode->clock >= 100000
5617                     && adjusted_mode->clock < 140500) {
5618                         clock.p1 = 2;
5619                         clock.p2 = 10;
5620                         clock.n = 3;
5621                         clock.m1 = 16;
5622                         clock.m2 = 8;
5623                 } else if (adjusted_mode->clock >= 140500
5624                            && adjusted_mode->clock <= 200000) {
5625                         clock.p1 = 1;
5626                         clock.p2 = 10;
5627                         clock.n = 6;
5628                         clock.m1 = 12;
5629                         clock.m2 = 8;
5630                 }
5631         }
5632
5633         /* FDI link */
5634         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5635         lane = 0;
5636         /* CPU eDP doesn't require FDI link, so just set DP M/N
5637            according to current link config */
5638         if (has_edp_encoder &&
5639             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5640                 target_clock = mode->clock;
5641                 intel_edp_link_config(has_edp_encoder,
5642                                       &lane, &link_bw);
5643         } else {
5644                 /* [e]DP over FDI requires target mode clock
5645                    instead of link clock */
5646                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5647                         target_clock = mode->clock;
5648                 else
5649                         target_clock = adjusted_mode->clock;
5650
5651                 /* FDI is a binary signal running at ~2.7GHz, encoding
5652                  * each output octet as 10 bits. The actual frequency
5653                  * is stored as a divider into a 100MHz clock, and the
5654                  * mode pixel clock is stored in units of 1KHz.
5655                  * Hence the bw of each lane in terms of the mode signal
5656                  * is:
5657                  */
5658                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5659         }
5660
5661         /* determine panel color depth */
5662         temp = I915_READ(PIPECONF(pipe));
5663         temp &= ~PIPE_BPC_MASK;
5664         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5665         switch (pipe_bpp) {
5666         case 18:
5667                 temp |= PIPE_6BPC;
5668                 break;
5669         case 24:
5670                 temp |= PIPE_8BPC;
5671                 break;
5672         case 30:
5673                 temp |= PIPE_10BPC;
5674                 break;
5675         case 36:
5676                 temp |= PIPE_12BPC;
5677                 break;
5678         default:
5679                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5680                         pipe_bpp);
5681                 temp |= PIPE_8BPC;
5682                 pipe_bpp = 24;
5683                 break;
5684         }
5685
5686         intel_crtc->bpp = pipe_bpp;
5687         I915_WRITE(PIPECONF(pipe), temp);
5688
5689         if (!lane) {
5690                 /*
5691                  * Account for spread spectrum to avoid
5692                  * oversubscribing the link. Max center spread
5693                  * is 2.5%; use 5% for safety's sake.
5694                  */
5695                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5696                 lane = bps / (link_bw * 8) + 1;
5697         }
5698
5699         intel_crtc->fdi_lanes = lane;
5700
5701         if (pixel_multiplier > 1)
5702                 link_bw *= pixel_multiplier;
5703         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5704                              &m_n);
5705
5706         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5707         if (has_reduced_clock)
5708                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5709                         reduced_clock.m2;
5710
5711         /* Enable autotuning of the PLL clock (if permissible) */
5712         factor = 21;
5713         if (is_lvds) {
5714                 if ((intel_panel_use_ssc(dev_priv) &&
5715                      dev_priv->lvds_ssc_freq == 100) ||
5716                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5717                         factor = 25;
5718         } else if (is_sdvo && is_tv)
5719                 factor = 20;
5720
5721         if (clock.m < factor * clock.n)
5722                 fp |= FP_CB_TUNE;
5723
5724         dpll = 0;
5725
5726         if (is_lvds)
5727                 dpll |= DPLLB_MODE_LVDS;
5728         else
5729                 dpll |= DPLLB_MODE_DAC_SERIAL;
5730         if (is_sdvo) {
5731                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5732                 if (pixel_multiplier > 1) {
5733                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5734                 }
5735                 dpll |= DPLL_DVO_HIGH_SPEED;
5736         }
5737         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5738                 dpll |= DPLL_DVO_HIGH_SPEED;
5739
5740         /* compute bitmask from p1 value */
5741         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5742         /* also FPA1 */
5743         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5744
5745         switch (clock.p2) {
5746         case 5:
5747                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5748                 break;
5749         case 7:
5750                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5751                 break;
5752         case 10:
5753                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5754                 break;
5755         case 14:
5756                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5757                 break;
5758         }
5759
5760         if (is_sdvo && is_tv)
5761                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5762         else if (is_tv)
5763                 /* XXX: just matching BIOS for now */
5764                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5765                 dpll |= 3;
5766         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5767                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5768         else
5769                 dpll |= PLL_REF_INPUT_DREFCLK;
5770
5771         /* setup pipeconf */
5772         pipeconf = I915_READ(PIPECONF(pipe));
5773
5774         /* Set up the display plane register */
5775         dspcntr = DISPPLANE_GAMMA_ENABLE;
5776
5777         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5778         drm_mode_debug_printmodeline(mode);
5779
5780         /* PCH eDP needs FDI, but CPU eDP does not */
5781         if (!intel_crtc->no_pll) {
5782                 if (!has_edp_encoder ||
5783                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5784                         I915_WRITE(PCH_FP0(pipe), fp);
5785                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5786
5787                         POSTING_READ(PCH_DPLL(pipe));
5788                         udelay(150);
5789                 }
5790         } else {
5791                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5792                     fp == I915_READ(PCH_FP0(0))) {
5793                         intel_crtc->use_pll_a = true;
5794                         DRM_DEBUG_KMS("using pipe a dpll\n");
5795                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5796                            fp == I915_READ(PCH_FP0(1))) {
5797                         intel_crtc->use_pll_a = false;
5798                         DRM_DEBUG_KMS("using pipe b dpll\n");
5799                 } else {
5800                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5801                         return -EINVAL;
5802                 }
5803         }
5804
5805         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5806          * This is an exception to the general rule that mode_set doesn't turn
5807          * things on.
5808          */
5809         if (is_lvds) {
5810                 temp = I915_READ(PCH_LVDS);
5811                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5812                 if (HAS_PCH_CPT(dev)) {
5813                         temp &= ~PORT_TRANS_SEL_MASK;
5814                         temp |= PORT_TRANS_SEL_CPT(pipe);
5815                 } else {
5816                         if (pipe == 1)
5817                                 temp |= LVDS_PIPEB_SELECT;
5818                         else
5819                                 temp &= ~LVDS_PIPEB_SELECT;
5820                 }
5821
5822                 /* set the corresponsding LVDS_BORDER bit */
5823                 temp |= dev_priv->lvds_border_bits;
5824                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5825                  * set the DPLLs for dual-channel mode or not.
5826                  */
5827                 if (clock.p2 == 7)
5828                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5829                 else
5830                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5831
5832                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5833                  * appropriately here, but we need to look more thoroughly into how
5834                  * panels behave in the two modes.
5835                  */
5836                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5837                         lvds_sync |= LVDS_HSYNC_POLARITY;
5838                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5839                         lvds_sync |= LVDS_VSYNC_POLARITY;
5840                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5841                     != lvds_sync) {
5842                         char flags[2] = "-+";
5843                         DRM_INFO("Changing LVDS panel from "
5844                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5845                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5846                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5847                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5848                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5849                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5850                         temp |= lvds_sync;
5851                 }
5852                 I915_WRITE(PCH_LVDS, temp);
5853         }
5854
5855         pipeconf &= ~PIPECONF_DITHER_EN;
5856         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5857         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5858                 pipeconf |= PIPECONF_DITHER_EN;
5859                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5860         }
5861         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5862                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5863         } else {
5864                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5865                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5866                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5867                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5868                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5869         }
5870
5871         if (!intel_crtc->no_pll &&
5872             (!has_edp_encoder ||
5873              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5874                 I915_WRITE(PCH_DPLL(pipe), dpll);
5875
5876                 /* Wait for the clocks to stabilize. */
5877                 POSTING_READ(PCH_DPLL(pipe));
5878                 udelay(150);
5879
5880                 /* The pixel multiplier can only be updated once the
5881                  * DPLL is enabled and the clocks are stable.
5882                  *
5883                  * So write it again.
5884                  */
5885                 I915_WRITE(PCH_DPLL(pipe), dpll);
5886         }
5887
5888         intel_crtc->lowfreq_avail = false;
5889         if (!intel_crtc->no_pll) {
5890                 if (is_lvds && has_reduced_clock && i915_powersave) {
5891                         I915_WRITE(PCH_FP1(pipe), fp2);
5892                         intel_crtc->lowfreq_avail = true;
5893                         if (HAS_PIPE_CXSR(dev)) {
5894                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5895                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5896                         }
5897                 } else {
5898                         I915_WRITE(PCH_FP1(pipe), fp);
5899                         if (HAS_PIPE_CXSR(dev)) {
5900                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5901                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5902                         }
5903                 }
5904         }
5905
5906         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5907         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5908                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5909                 /* the chip adds 2 halflines automatically */
5910                 adjusted_mode->crtc_vdisplay -= 1;
5911                 adjusted_mode->crtc_vtotal -= 1;
5912                 adjusted_mode->crtc_vblank_start -= 1;
5913                 adjusted_mode->crtc_vblank_end -= 1;
5914                 adjusted_mode->crtc_vsync_end -= 1;
5915                 adjusted_mode->crtc_vsync_start -= 1;
5916         } else
5917                 pipeconf |= PIPECONF_PROGRESSIVE;
5918
5919         I915_WRITE(HTOTAL(pipe),
5920                    (adjusted_mode->crtc_hdisplay - 1) |
5921                    ((adjusted_mode->crtc_htotal - 1) << 16));
5922         I915_WRITE(HBLANK(pipe),
5923                    (adjusted_mode->crtc_hblank_start - 1) |
5924                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5925         I915_WRITE(HSYNC(pipe),
5926                    (adjusted_mode->crtc_hsync_start - 1) |
5927                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5928
5929         I915_WRITE(VTOTAL(pipe),
5930                    (adjusted_mode->crtc_vdisplay - 1) |
5931                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5932         I915_WRITE(VBLANK(pipe),
5933                    (adjusted_mode->crtc_vblank_start - 1) |
5934                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5935         I915_WRITE(VSYNC(pipe),
5936                    (adjusted_mode->crtc_vsync_start - 1) |
5937                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5938
5939         /* pipesrc controls the size that is scaled from, which should
5940          * always be the user's requested size.
5941          */
5942         I915_WRITE(PIPESRC(pipe),
5943                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5944
5945         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5946         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5947         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5948         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5949
5950         if (has_edp_encoder &&
5951             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5952                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5953         }
5954
5955         I915_WRITE(PIPECONF(pipe), pipeconf);
5956         POSTING_READ(PIPECONF(pipe));
5957
5958         intel_wait_for_vblank(dev, pipe);
5959
5960         if (IS_GEN5(dev)) {
5961                 /* enable address swizzle for tiling buffer */
5962                 temp = I915_READ(DISP_ARB_CTL);
5963                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5964         }
5965
5966         I915_WRITE(DSPCNTR(plane), dspcntr);
5967         POSTING_READ(DSPCNTR(plane));
5968
5969         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5970
5971         intel_update_watermarks(dev);
5972
5973         return ret;
5974 }
5975
5976 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5977                                struct drm_display_mode *mode,
5978                                struct drm_display_mode *adjusted_mode,
5979                                int x, int y,
5980                                struct drm_framebuffer *old_fb)
5981 {
5982         struct drm_device *dev = crtc->dev;
5983         struct drm_i915_private *dev_priv = dev->dev_private;
5984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5985         int pipe = intel_crtc->pipe;
5986         int ret;
5987
5988         drm_vblank_pre_modeset(dev, pipe);
5989
5990         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5991                                               x, y, old_fb);
5992         drm_vblank_post_modeset(dev, pipe);
5993
5994         if (ret)
5995                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5996         else
5997                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5998
5999         return ret;
6000 }
6001
6002 static bool intel_eld_uptodate(struct drm_connector *connector,
6003                                int reg_eldv, uint32_t bits_eldv,
6004                                int reg_elda, uint32_t bits_elda,
6005                                int reg_edid)
6006 {
6007         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6008         uint8_t *eld = connector->eld;
6009         uint32_t i;
6010
6011         i = I915_READ(reg_eldv);
6012         i &= bits_eldv;
6013
6014         if (!eld[0])
6015                 return !i;
6016
6017         if (!i)
6018                 return false;
6019
6020         i = I915_READ(reg_elda);
6021         i &= ~bits_elda;
6022         I915_WRITE(reg_elda, i);
6023
6024         for (i = 0; i < eld[2]; i++)
6025                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6026                         return false;
6027
6028         return true;
6029 }
6030
6031 static void g4x_write_eld(struct drm_connector *connector,
6032                           struct drm_crtc *crtc)
6033 {
6034         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6035         uint8_t *eld = connector->eld;
6036         uint32_t eldv;
6037         uint32_t len;
6038         uint32_t i;
6039
6040         i = I915_READ(G4X_AUD_VID_DID);
6041
6042         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6043                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6044         else
6045                 eldv = G4X_ELDV_DEVCTG;
6046
6047         if (intel_eld_uptodate(connector,
6048                                G4X_AUD_CNTL_ST, eldv,
6049                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6050                                G4X_HDMIW_HDMIEDID))
6051                 return;
6052
6053         i = I915_READ(G4X_AUD_CNTL_ST);
6054         i &= ~(eldv | G4X_ELD_ADDR);
6055         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6056         I915_WRITE(G4X_AUD_CNTL_ST, i);
6057
6058         if (!eld[0])
6059                 return;
6060
6061         len = min_t(uint8_t, eld[2], len);
6062         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6063         for (i = 0; i < len; i++)
6064                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6065
6066         i = I915_READ(G4X_AUD_CNTL_ST);
6067         i |= eldv;
6068         I915_WRITE(G4X_AUD_CNTL_ST, i);
6069 }
6070
6071 static void ironlake_write_eld(struct drm_connector *connector,
6072                                      struct drm_crtc *crtc)
6073 {
6074         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6075         uint8_t *eld = connector->eld;
6076         uint32_t eldv;
6077         uint32_t i;
6078         int len;
6079         int hdmiw_hdmiedid;
6080         int aud_cntl_st;
6081         int aud_cntrl_st2;
6082
6083         if (HAS_PCH_IBX(connector->dev)) {
6084                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6085                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6086                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6087         } else {
6088                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6089                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6090                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6091         }
6092
6093         i = to_intel_crtc(crtc)->pipe;
6094         hdmiw_hdmiedid += i * 0x100;
6095         aud_cntl_st += i * 0x100;
6096
6097         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6098
6099         i = I915_READ(aud_cntl_st);
6100         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6101         if (!i) {
6102                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6103                 /* operate blindly on all ports */
6104                 eldv = IBX_ELD_VALIDB;
6105                 eldv |= IBX_ELD_VALIDB << 4;
6106                 eldv |= IBX_ELD_VALIDB << 8;
6107         } else {
6108                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6109                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6110         }
6111
6112         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6113                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6114                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6115         }
6116
6117         if (intel_eld_uptodate(connector,
6118                                aud_cntrl_st2, eldv,
6119                                aud_cntl_st, IBX_ELD_ADDRESS,
6120                                hdmiw_hdmiedid))
6121                 return;
6122
6123         i = I915_READ(aud_cntrl_st2);
6124         i &= ~eldv;
6125         I915_WRITE(aud_cntrl_st2, i);
6126
6127         if (!eld[0])
6128                 return;
6129
6130         i = I915_READ(aud_cntl_st);
6131         i &= ~IBX_ELD_ADDRESS;
6132         I915_WRITE(aud_cntl_st, i);
6133
6134         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6135         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6136         for (i = 0; i < len; i++)
6137                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6138
6139         i = I915_READ(aud_cntrl_st2);
6140         i |= eldv;
6141         I915_WRITE(aud_cntrl_st2, i);
6142 }
6143
6144 void intel_write_eld(struct drm_encoder *encoder,
6145                      struct drm_display_mode *mode)
6146 {
6147         struct drm_crtc *crtc = encoder->crtc;
6148         struct drm_connector *connector;
6149         struct drm_device *dev = encoder->dev;
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151
6152         connector = drm_select_eld(encoder, mode);
6153         if (!connector)
6154                 return;
6155
6156         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6157                          connector->base.id,
6158                          drm_get_connector_name(connector),
6159                          connector->encoder->base.id,
6160                          drm_get_encoder_name(connector->encoder));
6161
6162         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6163
6164         if (dev_priv->display.write_eld)
6165                 dev_priv->display.write_eld(connector, crtc);
6166 }
6167
6168 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6169 void intel_crtc_load_lut(struct drm_crtc *crtc)
6170 {
6171         struct drm_device *dev = crtc->dev;
6172         struct drm_i915_private *dev_priv = dev->dev_private;
6173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6174         int palreg = PALETTE(intel_crtc->pipe);
6175         int i;
6176
6177         /* The clocks have to be on to load the palette. */
6178         if (!crtc->enabled)
6179                 return;
6180
6181         /* use legacy palette for Ironlake */
6182         if (HAS_PCH_SPLIT(dev))
6183                 palreg = LGC_PALETTE(intel_crtc->pipe);
6184
6185         for (i = 0; i < 256; i++) {
6186                 I915_WRITE(palreg + 4 * i,
6187                            (intel_crtc->lut_r[i] << 16) |
6188                            (intel_crtc->lut_g[i] << 8) |
6189                            intel_crtc->lut_b[i]);
6190         }
6191 }
6192
6193 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6194 {
6195         struct drm_device *dev = crtc->dev;
6196         struct drm_i915_private *dev_priv = dev->dev_private;
6197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198         bool visible = base != 0;
6199         u32 cntl;
6200
6201         if (intel_crtc->cursor_visible == visible)
6202                 return;
6203
6204         cntl = I915_READ(_CURACNTR);
6205         if (visible) {
6206                 /* On these chipsets we can only modify the base whilst
6207                  * the cursor is disabled.
6208                  */
6209                 I915_WRITE(_CURABASE, base);
6210
6211                 cntl &= ~(CURSOR_FORMAT_MASK);
6212                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6213                 cntl |= CURSOR_ENABLE |
6214                         CURSOR_GAMMA_ENABLE |
6215                         CURSOR_FORMAT_ARGB;
6216         } else
6217                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6218         I915_WRITE(_CURACNTR, cntl);
6219
6220         intel_crtc->cursor_visible = visible;
6221 }
6222
6223 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6224 {
6225         struct drm_device *dev = crtc->dev;
6226         struct drm_i915_private *dev_priv = dev->dev_private;
6227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6228         int pipe = intel_crtc->pipe;
6229         bool visible = base != 0;
6230
6231         if (intel_crtc->cursor_visible != visible) {
6232                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6233                 if (base) {
6234                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6235                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6236                         cntl |= pipe << 28; /* Connect to correct pipe */
6237                 } else {
6238                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6239                         cntl |= CURSOR_MODE_DISABLE;
6240                 }
6241                 I915_WRITE(CURCNTR(pipe), cntl);
6242
6243                 intel_crtc->cursor_visible = visible;
6244         }
6245         /* and commit changes on next vblank */
6246         I915_WRITE(CURBASE(pipe), base);
6247 }
6248
6249 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6250 {
6251         struct drm_device *dev = crtc->dev;
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254         int pipe = intel_crtc->pipe;
6255         bool visible = base != 0;
6256
6257         if (intel_crtc->cursor_visible != visible) {
6258                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6259                 if (base) {
6260                         cntl &= ~CURSOR_MODE;
6261                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6262                 } else {
6263                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6264                         cntl |= CURSOR_MODE_DISABLE;
6265                 }
6266                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6267
6268                 intel_crtc->cursor_visible = visible;
6269         }
6270         /* and commit changes on next vblank */
6271         I915_WRITE(CURBASE_IVB(pipe), base);
6272 }
6273
6274 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6275 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6276                                      bool on)
6277 {
6278         struct drm_device *dev = crtc->dev;
6279         struct drm_i915_private *dev_priv = dev->dev_private;
6280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281         int pipe = intel_crtc->pipe;
6282         int x = intel_crtc->cursor_x;
6283         int y = intel_crtc->cursor_y;
6284         u32 base, pos;
6285         bool visible;
6286
6287         pos = 0;
6288
6289         if (on && crtc->enabled && crtc->fb) {
6290                 base = intel_crtc->cursor_addr;
6291                 if (x > (int) crtc->fb->width)
6292                         base = 0;
6293
6294                 if (y > (int) crtc->fb->height)
6295                         base = 0;
6296         } else
6297                 base = 0;
6298
6299         if (x < 0) {
6300                 if (x + intel_crtc->cursor_width < 0)
6301                         base = 0;
6302
6303                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6304                 x = -x;
6305         }
6306         pos |= x << CURSOR_X_SHIFT;
6307
6308         if (y < 0) {
6309                 if (y + intel_crtc->cursor_height < 0)
6310                         base = 0;
6311
6312                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6313                 y = -y;
6314         }
6315         pos |= y << CURSOR_Y_SHIFT;
6316
6317         visible = base != 0;
6318         if (!visible && !intel_crtc->cursor_visible)
6319                 return;
6320
6321         if (IS_IVYBRIDGE(dev)) {
6322                 I915_WRITE(CURPOS_IVB(pipe), pos);
6323                 ivb_update_cursor(crtc, base);
6324         } else {
6325                 I915_WRITE(CURPOS(pipe), pos);
6326                 if (IS_845G(dev) || IS_I865G(dev))
6327                         i845_update_cursor(crtc, base);
6328                 else
6329                         i9xx_update_cursor(crtc, base);
6330         }
6331
6332         if (visible)
6333                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6334 }
6335
6336 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6337                                  struct drm_file *file,
6338                                  uint32_t handle,
6339                                  uint32_t width, uint32_t height)
6340 {
6341         struct drm_device *dev = crtc->dev;
6342         struct drm_i915_private *dev_priv = dev->dev_private;
6343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6344         struct drm_i915_gem_object *obj;
6345         uint32_t addr;
6346         int ret;
6347
6348         DRM_DEBUG_KMS("\n");
6349
6350         /* if we want to turn off the cursor ignore width and height */
6351         if (!handle) {
6352                 DRM_DEBUG_KMS("cursor off\n");
6353                 addr = 0;
6354                 obj = NULL;
6355                 mutex_lock(&dev->struct_mutex);
6356                 goto finish;
6357         }
6358
6359         /* Currently we only support 64x64 cursors */
6360         if (width != 64 || height != 64) {
6361                 DRM_ERROR("we currently only support 64x64 cursors\n");
6362                 return -EINVAL;
6363         }
6364
6365         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6366         if (&obj->base == NULL)
6367                 return -ENOENT;
6368
6369         if (obj->base.size < width * height * 4) {
6370                 DRM_ERROR("buffer is to small\n");
6371                 ret = -ENOMEM;
6372                 goto fail;
6373         }
6374
6375         /* we only need to pin inside GTT if cursor is non-phy */
6376         mutex_lock(&dev->struct_mutex);
6377         if (!dev_priv->info->cursor_needs_physical) {
6378                 if (obj->tiling_mode) {
6379                         DRM_ERROR("cursor cannot be tiled\n");
6380                         ret = -EINVAL;
6381                         goto fail_locked;
6382                 }
6383
6384                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6385                 if (ret) {
6386                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6387                         goto fail_locked;
6388                 }
6389
6390                 ret = i915_gem_object_put_fence(obj);
6391                 if (ret) {
6392                         DRM_ERROR("failed to release fence for cursor");
6393                         goto fail_unpin;
6394                 }
6395
6396                 addr = obj->gtt_offset;
6397         } else {
6398                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6399                 ret = i915_gem_attach_phys_object(dev, obj,
6400                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6401                                                   align);
6402                 if (ret) {
6403                         DRM_ERROR("failed to attach phys object\n");
6404                         goto fail_locked;
6405                 }
6406                 addr = obj->phys_obj->handle->busaddr;
6407         }
6408
6409         if (IS_GEN2(dev))
6410                 I915_WRITE(CURSIZE, (height << 12) | width);
6411
6412  finish:
6413         if (intel_crtc->cursor_bo) {
6414                 if (dev_priv->info->cursor_needs_physical) {
6415                         if (intel_crtc->cursor_bo != obj)
6416                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6417                 } else
6418                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6419                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6420         }
6421
6422         mutex_unlock(&dev->struct_mutex);
6423
6424         intel_crtc->cursor_addr = addr;
6425         intel_crtc->cursor_bo = obj;
6426         intel_crtc->cursor_width = width;
6427         intel_crtc->cursor_height = height;
6428
6429         intel_crtc_update_cursor(crtc, true);
6430
6431         return 0;
6432 fail_unpin:
6433         i915_gem_object_unpin(obj);
6434 fail_locked:
6435         mutex_unlock(&dev->struct_mutex);
6436 fail:
6437         drm_gem_object_unreference_unlocked(&obj->base);
6438         return ret;
6439 }
6440
6441 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6442 {
6443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6444
6445         intel_crtc->cursor_x = x;
6446         intel_crtc->cursor_y = y;
6447
6448         intel_crtc_update_cursor(crtc, true);
6449
6450         return 0;
6451 }
6452
6453 /** Sets the color ramps on behalf of RandR */
6454 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6455                                  u16 blue, int regno)
6456 {
6457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6458
6459         intel_crtc->lut_r[regno] = red >> 8;
6460         intel_crtc->lut_g[regno] = green >> 8;
6461         intel_crtc->lut_b[regno] = blue >> 8;
6462 }
6463
6464 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6465                              u16 *blue, int regno)
6466 {
6467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6468
6469         *red = intel_crtc->lut_r[regno] << 8;
6470         *green = intel_crtc->lut_g[regno] << 8;
6471         *blue = intel_crtc->lut_b[regno] << 8;
6472 }
6473
6474 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6475                                  u16 *blue, uint32_t start, uint32_t size)
6476 {
6477         int end = (start + size > 256) ? 256 : start + size, i;
6478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479
6480         for (i = start; i < end; i++) {
6481                 intel_crtc->lut_r[i] = red[i] >> 8;
6482                 intel_crtc->lut_g[i] = green[i] >> 8;
6483                 intel_crtc->lut_b[i] = blue[i] >> 8;
6484         }
6485
6486         intel_crtc_load_lut(crtc);
6487 }
6488
6489 /**
6490  * Get a pipe with a simple mode set on it for doing load-based monitor
6491  * detection.
6492  *
6493  * It will be up to the load-detect code to adjust the pipe as appropriate for
6494  * its requirements.  The pipe will be connected to no other encoders.
6495  *
6496  * Currently this code will only succeed if there is a pipe with no encoders
6497  * configured for it.  In the future, it could choose to temporarily disable
6498  * some outputs to free up a pipe for its use.
6499  *
6500  * \return crtc, or NULL if no pipes are available.
6501  */
6502
6503 /* VESA 640x480x72Hz mode to set on the pipe */
6504 static struct drm_display_mode load_detect_mode = {
6505         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6506                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6507 };
6508
6509 static struct drm_framebuffer *
6510 intel_framebuffer_create(struct drm_device *dev,
6511                          struct drm_mode_fb_cmd2 *mode_cmd,
6512                          struct drm_i915_gem_object *obj)
6513 {
6514         struct intel_framebuffer *intel_fb;
6515         int ret;
6516
6517         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6518         if (!intel_fb) {
6519                 drm_gem_object_unreference_unlocked(&obj->base);
6520                 return ERR_PTR(-ENOMEM);
6521         }
6522
6523         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6524         if (ret) {
6525                 drm_gem_object_unreference_unlocked(&obj->base);
6526                 kfree(intel_fb);
6527                 return ERR_PTR(ret);
6528         }
6529
6530         return &intel_fb->base;
6531 }
6532
6533 static u32
6534 intel_framebuffer_pitch_for_width(int width, int bpp)
6535 {
6536         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6537         return ALIGN(pitch, 64);
6538 }
6539
6540 static u32
6541 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6542 {
6543         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6544         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6545 }
6546
6547 static struct drm_framebuffer *
6548 intel_framebuffer_create_for_mode(struct drm_device *dev,
6549                                   struct drm_display_mode *mode,
6550                                   int depth, int bpp)
6551 {
6552         struct drm_i915_gem_object *obj;
6553         struct drm_mode_fb_cmd2 mode_cmd;
6554
6555         obj = i915_gem_alloc_object(dev,
6556                                     intel_framebuffer_size_for_mode(mode, bpp));
6557         if (obj == NULL)
6558                 return ERR_PTR(-ENOMEM);
6559
6560         mode_cmd.width = mode->hdisplay;
6561         mode_cmd.height = mode->vdisplay;
6562         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6563                                                                 bpp);
6564         mode_cmd.pixel_format = 0;
6565
6566         return intel_framebuffer_create(dev, &mode_cmd, obj);
6567 }
6568
6569 static struct drm_framebuffer *
6570 mode_fits_in_fbdev(struct drm_device *dev,
6571                    struct drm_display_mode *mode)
6572 {
6573         struct drm_i915_private *dev_priv = dev->dev_private;
6574         struct drm_i915_gem_object *obj;
6575         struct drm_framebuffer *fb;
6576
6577         if (dev_priv->fbdev == NULL)
6578                 return NULL;
6579
6580         obj = dev_priv->fbdev->ifb.obj;
6581         if (obj == NULL)
6582                 return NULL;
6583
6584         fb = &dev_priv->fbdev->ifb.base;
6585         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6586                                                                fb->bits_per_pixel))
6587                 return NULL;
6588
6589         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6590                 return NULL;
6591
6592         return fb;
6593 }
6594
6595 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6596                                 struct drm_connector *connector,
6597                                 struct drm_display_mode *mode,
6598                                 struct intel_load_detect_pipe *old)
6599 {
6600         struct intel_crtc *intel_crtc;
6601         struct drm_crtc *possible_crtc;
6602         struct drm_encoder *encoder = &intel_encoder->base;
6603         struct drm_crtc *crtc = NULL;
6604         struct drm_device *dev = encoder->dev;
6605         struct drm_framebuffer *old_fb;
6606         int i = -1;
6607
6608         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6609                       connector->base.id, drm_get_connector_name(connector),
6610                       encoder->base.id, drm_get_encoder_name(encoder));
6611
6612         /*
6613          * Algorithm gets a little messy:
6614          *
6615          *   - if the connector already has an assigned crtc, use it (but make
6616          *     sure it's on first)
6617          *
6618          *   - try to find the first unused crtc that can drive this connector,
6619          *     and use that if we find one
6620          */
6621
6622         /* See if we already have a CRTC for this connector */
6623         if (encoder->crtc) {
6624                 crtc = encoder->crtc;
6625
6626                 intel_crtc = to_intel_crtc(crtc);
6627                 old->dpms_mode = intel_crtc->dpms_mode;
6628                 old->load_detect_temp = false;
6629
6630                 /* Make sure the crtc and connector are running */
6631                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6632                         struct drm_encoder_helper_funcs *encoder_funcs;
6633                         struct drm_crtc_helper_funcs *crtc_funcs;
6634
6635                         crtc_funcs = crtc->helper_private;
6636                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6637
6638                         encoder_funcs = encoder->helper_private;
6639                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6640                 }
6641
6642                 return true;
6643         }
6644
6645         /* Find an unused one (if possible) */
6646         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6647                 i++;
6648                 if (!(encoder->possible_crtcs & (1 << i)))
6649                         continue;
6650                 if (!possible_crtc->enabled) {
6651                         crtc = possible_crtc;
6652                         break;
6653                 }
6654         }
6655
6656         /*
6657          * If we didn't find an unused CRTC, don't use any.
6658          */
6659         if (!crtc) {
6660                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6661                 return false;
6662         }
6663
6664         encoder->crtc = crtc;
6665         connector->encoder = encoder;
6666
6667         intel_crtc = to_intel_crtc(crtc);
6668         old->dpms_mode = intel_crtc->dpms_mode;
6669         old->load_detect_temp = true;
6670         old->release_fb = NULL;
6671
6672         if (!mode)
6673                 mode = &load_detect_mode;
6674
6675         old_fb = crtc->fb;
6676
6677         /* We need a framebuffer large enough to accommodate all accesses
6678          * that the plane may generate whilst we perform load detection.
6679          * We can not rely on the fbcon either being present (we get called
6680          * during its initialisation to detect all boot displays, or it may
6681          * not even exist) or that it is large enough to satisfy the
6682          * requested mode.
6683          */
6684         crtc->fb = mode_fits_in_fbdev(dev, mode);
6685         if (crtc->fb == NULL) {
6686                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6687                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6688                 old->release_fb = crtc->fb;
6689         } else
6690                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6691         if (IS_ERR(crtc->fb)) {
6692                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6693                 crtc->fb = old_fb;
6694                 return false;
6695         }
6696
6697         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6698                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6699                 if (old->release_fb)
6700                         old->release_fb->funcs->destroy(old->release_fb);
6701                 crtc->fb = old_fb;
6702                 return false;
6703         }
6704
6705         /* let the connector get through one full cycle before testing */
6706         intel_wait_for_vblank(dev, intel_crtc->pipe);
6707
6708         return true;
6709 }
6710
6711 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6712                                     struct drm_connector *connector,
6713                                     struct intel_load_detect_pipe *old)
6714 {
6715         struct drm_encoder *encoder = &intel_encoder->base;
6716         struct drm_device *dev = encoder->dev;
6717         struct drm_crtc *crtc = encoder->crtc;
6718         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6719         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6720
6721         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6722                       connector->base.id, drm_get_connector_name(connector),
6723                       encoder->base.id, drm_get_encoder_name(encoder));
6724
6725         if (old->load_detect_temp) {
6726                 connector->encoder = NULL;
6727                 drm_helper_disable_unused_functions(dev);
6728
6729                 if (old->release_fb)
6730                         old->release_fb->funcs->destroy(old->release_fb);
6731
6732                 return;
6733         }
6734
6735         /* Switch crtc and encoder back off if necessary */
6736         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6737                 encoder_funcs->dpms(encoder, old->dpms_mode);
6738                 crtc_funcs->dpms(crtc, old->dpms_mode);
6739         }
6740 }
6741
6742 /* Returns the clock of the currently programmed mode of the given pipe. */
6743 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6744 {
6745         struct drm_i915_private *dev_priv = dev->dev_private;
6746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6747         int pipe = intel_crtc->pipe;
6748         u32 dpll = I915_READ(DPLL(pipe));
6749         u32 fp;
6750         intel_clock_t clock;
6751
6752         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6753                 fp = I915_READ(FP0(pipe));
6754         else
6755                 fp = I915_READ(FP1(pipe));
6756
6757         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6758         if (IS_PINEVIEW(dev)) {
6759                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6760                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6761         } else {
6762                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6763                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6764         }
6765
6766         if (!IS_GEN2(dev)) {
6767                 if (IS_PINEVIEW(dev))
6768                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6769                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6770                 else
6771                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6772                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6773
6774                 switch (dpll & DPLL_MODE_MASK) {
6775                 case DPLLB_MODE_DAC_SERIAL:
6776                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6777                                 5 : 10;
6778                         break;
6779                 case DPLLB_MODE_LVDS:
6780                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6781                                 7 : 14;
6782                         break;
6783                 default:
6784                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6785                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6786                         return 0;
6787                 }
6788
6789                 /* XXX: Handle the 100Mhz refclk */
6790                 intel_clock(dev, 96000, &clock);
6791         } else {
6792                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6793
6794                 if (is_lvds) {
6795                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6796                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6797                         clock.p2 = 14;
6798
6799                         if ((dpll & PLL_REF_INPUT_MASK) ==
6800                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6801                                 /* XXX: might not be 66MHz */
6802                                 intel_clock(dev, 66000, &clock);
6803                         } else
6804                                 intel_clock(dev, 48000, &clock);
6805                 } else {
6806                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6807                                 clock.p1 = 2;
6808                         else {
6809                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6810                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6811                         }
6812                         if (dpll & PLL_P2_DIVIDE_BY_4)
6813                                 clock.p2 = 4;
6814                         else
6815                                 clock.p2 = 2;
6816
6817                         intel_clock(dev, 48000, &clock);
6818                 }
6819         }
6820
6821         /* XXX: It would be nice to validate the clocks, but we can't reuse
6822          * i830PllIsValid() because it relies on the xf86_config connector
6823          * configuration being accurate, which it isn't necessarily.
6824          */
6825
6826         return clock.dot;
6827 }
6828
6829 /** Returns the currently programmed mode of the given pipe. */
6830 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6831                                              struct drm_crtc *crtc)
6832 {
6833         struct drm_i915_private *dev_priv = dev->dev_private;
6834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6835         int pipe = intel_crtc->pipe;
6836         struct drm_display_mode *mode;
6837         int htot = I915_READ(HTOTAL(pipe));
6838         int hsync = I915_READ(HSYNC(pipe));
6839         int vtot = I915_READ(VTOTAL(pipe));
6840         int vsync = I915_READ(VSYNC(pipe));
6841
6842         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6843         if (!mode)
6844                 return NULL;
6845
6846         mode->clock = intel_crtc_clock_get(dev, crtc);
6847         mode->hdisplay = (htot & 0xffff) + 1;
6848         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6849         mode->hsync_start = (hsync & 0xffff) + 1;
6850         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6851         mode->vdisplay = (vtot & 0xffff) + 1;
6852         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6853         mode->vsync_start = (vsync & 0xffff) + 1;
6854         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6855
6856         drm_mode_set_name(mode);
6857         drm_mode_set_crtcinfo(mode, 0);
6858
6859         return mode;
6860 }
6861
6862 #define GPU_IDLE_TIMEOUT 500 /* ms */
6863
6864 /* When this timer fires, we've been idle for awhile */
6865 static void intel_gpu_idle_timer(unsigned long arg)
6866 {
6867         struct drm_device *dev = (struct drm_device *)arg;
6868         drm_i915_private_t *dev_priv = dev->dev_private;
6869
6870         if (!list_empty(&dev_priv->mm.active_list)) {
6871                 /* Still processing requests, so just re-arm the timer. */
6872                 mod_timer(&dev_priv->idle_timer, jiffies +
6873                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6874                 return;
6875         }
6876
6877         dev_priv->busy = false;
6878         queue_work(dev_priv->wq, &dev_priv->idle_work);
6879 }
6880
6881 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6882
6883 static void intel_crtc_idle_timer(unsigned long arg)
6884 {
6885         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6886         struct drm_crtc *crtc = &intel_crtc->base;
6887         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6888         struct intel_framebuffer *intel_fb;
6889
6890         intel_fb = to_intel_framebuffer(crtc->fb);
6891         if (intel_fb && intel_fb->obj->active) {
6892                 /* The framebuffer is still being accessed by the GPU. */
6893                 mod_timer(&intel_crtc->idle_timer, jiffies +
6894                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6895                 return;
6896         }
6897
6898         intel_crtc->busy = false;
6899         queue_work(dev_priv->wq, &dev_priv->idle_work);
6900 }
6901
6902 static void intel_increase_pllclock(struct drm_crtc *crtc)
6903 {
6904         struct drm_device *dev = crtc->dev;
6905         drm_i915_private_t *dev_priv = dev->dev_private;
6906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6907         int pipe = intel_crtc->pipe;
6908         int dpll_reg = DPLL(pipe);
6909         int dpll;
6910
6911         if (HAS_PCH_SPLIT(dev))
6912                 return;
6913
6914         if (!dev_priv->lvds_downclock_avail)
6915                 return;
6916
6917         dpll = I915_READ(dpll_reg);
6918         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6919                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6920
6921                 /* Unlock panel regs */
6922                 I915_WRITE(PP_CONTROL,
6923                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6924
6925                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6926                 I915_WRITE(dpll_reg, dpll);
6927                 intel_wait_for_vblank(dev, pipe);
6928
6929                 dpll = I915_READ(dpll_reg);
6930                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6931                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6932
6933                 /* ...and lock them again */
6934                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6935         }
6936
6937         /* Schedule downclock */
6938         mod_timer(&intel_crtc->idle_timer, jiffies +
6939                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6940 }
6941
6942 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6943 {
6944         struct drm_device *dev = crtc->dev;
6945         drm_i915_private_t *dev_priv = dev->dev_private;
6946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6947         int pipe = intel_crtc->pipe;
6948         int dpll_reg = DPLL(pipe);
6949         int dpll = I915_READ(dpll_reg);
6950
6951         if (HAS_PCH_SPLIT(dev))
6952                 return;
6953
6954         if (!dev_priv->lvds_downclock_avail)
6955                 return;
6956
6957         /*
6958          * Since this is called by a timer, we should never get here in
6959          * the manual case.
6960          */
6961         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6962                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6963
6964                 /* Unlock panel regs */
6965                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6966                            PANEL_UNLOCK_REGS);
6967
6968                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6969                 I915_WRITE(dpll_reg, dpll);
6970                 intel_wait_for_vblank(dev, pipe);
6971                 dpll = I915_READ(dpll_reg);
6972                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6973                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6974
6975                 /* ...and lock them again */
6976                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6977         }
6978
6979 }
6980
6981 /**
6982  * intel_idle_update - adjust clocks for idleness
6983  * @work: work struct
6984  *
6985  * Either the GPU or display (or both) went idle.  Check the busy status
6986  * here and adjust the CRTC and GPU clocks as necessary.
6987  */
6988 static void intel_idle_update(struct work_struct *work)
6989 {
6990         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6991                                                     idle_work);
6992         struct drm_device *dev = dev_priv->dev;
6993         struct drm_crtc *crtc;
6994         struct intel_crtc *intel_crtc;
6995
6996         if (!i915_powersave)
6997                 return;
6998
6999         mutex_lock(&dev->struct_mutex);
7000
7001         i915_update_gfx_val(dev_priv);
7002
7003         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7004                 /* Skip inactive CRTCs */
7005                 if (!crtc->fb)
7006                         continue;
7007
7008                 intel_crtc = to_intel_crtc(crtc);
7009                 if (!intel_crtc->busy)
7010                         intel_decrease_pllclock(crtc);
7011         }
7012
7013
7014         mutex_unlock(&dev->struct_mutex);
7015 }
7016
7017 /**
7018  * intel_mark_busy - mark the GPU and possibly the display busy
7019  * @dev: drm device
7020  * @obj: object we're operating on
7021  *
7022  * Callers can use this function to indicate that the GPU is busy processing
7023  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7024  * buffer), we'll also mark the display as busy, so we know to increase its
7025  * clock frequency.
7026  */
7027 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7028 {
7029         drm_i915_private_t *dev_priv = dev->dev_private;
7030         struct drm_crtc *crtc = NULL;
7031         struct intel_framebuffer *intel_fb;
7032         struct intel_crtc *intel_crtc;
7033
7034         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7035                 return;
7036
7037         if (!dev_priv->busy)
7038                 dev_priv->busy = true;
7039         else
7040                 mod_timer(&dev_priv->idle_timer, jiffies +
7041                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7042
7043         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7044                 if (!crtc->fb)
7045                         continue;
7046
7047                 intel_crtc = to_intel_crtc(crtc);
7048                 intel_fb = to_intel_framebuffer(crtc->fb);
7049                 if (intel_fb->obj == obj) {
7050                         if (!intel_crtc->busy) {
7051                                 /* Non-busy -> busy, upclock */
7052                                 intel_increase_pllclock(crtc);
7053                                 intel_crtc->busy = true;
7054                         } else {
7055                                 /* Busy -> busy, put off timer */
7056                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7057                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7058                         }
7059                 }
7060         }
7061 }
7062
7063 static void intel_crtc_destroy(struct drm_crtc *crtc)
7064 {
7065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7066         struct drm_device *dev = crtc->dev;
7067         struct intel_unpin_work *work;
7068         unsigned long flags;
7069
7070         spin_lock_irqsave(&dev->event_lock, flags);
7071         work = intel_crtc->unpin_work;
7072         intel_crtc->unpin_work = NULL;
7073         spin_unlock_irqrestore(&dev->event_lock, flags);
7074
7075         if (work) {
7076                 cancel_work_sync(&work->work);
7077                 kfree(work);
7078         }
7079
7080         drm_crtc_cleanup(crtc);
7081
7082         kfree(intel_crtc);
7083 }
7084
7085 static void intel_unpin_work_fn(struct work_struct *__work)
7086 {
7087         struct intel_unpin_work *work =
7088                 container_of(__work, struct intel_unpin_work, work);
7089
7090         mutex_lock(&work->dev->struct_mutex);
7091         i915_gem_object_unpin(work->old_fb_obj);
7092         drm_gem_object_unreference(&work->pending_flip_obj->base);
7093         drm_gem_object_unreference(&work->old_fb_obj->base);
7094
7095         intel_update_fbc(work->dev);
7096         mutex_unlock(&work->dev->struct_mutex);
7097         kfree(work);
7098 }
7099
7100 static void do_intel_finish_page_flip(struct drm_device *dev,
7101                                       struct drm_crtc *crtc)
7102 {
7103         drm_i915_private_t *dev_priv = dev->dev_private;
7104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7105         struct intel_unpin_work *work;
7106         struct drm_i915_gem_object *obj;
7107         struct drm_pending_vblank_event *e;
7108         struct timeval tnow, tvbl;
7109         unsigned long flags;
7110
7111         /* Ignore early vblank irqs */
7112         if (intel_crtc == NULL)
7113                 return;
7114
7115         do_gettimeofday(&tnow);
7116
7117         spin_lock_irqsave(&dev->event_lock, flags);
7118         work = intel_crtc->unpin_work;
7119         if (work == NULL || !work->pending) {
7120                 spin_unlock_irqrestore(&dev->event_lock, flags);
7121                 return;
7122         }
7123
7124         intel_crtc->unpin_work = NULL;
7125
7126         if (work->event) {
7127                 e = work->event;
7128                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7129
7130                 /* Called before vblank count and timestamps have
7131                  * been updated for the vblank interval of flip
7132                  * completion? Need to increment vblank count and
7133                  * add one videorefresh duration to returned timestamp
7134                  * to account for this. We assume this happened if we
7135                  * get called over 0.9 frame durations after the last
7136                  * timestamped vblank.
7137                  *
7138                  * This calculation can not be used with vrefresh rates
7139                  * below 5Hz (10Hz to be on the safe side) without
7140                  * promoting to 64 integers.
7141                  */
7142                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7143                     9 * crtc->framedur_ns) {
7144                         e->event.sequence++;
7145                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7146                                              crtc->framedur_ns);
7147                 }
7148
7149                 e->event.tv_sec = tvbl.tv_sec;
7150                 e->event.tv_usec = tvbl.tv_usec;
7151
7152                 list_add_tail(&e->base.link,
7153                               &e->base.file_priv->event_list);
7154                 wake_up_interruptible(&e->base.file_priv->event_wait);
7155         }
7156
7157         drm_vblank_put(dev, intel_crtc->pipe);
7158
7159         spin_unlock_irqrestore(&dev->event_lock, flags);
7160
7161         obj = work->old_fb_obj;
7162
7163         atomic_clear_mask(1 << intel_crtc->plane,
7164                           &obj->pending_flip.counter);
7165         if (atomic_read(&obj->pending_flip) == 0)
7166                 wake_up(&dev_priv->pending_flip_queue);
7167
7168         schedule_work(&work->work);
7169
7170         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7171 }
7172
7173 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7174 {
7175         drm_i915_private_t *dev_priv = dev->dev_private;
7176         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7177
7178         do_intel_finish_page_flip(dev, crtc);
7179 }
7180
7181 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7182 {
7183         drm_i915_private_t *dev_priv = dev->dev_private;
7184         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7185
7186         do_intel_finish_page_flip(dev, crtc);
7187 }
7188
7189 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7190 {
7191         drm_i915_private_t *dev_priv = dev->dev_private;
7192         struct intel_crtc *intel_crtc =
7193                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7194         unsigned long flags;
7195
7196         spin_lock_irqsave(&dev->event_lock, flags);
7197         if (intel_crtc->unpin_work) {
7198                 if ((++intel_crtc->unpin_work->pending) > 1)
7199                         DRM_ERROR("Prepared flip multiple times\n");
7200         } else {
7201                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7202         }
7203         spin_unlock_irqrestore(&dev->event_lock, flags);
7204 }
7205
7206 static int intel_gen2_queue_flip(struct drm_device *dev,
7207                                  struct drm_crtc *crtc,
7208                                  struct drm_framebuffer *fb,
7209                                  struct drm_i915_gem_object *obj)
7210 {
7211         struct drm_i915_private *dev_priv = dev->dev_private;
7212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7213         unsigned long offset;
7214         u32 flip_mask;
7215         int ret;
7216
7217         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7218         if (ret)
7219                 goto out;
7220
7221         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7222         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7223
7224         ret = BEGIN_LP_RING(6);
7225         if (ret)
7226                 goto out;
7227
7228         /* Can't queue multiple flips, so wait for the previous
7229          * one to finish before executing the next.
7230          */
7231         if (intel_crtc->plane)
7232                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7233         else
7234                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7235         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7236         OUT_RING(MI_NOOP);
7237         OUT_RING(MI_DISPLAY_FLIP |
7238                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7239         OUT_RING(fb->pitches[0]);
7240         OUT_RING(obj->gtt_offset + offset);
7241         OUT_RING(MI_NOOP);
7242         ADVANCE_LP_RING();
7243 out:
7244         return ret;
7245 }
7246
7247 static int intel_gen3_queue_flip(struct drm_device *dev,
7248                                  struct drm_crtc *crtc,
7249                                  struct drm_framebuffer *fb,
7250                                  struct drm_i915_gem_object *obj)
7251 {
7252         struct drm_i915_private *dev_priv = dev->dev_private;
7253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7254         unsigned long offset;
7255         u32 flip_mask;
7256         int ret;
7257
7258         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7259         if (ret)
7260                 goto out;
7261
7262         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7263         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7264
7265         ret = BEGIN_LP_RING(6);
7266         if (ret)
7267                 goto out;
7268
7269         if (intel_crtc->plane)
7270                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7271         else
7272                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7273         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7274         OUT_RING(MI_NOOP);
7275         OUT_RING(MI_DISPLAY_FLIP_I915 |
7276                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7277         OUT_RING(fb->pitches[0]);
7278         OUT_RING(obj->gtt_offset + offset);
7279         OUT_RING(MI_NOOP);
7280
7281         ADVANCE_LP_RING();
7282 out:
7283         return ret;
7284 }
7285
7286 static int intel_gen4_queue_flip(struct drm_device *dev,
7287                                  struct drm_crtc *crtc,
7288                                  struct drm_framebuffer *fb,
7289                                  struct drm_i915_gem_object *obj)
7290 {
7291         struct drm_i915_private *dev_priv = dev->dev_private;
7292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7293         uint32_t pf, pipesrc;
7294         int ret;
7295
7296         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7297         if (ret)
7298                 goto out;
7299
7300         ret = BEGIN_LP_RING(4);
7301         if (ret)
7302                 goto out;
7303
7304         /* i965+ uses the linear or tiled offsets from the
7305          * Display Registers (which do not change across a page-flip)
7306          * so we need only reprogram the base address.
7307          */
7308         OUT_RING(MI_DISPLAY_FLIP |
7309                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7310         OUT_RING(fb->pitches[0]);
7311         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7312
7313         /* XXX Enabling the panel-fitter across page-flip is so far
7314          * untested on non-native modes, so ignore it for now.
7315          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7316          */
7317         pf = 0;
7318         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7319         OUT_RING(pf | pipesrc);
7320         ADVANCE_LP_RING();
7321 out:
7322         return ret;
7323 }
7324
7325 static int intel_gen6_queue_flip(struct drm_device *dev,
7326                                  struct drm_crtc *crtc,
7327                                  struct drm_framebuffer *fb,
7328                                  struct drm_i915_gem_object *obj)
7329 {
7330         struct drm_i915_private *dev_priv = dev->dev_private;
7331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7332         uint32_t pf, pipesrc;
7333         int ret;
7334
7335         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7336         if (ret)
7337                 goto out;
7338
7339         ret = BEGIN_LP_RING(4);
7340         if (ret)
7341                 goto out;
7342
7343         OUT_RING(MI_DISPLAY_FLIP |
7344                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7345         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7346         OUT_RING(obj->gtt_offset);
7347
7348         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7349         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7350         OUT_RING(pf | pipesrc);
7351         ADVANCE_LP_RING();
7352 out:
7353         return ret;
7354 }
7355
7356 /*
7357  * On gen7 we currently use the blit ring because (in early silicon at least)
7358  * the render ring doesn't give us interrpts for page flip completion, which
7359  * means clients will hang after the first flip is queued.  Fortunately the
7360  * blit ring generates interrupts properly, so use it instead.
7361  */
7362 static int intel_gen7_queue_flip(struct drm_device *dev,
7363                                  struct drm_crtc *crtc,
7364                                  struct drm_framebuffer *fb,
7365                                  struct drm_i915_gem_object *obj)
7366 {
7367         struct drm_i915_private *dev_priv = dev->dev_private;
7368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7369         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7370         int ret;
7371
7372         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7373         if (ret)
7374                 goto out;
7375
7376         ret = intel_ring_begin(ring, 4);
7377         if (ret)
7378                 goto out;
7379
7380         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7381         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7382         intel_ring_emit(ring, (obj->gtt_offset));
7383         intel_ring_emit(ring, (MI_NOOP));
7384         intel_ring_advance(ring);
7385 out:
7386         return ret;
7387 }
7388
7389 static int intel_default_queue_flip(struct drm_device *dev,
7390                                     struct drm_crtc *crtc,
7391                                     struct drm_framebuffer *fb,
7392                                     struct drm_i915_gem_object *obj)
7393 {
7394         return -ENODEV;
7395 }
7396
7397 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7398                                 struct drm_framebuffer *fb,
7399                                 struct drm_pending_vblank_event *event)
7400 {
7401         struct drm_device *dev = crtc->dev;
7402         struct drm_i915_private *dev_priv = dev->dev_private;
7403         struct intel_framebuffer *intel_fb;
7404         struct drm_i915_gem_object *obj;
7405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7406         struct intel_unpin_work *work;
7407         unsigned long flags;
7408         int ret;
7409
7410         work = kzalloc(sizeof *work, GFP_KERNEL);
7411         if (work == NULL)
7412                 return -ENOMEM;
7413
7414         work->event = event;
7415         work->dev = crtc->dev;
7416         intel_fb = to_intel_framebuffer(crtc->fb);
7417         work->old_fb_obj = intel_fb->obj;
7418         INIT_WORK(&work->work, intel_unpin_work_fn);
7419
7420         ret = drm_vblank_get(dev, intel_crtc->pipe);
7421         if (ret)
7422                 goto free_work;
7423
7424         /* We borrow the event spin lock for protecting unpin_work */
7425         spin_lock_irqsave(&dev->event_lock, flags);
7426         if (intel_crtc->unpin_work) {
7427                 spin_unlock_irqrestore(&dev->event_lock, flags);
7428                 kfree(work);
7429                 drm_vblank_put(dev, intel_crtc->pipe);
7430
7431                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7432                 return -EBUSY;
7433         }
7434         intel_crtc->unpin_work = work;
7435         spin_unlock_irqrestore(&dev->event_lock, flags);
7436
7437         intel_fb = to_intel_framebuffer(fb);
7438         obj = intel_fb->obj;
7439
7440         mutex_lock(&dev->struct_mutex);
7441
7442         /* Reference the objects for the scheduled work. */
7443         drm_gem_object_reference(&work->old_fb_obj->base);
7444         drm_gem_object_reference(&obj->base);
7445
7446         crtc->fb = fb;
7447
7448         work->pending_flip_obj = obj;
7449
7450         work->enable_stall_check = true;
7451
7452         /* Block clients from rendering to the new back buffer until
7453          * the flip occurs and the object is no longer visible.
7454          */
7455         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7456
7457         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7458         if (ret)
7459                 goto cleanup_pending;
7460
7461         intel_disable_fbc(dev);
7462         mutex_unlock(&dev->struct_mutex);
7463
7464         trace_i915_flip_request(intel_crtc->plane, obj);
7465
7466         return 0;
7467
7468 cleanup_pending:
7469         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7470         drm_gem_object_unreference(&work->old_fb_obj->base);
7471         drm_gem_object_unreference(&obj->base);
7472         mutex_unlock(&dev->struct_mutex);
7473
7474         spin_lock_irqsave(&dev->event_lock, flags);
7475         intel_crtc->unpin_work = NULL;
7476         spin_unlock_irqrestore(&dev->event_lock, flags);
7477
7478         drm_vblank_put(dev, intel_crtc->pipe);
7479 free_work:
7480         kfree(work);
7481
7482         return ret;
7483 }
7484
7485 static void intel_sanitize_modesetting(struct drm_device *dev,
7486                                        int pipe, int plane)
7487 {
7488         struct drm_i915_private *dev_priv = dev->dev_private;
7489         u32 reg, val;
7490
7491         if (HAS_PCH_SPLIT(dev))
7492                 return;
7493
7494         /* Who knows what state these registers were left in by the BIOS or
7495          * grub?
7496          *
7497          * If we leave the registers in a conflicting state (e.g. with the
7498          * display plane reading from the other pipe than the one we intend
7499          * to use) then when we attempt to teardown the active mode, we will
7500          * not disable the pipes and planes in the correct order -- leaving
7501          * a plane reading from a disabled pipe and possibly leading to
7502          * undefined behaviour.
7503          */
7504
7505         reg = DSPCNTR(plane);
7506         val = I915_READ(reg);
7507
7508         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7509                 return;
7510         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7511                 return;
7512
7513         /* This display plane is active and attached to the other CPU pipe. */
7514         pipe = !pipe;
7515
7516         /* Disable the plane and wait for it to stop reading from the pipe. */
7517         intel_disable_plane(dev_priv, plane, pipe);
7518         intel_disable_pipe(dev_priv, pipe);
7519 }
7520
7521 static void intel_crtc_reset(struct drm_crtc *crtc)
7522 {
7523         struct drm_device *dev = crtc->dev;
7524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7525
7526         /* Reset flags back to the 'unknown' status so that they
7527          * will be correctly set on the initial modeset.
7528          */
7529         intel_crtc->dpms_mode = -1;
7530
7531         /* We need to fix up any BIOS configuration that conflicts with
7532          * our expectations.
7533          */
7534         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7535 }
7536
7537 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7538         .dpms = intel_crtc_dpms,
7539         .mode_fixup = intel_crtc_mode_fixup,
7540         .mode_set = intel_crtc_mode_set,
7541         .mode_set_base = intel_pipe_set_base,
7542         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7543         .load_lut = intel_crtc_load_lut,
7544         .disable = intel_crtc_disable,
7545 };
7546
7547 static const struct drm_crtc_funcs intel_crtc_funcs = {
7548         .reset = intel_crtc_reset,
7549         .cursor_set = intel_crtc_cursor_set,
7550         .cursor_move = intel_crtc_cursor_move,
7551         .gamma_set = intel_crtc_gamma_set,
7552         .set_config = drm_crtc_helper_set_config,
7553         .destroy = intel_crtc_destroy,
7554         .page_flip = intel_crtc_page_flip,
7555 };
7556
7557 static void intel_crtc_init(struct drm_device *dev, int pipe)
7558 {
7559         drm_i915_private_t *dev_priv = dev->dev_private;
7560         struct intel_crtc *intel_crtc;
7561         int i;
7562
7563         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7564         if (intel_crtc == NULL)
7565                 return;
7566
7567         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7568
7569         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7570         for (i = 0; i < 256; i++) {
7571                 intel_crtc->lut_r[i] = i;
7572                 intel_crtc->lut_g[i] = i;
7573                 intel_crtc->lut_b[i] = i;
7574         }
7575
7576         /* Swap pipes & planes for FBC on pre-965 */
7577         intel_crtc->pipe = pipe;
7578         intel_crtc->plane = pipe;
7579         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7580                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7581                 intel_crtc->plane = !pipe;
7582         }
7583
7584         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7585                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7586         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7587         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7588
7589         intel_crtc_reset(&intel_crtc->base);
7590         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7591         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7592
7593         if (HAS_PCH_SPLIT(dev)) {
7594                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7595                         intel_crtc->no_pll = true;
7596                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7597                 intel_helper_funcs.commit = ironlake_crtc_commit;
7598         } else {
7599                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7600                 intel_helper_funcs.commit = i9xx_crtc_commit;
7601         }
7602
7603         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7604
7605         intel_crtc->busy = false;
7606
7607         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7608                     (unsigned long)intel_crtc);
7609 }
7610
7611 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7612                                 struct drm_file *file)
7613 {
7614         drm_i915_private_t *dev_priv = dev->dev_private;
7615         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7616         struct drm_mode_object *drmmode_obj;
7617         struct intel_crtc *crtc;
7618
7619         if (!dev_priv) {
7620                 DRM_ERROR("called with no initialization\n");
7621                 return -EINVAL;
7622         }
7623
7624         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7625                         DRM_MODE_OBJECT_CRTC);
7626
7627         if (!drmmode_obj) {
7628                 DRM_ERROR("no such CRTC id\n");
7629                 return -EINVAL;
7630         }
7631
7632         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7633         pipe_from_crtc_id->pipe = crtc->pipe;
7634
7635         return 0;
7636 }
7637
7638 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7639 {
7640         struct intel_encoder *encoder;
7641         int index_mask = 0;
7642         int entry = 0;
7643
7644         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7645                 if (type_mask & encoder->clone_mask)
7646                         index_mask |= (1 << entry);
7647                 entry++;
7648         }
7649
7650         return index_mask;
7651 }
7652
7653 static bool has_edp_a(struct drm_device *dev)
7654 {
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656
7657         if (!IS_MOBILE(dev))
7658                 return false;
7659
7660         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7661                 return false;
7662
7663         if (IS_GEN5(dev) &&
7664             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7665                 return false;
7666
7667         return true;
7668 }
7669
7670 static void intel_setup_outputs(struct drm_device *dev)
7671 {
7672         struct drm_i915_private *dev_priv = dev->dev_private;
7673         struct intel_encoder *encoder;
7674         bool dpd_is_edp = false;
7675         bool has_lvds = false;
7676
7677         if (IS_MOBILE(dev) && !IS_I830(dev))
7678                 has_lvds = intel_lvds_init(dev);
7679         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7680                 /* disable the panel fitter on everything but LVDS */
7681                 I915_WRITE(PFIT_CONTROL, 0);
7682         }
7683
7684         if (HAS_PCH_SPLIT(dev)) {
7685                 dpd_is_edp = intel_dpd_is_edp(dev);
7686
7687                 if (has_edp_a(dev))
7688                         intel_dp_init(dev, DP_A);
7689
7690                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7691                         intel_dp_init(dev, PCH_DP_D);
7692         }
7693
7694         intel_crt_init(dev);
7695
7696         if (HAS_PCH_SPLIT(dev)) {
7697                 int found;
7698
7699                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7700                         /* PCH SDVOB multiplex with HDMIB */
7701                         found = intel_sdvo_init(dev, PCH_SDVOB);
7702                         if (!found)
7703                                 intel_hdmi_init(dev, HDMIB);
7704                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7705                                 intel_dp_init(dev, PCH_DP_B);
7706                 }
7707
7708                 if (I915_READ(HDMIC) & PORT_DETECTED)
7709                         intel_hdmi_init(dev, HDMIC);
7710
7711                 if (I915_READ(HDMID) & PORT_DETECTED)
7712                         intel_hdmi_init(dev, HDMID);
7713
7714                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7715                         intel_dp_init(dev, PCH_DP_C);
7716
7717                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7718                         intel_dp_init(dev, PCH_DP_D);
7719
7720         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7721                 bool found = false;
7722
7723                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7724                         DRM_DEBUG_KMS("probing SDVOB\n");
7725                         found = intel_sdvo_init(dev, SDVOB);
7726                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7727                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7728                                 intel_hdmi_init(dev, SDVOB);
7729                         }
7730
7731                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7732                                 DRM_DEBUG_KMS("probing DP_B\n");
7733                                 intel_dp_init(dev, DP_B);
7734                         }
7735                 }
7736
7737                 /* Before G4X SDVOC doesn't have its own detect register */
7738
7739                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7740                         DRM_DEBUG_KMS("probing SDVOC\n");
7741                         found = intel_sdvo_init(dev, SDVOC);
7742                 }
7743
7744                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7745
7746                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7747                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7748                                 intel_hdmi_init(dev, SDVOC);
7749                         }
7750                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7751                                 DRM_DEBUG_KMS("probing DP_C\n");
7752                                 intel_dp_init(dev, DP_C);
7753                         }
7754                 }
7755
7756                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7757                     (I915_READ(DP_D) & DP_DETECTED)) {
7758                         DRM_DEBUG_KMS("probing DP_D\n");
7759                         intel_dp_init(dev, DP_D);
7760                 }
7761         } else if (IS_GEN2(dev))
7762                 intel_dvo_init(dev);
7763
7764         if (SUPPORTS_TV(dev))
7765                 intel_tv_init(dev);
7766
7767         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7768                 encoder->base.possible_crtcs = encoder->crtc_mask;
7769                 encoder->base.possible_clones =
7770                         intel_encoder_clones(dev, encoder->clone_mask);
7771         }
7772
7773         /* disable all the possible outputs/crtcs before entering KMS mode */
7774         drm_helper_disable_unused_functions(dev);
7775
7776         if (HAS_PCH_SPLIT(dev))
7777                 ironlake_init_pch_refclk(dev);
7778 }
7779
7780 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7781 {
7782         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7783
7784         drm_framebuffer_cleanup(fb);
7785         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7786
7787         kfree(intel_fb);
7788 }
7789
7790 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7791                                                 struct drm_file *file,
7792                                                 unsigned int *handle)
7793 {
7794         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7795         struct drm_i915_gem_object *obj = intel_fb->obj;
7796
7797         return drm_gem_handle_create(file, &obj->base, handle);
7798 }
7799
7800 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7801         .destroy = intel_user_framebuffer_destroy,
7802         .create_handle = intel_user_framebuffer_create_handle,
7803 };
7804
7805 int intel_framebuffer_init(struct drm_device *dev,
7806                            struct intel_framebuffer *intel_fb,
7807                            struct drm_mode_fb_cmd2 *mode_cmd,
7808                            struct drm_i915_gem_object *obj)
7809 {
7810         int ret;
7811
7812         if (obj->tiling_mode == I915_TILING_Y)
7813                 return -EINVAL;
7814
7815         if (mode_cmd->pitches[0] & 63)
7816                 return -EINVAL;
7817
7818         switch (mode_cmd->pixel_format) {
7819         case DRM_FORMAT_RGB332:
7820         case DRM_FORMAT_RGB565:
7821         case DRM_FORMAT_XRGB8888:
7822         case DRM_FORMAT_ARGB8888:
7823         case DRM_FORMAT_XRGB2101010:
7824         case DRM_FORMAT_ARGB2101010:
7825                 /* RGB formats are common across chipsets */
7826                 break;
7827         case DRM_FORMAT_YUYV:
7828         case DRM_FORMAT_UYVY:
7829         case DRM_FORMAT_YVYU:
7830         case DRM_FORMAT_VYUY:
7831                 break;
7832         default:
7833                 DRM_ERROR("unsupported pixel format\n");
7834                 return -EINVAL;
7835         }
7836
7837         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7838         if (ret) {
7839                 DRM_ERROR("framebuffer init failed %d\n", ret);
7840                 return ret;
7841         }
7842
7843         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7844         intel_fb->obj = obj;
7845         return 0;
7846 }
7847
7848 static struct drm_framebuffer *
7849 intel_user_framebuffer_create(struct drm_device *dev,
7850                               struct drm_file *filp,
7851                               struct drm_mode_fb_cmd2 *mode_cmd)
7852 {
7853         struct drm_i915_gem_object *obj;
7854
7855         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7856                                                 mode_cmd->handles[0]));
7857         if (&obj->base == NULL)
7858                 return ERR_PTR(-ENOENT);
7859
7860         return intel_framebuffer_create(dev, mode_cmd, obj);
7861 }
7862
7863 static const struct drm_mode_config_funcs intel_mode_funcs = {
7864         .fb_create = intel_user_framebuffer_create,
7865         .output_poll_changed = intel_fb_output_poll_changed,
7866 };
7867
7868 static struct drm_i915_gem_object *
7869 intel_alloc_context_page(struct drm_device *dev)
7870 {
7871         struct drm_i915_gem_object *ctx;
7872         int ret;
7873
7874         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7875
7876         ctx = i915_gem_alloc_object(dev, 4096);
7877         if (!ctx) {
7878                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7879                 return NULL;
7880         }
7881
7882         ret = i915_gem_object_pin(ctx, 4096, true);
7883         if (ret) {
7884                 DRM_ERROR("failed to pin power context: %d\n", ret);
7885                 goto err_unref;
7886         }
7887
7888         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7889         if (ret) {
7890                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7891                 goto err_unpin;
7892         }
7893
7894         return ctx;
7895
7896 err_unpin:
7897         i915_gem_object_unpin(ctx);
7898 err_unref:
7899         drm_gem_object_unreference(&ctx->base);
7900         mutex_unlock(&dev->struct_mutex);
7901         return NULL;
7902 }
7903
7904 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7905 {
7906         struct drm_i915_private *dev_priv = dev->dev_private;
7907         u16 rgvswctl;
7908
7909         rgvswctl = I915_READ16(MEMSWCTL);
7910         if (rgvswctl & MEMCTL_CMD_STS) {
7911                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7912                 return false; /* still busy with another command */
7913         }
7914
7915         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7916                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7917         I915_WRITE16(MEMSWCTL, rgvswctl);
7918         POSTING_READ16(MEMSWCTL);
7919
7920         rgvswctl |= MEMCTL_CMD_STS;
7921         I915_WRITE16(MEMSWCTL, rgvswctl);
7922
7923         return true;
7924 }
7925
7926 void ironlake_enable_drps(struct drm_device *dev)
7927 {
7928         struct drm_i915_private *dev_priv = dev->dev_private;
7929         u32 rgvmodectl = I915_READ(MEMMODECTL);
7930         u8 fmax, fmin, fstart, vstart;
7931
7932         /* Enable temp reporting */
7933         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7934         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7935
7936         /* 100ms RC evaluation intervals */
7937         I915_WRITE(RCUPEI, 100000);
7938         I915_WRITE(RCDNEI, 100000);
7939
7940         /* Set max/min thresholds to 90ms and 80ms respectively */
7941         I915_WRITE(RCBMAXAVG, 90000);
7942         I915_WRITE(RCBMINAVG, 80000);
7943
7944         I915_WRITE(MEMIHYST, 1);
7945
7946         /* Set up min, max, and cur for interrupt handling */
7947         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7948         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7949         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7950                 MEMMODE_FSTART_SHIFT;
7951
7952         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7953                 PXVFREQ_PX_SHIFT;
7954
7955         dev_priv->fmax = fmax; /* IPS callback will increase this */
7956         dev_priv->fstart = fstart;
7957
7958         dev_priv->max_delay = fstart;
7959         dev_priv->min_delay = fmin;
7960         dev_priv->cur_delay = fstart;
7961
7962         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7963                          fmax, fmin, fstart);
7964
7965         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7966
7967         /*
7968          * Interrupts will be enabled in ironlake_irq_postinstall
7969          */
7970
7971         I915_WRITE(VIDSTART, vstart);
7972         POSTING_READ(VIDSTART);
7973
7974         rgvmodectl |= MEMMODE_SWMODE_EN;
7975         I915_WRITE(MEMMODECTL, rgvmodectl);
7976
7977         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7978                 DRM_ERROR("stuck trying to change perf mode\n");
7979         msleep(1);
7980
7981         ironlake_set_drps(dev, fstart);
7982
7983         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7984                 I915_READ(0x112e0);
7985         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7986         dev_priv->last_count2 = I915_READ(0x112f4);
7987         getrawmonotonic(&dev_priv->last_time2);
7988 }
7989
7990 void ironlake_disable_drps(struct drm_device *dev)
7991 {
7992         struct drm_i915_private *dev_priv = dev->dev_private;
7993         u16 rgvswctl = I915_READ16(MEMSWCTL);
7994
7995         /* Ack interrupts, disable EFC interrupt */
7996         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7997         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7998         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7999         I915_WRITE(DEIIR, DE_PCU_EVENT);
8000         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8001
8002         /* Go back to the starting frequency */
8003         ironlake_set_drps(dev, dev_priv->fstart);
8004         msleep(1);
8005         rgvswctl |= MEMCTL_CMD_STS;
8006         I915_WRITE(MEMSWCTL, rgvswctl);
8007         msleep(1);
8008
8009 }
8010
8011 void gen6_set_rps(struct drm_device *dev, u8 val)
8012 {
8013         struct drm_i915_private *dev_priv = dev->dev_private;
8014         u32 swreq;
8015
8016         swreq = (val & 0x3ff) << 25;
8017         I915_WRITE(GEN6_RPNSWREQ, swreq);
8018 }
8019
8020 void gen6_disable_rps(struct drm_device *dev)
8021 {
8022         struct drm_i915_private *dev_priv = dev->dev_private;
8023
8024         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8025         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8026         I915_WRITE(GEN6_PMIER, 0);
8027         /* Complete PM interrupt masking here doesn't race with the rps work
8028          * item again unmasking PM interrupts because that is using a different
8029          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8030          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8031
8032         spin_lock_irq(&dev_priv->rps_lock);
8033         dev_priv->pm_iir = 0;
8034         spin_unlock_irq(&dev_priv->rps_lock);
8035
8036         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8037 }
8038
8039 static unsigned long intel_pxfreq(u32 vidfreq)
8040 {
8041         unsigned long freq;
8042         int div = (vidfreq & 0x3f0000) >> 16;
8043         int post = (vidfreq & 0x3000) >> 12;
8044         int pre = (vidfreq & 0x7);
8045
8046         if (!pre)
8047                 return 0;
8048
8049         freq = ((div * 133333) / ((1<<post) * pre));
8050
8051         return freq;
8052 }
8053
8054 void intel_init_emon(struct drm_device *dev)
8055 {
8056         struct drm_i915_private *dev_priv = dev->dev_private;
8057         u32 lcfuse;
8058         u8 pxw[16];
8059         int i;
8060
8061         /* Disable to program */
8062         I915_WRITE(ECR, 0);
8063         POSTING_READ(ECR);
8064
8065         /* Program energy weights for various events */
8066         I915_WRITE(SDEW, 0x15040d00);
8067         I915_WRITE(CSIEW0, 0x007f0000);
8068         I915_WRITE(CSIEW1, 0x1e220004);
8069         I915_WRITE(CSIEW2, 0x04000004);
8070
8071         for (i = 0; i < 5; i++)
8072                 I915_WRITE(PEW + (i * 4), 0);
8073         for (i = 0; i < 3; i++)
8074                 I915_WRITE(DEW + (i * 4), 0);
8075
8076         /* Program P-state weights to account for frequency power adjustment */
8077         for (i = 0; i < 16; i++) {
8078                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8079                 unsigned long freq = intel_pxfreq(pxvidfreq);
8080                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8081                         PXVFREQ_PX_SHIFT;
8082                 unsigned long val;
8083
8084                 val = vid * vid;
8085                 val *= (freq / 1000);
8086                 val *= 255;
8087                 val /= (127*127*900);
8088                 if (val > 0xff)
8089                         DRM_ERROR("bad pxval: %ld\n", val);
8090                 pxw[i] = val;
8091         }
8092         /* Render standby states get 0 weight */
8093         pxw[14] = 0;
8094         pxw[15] = 0;
8095
8096         for (i = 0; i < 4; i++) {
8097                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8098                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8099                 I915_WRITE(PXW + (i * 4), val);
8100         }
8101
8102         /* Adjust magic regs to magic values (more experimental results) */
8103         I915_WRITE(OGW0, 0);
8104         I915_WRITE(OGW1, 0);
8105         I915_WRITE(EG0, 0x00007f00);
8106         I915_WRITE(EG1, 0x0000000e);
8107         I915_WRITE(EG2, 0x000e0000);
8108         I915_WRITE(EG3, 0x68000300);
8109         I915_WRITE(EG4, 0x42000000);
8110         I915_WRITE(EG5, 0x00140031);
8111         I915_WRITE(EG6, 0);
8112         I915_WRITE(EG7, 0);
8113
8114         for (i = 0; i < 8; i++)
8115                 I915_WRITE(PXWL + (i * 4), 0);
8116
8117         /* Enable PMON + select events */
8118         I915_WRITE(ECR, 0x80000019);
8119
8120         lcfuse = I915_READ(LCFUSE02);
8121
8122         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8123 }
8124
8125 static bool intel_enable_rc6(struct drm_device *dev)
8126 {
8127         /*
8128          * Respect the kernel parameter if it is set
8129          */
8130         if (i915_enable_rc6 >= 0)
8131                 return i915_enable_rc6;
8132
8133         /*
8134          * Disable RC6 on Ironlake
8135          */
8136         if (INTEL_INFO(dev)->gen == 5)
8137                 return 0;
8138
8139         /*
8140          * Disable rc6 on Sandybridge
8141          */
8142         if (INTEL_INFO(dev)->gen == 6) {
8143                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8144                 return 0;
8145         }
8146         DRM_DEBUG_DRIVER("RC6 enabled\n");
8147         return 1;
8148 }
8149
8150 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8151 {
8152         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8153         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8154         u32 pcu_mbox, rc6_mask = 0;
8155         int cur_freq, min_freq, max_freq;
8156         int i;
8157
8158         /* Here begins a magic sequence of register writes to enable
8159          * auto-downclocking.
8160          *
8161          * Perhaps there might be some value in exposing these to
8162          * userspace...
8163          */
8164         I915_WRITE(GEN6_RC_STATE, 0);
8165         mutex_lock(&dev_priv->dev->struct_mutex);
8166         gen6_gt_force_wake_get(dev_priv);
8167
8168         /* disable the counters and set deterministic thresholds */
8169         I915_WRITE(GEN6_RC_CONTROL, 0);
8170
8171         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8172         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8173         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8174         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8175         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8176
8177         for (i = 0; i < I915_NUM_RINGS; i++)
8178                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8179
8180         I915_WRITE(GEN6_RC_SLEEP, 0);
8181         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8182         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8183         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8184         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8185
8186         if (intel_enable_rc6(dev_priv->dev))
8187                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8188                         (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
8189
8190         I915_WRITE(GEN6_RC_CONTROL,
8191                    rc6_mask |
8192                    GEN6_RC_CTL_EI_MODE(1) |
8193                    GEN6_RC_CTL_HW_ENABLE);
8194
8195         I915_WRITE(GEN6_RPNSWREQ,
8196                    GEN6_FREQUENCY(10) |
8197                    GEN6_OFFSET(0) |
8198                    GEN6_AGGRESSIVE_TURBO);
8199         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8200                    GEN6_FREQUENCY(12));
8201
8202         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8203         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8204                    18 << 24 |
8205                    6 << 16);
8206         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8207         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8208         I915_WRITE(GEN6_RP_UP_EI, 100000);
8209         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8210         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8211         I915_WRITE(GEN6_RP_CONTROL,
8212                    GEN6_RP_MEDIA_TURBO |
8213                    GEN6_RP_MEDIA_HW_MODE |
8214                    GEN6_RP_MEDIA_IS_GFX |
8215                    GEN6_RP_ENABLE |
8216                    GEN6_RP_UP_BUSY_AVG |
8217                    GEN6_RP_DOWN_IDLE_CONT);
8218
8219         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8220                      500))
8221                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8222
8223         I915_WRITE(GEN6_PCODE_DATA, 0);
8224         I915_WRITE(GEN6_PCODE_MAILBOX,
8225                    GEN6_PCODE_READY |
8226                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8227         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8228                      500))
8229                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8230
8231         min_freq = (rp_state_cap & 0xff0000) >> 16;
8232         max_freq = rp_state_cap & 0xff;
8233         cur_freq = (gt_perf_status & 0xff00) >> 8;
8234
8235         /* Check for overclock support */
8236         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8237                      500))
8238                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8239         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8240         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8241         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8242                      500))
8243                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8244         if (pcu_mbox & (1<<31)) { /* OC supported */
8245                 max_freq = pcu_mbox & 0xff;
8246                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8247         }
8248
8249         /* In units of 100MHz */
8250         dev_priv->max_delay = max_freq;
8251         dev_priv->min_delay = min_freq;
8252         dev_priv->cur_delay = cur_freq;
8253
8254         /* requires MSI enabled */
8255         I915_WRITE(GEN6_PMIER,
8256                    GEN6_PM_MBOX_EVENT |
8257                    GEN6_PM_THERMAL_EVENT |
8258                    GEN6_PM_RP_DOWN_TIMEOUT |
8259                    GEN6_PM_RP_UP_THRESHOLD |
8260                    GEN6_PM_RP_DOWN_THRESHOLD |
8261                    GEN6_PM_RP_UP_EI_EXPIRED |
8262                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8263         spin_lock_irq(&dev_priv->rps_lock);
8264         WARN_ON(dev_priv->pm_iir != 0);
8265         I915_WRITE(GEN6_PMIMR, 0);
8266         spin_unlock_irq(&dev_priv->rps_lock);
8267         /* enable all PM interrupts */
8268         I915_WRITE(GEN6_PMINTRMSK, 0);
8269
8270         gen6_gt_force_wake_put(dev_priv);
8271         mutex_unlock(&dev_priv->dev->struct_mutex);
8272 }
8273
8274 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8275 {
8276         int min_freq = 15;
8277         int gpu_freq, ia_freq, max_ia_freq;
8278         int scaling_factor = 180;
8279
8280         max_ia_freq = cpufreq_quick_get_max(0);
8281         /*
8282          * Default to measured freq if none found, PCU will ensure we don't go
8283          * over
8284          */
8285         if (!max_ia_freq)
8286 #ifndef CONFIG_XEN
8287                 max_ia_freq = tsc_khz;
8288 #else
8289                 max_ia_freq = cpu_khz;
8290 #endif
8291
8292         /* Convert from kHz to MHz */
8293         max_ia_freq /= 1000;
8294
8295         mutex_lock(&dev_priv->dev->struct_mutex);
8296
8297         /*
8298          * For each potential GPU frequency, load a ring frequency we'd like
8299          * to use for memory access.  We do this by specifying the IA frequency
8300          * the PCU should use as a reference to determine the ring frequency.
8301          */
8302         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8303              gpu_freq--) {
8304                 int diff = dev_priv->max_delay - gpu_freq;
8305
8306                 /*
8307                  * For GPU frequencies less than 750MHz, just use the lowest
8308                  * ring freq.
8309                  */
8310                 if (gpu_freq < min_freq)
8311                         ia_freq = 800;
8312                 else
8313                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8314                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8315
8316                 I915_WRITE(GEN6_PCODE_DATA,
8317                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8318                            gpu_freq);
8319                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8320                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8321                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8322                               GEN6_PCODE_READY) == 0, 10)) {
8323                         DRM_ERROR("pcode write of freq table timed out\n");
8324                         continue;
8325                 }
8326         }
8327
8328         mutex_unlock(&dev_priv->dev->struct_mutex);
8329 }
8330
8331 static void ironlake_init_clock_gating(struct drm_device *dev)
8332 {
8333         struct drm_i915_private *dev_priv = dev->dev_private;
8334         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8335
8336         /* Required for FBC */
8337         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8338                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8339                 DPFDUNIT_CLOCK_GATE_DISABLE;
8340         /* Required for CxSR */
8341         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8342
8343         I915_WRITE(PCH_3DCGDIS0,
8344                    MARIUNIT_CLOCK_GATE_DISABLE |
8345                    SVSMUNIT_CLOCK_GATE_DISABLE);
8346         I915_WRITE(PCH_3DCGDIS1,
8347                    VFMUNIT_CLOCK_GATE_DISABLE);
8348
8349         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8350
8351         /*
8352          * According to the spec the following bits should be set in
8353          * order to enable memory self-refresh
8354          * The bit 22/21 of 0x42004
8355          * The bit 5 of 0x42020
8356          * The bit 15 of 0x45000
8357          */
8358         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8359                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8360                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8361         I915_WRITE(ILK_DSPCLK_GATE,
8362                    (I915_READ(ILK_DSPCLK_GATE) |
8363                     ILK_DPARB_CLK_GATE));
8364         I915_WRITE(DISP_ARB_CTL,
8365                    (I915_READ(DISP_ARB_CTL) |
8366                     DISP_FBC_WM_DIS));
8367         I915_WRITE(WM3_LP_ILK, 0);
8368         I915_WRITE(WM2_LP_ILK, 0);
8369         I915_WRITE(WM1_LP_ILK, 0);
8370
8371         /*
8372          * Based on the document from hardware guys the following bits
8373          * should be set unconditionally in order to enable FBC.
8374          * The bit 22 of 0x42000
8375          * The bit 22 of 0x42004
8376          * The bit 7,8,9 of 0x42020.
8377          */
8378         if (IS_IRONLAKE_M(dev)) {
8379                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8380                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8381                            ILK_FBCQ_DIS);
8382                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8383                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8384                            ILK_DPARB_GATE);
8385                 I915_WRITE(ILK_DSPCLK_GATE,
8386                            I915_READ(ILK_DSPCLK_GATE) |
8387                            ILK_DPFC_DIS1 |
8388                            ILK_DPFC_DIS2 |
8389                            ILK_CLK_FBC);
8390         }
8391
8392         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8393                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8394                    ILK_ELPIN_409_SELECT);
8395         I915_WRITE(_3D_CHICKEN2,
8396                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8397                    _3D_CHICKEN2_WM_READ_PIPELINED);
8398 }
8399
8400 static void gen6_init_clock_gating(struct drm_device *dev)
8401 {
8402         struct drm_i915_private *dev_priv = dev->dev_private;
8403         int pipe;
8404         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8405
8406         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8407
8408         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8409                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8410                    ILK_ELPIN_409_SELECT);
8411
8412         I915_WRITE(WM3_LP_ILK, 0);
8413         I915_WRITE(WM2_LP_ILK, 0);
8414         I915_WRITE(WM1_LP_ILK, 0);
8415
8416         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8417          * gating disable must be set.  Failure to set it results in
8418          * flickering pixels due to Z write ordering failures after
8419          * some amount of runtime in the Mesa "fire" demo, and Unigine
8420          * Sanctuary and Tropics, and apparently anything else with
8421          * alpha test or pixel discard.
8422          *
8423          * According to the spec, bit 11 (RCCUNIT) must also be set,
8424          * but we didn't debug actual testcases to find it out.
8425          */
8426         I915_WRITE(GEN6_UCGCTL2,
8427                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8428                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8429
8430         /*
8431          * According to the spec the following bits should be
8432          * set in order to enable memory self-refresh and fbc:
8433          * The bit21 and bit22 of 0x42000
8434          * The bit21 and bit22 of 0x42004
8435          * The bit5 and bit7 of 0x42020
8436          * The bit14 of 0x70180
8437          * The bit14 of 0x71180
8438          */
8439         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8440                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8441                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8442         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8443                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8444                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8445         I915_WRITE(ILK_DSPCLK_GATE,
8446                    I915_READ(ILK_DSPCLK_GATE) |
8447                    ILK_DPARB_CLK_GATE  |
8448                    ILK_DPFD_CLK_GATE);
8449
8450         for_each_pipe(pipe) {
8451                 I915_WRITE(DSPCNTR(pipe),
8452                            I915_READ(DSPCNTR(pipe)) |
8453                            DISPPLANE_TRICKLE_FEED_DISABLE);
8454                 intel_flush_display_plane(dev_priv, pipe);
8455         }
8456 }
8457
8458 static void ivybridge_init_clock_gating(struct drm_device *dev)
8459 {
8460         struct drm_i915_private *dev_priv = dev->dev_private;
8461         int pipe;
8462         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8463
8464         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8465
8466         I915_WRITE(WM3_LP_ILK, 0);
8467         I915_WRITE(WM2_LP_ILK, 0);
8468         I915_WRITE(WM1_LP_ILK, 0);
8469
8470         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8471          * This implements the WaDisableRCZUnitClockGating workaround.
8472          */
8473         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8474
8475         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8476
8477         I915_WRITE(IVB_CHICKEN3,
8478                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8479                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8480
8481         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8482         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8483                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8484
8485         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8486         I915_WRITE(GEN7_L3CNTLREG1,
8487                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8488         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8489                         GEN7_WA_L3_CHICKEN_MODE);
8490
8491         /* This is required by WaCatErrorRejectionIssue */
8492         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8493                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8494                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8495
8496         for_each_pipe(pipe) {
8497                 I915_WRITE(DSPCNTR(pipe),
8498                            I915_READ(DSPCNTR(pipe)) |
8499                            DISPPLANE_TRICKLE_FEED_DISABLE);
8500                 intel_flush_display_plane(dev_priv, pipe);
8501         }
8502 }
8503
8504 static void g4x_init_clock_gating(struct drm_device *dev)
8505 {
8506         struct drm_i915_private *dev_priv = dev->dev_private;
8507         uint32_t dspclk_gate;
8508
8509         I915_WRITE(RENCLK_GATE_D1, 0);
8510         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8511                    GS_UNIT_CLOCK_GATE_DISABLE |
8512                    CL_UNIT_CLOCK_GATE_DISABLE);
8513         I915_WRITE(RAMCLK_GATE_D, 0);
8514         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8515                 OVRUNIT_CLOCK_GATE_DISABLE |
8516                 OVCUNIT_CLOCK_GATE_DISABLE;
8517         if (IS_GM45(dev))
8518                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8519         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8520 }
8521
8522 static void crestline_init_clock_gating(struct drm_device *dev)
8523 {
8524         struct drm_i915_private *dev_priv = dev->dev_private;
8525
8526         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8527         I915_WRITE(RENCLK_GATE_D2, 0);
8528         I915_WRITE(DSPCLK_GATE_D, 0);
8529         I915_WRITE(RAMCLK_GATE_D, 0);
8530         I915_WRITE16(DEUC, 0);
8531 }
8532
8533 static void broadwater_init_clock_gating(struct drm_device *dev)
8534 {
8535         struct drm_i915_private *dev_priv = dev->dev_private;
8536
8537         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8538                    I965_RCC_CLOCK_GATE_DISABLE |
8539                    I965_RCPB_CLOCK_GATE_DISABLE |
8540                    I965_ISC_CLOCK_GATE_DISABLE |
8541                    I965_FBC_CLOCK_GATE_DISABLE);
8542         I915_WRITE(RENCLK_GATE_D2, 0);
8543 }
8544
8545 static void gen3_init_clock_gating(struct drm_device *dev)
8546 {
8547         struct drm_i915_private *dev_priv = dev->dev_private;
8548         u32 dstate = I915_READ(D_STATE);
8549
8550         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8551                 DSTATE_DOT_CLOCK_GATING;
8552         I915_WRITE(D_STATE, dstate);
8553 }
8554
8555 static void i85x_init_clock_gating(struct drm_device *dev)
8556 {
8557         struct drm_i915_private *dev_priv = dev->dev_private;
8558
8559         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8560 }
8561
8562 static void i830_init_clock_gating(struct drm_device *dev)
8563 {
8564         struct drm_i915_private *dev_priv = dev->dev_private;
8565
8566         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8567 }
8568
8569 static void ibx_init_clock_gating(struct drm_device *dev)
8570 {
8571         struct drm_i915_private *dev_priv = dev->dev_private;
8572
8573         /*
8574          * On Ibex Peak and Cougar Point, we need to disable clock
8575          * gating for the panel power sequencer or it will fail to
8576          * start up when no ports are active.
8577          */
8578         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8579 }
8580
8581 static void cpt_init_clock_gating(struct drm_device *dev)
8582 {
8583         struct drm_i915_private *dev_priv = dev->dev_private;
8584         int pipe;
8585
8586         /*
8587          * On Ibex Peak and Cougar Point, we need to disable clock
8588          * gating for the panel power sequencer or it will fail to
8589          * start up when no ports are active.
8590          */
8591         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8592         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8593                    DPLS_EDP_PPS_FIX_DIS);
8594         /* Without this, mode sets may fail silently on FDI */
8595         for_each_pipe(pipe)
8596                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8597 }
8598
8599 static void ironlake_teardown_rc6(struct drm_device *dev)
8600 {
8601         struct drm_i915_private *dev_priv = dev->dev_private;
8602
8603         if (dev_priv->renderctx) {
8604                 i915_gem_object_unpin(dev_priv->renderctx);
8605                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8606                 dev_priv->renderctx = NULL;
8607         }
8608
8609         if (dev_priv->pwrctx) {
8610                 i915_gem_object_unpin(dev_priv->pwrctx);
8611                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8612                 dev_priv->pwrctx = NULL;
8613         }
8614 }
8615
8616 static void ironlake_disable_rc6(struct drm_device *dev)
8617 {
8618         struct drm_i915_private *dev_priv = dev->dev_private;
8619
8620         if (I915_READ(PWRCTXA)) {
8621                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8622                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8623                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8624                          50);
8625
8626                 I915_WRITE(PWRCTXA, 0);
8627                 POSTING_READ(PWRCTXA);
8628
8629                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8630                 POSTING_READ(RSTDBYCTL);
8631         }
8632
8633         ironlake_teardown_rc6(dev);
8634 }
8635
8636 static int ironlake_setup_rc6(struct drm_device *dev)
8637 {
8638         struct drm_i915_private *dev_priv = dev->dev_private;
8639
8640         if (dev_priv->renderctx == NULL)
8641                 dev_priv->renderctx = intel_alloc_context_page(dev);
8642         if (!dev_priv->renderctx)
8643                 return -ENOMEM;
8644
8645         if (dev_priv->pwrctx == NULL)
8646                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8647         if (!dev_priv->pwrctx) {
8648                 ironlake_teardown_rc6(dev);
8649                 return -ENOMEM;
8650         }
8651
8652         return 0;
8653 }
8654
8655 void ironlake_enable_rc6(struct drm_device *dev)
8656 {
8657         struct drm_i915_private *dev_priv = dev->dev_private;
8658         int ret;
8659
8660         /* rc6 disabled by default due to repeated reports of hanging during
8661          * boot and resume.
8662          */
8663         if (!intel_enable_rc6(dev))
8664                 return;
8665
8666         mutex_lock(&dev->struct_mutex);
8667         ret = ironlake_setup_rc6(dev);
8668         if (ret) {
8669                 mutex_unlock(&dev->struct_mutex);
8670                 return;
8671         }
8672
8673         /*
8674          * GPU can automatically power down the render unit if given a page
8675          * to save state.
8676          */
8677         ret = BEGIN_LP_RING(6);
8678         if (ret) {
8679                 ironlake_teardown_rc6(dev);
8680                 mutex_unlock(&dev->struct_mutex);
8681                 return;
8682         }
8683
8684         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8685         OUT_RING(MI_SET_CONTEXT);
8686         OUT_RING(dev_priv->renderctx->gtt_offset |
8687                  MI_MM_SPACE_GTT |
8688                  MI_SAVE_EXT_STATE_EN |
8689                  MI_RESTORE_EXT_STATE_EN |
8690                  MI_RESTORE_INHIBIT);
8691         OUT_RING(MI_SUSPEND_FLUSH);
8692         OUT_RING(MI_NOOP);
8693         OUT_RING(MI_FLUSH);
8694         ADVANCE_LP_RING();
8695
8696         /*
8697          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8698          * does an implicit flush, combined with MI_FLUSH above, it should be
8699          * safe to assume that renderctx is valid
8700          */
8701         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8702         if (ret) {
8703                 DRM_ERROR("failed to enable ironlake power power savings\n");
8704                 ironlake_teardown_rc6(dev);
8705                 mutex_unlock(&dev->struct_mutex);
8706                 return;
8707         }
8708
8709         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8710         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8711         mutex_unlock(&dev->struct_mutex);
8712 }
8713
8714 void intel_init_clock_gating(struct drm_device *dev)
8715 {
8716         struct drm_i915_private *dev_priv = dev->dev_private;
8717
8718         dev_priv->display.init_clock_gating(dev);
8719
8720         if (dev_priv->display.init_pch_clock_gating)
8721                 dev_priv->display.init_pch_clock_gating(dev);
8722 }
8723
8724 /* Set up chip specific display functions */
8725 static void intel_init_display(struct drm_device *dev)
8726 {
8727         struct drm_i915_private *dev_priv = dev->dev_private;
8728
8729         /* We always want a DPMS function */
8730         if (HAS_PCH_SPLIT(dev)) {
8731                 dev_priv->display.dpms = ironlake_crtc_dpms;
8732                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8733                 dev_priv->display.update_plane = ironlake_update_plane;
8734         } else {
8735                 dev_priv->display.dpms = i9xx_crtc_dpms;
8736                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8737                 dev_priv->display.update_plane = i9xx_update_plane;
8738         }
8739
8740         if (I915_HAS_FBC(dev)) {
8741                 if (HAS_PCH_SPLIT(dev)) {
8742                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8743                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8744                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8745                 } else if (IS_GM45(dev)) {
8746                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8747                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8748                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8749                 } else if (IS_CRESTLINE(dev)) {
8750                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8751                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8752                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8753                 }
8754                 /* 855GM needs testing */
8755         }
8756
8757         /* Returns the core display clock speed */
8758         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8759                 dev_priv->display.get_display_clock_speed =
8760                         i945_get_display_clock_speed;
8761         else if (IS_I915G(dev))
8762                 dev_priv->display.get_display_clock_speed =
8763                         i915_get_display_clock_speed;
8764         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8765                 dev_priv->display.get_display_clock_speed =
8766                         i9xx_misc_get_display_clock_speed;
8767         else if (IS_I915GM(dev))
8768                 dev_priv->display.get_display_clock_speed =
8769                         i915gm_get_display_clock_speed;
8770         else if (IS_I865G(dev))
8771                 dev_priv->display.get_display_clock_speed =
8772                         i865_get_display_clock_speed;
8773         else if (IS_I85X(dev))
8774                 dev_priv->display.get_display_clock_speed =
8775                         i855_get_display_clock_speed;
8776         else /* 852, 830 */
8777                 dev_priv->display.get_display_clock_speed =
8778                         i830_get_display_clock_speed;
8779
8780         /* For FIFO watermark updates */
8781         if (HAS_PCH_SPLIT(dev)) {
8782                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8783                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8784
8785                 /* IVB configs may use multi-threaded forcewake */
8786                 if (IS_IVYBRIDGE(dev)) {
8787                         u32     ecobus;
8788
8789                         /* A small trick here - if the bios hasn't configured MT forcewake,
8790                          * and if the device is in RC6, then force_wake_mt_get will not wake
8791                          * the device and the ECOBUS read will return zero. Which will be
8792                          * (correctly) interpreted by the test below as MT forcewake being
8793                          * disabled.
8794                          */
8795                         mutex_lock(&dev->struct_mutex);
8796                         __gen6_gt_force_wake_mt_get(dev_priv);
8797                         ecobus = I915_READ_NOTRACE(ECOBUS);
8798                         __gen6_gt_force_wake_mt_put(dev_priv);
8799                         mutex_unlock(&dev->struct_mutex);
8800
8801                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8802                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8803                                 dev_priv->display.force_wake_get =
8804                                         __gen6_gt_force_wake_mt_get;
8805                                 dev_priv->display.force_wake_put =
8806                                         __gen6_gt_force_wake_mt_put;
8807                         }
8808                 }
8809
8810                 if (HAS_PCH_IBX(dev))
8811                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8812                 else if (HAS_PCH_CPT(dev))
8813                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8814
8815                 if (IS_GEN5(dev)) {
8816                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8817                                 dev_priv->display.update_wm = ironlake_update_wm;
8818                         else {
8819                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8820                                               "Disable CxSR\n");
8821                                 dev_priv->display.update_wm = NULL;
8822                         }
8823                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8824                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8825                         dev_priv->display.write_eld = ironlake_write_eld;
8826                 } else if (IS_GEN6(dev)) {
8827                         if (SNB_READ_WM0_LATENCY()) {
8828                                 dev_priv->display.update_wm = sandybridge_update_wm;
8829                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8830                         } else {
8831                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8832                                               "Disable CxSR\n");
8833                                 dev_priv->display.update_wm = NULL;
8834                         }
8835                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8836                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8837                         dev_priv->display.write_eld = ironlake_write_eld;
8838                 } else if (IS_IVYBRIDGE(dev)) {
8839                         /* FIXME: detect B0+ stepping and use auto training */
8840                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8841                         if (SNB_READ_WM0_LATENCY()) {
8842                                 dev_priv->display.update_wm = sandybridge_update_wm;
8843                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8844                         } else {
8845                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8846                                               "Disable CxSR\n");
8847                                 dev_priv->display.update_wm = NULL;
8848                         }
8849                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8850                         dev_priv->display.write_eld = ironlake_write_eld;
8851                 } else
8852                         dev_priv->display.update_wm = NULL;
8853         } else if (IS_PINEVIEW(dev)) {
8854                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8855                                             dev_priv->is_ddr3,
8856                                             dev_priv->fsb_freq,
8857                                             dev_priv->mem_freq)) {
8858                         DRM_INFO("failed to find known CxSR latency "
8859                                  "(found ddr%s fsb freq %d, mem freq %d), "
8860                                  "disabling CxSR\n",
8861                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8862                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8863                         /* Disable CxSR and never update its watermark again */
8864                         pineview_disable_cxsr(dev);
8865                         dev_priv->display.update_wm = NULL;
8866                 } else
8867                         dev_priv->display.update_wm = pineview_update_wm;
8868                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8869         } else if (IS_G4X(dev)) {
8870                 dev_priv->display.write_eld = g4x_write_eld;
8871                 dev_priv->display.update_wm = g4x_update_wm;
8872                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8873         } else if (IS_GEN4(dev)) {
8874                 dev_priv->display.update_wm = i965_update_wm;
8875                 if (IS_CRESTLINE(dev))
8876                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8877                 else if (IS_BROADWATER(dev))
8878                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8879         } else if (IS_GEN3(dev)) {
8880                 dev_priv->display.update_wm = i9xx_update_wm;
8881                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8882                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8883         } else if (IS_I865G(dev)) {
8884                 dev_priv->display.update_wm = i830_update_wm;
8885                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8886                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8887         } else if (IS_I85X(dev)) {
8888                 dev_priv->display.update_wm = i9xx_update_wm;
8889                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8890                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8891         } else {
8892                 dev_priv->display.update_wm = i830_update_wm;
8893                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8894                 if (IS_845G(dev))
8895                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8896                 else
8897                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8898         }
8899
8900         /* Default just returns -ENODEV to indicate unsupported */
8901         dev_priv->display.queue_flip = intel_default_queue_flip;
8902
8903         switch (INTEL_INFO(dev)->gen) {
8904         case 2:
8905                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8906                 break;
8907
8908         case 3:
8909                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8910                 break;
8911
8912         case 4:
8913         case 5:
8914                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8915                 break;
8916
8917         case 6:
8918                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8919                 break;
8920         case 7:
8921                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8922                 break;
8923         }
8924 }
8925
8926 /*
8927  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8928  * resume, or other times.  This quirk makes sure that's the case for
8929  * affected systems.
8930  */
8931 static void quirk_pipea_force(struct drm_device *dev)
8932 {
8933         struct drm_i915_private *dev_priv = dev->dev_private;
8934
8935         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8936         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8937 }
8938
8939 /*
8940  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8941  */
8942 static void quirk_ssc_force_disable(struct drm_device *dev)
8943 {
8944         struct drm_i915_private *dev_priv = dev->dev_private;
8945         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8946 }
8947
8948 struct intel_quirk {
8949         int device;
8950         int subsystem_vendor;
8951         int subsystem_device;
8952         void (*hook)(struct drm_device *dev);
8953 };
8954
8955 struct intel_quirk intel_quirks[] = {
8956         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8957         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8958         /* HP Mini needs pipe A force quirk (LP: #322104) */
8959         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8960
8961         /* Thinkpad R31 needs pipe A force quirk */
8962         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8963         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8964         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8965
8966         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8967         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8968         /* ThinkPad X40 needs pipe A force quirk */
8969
8970         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8971         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8972
8973         /* 855 & before need to leave pipe A & dpll A up */
8974         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8975         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8976
8977         /* Lenovo U160 cannot use SSC on LVDS */
8978         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8979
8980         /* Sony Vaio Y cannot use SSC on LVDS */
8981         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8982 };
8983
8984 static void intel_init_quirks(struct drm_device *dev)
8985 {
8986         struct pci_dev *d = dev->pdev;
8987         int i;
8988
8989         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8990                 struct intel_quirk *q = &intel_quirks[i];
8991
8992                 if (d->device == q->device &&
8993                     (d->subsystem_vendor == q->subsystem_vendor ||
8994                      q->subsystem_vendor == PCI_ANY_ID) &&
8995                     (d->subsystem_device == q->subsystem_device ||
8996                      q->subsystem_device == PCI_ANY_ID))
8997                         q->hook(dev);
8998         }
8999 }
9000
9001 /* Disable the VGA plane that we never use */
9002 static void i915_disable_vga(struct drm_device *dev)
9003 {
9004         struct drm_i915_private *dev_priv = dev->dev_private;
9005         u8 sr1;
9006         u32 vga_reg;
9007
9008         if (HAS_PCH_SPLIT(dev))
9009                 vga_reg = CPU_VGACNTRL;
9010         else
9011                 vga_reg = VGACNTRL;
9012
9013         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9014         outb(1, VGA_SR_INDEX);
9015         sr1 = inb(VGA_SR_DATA);
9016         outb(sr1 | 1<<5, VGA_SR_DATA);
9017         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9018         udelay(300);
9019
9020         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9021         POSTING_READ(vga_reg);
9022 }
9023
9024 void intel_modeset_init(struct drm_device *dev)
9025 {
9026         struct drm_i915_private *dev_priv = dev->dev_private;
9027         int i, ret;
9028
9029         drm_mode_config_init(dev);
9030
9031         dev->mode_config.min_width = 0;
9032         dev->mode_config.min_height = 0;
9033
9034         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9035
9036         intel_init_quirks(dev);
9037
9038         intel_init_display(dev);
9039
9040         if (IS_GEN2(dev)) {
9041                 dev->mode_config.max_width = 2048;
9042                 dev->mode_config.max_height = 2048;
9043         } else if (IS_GEN3(dev)) {
9044                 dev->mode_config.max_width = 4096;
9045                 dev->mode_config.max_height = 4096;
9046         } else {
9047                 dev->mode_config.max_width = 8192;
9048                 dev->mode_config.max_height = 8192;
9049         }
9050         dev->mode_config.fb_base = dev->agp->base;
9051
9052         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9053                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9054
9055         for (i = 0; i < dev_priv->num_pipe; i++) {
9056                 intel_crtc_init(dev, i);
9057                 ret = intel_plane_init(dev, i);
9058                 if (ret)
9059                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9060         }
9061
9062         /* Just disable it once at startup */
9063         i915_disable_vga(dev);
9064         intel_setup_outputs(dev);
9065
9066         intel_init_clock_gating(dev);
9067
9068         if (IS_IRONLAKE_M(dev)) {
9069                 ironlake_enable_drps(dev);
9070                 intel_init_emon(dev);
9071         }
9072
9073         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9074                 gen6_enable_rps(dev_priv);
9075                 gen6_update_ring_freq(dev_priv);
9076         }
9077
9078         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9079         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9080                     (unsigned long)dev);
9081 }
9082
9083 void intel_modeset_gem_init(struct drm_device *dev)
9084 {
9085         if (IS_IRONLAKE_M(dev))
9086                 ironlake_enable_rc6(dev);
9087
9088         intel_setup_overlay(dev);
9089 }
9090
9091 void intel_modeset_cleanup(struct drm_device *dev)
9092 {
9093         struct drm_i915_private *dev_priv = dev->dev_private;
9094         struct drm_crtc *crtc;
9095         struct intel_crtc *intel_crtc;
9096
9097         drm_kms_helper_poll_fini(dev);
9098         mutex_lock(&dev->struct_mutex);
9099
9100         intel_unregister_dsm_handler();
9101
9102
9103         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9104                 /* Skip inactive CRTCs */
9105                 if (!crtc->fb)
9106                         continue;
9107
9108                 intel_crtc = to_intel_crtc(crtc);
9109                 intel_increase_pllclock(crtc);
9110         }
9111
9112         intel_disable_fbc(dev);
9113
9114         if (IS_IRONLAKE_M(dev))
9115                 ironlake_disable_drps(dev);
9116         if (IS_GEN6(dev) || IS_GEN7(dev))
9117                 gen6_disable_rps(dev);
9118
9119         if (IS_IRONLAKE_M(dev))
9120                 ironlake_disable_rc6(dev);
9121
9122         mutex_unlock(&dev->struct_mutex);
9123
9124         /* Disable the irq before mode object teardown, for the irq might
9125          * enqueue unpin/hotplug work. */
9126         drm_irq_uninstall(dev);
9127         cancel_work_sync(&dev_priv->hotplug_work);
9128         cancel_work_sync(&dev_priv->rps_work);
9129
9130         /* flush any delayed tasks or pending work */
9131         flush_scheduled_work();
9132
9133         /* Shut off idle work before the crtcs get freed. */
9134         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9135                 intel_crtc = to_intel_crtc(crtc);
9136                 del_timer_sync(&intel_crtc->idle_timer);
9137         }
9138         del_timer_sync(&dev_priv->idle_timer);
9139         cancel_work_sync(&dev_priv->idle_work);
9140
9141         drm_mode_config_cleanup(dev);
9142 }
9143
9144 /*
9145  * Return which encoder is currently attached for connector.
9146  */
9147 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9148 {
9149         return &intel_attached_encoder(connector)->base;
9150 }
9151
9152 void intel_connector_attach_encoder(struct intel_connector *connector,
9153                                     struct intel_encoder *encoder)
9154 {
9155         connector->encoder = encoder;
9156         drm_mode_connector_attach_encoder(&connector->base,
9157                                           &encoder->base);
9158 }
9159
9160 /*
9161  * set vga decode state - true == enable VGA decode
9162  */
9163 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9164 {
9165         struct drm_i915_private *dev_priv = dev->dev_private;
9166         u16 gmch_ctrl;
9167
9168         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9169         if (state)
9170                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9171         else
9172                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9173         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9174         return 0;
9175 }
9176
9177 #ifdef CONFIG_DEBUG_FS
9178 #include <linux/seq_file.h>
9179
9180 struct intel_display_error_state {
9181         struct intel_cursor_error_state {
9182                 u32 control;
9183                 u32 position;
9184                 u32 base;
9185                 u32 size;
9186         } cursor[2];
9187
9188         struct intel_pipe_error_state {
9189                 u32 conf;
9190                 u32 source;
9191
9192                 u32 htotal;
9193                 u32 hblank;
9194                 u32 hsync;
9195                 u32 vtotal;
9196                 u32 vblank;
9197                 u32 vsync;
9198         } pipe[2];
9199
9200         struct intel_plane_error_state {
9201                 u32 control;
9202                 u32 stride;
9203                 u32 size;
9204                 u32 pos;
9205                 u32 addr;
9206                 u32 surface;
9207                 u32 tile_offset;
9208         } plane[2];
9209 };
9210
9211 struct intel_display_error_state *
9212 intel_display_capture_error_state(struct drm_device *dev)
9213 {
9214         drm_i915_private_t *dev_priv = dev->dev_private;
9215         struct intel_display_error_state *error;
9216         int i;
9217
9218         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9219         if (error == NULL)
9220                 return NULL;
9221
9222         for (i = 0; i < 2; i++) {
9223                 error->cursor[i].control = I915_READ(CURCNTR(i));
9224                 error->cursor[i].position = I915_READ(CURPOS(i));
9225                 error->cursor[i].base = I915_READ(CURBASE(i));
9226
9227                 error->plane[i].control = I915_READ(DSPCNTR(i));
9228                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9229                 error->plane[i].size = I915_READ(DSPSIZE(i));
9230                 error->plane[i].pos = I915_READ(DSPPOS(i));
9231                 error->plane[i].addr = I915_READ(DSPADDR(i));
9232                 if (INTEL_INFO(dev)->gen >= 4) {
9233                         error->plane[i].surface = I915_READ(DSPSURF(i));
9234                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9235                 }
9236
9237                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9238                 error->pipe[i].source = I915_READ(PIPESRC(i));
9239                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9240                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9241                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9242                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9243                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9244                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9245         }
9246
9247         return error;
9248 }
9249
9250 void
9251 intel_display_print_error_state(struct seq_file *m,
9252                                 struct drm_device *dev,
9253                                 struct intel_display_error_state *error)
9254 {
9255         int i;
9256
9257         for (i = 0; i < 2; i++) {
9258                 seq_printf(m, "Pipe [%d]:\n", i);
9259                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9260                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9261                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9262                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9263                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9264                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9265                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9266                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9267
9268                 seq_printf(m, "Plane [%d]:\n", i);
9269                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9270                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9271                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9272                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9273                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9274                 if (INTEL_INFO(dev)->gen >= 4) {
9275                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9276                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9277                 }
9278
9279                 seq_printf(m, "Cursor [%d]:\n", i);
9280                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9281                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9282                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9283         }
9284 }
9285 #endif