2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/slab.h>
21 #include <asm/pci_x86.h>
25 #include <xen/interface/physdev.h>
28 #define PREFIX "PCI: "
30 /* Indicate if the mmcfg resources have been placed into the resource table. */
31 static int __initdata pci_mmcfg_resources_inserted;
33 LIST_HEAD(pci_mmcfg_list);
35 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
38 release_resource(&cfg->res);
43 static __init void free_all_mmcfg(void)
45 struct pci_mmcfg_region *cfg, *tmp;
47 pci_mmcfg_arch_free();
48 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
49 pci_mmconfig_remove(cfg);
52 static __init void list_add_sorted(struct pci_mmcfg_region *new)
54 struct pci_mmcfg_region *cfg;
56 /* keep list sorted by segment and starting bus number */
57 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
58 if (cfg->segment > new->segment ||
59 (cfg->segment == new->segment &&
60 cfg->start_bus >= new->start_bus)) {
61 list_add_tail(&new->list, &cfg->list);
65 list_add_tail(&new->list, &pci_mmcfg_list);
68 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
71 struct pci_mmcfg_region *new;
77 new = kzalloc(sizeof(*new), GFP_KERNEL);
82 new->segment = segment;
83 new->start_bus = start;
89 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
90 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
91 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
92 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
93 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
94 res->name = new->name;
96 printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
97 "%pR (base %#lx)\n", segment, start, end, &new->res,
98 (unsigned long) addr);
103 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
105 struct pci_mmcfg_region *cfg;
107 list_for_each_entry(cfg, &pci_mmcfg_list, list)
108 if (cfg->segment == segment &&
109 cfg->start_bus <= bus && bus <= cfg->end_bus)
115 static const char __init *pci_mmcfg_e7520(void)
118 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
121 if (win == 0x0000 || win == 0xf000)
124 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
127 return "Intel Corporation E7520 Memory Controller Hub";
130 static const char __init *pci_mmcfg_intel_945(void)
132 u32 pciexbar, mask = 0, len = 0;
134 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
141 switch ((pciexbar >> 1) & 3) {
158 /* Errata #2, things break when not aligned on a 256Mb boundary */
159 /* Can only happen in 64M/128M mode */
161 if ((pciexbar & mask) & 0x0fffffffU)
164 /* Don't hit the APIC registers and their friends */
165 if ((pciexbar & mask) >= 0xf0000000U)
168 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
171 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
174 static const char __init *pci_mmcfg_amd_fam10h(void)
176 u32 low, high, address;
179 unsigned segnbits = 0, busnbits, end_bus;
181 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
184 address = MSR_FAM10H_MMIO_CONF_BASE;
185 if (rdmsr_safe(address, &low, &high))
192 /* mmconfig is not enable */
193 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
196 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
198 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
199 FAM10H_MMIO_CONF_BUSRANGE_MASK;
202 * only handle bus 0 ?
209 segnbits = busnbits - 8;
213 end_bus = (1 << busnbits) - 1;
214 for (i = 0; i < (1 << segnbits); i++)
215 if (pci_mmconfig_add(i, 0, end_bus,
216 base + (1<<28) * i) == NULL) {
221 return "AMD Family 10h NB";
224 static bool __initdata mcp55_checked;
225 static const char __init *pci_mmcfg_nvidia_mcp55(void)
228 int mcp55_mmconf_found = 0;
230 static const u32 extcfg_regnum = 0x90;
231 static const u32 extcfg_regsize = 4;
232 static const u32 extcfg_enable_mask = 1<<31;
233 static const u32 extcfg_start_mask = 0xff<<16;
234 static const int extcfg_start_shift = 16;
235 static const u32 extcfg_size_mask = 0x3<<28;
236 static const int extcfg_size_shift = 28;
237 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
238 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
239 static const int extcfg_base_lshift = 25;
242 * do check if amd fam10h already took over
244 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
247 mcp55_checked = true;
248 for (bus = 0; bus < 256; bus++) {
252 int start, size_index, end;
254 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
256 device = (l >> 16) & 0xffff;
258 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
261 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
262 extcfg_regsize, &extcfg);
264 if (!(extcfg & extcfg_enable_mask))
267 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
268 base = extcfg & extcfg_base_mask[size_index];
269 /* base could > 4G */
270 base <<= extcfg_base_lshift;
271 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
272 end = start + extcfg_sizebus[size_index] - 1;
273 if (pci_mmconfig_add(0, start, end, base) == NULL)
275 mcp55_mmconf_found++;
278 if (!mcp55_mmconf_found)
281 return "nVidia MCP55";
284 struct pci_mmcfg_hostbridge_probe {
289 const char *(*probe)(void);
292 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
293 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
294 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
295 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
296 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
297 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
298 0x1200, pci_mmcfg_amd_fam10h },
299 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
300 0x1200, pci_mmcfg_amd_fam10h },
301 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
302 0x0369, pci_mmcfg_nvidia_mcp55 },
305 static void __init pci_mmcfg_check_end_bus_number(void)
307 struct pci_mmcfg_region *cfg, *cfgx;
310 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
311 if (cfg->end_bus < cfg->start_bus)
314 /* Don't access the list head ! */
315 if (cfg->list.next == &pci_mmcfg_list)
318 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
319 if (cfg->end_bus >= cfgx->start_bus)
320 cfg->end_bus = cfgx->start_bus - 1;
324 static int __init pci_mmcfg_check_hostbridge(void)
337 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
338 bus = pci_mmcfg_probes[i].bus;
339 devfn = pci_mmcfg_probes[i].devfn;
340 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
342 device = (l >> 16) & 0xffff;
345 if (pci_mmcfg_probes[i].vendor == vendor &&
346 pci_mmcfg_probes[i].device == device)
347 name = pci_mmcfg_probes[i].probe();
350 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
354 /* some end_bus_number is crazy, fix it */
355 pci_mmcfg_check_end_bus_number();
357 return !list_empty(&pci_mmcfg_list);
360 static void __init pci_mmcfg_insert_resources(void)
362 struct pci_mmcfg_region *cfg;
364 list_for_each_entry(cfg, &pci_mmcfg_list, list)
365 insert_resource(&iomem_resource, &cfg->res);
367 /* Mark that the resources have been inserted. */
368 pci_mmcfg_resources_inserted = 1;
371 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
374 struct resource *mcfg_res = data;
375 struct acpi_resource_address64 address;
378 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
379 struct acpi_resource_fixed_memory32 *fixmem32 =
380 &res->data.fixed_memory32;
383 if ((mcfg_res->start >= fixmem32->address) &&
384 (mcfg_res->end < (fixmem32->address +
385 fixmem32->address_length))) {
387 return AE_CTRL_TERMINATE;
390 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
391 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
394 status = acpi_resource_to_address64(res, &address);
395 if (ACPI_FAILURE(status) ||
396 (address.address_length <= 0) ||
397 (address.resource_type != ACPI_MEMORY_RANGE))
400 if ((mcfg_res->start >= address.minimum) &&
401 (mcfg_res->end < (address.minimum + address.address_length))) {
403 return AE_CTRL_TERMINATE;
408 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
409 void *context, void **rv)
411 struct resource *mcfg_res = context;
413 acpi_walk_resources(handle, METHOD_NAME__CRS,
414 check_mcfg_resource, context);
417 return AE_CTRL_TERMINATE;
422 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
424 struct resource mcfg_res;
426 mcfg_res.start = start;
427 mcfg_res.end = end - 1;
430 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
433 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
436 return mcfg_res.flags;
439 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
441 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
442 struct pci_mmcfg_region *cfg, int with_e820)
444 u64 addr = cfg->res.start;
445 u64 size = resource_size(&cfg->res);
447 int valid = 0, num_buses;
449 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
451 if (size < (16UL<<20))
455 if (size >= (16UL<<20) || size == old_size) {
456 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
458 with_e820 ? "E820" : "ACPI motherboard resources");
461 if (old_size != size) {
463 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
464 num_buses = cfg->end_bus - cfg->start_bus + 1;
465 cfg->res.end = cfg->res.start +
466 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
467 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
468 "PCI MMCONFIG %04x [bus %02x-%02x]",
469 cfg->segment, cfg->start_bus, cfg->end_bus);
470 printk(KERN_INFO PREFIX
471 "MMCONFIG for %04x [bus%02x-%02x] "
472 "at %pR (base %#lx) (size reduced!)\n",
473 cfg->segment, cfg->start_bus, cfg->end_bus,
474 &cfg->res, (unsigned long) cfg->address);
480 struct physdev_pci_mmcfg_reserved r = {
481 .address = cfg->address,
482 .segment = cfg->segment,
483 .start_bus = cfg->start_bus,
484 .end_bus = cfg->end_bus,
485 .flags = valid ? XEN_PCI_MMCFG_RESERVED : 0
489 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pci_mmcfg_reserved, &r);
491 case 0: case -ENOSYS:
494 pr_warn(PREFIX "Failed to report MMCONFIG reservation"
495 " state for %04x [bus%02x-%02x] to hypervisor"
497 cfg->segment, cfg->start_bus, cfg->end_bus,
506 static void __init pci_mmcfg_reject_broken(int early)
508 struct pci_mmcfg_region *cfg;
510 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
513 if (!early && !acpi_disabled) {
514 valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
519 printk(KERN_ERR FW_BUG PREFIX
520 "MMCONFIG at %pR not reserved in "
521 "ACPI motherboard resources\n",
525 /* Don't try to do this check unless configuration
526 type 1 is available. how about type 2 ?*/
528 valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
537 printk(KERN_INFO PREFIX "not using MMCONFIG\n");
541 static int __initdata known_bridge;
543 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
544 struct acpi_mcfg_allocation *cfg)
548 if (cfg->address < 0xFFFFFFFF)
551 if (!strcmp(mcfg->header.oem_id, "SGI") ||
552 !strcmp(mcfg->header.oem_id, "SGI2"))
555 if (mcfg->header.revision >= 1) {
556 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
561 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
562 "is above 4GB, ignored\n", cfg->pci_segment,
563 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
567 static int __init pci_parse_mcfg(struct acpi_table_header *header)
569 struct acpi_table_mcfg *mcfg;
570 struct acpi_mcfg_allocation *cfg_table, *cfg;
577 mcfg = (struct acpi_table_mcfg *)header;
579 /* how many config structures do we have */
582 i = header->length - sizeof(struct acpi_table_mcfg);
583 while (i >= sizeof(struct acpi_mcfg_allocation)) {
585 i -= sizeof(struct acpi_mcfg_allocation);
588 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
592 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
593 for (i = 0; i < entries; i++) {
595 if (acpi_mcfg_check_entry(mcfg, cfg)) {
600 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
601 cfg->end_bus_number, cfg->address) == NULL) {
602 printk(KERN_WARNING PREFIX
603 "no memory for MCFG entries\n");
612 static void __init __pci_mmcfg_init(int early)
614 /* MMCONFIG disabled */
615 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
618 /* MMCONFIG already enabled */
619 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
622 /* for late to exit */
627 if (pci_mmcfg_check_hostbridge())
632 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
634 pci_mmcfg_reject_broken(early);
636 if (list_empty(&pci_mmcfg_list))
639 if (pcibios_last_bus < 0) {
640 const struct pci_mmcfg_region *cfg;
642 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
645 pcibios_last_bus = cfg->end_bus;
649 if (pci_mmcfg_arch_init())
650 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
653 * Signal not to attempt to insert mmcfg resources because
654 * the architecture mmcfg setup could not initialize.
656 pci_mmcfg_resources_inserted = 1;
660 void __init pci_mmcfg_early_init(void)
665 void __init pci_mmcfg_late_init(void)
670 static int __init pci_mmcfg_late_insert_resources(void)
673 * If resources are already inserted or we are not using MMCONFIG,
674 * don't insert the resources.
676 if ((pci_mmcfg_resources_inserted == 1) ||
677 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
678 list_empty(&pci_mmcfg_list))
682 * Attempt to insert the mmcfg resources but not with the busy flag
683 * marked so it won't cause request errors when __request_region is
686 pci_mmcfg_insert_resources();
692 * Perform MMCONFIG resource insertion after PCI initialization to allow for
693 * misprogrammed MCFG tables that state larger sizes but actually conflict
694 * with other system resources.
696 late_initcall(pci_mmcfg_late_insert_resources);