2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/freezer.h>
35 #include <linux/kthread.h>
36 #include <linux/jiffies.h> /* time_after() */
37 #include <linux/slab.h>
39 #include <acpi/acpi_bus.h>
41 #include <linux/bootmem.h>
48 #include <asm/proto.h>
51 #include <asm/timer.h>
52 #include <asm/i8259.h>
53 #include <asm/setup.h>
54 #include <asm/hw_irq.h>
59 #include <xen/interface/xen.h>
60 #include <xen/interface/physdev.h>
61 #include <xen/evtchn.h>
64 static void make_8259A_irq(unsigned int irq) { io_apic_irqs &= ~(1UL<<irq); }
65 static const struct legacy_pic xen_legacy_pic = {
66 .nr_legacy_irqs = NR_IRQS_LEGACY,
67 .make_irq = make_8259A_irq
69 #define legacy_pic (&xen_legacy_pic)
71 unsigned long io_apic_irqs;
72 #endif /* CONFIG_XEN */
74 #define __apicdebuginit(type) static type __init
75 #define for_each_irq_pin(entry, head) \
76 for (entry = head; entry; entry = entry->next)
79 * Is the SiS APIC rmw bug present ?
80 * -1 = don't know, 0 = no, 1 = yes
82 int sis_apic_bug = -1;
84 static DEFINE_RAW_SPINLOCK(ioapic_lock);
86 static DEFINE_RAW_SPINLOCK(vector_lock);
89 static struct ioapic {
91 * # of IRQ routing registers
96 * Saved state during suspend/resume, or while enabling intr-remap.
98 struct IO_APIC_route_entry *saved_registers;
100 /* I/O APIC config */
101 struct mpc_ioapic mp_config;
102 /* IO APIC gsi routing info */
103 struct mp_ioapic_gsi gsi_config;
104 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
105 } ioapics[MAX_IO_APICS];
107 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
109 int mpc_ioapic_id(int ioapic_idx)
111 return ioapics[ioapic_idx].mp_config.apicid;
114 unsigned int mpc_ioapic_addr(int ioapic_idx)
116 return ioapics[ioapic_idx].mp_config.apicaddr;
119 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
121 return &ioapics[ioapic_idx].gsi_config;
126 /* The one past the highest gsi number used */
129 /* MP IRQ source entries */
130 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
132 /* # of MP IRQ source entries */
137 static int nr_irqs_gsi = NR_IRQS_LEGACY;
140 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
141 int mp_bus_id_to_type[MAX_MP_BUSSES];
144 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
146 int skip_ioapic_setup;
149 * disable_ioapic_support() - disables ioapic support at runtime
151 static void __init _disable_ioapic_support(void)
155 noioapicreroute = -1;
157 skip_ioapic_setup = 1;
160 static int __init parse_noapic(char *str)
162 /* disable IO-APIC */
163 _disable_ioapic_support();
166 early_param("noapic", parse_noapic);
168 static int io_apic_setup_irq_pin(unsigned int irq, int node,
169 struct io_apic_irq_attr *attr);
171 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
172 void mp_save_irq(struct mpc_intsrc *m)
176 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
177 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
178 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
179 m->srcbusirq, m->dstapic, m->dstirq);
181 for (i = 0; i < mp_irq_entries; i++) {
182 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
186 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
187 if (++mp_irq_entries == MAX_IRQ_SOURCES)
188 panic("Max # of irq sources exceeded!!\n");
192 struct irq_pin_list {
194 struct irq_pin_list *next;
197 static struct irq_pin_list *alloc_irq_pin_list(int node)
199 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
203 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
204 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
206 int __init arch_early_irq_init(void)
211 if (!legacy_pic->nr_legacy_irqs)
214 for (i = 0; i < nr_ioapics; i++) {
215 ioapics[i].saved_registers =
216 kzalloc(sizeof(struct IO_APIC_route_entry) *
217 ioapics[i].nr_registers, GFP_KERNEL);
218 if (!ioapics[i].saved_registers)
219 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
223 count = ARRAY_SIZE(irq_cfgx);
224 node = cpu_to_node(0);
226 /* Make sure the legacy interrupts are marked in the bitmap */
227 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
229 for (i = 0; i < count; i++) {
230 irq_set_chip_data(i, &cfg[i]);
231 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
232 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
234 * For legacy IRQ's, start with assigning irq0 to irq15 to
235 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
237 if (i < legacy_pic->nr_legacy_irqs) {
238 cfg[i].vector = IRQ0_VECTOR + i;
239 cpumask_set_cpu(0, cfg[i].domain);
246 static struct irq_cfg *irq_cfg(unsigned int irq)
248 return irq_get_chip_data(irq);
251 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
255 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
258 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
260 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
264 free_cpumask_var(cfg->domain);
270 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
274 irq_set_chip_data(at, NULL);
275 free_cpumask_var(cfg->domain);
276 free_cpumask_var(cfg->old_domain);
280 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
282 int res = irq_alloc_desc_at(at, node);
288 cfg = irq_get_chip_data(at);
293 cfg = alloc_irq_cfg(at, node);
295 irq_set_chip_data(at, cfg);
301 static int alloc_irq_from(unsigned int from, int node)
303 return irq_alloc_desc_from(from, node);
306 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
308 free_irq_cfg(at, cfg);
314 unsigned int unused[3];
316 unsigned int unused2[11];
320 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
322 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
323 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
326 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
328 struct io_apic __iomem *io_apic = io_apic_base(apic);
329 writel(vector, &io_apic->eoi);
331 #endif /* !CONFIG_XEN */
333 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
336 struct io_apic __iomem *io_apic = io_apic_base(apic);
337 writel(reg, &io_apic->index);
338 return readl(&io_apic->data);
340 struct physdev_apic apic_op;
343 apic_op.apic_physbase = mpc_ioapic_addr(apic);
345 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
348 return apic_op.value;
352 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
355 struct io_apic __iomem *io_apic = io_apic_base(apic);
356 writel(reg, &io_apic->index);
357 writel(value, &io_apic->data);
359 struct physdev_apic apic_op;
361 apic_op.apic_physbase = mpc_ioapic_addr(apic);
363 apic_op.value = value;
364 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
369 #define io_apic_modify io_apic_write
372 * Re-write a value: to be used for read-modify-write
373 * cycles where the read already set up the index register.
375 * Older SiS APIC requires we rewrite the index register
377 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
379 struct io_apic __iomem *io_apic = io_apic_base(apic);
382 writel(reg, &io_apic->index);
383 writel(value, &io_apic->data);
386 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
388 struct irq_pin_list *entry;
391 raw_spin_lock_irqsave(&ioapic_lock, flags);
392 for_each_irq_pin(entry, cfg->irq_2_pin) {
397 reg = io_apic_read(entry->apic, 0x10 + pin*2);
398 /* Is the remote IRR bit set? */
399 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
400 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
404 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
408 #endif /* CONFIG_XEN */
411 struct { u32 w1, w2; };
412 struct IO_APIC_route_entry entry;
416 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
418 union entry_union eu;
420 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
421 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
425 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
427 union entry_union eu;
429 raw_spin_lock_irqsave(&ioapic_lock, flags);
430 eu.entry = __ioapic_read_entry(apic, pin);
431 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
437 * When we write a new IO APIC routing entry, we need to write the high
438 * word first! If the mask bit in the low word is clear, we will enable
439 * the interrupt, and we need to make sure the entry is fully populated
440 * before that happens.
443 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
445 union entry_union eu = {{0, 0}};
448 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
449 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
452 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
455 raw_spin_lock_irqsave(&ioapic_lock, flags);
456 __ioapic_write_entry(apic, pin, e);
457 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
462 * When we mask an IO APIC routing entry, we need to write the low
463 * word first, in order to set the mask bit before we change the
466 static void ioapic_mask_entry(int apic, int pin)
469 union entry_union eu = { .entry.mask = 1 };
471 raw_spin_lock_irqsave(&ioapic_lock, flags);
472 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
473 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
474 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
478 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
479 * shared ISA-space IRQs, so we have to support them. We are super
480 * fast in the common case, and fast for shared ISA-space IRQs.
483 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
485 struct irq_pin_list **last, *entry;
487 /* don't allow duplicates */
488 last = &cfg->irq_2_pin;
489 for_each_irq_pin(entry, cfg->irq_2_pin) {
490 if (entry->apic == apic && entry->pin == pin)
495 entry = alloc_irq_pin_list(node);
497 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
508 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
510 if (__add_pin_to_irq_node(cfg, node, apic, pin))
511 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
515 * Reroute an IRQ to a different pin.
517 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
518 int oldapic, int oldpin,
519 int newapic, int newpin)
521 struct irq_pin_list *entry;
523 for_each_irq_pin(entry, cfg->irq_2_pin) {
524 if (entry->apic == oldapic && entry->pin == oldpin) {
525 entry->apic = newapic;
527 /* every one is different, right? */
532 /* old apic/pin didn't exist, so just add new ones */
533 add_pin_to_irq_node(cfg, node, newapic, newpin);
536 static void __io_apic_modify_irq(struct irq_pin_list *entry,
537 int mask_and, int mask_or,
538 void (*final)(struct irq_pin_list *entry))
540 unsigned int reg, pin;
543 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
546 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
551 static void io_apic_modify_irq(struct irq_cfg *cfg,
552 int mask_and, int mask_or,
553 void (*final)(struct irq_pin_list *entry))
555 struct irq_pin_list *entry;
557 for_each_irq_pin(entry, cfg->irq_2_pin)
558 __io_apic_modify_irq(entry, mask_and, mask_or, final);
561 static void io_apic_sync(struct irq_pin_list *entry)
564 * Synchronize the IO-APIC and the CPU by doing
565 * a dummy read from the IO-APIC
567 struct io_apic __iomem *io_apic;
568 io_apic = io_apic_base(entry->apic);
569 readl(&io_apic->data);
572 static void mask_ioapic(struct irq_cfg *cfg)
576 raw_spin_lock_irqsave(&ioapic_lock, flags);
577 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
578 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
581 static void mask_ioapic_irq(struct irq_data *data)
583 mask_ioapic(data->chip_data);
586 static void __unmask_ioapic(struct irq_cfg *cfg)
588 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
591 static void unmask_ioapic(struct irq_cfg *cfg)
595 raw_spin_lock_irqsave(&ioapic_lock, flags);
596 __unmask_ioapic(cfg);
597 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
600 static void unmask_ioapic_irq(struct irq_data *data)
602 unmask_ioapic(data->chip_data);
606 * IO-APIC versions below 0x20 don't support EOI register.
607 * For the record, here is the information about various versions:
609 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
610 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
613 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
614 * version as 0x2. This is an error with documentation and these ICH chips
615 * use io-apic's of version 0x20.
617 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
618 * Otherwise, we simulate the EOI message manually by changing the trigger
619 * mode to edge and then back to level, with RTE being masked during this.
621 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
623 if (mpc_ioapic_ver(apic) >= 0x20) {
625 * Intr-remapping uses pin number as the virtual vector
626 * in the RTE. Actual vector is programmed in
627 * intr-remapping table entry. Hence for the io-apic
628 * EOI we use the pin number.
630 if (cfg && irq_remapped(cfg))
631 io_apic_eoi(apic, pin);
633 io_apic_eoi(apic, vector);
635 struct IO_APIC_route_entry entry, entry1;
637 entry = entry1 = __ioapic_read_entry(apic, pin);
640 * Mask the entry and change the trigger mode to edge.
643 entry1.trigger = IOAPIC_EDGE;
645 __ioapic_write_entry(apic, pin, entry1);
648 * Restore the previous level triggered entry.
650 __ioapic_write_entry(apic, pin, entry);
654 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
656 struct irq_pin_list *entry;
659 raw_spin_lock_irqsave(&ioapic_lock, flags);
660 for_each_irq_pin(entry, cfg->irq_2_pin)
661 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
662 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
665 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
667 struct IO_APIC_route_entry entry;
669 /* Check delivery_mode to be sure we're not clearing an SMI pin */
670 entry = ioapic_read_entry(apic, pin);
671 if (entry.delivery_mode == dest_SMI)
675 * Make sure the entry is masked and re-read the contents to check
676 * if it is a level triggered pin and if the remote-IRR is set.
680 ioapic_write_entry(apic, pin, entry);
681 entry = ioapic_read_entry(apic, pin);
688 * Make sure the trigger mode is set to level. Explicit EOI
689 * doesn't clear the remote-IRR if the trigger mode is not
692 if (!entry.trigger) {
693 entry.trigger = IOAPIC_LEVEL;
694 ioapic_write_entry(apic, pin, entry);
697 raw_spin_lock_irqsave(&ioapic_lock, flags);
698 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
699 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
703 * Clear the rest of the bits in the IO-APIC RTE except for the mask
706 ioapic_mask_entry(apic, pin);
707 entry = ioapic_read_entry(apic, pin);
709 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
710 mpc_ioapic_id(apic), pin);
713 static void clear_IO_APIC (void)
717 for (apic = 0; apic < nr_ioapics; apic++)
718 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
719 clear_IO_APIC_pin(apic, pin);
722 #define add_pin_to_irq_node(cfg, node, apic, pin)
723 #define __add_pin_to_irq_node(cfg, node, apic, pin) 0
724 #endif /* !CONFIG_XEN */
728 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
729 * specific CPU-side IRQs.
733 static int pirq_entries[MAX_PIRQS] = {
734 [0 ... MAX_PIRQS - 1] = -1
737 static int __init ioapic_pirq_setup(char *str)
740 int ints[MAX_PIRQS+1];
742 get_options(str, ARRAY_SIZE(ints), ints);
744 apic_printk(APIC_VERBOSE, KERN_INFO
745 "PIRQ redirection, working around broken MP-BIOS.\n");
747 if (ints[0] < MAX_PIRQS)
750 for (i = 0; i < max; i++) {
751 apic_printk(APIC_VERBOSE, KERN_DEBUG
752 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
754 * PIRQs are mapped upside down, usually.
756 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
761 __setup("pirq=", ioapic_pirq_setup);
762 #endif /* CONFIG_X86_32 */
766 * Saves all the IO-APIC RTE's
768 int save_ioapic_entries(void)
773 for (apic = 0; apic < nr_ioapics; apic++) {
774 if (!ioapics[apic].saved_registers) {
779 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
780 ioapics[apic].saved_registers[pin] =
781 ioapic_read_entry(apic, pin);
788 * Mask all IO APIC entries.
790 void mask_ioapic_entries(void)
794 for (apic = 0; apic < nr_ioapics; apic++) {
795 if (!ioapics[apic].saved_registers)
798 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
799 struct IO_APIC_route_entry entry;
801 entry = ioapics[apic].saved_registers[pin];
804 ioapic_write_entry(apic, pin, entry);
811 * Restore IO APIC entries which was saved in the ioapic structure.
813 int restore_ioapic_entries(void)
817 for (apic = 0; apic < nr_ioapics; apic++) {
818 if (!ioapics[apic].saved_registers)
821 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
822 ioapic_write_entry(apic, pin,
823 ioapics[apic].saved_registers[pin]);
827 #endif /* CONFIG_XEN */
830 * Find the IRQ entry number of a certain pin.
832 static int find_irq_entry(int ioapic_idx, int pin, int type)
836 for (i = 0; i < mp_irq_entries; i++)
837 if (mp_irqs[i].irqtype == type &&
838 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
839 mp_irqs[i].dstapic == MP_APIC_ALL) &&
840 mp_irqs[i].dstirq == pin)
848 * Find the pin to which IRQ[irq] (ISA) is connected
850 static int __init find_isa_irq_pin(int irq, int type)
854 for (i = 0; i < mp_irq_entries; i++) {
855 int lbus = mp_irqs[i].srcbus;
857 if (test_bit(lbus, mp_bus_not_pci) &&
858 (mp_irqs[i].irqtype == type) &&
859 (mp_irqs[i].srcbusirq == irq))
861 return mp_irqs[i].dstirq;
866 static int __init find_isa_irq_apic(int irq, int type)
870 for (i = 0; i < mp_irq_entries; i++) {
871 int lbus = mp_irqs[i].srcbus;
873 if (test_bit(lbus, mp_bus_not_pci) &&
874 (mp_irqs[i].irqtype == type) &&
875 (mp_irqs[i].srcbusirq == irq))
879 if (i < mp_irq_entries) {
882 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
883 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
891 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
893 * EISA Edge/Level control register, ELCR
895 static int EISA_ELCR(unsigned int irq)
897 if (irq < legacy_pic->nr_legacy_irqs) {
898 unsigned int port = 0x4d0 + (irq >> 3);
899 return (inb(port) >> (irq & 7)) & 1;
901 apic_printk(APIC_VERBOSE, KERN_INFO
902 "Broken MPtable reports ISA irq %d\n", irq);
908 /* ISA interrupts are always polarity zero edge triggered,
909 * when listed as conforming in the MP table. */
911 #define default_ISA_trigger(idx) (0)
912 #define default_ISA_polarity(idx) (0)
914 /* EISA interrupts are always polarity zero and can be edge or level
915 * trigger depending on the ELCR value. If an interrupt is listed as
916 * EISA conforming in the MP table, that means its trigger type must
917 * be read in from the ELCR */
919 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
920 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
922 /* PCI interrupts are always polarity one level triggered,
923 * when listed as conforming in the MP table. */
925 #define default_PCI_trigger(idx) (1)
926 #define default_PCI_polarity(idx) (1)
928 /* MCA interrupts are always polarity zero level triggered,
929 * when listed as conforming in the MP table. */
931 #define default_MCA_trigger(idx) (1)
932 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
934 static int irq_polarity(int idx)
936 int bus = mp_irqs[idx].srcbus;
940 * Determine IRQ line polarity (high active or low active):
942 switch (mp_irqs[idx].irqflag & 3)
944 case 0: /* conforms, ie. bus-type dependent polarity */
945 if (test_bit(bus, mp_bus_not_pci))
946 polarity = default_ISA_polarity(idx);
948 polarity = default_PCI_polarity(idx);
950 case 1: /* high active */
955 case 2: /* reserved */
957 printk(KERN_WARNING "broken BIOS!!\n");
961 case 3: /* low active */
966 default: /* invalid */
968 printk(KERN_WARNING "broken BIOS!!\n");
976 static int irq_trigger(int idx)
978 int bus = mp_irqs[idx].srcbus;
982 * Determine IRQ trigger mode (edge or level sensitive):
984 switch ((mp_irqs[idx].irqflag>>2) & 3)
986 case 0: /* conforms, ie. bus-type dependent */
987 if (test_bit(bus, mp_bus_not_pci))
988 trigger = default_ISA_trigger(idx);
990 trigger = default_PCI_trigger(idx);
991 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
992 switch (mp_bus_id_to_type[bus]) {
993 case MP_BUS_ISA: /* ISA pin */
995 /* set before the switch */
998 case MP_BUS_EISA: /* EISA pin */
1000 trigger = default_EISA_trigger(idx);
1003 case MP_BUS_PCI: /* PCI pin */
1005 /* set before the switch */
1008 case MP_BUS_MCA: /* MCA pin */
1010 trigger = default_MCA_trigger(idx);
1015 printk(KERN_WARNING "broken BIOS!!\n");
1027 case 2: /* reserved */
1029 printk(KERN_WARNING "broken BIOS!!\n");
1038 default: /* invalid */
1040 printk(KERN_WARNING "broken BIOS!!\n");
1048 static int pin_2_irq(int idx, int apic, int pin)
1051 int bus = mp_irqs[idx].srcbus;
1052 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
1055 * Debugging check, we are in big trouble if this message pops up!
1057 if (mp_irqs[idx].dstirq != pin)
1058 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1060 if (test_bit(bus, mp_bus_not_pci)) {
1061 irq = mp_irqs[idx].srcbusirq;
1063 u32 gsi = gsi_cfg->gsi_base + pin;
1065 if (gsi >= NR_IRQS_LEGACY)
1068 irq = gsi_top + gsi;
1071 #ifdef CONFIG_X86_32
1073 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1075 if ((pin >= 16) && (pin <= 23)) {
1076 if (pirq_entries[pin-16] != -1) {
1077 if (!pirq_entries[pin-16]) {
1078 apic_printk(APIC_VERBOSE, KERN_DEBUG
1079 "disabling PIRQ%d\n", pin-16);
1081 irq = pirq_entries[pin-16];
1082 apic_printk(APIC_VERBOSE, KERN_DEBUG
1083 "using PIRQ%d -> IRQ %d\n",
1094 * Find a specific PCI IRQ entry.
1095 * Not an __init, possibly needed by modules
1097 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1098 struct io_apic_irq_attr *irq_attr)
1100 int ioapic_idx, i, best_guess = -1;
1102 apic_printk(APIC_DEBUG,
1103 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1105 if (test_bit(bus, mp_bus_not_pci)) {
1106 apic_printk(APIC_VERBOSE,
1107 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1110 for (i = 0; i < mp_irq_entries; i++) {
1111 int lbus = mp_irqs[i].srcbus;
1113 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1114 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1115 mp_irqs[i].dstapic == MP_APIC_ALL)
1118 if (!test_bit(lbus, mp_bus_not_pci) &&
1119 !mp_irqs[i].irqtype &&
1121 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1122 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1124 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1127 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1128 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1135 * Use the first all-but-pin matching entry as a
1136 * best-guess fuzzy result for broken mptables.
1138 if (best_guess < 0) {
1139 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1149 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1152 void lock_vector_lock(void)
1154 /* Used to the online set of cpus does not change
1155 * during assign_irq_vector.
1157 raw_spin_lock(&vector_lock);
1160 void unlock_vector_lock(void)
1162 raw_spin_unlock(&vector_lock);
1166 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1169 * NOTE! The local APIC isn't very good at handling
1170 * multiple interrupts at the same interrupt level.
1171 * As the interrupt level is determined by taking the
1172 * vector number and shifting that right by 4, we
1173 * want to spread these out a bit so that they don't
1174 * all fall in the same interrupt level.
1176 * Also, we've got to be careful not to trash gate
1177 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1179 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1180 static int current_offset = VECTOR_OFFSET_START % 8;
1181 unsigned int old_vector;
1183 cpumask_var_t tmp_mask;
1185 if (cfg->move_in_progress)
1188 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1191 old_vector = cfg->vector;
1193 cpumask_and(tmp_mask, mask, cpu_online_mask);
1194 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1195 if (!cpumask_empty(tmp_mask)) {
1196 free_cpumask_var(tmp_mask);
1201 /* Only try and allocate irqs on cpus that are present */
1203 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1207 apic->vector_allocation_domain(cpu, tmp_mask);
1209 vector = current_vector;
1210 offset = current_offset;
1213 if (vector >= first_system_vector) {
1214 /* If out of vectors on large boxen, must share them. */
1215 offset = (offset + 1) % 8;
1216 vector = FIRST_EXTERNAL_VECTOR + offset;
1218 if (unlikely(current_vector == vector))
1221 if (test_bit(vector, used_vectors))
1225 if (vector == KDBENTER_VECTOR)
1227 #endif /* CONFIG_KDB */
1228 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1229 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1232 current_vector = vector;
1233 current_offset = offset;
1235 cfg->move_in_progress = 1;
1236 cpumask_copy(cfg->old_domain, cfg->domain);
1238 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1239 per_cpu(vector_irq, new_cpu)[vector] = irq;
1240 cfg->vector = vector;
1241 cpumask_copy(cfg->domain, tmp_mask);
1245 free_cpumask_var(tmp_mask);
1249 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1252 unsigned long flags;
1254 raw_spin_lock_irqsave(&vector_lock, flags);
1255 err = __assign_irq_vector(irq, cfg, mask);
1256 raw_spin_unlock_irqrestore(&vector_lock, flags);
1260 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1264 BUG_ON(!cfg->vector);
1266 vector = cfg->vector;
1267 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1268 per_cpu(vector_irq, cpu)[vector] = -1;
1271 cpumask_clear(cfg->domain);
1273 if (likely(!cfg->move_in_progress))
1275 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1276 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1278 if (per_cpu(vector_irq, cpu)[vector] != irq)
1280 per_cpu(vector_irq, cpu)[vector] = -1;
1284 cfg->move_in_progress = 0;
1287 void __setup_vector_irq(int cpu)
1289 /* Initialize vector_irq on a new cpu */
1291 struct irq_cfg *cfg;
1294 * vector_lock will make sure that we don't run into irq vector
1295 * assignments that might be happening on another cpu in parallel,
1296 * while we setup our initial vector to irq mappings.
1298 raw_spin_lock(&vector_lock);
1299 /* Mark the inuse vectors */
1300 for_each_active_irq(irq) {
1301 cfg = irq_get_chip_data(irq);
1305 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1306 * will be part of the irq_cfg's domain.
1308 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1309 cpumask_set_cpu(cpu, cfg->domain);
1311 if (!cpumask_test_cpu(cpu, cfg->domain))
1313 vector = cfg->vector;
1314 per_cpu(vector_irq, cpu)[vector] = irq;
1316 /* Mark the free vectors */
1317 for (vector = 0; vector < NR_VECTORS; ++vector) {
1318 irq = per_cpu(vector_irq, cpu)[vector];
1323 if (!cpumask_test_cpu(cpu, cfg->domain))
1324 per_cpu(vector_irq, cpu)[vector] = -1;
1326 raw_spin_unlock(&vector_lock);
1329 static struct irq_chip ioapic_chip;
1331 #ifdef CONFIG_X86_32
1332 static inline int IO_APIC_irq_trigger(int irq)
1336 for (apic = 0; apic < nr_ioapics; apic++) {
1337 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1338 idx = find_irq_entry(apic, pin, mp_INT);
1339 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1340 return irq_trigger(idx);
1344 * nonexistent IRQs are edge default
1349 static inline int IO_APIC_irq_trigger(int irq)
1355 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1356 unsigned long trigger)
1358 struct irq_chip *chip = &ioapic_chip;
1359 irq_flow_handler_t hdl;
1362 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1363 trigger == IOAPIC_LEVEL) {
1364 irq_set_status_flags(irq, IRQ_LEVEL);
1367 irq_clear_status_flags(irq, IRQ_LEVEL);
1371 if (irq_remapped(cfg)) {
1372 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1373 irq_remap_modify_chip_defaults(chip);
1374 fasteoi = trigger != 0;
1377 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1378 irq_set_chip_and_handler_name(irq, chip, hdl,
1379 fasteoi ? "fasteoi" : "edge");
1383 static int setup_ir_ioapic_entry(int irq,
1384 struct IR_IO_APIC_route_entry *entry,
1385 unsigned int destination, int vector,
1386 struct io_apic_irq_attr *attr)
1390 int ioapic_id = mpc_ioapic_id(attr->ioapic);
1391 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
1394 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
1398 index = alloc_irte(iommu, irq, 1);
1400 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
1404 prepare_irte(&irte, vector, destination);
1406 /* Set source-id of interrupt request */
1407 set_ioapic_sid(&irte, ioapic_id);
1409 modify_irte(irq, &irte);
1411 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1412 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1413 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1414 "Avail:%X Vector:%02X Dest:%08X "
1415 "SID:%04X SQ:%X SVT:%X)\n",
1416 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1417 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1418 irte.avail, irte.vector, irte.dest_id,
1419 irte.sid, irte.sq, irte.svt);
1421 memset(entry, 0, sizeof(*entry));
1423 entry->index2 = (index >> 15) & 0x1;
1426 entry->index = (index & 0x7fff);
1428 * IO-APIC RTE will be configured with virtual vector.
1429 * irq handler will do the explicit EOI to the io-apic.
1431 entry->vector = attr->ioapic_pin;
1432 entry->mask = 0; /* enable IRQ */
1433 entry->trigger = attr->trigger;
1434 entry->polarity = attr->polarity;
1436 /* Mask level triggered irqs.
1437 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1444 #else /* !CONFIG_XEN */
1445 #define __clear_irq_vector(irq, cfg) ((void)0)
1446 #define ioapic_register_intr(irq, cfg, trigger) evtchn_register_pirq(irq)
1449 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1450 unsigned int destination, int vector,
1451 struct io_apic_irq_attr *attr)
1454 if (intr_remapping_enabled)
1455 return setup_ir_ioapic_entry(irq,
1456 (struct IR_IO_APIC_route_entry *)entry,
1457 destination, vector, attr);
1460 memset(entry, 0, sizeof(*entry));
1462 entry->delivery_mode = apic->irq_delivery_mode;
1463 entry->dest_mode = apic->irq_dest_mode;
1464 entry->dest = destination;
1465 entry->vector = vector;
1466 entry->mask = 0; /* enable IRQ */
1467 entry->trigger = attr->trigger;
1468 entry->polarity = attr->polarity;
1471 * Mask level triggered irqs.
1472 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1480 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1481 struct io_apic_irq_attr *attr)
1483 struct IO_APIC_route_entry entry;
1486 if (!IO_APIC_IRQ(irq))
1490 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1491 * controllers like 8259. Now that IO-APIC can handle this irq, update
1494 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1495 apic->vector_allocation_domain(0, cfg->domain);
1498 * For legacy IRQs we may get here before trigger mode and polarity
1499 * get obtained, but Xen refuses to set those through
1500 * PHYSDEVOP_setup_gsi more than once (perhaps even at all).
1502 if (irq >= legacy_pic->nr_legacy_irqs
1503 || test_bit(attr->ioapic_pin,
1504 ioapics[attr->ioapic].pin_programmed)) {
1505 struct physdev_setup_gsi setup_gsi = {
1507 .triggering = attr->trigger,
1508 .polarity = attr->polarity
1510 struct physdev_map_pirq map_pirq = {
1511 .domid = DOMID_SELF,
1512 .type = MAP_PIRQ_TYPE_GSI,
1517 switch (HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi,
1520 if (irq < legacy_pic->nr_legacy_irqs)
1524 evtchn_register_pirq(irq);
1525 if (HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
1527 /* fake (for init_IO_APIC_traps()): */
1535 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1539 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1541 dest = 0; /* meaningless */
1544 apic_printk(APIC_VERBOSE,KERN_DEBUG
1545 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1546 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1547 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1548 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1550 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1551 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1552 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1553 __clear_irq_vector(irq, cfg);
1558 ioapic_register_intr(irq, cfg, attr->trigger);
1560 if (irq < legacy_pic->nr_legacy_irqs)
1561 legacy_pic->mask(irq);
1564 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1567 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1572 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1573 mpc_ioapic_id(ioapic_idx), pin);
1577 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1579 int idx, node = cpu_to_node(0);
1580 struct io_apic_irq_attr attr;
1581 unsigned int pin, irq;
1583 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1584 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1585 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1588 irq = pin_2_irq(idx, ioapic_idx, pin);
1590 if ((ioapic_idx > 0) && (irq > 16))
1594 if (irq < PIRQ_BASE || irq >= PIRQ_BASE + nr_pirqs)
1598 * Skip the timer IRQ if there's a quirk handler
1599 * installed and if it returns 1:
1601 if (apic->multi_timer_check &&
1602 apic->multi_timer_check(ioapic_idx, irq))
1606 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1609 io_apic_setup_irq_pin(irq, node, &attr);
1613 static void __init setup_IO_APIC_irqs(void)
1615 unsigned int ioapic_idx;
1617 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1619 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1620 __io_apic_setup_irqs(ioapic_idx);
1624 * for the gsit that is not in first ioapic
1625 * but could not use acpi_register_gsi()
1626 * like some special sci in IBM x3330
1628 void setup_IO_APIC_irq_extra(u32 gsi)
1630 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1631 struct io_apic_irq_attr attr;
1634 * Convert 'gsi' to 'ioapic.pin'.
1636 ioapic_idx = mp_find_ioapic(gsi);
1640 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1641 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1645 irq = pin_2_irq(idx, ioapic_idx, pin);
1647 if (irq < PIRQ_BASE || irq >= PIRQ_BASE + nr_pirqs)
1651 /* Only handle the non legacy irqs on secondary ioapics */
1652 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1655 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1658 io_apic_setup_irq_pin_once(irq, node, &attr);
1663 * Set up the timer pin, possibly with the 8259A-master behind.
1665 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1666 unsigned int pin, int vector)
1668 struct IO_APIC_route_entry entry;
1670 if (intr_remapping_enabled)
1673 memset(&entry, 0, sizeof(entry));
1676 * We use logical delivery to get the timer IRQ
1679 entry.dest_mode = apic->irq_dest_mode;
1680 entry.mask = 0; /* don't mask IRQ for edge */
1681 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1682 entry.delivery_mode = apic->irq_delivery_mode;
1685 entry.vector = vector;
1688 * The timer IRQ doesn't have to know that behind the
1689 * scene we may have a 8259A-master in AEOI mode ...
1691 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1695 * Add it to the IO-APIC irq-routing table:
1697 ioapic_write_entry(ioapic_idx, pin, entry);
1700 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1703 union IO_APIC_reg_00 reg_00;
1704 union IO_APIC_reg_01 reg_01;
1705 union IO_APIC_reg_02 reg_02;
1706 union IO_APIC_reg_03 reg_03;
1707 unsigned long flags;
1709 raw_spin_lock_irqsave(&ioapic_lock, flags);
1710 reg_00.raw = io_apic_read(ioapic_idx, 0);
1711 reg_01.raw = io_apic_read(ioapic_idx, 1);
1712 if (reg_01.bits.version >= 0x10)
1713 reg_02.raw = io_apic_read(ioapic_idx, 2);
1714 if (reg_01.bits.version >= 0x20)
1715 reg_03.raw = io_apic_read(ioapic_idx, 3);
1716 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1719 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1720 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1721 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1722 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1723 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1725 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1726 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1727 reg_01.bits.entries);
1729 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1730 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1731 reg_01.bits.version);
1734 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1735 * but the value of reg_02 is read as the previous read register
1736 * value, so ignore it if reg_02 == reg_01.
1738 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1739 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1740 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1744 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1745 * or reg_03, but the value of reg_0[23] is read as the previous read
1746 * register value, so ignore it if reg_03 == reg_0[12].
1748 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1749 reg_03.raw != reg_01.raw) {
1750 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1751 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1754 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1756 if (intr_remapping_enabled) {
1757 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1758 " Pol Stat Indx2 Zero Vect:\n");
1760 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1761 " Stat Dmod Deli Vect:\n");
1764 for (i = 0; i <= reg_01.bits.entries; i++) {
1765 if (intr_remapping_enabled) {
1766 struct IO_APIC_route_entry entry;
1767 struct IR_IO_APIC_route_entry *ir_entry;
1769 entry = ioapic_read_entry(ioapic_idx, i);
1770 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1771 printk(KERN_DEBUG " %02x %04X ",
1775 printk("%1d %1d %1d %1d %1d "
1776 "%1d %1d %X %02X\n",
1782 ir_entry->delivery_status,
1788 struct IO_APIC_route_entry entry;
1790 entry = ioapic_read_entry(ioapic_idx, i);
1791 printk(KERN_DEBUG " %02x %02X ",
1795 printk("%1d %1d %1d %1d %1d "
1801 entry.delivery_status,
1803 entry.delivery_mode,
1810 __apicdebuginit(void) print_IO_APICs(void)
1813 struct irq_cfg *cfg;
1815 struct irq_chip *chip;
1817 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1818 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1819 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1820 mpc_ioapic_id(ioapic_idx),
1821 ioapics[ioapic_idx].nr_registers);
1824 * We are a bit conservative about what we expect. We have to
1825 * know about every hardware change ASAP.
1827 printk(KERN_INFO "testing the IO APIC.......................\n");
1829 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1830 print_IO_APIC(ioapic_idx);
1832 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1833 for_each_active_irq(irq) {
1834 struct irq_pin_list *entry;
1836 chip = irq_get_chip(irq);
1837 if (chip != &ioapic_chip)
1840 cfg = irq_get_chip_data(irq);
1843 entry = cfg->irq_2_pin;
1846 printk(KERN_DEBUG "IRQ%d ", irq);
1847 for_each_irq_pin(entry, cfg->irq_2_pin)
1848 printk("-> %d:%d", entry->apic, entry->pin);
1852 printk(KERN_INFO ".................................... done.\n");
1855 __apicdebuginit(void) print_APIC_field(int base)
1861 for (i = 0; i < 8; i++)
1862 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1864 printk(KERN_CONT "\n");
1867 __apicdebuginit(void) print_local_APIC(void *dummy)
1869 unsigned int i, v, ver, maxlvt;
1872 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1873 smp_processor_id(), hard_smp_processor_id());
1874 v = apic_read(APIC_ID);
1875 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1876 v = apic_read(APIC_LVR);
1877 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1878 ver = GET_APIC_VERSION(v);
1879 maxlvt = lapic_get_maxlvt();
1881 v = apic_read(APIC_TASKPRI);
1882 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1884 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1885 if (!APIC_XAPIC(ver)) {
1886 v = apic_read(APIC_ARBPRI);
1887 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1888 v & APIC_ARBPRI_MASK);
1890 v = apic_read(APIC_PROCPRI);
1891 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1895 * Remote read supported only in the 82489DX and local APIC for
1896 * Pentium processors.
1898 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1899 v = apic_read(APIC_RRR);
1900 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1903 v = apic_read(APIC_LDR);
1904 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1905 if (!x2apic_enabled()) {
1906 v = apic_read(APIC_DFR);
1907 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1909 v = apic_read(APIC_SPIV);
1910 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1912 printk(KERN_DEBUG "... APIC ISR field:\n");
1913 print_APIC_field(APIC_ISR);
1914 printk(KERN_DEBUG "... APIC TMR field:\n");
1915 print_APIC_field(APIC_TMR);
1916 printk(KERN_DEBUG "... APIC IRR field:\n");
1917 print_APIC_field(APIC_IRR);
1919 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1920 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1921 apic_write(APIC_ESR, 0);
1923 v = apic_read(APIC_ESR);
1924 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1927 icr = apic_icr_read();
1928 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1929 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1931 v = apic_read(APIC_LVTT);
1932 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1934 if (maxlvt > 3) { /* PC is LVT#4. */
1935 v = apic_read(APIC_LVTPC);
1936 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1938 v = apic_read(APIC_LVT0);
1939 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1940 v = apic_read(APIC_LVT1);
1941 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1943 if (maxlvt > 2) { /* ERR is LVT#3. */
1944 v = apic_read(APIC_LVTERR);
1945 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1948 v = apic_read(APIC_TMICT);
1949 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1950 v = apic_read(APIC_TMCCT);
1951 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1952 v = apic_read(APIC_TDCR);
1953 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1955 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1956 v = apic_read(APIC_EFEAT);
1957 maxlvt = (v >> 16) & 0xff;
1958 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1959 v = apic_read(APIC_ECTRL);
1960 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1961 for (i = 0; i < maxlvt; i++) {
1962 v = apic_read(APIC_EILVTn(i));
1963 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1969 __apicdebuginit(void) print_local_APICs(int maxcpu)
1977 for_each_online_cpu(cpu) {
1980 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1985 __apicdebuginit(void) print_PIC(void)
1988 unsigned long flags;
1990 if (!legacy_pic->nr_legacy_irqs)
1993 printk(KERN_DEBUG "\nprinting PIC contents\n");
1995 raw_spin_lock_irqsave(&i8259A_lock, flags);
1997 v = inb(0xa1) << 8 | inb(0x21);
1998 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
2000 v = inb(0xa0) << 8 | inb(0x20);
2001 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
2005 v = inb(0xa0) << 8 | inb(0x20);
2009 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
2011 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
2013 v = inb(0x4d1) << 8 | inb(0x4d0);
2014 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
2017 static int __initdata show_lapic = 1;
2018 static __init int setup_show_lapic(char *arg)
2022 if (strcmp(arg, "all") == 0) {
2023 show_lapic = CONFIG_NR_CPUS;
2025 get_option(&arg, &num);
2032 __setup("show_lapic=", setup_show_lapic);
2034 __apicdebuginit(int) print_ICs(void)
2036 if (apic_verbosity == APIC_QUIET)
2041 /* don't print out if apic is not there */
2042 if (!cpu_has_apic && !apic_from_smp_config())
2045 print_local_APICs(show_lapic);
2051 late_initcall(print_ICs);
2054 /* Where if anywhere is the i8259 connect in external int mode */
2055 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
2057 void __init enable_IO_APIC(void)
2059 int i8259_apic, i8259_pin;
2062 if (!legacy_pic->nr_legacy_irqs)
2065 for(apic = 0; apic < nr_ioapics; apic++) {
2067 /* See if any of the pins is in ExtINT mode */
2068 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
2069 struct IO_APIC_route_entry entry;
2070 entry = ioapic_read_entry(apic, pin);
2072 /* If the interrupt line is enabled and in ExtInt mode
2073 * I have found the pin where the i8259 is connected.
2075 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2076 ioapic_i8259.apic = apic;
2077 ioapic_i8259.pin = pin;
2083 /* Look to see what if the MP table has reported the ExtINT */
2084 /* If we could not find the appropriate pin by looking at the ioapic
2085 * the i8259 probably is not connected the ioapic but give the
2086 * mptable a chance anyway.
2088 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2089 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2090 /* Trust the MP table if nothing is setup in the hardware */
2091 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2092 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2093 ioapic_i8259.pin = i8259_pin;
2094 ioapic_i8259.apic = i8259_apic;
2096 /* Complain if the MP table and the hardware disagree */
2097 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2098 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2100 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2104 * Do not trust the IO-APIC being empty at bootup
2110 * Not an __init, needed by the reboot code
2112 void disable_IO_APIC(void)
2115 * Clear the IO-APIC before rebooting:
2119 if (!legacy_pic->nr_legacy_irqs)
2123 * If the i8259 is routed through an IOAPIC
2124 * Put that IOAPIC in virtual wire mode
2125 * so legacy interrupts can be delivered.
2127 * With interrupt-remapping, for now we will use virtual wire A mode,
2128 * as virtual wire B is little complex (need to configure both
2129 * IOAPIC RTE as well as interrupt-remapping table entry).
2130 * As this gets called during crash dump, keep this simple for now.
2132 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2133 struct IO_APIC_route_entry entry;
2135 memset(&entry, 0, sizeof(entry));
2136 entry.mask = 0; /* Enabled */
2137 entry.trigger = 0; /* Edge */
2139 entry.polarity = 0; /* High */
2140 entry.delivery_status = 0;
2141 entry.dest_mode = 0; /* Physical */
2142 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2144 entry.dest = read_apic_id();
2147 * Add it to the IO-APIC irq-routing table:
2149 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2153 * Use virtual wire A mode when interrupt remapping is enabled.
2155 if (cpu_has_apic || apic_from_smp_config())
2156 disconnect_bsp_APIC(!intr_remapping_enabled &&
2157 ioapic_i8259.pin != -1);
2160 #ifdef CONFIG_X86_32
2162 * function to set the IO-APIC physical IDs based on the
2163 * values stored in the MPC table.
2165 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2167 void __init setup_ioapic_ids_from_mpc_nocheck(void)
2169 union IO_APIC_reg_00 reg_00;
2170 physid_mask_t phys_id_present_map;
2173 unsigned char old_id;
2174 unsigned long flags;
2177 * This is broken; anything with a real cpu count has to
2178 * circumvent this idiocy regardless.
2180 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2183 * Set the IOAPIC ID to the value stored in the MPC table.
2185 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2186 /* Read the register 0 value */
2187 raw_spin_lock_irqsave(&ioapic_lock, flags);
2188 reg_00.raw = io_apic_read(ioapic_idx, 0);
2189 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2191 old_id = mpc_ioapic_id(ioapic_idx);
2193 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2194 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2195 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2196 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2198 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2202 * Sanity check, is the ID really free? Every APIC in a
2203 * system must have a unique ID or we get lots of nice
2204 * 'stuck on smp_invalidate_needed IPI wait' messages.
2206 if (apic->check_apicid_used(&phys_id_present_map,
2207 mpc_ioapic_id(ioapic_idx))) {
2208 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2209 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2210 for (i = 0; i < get_physical_broadcast(); i++)
2211 if (!physid_isset(i, phys_id_present_map))
2213 if (i >= get_physical_broadcast())
2214 panic("Max APIC ID exceeded!\n");
2215 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2217 physid_set(i, phys_id_present_map);
2218 ioapics[ioapic_idx].mp_config.apicid = i;
2221 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2223 apic_printk(APIC_VERBOSE, "Setting %d in the "
2224 "phys_id_present_map\n",
2225 mpc_ioapic_id(ioapic_idx));
2226 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2230 * We need to adjust the IRQ routing table
2231 * if the ID changed.
2233 if (old_id != mpc_ioapic_id(ioapic_idx))
2234 for (i = 0; i < mp_irq_entries; i++)
2235 if (mp_irqs[i].dstapic == old_id)
2237 = mpc_ioapic_id(ioapic_idx);
2240 * Update the ID register according to the right value
2241 * from the MPC table if they are different.
2243 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2246 apic_printk(APIC_VERBOSE, KERN_INFO
2247 "...changing IO-APIC physical APIC ID to %d ...",
2248 mpc_ioapic_id(ioapic_idx));
2250 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2251 raw_spin_lock_irqsave(&ioapic_lock, flags);
2252 io_apic_write(ioapic_idx, 0, reg_00.raw);
2253 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2258 raw_spin_lock_irqsave(&ioapic_lock, flags);
2259 reg_00.raw = io_apic_read(ioapic_idx, 0);
2260 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2261 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2262 printk("could not set ID!\n");
2264 apic_printk(APIC_VERBOSE, " ok.\n");
2268 void __init setup_ioapic_ids_from_mpc(void)
2274 * Don't check I/O APIC IDs for xAPIC systems. They have
2275 * no meaning without the serial APIC bus.
2277 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2278 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2280 setup_ioapic_ids_from_mpc_nocheck();
2284 int no_timer_check __initdata;
2286 static int __init notimercheck(char *s)
2291 __setup("no_timer_check", notimercheck);
2294 * There is a nasty bug in some older SMP boards, their mptable lies
2295 * about the timer IRQ. We do the following to work around the situation:
2297 * - timer IRQ defaults to IO-APIC IRQ
2298 * - if this function detects that timer IRQs are defunct, then we fall
2299 * back to ISA timer IRQs
2301 static int __init timer_irq_works(void)
2303 unsigned long t1 = jiffies;
2304 unsigned long flags;
2309 local_save_flags(flags);
2311 /* Let ten ticks pass... */
2312 mdelay((10 * 1000) / HZ);
2313 local_irq_restore(flags);
2316 * Expect a few ticks at least, to be sure some possible
2317 * glue logic does not lock up after one or two first
2318 * ticks in a non-ExtINT mode. Also the local APIC
2319 * might have cached one ExtINT interrupt. Finally, at
2320 * least one tick may be lost due to delays.
2324 if (time_after(jiffies, t1 + 4))
2330 * In the SMP+IOAPIC case it might happen that there are an unspecified
2331 * number of pending IRQ events unhandled. These cases are very rare,
2332 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2333 * better to do it this way as thus we do not have to be aware of
2334 * 'pending' interrupts in the IRQ path, except at this point.
2337 * Edge triggered needs to resend any interrupt
2338 * that was delayed but this is now handled in the device
2343 * Starting up a edge-triggered IO-APIC interrupt is
2344 * nasty - we need to make sure that we get the edge.
2345 * If it is already asserted for some reason, we need
2346 * return 1 to indicate that is was pending.
2348 * This is not complete - we should be able to fake
2349 * an edge even if it isn't on the 8259A...
2352 static unsigned int startup_ioapic_irq(struct irq_data *data)
2354 int was_pending = 0, irq = data->irq;
2355 unsigned long flags;
2357 raw_spin_lock_irqsave(&ioapic_lock, flags);
2358 if (irq < legacy_pic->nr_legacy_irqs) {
2359 legacy_pic->mask(irq);
2360 if (legacy_pic->irq_pending(irq))
2363 __unmask_ioapic(data->chip_data);
2364 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2369 static int ioapic_retrigger_irq(struct irq_data *data)
2371 struct irq_cfg *cfg = data->chip_data;
2372 unsigned long flags;
2374 raw_spin_lock_irqsave(&vector_lock, flags);
2375 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2376 raw_spin_unlock_irqrestore(&vector_lock, flags);
2382 * Level and edge triggered IO-APIC interrupts need different handling,
2383 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2384 * handled with the level-triggered descriptor, but that one has slightly
2385 * more overhead. Level-triggered interrupts cannot be handled with the
2386 * edge-triggered handler, without risking IRQ storms and other ugly
2391 void send_cleanup_vector(struct irq_cfg *cfg)
2393 cpumask_var_t cleanup_mask;
2395 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2397 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2398 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2400 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2401 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2402 free_cpumask_var(cleanup_mask);
2404 cfg->move_in_progress = 0;
2407 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2410 struct irq_pin_list *entry;
2411 u8 vector = cfg->vector;
2413 for_each_irq_pin(entry, cfg->irq_2_pin) {
2419 * With interrupt-remapping, destination information comes
2420 * from interrupt-remapping table entry.
2422 if (!irq_remapped(cfg))
2423 io_apic_write(apic, 0x11 + pin*2, dest);
2424 reg = io_apic_read(apic, 0x10 + pin*2);
2425 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2427 io_apic_modify(apic, 0x10 + pin*2, reg);
2432 * Either sets data->affinity to a valid value, and returns
2433 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2434 * leaves data->affinity untouched.
2436 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2437 unsigned int *dest_id)
2439 struct irq_cfg *cfg = data->chip_data;
2441 if (!cpumask_intersects(mask, cpu_online_mask))
2444 if (assign_irq_vector(data->irq, data->chip_data, mask))
2447 cpumask_copy(data->affinity, mask);
2449 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2454 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2457 unsigned int dest, irq = data->irq;
2458 unsigned long flags;
2461 raw_spin_lock_irqsave(&ioapic_lock, flags);
2462 ret = __ioapic_set_affinity(data, mask, &dest);
2464 /* Only the high 8 bits are valid. */
2465 dest = SET_APIC_LOGICAL_ID(dest);
2466 __target_IO_APIC_irq(irq, dest, data->chip_data);
2468 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2472 #ifdef CONFIG_IRQ_REMAP
2475 * Migrate the IO-APIC irq in the presence of intr-remapping.
2477 * For both level and edge triggered, irq migration is a simple atomic
2478 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2480 * For level triggered, we eliminate the io-apic RTE modification (with the
2481 * updated vector information), by using a virtual vector (io-apic pin number).
2482 * Real vector that is used for interrupting cpu will be coming from
2483 * the interrupt-remapping table entry.
2485 * As the migration is a simple atomic update of IRTE, the same mechanism
2486 * is used to migrate MSI irq's in the presence of interrupt-remapping.
2489 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2492 struct irq_cfg *cfg = data->chip_data;
2493 unsigned int dest, irq = data->irq;
2496 if (!cpumask_intersects(mask, cpu_online_mask))
2499 if (get_irte(irq, &irte))
2502 if (assign_irq_vector(irq, cfg, mask))
2505 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2507 irte.vector = cfg->vector;
2508 irte.dest_id = IRTE_DEST(dest);
2511 * Atomically updates the IRTE with the new destination, vector
2512 * and flushes the interrupt entry cache.
2514 modify_irte(irq, &irte);
2517 * After this point, all the interrupts will start arriving
2518 * at the new destination. So, time to cleanup the previous
2519 * vector allocation.
2521 if (cfg->move_in_progress)
2522 send_cleanup_vector(cfg);
2524 cpumask_copy(data->affinity, mask);
2530 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2537 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2539 unsigned vector, me;
2545 me = smp_processor_id();
2546 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2549 struct irq_desc *desc;
2550 struct irq_cfg *cfg;
2551 irq = __this_cpu_read(vector_irq[vector]);
2556 desc = irq_to_desc(irq);
2561 raw_spin_lock(&desc->lock);
2564 * Check if the irq migration is in progress. If so, we
2565 * haven't received the cleanup request yet for this irq.
2567 if (cfg->move_in_progress)
2570 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2573 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2575 * Check if the vector that needs to be cleanedup is
2576 * registered at the cpu's IRR. If so, then this is not
2577 * the best time to clean it up. Lets clean it up in the
2578 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2581 if (irr & (1 << (vector % 32))) {
2582 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2585 __this_cpu_write(vector_irq[vector], -1);
2587 raw_spin_unlock(&desc->lock);
2593 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2597 if (likely(!cfg->move_in_progress))
2600 me = smp_processor_id();
2602 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2603 send_cleanup_vector(cfg);
2606 static void irq_complete_move(struct irq_cfg *cfg)
2608 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2611 void irq_force_complete_move(int irq)
2613 struct irq_cfg *cfg = irq_get_chip_data(irq);
2618 __irq_complete_move(cfg, cfg->vector);
2621 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2624 static void ack_apic_edge(struct irq_data *data)
2626 irq_complete_move(data->chip_data);
2631 atomic_t irq_mis_count;
2633 static void ack_apic_level(struct irq_data *data)
2635 struct irq_cfg *cfg = data->chip_data;
2636 int i, do_unmask_irq = 0, irq = data->irq;
2639 irq_complete_move(cfg);
2640 #ifdef CONFIG_GENERIC_PENDING_IRQ
2641 /* If we are moving the irq we need to mask it */
2642 if (unlikely(irqd_is_setaffinity_pending(data))) {
2649 * It appears there is an erratum which affects at least version 0x11
2650 * of I/O APIC (that's the 82093AA and cores integrated into various
2651 * chipsets). Under certain conditions a level-triggered interrupt is
2652 * erroneously delivered as edge-triggered one but the respective IRR
2653 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2654 * message but it will never arrive and further interrupts are blocked
2655 * from the source. The exact reason is so far unknown, but the
2656 * phenomenon was observed when two consecutive interrupt requests
2657 * from a given source get delivered to the same CPU and the source is
2658 * temporarily disabled in between.
2660 * A workaround is to simulate an EOI message manually. We achieve it
2661 * by setting the trigger mode to edge and then to level when the edge
2662 * trigger mode gets detected in the TMR of a local APIC for a
2663 * level-triggered interrupt. We mask the source for the time of the
2664 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2665 * The idea is from Manfred Spraul. --macro
2667 * Also in the case when cpu goes offline, fixup_irqs() will forward
2668 * any unhandled interrupt on the offlined cpu to the new cpu
2669 * destination that is handling the corresponding interrupt. This
2670 * interrupt forwarding is done via IPI's. Hence, in this case also
2671 * level-triggered io-apic interrupt will be seen as an edge
2672 * interrupt in the IRR. And we can't rely on the cpu's EOI
2673 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2674 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2675 * supporting EOI register, we do an explicit EOI to clear the
2676 * remote IRR and on IO-APIC's which don't have an EOI register,
2677 * we use the above logic (mask+edge followed by unmask+level) from
2678 * Manfred Spraul to clear the remote IRR.
2681 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2684 * We must acknowledge the irq before we move it or the acknowledge will
2685 * not propagate properly.
2690 * Tail end of clearing remote IRR bit (either by delivering the EOI
2691 * message via io-apic EOI register write or simulating it using
2692 * mask+edge followed by unnask+level logic) manually when the
2693 * level triggered interrupt is seen as the edge triggered interrupt
2696 if (!(v & (1 << (i & 0x1f)))) {
2697 atomic_inc(&irq_mis_count);
2699 eoi_ioapic_irq(irq, cfg);
2702 /* Now we can move and renable the irq */
2703 if (unlikely(do_unmask_irq)) {
2704 /* Only migrate the irq if the ack has been received.
2706 * On rare occasions the broadcast level triggered ack gets
2707 * delayed going to ioapics, and if we reprogram the
2708 * vector while Remote IRR is still set the irq will never
2711 * To prevent this scenario we read the Remote IRR bit
2712 * of the ioapic. This has two effects.
2713 * - On any sane system the read of the ioapic will
2714 * flush writes (and acks) going to the ioapic from
2716 * - We get to see if the ACK has actually been delivered.
2718 * Based on failed experiments of reprogramming the
2719 * ioapic entry from outside of irq context starting
2720 * with masking the ioapic entry and then polling until
2721 * Remote IRR was clear before reprogramming the
2722 * ioapic I don't trust the Remote IRR bit to be
2723 * completey accurate.
2725 * However there appears to be no other way to plug
2726 * this race, so if the Remote IRR bit is not
2727 * accurate and is causing problems then it is a hardware bug
2728 * and you can go talk to the chipset vendor about it.
2730 if (!io_apic_level_ack_pending(cfg))
2731 irq_move_masked_irq(data);
2736 #ifdef CONFIG_IRQ_REMAP
2737 static void ir_ack_apic_edge(struct irq_data *data)
2742 static void ir_ack_apic_level(struct irq_data *data)
2745 eoi_ioapic_irq(data->irq, data->chip_data);
2748 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2750 seq_printf(p, " IR-%s", data->chip->name);
2753 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2755 chip->irq_print_chip = ir_print_prefix;
2756 chip->irq_ack = ir_ack_apic_edge;
2757 chip->irq_eoi = ir_ack_apic_level;
2760 chip->irq_set_affinity = ir_ioapic_set_affinity;
2763 #endif /* CONFIG_IRQ_REMAP */
2765 static struct irq_chip ioapic_chip __read_mostly = {
2767 .irq_startup = startup_ioapic_irq,
2768 .irq_mask = mask_ioapic_irq,
2769 .irq_unmask = unmask_ioapic_irq,
2770 .irq_ack = ack_apic_edge,
2771 .irq_eoi = ack_apic_level,
2773 .irq_set_affinity = ioapic_set_affinity,
2775 .irq_retrigger = ioapic_retrigger_irq,
2777 #endif /* !CONFIG_XEN */
2779 static inline void init_IO_APIC_traps(void)
2781 struct irq_cfg *cfg;
2785 * NOTE! The local APIC isn't very good at handling
2786 * multiple interrupts at the same interrupt level.
2787 * As the interrupt level is determined by taking the
2788 * vector number and shifting that right by 4, we
2789 * want to spread these out a bit so that they don't
2790 * all fall in the same interrupt level.
2792 * Also, we've got to be careful not to trash gate
2793 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2795 for_each_active_irq(irq) {
2797 if (irq < PIRQ_BASE || irq >= PIRQ_BASE + nr_pirqs)
2800 cfg = irq_get_chip_data(irq);
2801 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2803 * Hmm.. We don't have an entry for this,
2804 * so default to an old-fashioned 8259
2805 * interrupt if we can..
2807 if (irq < legacy_pic->nr_legacy_irqs)
2808 legacy_pic->make_irq(irq);
2810 /* Strange. Oh, well.. */
2811 irq_set_chip(irq, &no_irq_chip);
2818 * The local APIC irq-chip implementation:
2821 static void mask_lapic_irq(struct irq_data *data)
2825 v = apic_read(APIC_LVT0);
2826 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2829 static void unmask_lapic_irq(struct irq_data *data)
2833 v = apic_read(APIC_LVT0);
2834 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2837 static void ack_lapic_irq(struct irq_data *data)
2842 static struct irq_chip lapic_chip __read_mostly = {
2843 .name = "local-APIC",
2844 .irq_mask = mask_lapic_irq,
2845 .irq_unmask = unmask_lapic_irq,
2846 .irq_ack = ack_lapic_irq,
2849 static void lapic_register_intr(int irq)
2851 irq_clear_status_flags(irq, IRQ_LEVEL);
2852 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2857 * This looks a bit hackish but it's about the only one way of sending
2858 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2859 * not support the ExtINT mode, unfortunately. We need to send these
2860 * cycles as some i82489DX-based boards have glue logic that keeps the
2861 * 8259A interrupt line asserted until INTA. --macro
2863 static inline void __init unlock_ExtINT_logic(void)
2866 struct IO_APIC_route_entry entry0, entry1;
2867 unsigned char save_control, save_freq_select;
2869 pin = find_isa_irq_pin(8, mp_INT);
2874 apic = find_isa_irq_apic(8, mp_INT);
2880 entry0 = ioapic_read_entry(apic, pin);
2881 clear_IO_APIC_pin(apic, pin);
2883 memset(&entry1, 0, sizeof(entry1));
2885 entry1.dest_mode = 0; /* physical delivery */
2886 entry1.mask = 0; /* unmask IRQ now */
2887 entry1.dest = hard_smp_processor_id();
2888 entry1.delivery_mode = dest_ExtINT;
2889 entry1.polarity = entry0.polarity;
2893 ioapic_write_entry(apic, pin, entry1);
2895 save_control = CMOS_READ(RTC_CONTROL);
2896 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2897 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2899 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2904 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2908 CMOS_WRITE(save_control, RTC_CONTROL);
2909 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2910 clear_IO_APIC_pin(apic, pin);
2912 ioapic_write_entry(apic, pin, entry0);
2915 static int disable_timer_pin_1 __initdata;
2916 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2917 static int __init disable_timer_pin_setup(char *arg)
2919 disable_timer_pin_1 = 1;
2922 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2924 int timer_through_8259 __initdata;
2927 * This code may look a bit paranoid, but it's supposed to cooperate with
2928 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2929 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2930 * fanatically on his truly buggy board.
2932 * FIXME: really need to revamp this for all platforms.
2934 static inline void __init check_timer(void)
2936 struct irq_cfg *cfg = irq_get_chip_data(0);
2937 int node = cpu_to_node(0);
2938 int apic1, pin1, apic2, pin2;
2939 unsigned long flags;
2942 local_irq_save(flags);
2945 * get/set the timer IRQ vector:
2947 legacy_pic->mask(0);
2948 assign_irq_vector(0, cfg, apic->target_cpus());
2951 * As IRQ0 is to be enabled in the 8259A, the virtual
2952 * wire has to be disabled in the local APIC. Also
2953 * timer interrupts need to be acknowledged manually in
2954 * the 8259A for the i82489DX when using the NMI
2955 * watchdog as that APIC treats NMIs as level-triggered.
2956 * The AEOI mode will finish them in the 8259A
2959 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2960 legacy_pic->init(1);
2962 pin1 = find_isa_irq_pin(0, mp_INT);
2963 apic1 = find_isa_irq_apic(0, mp_INT);
2964 pin2 = ioapic_i8259.pin;
2965 apic2 = ioapic_i8259.apic;
2967 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2968 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2969 cfg->vector, apic1, pin1, apic2, pin2);
2972 * Some BIOS writers are clueless and report the ExtINTA
2973 * I/O APIC input from the cascaded 8259A as the timer
2974 * interrupt input. So just in case, if only one pin
2975 * was found above, try it both directly and through the
2979 if (intr_remapping_enabled)
2980 panic("BIOS bug: timer not connected to IO-APIC");
2984 } else if (pin2 == -1) {
2991 * Ok, does IRQ0 through the IOAPIC work?
2994 add_pin_to_irq_node(cfg, node, apic1, pin1);
2995 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2997 /* for edge trigger, setup_ioapic_irq already
2998 * leave it unmasked.
2999 * so only need to unmask if it is level-trigger
3000 * do we really have level trigger timer?
3003 idx = find_irq_entry(apic1, pin1, mp_INT);
3004 if (idx != -1 && irq_trigger(idx))
3007 if (timer_irq_works()) {
3008 if (disable_timer_pin_1 > 0)
3009 clear_IO_APIC_pin(0, pin1);
3012 if (intr_remapping_enabled)
3013 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3014 local_irq_disable();
3015 clear_IO_APIC_pin(apic1, pin1);
3017 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3018 "8254 timer not connected to IO-APIC\n");
3020 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3021 "(IRQ0) through the 8259A ...\n");
3022 apic_printk(APIC_QUIET, KERN_INFO
3023 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3025 * legacy devices should be connected to IO APIC #0
3027 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3028 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3029 legacy_pic->unmask(0);
3030 if (timer_irq_works()) {
3031 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3032 timer_through_8259 = 1;
3036 * Cleanup, just in case ...
3038 local_irq_disable();
3039 legacy_pic->mask(0);
3040 clear_IO_APIC_pin(apic2, pin2);
3041 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3044 apic_printk(APIC_QUIET, KERN_INFO
3045 "...trying to set up timer as Virtual Wire IRQ...\n");
3047 lapic_register_intr(0);
3048 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3049 legacy_pic->unmask(0);
3051 if (timer_irq_works()) {
3052 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3055 local_irq_disable();
3056 legacy_pic->mask(0);
3057 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3058 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3060 apic_printk(APIC_QUIET, KERN_INFO
3061 "...trying to set up timer as ExtINT IRQ...\n");
3063 legacy_pic->init(0);
3064 legacy_pic->make_irq(0);
3065 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3067 unlock_ExtINT_logic();
3069 if (timer_irq_works()) {
3070 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3073 local_irq_disable();
3074 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3075 if (x2apic_preenabled)
3076 apic_printk(APIC_QUIET, KERN_INFO
3077 "Perhaps problem with the pre-enabled x2apic mode\n"
3078 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
3079 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3080 "report. Then try booting with the 'noapic' option.\n");
3082 local_irq_restore(flags);
3085 #define check_timer() ((void)0)
3089 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3090 * to devices. However there may be an I/O APIC pin available for
3091 * this interrupt regardless. The pin may be left unconnected, but
3092 * typically it will be reused as an ExtINT cascade interrupt for
3093 * the master 8259A. In the MPS case such a pin will normally be
3094 * reported as an ExtINT interrupt in the MP table. With ACPI
3095 * there is no provision for ExtINT interrupts, and in the absence
3096 * of an override it would be treated as an ordinary ISA I/O APIC
3097 * interrupt, that is edge-triggered and unmasked by default. We
3098 * used to do this, but it caused problems on some systems because
3099 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3100 * the same ExtINT cascade interrupt to drive the local APIC of the
3101 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3102 * the I/O APIC in all cases now. No actual device should request
3103 * it anyway. --macro
3105 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3107 void __init setup_IO_APIC(void)
3111 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3113 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3115 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3117 * Set up IO-APIC IRQ routing.
3120 x86_init.mpparse.setup_ioapic_ids();
3124 setup_IO_APIC_irqs();
3125 init_IO_APIC_traps();
3126 if (legacy_pic->nr_legacy_irqs)
3131 * Called after all the initialization is done. If we didn't find any
3132 * APIC bugs then we can allow the modify fast path
3135 static int __init io_apic_bug_finalize(void)
3137 if (sis_apic_bug == -1)
3139 #ifdef CONFIG_X86_XEN
3140 if (is_initial_xendomain()) {
3141 struct xen_platform_op op = { .cmd = XENPF_platform_quirk };
3142 op.u.platform_quirk.quirk_id = sis_apic_bug ?
3143 QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
3144 VOID(HYPERVISOR_platform_op(&op));
3150 late_initcall(io_apic_bug_finalize);
3153 static void resume_ioapic_id(int ioapic_idx)
3155 unsigned long flags;
3156 union IO_APIC_reg_00 reg_00;
3158 raw_spin_lock_irqsave(&ioapic_lock, flags);
3159 reg_00.raw = io_apic_read(ioapic_idx, 0);
3160 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
3161 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
3162 io_apic_write(ioapic_idx, 0, reg_00.raw);
3164 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3167 static void ioapic_resume(void)
3171 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
3172 resume_ioapic_id(ioapic_idx);
3174 restore_ioapic_entries();
3177 static struct syscore_ops ioapic_syscore_ops = {
3178 .suspend = save_ioapic_entries,
3179 .resume = ioapic_resume,
3182 static int __init ioapic_init_ops(void)
3184 register_syscore_ops(&ioapic_syscore_ops);
3189 device_initcall(ioapic_init_ops);
3192 * Dynamic irq allocate and deallocation
3194 unsigned int create_irq_nr(unsigned int from, int node)
3196 struct irq_cfg *cfg;
3197 unsigned long flags;
3198 unsigned int ret = 0;
3201 if (from < nr_irqs_gsi)
3204 irq = alloc_irq_from(from, node);
3207 cfg = alloc_irq_cfg(irq, node);
3209 free_irq_at(irq, NULL);
3213 raw_spin_lock_irqsave(&vector_lock, flags);
3214 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3216 raw_spin_unlock_irqrestore(&vector_lock, flags);
3219 irq_set_chip_data(irq, cfg);
3220 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3222 free_irq_at(irq, cfg);
3227 int create_irq(void)
3229 int node = cpu_to_node(0);
3230 unsigned int irq_want;
3233 irq_want = nr_irqs_gsi;
3234 irq = create_irq_nr(irq_want, node);
3242 void destroy_irq(unsigned int irq)
3244 struct irq_cfg *cfg = irq_get_chip_data(irq);
3245 unsigned long flags;
3247 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3249 if (irq_remapped(cfg))
3251 raw_spin_lock_irqsave(&vector_lock, flags);
3252 __clear_irq_vector(irq, cfg);
3253 raw_spin_unlock_irqrestore(&vector_lock, flags);
3254 free_irq_at(irq, cfg);
3256 #endif /* !CONFIG_XEN */
3259 * MSI message composition
3261 #if defined(CONFIG_PCI_MSI) && !defined(CONFIG_XEN)
3262 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3263 struct msi_msg *msg, u8 hpet_id)
3265 struct irq_cfg *cfg;
3273 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3277 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3279 if (irq_remapped(cfg)) {
3284 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3285 BUG_ON(ir_index == -1);
3287 prepare_irte(&irte, cfg->vector, dest);
3289 /* Set source-id of interrupt request */
3291 set_msi_sid(&irte, pdev);
3293 set_hpet_sid(&irte, hpet_id);
3295 modify_irte(irq, &irte);
3297 msg->address_hi = MSI_ADDR_BASE_HI;
3298 msg->data = sub_handle;
3299 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3301 MSI_ADDR_IR_INDEX1(ir_index) |
3302 MSI_ADDR_IR_INDEX2(ir_index);
3304 if (x2apic_enabled())
3305 msg->address_hi = MSI_ADDR_BASE_HI |
3306 MSI_ADDR_EXT_DEST_ID(dest);
3308 msg->address_hi = MSI_ADDR_BASE_HI;
3312 ((apic->irq_dest_mode == 0) ?
3313 MSI_ADDR_DEST_MODE_PHYSICAL:
3314 MSI_ADDR_DEST_MODE_LOGICAL) |
3315 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3316 MSI_ADDR_REDIRECTION_CPU:
3317 MSI_ADDR_REDIRECTION_LOWPRI) |
3318 MSI_ADDR_DEST_ID(dest);
3321 MSI_DATA_TRIGGER_EDGE |
3322 MSI_DATA_LEVEL_ASSERT |
3323 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3324 MSI_DATA_DELIVERY_FIXED:
3325 MSI_DATA_DELIVERY_LOWPRI) |
3326 MSI_DATA_VECTOR(cfg->vector);
3333 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3335 struct irq_cfg *cfg = data->chip_data;
3339 if (__ioapic_set_affinity(data, mask, &dest))
3342 __get_cached_msi_msg(data->msi_desc, &msg);
3344 msg.data &= ~MSI_DATA_VECTOR_MASK;
3345 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3346 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3347 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3349 __write_msi_msg(data->msi_desc, &msg);
3353 #endif /* CONFIG_SMP */
3356 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3357 * which implement the MSI or MSI-X Capability Structure.
3359 static struct irq_chip msi_chip = {
3361 .irq_unmask = unmask_msi_irq,
3362 .irq_mask = mask_msi_irq,
3363 .irq_ack = ack_apic_edge,
3365 .irq_set_affinity = msi_set_affinity,
3367 .irq_retrigger = ioapic_retrigger_irq,
3371 * Map the PCI dev to the corresponding remapping hardware unit
3372 * and allocate 'nvec' consecutive interrupt-remapping table entries
3375 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3377 struct intel_iommu *iommu;
3380 iommu = map_dev_to_ir(dev);
3383 "Unable to map PCI %s to iommu\n", pci_name(dev));
3387 index = alloc_irte(iommu, irq, nvec);
3390 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3397 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3399 struct irq_chip *chip = &msi_chip;
3403 ret = msi_compose_msg(dev, irq, &msg, -1);
3407 irq_set_msi_desc(irq, msidesc);
3408 write_msi_msg(irq, &msg);
3410 if (irq_remapped(irq_get_chip_data(irq))) {
3411 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3412 irq_remap_modify_chip_defaults(chip);
3415 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3417 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3422 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3424 int node, ret, sub_handle, index = 0;
3425 unsigned int irq, irq_want;
3426 struct msi_desc *msidesc;
3427 struct intel_iommu *iommu = NULL;
3429 /* x86 doesn't support multiple MSI yet */
3430 if (type == PCI_CAP_ID_MSI && nvec > 1)
3433 node = dev_to_node(&dev->dev);
3434 irq_want = nr_irqs_gsi;
3436 list_for_each_entry(msidesc, &dev->msi_list, list) {
3437 irq = create_irq_nr(irq_want, node);
3441 if (!intr_remapping_enabled)
3446 * allocate the consecutive block of IRTE's
3449 index = msi_alloc_irte(dev, irq, nvec);
3455 iommu = map_dev_to_ir(dev);
3461 * setup the mapping between the irq and the IRTE
3462 * base index, the sub_handle pointing to the
3463 * appropriate interrupt remap table entry.
3465 set_irte_irq(irq, iommu, index, sub_handle);
3468 ret = setup_msi_irq(dev, msidesc, irq);
3480 void native_teardown_msi_irq(unsigned int irq)
3485 #ifdef CONFIG_DMAR_TABLE
3488 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3491 struct irq_cfg *cfg = data->chip_data;
3492 unsigned int dest, irq = data->irq;
3495 if (__ioapic_set_affinity(data, mask, &dest))
3498 dmar_msi_read(irq, &msg);
3500 msg.data &= ~MSI_DATA_VECTOR_MASK;
3501 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3502 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3503 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3504 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3506 dmar_msi_write(irq, &msg);
3511 #endif /* CONFIG_SMP */
3513 static struct irq_chip dmar_msi_type = {
3515 .irq_unmask = dmar_msi_unmask,
3516 .irq_mask = dmar_msi_mask,
3517 .irq_ack = ack_apic_edge,
3519 .irq_set_affinity = dmar_msi_set_affinity,
3521 .irq_retrigger = ioapic_retrigger_irq,
3524 int arch_setup_dmar_msi(unsigned int irq)
3529 ret = msi_compose_msg(NULL, irq, &msg, -1);
3532 dmar_msi_write(irq, &msg);
3533 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3539 #ifdef CONFIG_HPET_TIMER
3542 static int hpet_msi_set_affinity(struct irq_data *data,
3543 const struct cpumask *mask, bool force)
3545 struct irq_cfg *cfg = data->chip_data;
3549 if (__ioapic_set_affinity(data, mask, &dest))
3552 hpet_msi_read(data->handler_data, &msg);
3554 msg.data &= ~MSI_DATA_VECTOR_MASK;
3555 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3556 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3557 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3559 hpet_msi_write(data->handler_data, &msg);
3564 #endif /* CONFIG_SMP */
3566 static struct irq_chip hpet_msi_type = {
3568 .irq_unmask = hpet_msi_unmask,
3569 .irq_mask = hpet_msi_mask,
3570 .irq_ack = ack_apic_edge,
3572 .irq_set_affinity = hpet_msi_set_affinity,
3574 .irq_retrigger = ioapic_retrigger_irq,
3577 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3579 struct irq_chip *chip = &hpet_msi_type;
3583 if (intr_remapping_enabled) {
3584 struct intel_iommu *iommu = map_hpet_to_ir(id);
3590 index = alloc_irte(iommu, irq, 1);
3595 ret = msi_compose_msg(NULL, irq, &msg, id);
3599 hpet_msi_write(irq_get_handler_data(irq), &msg);
3600 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3601 if (irq_remapped(irq_get_chip_data(irq)))
3602 irq_remap_modify_chip_defaults(chip);
3604 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3609 #endif /* CONFIG_PCI_MSI */
3611 * Hypertransport interrupt support
3613 #ifdef CONFIG_HT_IRQ
3617 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3619 struct ht_irq_msg msg;
3620 fetch_ht_irq_msg(irq, &msg);
3622 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3623 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3625 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3626 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3628 write_ht_irq_msg(irq, &msg);
3632 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3634 struct irq_cfg *cfg = data->chip_data;
3637 if (__ioapic_set_affinity(data, mask, &dest))
3640 target_ht_irq(data->irq, dest, cfg->vector);
3646 static struct irq_chip ht_irq_chip = {
3648 .irq_mask = mask_ht_irq,
3649 .irq_unmask = unmask_ht_irq,
3650 .irq_ack = ack_apic_edge,
3652 .irq_set_affinity = ht_set_affinity,
3654 .irq_retrigger = ioapic_retrigger_irq,
3657 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3659 struct irq_cfg *cfg;
3666 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3668 struct ht_irq_msg msg;
3671 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3672 apic->target_cpus());
3674 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3678 HT_IRQ_LOW_DEST_ID(dest) |
3679 HT_IRQ_LOW_VECTOR(cfg->vector) |
3680 ((apic->irq_dest_mode == 0) ?
3681 HT_IRQ_LOW_DM_PHYSICAL :
3682 HT_IRQ_LOW_DM_LOGICAL) |
3683 HT_IRQ_LOW_RQEOI_EDGE |
3684 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3685 HT_IRQ_LOW_MT_FIXED :
3686 HT_IRQ_LOW_MT_ARBITRATED) |
3687 HT_IRQ_LOW_IRQ_MASKED;
3689 write_ht_irq_msg(irq, &msg);
3691 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3692 handle_edge_irq, "edge");
3694 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3698 #endif /* CONFIG_HT_IRQ */
3701 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3703 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3708 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3710 setup_ioapic_irq(irq, cfg, attr);
3714 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3715 struct io_apic_irq_attr *attr)
3717 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3720 /* Avoid redundant programming */
3721 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3722 pr_debug("Pin %d-%d already programmed\n",
3723 mpc_ioapic_id(ioapic_idx), pin);
3726 ret = io_apic_setup_irq_pin(irq, node, attr);
3728 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3732 static int __init io_apic_get_redir_entries(int ioapic)
3734 union IO_APIC_reg_01 reg_01;
3735 unsigned long flags;
3737 raw_spin_lock_irqsave(&ioapic_lock, flags);
3738 reg_01.raw = io_apic_read(ioapic, 1);
3739 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3741 /* The register returns the maximum index redir index
3742 * supported, which is one less than the total number of redir
3745 return reg_01.bits.entries + 1;
3749 static void __init probe_nr_irqs_gsi(void)
3753 nr = gsi_top + NR_IRQS_LEGACY;
3754 if (nr > nr_irqs_gsi)
3757 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3760 int get_nr_irqs_gsi(void)
3765 int __init arch_probe_nr_irqs(void)
3769 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3770 nr_irqs = NR_VECTORS * nr_cpu_ids;
3772 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3773 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3775 * for MSI and HT dyn irq
3777 nr += nr_irqs_gsi * 16;
3782 return NR_IRQS_LEGACY;
3784 #endif /* CONFIG_XEN */
3786 int io_apic_set_pci_routing(struct device *dev, int irq,
3787 struct io_apic_irq_attr *irq_attr)
3792 if (irq < PIRQ_BASE || irq >= PIRQ_BASE + nr_pirqs) {
3793 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ %d\n",
3794 irq_attr->ioapic, irq);
3798 if (!IO_APIC_IRQ(irq)) {
3799 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3804 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3806 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3809 #ifdef CONFIG_X86_32
3811 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3813 union IO_APIC_reg_00 reg_00;
3814 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3816 unsigned long flags;
3820 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3821 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3822 * supports up to 16 on one shared APIC bus.
3824 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3825 * advantage of new APIC bus architecture.
3828 if (physids_empty(apic_id_map))
3829 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3831 raw_spin_lock_irqsave(&ioapic_lock, flags);
3832 reg_00.raw = io_apic_read(ioapic, 0);
3833 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3835 if (apic_id >= get_physical_broadcast()) {
3836 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3837 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3838 apic_id = reg_00.bits.ID;
3842 * Every APIC in a system must have a unique ID or we get lots of nice
3843 * 'stuck on smp_invalidate_needed IPI wait' messages.
3845 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3847 for (i = 0; i < get_physical_broadcast(); i++) {
3848 if (!apic->check_apicid_used(&apic_id_map, i))
3852 if (i == get_physical_broadcast())
3853 panic("Max apic_id exceeded!\n");
3855 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3856 "trying %d\n", ioapic, apic_id, i);
3861 apic->apicid_to_cpu_present(apic_id, &tmp);
3862 physids_or(apic_id_map, apic_id_map, tmp);
3864 if (reg_00.bits.ID != apic_id) {
3865 reg_00.bits.ID = apic_id;
3867 raw_spin_lock_irqsave(&ioapic_lock, flags);
3868 io_apic_write(ioapic, 0, reg_00.raw);
3869 reg_00.raw = io_apic_read(ioapic, 0);
3870 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3873 if (reg_00.bits.ID != apic_id) {
3874 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3879 apic_printk(APIC_VERBOSE, KERN_INFO
3880 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3886 static u8 __init io_apic_unique_id(u8 id)
3889 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3890 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3891 return io_apic_get_unique_id(nr_ioapics, id);
3897 static u8 __init io_apic_unique_id(u8 id)
3900 DECLARE_BITMAP(used, 256);
3902 bitmap_zero(used, 256);
3903 for (i = 0; i < nr_ioapics; i++) {
3904 __set_bit(mpc_ioapic_id(i), used);
3906 if (!test_bit(id, used))
3908 return find_first_zero_bit(used, 256);
3912 static int __init io_apic_get_version(int ioapic)
3914 union IO_APIC_reg_01 reg_01;
3915 unsigned long flags;
3917 raw_spin_lock_irqsave(&ioapic_lock, flags);
3918 reg_01.raw = io_apic_read(ioapic, 1);
3919 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3921 return reg_01.bits.version;
3924 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3926 int ioapic, pin, idx;
3928 if (skip_ioapic_setup)
3931 ioapic = mp_find_ioapic(gsi);
3935 pin = mp_find_ioapic_pin(ioapic, gsi);
3939 idx = find_irq_entry(ioapic, pin, mp_INT);
3943 *trigger = irq_trigger(idx);
3944 *polarity = irq_polarity(idx);
3950 * This function currently is only a helper for the i386 smp boot process where
3951 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3952 * so mask in all cases should simply be apic->target_cpus()
3955 void __init setup_ioapic_dest(void)
3957 int pin, ioapic, irq, irq_entry;
3958 const struct cpumask *mask;
3959 struct irq_data *idata;
3961 if (skip_ioapic_setup == 1)
3964 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3965 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3966 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3967 if (irq_entry == -1)
3969 irq = pin_2_irq(irq_entry, ioapic, pin);
3971 if ((ioapic > 0) && (irq > 16))
3974 idata = irq_get_irq_data(irq);
3977 * Honour affinities which have been set in early boot
3979 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3980 mask = idata->affinity;
3982 mask = apic->target_cpus();
3984 if (intr_remapping_enabled)
3985 ir_ioapic_set_affinity(idata, mask, false);
3987 ioapic_set_affinity(idata, mask, false);
3993 #define IOAPIC_RESOURCE_NAME_SIZE 11
3995 static struct resource *ioapic_resources;
3997 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4000 struct resource *res;
4004 if (nr_ioapics <= 0)
4007 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4010 mem = alloc_bootmem(n);
4013 mem += sizeof(struct resource) * nr_ioapics;
4015 for (i = 0; i < nr_ioapics; i++) {
4017 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4018 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4019 mem += IOAPIC_RESOURCE_NAME_SIZE;
4022 ioapic_resources = res;
4027 void __init ioapic_and_gsi_init(void)
4029 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4030 struct resource *ioapic_res;
4033 ioapic_res = ioapic_setup_resources(nr_ioapics);
4034 for (i = 0; i < nr_ioapics; i++) {
4035 if (smp_found_config) {
4036 ioapic_phys = mpc_ioapic_addr(i);
4037 #ifdef CONFIG_X86_32
4040 "WARNING: bogus zero IO-APIC "
4041 "address found in MPTABLE, "
4042 "disabling IO/APIC support!\n");
4043 smp_found_config = 0;
4044 skip_ioapic_setup = 1;
4045 goto fake_ioapic_page;
4049 #ifdef CONFIG_X86_32
4052 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4053 ioapic_phys = __pa(ioapic_phys);
4055 set_fixmap_nocache(idx, ioapic_phys);
4056 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4057 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4061 ioapic_res->start = ioapic_phys;
4062 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4066 probe_nr_irqs_gsi();
4069 void __init ioapic_insert_resources(void)
4072 struct resource *r = ioapic_resources;
4077 "IO APIC resources couldn't be allocated.\n");
4081 for (i = 0; i < nr_ioapics; i++) {
4082 insert_resource(&iomem_resource, r);
4086 #endif /* !CONFIG_XEN */
4088 int mp_find_ioapic(u32 gsi)
4092 if (nr_ioapics == 0)
4095 /* Find the IOAPIC that manages this GSI. */
4096 for (i = 0; i < nr_ioapics; i++) {
4097 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
4098 if ((gsi >= gsi_cfg->gsi_base)
4099 && (gsi <= gsi_cfg->gsi_end))
4103 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4107 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4109 struct mp_ioapic_gsi *gsi_cfg;
4111 if (WARN_ON(ioapic == -1))
4114 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
4115 if (WARN_ON(gsi > gsi_cfg->gsi_end))
4118 return gsi - gsi_cfg->gsi_base;
4121 static __init int bad_ioapic(unsigned long address)
4123 if (nr_ioapics >= MAX_IO_APICS) {
4124 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
4125 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4129 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4130 " found in table, skipping!\n");
4136 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4140 struct mp_ioapic_gsi *gsi_cfg;
4142 if (bad_ioapic(address))
4147 ioapics[idx].mp_config.type = MP_IOAPIC;
4148 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
4149 ioapics[idx].mp_config.apicaddr = address;
4152 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4154 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
4155 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
4158 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4159 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4161 entries = io_apic_get_redir_entries(idx);
4162 gsi_cfg = mp_ioapic_gsi_routing(idx);
4163 gsi_cfg->gsi_base = gsi_base;
4164 gsi_cfg->gsi_end = gsi_base + entries - 1;
4167 * The number of IO-APIC IRQ registers (== #pins):
4169 ioapics[idx].nr_registers = entries;
4171 if (gsi_cfg->gsi_end >= gsi_top)
4172 gsi_top = gsi_cfg->gsi_end + 1;
4174 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4175 "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
4176 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4177 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4182 #ifdef CONFIG_X86_MRST
4183 /* Enable IOAPIC early just for system timer */
4184 void __init pre_init_apic_IRQ0(void)
4186 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4188 printk(KERN_INFO "Early APIC setup for system timer0\n");
4190 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4191 &phys_cpu_present_map);
4195 io_apic_setup_irq_pin(0, 0, &attr);
4196 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,