1 #ifndef _ASM_X86_SPINLOCK_H
2 #define _ASM_X86_SPINLOCK_H
4 #include <linux/atomic.h>
6 #include <asm/processor.h>
7 #include <linux/compiler.h>
10 * Your basic SMP spinlocks, allowing only a single CPU anywhere
12 * Simple spin lock operations. There are two variants, one clears IRQ's
13 * on the local processor, one does not.
15 * These are fair FIFO ticket locks, which are currently limited to 256
18 * (the type definitions are in asm/spinlock_types.h)
22 # define LOCK_PTR_REG "a"
23 # define REG_PTR_MODE "k"
25 # define LOCK_PTR_REG "D"
26 # define REG_PTR_MODE "q"
29 #if defined(CONFIG_XEN) || (defined(CONFIG_X86_32) && \
30 (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)))
32 * On Xen, as we read back the result of the unlocking increment, we must use
33 * a locked access (or insert a full memory barrier) in all cases (so that we
34 * read what is globally visible).
36 * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
37 * (PPro errata 66, 92)
39 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
41 # define UNLOCK_LOCK_PREFIX
46 #include <asm/irqflags.h>
47 #include <asm/smp-processor-id.h>
49 int xen_spinlock_init(unsigned int cpu);
50 void xen_spinlock_cleanup(unsigned int cpu);
51 #if CONFIG_XEN_SPINLOCK_ACQUIRE_NESTING
52 struct __raw_tickets xen_spin_adjust(const arch_spinlock_t *,
53 struct __raw_tickets);
55 #define xen_spin_adjust(lock, raw_tickets) (raw_tickets)
56 #define xen_spin_wait(l, t, f) xen_spin_wait(l, t)
58 unsigned int xen_spin_wait(arch_spinlock_t *, struct __raw_tickets *,
60 void xen_spin_kick(const arch_spinlock_t *, unsigned int ticket);
63 * Ticket locks are conceptually two parts, one indicating the current head of
64 * the queue, and the other indicating the current tail. The lock is acquired
65 * by atomically noting the tail and incrementing it by one (thus adding
66 * ourself to the queue and noting our position), then waiting until the head
67 * becomes equal to the the initial value of the tail.
69 * We use an xadd covering *both* parts of the lock, to increment the tail and
70 * also load the position of the head, which takes care of memory ordering
71 * issues and should be optimal for the uncontended case. Note the tail must be
72 * in the high part, because a wide xadd increment of the low part would carry
73 * up and contaminate the high part.
75 #define __spin_count_dec(c, l) (vcpu_running((l)->owner) ? --(c) : ((c) >>= 1))
77 #if CONFIG_XEN_SPINLOCK_ACQUIRE_NESTING
78 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
80 struct __raw_tickets inc = { .tail = 1 };
81 unsigned int count, flags = arch_local_irq_save();
83 inc = xadd(&lock->tickets, inc);
84 if (likely(inc.head == inc.tail))
85 arch_local_irq_restore(flags);
87 inc = xen_spin_adjust(lock, inc);
88 arch_local_irq_restore(flags);
91 while (inc.head != inc.tail
92 && __spin_count_dec(count, lock)) {
94 inc.head = ACCESS_ONCE(lock->tickets.head);
96 } while (unlikely(!count)
97 && (count = xen_spin_wait(lock, &inc, flags)));
99 barrier(); /* make sure nothing creeps before the lock is taken */
100 lock->owner = raw_smp_processor_id();
103 #define __ticket_spin_lock(lock) __ticket_spin_lock_flags(lock, -1)
106 static __always_inline void __ticket_spin_lock_flags(arch_spinlock_t *lock,
109 struct __raw_tickets inc = { .tail = 1 };
111 inc = xadd(&lock->tickets, inc);
112 if (unlikely(inc.head != inc.tail)) {
113 unsigned int count = 1 << 12;
115 inc = xen_spin_adjust(lock, inc);
117 while (inc.head != inc.tail
118 && __spin_count_dec(count, lock)) {
120 inc.head = ACCESS_ONCE(lock->tickets.head);
122 } while (unlikely(!count)
123 && (count = xen_spin_wait(lock, &inc, flags)));
125 barrier(); /* make sure nothing creeps before the lock is taken */
126 lock->owner = raw_smp_processor_id();
129 #undef __spin_count_dec
131 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
135 old.tickets = ACCESS_ONCE(lock->tickets);
136 if (old.tickets.head != old.tickets.tail)
139 /* cmpxchg is a full barrier, so nothing can move before it */
140 if (cmpxchg(&lock->head_tail, old.head_tail,
141 old.head_tail + (1 << TICKET_SHIFT)) != old.head_tail)
143 lock->owner = raw_smp_processor_id();
147 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
149 register struct __raw_tickets new;
151 __add(&lock->tickets.head, 1, UNLOCK_LOCK_PREFIX);
152 #if !defined(XEN_SPINLOCK_SOURCE) || !CONFIG_XEN_SPINLOCK_ACQUIRE_NESTING
153 # undef UNLOCK_LOCK_PREFIX
155 new = ACCESS_ONCE(lock->tickets);
156 if (new.head != new.tail)
157 xen_spin_kick(lock, new.head);
160 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
162 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
164 return tmp.tail != tmp.head;
167 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
169 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
171 return (__ticket_t)(tmp.tail - tmp.head) > 1;
174 #define __arch_spin(n) __ticket_spin_##n
176 #else /* TICKET_SHIFT */
178 static inline int xen_spinlock_init(unsigned int cpu) { return 0; }
179 static inline void xen_spinlock_cleanup(unsigned int cpu) {}
181 static inline int __byte_spin_is_locked(arch_spinlock_t *lock)
183 return lock->lock != 0;
186 static inline int __byte_spin_is_contended(arch_spinlock_t *lock)
188 return lock->spinners != 0;
191 static inline void __byte_spin_lock(arch_spinlock_t *lock)
195 asm("1: xchgb %1, %0\n"
198 " " LOCK_PREFIX "incb %2\n"
202 " " LOCK_PREFIX "decb %2\n"
205 : "+m" (lock->lock), "+q" (val), "+m" (lock->spinners): : "memory");
208 #define __byte_spin_lock_flags(lock, flags) __byte_spin_lock(lock)
210 static inline int __byte_spin_trylock(arch_spinlock_t *lock)
215 : "+m" (lock->lock), "+q" (old) : : "memory");
220 static inline void __byte_spin_unlock(arch_spinlock_t *lock)
226 #define __arch_spin(n) __byte_spin_##n
228 #endif /* TICKET_SHIFT */
230 #if defined(CONFIG_XEN_SPINLOCK_ACQUIRE_NESTING) \
231 && CONFIG_XEN_SPINLOCK_ACQUIRE_NESTING
232 void xen_spin_irq_enter(void);
233 void xen_spin_irq_exit(void);
235 static inline void xen_spin_irq_enter(void) {}
236 static inline void xen_spin_irq_exit(void) {}
239 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
241 return __arch_spin(is_locked)(lock);
244 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
246 return __arch_spin(is_contended)(lock);
248 #define arch_spin_is_contended arch_spin_is_contended
250 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
252 __arch_spin(lock)(lock);
255 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
257 return __arch_spin(trylock)(lock);
260 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
262 __arch_spin(unlock)(lock);
265 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
268 __arch_spin(lock_flags)(lock, flags);
273 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
275 while (arch_spin_is_locked(lock))
280 * Read-write spinlocks, allowing multiple readers
281 * but only one writer.
283 * NOTE! it is quite common to have readers in interrupts
284 * but no interrupt writers. For those circumstances we
285 * can "mix" irq-safe locks - any writer needs to get a
286 * irq-safe write-lock, but readers can get non-irqsafe
289 * On x86, we implement read-write locks as a 32-bit counter
290 * with the high bit (sign) being the "contended" bit.
294 * read_can_lock - would read_trylock() succeed?
295 * @lock: the rwlock in question.
297 static inline int arch_read_can_lock(arch_rwlock_t *lock)
299 return lock->lock > 0;
303 * write_can_lock - would write_trylock() succeed?
304 * @lock: the rwlock in question.
306 static inline int arch_write_can_lock(arch_rwlock_t *lock)
308 return lock->write == WRITE_LOCK_CMP;
311 static inline void arch_read_lock(arch_rwlock_t *rw)
313 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
315 "call __read_lock_failed\n\t"
317 ::LOCK_PTR_REG (rw) : "memory");
320 static inline void arch_write_lock(arch_rwlock_t *rw)
322 asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
324 "call __write_lock_failed\n\t"
326 ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
330 static inline int arch_read_trylock(arch_rwlock_t *lock)
332 READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
334 if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
336 READ_LOCK_ATOMIC(inc)(count);
340 static inline int arch_write_trylock(arch_rwlock_t *lock)
342 atomic_t *count = (atomic_t *)&lock->write;
344 if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
346 atomic_add(WRITE_LOCK_CMP, count);
350 static inline void arch_read_unlock(arch_rwlock_t *rw)
352 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
353 :"+m" (rw->lock) : : "memory");
356 static inline void arch_write_unlock(arch_rwlock_t *rw)
358 asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
359 : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
362 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
363 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
365 #undef READ_LOCK_SIZE
366 #undef READ_LOCK_ATOMIC
367 #undef WRITE_LOCK_ADD
368 #undef WRITE_LOCK_SUB
369 #undef WRITE_LOCK_CMP
371 #define arch_spin_relax(lock) cpu_relax()
372 #define arch_read_relax(lock) cpu_relax()
373 #define arch_write_relax(lock) cpu_relax()
375 /* The {read|write|spin}_lock() on x86 are full memory barriers. */
376 static inline void smp_mb__after_lock(void) { }
377 #define ARCH_HAS_SMP_MB_AFTER_LOCK
379 #endif /* _ASM_X86_SPINLOCK_H */