1 /* $Id: sni.h,v 1.2 1998/09/19 19:19:39 ralf Exp $
3 * SNI specific definitions
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * Copyright (C) 1997, 1998 by Ralf Baechle
11 #ifndef __ASM_MIPS_SNI_H
12 #define __ASM_MIPS_SNI_H
14 #define SNI_PORT_BASE 0xb4000000
17 * ASIC PCI registers for little endian configuration.
20 #error "Fix me for big endian"
22 #define PCIMT_UCONF 0xbfff0000
23 #define PCIMT_IOADTIMEOUT2 0xbfff0008
24 #define PCIMT_IOMEMCONF 0xbfff0010
25 #define PCIMT_IOMMU 0xbfff0018
26 #define PCIMT_IOADTIMEOUT1 0xbfff0020
27 #define PCIMT_DMAACCESS 0xbfff0028
28 #define PCIMT_DMAHIT 0xbfff0030
29 #define PCIMT_ERRSTATUS 0xbfff0038
30 #define PCIMT_ERRADDR 0xbfff0040
31 #define PCIMT_SYNDROME 0xbfff0048
32 #define PCIMT_ITPEND 0xbfff0050
41 #define PCIMT_IRQSEL 0xbfff0058
42 #define PCIMT_TESTMEM 0xbfff0060
43 #define PCIMT_ECCREG 0xbfff0068
44 #define PCIMT_CONFIG_ADDRESS 0xbfff0070
45 #define PCIMT_ASIC_ID 0xbfff0078 /* read */
46 #define PCIMT_SOFT_RESET 0xbfff0078 /* write */
47 #define PCIMT_PIA_OE 0xbfff0080
48 #define PCIMT_PIA_DATAOUT 0xbfff0088
49 #define PCIMT_PIA_DATAIN 0xbfff0090
50 #define PCIMT_CACHECONF 0xbfff0098
51 #define PCIMT_INVSPACE 0xbfff00a0
52 #define PCIMT_PCI_CONF 0xbfff0100
55 * Data port for the PCI bus.
57 #define PCIMT_CONFIG_DATA 0xb4000cfc
60 * Board specific registers
62 #define PCIMT_CSMSR 0xbfd00000
63 #define PCIMT_CSSWITCH 0xbfd10000
64 #define PCIMT_CSITPEND 0xbfd20000
65 #define PCIMT_AUTO_PO_EN 0xbfd30000
66 #define PCIMT_CLR_TEMP 0xbfd40000
67 #define PCIMT_AUTO_PO_DIS 0xbfd50000
68 #define PCIMT_EXMSR 0xbfd60000
69 #define PCIMT_UNUSED1 0xbfd70000
70 #define PCIMT_CSWCSM 0xbfd80000
71 #define PCIMT_UNUSED2 0xbfd90000
72 #define PCIMT_CSLED 0xbfda0000
73 #define PCIMT_CSMAPISA 0xbfdb0000
74 #define PCIMT_CSRSTBP 0xbfdc0000
75 #define PCIMT_CLRPOFF 0xbfdd0000
76 #define PCIMT_CSTIMER 0xbfde0000
77 #define PCIMT_PWDN 0xbfdf0000
80 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
81 * to the other interrupts generated by ASIC PCI.
83 #define PCIMT_KEYBOARD_IRQ 1
84 #define PCIMT_IRQ_INT2 16 /* What is that? */
85 #define PCIMT_IRQ_INTD 17
86 #define PCIMT_IRQ_INTC 18
87 #define PCIMT_IRQ_INTB 19
88 #define PCIMT_IRQ_INTA 20
89 #define PCIMT_IRQ_EISA 21
90 #define PCIMT_IRQ_SCSI 22
91 #define PCIMT_IRQ_ETHERNET 23
92 #define PCIMT_IRQ_TEMPERATURE 24
93 #define PCIMT_IRQ_EISA_NMI 25
94 #define PCIMT_IRQ_POWER_OFF 26
95 #define PCIMT_IRQ_BUTTON 27
98 * Base address for the mapped 16mb EISA bus segment.
100 #define PCIMT_EISA_BASE 0xb0000000
102 /* PCI EISA Interrupt acknowledge */
103 #define PCIMT_INT_ACKNOWLEDGE 0xba000000
105 #endif /* __ASM_MIPS_SNI_H */