4 #include <asm/pgtable.h>
5 #include <asm/cacheflush.h>
6 #include <asm/system.h>
9 * Functions to keep the agpgart mappings coherent with the MMU. The
10 * GART gives the CPU a physical alias of pages in memory. The alias
11 * region is mapped uncacheable. Make sure there are no conflicting
12 * mappings with different cachability attributes for the same
13 * page. This avoids data corruption on some CPUs.
17 * Caller's responsibility to call global_flush_tlb() for performance
20 #define map_page_into_agp(page) ( \
21 xen_create_contiguous_region((unsigned long)page_address(page), 0, 32) \
22 ?: change_page_attr(page, 1, PAGE_KERNEL_NOCACHE))
23 #define unmap_page_from_agp(page) ( \
24 xen_destroy_contiguous_region((unsigned long)page_address(page), 0), \
25 /* only a fallback: xen_destroy_contiguous_region uses PAGE_KERNEL */ \
26 change_page_attr(page, 1, PAGE_KERNEL))
27 #define flush_agp_mappings() global_flush_tlb()
30 * Could use CLFLUSH here if the cpu supports it. But then it would
31 * need to be called for each cacheline of the whole page so it may
32 * not be worth it. Would need a page for it.
34 #define flush_agp_cache() wbinvd()
36 /* Convert a physical address to an address suitable for the GART. */
37 #define phys_to_gart(x) phys_to_machine(x)
38 #define gart_to_phys(x) machine_to_phys(x)
40 /* GATT allocation. Returns/accepts GATT kernel virtual address. */
41 #define alloc_gatt_pages(order) ({ \
42 char *_t; dma_addr_t _d; \
43 _t = dma_alloc_coherent(NULL,PAGE_SIZE<<(order),&_d,GFP_KERNEL); \
45 #define free_gatt_pages(table, order) \
46 dma_free_coherent(NULL,PAGE_SIZE<<(order),(table),virt_to_bus(table))