include/asm-x86/apicdef_64.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 #ifndef CONFIG_XEN
   5
   6 /*
   7  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   8  *
   9  * Alan Cox <Alan.Cox@linux.org>, 1995.
  10  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
  11  */
  12
  13 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  14
  15 #define         APIC_ID         0x20
  16 #define                 APIC_ID_MASK            (0xFFu<<24)
  17 #define                 GET_APIC_ID(x)          (((x)>>24)&0xFFu)
  18 #define                 SET_APIC_ID(x)          (((x)<<24))
  19 #define         APIC_LVR        0x30
  20 #define                 APIC_LVR_MASK           0xFF00FF
  21 #define                 GET_APIC_VERSION(x)     ((x)&0xFFu)
  22 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFFu)
  23 #define                 APIC_INTEGRATED(x)      ((x)&0xF0u)
  24 #define         APIC_TASKPRI    0x80
  25 #define                 APIC_TPRI_MASK          0xFFu
  26 #define         APIC_ARBPRI     0x90
  27 #define                 APIC_ARBPRI_MASK        0xFFu
  28 #define         APIC_PROCPRI    0xA0
  29 #define         APIC_EOI        0xB0
  30 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  31 #define         APIC_RRR        0xC0
  32 #define         APIC_LDR        0xD0
  33 #define                 APIC_LDR_MASK           (0xFFu<<24)
  34 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFFu)
  35 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  36 #define                 APIC_ALL_CPUS           0xFFu
  37 #define         APIC_DFR        0xE0
  38 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  39 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  40 #define         APIC_SPIV       0xF0
  41 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  42 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  43 #define         APIC_ISR        0x100
  44 #define         APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
  45 #define         APIC_TMR        0x180
  46 #define         APIC_IRR        0x200
  47 #define         APIC_ESR        0x280
  48 #define                 APIC_ESR_SEND_CS        0x00001
  49 #define                 APIC_ESR_RECV_CS        0x00002
  50 #define                 APIC_ESR_SEND_ACC       0x00004
  51 #define                 APIC_ESR_RECV_ACC       0x00008
  52 #define                 APIC_ESR_SENDILL        0x00020
  53 #define                 APIC_ESR_RECVILL        0x00040
  54 #define                 APIC_ESR_ILLREGA        0x00080
  55 #define         APIC_ICR        0x300
  56 #define                 APIC_DEST_SELF          0x40000
  57 #define                 APIC_DEST_ALLINC        0x80000
  58 #define                 APIC_DEST_ALLBUT        0xC0000
  59 #define                 APIC_ICR_RR_MASK        0x30000
  60 #define                 APIC_ICR_RR_INVALID     0x00000
  61 #define                 APIC_ICR_RR_INPROG      0x10000
  62 #define                 APIC_ICR_RR_VALID       0x20000
  63 #define                 APIC_INT_LEVELTRIG      0x08000
  64 #define                 APIC_INT_ASSERT         0x04000
  65 #define                 APIC_ICR_BUSY           0x01000
  66 #define                 APIC_DEST_LOGICAL       0x00800
  67 #define                 APIC_DEST_PHYSICAL      0x00000
  68 #define                 APIC_DM_FIXED           0x00000
  69 #define                 APIC_DM_LOWEST          0x00100
  70 #define                 APIC_DM_SMI             0x00200
  71 #define                 APIC_DM_REMRD           0x00300
  72 #define                 APIC_DM_NMI             0x00400
  73 #define                 APIC_DM_INIT            0x00500
  74 #define                 APIC_DM_STARTUP         0x00600
  75 #define                 APIC_DM_EXTINT          0x00700
  76 #define                 APIC_VECTOR_MASK        0x000FF
  77 #define         APIC_ICR2       0x310
  78 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  79 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  80 #define         APIC_LVTT       0x320
  81 #define         APIC_LVTTHMR    0x330
  82 #define         APIC_LVTPC      0x340
  83 #define         APIC_LVT0       0x350
  84 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  85 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  86 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  87 #define                 APIC_TIMER_BASE_CLKIN           0x0
  88 #define                 APIC_TIMER_BASE_TMBASE          0x1
  89 #define                 APIC_TIMER_BASE_DIV             0x2
  90 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  91 #define                 APIC_LVT_MASKED                 (1<<16)
  92 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  93 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  94 #define                 APIC_INPUT_POLARITY             (1<<13)
  95 #define                 APIC_SEND_PENDING               (1<<12)
  96 #define                 APIC_MODE_MASK                  0x700
  97 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  98 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  99 #define                         APIC_MODE_FIXED         0x0
 100 #define                         APIC_MODE_NMI           0x4
 101 #define                         APIC_MODE_EXTINT        0x7
 102 #define         APIC_LVT1       0x360
 103 #define         APIC_LVTERR     0x370
 104 #define         APIC_TMICT      0x380
 105 #define         APIC_TMCCT      0x390
 106 #define         APIC_TDCR       0x3E0
 107 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 108 #define                 APIC_TDR_DIV_1          0xB
 109 #define                 APIC_TDR_DIV_2          0x0
 110 #define                 APIC_TDR_DIV_4          0x1
 111 #define                 APIC_TDR_DIV_8          0x2
 112 #define                 APIC_TDR_DIV_16         0x3
 113 #define                 APIC_TDR_DIV_32         0x8
 114 #define                 APIC_TDR_DIV_64         0x9
 115 #define                 APIC_TDR_DIV_128        0xA
 116
 117 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 118
 119 #else /* CONFIG_XEN */
 120
 121 #define                 APIC_ALL_CPUS           0xFFu
 122
 123 enum {
 124         APIC_DEST_ALLBUT = 0x1,
 125         APIC_DEST_SELF,
 126         APIC_DEST_ALLINC
 127 };
 128
 129 #endif /* CONFIG_XEN */
 130
 131 #define MAX_IO_APICS 128
 132
 133 #ifndef CONFIG_XEN
 134
 135 #define MAX_LOCAL_APIC 256
 136
 137 /*
 138  * All x86-64 systems are xAPIC compatible.
 139  * In the following, "apicid" is a physical APIC ID.
 140  */
 141 #define XAPIC_DEST_CPUS_SHIFT   4
 142 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 143 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 144 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
 145 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
 146 #define APIC_CPUID(apicid)      ((apicid) & XAPIC_DEST_CPUS_MASK)
 147 #define NUM_APIC_CLUSTERS       ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 148
 149 /*
 150  * the local APIC register structure, memory mapped. Not terribly well
 151  * tested, but we might eventually use this one in the future - the
 152  * problem why we cannot use it right now is the P5 APIC, it has an
 153  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 154  */
 155 #define u32 unsigned int
 156
 157 struct local_apic {
 158
 159 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 160
 161 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 162
 163 /*020*/ struct { /* APIC ID Register */
 164                 u32   __reserved_1      : 24,
 165                         phys_apic_id    :  4,
 166                         __reserved_2    :  4;
 167                 u32 __reserved[3];
 168         } id;
 169
 170 /*030*/ const
 171         struct { /* APIC Version Register */
 172                 u32   version           :  8,
 173                         __reserved_1    :  8,
 174                         max_lvt         :  8,
 175                         __reserved_2    :  8;
 176                 u32 __reserved[3];
 177         } version;
 178
 179 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 180
 181 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 182
 183 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 184
 185 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 186
 187 /*080*/ struct { /* Task Priority Register */
 188                 u32   priority  :  8,
 189                         __reserved_1    : 24;
 190                 u32 __reserved_2[3];
 191         } tpr;
 192
 193 /*090*/ const
 194         struct { /* Arbitration Priority Register */
 195                 u32   priority  :  8,
 196                         __reserved_1    : 24;
 197                 u32 __reserved_2[3];
 198         } apr;
 199
 200 /*0A0*/ const
 201         struct { /* Processor Priority Register */
 202                 u32   priority  :  8,
 203                         __reserved_1    : 24;
 204                 u32 __reserved_2[3];
 205         } ppr;
 206
 207 /*0B0*/ struct { /* End Of Interrupt Register */
 208                 u32   eoi;
 209                 u32 __reserved[3];
 210         } eoi;
 211
 212 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 213
 214 /*0D0*/ struct { /* Logical Destination Register */
 215                 u32   __reserved_1      : 24,
 216                         logical_dest    :  8;
 217                 u32 __reserved_2[3];
 218         } ldr;
 219
 220 /*0E0*/ struct { /* Destination Format Register */
 221                 u32   __reserved_1      : 28,
 222                         model           :  4;
 223                 u32 __reserved_2[3];
 224         } dfr;
 225
 226 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 227                 u32     spurious_vector :  8,
 228                         apic_enabled    :  1,
 229                         focus_cpu       :  1,
 230                         __reserved_2    : 22;
 231                 u32 __reserved_3[3];
 232         } svr;
 233
 234 /*100*/ struct { /* In Service Register */
 235 /*170*/         u32 bitfield;
 236                 u32 __reserved[3];
 237         } isr [8];
 238
 239 /*180*/ struct { /* Trigger Mode Register */
 240 /*1F0*/         u32 bitfield;
 241                 u32 __reserved[3];
 242         } tmr [8];
 243
 244 /*200*/ struct { /* Interrupt Request Register */
 245 /*270*/         u32 bitfield;
 246                 u32 __reserved[3];
 247         } irr [8];
 248
 249 /*280*/ union { /* Error Status Register */
 250                 struct {
 251                         u32   send_cs_error                     :  1,
 252                                 receive_cs_error                :  1,
 253                                 send_accept_error               :  1,
 254                                 receive_accept_error            :  1,
 255                                 __reserved_1                    :  1,
 256                                 send_illegal_vector             :  1,
 257                                 receive_illegal_vector          :  1,
 258                                 illegal_register_address        :  1,
 259                                 __reserved_2                    : 24;
 260                         u32 __reserved_3[3];
 261                 } error_bits;
 262                 struct {
 263                         u32 errors;
 264                         u32 __reserved_3[3];
 265                 } all_errors;
 266         } esr;
 267
 268 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 269
 270 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 271
 272 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 273
 274 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 275
 276 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 277
 278 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 279
 280 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 281
 282 /*300*/ struct { /* Interrupt Command Register 1 */
 283                 u32   vector                    :  8,
 284                         delivery_mode           :  3,
 285                         destination_mode        :  1,
 286                         delivery_status         :  1,
 287                         __reserved_1            :  1,
 288                         level                   :  1,
 289                         trigger                 :  1,
 290                         __reserved_2            :  2,
 291                         shorthand               :  2,
 292                         __reserved_3            :  12;
 293                 u32 __reserved_4[3];
 294         } icr1;
 295
 296 /*310*/ struct { /* Interrupt Command Register 2 */
 297                 union {
 298                         u32   __reserved_1      : 24,
 299                                 phys_dest       :  4,
 300                                 __reserved_2    :  4;
 301                         u32   __reserved_3      : 24,
 302                                 logical_dest    :  8;
 303                 } dest;
 304                 u32 __reserved_4[3];
 305         } icr2;
 306
 307 /*320*/ struct { /* LVT - Timer */
 308                 u32   vector            :  8,
 309                         __reserved_1    :  4,
 310                         delivery_status :  1,
 311                         __reserved_2    :  3,
 312                         mask            :  1,
 313                         timer_mode      :  1,
 314                         __reserved_3    : 14;
 315                 u32 __reserved_4[3];
 316         } lvt_timer;
 317
 318 /*330*/ struct { /* LVT - Thermal Sensor */
 319                 u32  vector             :  8,
 320                         delivery_mode   :  3,
 321                         __reserved_1    :  1,
 322                         delivery_status :  1,
 323                         __reserved_2    :  3,
 324                         mask            :  1,
 325                         __reserved_3    : 15;
 326                 u32 __reserved_4[3];
 327         } lvt_thermal;
 328
 329 /*340*/ struct { /* LVT - Performance Counter */
 330                 u32   vector            :  8,
 331                         delivery_mode   :  3,
 332                         __reserved_1    :  1,
 333                         delivery_status :  1,
 334                         __reserved_2    :  3,
 335                         mask            :  1,
 336                         __reserved_3    : 15;
 337                 u32 __reserved_4[3];
 338         } lvt_pc;
 339
 340 /*350*/ struct { /* LVT - LINT0 */
 341                 u32   vector            :  8,
 342                         delivery_mode   :  3,
 343                         __reserved_1    :  1,
 344                         delivery_status :  1,
 345                         polarity        :  1,
 346                         remote_irr      :  1,
 347                         trigger         :  1,
 348                         mask            :  1,
 349                         __reserved_2    : 15;
 350                 u32 __reserved_3[3];
 351         } lvt_lint0;
 352
 353 /*360*/ struct { /* LVT - LINT1 */
 354                 u32   vector            :  8,
 355                         delivery_mode   :  3,
 356                         __reserved_1    :  1,
 357                         delivery_status :  1,
 358                         polarity        :  1,
 359                         remote_irr      :  1,
 360                         trigger         :  1,
 361                         mask            :  1,
 362                         __reserved_2    : 15;
 363                 u32 __reserved_3[3];
 364         } lvt_lint1;
 365
 366 /*370*/ struct { /* LVT - Error */
 367                 u32   vector            :  8,
 368                         __reserved_1    :  4,
 369                         delivery_status :  1,
 370                         __reserved_2    :  3,
 371                         mask            :  1,
 372                         __reserved_3    : 15;
 373                 u32 __reserved_4[3];
 374         } lvt_error;
 375
 376 /*380*/ struct { /* Timer Initial Count Register */
 377                 u32   initial_count;
 378                 u32 __reserved_2[3];
 379         } timer_icr;
 380
 381 /*390*/ const
 382         struct { /* Timer Current Count Register */
 383                 u32   curr_count;
 384                 u32 __reserved_2[3];
 385         } timer_ccr;
 386
 387 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 388
 389 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 390
 391 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 392
 393 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 394
 395 /*3E0*/ struct { /* Timer Divide Configuration Register */
 396                 u32   divisor           :  4,
 397                         __reserved_1    : 28;
 398                 u32 __reserved_2[3];
 399         } timer_dcr;
 400
 401 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 402
 403 } __attribute__ ((packed));
 404
 405 #undef u32
 406
 407 #endif /* CONFIG_XEN */
 408
 409 #define BAD_APICID 0xFFu
 410
 411 #endif