drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47
  48 #ifdef RTL8169_DEBUG
  49 #define assert(expr) \
  50         if (!(expr)) {                                  \
  51                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  52                 #expr,__FILE__,__func__,__LINE__);              \
  53         }
  54 #define dprintk(fmt, args...) \
  55         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  56 #else
  57 #define assert(expr) do {} while (0)
  58 #define dprintk(fmt, args...)   do {} while (0)
  59 #endif /* RTL8169_DEBUG */
  60
  61 #define R8169_MSG_DEFAULT \
  62         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  63
  64 #define TX_BUFFS_AVAIL(tp) \
  65         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  66
  67 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  68    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  69 static const int multicast_filter_limit = 32;
  70
  71 #define MAX_READ_REQUEST_SHIFT  12
  72 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  73 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  74 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  75
  76 #define R8169_REGS_SIZE         256
  77 #define R8169_NAPI_WEIGHT       64
  78 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  79 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  80 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  81 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  82 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  83
  84 #define RTL8169_TX_TIMEOUT      (6*HZ)
  85 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  86
  87 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  88 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  89 #define RTL_EEPROM_SIG_ADDR     0x0000
  90
  91 /* write/read MMIO register */
  92 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  93 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  94 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  95 #define RTL_R8(reg)             readb (ioaddr + (reg))
  96 #define RTL_R16(reg)            readw (ioaddr + (reg))
  97 #define RTL_R32(reg)            readl (ioaddr + (reg))
  98
  99 enum mac_version {
 100         RTL_GIGA_MAC_VER_01 = 0,
 101         RTL_GIGA_MAC_VER_02,
 102         RTL_GIGA_MAC_VER_03,
 103         RTL_GIGA_MAC_VER_04,
 104         RTL_GIGA_MAC_VER_05,
 105         RTL_GIGA_MAC_VER_06,
 106         RTL_GIGA_MAC_VER_07,
 107         RTL_GIGA_MAC_VER_08,
 108         RTL_GIGA_MAC_VER_09,
 109         RTL_GIGA_MAC_VER_10,
 110         RTL_GIGA_MAC_VER_11,
 111         RTL_GIGA_MAC_VER_12,
 112         RTL_GIGA_MAC_VER_13,
 113         RTL_GIGA_MAC_VER_14,
 114         RTL_GIGA_MAC_VER_15,
 115         RTL_GIGA_MAC_VER_16,
 116         RTL_GIGA_MAC_VER_17,
 117         RTL_GIGA_MAC_VER_18,
 118         RTL_GIGA_MAC_VER_19,
 119         RTL_GIGA_MAC_VER_20,
 120         RTL_GIGA_MAC_VER_21,
 121         RTL_GIGA_MAC_VER_22,
 122         RTL_GIGA_MAC_VER_23,
 123         RTL_GIGA_MAC_VER_24,
 124         RTL_GIGA_MAC_VER_25,
 125         RTL_GIGA_MAC_VER_26,
 126         RTL_GIGA_MAC_VER_27,
 127         RTL_GIGA_MAC_VER_28,
 128         RTL_GIGA_MAC_VER_29,
 129         RTL_GIGA_MAC_VER_30,
 130         RTL_GIGA_MAC_VER_31,
 131         RTL_GIGA_MAC_VER_32,
 132         RTL_GIGA_MAC_VER_33,
 133         RTL_GIGA_MAC_VER_34,
 134         RTL_GIGA_MAC_VER_35,
 135         RTL_GIGA_MAC_VER_36,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define JUMBO_1K        ETH_DATA_LEN
 145 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 146 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 147 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 148 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 149
 150 #define _R(NAME,TD,FW,SZ,B) {   \
 151         .name = NAME,           \
 152         .txd_version = TD,      \
 153         .fw_name = FW,          \
 154         .jumbo_max = SZ,        \
 155         .jumbo_tx_csum = B      \
 156 }
 157
 158 static const struct {
 159         const char *name;
 160         enum rtl_tx_desc_version txd_version;
 161         const char *fw_name;
 162         u16 jumbo_max;
 163         bool jumbo_tx_csum;
 164 } rtl_chip_infos[] = {
 165         /* PCI devices. */
 166         [RTL_GIGA_MAC_VER_01] =
 167                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 168         [RTL_GIGA_MAC_VER_02] =
 169                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 170         [RTL_GIGA_MAC_VER_03] =
 171                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_04] =
 173                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_05] =
 175                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_06] =
 177                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         /* PCI-E devices. */
 179         [RTL_GIGA_MAC_VER_07] =
 180                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 181         [RTL_GIGA_MAC_VER_08] =
 182                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 183         [RTL_GIGA_MAC_VER_09] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_10] =
 186                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_11] =
 188                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 189         [RTL_GIGA_MAC_VER_12] =
 190                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 191         [RTL_GIGA_MAC_VER_13] =
 192                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_14] =
 194                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_15] =
 196                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_16] =
 198                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_17] =
 200                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 201         [RTL_GIGA_MAC_VER_18] =
 202                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 203         [RTL_GIGA_MAC_VER_19] =
 204                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 205         [RTL_GIGA_MAC_VER_20] =
 206                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_21] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_22] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_23] =
 212                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_24] =
 214                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_25] =
 216                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 217                                                         JUMBO_9K, false),
 218         [RTL_GIGA_MAC_VER_26] =
 219                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 220                                                         JUMBO_9K, false),
 221         [RTL_GIGA_MAC_VER_27] =
 222                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 223         [RTL_GIGA_MAC_VER_28] =
 224                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_29] =
 226                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 227                                                         JUMBO_1K, true),
 228         [RTL_GIGA_MAC_VER_30] =
 229                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 230                                                         JUMBO_1K, true),
 231         [RTL_GIGA_MAC_VER_31] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_32] =
 234                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 235                                                         JUMBO_9K, false),
 236         [RTL_GIGA_MAC_VER_33] =
 237                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 238                                                         JUMBO_9K, false),
 239         [RTL_GIGA_MAC_VER_34] =
 240                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 241                                                         JUMBO_9K, false),
 242         [RTL_GIGA_MAC_VER_35] =
 243                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 244                                                         JUMBO_9K, false),
 245         [RTL_GIGA_MAC_VER_36] =
 246                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 247                                                         JUMBO_9K, false),
 248 };
 249 #undef _R
 250
 251 enum cfg_version {
 252         RTL_CFG_0 = 0x00,
 253         RTL_CFG_1,
 254         RTL_CFG_2
 255 };
 256
 257 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 258         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 259         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 260         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 261         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 262         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 266         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 267         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 268                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 269         { 0x0001,                               0x8168,
 270                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 271         {0,},
 272 };
 273
 274 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 275
 276 static int rx_buf_sz = 16383;
 277 static int use_dac;
 278 static struct {
 279         u32 msg_enable;
 280 } debug = { -1 };
 281
 282 enum rtl_registers {
 283         MAC0            = 0,    /* Ethernet hardware address. */
 284         MAC4            = 4,
 285         MAR0            = 8,    /* Multicast filter. */
 286         CounterAddrLow          = 0x10,
 287         CounterAddrHigh         = 0x14,
 288         TxDescStartAddrLow      = 0x20,
 289         TxDescStartAddrHigh     = 0x24,
 290         TxHDescStartAddrLow     = 0x28,
 291         TxHDescStartAddrHigh    = 0x2c,
 292         FLASH           = 0x30,
 293         ERSR            = 0x36,
 294         ChipCmd         = 0x37,
 295         TxPoll          = 0x38,
 296         IntrMask        = 0x3c,
 297         IntrStatus      = 0x3e,
 298
 299         TxConfig        = 0x40,
 300 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 301 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 302
 303         RxConfig        = 0x44,
 304 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 305 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 306 #define RXCFG_FIFO_SHIFT                13
 307                                         /* No threshold before first PCI xfer */
 308 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 309 #define RXCFG_DMA_SHIFT                 8
 310                                         /* Unlimited maximum PCI burst. */
 311 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 312
 313         RxMissed        = 0x4c,
 314         Cfg9346         = 0x50,
 315         Config0         = 0x51,
 316         Config1         = 0x52,
 317         Config2         = 0x53,
 318         Config3         = 0x54,
 319         Config4         = 0x55,
 320         Config5         = 0x56,
 321         MultiIntr       = 0x5c,
 322         PHYAR           = 0x60,
 323         PHYstatus       = 0x6c,
 324         RxMaxSize       = 0xda,
 325         CPlusCmd        = 0xe0,
 326         IntrMitigate    = 0xe2,
 327         RxDescAddrLow   = 0xe4,
 328         RxDescAddrHigh  = 0xe8,
 329         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 330
 331 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 332
 333         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 334
 335 #define TxPacketMax     (8064 >> 7)
 336 #define EarlySize       0x27
 337
 338         FuncEvent       = 0xf0,
 339         FuncEventMask   = 0xf4,
 340         FuncPresetState = 0xf8,
 341         FuncForceEvent  = 0xfc,
 342 };
 343
 344 enum rtl8110_registers {
 345         TBICSR                  = 0x64,
 346         TBI_ANAR                = 0x68,
 347         TBI_LPAR                = 0x6a,
 348 };
 349
 350 enum rtl8168_8101_registers {
 351         CSIDR                   = 0x64,
 352         CSIAR                   = 0x68,
 353 #define CSIAR_FLAG                      0x80000000
 354 #define CSIAR_WRITE_CMD                 0x80000000
 355 #define CSIAR_BYTE_ENABLE               0x0f
 356 #define CSIAR_BYTE_ENABLE_SHIFT         12
 357 #define CSIAR_ADDR_MASK                 0x0fff
 358         PMCH                    = 0x6f,
 359         EPHYAR                  = 0x80,
 360 #define EPHYAR_FLAG                     0x80000000
 361 #define EPHYAR_WRITE_CMD                0x80000000
 362 #define EPHYAR_REG_MASK                 0x1f
 363 #define EPHYAR_REG_SHIFT                16
 364 #define EPHYAR_DATA_MASK                0xffff
 365         DLLPR                   = 0xd0,
 366 #define PFM_EN                          (1 << 6)
 367         DBG_REG                 = 0xd1,
 368 #define FIX_NAK_1                       (1 << 4)
 369 #define FIX_NAK_2                       (1 << 3)
 370         TWSI                    = 0xd2,
 371         MCU                     = 0xd3,
 372 #define NOW_IS_OOB                      (1 << 7)
 373 #define EN_NDP                          (1 << 3)
 374 #define EN_OOB_RESET                    (1 << 2)
 375         EFUSEAR                 = 0xdc,
 376 #define EFUSEAR_FLAG                    0x80000000
 377 #define EFUSEAR_WRITE_CMD               0x80000000
 378 #define EFUSEAR_READ_CMD                0x00000000
 379 #define EFUSEAR_REG_MASK                0x03ff
 380 #define EFUSEAR_REG_SHIFT               8
 381 #define EFUSEAR_DATA_MASK               0xff
 382 };
 383
 384 enum rtl8168_registers {
 385         LED_FREQ                = 0x1a,
 386         EEE_LED                 = 0x1b,
 387         ERIDR                   = 0x70,
 388         ERIAR                   = 0x74,
 389 #define ERIAR_FLAG                      0x80000000
 390 #define ERIAR_WRITE_CMD                 0x80000000
 391 #define ERIAR_READ_CMD                  0x00000000
 392 #define ERIAR_ADDR_BYTE_ALIGN           4
 393 #define ERIAR_TYPE_SHIFT                16
 394 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 395 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 396 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 397 #define ERIAR_MASK_SHIFT                12
 398 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 399 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 400 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 401         EPHY_RXER_NUM           = 0x7c,
 402         OCPDR                   = 0xb0, /* OCP GPHY access */
 403 #define OCPDR_WRITE_CMD                 0x80000000
 404 #define OCPDR_READ_CMD                  0x00000000
 405 #define OCPDR_REG_MASK                  0x7f
 406 #define OCPDR_GPHY_REG_SHIFT            16
 407 #define OCPDR_DATA_MASK                 0xffff
 408         OCPAR                   = 0xb4,
 409 #define OCPAR_FLAG                      0x80000000
 410 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 411 #define OCPAR_GPHY_READ_CMD             0x0000f060
 412         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 413         MISC                    = 0xf0, /* 8168e only. */
 414 #define TXPLA_RST                       (1 << 29)
 415 #define PWM_EN                          (1 << 22)
 416 };
 417
 418 enum rtl_register_content {
 419         /* InterruptStatusBits */
 420         SYSErr          = 0x8000,
 421         PCSTimeout      = 0x4000,
 422         SWInt           = 0x0100,
 423         TxDescUnavail   = 0x0080,
 424         RxFIFOOver      = 0x0040,
 425         LinkChg         = 0x0020,
 426         RxOverflow      = 0x0010,
 427         TxErr           = 0x0008,
 428         TxOK            = 0x0004,
 429         RxErr           = 0x0002,
 430         RxOK            = 0x0001,
 431
 432         /* RxStatusDesc */
 433         RxBOVF  = (1 << 24),
 434         RxFOVF  = (1 << 23),
 435         RxRWT   = (1 << 22),
 436         RxRES   = (1 << 21),
 437         RxRUNT  = (1 << 20),
 438         RxCRC   = (1 << 19),
 439
 440         /* ChipCmdBits */
 441         StopReq         = 0x80,
 442         CmdReset        = 0x10,
 443         CmdRxEnb        = 0x08,
 444         CmdTxEnb        = 0x04,
 445         RxBufEmpty      = 0x01,
 446
 447         /* TXPoll register p.5 */
 448         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 449         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 450         FSWInt          = 0x01,         /* Forced software interrupt */
 451
 452         /* Cfg9346Bits */
 453         Cfg9346_Lock    = 0x00,
 454         Cfg9346_Unlock  = 0xc0,
 455
 456         /* rx_mode_bits */
 457         AcceptErr       = 0x20,
 458         AcceptRunt      = 0x10,
 459         AcceptBroadcast = 0x08,
 460         AcceptMulticast = 0x04,
 461         AcceptMyPhys    = 0x02,
 462         AcceptAllPhys   = 0x01,
 463 #define RX_CONFIG_ACCEPT_MASK           0x3f
 464
 465         /* TxConfigBits */
 466         TxInterFrameGapShift = 24,
 467         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 468
 469         /* Config1 register p.24 */
 470         LEDS1           = (1 << 7),
 471         LEDS0           = (1 << 6),
 472         Speed_down      = (1 << 4),
 473         MEMMAP          = (1 << 3),
 474         IOMAP           = (1 << 2),
 475         VPD             = (1 << 1),
 476         PMEnable        = (1 << 0),     /* Power Management Enable */
 477
 478         /* Config2 register p. 25 */
 479         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 480         PCI_Clock_66MHz = 0x01,
 481         PCI_Clock_33MHz = 0x00,
 482
 483         /* Config3 register p.25 */
 484         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 485         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 486         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 487         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 488
 489         /* Config4 register */
 490         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 491
 492         /* Config5 register p.27 */
 493         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 494         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 495         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 496         Spi_en          = (1 << 3),
 497         LanWake         = (1 << 1),     /* LanWake enable/disable */
 498         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 499
 500         /* TBICSR p.28 */
 501         TBIReset        = 0x80000000,
 502         TBILoopback     = 0x40000000,
 503         TBINwEnable     = 0x20000000,
 504         TBINwRestart    = 0x10000000,
 505         TBILinkOk       = 0x02000000,
 506         TBINwComplete   = 0x01000000,
 507
 508         /* CPlusCmd p.31 */
 509         EnableBist      = (1 << 15),    // 8168 8101
 510         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 511         Normal_mode     = (1 << 13),    // unused
 512         Force_half_dup  = (1 << 12),    // 8168 8101
 513         Force_rxflow_en = (1 << 11),    // 8168 8101
 514         Force_txflow_en = (1 << 10),    // 8168 8101
 515         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 516         ASF             = (1 << 8),     // 8168 8101
 517         PktCntrDisable  = (1 << 7),     // 8168 8101
 518         Mac_dbgo_sel    = 0x001c,       // 8168
 519         RxVlan          = (1 << 6),
 520         RxChkSum        = (1 << 5),
 521         PCIDAC          = (1 << 4),
 522         PCIMulRW        = (1 << 3),
 523         INTT_0          = 0x0000,       // 8168
 524         INTT_1          = 0x0001,       // 8168
 525         INTT_2          = 0x0002,       // 8168
 526         INTT_3          = 0x0003,       // 8168
 527
 528         /* rtl8169_PHYstatus */
 529         TBI_Enable      = 0x80,
 530         TxFlowCtrl      = 0x40,
 531         RxFlowCtrl      = 0x20,
 532         _1000bpsF       = 0x10,
 533         _100bps         = 0x08,
 534         _10bps          = 0x04,
 535         LinkStatus      = 0x02,
 536         FullDup         = 0x01,
 537
 538         /* _TBICSRBit */
 539         TBILinkOK       = 0x02000000,
 540
 541         /* DumpCounterCommand */
 542         CounterDump     = 0x8,
 543 };
 544
 545 enum rtl_desc_bit {
 546         /* First doubleword. */
 547         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 548         RingEnd         = (1 << 30), /* End of descriptor ring */
 549         FirstFrag       = (1 << 29), /* First segment of a packet */
 550         LastFrag        = (1 << 28), /* Final segment of a packet */
 551 };
 552
 553 /* Generic case. */
 554 enum rtl_tx_desc_bit {
 555         /* First doubleword. */
 556         TD_LSO          = (1 << 27),            /* Large Send Offload */
 557 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 558
 559         /* Second doubleword. */
 560         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 561 };
 562
 563 /* 8169, 8168b and 810x except 8102e. */
 564 enum rtl_tx_desc_bit_0 {
 565         /* First doubleword. */
 566 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 567         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 568         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 569         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 570 };
 571
 572 /* 8102e, 8168c and beyond. */
 573 enum rtl_tx_desc_bit_1 {
 574         /* Second doubleword. */
 575 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 576         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 577         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 578         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 579 };
 580
 581 static const struct rtl_tx_desc_info {
 582         struct {
 583                 u32 udp;
 584                 u32 tcp;
 585         } checksum;
 586         u16 mss_shift;
 587         u16 opts_offset;
 588 } tx_desc_info [] = {
 589         [RTL_TD_0] = {
 590                 .checksum = {
 591                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 592                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 593                 },
 594                 .mss_shift      = TD0_MSS_SHIFT,
 595                 .opts_offset    = 0
 596         },
 597         [RTL_TD_1] = {
 598                 .checksum = {
 599                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 600                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 601                 },
 602                 .mss_shift      = TD1_MSS_SHIFT,
 603                 .opts_offset    = 1
 604         }
 605 };
 606
 607 enum rtl_rx_desc_bit {
 608         /* Rx private */
 609         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 610         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 611
 612 #define RxProtoUDP      (PID1)
 613 #define RxProtoTCP      (PID0)
 614 #define RxProtoIP       (PID1 | PID0)
 615 #define RxProtoMask     RxProtoIP
 616
 617         IPFail          = (1 << 16), /* IP checksum failed */
 618         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 619         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 620         RxVlanTag       = (1 << 16), /* VLAN tag available */
 621 };
 622
 623 #define RsvdMask        0x3fffc000
 624
 625 struct TxDesc {
 626         __le32 opts1;
 627         __le32 opts2;
 628         __le64 addr;
 629 };
 630
 631 struct RxDesc {
 632         __le32 opts1;
 633         __le32 opts2;
 634         __le64 addr;
 635 };
 636
 637 struct ring_info {
 638         struct sk_buff  *skb;
 639         u32             len;
 640         u8              __pad[sizeof(void *) - sizeof(u32)];
 641 };
 642
 643 enum features {
 644         RTL_FEATURE_WOL         = (1 << 0),
 645         RTL_FEATURE_MSI         = (1 << 1),
 646         RTL_FEATURE_GMII        = (1 << 2),
 647 };
 648
 649 struct rtl8169_counters {
 650         __le64  tx_packets;
 651         __le64  rx_packets;
 652         __le64  tx_errors;
 653         __le32  rx_errors;
 654         __le16  rx_missed;
 655         __le16  align_errors;
 656         __le32  tx_one_collision;
 657         __le32  tx_multi_collision;
 658         __le64  rx_unicast;
 659         __le64  rx_broadcast;
 660         __le32  rx_multicast;
 661         __le16  tx_aborted;
 662         __le16  tx_underun;
 663 };
 664
 665 enum rtl_flag {
 666         RTL_FLAG_TASK_ENABLED,
 667         RTL_FLAG_TASK_SLOW_PENDING,
 668         RTL_FLAG_TASK_RESET_PENDING,
 669         RTL_FLAG_TASK_PHY_PENDING,
 670         RTL_FLAG_MAX
 671 };
 672
 673 struct rtl8169_stats {
 674         u64                     packets;
 675         u64                     bytes;
 676         struct u64_stats_sync   syncp;
 677 };
 678
 679 struct rtl8169_private {
 680         void __iomem *mmio_addr;        /* memory map physical address */
 681         struct pci_dev *pci_dev;
 682         struct net_device *dev;
 683         struct napi_struct napi;
 684         u32 msg_enable;
 685         u16 txd_version;
 686         u16 mac_version;
 687         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 688         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 689         u32 dirty_rx;
 690         u32 dirty_tx;
 691         struct rtl8169_stats rx_stats;
 692         struct rtl8169_stats tx_stats;
 693         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 694         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 695         dma_addr_t TxPhyAddr;
 696         dma_addr_t RxPhyAddr;
 697         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 698         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 699         struct timer_list timer;
 700         u16 cp_cmd;
 701
 702         u16 event_slow;
 703
 704         struct mdio_ops {
 705                 void (*write)(void __iomem *, int, int);
 706                 int (*read)(void __iomem *, int);
 707         } mdio_ops;
 708
 709         struct pll_power_ops {
 710                 void (*down)(struct rtl8169_private *);
 711                 void (*up)(struct rtl8169_private *);
 712         } pll_power_ops;
 713
 714         struct jumbo_ops {
 715                 void (*enable)(struct rtl8169_private *);
 716                 void (*disable)(struct rtl8169_private *);
 717         } jumbo_ops;
 718
 719         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 720         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 721         void (*phy_reset_enable)(struct rtl8169_private *tp);
 722         void (*hw_start)(struct net_device *);
 723         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 724         unsigned int (*link_ok)(void __iomem *);
 725         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 726
 727         struct {
 728                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 729                 struct mutex mutex;
 730                 struct work_struct work;
 731         } wk;
 732
 733         unsigned features;
 734
 735         struct mii_if_info mii;
 736         struct rtl8169_counters counters;
 737         u32 saved_wolopts;
 738         u32 opts1_mask;
 739
 740         struct rtl_fw {
 741                 const struct firmware *fw;
 742
 743 #define RTL_VER_SIZE            32
 744
 745                 char version[RTL_VER_SIZE];
 746
 747                 struct rtl_fw_phy_action {
 748                         __le32 *code;
 749                         size_t size;
 750                 } phy_action;
 751         } *rtl_fw;
 752 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 753 };
 754
 755 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 756 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 757 module_param(use_dac, int, 0);
 758 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 759 module_param_named(debug, debug.msg_enable, int, 0);
 760 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 761 MODULE_LICENSE("GPL");
 762 MODULE_VERSION(RTL8169_VERSION);
 763 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 764 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 765 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 766 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 767 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 768 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 769 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 770 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 771
 772 static void rtl_lock_work(struct rtl8169_private *tp)
 773 {
 774         mutex_lock(&tp->wk.mutex);
 775 }
 776
 777 static void rtl_unlock_work(struct rtl8169_private *tp)
 778 {
 779         mutex_unlock(&tp->wk.mutex);
 780 }
 781
 782 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 783 {
 784         int cap = pci_pcie_cap(pdev);
 785
 786         if (cap) {
 787                 u16 ctl;
 788
 789                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 790                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 791                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 792         }
 793 }
 794
 795 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 796 {
 797         void __iomem *ioaddr = tp->mmio_addr;
 798         int i;
 799
 800         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 801         for (i = 0; i < 20; i++) {
 802                 udelay(100);
 803                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 804                         break;
 805         }
 806         return RTL_R32(OCPDR);
 807 }
 808
 809 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 810 {
 811         void __iomem *ioaddr = tp->mmio_addr;
 812         int i;
 813
 814         RTL_W32(OCPDR, data);
 815         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 816         for (i = 0; i < 20; i++) {
 817                 udelay(100);
 818                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 819                         break;
 820         }
 821 }
 822
 823 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 824 {
 825         void __iomem *ioaddr = tp->mmio_addr;
 826         int i;
 827
 828         RTL_W8(ERIDR, cmd);
 829         RTL_W32(ERIAR, 0x800010e8);
 830         msleep(2);
 831         for (i = 0; i < 5; i++) {
 832                 udelay(100);
 833                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 834                         break;
 835         }
 836
 837         ocp_write(tp, 0x1, 0x30, 0x00000001);
 838 }
 839
 840 #define OOB_CMD_RESET           0x00
 841 #define OOB_CMD_DRIVER_START    0x05
 842 #define OOB_CMD_DRIVER_STOP     0x06
 843
 844 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 845 {
 846         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 847 }
 848
 849 static void rtl8168_driver_start(struct rtl8169_private *tp)
 850 {
 851         u16 reg;
 852         int i;
 853
 854         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 855
 856         reg = rtl8168_get_ocp_reg(tp);
 857
 858         for (i = 0; i < 10; i++) {
 859                 msleep(10);
 860                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 861                         break;
 862         }
 863 }
 864
 865 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 866 {
 867         u16 reg;
 868         int i;
 869
 870         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 871
 872         reg = rtl8168_get_ocp_reg(tp);
 873
 874         for (i = 0; i < 10; i++) {
 875                 msleep(10);
 876                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 877                         break;
 878         }
 879 }
 880
 881 static int r8168dp_check_dash(struct rtl8169_private *tp)
 882 {
 883         u16 reg = rtl8168_get_ocp_reg(tp);
 884
 885         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 886 }
 887
 888 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 889 {
 890         int i;
 891
 892         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 893
 894         for (i = 20; i > 0; i--) {
 895                 /*
 896                  * Check if the RTL8169 has completed writing to the specified
 897                  * MII register.
 898                  */
 899                 if (!(RTL_R32(PHYAR) & 0x80000000))
 900                         break;
 901                 udelay(25);
 902         }
 903         /*
 904          * According to hardware specs a 20us delay is required after write
 905          * complete indication, but before sending next command.
 906          */
 907         udelay(20);
 908 }
 909
 910 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 911 {
 912         int i, value = -1;
 913
 914         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 915
 916         for (i = 20; i > 0; i--) {
 917                 /*
 918                  * Check if the RTL8169 has completed retrieving data from
 919                  * the specified MII register.
 920                  */
 921                 if (RTL_R32(PHYAR) & 0x80000000) {
 922                         value = RTL_R32(PHYAR) & 0xffff;
 923                         break;
 924                 }
 925                 udelay(25);
 926         }
 927         /*
 928          * According to hardware specs a 20us delay is required after read
 929          * complete indication, but before sending next command.
 930          */
 931         udelay(20);
 932
 933         return value;
 934 }
 935
 936 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 937 {
 938         int i;
 939
 940         RTL_W32(OCPDR, data |
 941                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 942         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 943         RTL_W32(EPHY_RXER_NUM, 0);
 944
 945         for (i = 0; i < 100; i++) {
 946                 mdelay(1);
 947                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 948                         break;
 949         }
 950 }
 951
 952 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 953 {
 954         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 955                 (value & OCPDR_DATA_MASK));
 956 }
 957
 958 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 959 {
 960         int i;
 961
 962         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 963
 964         mdelay(1);
 965         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 966         RTL_W32(EPHY_RXER_NUM, 0);
 967
 968         for (i = 0; i < 100; i++) {
 969                 mdelay(1);
 970                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 971                         break;
 972         }
 973
 974         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 975 }
 976
 977 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 978
 979 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 980 {
 981         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 982 }
 983
 984 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 985 {
 986         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 987 }
 988
 989 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 990 {
 991         r8168dp_2_mdio_start(ioaddr);
 992
 993         r8169_mdio_write(ioaddr, reg_addr, value);
 994
 995         r8168dp_2_mdio_stop(ioaddr);
 996 }
 997
 998 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 999 {
1000         int value;
1001
1002         r8168dp_2_mdio_start(ioaddr);
1003
1004         value = r8169_mdio_read(ioaddr, reg_addr);
1005
1006         r8168dp_2_mdio_stop(ioaddr);
1007
1008         return value;
1009 }
1010
1011 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1012 {
1013         tp->mdio_ops.write(tp->mmio_addr, location, val);
1014 }
1015
1016 static int rtl_readphy(struct rtl8169_private *tp, int location)
1017 {
1018         return tp->mdio_ops.read(tp->mmio_addr, location);
1019 }
1020
1021 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1022 {
1023         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1024 }
1025
1026 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1027 {
1028         int val;
1029
1030         val = rtl_readphy(tp, reg_addr);
1031         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1032 }
1033
1034 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1035                            int val)
1036 {
1037         struct rtl8169_private *tp = netdev_priv(dev);
1038
1039         rtl_writephy(tp, location, val);
1040 }
1041
1042 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1043 {
1044         struct rtl8169_private *tp = netdev_priv(dev);
1045
1046         return rtl_readphy(tp, location);
1047 }
1048
1049 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1050 {
1051         unsigned int i;
1052
1053         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1054                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1055
1056         for (i = 0; i < 100; i++) {
1057                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1058                         break;
1059                 udelay(10);
1060         }
1061 }
1062
1063 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1064 {
1065         u16 value = 0xffff;
1066         unsigned int i;
1067
1068         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1069
1070         for (i = 0; i < 100; i++) {
1071                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1072                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1073                         break;
1074                 }
1075                 udelay(10);
1076         }
1077
1078         return value;
1079 }
1080
1081 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1082 {
1083         unsigned int i;
1084
1085         RTL_W32(CSIDR, value);
1086         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1087                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1088
1089         for (i = 0; i < 100; i++) {
1090                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1091                         break;
1092                 udelay(10);
1093         }
1094 }
1095
1096 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1097 {
1098         u32 value = ~0x00;
1099         unsigned int i;
1100
1101         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1102                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1103
1104         for (i = 0; i < 100; i++) {
1105                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1106                         value = RTL_R32(CSIDR);
1107                         break;
1108                 }
1109                 udelay(10);
1110         }
1111
1112         return value;
1113 }
1114
1115 static
1116 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1117 {
1118         unsigned int i;
1119
1120         BUG_ON((addr & 3) || (mask == 0));
1121         RTL_W32(ERIDR, val);
1122         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1123
1124         for (i = 0; i < 100; i++) {
1125                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1126                         break;
1127                 udelay(100);
1128         }
1129 }
1130
1131 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1132 {
1133         u32 value = ~0x00;
1134         unsigned int i;
1135
1136         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1137
1138         for (i = 0; i < 100; i++) {
1139                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1140                         value = RTL_R32(ERIDR);
1141                         break;
1142                 }
1143                 udelay(100);
1144         }
1145
1146         return value;
1147 }
1148
1149 static void
1150 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1151 {
1152         u32 val;
1153
1154         val = rtl_eri_read(ioaddr, addr, type);
1155         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1156 }
1157
1158 struct exgmac_reg {
1159         u16 addr;
1160         u16 mask;
1161         u32 val;
1162 };
1163
1164 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1165                                    const struct exgmac_reg *r, int len)
1166 {
1167         while (len-- > 0) {
1168                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1169                 r++;
1170         }
1171 }
1172
1173 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1174 {
1175         u8 value = 0xff;
1176         unsigned int i;
1177
1178         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1179
1180         for (i = 0; i < 300; i++) {
1181                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1182                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1183                         break;
1184                 }
1185                 udelay(100);
1186         }
1187
1188         return value;
1189 }
1190
1191 static u16 rtl_get_events(struct rtl8169_private *tp)
1192 {
1193         void __iomem *ioaddr = tp->mmio_addr;
1194
1195         return RTL_R16(IntrStatus);
1196 }
1197
1198 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1199 {
1200         void __iomem *ioaddr = tp->mmio_addr;
1201
1202         RTL_W16(IntrStatus, bits);
1203         mmiowb();
1204 }
1205
1206 static void rtl_irq_disable(struct rtl8169_private *tp)
1207 {
1208         void __iomem *ioaddr = tp->mmio_addr;
1209
1210         RTL_W16(IntrMask, 0);
1211         mmiowb();
1212 }
1213
1214 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1215 {
1216         void __iomem *ioaddr = tp->mmio_addr;
1217
1218         RTL_W16(IntrMask, bits);
1219 }
1220
1221 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1222 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1223 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1224
1225 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1226 {
1227         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1228 }
1229
1230 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         rtl_irq_disable(tp);
1235         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1236         RTL_R8(ChipCmd);
1237 }
1238
1239 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1240 {
1241         void __iomem *ioaddr = tp->mmio_addr;
1242
1243         return RTL_R32(TBICSR) & TBIReset;
1244 }
1245
1246 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1247 {
1248         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1249 }
1250
1251 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1252 {
1253         return RTL_R32(TBICSR) & TBILinkOk;
1254 }
1255
1256 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1257 {
1258         return RTL_R8(PHYstatus) & LinkStatus;
1259 }
1260
1261 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1262 {
1263         void __iomem *ioaddr = tp->mmio_addr;
1264
1265         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1266 }
1267
1268 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1269 {
1270         unsigned int val;
1271
1272         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1273         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1274 }
1275
1276 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1277 {
1278         void __iomem *ioaddr = tp->mmio_addr;
1279         struct net_device *dev = tp->dev;
1280
1281         if (!netif_running(dev))
1282                 return;
1283
1284         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1285                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1286                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1287                                       0x00000011, ERIAR_EXGMAC);
1288                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1289                                       0x00000005, ERIAR_EXGMAC);
1290                 } else if (RTL_R8(PHYstatus) & _100bps) {
1291                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1292                                       0x0000001f, ERIAR_EXGMAC);
1293                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1294                                       0x00000005, ERIAR_EXGMAC);
1295                 } else {
1296                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1297                                       0x0000001f, ERIAR_EXGMAC);
1298                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1299                                       0x0000003f, ERIAR_EXGMAC);
1300                 }
1301                 /* Reset packet filter */
1302                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1303                              ERIAR_EXGMAC);
1304                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1305                              ERIAR_EXGMAC);
1306         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1307                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1308                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1309                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1310                                       0x00000011, ERIAR_EXGMAC);
1311                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1312                                       0x00000005, ERIAR_EXGMAC);
1313                 } else {
1314                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1315                                       0x0000001f, ERIAR_EXGMAC);
1316                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1317                                       0x0000003f, ERIAR_EXGMAC);
1318                 }
1319         }
1320 }
1321
1322 static void __rtl8169_check_link_status(struct net_device *dev,
1323                                         struct rtl8169_private *tp,
1324                                         void __iomem *ioaddr, bool pm)
1325 {
1326         if (tp->link_ok(ioaddr)) {
1327                 rtl_link_chg_patch(tp);
1328                 /* This is to cancel a scheduled suspend if there's one. */
1329                 if (pm)
1330                         pm_request_resume(&tp->pci_dev->dev);
1331                 netif_carrier_on(dev);
1332                 if (net_ratelimit())
1333                         netif_info(tp, ifup, dev, "link up\n");
1334         } else {
1335                 netif_carrier_off(dev);
1336                 netif_info(tp, ifdown, dev, "link down\n");
1337                 if (pm)
1338                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1339         }
1340 }
1341
1342 static void rtl8169_check_link_status(struct net_device *dev,
1343                                       struct rtl8169_private *tp,
1344                                       void __iomem *ioaddr)
1345 {
1346         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1347 }
1348
1349 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1350
1351 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1352 {
1353         void __iomem *ioaddr = tp->mmio_addr;
1354         u8 options;
1355         u32 wolopts = 0;
1356
1357         options = RTL_R8(Config1);
1358         if (!(options & PMEnable))
1359                 return 0;
1360
1361         options = RTL_R8(Config3);
1362         if (options & LinkUp)
1363                 wolopts |= WAKE_PHY;
1364         if (options & MagicPacket)
1365                 wolopts |= WAKE_MAGIC;
1366
1367         options = RTL_R8(Config5);
1368         if (options & UWF)
1369                 wolopts |= WAKE_UCAST;
1370         if (options & BWF)
1371                 wolopts |= WAKE_BCAST;
1372         if (options & MWF)
1373                 wolopts |= WAKE_MCAST;
1374
1375         return wolopts;
1376 }
1377
1378 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1379 {
1380         struct rtl8169_private *tp = netdev_priv(dev);
1381
1382         rtl_lock_work(tp);
1383
1384         wol->supported = WAKE_ANY;
1385         wol->wolopts = __rtl8169_get_wol(tp);
1386
1387         rtl_unlock_work(tp);
1388 }
1389
1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1391 {
1392         void __iomem *ioaddr = tp->mmio_addr;
1393         unsigned int i;
1394         static const struct {
1395                 u32 opt;
1396                 u16 reg;
1397                 u8  mask;
1398         } cfg[] = {
1399                 { WAKE_ANY,   Config1, PMEnable },
1400                 { WAKE_PHY,   Config3, LinkUp },
1401                 { WAKE_MAGIC, Config3, MagicPacket },
1402                 { WAKE_UCAST, Config5, UWF },
1403                 { WAKE_BCAST, Config5, BWF },
1404                 { WAKE_MCAST, Config5, MWF },
1405                 { WAKE_ANY,   Config5, LanWake }
1406         };
1407
1408         RTL_W8(Cfg9346, Cfg9346_Unlock);
1409
1410         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1411                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1412                 if (wolopts & cfg[i].opt)
1413                         options |= cfg[i].mask;
1414                 RTL_W8(cfg[i].reg, options);
1415         }
1416
1417         RTL_W8(Cfg9346, Cfg9346_Lock);
1418 }
1419
1420 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1421 {
1422         struct rtl8169_private *tp = netdev_priv(dev);
1423
1424         rtl_lock_work(tp);
1425
1426         if (wol->wolopts)
1427                 tp->features |= RTL_FEATURE_WOL;
1428         else
1429                 tp->features &= ~RTL_FEATURE_WOL;
1430         __rtl8169_set_wol(tp, wol->wolopts);
1431
1432         rtl_unlock_work(tp);
1433
1434         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1435
1436         return 0;
1437 }
1438
1439 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1440 {
1441         return rtl_chip_infos[tp->mac_version].fw_name;
1442 }
1443
1444 static void rtl8169_get_drvinfo(struct net_device *dev,
1445                                 struct ethtool_drvinfo *info)
1446 {
1447         struct rtl8169_private *tp = netdev_priv(dev);
1448         struct rtl_fw *rtl_fw = tp->rtl_fw;
1449
1450         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1451         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1452         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1453         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1454         if (!IS_ERR_OR_NULL(rtl_fw))
1455                 strlcpy(info->fw_version, rtl_fw->version,
1456                         sizeof(info->fw_version));
1457 }
1458
1459 static int rtl8169_get_regs_len(struct net_device *dev)
1460 {
1461         return R8169_REGS_SIZE;
1462 }
1463
1464 static int rtl8169_set_speed_tbi(struct net_device *dev,
1465                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468         void __iomem *ioaddr = tp->mmio_addr;
1469         int ret = 0;
1470         u32 reg;
1471
1472         reg = RTL_R32(TBICSR);
1473         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1474             (duplex == DUPLEX_FULL)) {
1475                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1476         } else if (autoneg == AUTONEG_ENABLE)
1477                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1478         else {
1479                 netif_warn(tp, link, dev,
1480                            "incorrect speed setting refused in TBI mode\n");
1481                 ret = -EOPNOTSUPP;
1482         }
1483
1484         return ret;
1485 }
1486
1487 static int rtl8169_set_speed_xmii(struct net_device *dev,
1488                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1489 {
1490         struct rtl8169_private *tp = netdev_priv(dev);
1491         int giga_ctrl, bmcr;
1492         int rc = -EINVAL;
1493
1494         rtl_writephy(tp, 0x1f, 0x0000);
1495
1496         if (autoneg == AUTONEG_ENABLE) {
1497                 int auto_nego;
1498
1499                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1500                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1501                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1502
1503                 if (adv & ADVERTISED_10baseT_Half)
1504                         auto_nego |= ADVERTISE_10HALF;
1505                 if (adv & ADVERTISED_10baseT_Full)
1506                         auto_nego |= ADVERTISE_10FULL;
1507                 if (adv & ADVERTISED_100baseT_Half)
1508                         auto_nego |= ADVERTISE_100HALF;
1509                 if (adv & ADVERTISED_100baseT_Full)
1510                         auto_nego |= ADVERTISE_100FULL;
1511
1512                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1513
1514                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1515                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1516
1517                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1518                 if (tp->mii.supports_gmii) {
1519                         if (adv & ADVERTISED_1000baseT_Half)
1520                                 giga_ctrl |= ADVERTISE_1000HALF;
1521                         if (adv & ADVERTISED_1000baseT_Full)
1522                                 giga_ctrl |= ADVERTISE_1000FULL;
1523                 } else if (adv & (ADVERTISED_1000baseT_Half |
1524                                   ADVERTISED_1000baseT_Full)) {
1525                         netif_info(tp, link, dev,
1526                                    "PHY does not support 1000Mbps\n");
1527                         goto out;
1528                 }
1529
1530                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1531
1532                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1533                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1534         } else {
1535                 giga_ctrl = 0;
1536
1537                 if (speed == SPEED_10)
1538                         bmcr = 0;
1539                 else if (speed == SPEED_100)
1540                         bmcr = BMCR_SPEED100;
1541                 else
1542                         goto out;
1543
1544                 if (duplex == DUPLEX_FULL)
1545                         bmcr |= BMCR_FULLDPLX;
1546         }
1547
1548         rtl_writephy(tp, MII_BMCR, bmcr);
1549
1550         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1551             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1552                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1553                         rtl_writephy(tp, 0x17, 0x2138);
1554                         rtl_writephy(tp, 0x0e, 0x0260);
1555                 } else {
1556                         rtl_writephy(tp, 0x17, 0x2108);
1557                         rtl_writephy(tp, 0x0e, 0x0000);
1558                 }
1559         }
1560
1561         rc = 0;
1562 out:
1563         return rc;
1564 }
1565
1566 static int rtl8169_set_speed(struct net_device *dev,
1567                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1568 {
1569         struct rtl8169_private *tp = netdev_priv(dev);
1570         int ret;
1571
1572         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1573         if (ret < 0)
1574                 goto out;
1575
1576         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1577             (advertising & ADVERTISED_1000baseT_Full)) {
1578                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1579         }
1580 out:
1581         return ret;
1582 }
1583
1584 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1585 {
1586         struct rtl8169_private *tp = netdev_priv(dev);
1587         int ret;
1588
1589         del_timer_sync(&tp->timer);
1590
1591         rtl_lock_work(tp);
1592         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1593                                 cmd->duplex, cmd->advertising);
1594         rtl_unlock_work(tp);
1595
1596         return ret;
1597 }
1598
1599 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1600         netdev_features_t features)
1601 {
1602         struct rtl8169_private *tp = netdev_priv(dev);
1603
1604         if (dev->mtu > TD_MSS_MAX)
1605                 features &= ~NETIF_F_ALL_TSO;
1606
1607         if (dev->mtu > JUMBO_1K &&
1608             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1609                 features &= ~NETIF_F_IP_CSUM;
1610
1611         return features;
1612 }
1613
1614 static void __rtl8169_set_features(struct net_device *dev,
1615                                    netdev_features_t features)
1616 {
1617         struct rtl8169_private *tp = netdev_priv(dev);
1618         netdev_features_t changed = features ^ dev->features;
1619         void __iomem *ioaddr = tp->mmio_addr;
1620
1621         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1622                 return;
1623
1624         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1625                 if (features & NETIF_F_RXCSUM)
1626                         tp->cp_cmd |= RxChkSum;
1627                 else
1628                         tp->cp_cmd &= ~RxChkSum;
1629
1630                 if (dev->features & NETIF_F_HW_VLAN_RX)
1631                         tp->cp_cmd |= RxVlan;
1632                 else
1633                         tp->cp_cmd &= ~RxVlan;
1634
1635                 RTL_W16(CPlusCmd, tp->cp_cmd);
1636                 RTL_R16(CPlusCmd);
1637         }
1638         if (changed & NETIF_F_RXALL) {
1639                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1640                 if (features & NETIF_F_RXALL)
1641                         tmp |= (AcceptErr | AcceptRunt);
1642                 RTL_W32(RxConfig, tmp);
1643         }
1644 }
1645
1646 static int rtl8169_set_features(struct net_device *dev,
1647                                 netdev_features_t features)
1648 {
1649         struct rtl8169_private *tp = netdev_priv(dev);
1650
1651         rtl_lock_work(tp);
1652         __rtl8169_set_features(dev, features);
1653         rtl_unlock_work(tp);
1654
1655         return 0;
1656 }
1657
1658
1659 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1660                                       struct sk_buff *skb)
1661 {
1662         return (vlan_tx_tag_present(skb)) ?
1663                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1664 }
1665
1666 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1667 {
1668         u32 opts2 = le32_to_cpu(desc->opts2);
1669
1670         if (opts2 & RxVlanTag)
1671                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1672
1673         desc->opts2 = 0;
1674 }
1675
1676 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1677 {
1678         struct rtl8169_private *tp = netdev_priv(dev);
1679         void __iomem *ioaddr = tp->mmio_addr;
1680         u32 status;
1681
1682         cmd->supported =
1683                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1684         cmd->port = PORT_FIBRE;
1685         cmd->transceiver = XCVR_INTERNAL;
1686
1687         status = RTL_R32(TBICSR);
1688         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1689         cmd->autoneg = !!(status & TBINwEnable);
1690
1691         ethtool_cmd_speed_set(cmd, SPEED_1000);
1692         cmd->duplex = DUPLEX_FULL; /* Always set */
1693
1694         return 0;
1695 }
1696
1697 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1698 {
1699         struct rtl8169_private *tp = netdev_priv(dev);
1700
1701         return mii_ethtool_gset(&tp->mii, cmd);
1702 }
1703
1704 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1705 {
1706         struct rtl8169_private *tp = netdev_priv(dev);
1707         int rc;
1708
1709         rtl_lock_work(tp);
1710         rc = tp->get_settings(dev, cmd);
1711         rtl_unlock_work(tp);
1712
1713         return rc;
1714 }
1715
1716 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1717                              void *p)
1718 {
1719         struct rtl8169_private *tp = netdev_priv(dev);
1720
1721         if (regs->len > R8169_REGS_SIZE)
1722                 regs->len = R8169_REGS_SIZE;
1723
1724         rtl_lock_work(tp);
1725         memcpy_fromio(p, tp->mmio_addr, regs->len);
1726         rtl_unlock_work(tp);
1727 }
1728
1729 static u32 rtl8169_get_msglevel(struct net_device *dev)
1730 {
1731         struct rtl8169_private *tp = netdev_priv(dev);
1732
1733         return tp->msg_enable;
1734 }
1735
1736 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1737 {
1738         struct rtl8169_private *tp = netdev_priv(dev);
1739
1740         tp->msg_enable = value;
1741 }
1742
1743 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1744         "tx_packets",
1745         "rx_packets",
1746         "tx_errors",
1747         "rx_errors",
1748         "rx_missed",
1749         "align_errors",
1750         "tx_single_collisions",
1751         "tx_multi_collisions",
1752         "unicast",
1753         "broadcast",
1754         "multicast",
1755         "tx_aborted",
1756         "tx_underrun",
1757 };
1758
1759 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1760 {
1761         switch (sset) {
1762         case ETH_SS_STATS:
1763                 return ARRAY_SIZE(rtl8169_gstrings);
1764         default:
1765                 return -EOPNOTSUPP;
1766         }
1767 }
1768
1769 static void rtl8169_update_counters(struct net_device *dev)
1770 {
1771         struct rtl8169_private *tp = netdev_priv(dev);
1772         void __iomem *ioaddr = tp->mmio_addr;
1773         struct device *d = &tp->pci_dev->dev;
1774         struct rtl8169_counters *counters;
1775         dma_addr_t paddr;
1776         u32 cmd;
1777         int wait = 1000;
1778
1779         /*
1780          * Some chips are unable to dump tally counters when the receiver
1781          * is disabled.
1782          */
1783         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1784                 return;
1785
1786         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1787         if (!counters)
1788                 return;
1789
1790         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1791         cmd = (u64)paddr & DMA_BIT_MASK(32);
1792         RTL_W32(CounterAddrLow, cmd);
1793         RTL_W32(CounterAddrLow, cmd | CounterDump);
1794
1795         while (wait--) {
1796                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1797                         memcpy(&tp->counters, counters, sizeof(*counters));
1798                         break;
1799                 }
1800                 udelay(10);
1801         }
1802
1803         RTL_W32(CounterAddrLow, 0);
1804         RTL_W32(CounterAddrHigh, 0);
1805
1806         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1807 }
1808
1809 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1810                                       struct ethtool_stats *stats, u64 *data)
1811 {
1812         struct rtl8169_private *tp = netdev_priv(dev);
1813
1814         ASSERT_RTNL();
1815
1816         rtl8169_update_counters(dev);
1817
1818         data[0] = le64_to_cpu(tp->counters.tx_packets);
1819         data[1] = le64_to_cpu(tp->counters.rx_packets);
1820         data[2] = le64_to_cpu(tp->counters.tx_errors);
1821         data[3] = le32_to_cpu(tp->counters.rx_errors);
1822         data[4] = le16_to_cpu(tp->counters.rx_missed);
1823         data[5] = le16_to_cpu(tp->counters.align_errors);
1824         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1825         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1826         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1827         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1828         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1829         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1830         data[12] = le16_to_cpu(tp->counters.tx_underun);
1831 }
1832
1833 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1834 {
1835         switch(stringset) {
1836         case ETH_SS_STATS:
1837                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1838                 break;
1839         }
1840 }
1841
1842 static const struct ethtool_ops rtl8169_ethtool_ops = {
1843         .get_drvinfo            = rtl8169_get_drvinfo,
1844         .get_regs_len           = rtl8169_get_regs_len,
1845         .get_link               = ethtool_op_get_link,
1846         .get_settings           = rtl8169_get_settings,
1847         .set_settings           = rtl8169_set_settings,
1848         .get_msglevel           = rtl8169_get_msglevel,
1849         .set_msglevel           = rtl8169_set_msglevel,
1850         .get_regs               = rtl8169_get_regs,
1851         .get_wol                = rtl8169_get_wol,
1852         .set_wol                = rtl8169_set_wol,
1853         .get_strings            = rtl8169_get_strings,
1854         .get_sset_count         = rtl8169_get_sset_count,
1855         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1856 };
1857
1858 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1859                                     struct net_device *dev, u8 default_version)
1860 {
1861         void __iomem *ioaddr = tp->mmio_addr;
1862         /*
1863          * The driver currently handles the 8168Bf and the 8168Be identically
1864          * but they can be identified more specifically through the test below
1865          * if needed:
1866          *
1867          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1868          *
1869          * Same thing for the 8101Eb and the 8101Ec:
1870          *
1871          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1872          */
1873         static const struct rtl_mac_info {
1874                 u32 mask;
1875                 u32 val;
1876                 int mac_version;
1877         } mac_info[] = {
1878                 /* 8168F family. */
1879                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1880                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1881
1882                 /* 8168E family. */
1883                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1884                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1885                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1886                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1887
1888                 /* 8168D family. */
1889                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1890                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1891                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1892
1893                 /* 8168DP family. */
1894                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1895                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1896                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1897
1898                 /* 8168C family. */
1899                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1900                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1901                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1902                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1903                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1904                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1905                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1906                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1907                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1908
1909                 /* 8168B family. */
1910                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1911                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1912                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1913                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1914
1915                 /* 8101 family. */
1916                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1917                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1918                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1919                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1920                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1921                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1922                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1923                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1924                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1925                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1926                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1927                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1928                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1929                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1930                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1931                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1932                 /* FIXME: where did these entries come from ? -- FR */
1933                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1934                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1935
1936                 /* 8110 family. */
1937                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1938                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1939                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1940                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1941                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1942                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1943
1944                 /* Catch-all */
1945                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1946         };
1947         const struct rtl_mac_info *p = mac_info;
1948         u32 reg;
1949
1950         reg = RTL_R32(TxConfig);
1951         while ((reg & p->mask) != p->val)
1952                 p++;
1953         tp->mac_version = p->mac_version;
1954
1955         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1956                 netif_notice(tp, probe, dev,
1957                              "unknown MAC, using family default\n");
1958                 tp->mac_version = default_version;
1959         }
1960 }
1961
1962 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1963 {
1964         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1965 }
1966
1967 struct phy_reg {
1968         u16 reg;
1969         u16 val;
1970 };
1971
1972 static void rtl_writephy_batch(struct rtl8169_private *tp,
1973                                const struct phy_reg *regs, int len)
1974 {
1975         while (len-- > 0) {
1976                 rtl_writephy(tp, regs->reg, regs->val);
1977                 regs++;
1978         }
1979 }
1980
1981 #define PHY_READ                0x00000000
1982 #define PHY_DATA_OR             0x10000000
1983 #define PHY_DATA_AND            0x20000000
1984 #define PHY_BJMPN               0x30000000
1985 #define PHY_READ_EFUSE          0x40000000
1986 #define PHY_READ_MAC_BYTE       0x50000000
1987 #define PHY_WRITE_MAC_BYTE      0x60000000
1988 #define PHY_CLEAR_READCOUNT     0x70000000
1989 #define PHY_WRITE               0x80000000
1990 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1991 #define PHY_COMP_EQ_SKIPN       0xa0000000
1992 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1993 #define PHY_WRITE_PREVIOUS      0xc0000000
1994 #define PHY_SKIPN               0xd0000000
1995 #define PHY_DELAY_MS            0xe0000000
1996 #define PHY_WRITE_ERI_WORD      0xf0000000
1997
1998 struct fw_info {
1999         u32     magic;
2000         char    version[RTL_VER_SIZE];
2001         __le32  fw_start;
2002         __le32  fw_len;
2003         u8      chksum;
2004 } __packed;
2005
2006 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2007
2008 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2009 {
2010         const struct firmware *fw = rtl_fw->fw;
2011         struct fw_info *fw_info = (struct fw_info *)fw->data;
2012         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2013         char *version = rtl_fw->version;
2014         bool rc = false;
2015
2016         if (fw->size < FW_OPCODE_SIZE)
2017                 goto out;
2018
2019         if (!fw_info->magic) {
2020                 size_t i, size, start;
2021                 u8 checksum = 0;
2022
2023                 if (fw->size < sizeof(*fw_info))
2024                         goto out;
2025
2026                 for (i = 0; i < fw->size; i++)
2027                         checksum += fw->data[i];
2028                 if (checksum != 0)
2029                         goto out;
2030
2031                 start = le32_to_cpu(fw_info->fw_start);
2032                 if (start > fw->size)
2033                         goto out;
2034
2035                 size = le32_to_cpu(fw_info->fw_len);
2036                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2037                         goto out;
2038
2039                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2040
2041                 pa->code = (__le32 *)(fw->data + start);
2042                 pa->size = size;
2043         } else {
2044                 if (fw->size % FW_OPCODE_SIZE)
2045                         goto out;
2046
2047                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2048
2049                 pa->code = (__le32 *)fw->data;
2050                 pa->size = fw->size / FW_OPCODE_SIZE;
2051         }
2052         version[RTL_VER_SIZE - 1] = 0;
2053
2054         rc = true;
2055 out:
2056         return rc;
2057 }
2058
2059 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2060                            struct rtl_fw_phy_action *pa)
2061 {
2062         bool rc = false;
2063         size_t index;
2064
2065         for (index = 0; index < pa->size; index++) {
2066                 u32 action = le32_to_cpu(pa->code[index]);
2067                 u32 regno = (action & 0x0fff0000) >> 16;
2068
2069                 switch(action & 0xf0000000) {
2070                 case PHY_READ:
2071                 case PHY_DATA_OR:
2072                 case PHY_DATA_AND:
2073                 case PHY_READ_EFUSE:
2074                 case PHY_CLEAR_READCOUNT:
2075                 case PHY_WRITE:
2076                 case PHY_WRITE_PREVIOUS:
2077                 case PHY_DELAY_MS:
2078                         break;
2079
2080                 case PHY_BJMPN:
2081                         if (regno > index) {
2082                                 netif_err(tp, ifup, tp->dev,
2083                                           "Out of range of firmware\n");
2084                                 goto out;
2085                         }
2086                         break;
2087                 case PHY_READCOUNT_EQ_SKIP:
2088                         if (index + 2 >= pa->size) {
2089                                 netif_err(tp, ifup, tp->dev,
2090                                           "Out of range of firmware\n");
2091                                 goto out;
2092                         }
2093                         break;
2094                 case PHY_COMP_EQ_SKIPN:
2095                 case PHY_COMP_NEQ_SKIPN:
2096                 case PHY_SKIPN:
2097                         if (index + 1 + regno >= pa->size) {
2098                                 netif_err(tp, ifup, tp->dev,
2099                                           "Out of range of firmware\n");
2100                                 goto out;
2101                         }
2102                         break;
2103
2104                 case PHY_READ_MAC_BYTE:
2105                 case PHY_WRITE_MAC_BYTE:
2106                 case PHY_WRITE_ERI_WORD:
2107                 default:
2108                         netif_err(tp, ifup, tp->dev,
2109                                   "Invalid action 0x%08x\n", action);
2110                         goto out;
2111                 }
2112         }
2113         rc = true;
2114 out:
2115         return rc;
2116 }
2117
2118 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2119 {
2120         struct net_device *dev = tp->dev;
2121         int rc = -EINVAL;
2122
2123         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2124                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2125                 goto out;
2126         }
2127
2128         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2129                 rc = 0;
2130 out:
2131         return rc;
2132 }
2133
2134 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2135 {
2136         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2137         u32 predata, count;
2138         size_t index;
2139
2140         predata = count = 0;
2141
2142         for (index = 0; index < pa->size; ) {
2143                 u32 action = le32_to_cpu(pa->code[index]);
2144                 u32 data = action & 0x0000ffff;
2145                 u32 regno = (action & 0x0fff0000) >> 16;
2146
2147                 if (!action)
2148                         break;
2149
2150                 switch(action & 0xf0000000) {
2151                 case PHY_READ:
2152                         predata = rtl_readphy(tp, regno);
2153                         count++;
2154                         index++;
2155                         break;
2156                 case PHY_DATA_OR:
2157                         predata |= data;
2158                         index++;
2159                         break;
2160                 case PHY_DATA_AND:
2161                         predata &= data;
2162                         index++;
2163                         break;
2164                 case PHY_BJMPN:
2165                         index -= regno;
2166                         break;
2167                 case PHY_READ_EFUSE:
2168                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2169                         index++;
2170                         break;
2171                 case PHY_CLEAR_READCOUNT:
2172                         count = 0;
2173                         index++;
2174                         break;
2175                 case PHY_WRITE:
2176                         rtl_writephy(tp, regno, data);
2177                         index++;
2178                         break;
2179                 case PHY_READCOUNT_EQ_SKIP:
2180                         index += (count == data) ? 2 : 1;
2181                         break;
2182                 case PHY_COMP_EQ_SKIPN:
2183                         if (predata == data)
2184                                 index += regno;
2185                         index++;
2186                         break;
2187                 case PHY_COMP_NEQ_SKIPN:
2188                         if (predata != data)
2189                                 index += regno;
2190                         index++;
2191                         break;
2192                 case PHY_WRITE_PREVIOUS:
2193                         rtl_writephy(tp, regno, predata);
2194                         index++;
2195                         break;
2196                 case PHY_SKIPN:
2197                         index += regno + 1;
2198                         break;
2199                 case PHY_DELAY_MS:
2200                         mdelay(data);
2201                         index++;
2202                         break;
2203
2204                 case PHY_READ_MAC_BYTE:
2205                 case PHY_WRITE_MAC_BYTE:
2206                 case PHY_WRITE_ERI_WORD:
2207                 default:
2208                         BUG();
2209                 }
2210         }
2211 }
2212
2213 static void rtl_release_firmware(struct rtl8169_private *tp)
2214 {
2215         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2216                 release_firmware(tp->rtl_fw->fw);
2217                 kfree(tp->rtl_fw);
2218         }
2219         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2220 }
2221
2222 static void rtl_apply_firmware(struct rtl8169_private *tp)
2223 {
2224         struct rtl_fw *rtl_fw = tp->rtl_fw;
2225
2226         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2227         if (!IS_ERR_OR_NULL(rtl_fw))
2228                 rtl_phy_write_fw(tp, rtl_fw);
2229 }
2230
2231 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2232 {
2233         if (rtl_readphy(tp, reg) != val)
2234                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2235         else
2236                 rtl_apply_firmware(tp);
2237 }
2238
2239 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2240 {
2241         static const struct phy_reg phy_reg_init[] = {
2242                 { 0x1f, 0x0001 },
2243                 { 0x06, 0x006e },
2244                 { 0x08, 0x0708 },
2245                 { 0x15, 0x4000 },
2246                 { 0x18, 0x65c7 },
2247
2248                 { 0x1f, 0x0001 },
2249                 { 0x03, 0x00a1 },
2250                 { 0x02, 0x0008 },
2251                 { 0x01, 0x0120 },
2252                 { 0x00, 0x1000 },
2253                 { 0x04, 0x0800 },
2254                 { 0x04, 0x0000 },
2255
2256                 { 0x03, 0xff41 },
2257                 { 0x02, 0xdf60 },
2258                 { 0x01, 0x0140 },
2259                 { 0x00, 0x0077 },
2260                 { 0x04, 0x7800 },
2261                 { 0x04, 0x7000 },
2262
2263                 { 0x03, 0x802f },
2264                 { 0x02, 0x4f02 },
2265                 { 0x01, 0x0409 },
2266                 { 0x00, 0xf0f9 },
2267                 { 0x04, 0x9800 },
2268                 { 0x04, 0x9000 },
2269
2270                 { 0x03, 0xdf01 },
2271                 { 0x02, 0xdf20 },
2272                 { 0x01, 0xff95 },
2273                 { 0x00, 0xba00 },
2274                 { 0x04, 0xa800 },
2275                 { 0x04, 0xa000 },
2276
2277                 { 0x03, 0xff41 },
2278                 { 0x02, 0xdf20 },
2279                 { 0x01, 0x0140 },
2280                 { 0x00, 0x00bb },
2281                 { 0x04, 0xb800 },
2282                 { 0x04, 0xb000 },
2283
2284                 { 0x03, 0xdf41 },
2285                 { 0x02, 0xdc60 },
2286                 { 0x01, 0x6340 },
2287                 { 0x00, 0x007d },
2288                 { 0x04, 0xd800 },
2289                 { 0x04, 0xd000 },
2290
2291                 { 0x03, 0xdf01 },
2292                 { 0x02, 0xdf20 },
2293                 { 0x01, 0x100a },
2294                 { 0x00, 0xa0ff },
2295                 { 0x04, 0xf800 },
2296                 { 0x04, 0xf000 },
2297
2298                 { 0x1f, 0x0000 },
2299                 { 0x0b, 0x0000 },
2300                 { 0x00, 0x9200 }
2301         };
2302
2303         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2304 }
2305
2306 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2307 {
2308         static const struct phy_reg phy_reg_init[] = {
2309                 { 0x1f, 0x0002 },
2310                 { 0x01, 0x90d0 },
2311                 { 0x1f, 0x0000 }
2312         };
2313
2314         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315 }
2316
2317 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2318 {
2319         struct pci_dev *pdev = tp->pci_dev;
2320
2321         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2322             (pdev->subsystem_device != 0xe000))
2323                 return;
2324
2325         rtl_writephy(tp, 0x1f, 0x0001);
2326         rtl_writephy(tp, 0x10, 0xf01b);
2327         rtl_writephy(tp, 0x1f, 0x0000);
2328 }
2329
2330 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2331 {
2332         static const struct phy_reg phy_reg_init[] = {
2333                 { 0x1f, 0x0001 },
2334                 { 0x04, 0x0000 },
2335                 { 0x03, 0x00a1 },
2336                 { 0x02, 0x0008 },
2337                 { 0x01, 0x0120 },
2338                 { 0x00, 0x1000 },
2339                 { 0x04, 0x0800 },
2340                 { 0x04, 0x9000 },
2341                 { 0x03, 0x802f },
2342                 { 0x02, 0x4f02 },
2343                 { 0x01, 0x0409 },
2344                 { 0x00, 0xf099 },
2345                 { 0x04, 0x9800 },
2346                 { 0x04, 0xa000 },
2347                 { 0x03, 0xdf01 },
2348                 { 0x02, 0xdf20 },
2349                 { 0x01, 0xff95 },
2350                 { 0x00, 0xba00 },
2351                 { 0x04, 0xa800 },
2352                 { 0x04, 0xf000 },
2353                 { 0x03, 0xdf01 },
2354                 { 0x02, 0xdf20 },
2355                 { 0x01, 0x101a },
2356                 { 0x00, 0xa0ff },
2357                 { 0x04, 0xf800 },
2358                 { 0x04, 0x0000 },
2359                 { 0x1f, 0x0000 },
2360
2361                 { 0x1f, 0x0001 },
2362                 { 0x10, 0xf41b },
2363                 { 0x14, 0xfb54 },
2364                 { 0x18, 0xf5c7 },
2365                 { 0x1f, 0x0000 },
2366
2367                 { 0x1f, 0x0001 },
2368                 { 0x17, 0x0cc0 },
2369                 { 0x1f, 0x0000 }
2370         };
2371
2372         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2373
2374         rtl8169scd_hw_phy_config_quirk(tp);
2375 }
2376
2377 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2378 {
2379         static const struct phy_reg phy_reg_init[] = {
2380                 { 0x1f, 0x0001 },
2381                 { 0x04, 0x0000 },
2382                 { 0x03, 0x00a1 },
2383                 { 0x02, 0x0008 },
2384                 { 0x01, 0x0120 },
2385                 { 0x00, 0x1000 },
2386                 { 0x04, 0x0800 },
2387                 { 0x04, 0x9000 },
2388                 { 0x03, 0x802f },
2389                 { 0x02, 0x4f02 },
2390                 { 0x01, 0x0409 },
2391                 { 0x00, 0xf099 },
2392                 { 0x04, 0x9800 },
2393                 { 0x04, 0xa000 },
2394                 { 0x03, 0xdf01 },
2395                 { 0x02, 0xdf20 },
2396                 { 0x01, 0xff95 },
2397                 { 0x00, 0xba00 },
2398                 { 0x04, 0xa800 },
2399                 { 0x04, 0xf000 },
2400                 { 0x03, 0xdf01 },
2401                 { 0x02, 0xdf20 },
2402                 { 0x01, 0x101a },
2403                 { 0x00, 0xa0ff },
2404                 { 0x04, 0xf800 },
2405                 { 0x04, 0x0000 },
2406                 { 0x1f, 0x0000 },
2407
2408                 { 0x1f, 0x0001 },
2409                 { 0x0b, 0x8480 },
2410                 { 0x1f, 0x0000 },
2411
2412                 { 0x1f, 0x0001 },
2413                 { 0x18, 0x67c7 },
2414                 { 0x04, 0x2000 },
2415                 { 0x03, 0x002f },
2416                 { 0x02, 0x4360 },
2417                 { 0x01, 0x0109 },
2418                 { 0x00, 0x3022 },
2419                 { 0x04, 0x2800 },
2420                 { 0x1f, 0x0000 },
2421
2422                 { 0x1f, 0x0001 },
2423                 { 0x17, 0x0cc0 },
2424                 { 0x1f, 0x0000 }
2425         };
2426
2427         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2428 }
2429
2430 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2431 {
2432         static const struct phy_reg phy_reg_init[] = {
2433                 { 0x10, 0xf41b },
2434                 { 0x1f, 0x0000 }
2435         };
2436
2437         rtl_writephy(tp, 0x1f, 0x0001);
2438         rtl_patchphy(tp, 0x16, 1 << 0);
2439
2440         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2441 }
2442
2443 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2444 {
2445         static const struct phy_reg phy_reg_init[] = {
2446                 { 0x1f, 0x0001 },
2447                 { 0x10, 0xf41b },
2448                 { 0x1f, 0x0000 }
2449         };
2450
2451         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2452 }
2453
2454 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2455 {
2456         static const struct phy_reg phy_reg_init[] = {
2457                 { 0x1f, 0x0000 },
2458                 { 0x1d, 0x0f00 },
2459                 { 0x1f, 0x0002 },
2460                 { 0x0c, 0x1ec8 },
2461                 { 0x1f, 0x0000 }
2462         };
2463
2464         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2465 }
2466
2467 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2468 {
2469         static const struct phy_reg phy_reg_init[] = {
2470                 { 0x1f, 0x0001 },
2471                 { 0x1d, 0x3d98 },
2472                 { 0x1f, 0x0000 }
2473         };
2474
2475         rtl_writephy(tp, 0x1f, 0x0000);
2476         rtl_patchphy(tp, 0x14, 1 << 5);
2477         rtl_patchphy(tp, 0x0d, 1 << 5);
2478
2479         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2480 }
2481
2482 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2483 {
2484         static const struct phy_reg phy_reg_init[] = {
2485                 { 0x1f, 0x0001 },
2486                 { 0x12, 0x2300 },
2487                 { 0x1f, 0x0002 },
2488                 { 0x00, 0x88d4 },
2489                 { 0x01, 0x82b1 },
2490                 { 0x03, 0x7002 },
2491                 { 0x08, 0x9e30 },
2492                 { 0x09, 0x01f0 },
2493                 { 0x0a, 0x5500 },
2494                 { 0x0c, 0x00c8 },
2495                 { 0x1f, 0x0003 },
2496                 { 0x12, 0xc096 },
2497                 { 0x16, 0x000a },
2498                 { 0x1f, 0x0000 },
2499                 { 0x1f, 0x0000 },
2500                 { 0x09, 0x2000 },
2501                 { 0x09, 0x0000 }
2502         };
2503
2504         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2505
2506         rtl_patchphy(tp, 0x14, 1 << 5);
2507         rtl_patchphy(tp, 0x0d, 1 << 5);
2508         rtl_writephy(tp, 0x1f, 0x0000);
2509 }
2510
2511 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2512 {
2513         static const struct phy_reg phy_reg_init[] = {
2514                 { 0x1f, 0x0001 },
2515                 { 0x12, 0x2300 },
2516                 { 0x03, 0x802f },
2517                 { 0x02, 0x4f02 },
2518                 { 0x01, 0x0409 },
2519                 { 0x00, 0xf099 },
2520                 { 0x04, 0x9800 },
2521                 { 0x04, 0x9000 },
2522                 { 0x1d, 0x3d98 },
2523                 { 0x1f, 0x0002 },
2524                 { 0x0c, 0x7eb8 },
2525                 { 0x06, 0x0761 },
2526                 { 0x1f, 0x0003 },
2527                 { 0x16, 0x0f0a },
2528                 { 0x1f, 0x0000 }
2529         };
2530
2531         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2532
2533         rtl_patchphy(tp, 0x16, 1 << 0);
2534         rtl_patchphy(tp, 0x14, 1 << 5);
2535         rtl_patchphy(tp, 0x0d, 1 << 5);
2536         rtl_writephy(tp, 0x1f, 0x0000);
2537 }
2538
2539 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2540 {
2541         static const struct phy_reg phy_reg_init[] = {
2542                 { 0x1f, 0x0001 },
2543                 { 0x12, 0x2300 },
2544                 { 0x1d, 0x3d98 },
2545                 { 0x1f, 0x0002 },
2546                 { 0x0c, 0x7eb8 },
2547                 { 0x06, 0x5461 },
2548                 { 0x1f, 0x0003 },
2549                 { 0x16, 0x0f0a },
2550                 { 0x1f, 0x0000 }
2551         };
2552
2553         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2554
2555         rtl_patchphy(tp, 0x16, 1 << 0);
2556         rtl_patchphy(tp, 0x14, 1 << 5);
2557         rtl_patchphy(tp, 0x0d, 1 << 5);
2558         rtl_writephy(tp, 0x1f, 0x0000);
2559 }
2560
2561 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2562 {
2563         rtl8168c_3_hw_phy_config(tp);
2564 }
2565
2566 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2567 {
2568         static const struct phy_reg phy_reg_init_0[] = {
2569                 /* Channel Estimation */
2570                 { 0x1f, 0x0001 },
2571                 { 0x06, 0x4064 },
2572                 { 0x07, 0x2863 },
2573                 { 0x08, 0x059c },
2574                 { 0x09, 0x26b4 },
2575                 { 0x0a, 0x6a19 },
2576                 { 0x0b, 0xdcc8 },
2577                 { 0x10, 0xf06d },
2578                 { 0x14, 0x7f68 },
2579                 { 0x18, 0x7fd9 },
2580                 { 0x1c, 0xf0ff },
2581                 { 0x1d, 0x3d9c },
2582                 { 0x1f, 0x0003 },
2583                 { 0x12, 0xf49f },
2584                 { 0x13, 0x070b },
2585                 { 0x1a, 0x05ad },
2586                 { 0x14, 0x94c0 },
2587
2588                 /*
2589                  * Tx Error Issue
2590                  * Enhance line driver power
2591                  */
2592                 { 0x1f, 0x0002 },
2593                 { 0x06, 0x5561 },
2594                 { 0x1f, 0x0005 },
2595                 { 0x05, 0x8332 },
2596                 { 0x06, 0x5561 },
2597
2598                 /*
2599                  * Can not link to 1Gbps with bad cable
2600                  * Decrease SNR threshold form 21.07dB to 19.04dB
2601                  */
2602                 { 0x1f, 0x0001 },
2603                 { 0x17, 0x0cc0 },
2604
2605                 { 0x1f, 0x0000 },
2606                 { 0x0d, 0xf880 }
2607         };
2608         void __iomem *ioaddr = tp->mmio_addr;
2609
2610         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2611
2612         /*
2613          * Rx Error Issue
2614          * Fine Tune Switching regulator parameter
2615          */
2616         rtl_writephy(tp, 0x1f, 0x0002);
2617         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2618         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2619
2620         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2621                 static const struct phy_reg phy_reg_init[] = {
2622                         { 0x1f, 0x0002 },
2623                         { 0x05, 0x669a },
2624                         { 0x1f, 0x0005 },
2625                         { 0x05, 0x8330 },
2626                         { 0x06, 0x669a },
2627                         { 0x1f, 0x0002 }
2628                 };
2629                 int val;
2630
2631                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2632
2633                 val = rtl_readphy(tp, 0x0d);
2634
2635                 if ((val & 0x00ff) != 0x006c) {
2636                         static const u32 set[] = {
2637                                 0x0065, 0x0066, 0x0067, 0x0068,
2638                                 0x0069, 0x006a, 0x006b, 0x006c
2639                         };
2640                         int i;
2641
2642                         rtl_writephy(tp, 0x1f, 0x0002);
2643
2644                         val &= 0xff00;
2645                         for (i = 0; i < ARRAY_SIZE(set); i++)
2646                                 rtl_writephy(tp, 0x0d, val | set[i]);
2647                 }
2648         } else {
2649                 static const struct phy_reg phy_reg_init[] = {
2650                         { 0x1f, 0x0002 },
2651                         { 0x05, 0x6662 },
2652                         { 0x1f, 0x0005 },
2653                         { 0x05, 0x8330 },
2654                         { 0x06, 0x6662 }
2655                 };
2656
2657                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2658         }
2659
2660         /* RSET couple improve */
2661         rtl_writephy(tp, 0x1f, 0x0002);
2662         rtl_patchphy(tp, 0x0d, 0x0300);
2663         rtl_patchphy(tp, 0x0f, 0x0010);
2664
2665         /* Fine tune PLL performance */
2666         rtl_writephy(tp, 0x1f, 0x0002);
2667         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2668         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2669
2670         rtl_writephy(tp, 0x1f, 0x0005);
2671         rtl_writephy(tp, 0x05, 0x001b);
2672
2673         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2674
2675         rtl_writephy(tp, 0x1f, 0x0000);
2676 }
2677
2678 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2679 {
2680         static const struct phy_reg phy_reg_init_0[] = {
2681                 /* Channel Estimation */
2682                 { 0x1f, 0x0001 },
2683                 { 0x06, 0x4064 },
2684                 { 0x07, 0x2863 },
2685                 { 0x08, 0x059c },
2686                 { 0x09, 0x26b4 },
2687                 { 0x0a, 0x6a19 },
2688                 { 0x0b, 0xdcc8 },
2689                 { 0x10, 0xf06d },
2690                 { 0x14, 0x7f68 },
2691                 { 0x18, 0x7fd9 },
2692                 { 0x1c, 0xf0ff },
2693                 { 0x1d, 0x3d9c },
2694                 { 0x1f, 0x0003 },
2695                 { 0x12, 0xf49f },
2696                 { 0x13, 0x070b },
2697                 { 0x1a, 0x05ad },
2698                 { 0x14, 0x94c0 },
2699
2700                 /*
2701                  * Tx Error Issue
2702                  * Enhance line driver power
2703                  */
2704                 { 0x1f, 0x0002 },
2705                 { 0x06, 0x5561 },
2706                 { 0x1f, 0x0005 },
2707                 { 0x05, 0x8332 },
2708                 { 0x06, 0x5561 },
2709
2710                 /*
2711                  * Can not link to 1Gbps with bad cable
2712                  * Decrease SNR threshold form 21.07dB to 19.04dB
2713                  */
2714                 { 0x1f, 0x0001 },
2715                 { 0x17, 0x0cc0 },
2716
2717                 { 0x1f, 0x0000 },
2718                 { 0x0d, 0xf880 }
2719         };
2720         void __iomem *ioaddr = tp->mmio_addr;
2721
2722         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2723
2724         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2725                 static const struct phy_reg phy_reg_init[] = {
2726                         { 0x1f, 0x0002 },
2727                         { 0x05, 0x669a },
2728                         { 0x1f, 0x0005 },
2729                         { 0x05, 0x8330 },
2730                         { 0x06, 0x669a },
2731
2732                         { 0x1f, 0x0002 }
2733                 };
2734                 int val;
2735
2736                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2737
2738                 val = rtl_readphy(tp, 0x0d);
2739                 if ((val & 0x00ff) != 0x006c) {
2740                         static const u32 set[] = {
2741                                 0x0065, 0x0066, 0x0067, 0x0068,
2742                                 0x0069, 0x006a, 0x006b, 0x006c
2743                         };
2744                         int i;
2745
2746                         rtl_writephy(tp, 0x1f, 0x0002);
2747
2748                         val &= 0xff00;
2749                         for (i = 0; i < ARRAY_SIZE(set); i++)
2750                                 rtl_writephy(tp, 0x0d, val | set[i]);
2751                 }
2752         } else {
2753                 static const struct phy_reg phy_reg_init[] = {
2754                         { 0x1f, 0x0002 },
2755                         { 0x05, 0x2642 },
2756                         { 0x1f, 0x0005 },
2757                         { 0x05, 0x8330 },
2758                         { 0x06, 0x2642 }
2759                 };
2760
2761                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2762         }
2763
2764         /* Fine tune PLL performance */
2765         rtl_writephy(tp, 0x1f, 0x0002);
2766         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2767         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2768
2769         /* Switching regulator Slew rate */
2770         rtl_writephy(tp, 0x1f, 0x0002);
2771         rtl_patchphy(tp, 0x0f, 0x0017);
2772
2773         rtl_writephy(tp, 0x1f, 0x0005);
2774         rtl_writephy(tp, 0x05, 0x001b);
2775
2776         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2777
2778         rtl_writephy(tp, 0x1f, 0x0000);
2779 }
2780
2781 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2782 {
2783         static const struct phy_reg phy_reg_init[] = {
2784                 { 0x1f, 0x0002 },
2785                 { 0x10, 0x0008 },
2786                 { 0x0d, 0x006c },
2787
2788                 { 0x1f, 0x0000 },
2789                 { 0x0d, 0xf880 },
2790
2791                 { 0x1f, 0x0001 },
2792                 { 0x17, 0x0cc0 },
2793
2794                 { 0x1f, 0x0001 },
2795                 { 0x0b, 0xa4d8 },
2796                 { 0x09, 0x281c },
2797                 { 0x07, 0x2883 },
2798                 { 0x0a, 0x6b35 },
2799                 { 0x1d, 0x3da4 },
2800                 { 0x1c, 0xeffd },
2801                 { 0x14, 0x7f52 },
2802                 { 0x18, 0x7fc6 },
2803                 { 0x08, 0x0601 },
2804                 { 0x06, 0x4063 },
2805                 { 0x10, 0xf074 },
2806                 { 0x1f, 0x0003 },
2807                 { 0x13, 0x0789 },
2808                 { 0x12, 0xf4bd },
2809                 { 0x1a, 0x04fd },
2810                 { 0x14, 0x84b0 },
2811                 { 0x1f, 0x0000 },
2812                 { 0x00, 0x9200 },
2813
2814                 { 0x1f, 0x0005 },
2815                 { 0x01, 0x0340 },
2816                 { 0x1f, 0x0001 },
2817                 { 0x04, 0x4000 },
2818                 { 0x03, 0x1d21 },
2819                 { 0x02, 0x0c32 },
2820                 { 0x01, 0x0200 },
2821                 { 0x00, 0x5554 },
2822                 { 0x04, 0x4800 },
2823                 { 0x04, 0x4000 },
2824                 { 0x04, 0xf000 },
2825                 { 0x03, 0xdf01 },
2826                 { 0x02, 0xdf20 },
2827                 { 0x01, 0x101a },
2828                 { 0x00, 0xa0ff },
2829                 { 0x04, 0xf800 },
2830                 { 0x04, 0xf000 },
2831                 { 0x1f, 0x0000 },
2832
2833                 { 0x1f, 0x0007 },
2834                 { 0x1e, 0x0023 },
2835                 { 0x16, 0x0000 },
2836                 { 0x1f, 0x0000 }
2837         };
2838
2839         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2840 }
2841
2842 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2843 {
2844         static const struct phy_reg phy_reg_init[] = {
2845                 { 0x1f, 0x0001 },
2846                 { 0x17, 0x0cc0 },
2847
2848                 { 0x1f, 0x0007 },
2849                 { 0x1e, 0x002d },
2850                 { 0x18, 0x0040 },
2851                 { 0x1f, 0x0000 }
2852         };
2853
2854         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2855         rtl_patchphy(tp, 0x0d, 1 << 5);
2856 }
2857
2858 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2859 {
2860         static const struct phy_reg phy_reg_init[] = {
2861                 /* Enable Delay cap */
2862                 { 0x1f, 0x0005 },
2863                 { 0x05, 0x8b80 },
2864                 { 0x06, 0xc896 },
2865                 { 0x1f, 0x0000 },
2866
2867                 /* Channel estimation fine tune */
2868                 { 0x1f, 0x0001 },
2869                 { 0x0b, 0x6c20 },
2870                 { 0x07, 0x2872 },
2871                 { 0x1c, 0xefff },
2872                 { 0x1f, 0x0003 },
2873                 { 0x14, 0x6420 },
2874                 { 0x1f, 0x0000 },
2875
2876                 /* Update PFM & 10M TX idle timer */
2877                 { 0x1f, 0x0007 },
2878                 { 0x1e, 0x002f },
2879                 { 0x15, 0x1919 },
2880                 { 0x1f, 0x0000 },
2881
2882                 { 0x1f, 0x0007 },
2883                 { 0x1e, 0x00ac },
2884                 { 0x18, 0x0006 },
2885                 { 0x1f, 0x0000 }
2886         };
2887
2888         rtl_apply_firmware(tp);
2889
2890         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2891
2892         /* DCO enable for 10M IDLE Power */
2893         rtl_writephy(tp, 0x1f, 0x0007);
2894         rtl_writephy(tp, 0x1e, 0x0023);
2895         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2896         rtl_writephy(tp, 0x1f, 0x0000);
2897
2898         /* For impedance matching */
2899         rtl_writephy(tp, 0x1f, 0x0002);
2900         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2901         rtl_writephy(tp, 0x1f, 0x0000);
2902
2903         /* PHY auto speed down */
2904         rtl_writephy(tp, 0x1f, 0x0007);
2905         rtl_writephy(tp, 0x1e, 0x002d);
2906         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2907         rtl_writephy(tp, 0x1f, 0x0000);
2908         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2909
2910         rtl_writephy(tp, 0x1f, 0x0005);
2911         rtl_writephy(tp, 0x05, 0x8b86);
2912         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2913         rtl_writephy(tp, 0x1f, 0x0000);
2914
2915         rtl_writephy(tp, 0x1f, 0x0005);
2916         rtl_writephy(tp, 0x05, 0x8b85);
2917         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2918         rtl_writephy(tp, 0x1f, 0x0007);
2919         rtl_writephy(tp, 0x1e, 0x0020);
2920         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2921         rtl_writephy(tp, 0x1f, 0x0006);
2922         rtl_writephy(tp, 0x00, 0x5a00);
2923         rtl_writephy(tp, 0x1f, 0x0000);
2924         rtl_writephy(tp, 0x0d, 0x0007);
2925         rtl_writephy(tp, 0x0e, 0x003c);
2926         rtl_writephy(tp, 0x0d, 0x4007);
2927         rtl_writephy(tp, 0x0e, 0x0000);
2928         rtl_writephy(tp, 0x0d, 0x0000);
2929 }
2930
2931 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2932 {
2933         static const struct phy_reg phy_reg_init[] = {
2934                 /* Enable Delay cap */
2935                 { 0x1f, 0x0004 },
2936                 { 0x1f, 0x0007 },
2937                 { 0x1e, 0x00ac },
2938                 { 0x18, 0x0006 },
2939                 { 0x1f, 0x0002 },
2940                 { 0x1f, 0x0000 },
2941                 { 0x1f, 0x0000 },
2942
2943                 /* Channel estimation fine tune */
2944                 { 0x1f, 0x0003 },
2945                 { 0x09, 0xa20f },
2946                 { 0x1f, 0x0000 },
2947                 { 0x1f, 0x0000 },
2948
2949                 /* Green Setting */
2950                 { 0x1f, 0x0005 },
2951                 { 0x05, 0x8b5b },
2952                 { 0x06, 0x9222 },
2953                 { 0x05, 0x8b6d },
2954                 { 0x06, 0x8000 },
2955                 { 0x05, 0x8b76 },
2956                 { 0x06, 0x8000 },
2957                 { 0x1f, 0x0000 }
2958         };
2959
2960         rtl_apply_firmware(tp);
2961
2962         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2963
2964         /* For 4-corner performance improve */
2965         rtl_writephy(tp, 0x1f, 0x0005);
2966         rtl_writephy(tp, 0x05, 0x8b80);
2967         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2968         rtl_writephy(tp, 0x1f, 0x0000);
2969
2970         /* PHY auto speed down */
2971         rtl_writephy(tp, 0x1f, 0x0004);
2972         rtl_writephy(tp, 0x1f, 0x0007);
2973         rtl_writephy(tp, 0x1e, 0x002d);
2974         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2975         rtl_writephy(tp, 0x1f, 0x0002);
2976         rtl_writephy(tp, 0x1f, 0x0000);
2977         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2978
2979         /* improve 10M EEE waveform */
2980         rtl_writephy(tp, 0x1f, 0x0005);
2981         rtl_writephy(tp, 0x05, 0x8b86);
2982         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2983         rtl_writephy(tp, 0x1f, 0x0000);
2984
2985         /* Improve 2-pair detection performance */
2986         rtl_writephy(tp, 0x1f, 0x0005);
2987         rtl_writephy(tp, 0x05, 0x8b85);
2988         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2989         rtl_writephy(tp, 0x1f, 0x0000);
2990
2991         /* EEE setting */
2992         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2993                      ERIAR_EXGMAC);
2994         rtl_writephy(tp, 0x1f, 0x0005);
2995         rtl_writephy(tp, 0x05, 0x8b85);
2996         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2997         rtl_writephy(tp, 0x1f, 0x0004);
2998         rtl_writephy(tp, 0x1f, 0x0007);
2999         rtl_writephy(tp, 0x1e, 0x0020);
3000         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3001         rtl_writephy(tp, 0x1f, 0x0002);
3002         rtl_writephy(tp, 0x1f, 0x0000);
3003         rtl_writephy(tp, 0x0d, 0x0007);
3004         rtl_writephy(tp, 0x0e, 0x003c);
3005         rtl_writephy(tp, 0x0d, 0x4007);
3006         rtl_writephy(tp, 0x0e, 0x0000);
3007         rtl_writephy(tp, 0x0d, 0x0000);
3008
3009         /* Green feature */
3010         rtl_writephy(tp, 0x1f, 0x0003);
3011         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3012         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3013         rtl_writephy(tp, 0x1f, 0x0000);
3014 }
3015
3016 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3017 {
3018         static const struct phy_reg phy_reg_init[] = {
3019                 /* Channel estimation fine tune */
3020                 { 0x1f, 0x0003 },
3021                 { 0x09, 0xa20f },
3022                 { 0x1f, 0x0000 },
3023
3024                 /* Modify green table for giga & fnet */
3025                 { 0x1f, 0x0005 },
3026                 { 0x05, 0x8b55 },
3027                 { 0x06, 0x0000 },
3028                 { 0x05, 0x8b5e },
3029                 { 0x06, 0x0000 },
3030                 { 0x05, 0x8b67 },
3031                 { 0x06, 0x0000 },
3032                 { 0x05, 0x8b70 },
3033                 { 0x06, 0x0000 },
3034                 { 0x1f, 0x0000 },
3035                 { 0x1f, 0x0007 },
3036                 { 0x1e, 0x0078 },
3037                 { 0x17, 0x0000 },
3038                 { 0x19, 0x00fb },
3039                 { 0x1f, 0x0000 },
3040
3041                 /* Modify green table for 10M */
3042                 { 0x1f, 0x0005 },
3043                 { 0x05, 0x8b79 },
3044                 { 0x06, 0xaa00 },
3045                 { 0x1f, 0x0000 },
3046
3047                 /* Disable hiimpedance detection (RTCT) */
3048                 { 0x1f, 0x0003 },
3049                 { 0x01, 0x328a },
3050                 { 0x1f, 0x0000 }
3051         };
3052
3053         rtl_apply_firmware(tp);
3054
3055         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3056
3057         /* For 4-corner performance improve */
3058         rtl_writephy(tp, 0x1f, 0x0005);
3059         rtl_writephy(tp, 0x05, 0x8b80);
3060         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3061         rtl_writephy(tp, 0x1f, 0x0000);
3062
3063         /* PHY auto speed down */
3064         rtl_writephy(tp, 0x1f, 0x0007);
3065         rtl_writephy(tp, 0x1e, 0x002d);
3066         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3067         rtl_writephy(tp, 0x1f, 0x0000);
3068         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3069
3070         /* Improve 10M EEE waveform */
3071         rtl_writephy(tp, 0x1f, 0x0005);
3072         rtl_writephy(tp, 0x05, 0x8b86);
3073         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3074         rtl_writephy(tp, 0x1f, 0x0000);
3075
3076         /* Improve 2-pair detection performance */
3077         rtl_writephy(tp, 0x1f, 0x0005);
3078         rtl_writephy(tp, 0x05, 0x8b85);
3079         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3080         rtl_writephy(tp, 0x1f, 0x0000);
3081 }
3082
3083 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3084 {
3085         rtl_apply_firmware(tp);
3086
3087         /* For 4-corner performance improve */
3088         rtl_writephy(tp, 0x1f, 0x0005);
3089         rtl_writephy(tp, 0x05, 0x8b80);
3090         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3091         rtl_writephy(tp, 0x1f, 0x0000);
3092
3093         /* PHY auto speed down */
3094         rtl_writephy(tp, 0x1f, 0x0007);
3095         rtl_writephy(tp, 0x1e, 0x002d);
3096         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3097         rtl_writephy(tp, 0x1f, 0x0000);
3098         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099
3100         /* Improve 10M EEE waveform */
3101         rtl_writephy(tp, 0x1f, 0x0005);
3102         rtl_writephy(tp, 0x05, 0x8b86);
3103         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3104         rtl_writephy(tp, 0x1f, 0x0000);
3105 }
3106
3107 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3108 {
3109         static const struct phy_reg phy_reg_init[] = {
3110                 { 0x1f, 0x0003 },
3111                 { 0x08, 0x441d },
3112                 { 0x01, 0x9100 },
3113                 { 0x1f, 0x0000 }
3114         };
3115
3116         rtl_writephy(tp, 0x1f, 0x0000);
3117         rtl_patchphy(tp, 0x11, 1 << 12);
3118         rtl_patchphy(tp, 0x19, 1 << 13);
3119         rtl_patchphy(tp, 0x10, 1 << 15);
3120
3121         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3122 }
3123
3124 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3125 {
3126         static const struct phy_reg phy_reg_init[] = {
3127                 { 0x1f, 0x0005 },
3128                 { 0x1a, 0x0000 },
3129                 { 0x1f, 0x0000 },
3130
3131                 { 0x1f, 0x0004 },
3132                 { 0x1c, 0x0000 },
3133                 { 0x1f, 0x0000 },
3134
3135                 { 0x1f, 0x0001 },
3136                 { 0x15, 0x7701 },
3137                 { 0x1f, 0x0000 }
3138         };
3139
3140         /* Disable ALDPS before ram code */
3141         rtl_writephy(tp, 0x1f, 0x0000);
3142         rtl_writephy(tp, 0x18, 0x0310);
3143         msleep(100);
3144
3145         rtl_apply_firmware(tp);
3146
3147         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3148 }
3149
3150 static void rtl_hw_phy_config(struct net_device *dev)
3151 {
3152         struct rtl8169_private *tp = netdev_priv(dev);
3153
3154         rtl8169_print_mac_version(tp);
3155
3156         switch (tp->mac_version) {
3157         case RTL_GIGA_MAC_VER_01:
3158                 break;
3159         case RTL_GIGA_MAC_VER_02:
3160         case RTL_GIGA_MAC_VER_03:
3161                 rtl8169s_hw_phy_config(tp);
3162                 break;
3163         case RTL_GIGA_MAC_VER_04:
3164                 rtl8169sb_hw_phy_config(tp);
3165                 break;
3166         case RTL_GIGA_MAC_VER_05:
3167                 rtl8169scd_hw_phy_config(tp);
3168                 break;
3169         case RTL_GIGA_MAC_VER_06:
3170                 rtl8169sce_hw_phy_config(tp);
3171                 break;
3172         case RTL_GIGA_MAC_VER_07:
3173         case RTL_GIGA_MAC_VER_08:
3174         case RTL_GIGA_MAC_VER_09:
3175                 rtl8102e_hw_phy_config(tp);
3176                 break;
3177         case RTL_GIGA_MAC_VER_11:
3178                 rtl8168bb_hw_phy_config(tp);
3179                 break;
3180         case RTL_GIGA_MAC_VER_12:
3181                 rtl8168bef_hw_phy_config(tp);
3182                 break;
3183         case RTL_GIGA_MAC_VER_17:
3184                 rtl8168bef_hw_phy_config(tp);
3185                 break;
3186         case RTL_GIGA_MAC_VER_18:
3187                 rtl8168cp_1_hw_phy_config(tp);
3188                 break;
3189         case RTL_GIGA_MAC_VER_19:
3190                 rtl8168c_1_hw_phy_config(tp);
3191                 break;
3192         case RTL_GIGA_MAC_VER_20:
3193                 rtl8168c_2_hw_phy_config(tp);
3194                 break;
3195         case RTL_GIGA_MAC_VER_21:
3196                 rtl8168c_3_hw_phy_config(tp);
3197                 break;
3198         case RTL_GIGA_MAC_VER_22:
3199                 rtl8168c_4_hw_phy_config(tp);
3200                 break;
3201         case RTL_GIGA_MAC_VER_23:
3202         case RTL_GIGA_MAC_VER_24:
3203                 rtl8168cp_2_hw_phy_config(tp);
3204                 break;
3205         case RTL_GIGA_MAC_VER_25:
3206                 rtl8168d_1_hw_phy_config(tp);
3207                 break;
3208         case RTL_GIGA_MAC_VER_26:
3209                 rtl8168d_2_hw_phy_config(tp);
3210                 break;
3211         case RTL_GIGA_MAC_VER_27:
3212                 rtl8168d_3_hw_phy_config(tp);
3213                 break;
3214         case RTL_GIGA_MAC_VER_28:
3215                 rtl8168d_4_hw_phy_config(tp);
3216                 break;
3217         case RTL_GIGA_MAC_VER_29:
3218         case RTL_GIGA_MAC_VER_30:
3219                 rtl8105e_hw_phy_config(tp);
3220                 break;
3221         case RTL_GIGA_MAC_VER_31:
3222                 /* None. */
3223                 break;
3224         case RTL_GIGA_MAC_VER_32:
3225         case RTL_GIGA_MAC_VER_33:
3226                 rtl8168e_1_hw_phy_config(tp);
3227                 break;
3228         case RTL_GIGA_MAC_VER_34:
3229                 rtl8168e_2_hw_phy_config(tp);
3230                 break;
3231         case RTL_GIGA_MAC_VER_35:
3232                 rtl8168f_1_hw_phy_config(tp);
3233                 break;
3234         case RTL_GIGA_MAC_VER_36:
3235                 rtl8168f_2_hw_phy_config(tp);
3236                 break;
3237
3238         default:
3239                 break;
3240         }
3241 }
3242
3243 static void rtl_phy_work(struct rtl8169_private *tp)
3244 {
3245         struct timer_list *timer = &tp->timer;
3246         void __iomem *ioaddr = tp->mmio_addr;
3247         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3248
3249         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3250
3251         if (tp->phy_reset_pending(tp)) {
3252                 /*
3253                  * A busy loop could burn quite a few cycles on nowadays CPU.
3254                  * Let's delay the execution of the timer for a few ticks.
3255                  */
3256                 timeout = HZ/10;
3257                 goto out_mod_timer;
3258         }
3259
3260         if (tp->link_ok(ioaddr))
3261                 return;
3262
3263         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3264
3265         tp->phy_reset_enable(tp);
3266
3267 out_mod_timer:
3268         mod_timer(timer, jiffies + timeout);
3269 }
3270
3271 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3272 {
3273         if (!test_and_set_bit(flag, tp->wk.flags))
3274                 schedule_work(&tp->wk.work);
3275 }
3276
3277 static void rtl8169_phy_timer(unsigned long __opaque)
3278 {
3279         struct net_device *dev = (struct net_device *)__opaque;
3280         struct rtl8169_private *tp = netdev_priv(dev);
3281
3282         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3283 }
3284
3285 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3286                                   void __iomem *ioaddr)
3287 {
3288         iounmap(ioaddr);
3289         pci_release_regions(pdev);
3290         pci_clear_mwi(pdev);
3291         pci_disable_device(pdev);
3292         free_netdev(dev);
3293 }
3294
3295 static void rtl8169_phy_reset(struct net_device *dev,
3296                               struct rtl8169_private *tp)
3297 {
3298         unsigned int i;
3299
3300         tp->phy_reset_enable(tp);
3301         for (i = 0; i < 100; i++) {
3302                 if (!tp->phy_reset_pending(tp))
3303                         return;
3304                 msleep(1);
3305         }
3306         netif_err(tp, link, dev, "PHY reset failed\n");
3307 }
3308
3309 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3310 {
3311         void __iomem *ioaddr = tp->mmio_addr;
3312
3313         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3314             (RTL_R8(PHYstatus) & TBI_Enable);
3315 }
3316
3317 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3318 {
3319         void __iomem *ioaddr = tp->mmio_addr;
3320
3321         rtl_hw_phy_config(dev);
3322
3323         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3324                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3325                 RTL_W8(0x82, 0x01);
3326         }
3327
3328         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3329
3330         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3331                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3332
3333         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3334                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3335                 RTL_W8(0x82, 0x01);
3336                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3337                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3338         }
3339
3340         rtl8169_phy_reset(dev, tp);
3341
3342         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3343                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3344                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3345                           (tp->mii.supports_gmii ?
3346                            ADVERTISED_1000baseT_Half |
3347                            ADVERTISED_1000baseT_Full : 0));
3348
3349         if (rtl_tbi_enabled(tp))
3350                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3351 }
3352
3353 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3354 {
3355         void __iomem *ioaddr = tp->mmio_addr;
3356         u32 high;
3357         u32 low;
3358
3359         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3360         high = addr[4] | (addr[5] << 8);
3361
3362         rtl_lock_work(tp);
3363
3364         RTL_W8(Cfg9346, Cfg9346_Unlock);
3365
3366         RTL_W32(MAC4, high);
3367         RTL_R32(MAC4);
3368
3369         RTL_W32(MAC0, low);
3370         RTL_R32(MAC0);
3371
3372         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3373                 const struct exgmac_reg e[] = {
3374                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3375                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3376                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3377                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3378                                                                 low  >> 16 },
3379                 };
3380
3381                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3382         }
3383
3384         RTL_W8(Cfg9346, Cfg9346_Lock);
3385
3386         rtl_unlock_work(tp);
3387 }
3388
3389 static int rtl_set_mac_address(struct net_device *dev, void *p)
3390 {
3391         struct rtl8169_private *tp = netdev_priv(dev);
3392         struct sockaddr *addr = p;
3393
3394         if (!is_valid_ether_addr(addr->sa_data))
3395                 return -EADDRNOTAVAIL;
3396
3397         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3398
3399         rtl_rar_set(tp, dev->dev_addr);
3400
3401         return 0;
3402 }
3403
3404 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3405 {
3406         struct rtl8169_private *tp = netdev_priv(dev);
3407         struct mii_ioctl_data *data = if_mii(ifr);
3408
3409         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3410 }
3411
3412 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3413                           struct mii_ioctl_data *data, int cmd)
3414 {
3415         switch (cmd) {
3416         case SIOCGMIIPHY:
3417                 data->phy_id = 32; /* Internal PHY */
3418                 return 0;
3419
3420         case SIOCGMIIREG:
3421                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3422                 return 0;
3423
3424         case SIOCSMIIREG:
3425                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3426                 return 0;
3427         }
3428         return -EOPNOTSUPP;
3429 }
3430
3431 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3432 {
3433         return -EOPNOTSUPP;
3434 }
3435
3436 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3437 {
3438         if (tp->features & RTL_FEATURE_MSI) {
3439                 pci_disable_msi(pdev);
3440                 tp->features &= ~RTL_FEATURE_MSI;
3441         }
3442 }
3443
3444 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3445 {
3446         struct mdio_ops *ops = &tp->mdio_ops;
3447
3448         switch (tp->mac_version) {
3449         case RTL_GIGA_MAC_VER_27:
3450                 ops->write      = r8168dp_1_mdio_write;
3451                 ops->read       = r8168dp_1_mdio_read;
3452                 break;
3453         case RTL_GIGA_MAC_VER_28:
3454         case RTL_GIGA_MAC_VER_31:
3455                 ops->write      = r8168dp_2_mdio_write;
3456                 ops->read       = r8168dp_2_mdio_read;
3457                 break;
3458         default:
3459                 ops->write      = r8169_mdio_write;
3460                 ops->read       = r8169_mdio_read;
3461                 break;
3462         }
3463 }
3464
3465 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3466 {
3467         void __iomem *ioaddr = tp->mmio_addr;
3468
3469         switch (tp->mac_version) {
3470         case RTL_GIGA_MAC_VER_29:
3471         case RTL_GIGA_MAC_VER_30:
3472         case RTL_GIGA_MAC_VER_32:
3473         case RTL_GIGA_MAC_VER_33:
3474         case RTL_GIGA_MAC_VER_34:
3475                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3476                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3477                 break;
3478         default:
3479                 break;
3480         }
3481 }
3482
3483 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3484 {
3485         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3486                 return false;
3487
3488         rtl_writephy(tp, 0x1f, 0x0000);
3489         rtl_writephy(tp, MII_BMCR, 0x0000);
3490
3491         rtl_wol_suspend_quirk(tp);
3492
3493         return true;
3494 }
3495
3496 static void r810x_phy_power_down(struct rtl8169_private *tp)
3497 {
3498         rtl_writephy(tp, 0x1f, 0x0000);
3499         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3500 }
3501
3502 static void r810x_phy_power_up(struct rtl8169_private *tp)
3503 {
3504         rtl_writephy(tp, 0x1f, 0x0000);
3505         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3506 }
3507
3508 static void r810x_pll_power_down(struct rtl8169_private *tp)
3509 {
3510         if (rtl_wol_pll_power_down(tp))
3511                 return;
3512
3513         r810x_phy_power_down(tp);
3514 }
3515
3516 static void r810x_pll_power_up(struct rtl8169_private *tp)
3517 {
3518         r810x_phy_power_up(tp);
3519 }
3520
3521 static void r8168_phy_power_up(struct rtl8169_private *tp)
3522 {
3523         rtl_writephy(tp, 0x1f, 0x0000);
3524         switch (tp->mac_version) {
3525         case RTL_GIGA_MAC_VER_11:
3526         case RTL_GIGA_MAC_VER_12:
3527         case RTL_GIGA_MAC_VER_17:
3528         case RTL_GIGA_MAC_VER_18:
3529         case RTL_GIGA_MAC_VER_19:
3530         case RTL_GIGA_MAC_VER_20:
3531         case RTL_GIGA_MAC_VER_21:
3532         case RTL_GIGA_MAC_VER_22:
3533         case RTL_GIGA_MAC_VER_23:
3534         case RTL_GIGA_MAC_VER_24:
3535         case RTL_GIGA_MAC_VER_25:
3536         case RTL_GIGA_MAC_VER_26:
3537         case RTL_GIGA_MAC_VER_27:
3538         case RTL_GIGA_MAC_VER_28:
3539         case RTL_GIGA_MAC_VER_31:
3540                 rtl_writephy(tp, 0x0e, 0x0000);
3541                 break;
3542         default:
3543                 break;
3544         }
3545         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3546 }
3547
3548 static void r8168_phy_power_down(struct rtl8169_private *tp)
3549 {
3550         rtl_writephy(tp, 0x1f, 0x0000);
3551         switch (tp->mac_version) {
3552         case RTL_GIGA_MAC_VER_32:
3553         case RTL_GIGA_MAC_VER_33:
3554                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3555                 break;
3556
3557         case RTL_GIGA_MAC_VER_11:
3558         case RTL_GIGA_MAC_VER_12:
3559         case RTL_GIGA_MAC_VER_17:
3560         case RTL_GIGA_MAC_VER_18:
3561         case RTL_GIGA_MAC_VER_19:
3562         case RTL_GIGA_MAC_VER_20:
3563         case RTL_GIGA_MAC_VER_21:
3564         case RTL_GIGA_MAC_VER_22:
3565         case RTL_GIGA_MAC_VER_23:
3566         case RTL_GIGA_MAC_VER_24:
3567         case RTL_GIGA_MAC_VER_25:
3568         case RTL_GIGA_MAC_VER_26:
3569         case RTL_GIGA_MAC_VER_27:
3570         case RTL_GIGA_MAC_VER_28:
3571         case RTL_GIGA_MAC_VER_31:
3572                 rtl_writephy(tp, 0x0e, 0x0200);
3573         default:
3574                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3575                 break;
3576         }
3577 }
3578
3579 static void r8168_pll_power_down(struct rtl8169_private *tp)
3580 {
3581         void __iomem *ioaddr = tp->mmio_addr;
3582
3583         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3584              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3585              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3586             r8168dp_check_dash(tp)) {
3587                 return;
3588         }
3589
3590         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3591              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3592             (RTL_R16(CPlusCmd) & ASF)) {
3593                 return;
3594         }
3595
3596         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3597             tp->mac_version == RTL_GIGA_MAC_VER_33)
3598                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3599
3600         if (rtl_wol_pll_power_down(tp))
3601                 return;
3602
3603         r8168_phy_power_down(tp);
3604
3605         switch (tp->mac_version) {
3606         case RTL_GIGA_MAC_VER_25:
3607         case RTL_GIGA_MAC_VER_26:
3608         case RTL_GIGA_MAC_VER_27:
3609         case RTL_GIGA_MAC_VER_28:
3610         case RTL_GIGA_MAC_VER_31:
3611         case RTL_GIGA_MAC_VER_32:
3612         case RTL_GIGA_MAC_VER_33:
3613                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3614                 break;
3615         }
3616 }
3617
3618 static void r8168_pll_power_up(struct rtl8169_private *tp)
3619 {
3620         void __iomem *ioaddr = tp->mmio_addr;
3621
3622         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3623              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3624              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3625             r8168dp_check_dash(tp)) {
3626                 return;
3627         }
3628
3629         switch (tp->mac_version) {
3630         case RTL_GIGA_MAC_VER_25:
3631         case RTL_GIGA_MAC_VER_26:
3632         case RTL_GIGA_MAC_VER_27:
3633         case RTL_GIGA_MAC_VER_28:
3634         case RTL_GIGA_MAC_VER_31:
3635         case RTL_GIGA_MAC_VER_32:
3636         case RTL_GIGA_MAC_VER_33:
3637                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3638                 break;
3639         }
3640
3641         r8168_phy_power_up(tp);
3642 }
3643
3644 static void rtl_generic_op(struct rtl8169_private *tp,
3645                            void (*op)(struct rtl8169_private *))
3646 {
3647         if (op)
3648                 op(tp);
3649 }
3650
3651 static void rtl_pll_power_down(struct rtl8169_private *tp)
3652 {
3653         rtl_generic_op(tp, tp->pll_power_ops.down);
3654 }
3655
3656 static void rtl_pll_power_up(struct rtl8169_private *tp)
3657 {
3658         rtl_generic_op(tp, tp->pll_power_ops.up);
3659 }
3660
3661 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3662 {
3663         struct pll_power_ops *ops = &tp->pll_power_ops;
3664
3665         switch (tp->mac_version) {
3666         case RTL_GIGA_MAC_VER_07:
3667         case RTL_GIGA_MAC_VER_08:
3668         case RTL_GIGA_MAC_VER_09:
3669         case RTL_GIGA_MAC_VER_10:
3670         case RTL_GIGA_MAC_VER_16:
3671         case RTL_GIGA_MAC_VER_29:
3672         case RTL_GIGA_MAC_VER_30:
3673                 ops->down       = r810x_pll_power_down;
3674                 ops->up         = r810x_pll_power_up;
3675                 break;
3676
3677         case RTL_GIGA_MAC_VER_11:
3678         case RTL_GIGA_MAC_VER_12:
3679         case RTL_GIGA_MAC_VER_17:
3680         case RTL_GIGA_MAC_VER_18:
3681         case RTL_GIGA_MAC_VER_19:
3682         case RTL_GIGA_MAC_VER_20:
3683         case RTL_GIGA_MAC_VER_21:
3684         case RTL_GIGA_MAC_VER_22:
3685         case RTL_GIGA_MAC_VER_23:
3686         case RTL_GIGA_MAC_VER_24:
3687         case RTL_GIGA_MAC_VER_25:
3688         case RTL_GIGA_MAC_VER_26:
3689         case RTL_GIGA_MAC_VER_27:
3690         case RTL_GIGA_MAC_VER_28:
3691         case RTL_GIGA_MAC_VER_31:
3692         case RTL_GIGA_MAC_VER_32:
3693         case RTL_GIGA_MAC_VER_33:
3694         case RTL_GIGA_MAC_VER_34:
3695         case RTL_GIGA_MAC_VER_35:
3696         case RTL_GIGA_MAC_VER_36:
3697                 ops->down       = r8168_pll_power_down;
3698                 ops->up         = r8168_pll_power_up;
3699                 break;
3700
3701         default:
3702                 ops->down       = NULL;
3703                 ops->up         = NULL;
3704                 break;
3705         }
3706 }
3707
3708 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3709 {
3710         void __iomem *ioaddr = tp->mmio_addr;
3711
3712         switch (tp->mac_version) {
3713         case RTL_GIGA_MAC_VER_01:
3714         case RTL_GIGA_MAC_VER_02:
3715         case RTL_GIGA_MAC_VER_03:
3716         case RTL_GIGA_MAC_VER_04:
3717         case RTL_GIGA_MAC_VER_05:
3718         case RTL_GIGA_MAC_VER_06:
3719         case RTL_GIGA_MAC_VER_10:
3720         case RTL_GIGA_MAC_VER_11:
3721         case RTL_GIGA_MAC_VER_12:
3722         case RTL_GIGA_MAC_VER_13:
3723         case RTL_GIGA_MAC_VER_14:
3724         case RTL_GIGA_MAC_VER_15:
3725         case RTL_GIGA_MAC_VER_16:
3726         case RTL_GIGA_MAC_VER_17:
3727                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3728                 break;
3729         case RTL_GIGA_MAC_VER_18:
3730         case RTL_GIGA_MAC_VER_19:
3731         case RTL_GIGA_MAC_VER_20:
3732         case RTL_GIGA_MAC_VER_21:
3733         case RTL_GIGA_MAC_VER_22:
3734         case RTL_GIGA_MAC_VER_23:
3735         case RTL_GIGA_MAC_VER_24:
3736                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3737                 break;
3738         default:
3739                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3740                 break;
3741         }
3742 }
3743
3744 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3745 {
3746         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3747 }
3748
3749 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3750 {
3751         void __iomem *ioaddr = tp->mmio_addr;
3752
3753         RTL_W8(Cfg9346, Cfg9346_Unlock);
3754         rtl_generic_op(tp, tp->jumbo_ops.enable);
3755         RTL_W8(Cfg9346, Cfg9346_Lock);
3756 }
3757
3758 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3759 {
3760         void __iomem *ioaddr = tp->mmio_addr;
3761
3762         RTL_W8(Cfg9346, Cfg9346_Unlock);
3763         rtl_generic_op(tp, tp->jumbo_ops.disable);
3764         RTL_W8(Cfg9346, Cfg9346_Lock);
3765 }
3766
3767 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3768 {
3769         void __iomem *ioaddr = tp->mmio_addr;
3770
3771         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3772         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3773         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3774 }
3775
3776 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3777 {
3778         void __iomem *ioaddr = tp->mmio_addr;
3779
3780         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3781         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3782         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3783 }
3784
3785 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3786 {
3787         void __iomem *ioaddr = tp->mmio_addr;
3788
3789         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3790 }
3791
3792 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3793 {
3794         void __iomem *ioaddr = tp->mmio_addr;
3795
3796         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3797 }
3798
3799 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3800 {
3801         void __iomem *ioaddr = tp->mmio_addr;
3802
3803         RTL_W8(MaxTxPacketSize, 0x3f);
3804         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3805         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3806         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3807 }
3808
3809 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3810 {
3811         void __iomem *ioaddr = tp->mmio_addr;
3812
3813         RTL_W8(MaxTxPacketSize, 0x0c);
3814         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3815         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3816         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3817 }
3818
3819 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3820 {
3821         rtl_tx_performance_tweak(tp->pci_dev,
3822                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3823 }
3824
3825 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3826 {
3827         rtl_tx_performance_tweak(tp->pci_dev,
3828                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3829 }
3830
3831 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3832 {
3833         void __iomem *ioaddr = tp->mmio_addr;
3834
3835         r8168b_0_hw_jumbo_enable(tp);
3836
3837         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3838 }
3839
3840 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3841 {
3842         void __iomem *ioaddr = tp->mmio_addr;
3843
3844         r8168b_0_hw_jumbo_disable(tp);
3845
3846         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3847 }
3848
3849 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3850 {
3851         struct jumbo_ops *ops = &tp->jumbo_ops;
3852
3853         switch (tp->mac_version) {
3854         case RTL_GIGA_MAC_VER_11:
3855                 ops->disable    = r8168b_0_hw_jumbo_disable;
3856                 ops->enable     = r8168b_0_hw_jumbo_enable;
3857                 break;
3858         case RTL_GIGA_MAC_VER_12:
3859         case RTL_GIGA_MAC_VER_17:
3860                 ops->disable    = r8168b_1_hw_jumbo_disable;
3861                 ops->enable     = r8168b_1_hw_jumbo_enable;
3862                 break;
3863         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3864         case RTL_GIGA_MAC_VER_19:
3865         case RTL_GIGA_MAC_VER_20:
3866         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3867         case RTL_GIGA_MAC_VER_22:
3868         case RTL_GIGA_MAC_VER_23:
3869         case RTL_GIGA_MAC_VER_24:
3870         case RTL_GIGA_MAC_VER_25:
3871         case RTL_GIGA_MAC_VER_26:
3872                 ops->disable    = r8168c_hw_jumbo_disable;
3873                 ops->enable     = r8168c_hw_jumbo_enable;
3874                 break;
3875         case RTL_GIGA_MAC_VER_27:
3876         case RTL_GIGA_MAC_VER_28:
3877                 ops->disable    = r8168dp_hw_jumbo_disable;
3878                 ops->enable     = r8168dp_hw_jumbo_enable;
3879                 break;
3880         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3881         case RTL_GIGA_MAC_VER_32:
3882         case RTL_GIGA_MAC_VER_33:
3883         case RTL_GIGA_MAC_VER_34:
3884                 ops->disable    = r8168e_hw_jumbo_disable;
3885                 ops->enable     = r8168e_hw_jumbo_enable;
3886                 break;
3887
3888         /*
3889          * No action needed for jumbo frames with 8169.
3890          * No jumbo for 810x at all.
3891          */
3892         default:
3893                 ops->disable    = NULL;
3894                 ops->enable     = NULL;
3895                 break;
3896         }
3897 }
3898
3899 static void rtl_hw_reset(struct rtl8169_private *tp)
3900 {
3901         void __iomem *ioaddr = tp->mmio_addr;
3902         int i;
3903
3904         /* Soft reset the chip. */
3905         RTL_W8(ChipCmd, CmdReset);
3906
3907         /* Check that the chip has finished the reset. */
3908         for (i = 0; i < 100; i++) {
3909                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3910                         break;
3911                 udelay(100);
3912         }
3913 }
3914
3915 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3916 {
3917         struct rtl_fw *rtl_fw;
3918         const char *name;
3919         int rc = -ENOMEM;
3920
3921         name = rtl_lookup_firmware_name(tp);
3922         if (!name)
3923                 goto out_no_firmware;
3924
3925         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3926         if (!rtl_fw)
3927                 goto err_warn;
3928
3929         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3930         if (rc < 0)
3931                 goto err_free;
3932
3933         rc = rtl_check_firmware(tp, rtl_fw);
3934         if (rc < 0)
3935                 goto err_release_firmware;
3936
3937         tp->rtl_fw = rtl_fw;
3938 out:
3939         return;
3940
3941 err_release_firmware:
3942         release_firmware(rtl_fw->fw);
3943 err_free:
3944         kfree(rtl_fw);
3945 err_warn:
3946         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3947                    name, rc);
3948 out_no_firmware:
3949         tp->rtl_fw = NULL;
3950         goto out;
3951 }
3952
3953 static void rtl_request_firmware(struct rtl8169_private *tp)
3954 {
3955         if (IS_ERR(tp->rtl_fw))
3956                 rtl_request_uncached_firmware(tp);
3957 }
3958
3959 static void rtl_rx_close(struct rtl8169_private *tp)
3960 {
3961         void __iomem *ioaddr = tp->mmio_addr;
3962
3963         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3964 }
3965
3966 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3967 {
3968         void __iomem *ioaddr = tp->mmio_addr;
3969
3970         /* Disable interrupts */
3971         rtl8169_irq_mask_and_ack(tp);
3972
3973         rtl_rx_close(tp);
3974
3975         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3976             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3977             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3978                 while (RTL_R8(TxPoll) & NPQ)
3979                         udelay(20);
3980         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3981                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3982                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
3983                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3984                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3985                         udelay(100);
3986         } else {
3987                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3988                 udelay(100);
3989         }
3990
3991         rtl_hw_reset(tp);
3992 }
3993
3994 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3995 {
3996         void __iomem *ioaddr = tp->mmio_addr;
3997
3998         /* Set DMA burst size and Interframe Gap Time */
3999         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4000                 (InterFrameGap << TxInterFrameGapShift));
4001 }
4002
4003 static void rtl_hw_start(struct net_device *dev)
4004 {
4005         struct rtl8169_private *tp = netdev_priv(dev);
4006
4007         tp->hw_start(dev);
4008
4009         rtl_irq_enable_all(tp);
4010 }
4011
4012 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4013                                          void __iomem *ioaddr)
4014 {
4015         /*
4016          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4017          * register to be written before TxDescAddrLow to work.
4018          * Switching from MMIO to I/O access fixes the issue as well.
4019          */
4020         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4021         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4022         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4023         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4024 }
4025
4026 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4027 {
4028         u16 cmd;
4029
4030         cmd = RTL_R16(CPlusCmd);
4031         RTL_W16(CPlusCmd, cmd);
4032         return cmd;
4033 }
4034
4035 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4036 {
4037         /* Low hurts. Let's disable the filtering. */
4038         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4039 }
4040
4041 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4042 {
4043         static const struct rtl_cfg2_info {
4044                 u32 mac_version;
4045                 u32 clk;
4046                 u32 val;
4047         } cfg2_info [] = {
4048                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4049                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4050                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4051                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4052         };
4053         const struct rtl_cfg2_info *p = cfg2_info;
4054         unsigned int i;
4055         u32 clk;
4056
4057         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4058         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4059                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4060                         RTL_W32(0x7c, p->val);
4061                         break;
4062                 }
4063         }
4064 }
4065
4066 static void rtl_set_rx_mode(struct net_device *dev)
4067 {
4068         struct rtl8169_private *tp = netdev_priv(dev);
4069         void __iomem *ioaddr = tp->mmio_addr;
4070         u32 mc_filter[2];       /* Multicast hash filter */
4071         int rx_mode;
4072         u32 tmp = 0;
4073
4074         if (dev->flags & IFF_PROMISC) {
4075                 /* Unconditionally log net taps. */
4076                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4077                 rx_mode =
4078                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4079                     AcceptAllPhys;
4080                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4081         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4082                    (dev->flags & IFF_ALLMULTI)) {
4083                 /* Too many to filter perfectly -- accept all multicasts. */
4084                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4085                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4086         } else {
4087                 struct netdev_hw_addr *ha;
4088
4089                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4090                 mc_filter[1] = mc_filter[0] = 0;
4091                 netdev_for_each_mc_addr(ha, dev) {
4092                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4093                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4094                         rx_mode |= AcceptMulticast;
4095                 }
4096         }
4097
4098         if (dev->features & NETIF_F_RXALL)
4099                 rx_mode |= (AcceptErr | AcceptRunt);
4100
4101         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4102
4103         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4104                 u32 data = mc_filter[0];
4105
4106                 mc_filter[0] = swab32(mc_filter[1]);
4107                 mc_filter[1] = swab32(data);
4108         }
4109
4110         RTL_W32(MAR0 + 4, mc_filter[1]);
4111         RTL_W32(MAR0 + 0, mc_filter[0]);
4112
4113         RTL_W32(RxConfig, tmp);
4114 }
4115
4116 static void rtl_hw_start_8169(struct net_device *dev)
4117 {
4118         struct rtl8169_private *tp = netdev_priv(dev);
4119         void __iomem *ioaddr = tp->mmio_addr;
4120         struct pci_dev *pdev = tp->pci_dev;
4121
4122         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4123                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4124                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4125         }
4126
4127         RTL_W8(Cfg9346, Cfg9346_Unlock);
4128         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4129             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4130             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4131             tp->mac_version == RTL_GIGA_MAC_VER_04)
4132                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4133
4134         rtl_init_rxcfg(tp);
4135
4136         RTL_W8(EarlyTxThres, NoEarlyTx);
4137
4138         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4139
4140         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4141             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4142             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4143             tp->mac_version == RTL_GIGA_MAC_VER_04)
4144                 rtl_set_rx_tx_config_registers(tp);
4145
4146         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4147
4148         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4149             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4150                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4151                         "Bit-3 and bit-14 MUST be 1\n");
4152                 tp->cp_cmd |= (1 << 14);
4153         }
4154
4155         RTL_W16(CPlusCmd, tp->cp_cmd);
4156
4157         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4158
4159         /*
4160          * Undocumented corner. Supposedly:
4161          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4162          */
4163         RTL_W16(IntrMitigate, 0x0000);
4164
4165         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4166
4167         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4168             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4169             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4170             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4171                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4172                 rtl_set_rx_tx_config_registers(tp);
4173         }
4174
4175         RTL_W8(Cfg9346, Cfg9346_Lock);
4176
4177         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4178         RTL_R8(IntrMask);
4179
4180         RTL_W32(RxMissed, 0);
4181
4182         rtl_set_rx_mode(dev);
4183
4184         /* no early-rx interrupts */
4185         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4186 }
4187
4188 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4189 {
4190         u32 csi;
4191
4192         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4193         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4194 }
4195
4196 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4197 {
4198         rtl_csi_access_enable(ioaddr, 0x17000000);
4199 }
4200
4201 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4202 {
4203         rtl_csi_access_enable(ioaddr, 0x27000000);
4204 }
4205
4206 struct ephy_info {
4207         unsigned int offset;
4208         u16 mask;
4209         u16 bits;
4210 };
4211
4212 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4213 {
4214         u16 w;
4215
4216         while (len-- > 0) {
4217                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4218                 rtl_ephy_write(ioaddr, e->offset, w);
4219                 e++;
4220         }
4221 }
4222
4223 static void rtl_disable_clock_request(struct pci_dev *pdev)
4224 {
4225         int cap = pci_pcie_cap(pdev);
4226
4227         if (cap) {
4228                 u16 ctl;
4229
4230                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4231                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4232                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4233         }
4234 }
4235
4236 static void rtl_enable_clock_request(struct pci_dev *pdev)
4237 {
4238         int cap = pci_pcie_cap(pdev);
4239
4240         if (cap) {
4241                 u16 ctl;
4242
4243                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4244                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4245                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4246         }
4247 }
4248
4249 #define R8168_CPCMD_QUIRK_MASK (\
4250         EnableBist | \
4251         Mac_dbgo_oe | \
4252         Force_half_dup | \
4253         Force_rxflow_en | \
4254         Force_txflow_en | \
4255         Cxpl_dbg_sel | \
4256         ASF | \
4257         PktCntrDisable | \
4258         Mac_dbgo_sel)
4259
4260 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4261 {
4262         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4263
4264         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4265
4266         rtl_tx_performance_tweak(pdev,
4267                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4268 }
4269
4270 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4271 {
4272         rtl_hw_start_8168bb(ioaddr, pdev);
4273
4274         RTL_W8(MaxTxPacketSize, TxPacketMax);
4275
4276         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4277 }
4278
4279 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4280 {
4281         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4282
4283         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4284
4285         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4286
4287         rtl_disable_clock_request(pdev);
4288
4289         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4290 }
4291
4292 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4293 {
4294         static const struct ephy_info e_info_8168cp[] = {
4295                 { 0x01, 0,      0x0001 },
4296                 { 0x02, 0x0800, 0x1000 },
4297                 { 0x03, 0,      0x0042 },
4298                 { 0x06, 0x0080, 0x0000 },
4299                 { 0x07, 0,      0x2000 }
4300         };
4301
4302         rtl_csi_access_enable_2(ioaddr);
4303
4304         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4305
4306         __rtl_hw_start_8168cp(ioaddr, pdev);
4307 }
4308
4309 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4310 {
4311         rtl_csi_access_enable_2(ioaddr);
4312
4313         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4314
4315         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4316
4317         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4318 }
4319
4320 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4321 {
4322         rtl_csi_access_enable_2(ioaddr);
4323
4324         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4325
4326         /* Magic. */
4327         RTL_W8(DBG_REG, 0x20);
4328
4329         RTL_W8(MaxTxPacketSize, TxPacketMax);
4330
4331         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4332
4333         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4334 }
4335
4336 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4337 {
4338         static const struct ephy_info e_info_8168c_1[] = {
4339                 { 0x02, 0x0800, 0x1000 },
4340                 { 0x03, 0,      0x0002 },
4341                 { 0x06, 0x0080, 0x0000 }
4342         };
4343
4344         rtl_csi_access_enable_2(ioaddr);
4345
4346         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4347
4348         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4349
4350         __rtl_hw_start_8168cp(ioaddr, pdev);
4351 }
4352
4353 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4354 {
4355         static const struct ephy_info e_info_8168c_2[] = {
4356                 { 0x01, 0,      0x0001 },
4357                 { 0x03, 0x0400, 0x0220 }
4358         };
4359
4360         rtl_csi_access_enable_2(ioaddr);
4361
4362         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4363
4364         __rtl_hw_start_8168cp(ioaddr, pdev);
4365 }
4366
4367 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4368 {
4369         rtl_hw_start_8168c_2(ioaddr, pdev);
4370 }
4371
4372 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4373 {
4374         rtl_csi_access_enable_2(ioaddr);
4375
4376         __rtl_hw_start_8168cp(ioaddr, pdev);
4377 }
4378
4379 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4380 {
4381         rtl_csi_access_enable_2(ioaddr);
4382
4383         rtl_disable_clock_request(pdev);
4384
4385         RTL_W8(MaxTxPacketSize, TxPacketMax);
4386
4387         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4388
4389         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4390 }
4391
4392 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4393 {
4394         rtl_csi_access_enable_1(ioaddr);
4395
4396         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4397
4398         RTL_W8(MaxTxPacketSize, TxPacketMax);
4399
4400         rtl_disable_clock_request(pdev);
4401 }
4402
4403 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4404 {
4405         static const struct ephy_info e_info_8168d_4[] = {
4406                 { 0x0b, ~0,     0x48 },
4407                 { 0x19, 0x20,   0x50 },
4408                 { 0x0c, ~0,     0x20 }
4409         };
4410         int i;
4411
4412         rtl_csi_access_enable_1(ioaddr);
4413
4414         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4415
4416         RTL_W8(MaxTxPacketSize, TxPacketMax);
4417
4418         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4419                 const struct ephy_info *e = e_info_8168d_4 + i;
4420                 u16 w;
4421
4422                 w = rtl_ephy_read(ioaddr, e->offset);
4423                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4424         }
4425
4426         rtl_enable_clock_request(pdev);
4427 }
4428
4429 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4430 {
4431         static const struct ephy_info e_info_8168e_1[] = {
4432                 { 0x00, 0x0200, 0x0100 },
4433                 { 0x00, 0x0000, 0x0004 },
4434                 { 0x06, 0x0002, 0x0001 },
4435                 { 0x06, 0x0000, 0x0030 },
4436                 { 0x07, 0x0000, 0x2000 },
4437                 { 0x00, 0x0000, 0x0020 },
4438                 { 0x03, 0x5800, 0x2000 },
4439                 { 0x03, 0x0000, 0x0001 },
4440                 { 0x01, 0x0800, 0x1000 },
4441                 { 0x07, 0x0000, 0x4000 },
4442                 { 0x1e, 0x0000, 0x2000 },
4443                 { 0x19, 0xffff, 0xfe6c },
4444                 { 0x0a, 0x0000, 0x0040 }
4445         };
4446
4447         rtl_csi_access_enable_2(ioaddr);
4448
4449         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4450
4451         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4452
4453         RTL_W8(MaxTxPacketSize, TxPacketMax);
4454
4455         rtl_disable_clock_request(pdev);
4456
4457         /* Reset tx FIFO pointer */
4458         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4459         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4460
4461         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4462 }
4463
4464 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4465 {
4466         static const struct ephy_info e_info_8168e_2[] = {
4467                 { 0x09, 0x0000, 0x0080 },
4468                 { 0x19, 0x0000, 0x0224 }
4469         };
4470
4471         rtl_csi_access_enable_1(ioaddr);
4472
4473         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4474
4475         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4476
4477         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4478         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4479         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4480         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4481         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4482         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4483         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4484         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4485                      ERIAR_EXGMAC);
4486
4487         RTL_W8(MaxTxPacketSize, EarlySize);
4488
4489         rtl_disable_clock_request(pdev);
4490
4491         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4492         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4493
4494         /* Adjust EEE LED frequency */
4495         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4496
4497         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4498         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4499         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4500 }
4501
4502 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4503 {
4504         static const struct ephy_info e_info_8168f_1[] = {
4505                 { 0x06, 0x00c0, 0x0020 },
4506                 { 0x08, 0x0001, 0x0002 },
4507                 { 0x09, 0x0000, 0x0080 },
4508                 { 0x19, 0x0000, 0x0224 }
4509         };
4510
4511         rtl_csi_access_enable_1(ioaddr);
4512
4513         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4514
4515         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4516
4517         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4518         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4519         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4520         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4521         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4522         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4523         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4524         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4525         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4526         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4527         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4528                      ERIAR_EXGMAC);
4529
4530         RTL_W8(MaxTxPacketSize, EarlySize);
4531
4532         rtl_disable_clock_request(pdev);
4533
4534         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4535         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4536
4537         /* Adjust EEE LED frequency */
4538         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4539
4540         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4541         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4542         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4543 }
4544
4545 static void rtl_hw_start_8168(struct net_device *dev)
4546 {
4547         struct rtl8169_private *tp = netdev_priv(dev);
4548         void __iomem *ioaddr = tp->mmio_addr;
4549         struct pci_dev *pdev = tp->pci_dev;
4550
4551         RTL_W8(Cfg9346, Cfg9346_Unlock);
4552
4553         RTL_W8(MaxTxPacketSize, TxPacketMax);
4554
4555         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4556
4557         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4558
4559         RTL_W16(CPlusCmd, tp->cp_cmd);
4560
4561         RTL_W16(IntrMitigate, 0x5151);
4562
4563         /* Work around for RxFIFO overflow. */
4564         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4565                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4566                 tp->event_slow &= ~RxOverflow;
4567         }
4568
4569         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4570
4571         rtl_set_rx_mode(dev);
4572
4573         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4574                 (InterFrameGap << TxInterFrameGapShift));
4575
4576         RTL_R8(IntrMask);
4577
4578         switch (tp->mac_version) {
4579         case RTL_GIGA_MAC_VER_11:
4580                 rtl_hw_start_8168bb(ioaddr, pdev);
4581                 break;
4582
4583         case RTL_GIGA_MAC_VER_12:
4584         case RTL_GIGA_MAC_VER_17:
4585                 rtl_hw_start_8168bef(ioaddr, pdev);
4586                 break;
4587
4588         case RTL_GIGA_MAC_VER_18:
4589                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4590                 break;
4591
4592         case RTL_GIGA_MAC_VER_19:
4593                 rtl_hw_start_8168c_1(ioaddr, pdev);
4594                 break;
4595
4596         case RTL_GIGA_MAC_VER_20:
4597                 rtl_hw_start_8168c_2(ioaddr, pdev);
4598                 break;
4599
4600         case RTL_GIGA_MAC_VER_21:
4601                 rtl_hw_start_8168c_3(ioaddr, pdev);
4602                 break;
4603
4604         case RTL_GIGA_MAC_VER_22:
4605                 rtl_hw_start_8168c_4(ioaddr, pdev);
4606                 break;
4607
4608         case RTL_GIGA_MAC_VER_23:
4609                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4610                 break;
4611
4612         case RTL_GIGA_MAC_VER_24:
4613                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4614                 break;
4615
4616         case RTL_GIGA_MAC_VER_25:
4617         case RTL_GIGA_MAC_VER_26:
4618         case RTL_GIGA_MAC_VER_27:
4619                 rtl_hw_start_8168d(ioaddr, pdev);
4620                 break;
4621
4622         case RTL_GIGA_MAC_VER_28:
4623                 rtl_hw_start_8168d_4(ioaddr, pdev);
4624                 break;
4625
4626         case RTL_GIGA_MAC_VER_31:
4627                 rtl_hw_start_8168dp(ioaddr, pdev);
4628                 break;
4629
4630         case RTL_GIGA_MAC_VER_32:
4631         case RTL_GIGA_MAC_VER_33:
4632                 rtl_hw_start_8168e_1(ioaddr, pdev);
4633                 break;
4634         case RTL_GIGA_MAC_VER_34:
4635                 rtl_hw_start_8168e_2(ioaddr, pdev);
4636                 break;
4637
4638         case RTL_GIGA_MAC_VER_35:
4639         case RTL_GIGA_MAC_VER_36:
4640                 rtl_hw_start_8168f_1(ioaddr, pdev);
4641                 break;
4642
4643         default:
4644                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4645                         dev->name, tp->mac_version);
4646                 break;
4647         }
4648
4649         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4650
4651         RTL_W8(Cfg9346, Cfg9346_Lock);
4652
4653         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4654 }
4655
4656 #define R810X_CPCMD_QUIRK_MASK (\
4657         EnableBist | \
4658         Mac_dbgo_oe | \
4659         Force_half_dup | \
4660         Force_rxflow_en | \
4661         Force_txflow_en | \
4662         Cxpl_dbg_sel | \
4663         ASF | \
4664         PktCntrDisable | \
4665         Mac_dbgo_sel)
4666
4667 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4668 {
4669         static const struct ephy_info e_info_8102e_1[] = {
4670                 { 0x01, 0, 0x6e65 },
4671                 { 0x02, 0, 0x091f },
4672                 { 0x03, 0, 0xc2f9 },
4673                 { 0x06, 0, 0xafb5 },
4674                 { 0x07, 0, 0x0e00 },
4675                 { 0x19, 0, 0xec80 },
4676                 { 0x01, 0, 0x2e65 },
4677                 { 0x01, 0, 0x6e65 }
4678         };
4679         u8 cfg1;
4680
4681         rtl_csi_access_enable_2(ioaddr);
4682
4683         RTL_W8(DBG_REG, FIX_NAK_1);
4684
4685         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4686
4687         RTL_W8(Config1,
4688                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4689         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4690
4691         cfg1 = RTL_R8(Config1);
4692         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4693                 RTL_W8(Config1, cfg1 & ~LEDS0);
4694
4695         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4696 }
4697
4698 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4699 {
4700         rtl_csi_access_enable_2(ioaddr);
4701
4702         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4703
4704         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4705         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4706 }
4707
4708 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4709 {
4710         rtl_hw_start_8102e_2(ioaddr, pdev);
4711
4712         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4713 }
4714
4715 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4716 {
4717         static const struct ephy_info e_info_8105e_1[] = {
4718                 { 0x07, 0, 0x4000 },
4719                 { 0x19, 0, 0x0200 },
4720                 { 0x19, 0, 0x0020 },
4721                 { 0x1e, 0, 0x2000 },
4722                 { 0x03, 0, 0x0001 },
4723                 { 0x19, 0, 0x0100 },
4724                 { 0x19, 0, 0x0004 },
4725                 { 0x0a, 0, 0x0020 }
4726         };
4727
4728         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4729         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4730
4731         /* Disable Early Tally Counter */
4732         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4733
4734         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4735         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4736
4737         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4738 }
4739
4740 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4741 {
4742         rtl_hw_start_8105e_1(ioaddr, pdev);
4743         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4744 }
4745
4746 static void rtl_hw_start_8101(struct net_device *dev)
4747 {
4748         struct rtl8169_private *tp = netdev_priv(dev);
4749         void __iomem *ioaddr = tp->mmio_addr;
4750         struct pci_dev *pdev = tp->pci_dev;
4751
4752         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4753                 tp->event_slow &= ~RxFIFOOver;
4754
4755         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4756             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4757                 int cap = pci_pcie_cap(pdev);
4758
4759                 if (cap) {
4760                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4761                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4762                 }
4763         }
4764
4765         RTL_W8(Cfg9346, Cfg9346_Unlock);
4766
4767         switch (tp->mac_version) {
4768         case RTL_GIGA_MAC_VER_07:
4769                 rtl_hw_start_8102e_1(ioaddr, pdev);
4770                 break;
4771
4772         case RTL_GIGA_MAC_VER_08:
4773                 rtl_hw_start_8102e_3(ioaddr, pdev);
4774                 break;
4775
4776         case RTL_GIGA_MAC_VER_09:
4777                 rtl_hw_start_8102e_2(ioaddr, pdev);
4778                 break;
4779
4780         case RTL_GIGA_MAC_VER_29:
4781                 rtl_hw_start_8105e_1(ioaddr, pdev);
4782                 break;
4783         case RTL_GIGA_MAC_VER_30:
4784                 rtl_hw_start_8105e_2(ioaddr, pdev);
4785                 break;
4786         }
4787
4788         RTL_W8(Cfg9346, Cfg9346_Lock);
4789
4790         RTL_W8(MaxTxPacketSize, TxPacketMax);
4791
4792         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4793
4794         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4795         RTL_W16(CPlusCmd, tp->cp_cmd);
4796
4797         RTL_W16(IntrMitigate, 0x0000);
4798
4799         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4800
4801         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4802         rtl_set_rx_tx_config_registers(tp);
4803
4804         RTL_R8(IntrMask);
4805
4806         rtl_set_rx_mode(dev);
4807
4808         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4809 }
4810
4811 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4812 {
4813         struct rtl8169_private *tp = netdev_priv(dev);
4814
4815         if (new_mtu < ETH_ZLEN ||
4816             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4817                 return -EINVAL;
4818
4819         if (new_mtu > ETH_DATA_LEN)
4820                 rtl_hw_jumbo_enable(tp);
4821         else
4822                 rtl_hw_jumbo_disable(tp);
4823
4824         dev->mtu = new_mtu;
4825         netdev_update_features(dev);
4826
4827         return 0;
4828 }
4829
4830 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4831 {
4832         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4833         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4834 }
4835
4836 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4837                                      void **data_buff, struct RxDesc *desc)
4838 {
4839         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4840                          DMA_FROM_DEVICE);
4841
4842         kfree(*data_buff);
4843         *data_buff = NULL;
4844         rtl8169_make_unusable_by_asic(desc);
4845 }
4846
4847 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4848 {
4849         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4850
4851         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4852 }
4853
4854 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4855                                        u32 rx_buf_sz)
4856 {
4857         desc->addr = cpu_to_le64(mapping);
4858         wmb();
4859         rtl8169_mark_to_asic(desc, rx_buf_sz);
4860 }
4861
4862 static inline void *rtl8169_align(void *data)
4863 {
4864         return (void *)ALIGN((long)data, 16);
4865 }
4866
4867 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4868                                              struct RxDesc *desc)
4869 {
4870         void *data;
4871         dma_addr_t mapping;
4872         struct device *d = &tp->pci_dev->dev;
4873         struct net_device *dev = tp->dev;
4874         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4875
4876         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4877         if (!data)
4878                 return NULL;
4879
4880         if (rtl8169_align(data) != data) {
4881                 kfree(data);
4882                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4883                 if (!data)
4884                         return NULL;
4885         }
4886
4887         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4888                                  DMA_FROM_DEVICE);
4889         if (unlikely(dma_mapping_error(d, mapping))) {
4890                 if (net_ratelimit())
4891                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4892                 goto err_out;
4893         }
4894
4895         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4896         return data;
4897
4898 err_out:
4899         kfree(data);
4900         return NULL;
4901 }
4902
4903 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4904 {
4905         unsigned int i;
4906
4907         for (i = 0; i < NUM_RX_DESC; i++) {
4908                 if (tp->Rx_databuff[i]) {
4909                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4910                                             tp->RxDescArray + i);
4911                 }
4912         }
4913 }
4914
4915 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4916 {
4917         desc->opts1 |= cpu_to_le32(RingEnd);
4918 }
4919
4920 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4921 {
4922         unsigned int i;
4923
4924         for (i = 0; i < NUM_RX_DESC; i++) {
4925                 void *data;
4926
4927                 if (tp->Rx_databuff[i])
4928                         continue;
4929
4930                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4931                 if (!data) {
4932                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4933                         goto err_out;
4934                 }
4935                 tp->Rx_databuff[i] = data;
4936         }
4937
4938         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4939         return 0;
4940
4941 err_out:
4942         rtl8169_rx_clear(tp);
4943         return -ENOMEM;
4944 }
4945
4946 static int rtl8169_init_ring(struct net_device *dev)
4947 {
4948         struct rtl8169_private *tp = netdev_priv(dev);
4949
4950         rtl8169_init_ring_indexes(tp);
4951
4952         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4953         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4954
4955         return rtl8169_rx_fill(tp);
4956 }
4957
4958 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4959                                  struct TxDesc *desc)
4960 {
4961         unsigned int len = tx_skb->len;
4962
4963         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4964
4965         desc->opts1 = 0x00;
4966         desc->opts2 = 0x00;
4967         desc->addr = 0x00;
4968         tx_skb->len = 0;
4969 }
4970
4971 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4972                                    unsigned int n)
4973 {
4974         unsigned int i;
4975
4976         for (i = 0; i < n; i++) {
4977                 unsigned int entry = (start + i) % NUM_TX_DESC;
4978                 struct ring_info *tx_skb = tp->tx_skb + entry;
4979                 unsigned int len = tx_skb->len;
4980
4981                 if (len) {
4982                         struct sk_buff *skb = tx_skb->skb;
4983
4984                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4985                                              tp->TxDescArray + entry);
4986                         if (skb) {
4987                                 tp->dev->stats.tx_dropped++;
4988                                 dev_kfree_skb(skb);
4989                                 tx_skb->skb = NULL;
4990                         }
4991                 }
4992         }
4993 }
4994
4995 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4996 {
4997         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4998         tp->cur_tx = tp->dirty_tx = 0;
4999         netdev_reset_queue(tp->dev);
5000 }
5001
5002 static void rtl_reset_work(struct rtl8169_private *tp)
5003 {
5004         struct net_device *dev = tp->dev;
5005         int i;
5006
5007         napi_disable(&tp->napi);
5008         netif_stop_queue(dev);
5009         synchronize_sched();
5010
5011         rtl8169_hw_reset(tp);
5012
5013         for (i = 0; i < NUM_RX_DESC; i++)
5014                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5015
5016         rtl8169_tx_clear(tp);
5017         rtl8169_init_ring_indexes(tp);
5018
5019         napi_enable(&tp->napi);
5020         rtl_hw_start(dev);
5021         netif_wake_queue(dev);
5022         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5023 }
5024
5025 static void rtl8169_tx_timeout(struct net_device *dev)
5026 {
5027         struct rtl8169_private *tp = netdev_priv(dev);
5028
5029         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5030 }
5031
5032 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5033                               u32 *opts)
5034 {
5035         struct skb_shared_info *info = skb_shinfo(skb);
5036         unsigned int cur_frag, entry;
5037         struct TxDesc * uninitialized_var(txd);
5038         struct device *d = &tp->pci_dev->dev;
5039
5040         entry = tp->cur_tx;
5041         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5042                 const skb_frag_t *frag = info->frags + cur_frag;
5043                 dma_addr_t mapping;
5044                 u32 status, len;
5045                 void *addr;
5046
5047                 entry = (entry + 1) % NUM_TX_DESC;
5048
5049                 txd = tp->TxDescArray + entry;
5050                 len = skb_frag_size(frag);
5051                 addr = skb_frag_address(frag);
5052                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5053                 if (unlikely(dma_mapping_error(d, mapping))) {
5054                         if (net_ratelimit())
5055                                 netif_err(tp, drv, tp->dev,
5056                                           "Failed to map TX fragments DMA!\n");
5057                         goto err_out;
5058                 }
5059
5060                 /* Anti gcc 2.95.3 bugware (sic) */
5061                 status = opts[0] | len |
5062                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5063
5064                 txd->opts1 = cpu_to_le32(status);
5065                 txd->opts2 = cpu_to_le32(opts[1]);
5066                 txd->addr = cpu_to_le64(mapping);
5067
5068                 tp->tx_skb[entry].len = len;
5069         }
5070
5071         if (cur_frag) {
5072                 tp->tx_skb[entry].skb = skb;
5073                 txd->opts1 |= cpu_to_le32(LastFrag);
5074         }
5075
5076         return cur_frag;
5077
5078 err_out:
5079         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5080         return -EIO;
5081 }
5082
5083 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5084                                     struct sk_buff *skb, u32 *opts)
5085 {
5086         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5087         u32 mss = skb_shinfo(skb)->gso_size;
5088         int offset = info->opts_offset;
5089
5090         if (mss) {
5091                 opts[0] |= TD_LSO;
5092                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5093         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5094                 const struct iphdr *ip = ip_hdr(skb);
5095
5096                 if (ip->protocol == IPPROTO_TCP)
5097                         opts[offset] |= info->checksum.tcp;
5098                 else if (ip->protocol == IPPROTO_UDP)
5099                         opts[offset] |= info->checksum.udp;
5100                 else
5101                         WARN_ON_ONCE(1);
5102         }
5103 }
5104
5105 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5106                                       struct net_device *dev)
5107 {
5108         struct rtl8169_private *tp = netdev_priv(dev);
5109         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5110         struct TxDesc *txd = tp->TxDescArray + entry;
5111         void __iomem *ioaddr = tp->mmio_addr;
5112         struct device *d = &tp->pci_dev->dev;
5113         dma_addr_t mapping;
5114         u32 status, len;
5115         u32 opts[2];
5116         int frags;
5117
5118         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5119                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5120                 goto err_stop_0;
5121         }
5122
5123         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5124                 goto err_stop_0;
5125
5126         len = skb_headlen(skb);
5127         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5128         if (unlikely(dma_mapping_error(d, mapping))) {
5129                 if (net_ratelimit())
5130                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5131                 goto err_dma_0;
5132         }
5133
5134         tp->tx_skb[entry].len = len;
5135         txd->addr = cpu_to_le64(mapping);
5136
5137         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5138         opts[0] = DescOwn;
5139
5140         rtl8169_tso_csum(tp, skb, opts);
5141
5142         frags = rtl8169_xmit_frags(tp, skb, opts);
5143         if (frags < 0)
5144                 goto err_dma_1;
5145         else if (frags)
5146                 opts[0] |= FirstFrag;
5147         else {
5148                 opts[0] |= FirstFrag | LastFrag;
5149                 tp->tx_skb[entry].skb = skb;
5150         }
5151
5152         txd->opts2 = cpu_to_le32(opts[1]);
5153
5154         netdev_sent_queue(dev, skb->len);
5155
5156         skb_tx_timestamp(skb);
5157
5158         wmb();
5159
5160         /* Anti gcc 2.95.3 bugware (sic) */
5161         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5162         txd->opts1 = cpu_to_le32(status);
5163
5164         tp->cur_tx += frags + 1;
5165
5166         wmb();
5167
5168         RTL_W8(TxPoll, NPQ);
5169
5170         mmiowb();
5171
5172         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5173                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5174                  * not miss a ring update when it notices a stopped queue.
5175                  */
5176                 smp_wmb();
5177                 netif_stop_queue(dev);
5178                 /* Sync with rtl_tx:
5179                  * - publish queue status and cur_tx ring index (write barrier)
5180                  * - refresh dirty_tx ring index (read barrier).
5181                  * May the current thread have a pessimistic view of the ring
5182                  * status and forget to wake up queue, a racing rtl_tx thread
5183                  * can't.
5184                  */
5185                 smp_mb();
5186                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5187                         netif_wake_queue(dev);
5188         }
5189
5190         return NETDEV_TX_OK;
5191
5192 err_dma_1:
5193         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5194 err_dma_0:
5195         dev_kfree_skb(skb);
5196         dev->stats.tx_dropped++;
5197         return NETDEV_TX_OK;
5198
5199 err_stop_0:
5200         netif_stop_queue(dev);
5201         dev->stats.tx_dropped++;
5202         return NETDEV_TX_BUSY;
5203 }
5204
5205 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5206 {
5207         struct rtl8169_private *tp = netdev_priv(dev);
5208         struct pci_dev *pdev = tp->pci_dev;
5209         u16 pci_status, pci_cmd;
5210
5211         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5212         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5213
5214         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5215                   pci_cmd, pci_status);
5216
5217         /*
5218          * The recovery sequence below admits a very elaborated explanation:
5219          * - it seems to work;
5220          * - I did not see what else could be done;
5221          * - it makes iop3xx happy.
5222          *
5223          * Feel free to adjust to your needs.
5224          */
5225         if (pdev->broken_parity_status)
5226                 pci_cmd &= ~PCI_COMMAND_PARITY;
5227         else
5228                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5229
5230         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5231
5232         pci_write_config_word(pdev, PCI_STATUS,
5233                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5234                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5235                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5236
5237         /* The infamous DAC f*ckup only happens at boot time */
5238         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5239                 void __iomem *ioaddr = tp->mmio_addr;
5240
5241                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5242                 tp->cp_cmd &= ~PCIDAC;
5243                 RTL_W16(CPlusCmd, tp->cp_cmd);
5244                 dev->features &= ~NETIF_F_HIGHDMA;
5245         }
5246
5247         rtl8169_hw_reset(tp);
5248
5249         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5250 }
5251
5252 struct rtl_txc {
5253         int packets;
5254         int bytes;
5255 };
5256
5257 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5258 {
5259         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5260         unsigned int dirty_tx, tx_left;
5261         struct rtl_txc txc = { 0, 0 };
5262
5263         dirty_tx = tp->dirty_tx;
5264         smp_rmb();
5265         tx_left = tp->cur_tx - dirty_tx;
5266
5267         while (tx_left > 0) {
5268                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5269                 struct ring_info *tx_skb = tp->tx_skb + entry;
5270                 u32 status;
5271
5272                 rmb();
5273                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5274                 if (status & DescOwn)
5275                         break;
5276
5277                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5278                                      tp->TxDescArray + entry);
5279                 if (status & LastFrag) {
5280                         struct sk_buff *skb = tx_skb->skb;
5281
5282                         txc.packets++;
5283                         txc.bytes += skb->len;
5284                         dev_kfree_skb(skb);
5285                         tx_skb->skb = NULL;
5286                 }
5287                 dirty_tx++;
5288                 tx_left--;
5289         }
5290
5291         u64_stats_update_begin(&tx_stats->syncp);
5292         tx_stats->packets += txc.packets;
5293         tx_stats->bytes += txc.bytes;
5294         u64_stats_update_end(&tx_stats->syncp);
5295
5296         netdev_completed_queue(dev, txc.packets, txc.bytes);
5297
5298         if (tp->dirty_tx != dirty_tx) {
5299                 tp->dirty_tx = dirty_tx;
5300                 /* Sync with rtl8169_start_xmit:
5301                  * - publish dirty_tx ring index (write barrier)
5302                  * - refresh cur_tx ring index and queue status (read barrier)
5303                  * May the current thread miss the stopped queue condition,
5304                  * a racing xmit thread can only have a right view of the
5305                  * ring status.
5306                  */
5307                 smp_mb();
5308                 if (netif_queue_stopped(dev) &&
5309                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5310                         netif_wake_queue(dev);
5311                 }
5312                 /*
5313                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5314                  * too close. Let's kick an extra TxPoll request when a burst
5315                  * of start_xmit activity is detected (if it is not detected,
5316                  * it is slow enough). -- FR
5317                  */
5318                 if (tp->cur_tx != dirty_tx) {
5319                         void __iomem *ioaddr = tp->mmio_addr;
5320
5321                         RTL_W8(TxPoll, NPQ);
5322                 }
5323         }
5324 }
5325
5326 static inline int rtl8169_fragmented_frame(u32 status)
5327 {
5328         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5329 }
5330
5331 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5332 {
5333         u32 status = opts1 & RxProtoMask;
5334
5335         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5336             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5337                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5338         else
5339                 skb_checksum_none_assert(skb);
5340 }
5341
5342 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5343                                            struct rtl8169_private *tp,
5344                                            int pkt_size,
5345                                            dma_addr_t addr)
5346 {
5347         struct sk_buff *skb;
5348         struct device *d = &tp->pci_dev->dev;
5349
5350         data = rtl8169_align(data);
5351         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5352         prefetch(data);
5353         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5354         if (skb)
5355                 memcpy(skb->data, data, pkt_size);
5356         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5357
5358         return skb;
5359 }
5360
5361 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5362 {
5363         unsigned int cur_rx, rx_left;
5364         unsigned int count;
5365
5366         cur_rx = tp->cur_rx;
5367         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5368         rx_left = min(rx_left, budget);
5369
5370         for (; rx_left > 0; rx_left--, cur_rx++) {
5371                 unsigned int entry = cur_rx % NUM_RX_DESC;
5372                 struct RxDesc *desc = tp->RxDescArray + entry;
5373                 u32 status;
5374
5375                 rmb();
5376                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5377
5378                 if (status & DescOwn)
5379                         break;
5380                 if (unlikely(status & RxRES)) {
5381                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5382                                    status);
5383                         dev->stats.rx_errors++;
5384                         if (status & (RxRWT | RxRUNT))
5385                                 dev->stats.rx_length_errors++;
5386                         if (status & RxCRC)
5387                                 dev->stats.rx_crc_errors++;
5388                         if (status & RxFOVF) {
5389                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5390                                 dev->stats.rx_fifo_errors++;
5391                         }
5392                         if ((status & (RxRUNT | RxCRC)) &&
5393                             !(status & (RxRWT | RxFOVF)) &&
5394                             (dev->features & NETIF_F_RXALL))
5395                                 goto process_pkt;
5396
5397                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5398                 } else {
5399                         struct sk_buff *skb;
5400                         dma_addr_t addr;
5401                         int pkt_size;
5402
5403 process_pkt:
5404                         addr = le64_to_cpu(desc->addr);
5405                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5406                                 pkt_size = (status & 0x00003fff) - 4;
5407                         else
5408                                 pkt_size = status & 0x00003fff;
5409
5410                         /*
5411                          * The driver does not support incoming fragmented
5412                          * frames. They are seen as a symptom of over-mtu
5413                          * sized frames.
5414                          */
5415                         if (unlikely(rtl8169_fragmented_frame(status))) {
5416                                 dev->stats.rx_dropped++;
5417                                 dev->stats.rx_length_errors++;
5418                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5419                                 continue;
5420                         }
5421
5422                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5423                                                   tp, pkt_size, addr);
5424                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5425                         if (!skb) {
5426                                 dev->stats.rx_dropped++;
5427                                 continue;
5428                         }
5429
5430                         rtl8169_rx_csum(skb, status);
5431                         skb_put(skb, pkt_size);
5432                         skb->protocol = eth_type_trans(skb, dev);
5433
5434                         rtl8169_rx_vlan_tag(desc, skb);
5435
5436                         napi_gro_receive(&tp->napi, skb);
5437
5438                         u64_stats_update_begin(&tp->rx_stats.syncp);
5439                         tp->rx_stats.packets++;
5440                         tp->rx_stats.bytes += pkt_size;
5441                         u64_stats_update_end(&tp->rx_stats.syncp);
5442                 }
5443
5444                 /* Work around for AMD plateform. */
5445                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5446                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5447                         desc->opts2 = 0;
5448                         cur_rx++;
5449                 }
5450         }
5451
5452         count = cur_rx - tp->cur_rx;
5453         tp->cur_rx = cur_rx;
5454
5455         tp->dirty_rx += count;
5456
5457         return count;
5458 }
5459
5460 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5461 {
5462         struct net_device *dev = dev_instance;
5463         struct rtl8169_private *tp = netdev_priv(dev);
5464         int handled = 0;
5465         u16 status;
5466
5467         status = rtl_get_events(tp);
5468         if (status && status != 0xffff) {
5469                 status &= RTL_EVENT_NAPI | tp->event_slow;
5470                 if (status) {
5471                         handled = 1;
5472
5473                         rtl_irq_disable(tp);
5474                         napi_schedule(&tp->napi);
5475                 }
5476         }
5477         return IRQ_RETVAL(handled);
5478 }
5479
5480 /*
5481  * Workqueue context.
5482  */
5483 static void rtl_slow_event_work(struct rtl8169_private *tp)
5484 {
5485         struct net_device *dev = tp->dev;
5486         u16 status;
5487
5488         status = rtl_get_events(tp) & tp->event_slow;
5489         rtl_ack_events(tp, status);
5490
5491         if (unlikely(status & RxFIFOOver)) {
5492                 switch (tp->mac_version) {
5493                 /* Work around for rx fifo overflow */
5494                 case RTL_GIGA_MAC_VER_11:
5495                         netif_stop_queue(dev);
5496                         /* XXX - Hack alert. See rtl_task(). */
5497                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5498                 default:
5499                         break;
5500                 }
5501         }
5502
5503         if (unlikely(status & SYSErr))
5504                 rtl8169_pcierr_interrupt(dev);
5505
5506         if (status & LinkChg)
5507                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5508
5509         napi_disable(&tp->napi);
5510         rtl_irq_disable(tp);
5511
5512         napi_enable(&tp->napi);
5513         napi_schedule(&tp->napi);
5514 }
5515
5516 static void rtl_task(struct work_struct *work)
5517 {
5518         static const struct {
5519                 int bitnr;
5520                 void (*action)(struct rtl8169_private *);
5521         } rtl_work[] = {
5522                 /* XXX - keep rtl_slow_event_work() as first element. */
5523                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5524                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5525                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5526         };
5527         struct rtl8169_private *tp =
5528                 container_of(work, struct rtl8169_private, wk.work);
5529         struct net_device *dev = tp->dev;
5530         int i;
5531
5532         rtl_lock_work(tp);
5533
5534         if (!netif_running(dev) ||
5535             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5536                 goto out_unlock;
5537
5538         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5539                 bool pending;
5540
5541                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5542                 if (pending)
5543                         rtl_work[i].action(tp);
5544         }
5545
5546 out_unlock:
5547         rtl_unlock_work(tp);
5548 }
5549
5550 static int rtl8169_poll(struct napi_struct *napi, int budget)
5551 {
5552         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5553         struct net_device *dev = tp->dev;
5554         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5555         int work_done= 0;
5556         u16 status;
5557
5558         status = rtl_get_events(tp);
5559         rtl_ack_events(tp, status & ~tp->event_slow);
5560
5561         if (status & RTL_EVENT_NAPI_RX)
5562                 work_done = rtl_rx(dev, tp, (u32) budget);
5563
5564         if (status & RTL_EVENT_NAPI_TX)
5565                 rtl_tx(dev, tp);
5566
5567         if (status & tp->event_slow) {
5568                 enable_mask &= ~tp->event_slow;
5569
5570                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5571         }
5572
5573         if (work_done < budget) {
5574                 napi_complete(napi);
5575
5576                 rtl_irq_enable(tp, enable_mask);
5577                 mmiowb();
5578         }
5579
5580         return work_done;
5581 }
5582
5583 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5584 {
5585         struct rtl8169_private *tp = netdev_priv(dev);
5586
5587         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5588                 return;
5589
5590         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5591         RTL_W32(RxMissed, 0);
5592 }
5593
5594 static void rtl8169_down(struct net_device *dev)
5595 {
5596         struct rtl8169_private *tp = netdev_priv(dev);
5597         void __iomem *ioaddr = tp->mmio_addr;
5598
5599         del_timer_sync(&tp->timer);
5600
5601         napi_disable(&tp->napi);
5602         netif_stop_queue(dev);
5603
5604         rtl8169_hw_reset(tp);
5605         /*
5606          * At this point device interrupts can not be enabled in any function,
5607          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5608          * and napi is disabled (rtl8169_poll).
5609          */
5610         rtl8169_rx_missed(dev, ioaddr);
5611
5612         /* Give a racing hard_start_xmit a few cycles to complete. */
5613         synchronize_sched();
5614
5615         rtl8169_tx_clear(tp);
5616
5617         rtl8169_rx_clear(tp);
5618
5619         rtl_pll_power_down(tp);
5620 }
5621
5622 static int rtl8169_close(struct net_device *dev)
5623 {
5624         struct rtl8169_private *tp = netdev_priv(dev);
5625         struct pci_dev *pdev = tp->pci_dev;
5626
5627         pm_runtime_get_sync(&pdev->dev);
5628
5629         /* Update counters before going down */
5630         rtl8169_update_counters(dev);
5631
5632         rtl_lock_work(tp);
5633         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5634
5635         rtl8169_down(dev);
5636         rtl_unlock_work(tp);
5637
5638         free_irq(pdev->irq, dev);
5639
5640         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5641                           tp->RxPhyAddr);
5642         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5643                           tp->TxPhyAddr);
5644         tp->TxDescArray = NULL;
5645         tp->RxDescArray = NULL;
5646
5647         pm_runtime_put_sync(&pdev->dev);
5648
5649         return 0;
5650 }
5651
5652 #ifdef CONFIG_NET_POLL_CONTROLLER
5653 static void rtl8169_netpoll(struct net_device *dev)
5654 {
5655         struct rtl8169_private *tp = netdev_priv(dev);
5656
5657         rtl8169_interrupt(tp->pci_dev->irq, dev);
5658 }
5659 #endif
5660
5661 static int rtl_open(struct net_device *dev)
5662 {
5663         struct rtl8169_private *tp = netdev_priv(dev);
5664         void __iomem *ioaddr = tp->mmio_addr;
5665         struct pci_dev *pdev = tp->pci_dev;
5666         int retval = -ENOMEM;
5667
5668         pm_runtime_get_sync(&pdev->dev);
5669
5670         /*
5671          * Rx and Tx desscriptors needs 256 bytes alignment.
5672          * dma_alloc_coherent provides more.
5673          */
5674         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5675                                              &tp->TxPhyAddr, GFP_KERNEL);
5676         if (!tp->TxDescArray)
5677                 goto err_pm_runtime_put;
5678
5679         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5680                                              &tp->RxPhyAddr, GFP_KERNEL);
5681         if (!tp->RxDescArray)
5682                 goto err_free_tx_0;
5683
5684         retval = rtl8169_init_ring(dev);
5685         if (retval < 0)
5686                 goto err_free_rx_1;
5687
5688         INIT_WORK(&tp->wk.work, rtl_task);
5689
5690         smp_mb();
5691
5692         rtl_request_firmware(tp);
5693
5694         retval = request_irq(pdev->irq, rtl8169_interrupt,
5695                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5696                              dev->name, dev);
5697         if (retval < 0)
5698                 goto err_release_fw_2;
5699
5700         rtl_lock_work(tp);
5701
5702         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5703
5704         napi_enable(&tp->napi);
5705
5706         rtl8169_init_phy(dev, tp);
5707
5708         __rtl8169_set_features(dev, dev->features);
5709
5710         rtl_pll_power_up(tp);
5711
5712         rtl_hw_start(dev);
5713
5714         netif_start_queue(dev);
5715
5716         rtl_unlock_work(tp);
5717
5718         tp->saved_wolopts = 0;
5719         pm_runtime_put_noidle(&pdev->dev);
5720
5721         rtl8169_check_link_status(dev, tp, ioaddr);
5722 out:
5723         return retval;
5724
5725 err_release_fw_2:
5726         rtl_release_firmware(tp);
5727         rtl8169_rx_clear(tp);
5728 err_free_rx_1:
5729         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5730                           tp->RxPhyAddr);
5731         tp->RxDescArray = NULL;
5732 err_free_tx_0:
5733         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5734                           tp->TxPhyAddr);
5735         tp->TxDescArray = NULL;
5736 err_pm_runtime_put:
5737         pm_runtime_put_noidle(&pdev->dev);
5738         goto out;
5739 }
5740
5741 static struct rtnl_link_stats64 *
5742 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5743 {
5744         struct rtl8169_private *tp = netdev_priv(dev);
5745         void __iomem *ioaddr = tp->mmio_addr;
5746         unsigned int start;
5747
5748         if (netif_running(dev))
5749                 rtl8169_rx_missed(dev, ioaddr);
5750
5751         do {
5752                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5753                 stats->rx_packets = tp->rx_stats.packets;
5754                 stats->rx_bytes = tp->rx_stats.bytes;
5755         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5756
5757
5758         do {
5759                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5760                 stats->tx_packets = tp->tx_stats.packets;
5761                 stats->tx_bytes = tp->tx_stats.bytes;
5762         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5763
5764         stats->rx_dropped       = dev->stats.rx_dropped;
5765         stats->tx_dropped       = dev->stats.tx_dropped;
5766         stats->rx_length_errors = dev->stats.rx_length_errors;
5767         stats->rx_errors        = dev->stats.rx_errors;
5768         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5769         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5770         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5771
5772         return stats;
5773 }
5774
5775 static void rtl8169_net_suspend(struct net_device *dev)
5776 {
5777         struct rtl8169_private *tp = netdev_priv(dev);
5778
5779         if (!netif_running(dev))
5780                 return;
5781
5782         netif_device_detach(dev);
5783         netif_stop_queue(dev);
5784
5785         rtl_lock_work(tp);
5786         napi_disable(&tp->napi);
5787         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5788         rtl_unlock_work(tp);
5789
5790         rtl_pll_power_down(tp);
5791 }
5792
5793 #ifdef CONFIG_PM
5794
5795 static int rtl8169_suspend(struct device *device)
5796 {
5797         struct pci_dev *pdev = to_pci_dev(device);
5798         struct net_device *dev = pci_get_drvdata(pdev);
5799
5800         rtl8169_net_suspend(dev);
5801
5802         return 0;
5803 }
5804
5805 static void __rtl8169_resume(struct net_device *dev)
5806 {
5807         struct rtl8169_private *tp = netdev_priv(dev);
5808
5809         netif_device_attach(dev);
5810
5811         rtl_pll_power_up(tp);
5812
5813         rtl_lock_work(tp);
5814         napi_enable(&tp->napi);
5815         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5816         rtl_unlock_work(tp);
5817
5818         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5819 }
5820
5821 static int rtl8169_resume(struct device *device)
5822 {
5823         struct pci_dev *pdev = to_pci_dev(device);
5824         struct net_device *dev = pci_get_drvdata(pdev);
5825         struct rtl8169_private *tp = netdev_priv(dev);
5826
5827         rtl8169_init_phy(dev, tp);
5828
5829         if (netif_running(dev))
5830                 __rtl8169_resume(dev);
5831
5832         return 0;
5833 }
5834
5835 static int rtl8169_runtime_suspend(struct device *device)
5836 {
5837         struct pci_dev *pdev = to_pci_dev(device);
5838         struct net_device *dev = pci_get_drvdata(pdev);
5839         struct rtl8169_private *tp = netdev_priv(dev);
5840
5841         if (!tp->TxDescArray)
5842                 return 0;
5843
5844         rtl_lock_work(tp);
5845         tp->saved_wolopts = __rtl8169_get_wol(tp);
5846         __rtl8169_set_wol(tp, WAKE_ANY);
5847         rtl_unlock_work(tp);
5848
5849         rtl8169_net_suspend(dev);
5850
5851         return 0;
5852 }
5853
5854 static int rtl8169_runtime_resume(struct device *device)
5855 {
5856         struct pci_dev *pdev = to_pci_dev(device);
5857         struct net_device *dev = pci_get_drvdata(pdev);
5858         struct rtl8169_private *tp = netdev_priv(dev);
5859
5860         if (!tp->TxDescArray)
5861                 return 0;
5862
5863         rtl_lock_work(tp);
5864         __rtl8169_set_wol(tp, tp->saved_wolopts);
5865         tp->saved_wolopts = 0;
5866         rtl_unlock_work(tp);
5867
5868         rtl8169_init_phy(dev, tp);
5869
5870         __rtl8169_resume(dev);
5871
5872         return 0;
5873 }
5874
5875 static int rtl8169_runtime_idle(struct device *device)
5876 {
5877         struct pci_dev *pdev = to_pci_dev(device);
5878         struct net_device *dev = pci_get_drvdata(pdev);
5879         struct rtl8169_private *tp = netdev_priv(dev);
5880
5881         return tp->TxDescArray ? -EBUSY : 0;
5882 }
5883
5884 static const struct dev_pm_ops rtl8169_pm_ops = {
5885         .suspend                = rtl8169_suspend,
5886         .resume                 = rtl8169_resume,
5887         .freeze                 = rtl8169_suspend,
5888         .thaw                   = rtl8169_resume,
5889         .poweroff               = rtl8169_suspend,
5890         .restore                = rtl8169_resume,
5891         .runtime_suspend        = rtl8169_runtime_suspend,
5892         .runtime_resume         = rtl8169_runtime_resume,
5893         .runtime_idle           = rtl8169_runtime_idle,
5894 };
5895
5896 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5897
5898 #else /* !CONFIG_PM */
5899
5900 #define RTL8169_PM_OPS  NULL
5901
5902 #endif /* !CONFIG_PM */
5903
5904 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5905 {
5906         void __iomem *ioaddr = tp->mmio_addr;
5907
5908         /* WoL fails with 8168b when the receiver is disabled. */
5909         switch (tp->mac_version) {
5910         case RTL_GIGA_MAC_VER_11:
5911         case RTL_GIGA_MAC_VER_12:
5912         case RTL_GIGA_MAC_VER_17:
5913                 pci_clear_master(tp->pci_dev);
5914
5915                 RTL_W8(ChipCmd, CmdRxEnb);
5916                 /* PCI commit */
5917                 RTL_R8(ChipCmd);
5918                 break;
5919         default:
5920                 break;
5921         }
5922 }
5923
5924 static void rtl_shutdown(struct pci_dev *pdev)
5925 {
5926         struct net_device *dev = pci_get_drvdata(pdev);
5927         struct rtl8169_private *tp = netdev_priv(dev);
5928         struct device *d = &pdev->dev;
5929
5930         pm_runtime_get_sync(d);
5931
5932         rtl8169_net_suspend(dev);
5933
5934         /* Restore original MAC address */
5935         rtl_rar_set(tp, dev->perm_addr);
5936
5937         rtl8169_hw_reset(tp);
5938
5939         if (system_state == SYSTEM_POWER_OFF) {
5940                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5941                         rtl_wol_suspend_quirk(tp);
5942                         rtl_wol_shutdown_quirk(tp);
5943                 }
5944
5945                 pci_wake_from_d3(pdev, true);
5946                 pci_set_power_state(pdev, PCI_D3hot);
5947         }
5948
5949         pm_runtime_put_noidle(d);
5950 }
5951
5952 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5953 {
5954         struct net_device *dev = pci_get_drvdata(pdev);
5955         struct rtl8169_private *tp = netdev_priv(dev);
5956
5957         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5958             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5959             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5960                 rtl8168_driver_stop(tp);
5961         }
5962
5963         cancel_work_sync(&tp->wk.work);
5964
5965         unregister_netdev(dev);
5966
5967         rtl_release_firmware(tp);
5968
5969         if (pci_dev_run_wake(pdev))
5970                 pm_runtime_get_noresume(&pdev->dev);
5971
5972         /* restore original MAC address */
5973         rtl_rar_set(tp, dev->perm_addr);
5974
5975         rtl_disable_msi(pdev, tp);
5976         rtl8169_release_board(pdev, dev, tp->mmio_addr);
5977         pci_set_drvdata(pdev, NULL);
5978 }
5979
5980 static const struct net_device_ops rtl_netdev_ops = {
5981         .ndo_open               = rtl_open,
5982         .ndo_stop               = rtl8169_close,
5983         .ndo_get_stats64        = rtl8169_get_stats64,
5984         .ndo_start_xmit         = rtl8169_start_xmit,
5985         .ndo_tx_timeout         = rtl8169_tx_timeout,
5986         .ndo_validate_addr      = eth_validate_addr,
5987         .ndo_change_mtu         = rtl8169_change_mtu,
5988         .ndo_fix_features       = rtl8169_fix_features,
5989         .ndo_set_features       = rtl8169_set_features,
5990         .ndo_set_mac_address    = rtl_set_mac_address,
5991         .ndo_do_ioctl           = rtl8169_ioctl,
5992         .ndo_set_rx_mode        = rtl_set_rx_mode,
5993 #ifdef CONFIG_NET_POLL_CONTROLLER
5994         .ndo_poll_controller    = rtl8169_netpoll,
5995 #endif
5996
5997 };
5998
5999 static const struct rtl_cfg_info {
6000         void (*hw_start)(struct net_device *);
6001         unsigned int region;
6002         unsigned int align;
6003         u16 event_slow;
6004         unsigned features;
6005         u8 default_ver;
6006 } rtl_cfg_infos [] = {
6007         [RTL_CFG_0] = {
6008                 .hw_start       = rtl_hw_start_8169,
6009                 .region         = 1,
6010                 .align          = 0,
6011                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6012                 .features       = RTL_FEATURE_GMII,
6013                 .default_ver    = RTL_GIGA_MAC_VER_01,
6014         },
6015         [RTL_CFG_1] = {
6016                 .hw_start       = rtl_hw_start_8168,
6017                 .region         = 2,
6018                 .align          = 8,
6019                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6020                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6021                 .default_ver    = RTL_GIGA_MAC_VER_11,
6022         },
6023         [RTL_CFG_2] = {
6024                 .hw_start       = rtl_hw_start_8101,
6025                 .region         = 2,
6026                 .align          = 8,
6027                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6028                                   PCSTimeout,
6029                 .features       = RTL_FEATURE_MSI,
6030                 .default_ver    = RTL_GIGA_MAC_VER_13,
6031         }
6032 };
6033
6034 /* Cfg9346_Unlock assumed. */
6035 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6036                             const struct rtl_cfg_info *cfg)
6037 {
6038         void __iomem *ioaddr = tp->mmio_addr;
6039         unsigned msi = 0;
6040         u8 cfg2;
6041
6042         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6043         if (cfg->features & RTL_FEATURE_MSI) {
6044                 if (pci_enable_msi(tp->pci_dev)) {
6045                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6046                 } else {
6047                         cfg2 |= MSIEnable;
6048                         msi = RTL_FEATURE_MSI;
6049                 }
6050         }
6051         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6052                 RTL_W8(Config2, cfg2);
6053         return msi;
6054 }
6055
6056 static int __devinit
6057 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6058 {
6059         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6060         const unsigned int region = cfg->region;
6061         struct rtl8169_private *tp;
6062         struct mii_if_info *mii;
6063         struct net_device *dev;
6064         void __iomem *ioaddr;
6065         int chipset, i;
6066         int rc;
6067
6068         if (netif_msg_drv(&debug)) {
6069                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6070                        MODULENAME, RTL8169_VERSION);
6071         }
6072
6073         dev = alloc_etherdev(sizeof (*tp));
6074         if (!dev) {
6075                 rc = -ENOMEM;
6076                 goto out;
6077         }
6078
6079         SET_NETDEV_DEV(dev, &pdev->dev);
6080         dev->netdev_ops = &rtl_netdev_ops;
6081         tp = netdev_priv(dev);
6082         tp->dev = dev;
6083         tp->pci_dev = pdev;
6084         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6085
6086         mii = &tp->mii;
6087         mii->dev = dev;
6088         mii->mdio_read = rtl_mdio_read;
6089         mii->mdio_write = rtl_mdio_write;
6090         mii->phy_id_mask = 0x1f;
6091         mii->reg_num_mask = 0x1f;
6092         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6093
6094         /* disable ASPM completely as that cause random device stop working
6095          * problems as well as full system hangs for some PCIe devices users */
6096         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6097                                      PCIE_LINK_STATE_CLKPM);
6098
6099         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6100         rc = pci_enable_device(pdev);
6101         if (rc < 0) {
6102                 netif_err(tp, probe, dev, "enable failure\n");
6103                 goto err_out_free_dev_1;
6104         }
6105
6106         if (pci_set_mwi(pdev) < 0)
6107                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6108
6109         /* make sure PCI base addr 1 is MMIO */
6110         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6111                 netif_err(tp, probe, dev,
6112                           "region #%d not an MMIO resource, aborting\n",
6113                           region);
6114                 rc = -ENODEV;
6115                 goto err_out_mwi_2;
6116         }
6117
6118         /* check for weird/broken PCI region reporting */
6119         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6120                 netif_err(tp, probe, dev,
6121                           "Invalid PCI region size(s), aborting\n");
6122                 rc = -ENODEV;
6123                 goto err_out_mwi_2;
6124         }
6125
6126         rc = pci_request_regions(pdev, MODULENAME);
6127         if (rc < 0) {
6128                 netif_err(tp, probe, dev, "could not request regions\n");
6129                 goto err_out_mwi_2;
6130         }
6131
6132         tp->cp_cmd = RxChkSum;
6133
6134         if ((sizeof(dma_addr_t) > 4) &&
6135             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6136                 tp->cp_cmd |= PCIDAC;
6137                 dev->features |= NETIF_F_HIGHDMA;
6138         } else {
6139                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6140                 if (rc < 0) {
6141                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6142                         goto err_out_free_res_3;
6143                 }
6144         }
6145
6146         /* ioremap MMIO region */
6147         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6148         if (!ioaddr) {
6149                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6150                 rc = -EIO;
6151                 goto err_out_free_res_3;
6152         }
6153         tp->mmio_addr = ioaddr;
6154
6155         if (!pci_is_pcie(pdev))
6156                 netif_info(tp, probe, dev, "not PCI Express\n");
6157
6158         /* Identify chip attached to board */
6159         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6160
6161         rtl_init_rxcfg(tp);
6162
6163         rtl_irq_disable(tp);
6164
6165         rtl_hw_reset(tp);
6166
6167         rtl_ack_events(tp, 0xffff);
6168
6169         pci_set_master(pdev);
6170
6171         /*
6172          * Pretend we are using VLANs; This bypasses a nasty bug where
6173          * Interrupts stop flowing on high load on 8110SCd controllers.
6174          */
6175         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6176                 tp->cp_cmd |= RxVlan;
6177
6178         rtl_init_mdio_ops(tp);
6179         rtl_init_pll_power_ops(tp);
6180         rtl_init_jumbo_ops(tp);
6181
6182         rtl8169_print_mac_version(tp);
6183
6184         chipset = tp->mac_version;
6185         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6186
6187         RTL_W8(Cfg9346, Cfg9346_Unlock);
6188         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6189         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6190         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6191                 tp->features |= RTL_FEATURE_WOL;
6192         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6193                 tp->features |= RTL_FEATURE_WOL;
6194         tp->features |= rtl_try_msi(tp, cfg);
6195         RTL_W8(Cfg9346, Cfg9346_Lock);
6196
6197         if (rtl_tbi_enabled(tp)) {
6198                 tp->set_speed = rtl8169_set_speed_tbi;
6199                 tp->get_settings = rtl8169_gset_tbi;
6200                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6201                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6202                 tp->link_ok = rtl8169_tbi_link_ok;
6203                 tp->do_ioctl = rtl_tbi_ioctl;
6204         } else {
6205                 tp->set_speed = rtl8169_set_speed_xmii;
6206                 tp->get_settings = rtl8169_gset_xmii;
6207                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6208                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6209                 tp->link_ok = rtl8169_xmii_link_ok;
6210                 tp->do_ioctl = rtl_xmii_ioctl;
6211         }
6212
6213         mutex_init(&tp->wk.mutex);
6214
6215         /* Get MAC address */
6216         for (i = 0; i < ETH_ALEN; i++)
6217                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6218         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6219
6220         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6221         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6222
6223         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6224
6225         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6226          * properly for all devices */
6227         dev->features |= NETIF_F_RXCSUM |
6228                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6229
6230         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6231                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6232         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6233                 NETIF_F_HIGHDMA;
6234
6235         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6236                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6237                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6238
6239         dev->hw_features |= NETIF_F_RXALL;
6240         dev->hw_features |= NETIF_F_RXFCS;
6241
6242         tp->hw_start = cfg->hw_start;
6243         tp->event_slow = cfg->event_slow;
6244
6245         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6246                 ~(RxBOVF | RxFOVF) : ~0;
6247
6248         init_timer(&tp->timer);
6249         tp->timer.data = (unsigned long) dev;
6250         tp->timer.function = rtl8169_phy_timer;
6251
6252         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6253
6254         rc = register_netdev(dev);
6255         if (rc < 0)
6256                 goto err_out_msi_4;
6257
6258         pci_set_drvdata(pdev, dev);
6259
6260         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6261                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6262                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6263         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6264                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6265                            "tx checksumming: %s]\n",
6266                            rtl_chip_infos[chipset].jumbo_max,
6267                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6268         }
6269
6270         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6271             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6272             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6273                 rtl8168_driver_start(tp);
6274         }
6275
6276         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6277
6278         if (pci_dev_run_wake(pdev))
6279                 pm_runtime_put_noidle(&pdev->dev);
6280
6281         netif_carrier_off(dev);
6282
6283 out:
6284         return rc;
6285
6286 err_out_msi_4:
6287         rtl_disable_msi(pdev, tp);
6288         iounmap(ioaddr);
6289 err_out_free_res_3:
6290         pci_release_regions(pdev);
6291 err_out_mwi_2:
6292         pci_clear_mwi(pdev);
6293         pci_disable_device(pdev);
6294 err_out_free_dev_1:
6295         free_netdev(dev);
6296         goto out;
6297 }
6298
6299 static struct pci_driver rtl8169_pci_driver = {
6300         .name           = MODULENAME,
6301         .id_table       = rtl8169_pci_tbl,
6302         .probe          = rtl_init_one,
6303         .remove         = __devexit_p(rtl_remove_one),
6304         .shutdown       = rtl_shutdown,
6305         .driver.pm      = RTL8169_PM_OPS,
6306 };
6307
6308 static int __init rtl8169_init_module(void)
6309 {
6310         return pci_register_driver(&rtl8169_pci_driver);
6311 }
6312
6313 static void __exit rtl8169_cleanup_module(void)
6314 {
6315         pci_unregister_driver(&rtl8169_pci_driver);
6316 }
6317
6318 module_init(rtl8169_init_module);
6319 module_exit(rtl8169_cleanup_module);