sound/soc/tegra/tegra_i2s.c

   1 /*
   2  * tegra_i2s.c - Tegra I2S driver
   3  *
   4  * Author: Stephen Warren <swarren@nvidia.com>
   5  * Copyright (C) 2010 - NVIDIA, Inc.
   6  *
   7  * Based on code copyright/by:
   8  *
   9  * Copyright (c) 2009-2010, NVIDIA Corporation.
  10  * Scott Peterson <speterson@nvidia.com>
  11  *
  12  * Copyright (C) 2010 Google, Inc.
  13  * Iliyan Malchev <malchev@google.com>
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * version 2 as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope that it will be useful, but
  20  * WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  22  * General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  27  * 02110-1301 USA
  28  *
  29  */
  30
  31 #include <linux/clk.h>
  32 #include <linux/module.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/device.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/slab.h>
  38 #include <linux/io.h>
  39 #include <linux/of.h>
  40 #include <mach/iomap.h>
  41 #include <sound/core.h>
  42 #include <sound/pcm.h>
  43 #include <sound/pcm_params.h>
  44 #include <sound/soc.h>
  45
  46 #include "tegra_i2s.h"
  47
  48 #define DRV_NAME "tegra-i2s"
  49
  50 static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
  51 {
  52         __raw_writel(val, i2s->regs + reg);
  53 }
  54
  55 static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
  56 {
  57         return __raw_readl(i2s->regs + reg);
  58 }
  59
  60 #ifdef CONFIG_DEBUG_FS
  61 static int tegra_i2s_show(struct seq_file *s, void *unused)
  62 {
  63 #define REG(r) { r, #r }
  64         static const struct {
  65                 int offset;
  66                 const char *name;
  67         } regs[] = {
  68                 REG(TEGRA_I2S_CTRL),
  69                 REG(TEGRA_I2S_STATUS),
  70                 REG(TEGRA_I2S_TIMING),
  71                 REG(TEGRA_I2S_FIFO_SCR),
  72                 REG(TEGRA_I2S_PCM_CTRL),
  73                 REG(TEGRA_I2S_NW_CTRL),
  74                 REG(TEGRA_I2S_TDM_CTRL),
  75                 REG(TEGRA_I2S_TDM_TX_RX_CTRL),
  76         };
  77 #undef REG
  78
  79         struct tegra_i2s *i2s = s->private;
  80         int i;
  81
  82         clk_enable(i2s->clk_i2s);
  83
  84         for (i = 0; i < ARRAY_SIZE(regs); i++) {
  85                 u32 val = tegra_i2s_read(i2s, regs[i].offset);
  86                 seq_printf(s, "%s = %08x\n", regs[i].name, val);
  87         }
  88
  89         clk_disable(i2s->clk_i2s);
  90
  91         return 0;
  92 }
  93
  94 static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
  95 {
  96         return single_open(file, tegra_i2s_show, inode->i_private);
  97 }
  98
  99 static const struct file_operations tegra_i2s_debug_fops = {
 100         .open    = tegra_i2s_debug_open,
 101         .read    = seq_read,
 102         .llseek  = seq_lseek,
 103         .release = single_release,
 104 };
 105
 106 static void tegra_i2s_debug_add(struct tegra_i2s *i2s)
 107 {
 108         i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
 109                                          snd_soc_debugfs_root, i2s,
 110                                          &tegra_i2s_debug_fops);
 111 }
 112
 113 static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
 114 {
 115         if (i2s->debug)
 116                 debugfs_remove(i2s->debug);
 117 }
 118 #else
 119 static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s)
 120 {
 121 }
 122
 123 static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
 124 {
 125 }
 126 #endif
 127
 128 static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
 129                                 unsigned int fmt)
 130 {
 131         struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 132
 133         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 134         case SND_SOC_DAIFMT_NB_NF:
 135                 break;
 136         default:
 137                 return -EINVAL;
 138         }
 139
 140         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
 141         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 142         case SND_SOC_DAIFMT_CBS_CFS:
 143                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
 144                 break;
 145         case SND_SOC_DAIFMT_CBM_CFM:
 146                 break;
 147         default:
 148                 return -EINVAL;
 149         }
 150
 151         i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK |
 152                                 TEGRA_I2S_CTRL_LRCK_MASK);
 153         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 154         case SND_SOC_DAIFMT_DSP_A:
 155                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
 156                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 157                 break;
 158         case SND_SOC_DAIFMT_DSP_B:
 159                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
 160                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
 161                 break;
 162         case SND_SOC_DAIFMT_I2S:
 163                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
 164                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 165                 break;
 166         case SND_SOC_DAIFMT_RIGHT_J:
 167                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
 168                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 169                 break;
 170         case SND_SOC_DAIFMT_LEFT_J:
 171                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
 172                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 173                 break;
 174         default:
 175                 return -EINVAL;
 176         }
 177
 178         return 0;
 179 }
 180
 181 static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
 182                                 struct snd_pcm_hw_params *params,
 183                                 struct snd_soc_dai *dai)
 184 {
 185         struct device *dev = substream->pcm->card->dev;
 186         struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 187         u32 reg;
 188         int ret, sample_size, srate, i2sclock, bitcnt;
 189
 190         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
 191         switch (params_format(params)) {
 192         case SNDRV_PCM_FORMAT_S16_LE:
 193                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
 194                 sample_size = 16;
 195                 break;
 196         case SNDRV_PCM_FORMAT_S24_LE:
 197                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
 198                 sample_size = 24;
 199                 break;
 200         case SNDRV_PCM_FORMAT_S32_LE:
 201                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
 202                 sample_size = 32;
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         srate = params_rate(params);
 209
 210         /* Final "* 2" required by Tegra hardware */
 211         i2sclock = srate * params_channels(params) * sample_size * 2;
 212
 213         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
 214         if (ret) {
 215                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
 216                 return ret;
 217         }
 218
 219         bitcnt = (i2sclock / (2 * srate)) - 1;
 220         if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
 221                 return -EINVAL;
 222         reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
 223
 224         if (i2sclock % (2 * srate))
 225                 reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
 226
 227         if (!i2s->clk_refs)
 228                 clk_enable(i2s->clk_i2s);
 229
 230         tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
 231
 232         tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
 233                 TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
 234                 TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
 235
 236         if (!i2s->clk_refs)
 237                 clk_disable(i2s->clk_i2s);
 238
 239         return 0;
 240 }
 241
 242 static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
 243 {
 244         i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
 245         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 246 }
 247
 248 static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
 249 {
 250         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
 251         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 252 }
 253
 254 static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
 255 {
 256         i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
 257         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 258 }
 259
 260 static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
 261 {
 262         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
 263         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 264 }
 265
 266 static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 267                                 struct snd_soc_dai *dai)
 268 {
 269         struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 270
 271         switch (cmd) {
 272         case SNDRV_PCM_TRIGGER_START:
 273         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 274         case SNDRV_PCM_TRIGGER_RESUME:
 275                 if (!i2s->clk_refs)
 276                         clk_enable(i2s->clk_i2s);
 277                 i2s->clk_refs++;
 278                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 279                         tegra_i2s_start_playback(i2s);
 280                 else
 281                         tegra_i2s_start_capture(i2s);
 282                 break;
 283         case SNDRV_PCM_TRIGGER_STOP:
 284         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 285         case SNDRV_PCM_TRIGGER_SUSPEND:
 286                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 287                         tegra_i2s_stop_playback(i2s);
 288                 else
 289                         tegra_i2s_stop_capture(i2s);
 290                 i2s->clk_refs--;
 291                 if (!i2s->clk_refs)
 292                         clk_disable(i2s->clk_i2s);
 293                 break;
 294         default:
 295                 return -EINVAL;
 296         }
 297
 298         return 0;
 299 }
 300
 301 static int tegra_i2s_probe(struct snd_soc_dai *dai)
 302 {
 303         struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
 304
 305         dai->capture_dma_data = &i2s->capture_dma_data;
 306         dai->playback_dma_data = &i2s->playback_dma_data;
 307
 308         return 0;
 309 }
 310
 311 static const struct snd_soc_dai_ops tegra_i2s_dai_ops = {
 312         .set_fmt        = tegra_i2s_set_fmt,
 313         .hw_params      = tegra_i2s_hw_params,
 314         .trigger        = tegra_i2s_trigger,
 315 };
 316
 317 static const struct snd_soc_dai_driver tegra_i2s_dai_template = {
 318         .probe = tegra_i2s_probe,
 319         .playback = {
 320                 .channels_min = 2,
 321                 .channels_max = 2,
 322                 .rates = SNDRV_PCM_RATE_8000_96000,
 323                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 324         },
 325         .capture = {
 326                 .channels_min = 2,
 327                 .channels_max = 2,
 328                 .rates = SNDRV_PCM_RATE_8000_96000,
 329                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 330         },
 331         .ops = &tegra_i2s_dai_ops,
 332         .symmetric_rates = 1,
 333 };
 334
 335 static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
 336 {
 337         struct tegra_i2s * i2s;
 338         struct resource *mem, *memregion, *dmareq;
 339         u32 of_dma[2];
 340         u32 dma_ch;
 341         int ret;
 342
 343         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL);
 344         if (!i2s) {
 345                 dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
 346                 ret = -ENOMEM;
 347                 goto err;
 348         }
 349         dev_set_drvdata(&pdev->dev, i2s);
 350
 351         i2s->dai = tegra_i2s_dai_template;
 352         i2s->dai.name = dev_name(&pdev->dev);
 353
 354         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
 355         if (IS_ERR(i2s->clk_i2s)) {
 356                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 357                 ret = PTR_ERR(i2s->clk_i2s);
 358                 goto err;
 359         }
 360
 361         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 362         if (!mem) {
 363                 dev_err(&pdev->dev, "No memory resource\n");
 364                 ret = -ENODEV;
 365                 goto err_clk_put;
 366         }
 367
 368         dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 369         if (!dmareq) {
 370                 if (of_property_read_u32_array(pdev->dev.of_node,
 371                                         "nvidia,dma-request-selector",
 372                                         of_dma, 2) < 0) {
 373                         dev_err(&pdev->dev, "No DMA resource\n");
 374                         ret = -ENODEV;
 375                         goto err_clk_put;
 376                 }
 377                 dma_ch = of_dma[1];
 378         } else {
 379                 dma_ch = dmareq->start;
 380         }
 381
 382         memregion = devm_request_mem_region(&pdev->dev, mem->start,
 383                                             resource_size(mem), DRV_NAME);
 384         if (!memregion) {
 385                 dev_err(&pdev->dev, "Memory region already claimed\n");
 386                 ret = -EBUSY;
 387                 goto err_clk_put;
 388         }
 389
 390         i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
 391         if (!i2s->regs) {
 392                 dev_err(&pdev->dev, "ioremap failed\n");
 393                 ret = -ENOMEM;
 394                 goto err_clk_put;
 395         }
 396
 397         i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
 398         i2s->capture_dma_data.wrap = 4;
 399         i2s->capture_dma_data.width = 32;
 400         i2s->capture_dma_data.req_sel = dma_ch;
 401
 402         i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
 403         i2s->playback_dma_data.wrap = 4;
 404         i2s->playback_dma_data.width = 32;
 405         i2s->playback_dma_data.req_sel = dma_ch;
 406
 407         i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
 408
 409         ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
 410         if (ret) {
 411                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 412                 ret = -ENOMEM;
 413                 goto err_clk_put;
 414         }
 415
 416         tegra_i2s_debug_add(i2s);
 417
 418         return 0;
 419
 420 err_clk_put:
 421         clk_put(i2s->clk_i2s);
 422 err:
 423         return ret;
 424 }
 425
 426 static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
 427 {
 428         struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
 429
 430         snd_soc_unregister_dai(&pdev->dev);
 431
 432         tegra_i2s_debug_remove(i2s);
 433
 434         clk_put(i2s->clk_i2s);
 435
 436         return 0;
 437 }
 438
 439 static const struct of_device_id tegra_i2s_of_match[] __devinitconst = {
 440         { .compatible = "nvidia,tegra20-i2s", },
 441         {},
 442 };
 443
 444 static struct platform_driver tegra_i2s_driver = {
 445         .driver = {
 446                 .name = DRV_NAME,
 447                 .owner = THIS_MODULE,
 448                 .of_match_table = tegra_i2s_of_match,
 449         },
 450         .probe = tegra_i2s_platform_probe,
 451         .remove = __devexit_p(tegra_i2s_platform_remove),
 452 };
 453 module_platform_driver(tegra_i2s_driver);
 454
 455 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 456 MODULE_DESCRIPTION("Tegra I2S ASoC driver");
 457 MODULE_LICENSE("GPL");
 458 MODULE_ALIAS("platform:" DRV_NAME);
 459 MODULE_DEVICE_TABLE(of, tegra_i2s_of_match);