arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/gpio.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/fsmc.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/consumer.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/dma-mapping.h>
  33
  34 #include <asm/types.h>
  35 #include <asm/setup.h>
  36 #include <asm/memory.h>
  37 #include <asm/hardware/vic.h>
  38 #include <asm/mach/map.h>
  39 #include <asm/mach/irq.h>
  40
  41 #include <mach/coh901318.h>
  42 #include <mach/hardware.h>
  43 #include <mach/syscon.h>
  44 #include <mach/dma_channels.h>
  45 #include <mach/gpio-u300.h>
  46
  47 #include "clock.h"
  48 #include "spi.h"
  49 #include "i2c.h"
  50 #include "u300-gpio.h"
  51
  52 /*
  53  * Static I/O mappings that are needed for booting the U300 platforms. The
  54  * only things we need are the areas where we find the timer, syscon and
  55  * intcon, since the remaining device drivers will map their own memory
  56  * physical to virtual as the need arise.
  57  */
  58 static struct map_desc u300_io_desc[] __initdata = {
  59         {
  60                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  61                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  62                 .length         = SZ_64K,
  63                 .type           = MT_DEVICE,
  64         },
  65         {
  66                 .virtual        = U300_AHB_PER_VIRT_BASE,
  67                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  68                 .length         = SZ_32K,
  69                 .type           = MT_DEVICE,
  70         },
  71         {
  72                 .virtual        = U300_FAST_PER_VIRT_BASE,
  73                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  74                 .length         = SZ_32K,
  75                 .type           = MT_DEVICE,
  76         },
  77 };
  78
  79 void __init u300_map_io(void)
  80 {
  81         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  82         /* We enable a real big DMA buffer if need be. */
  83         init_consistent_dma_size(SZ_4M);
  84 }
  85
  86 /*
  87  * Declaration of devices found on the U300 board and
  88  * their respective memory locations.
  89  */
  90
  91 static struct amba_pl011_data uart0_plat_data = {
  92 #ifdef CONFIG_COH901318
  93         .dma_filter = coh901318_filter_id,
  94         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  95         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  96 #endif
  97 };
  98
  99 /* Slow device at 0x3000 offset */
 100 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 101         { IRQ_U300_UART0 }, &uart0_plat_data);
 102
 103 /* The U335 have an additional UART1 on the APP CPU */
 104 #ifdef CONFIG_MACH_U300_BS335
 105 static struct amba_pl011_data uart1_plat_data = {
 106 #ifdef CONFIG_COH901318
 107         .dma_filter = coh901318_filter_id,
 108         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 109         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 110 #endif
 111 };
 112
 113 /* Fast device at 0x7000 offset */
 114 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 115         { IRQ_U300_UART1 }, &uart1_plat_data);
 116 #endif
 117
 118 /* AHB device at 0x4000 offset */
 119 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 120
 121 /* Fast device at 0x6000 offset */
 122 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
 123         { IRQ_U300_SPI }, NULL);
 124
 125 /* Fast device at 0x1000 offset */
 126 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 127
 128 static struct mmci_platform_data mmcsd_platform_data = {
 129         /*
 130          * Do not set ocr_mask or voltage translation function,
 131          * we have a regulator we can control instead.
 132          */
 133         .f_max = 24000000,
 134         .gpio_wp = -1,
 135         .gpio_cd = U300_GPIO_PIN_MMC_CD,
 136         .cd_invert = true,
 137         .capabilities = MMC_CAP_MMC_HIGHSPEED |
 138         MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 139 #ifdef CONFIG_COH901318
 140         .dma_filter = coh901318_filter_id,
 141         .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
 142         /* Don't specify a TX channel, this RX channel is bidirectional */
 143 #endif
 144 };
 145
 146 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 147         U300_MMCSD_IRQS, &mmcsd_platform_data);
 148
 149 /*
 150  * The order of device declaration may be important, since some devices
 151  * have dependencies on other devices being initialized first.
 152  */
 153 static struct amba_device *amba_devs[] __initdata = {
 154         &uart0_device,
 155 #ifdef CONFIG_MACH_U300_BS335
 156         &uart1_device,
 157 #endif
 158         &pl022_device,
 159         &pl172_device,
 160         &mmcsd_device,
 161 };
 162
 163 /* Here follows a list of all hw resources that the platform devices
 164  * allocate. Note, clock dependencies are not included
 165  */
 166
 167 static struct resource gpio_resources[] = {
 168         {
 169                 .start = U300_GPIO_BASE,
 170                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 171                 .flags = IORESOURCE_MEM,
 172         },
 173         {
 174                 .name  = "gpio0",
 175                 .start = IRQ_U300_GPIO_PORT0,
 176                 .end   = IRQ_U300_GPIO_PORT0,
 177                 .flags = IORESOURCE_IRQ,
 178         },
 179         {
 180                 .name  = "gpio1",
 181                 .start = IRQ_U300_GPIO_PORT1,
 182                 .end   = IRQ_U300_GPIO_PORT1,
 183                 .flags = IORESOURCE_IRQ,
 184         },
 185         {
 186                 .name  = "gpio2",
 187                 .start = IRQ_U300_GPIO_PORT2,
 188                 .end   = IRQ_U300_GPIO_PORT2,
 189                 .flags = IORESOURCE_IRQ,
 190         },
 191 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
 192         {
 193                 .name  = "gpio3",
 194                 .start = IRQ_U300_GPIO_PORT3,
 195                 .end   = IRQ_U300_GPIO_PORT3,
 196                 .flags = IORESOURCE_IRQ,
 197         },
 198         {
 199                 .name  = "gpio4",
 200                 .start = IRQ_U300_GPIO_PORT4,
 201                 .end   = IRQ_U300_GPIO_PORT4,
 202                 .flags = IORESOURCE_IRQ,
 203         },
 204 #endif
 205 #ifdef CONFIG_MACH_U300_BS335
 206         {
 207                 .name  = "gpio5",
 208                 .start = IRQ_U300_GPIO_PORT5,
 209                 .end   = IRQ_U300_GPIO_PORT5,
 210                 .flags = IORESOURCE_IRQ,
 211         },
 212         {
 213                 .name  = "gpio6",
 214                 .start = IRQ_U300_GPIO_PORT6,
 215                 .end   = IRQ_U300_GPIO_PORT6,
 216                 .flags = IORESOURCE_IRQ,
 217         },
 218 #endif /* CONFIG_MACH_U300_BS335 */
 219 };
 220
 221 static struct resource keypad_resources[] = {
 222         {
 223                 .start = U300_KEYPAD_BASE,
 224                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 225                 .flags = IORESOURCE_MEM,
 226         },
 227         {
 228                 .name  = "coh901461-press",
 229                 .start = IRQ_U300_KEYPAD_KEYBF,
 230                 .end   = IRQ_U300_KEYPAD_KEYBF,
 231                 .flags = IORESOURCE_IRQ,
 232         },
 233         {
 234                 .name  = "coh901461-release",
 235                 .start = IRQ_U300_KEYPAD_KEYBR,
 236                 .end   = IRQ_U300_KEYPAD_KEYBR,
 237                 .flags = IORESOURCE_IRQ,
 238         },
 239 };
 240
 241 static struct resource rtc_resources[] = {
 242         {
 243                 .start = U300_RTC_BASE,
 244                 .end   = U300_RTC_BASE + SZ_4K - 1,
 245                 .flags = IORESOURCE_MEM,
 246         },
 247         {
 248                 .start = IRQ_U300_RTC,
 249                 .end   = IRQ_U300_RTC,
 250                 .flags = IORESOURCE_IRQ,
 251         },
 252 };
 253
 254 /*
 255  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 256  * but these are not yet used by the driver.
 257  */
 258 static struct resource fsmc_resources[] = {
 259         {
 260                 .name  = "nand_data",
 261                 .start = U300_NAND_CS0_PHYS_BASE,
 262                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 263                 .flags = IORESOURCE_MEM,
 264         },
 265         {
 266                 .name  = "fsmc_regs",
 267                 .start = U300_NAND_IF_PHYS_BASE,
 268                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 269                 .flags = IORESOURCE_MEM,
 270         },
 271 };
 272
 273 static struct resource i2c0_resources[] = {
 274         {
 275                 .start = U300_I2C0_BASE,
 276                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 277                 .flags = IORESOURCE_MEM,
 278         },
 279         {
 280                 .start = IRQ_U300_I2C0,
 281                 .end   = IRQ_U300_I2C0,
 282                 .flags = IORESOURCE_IRQ,
 283         },
 284 };
 285
 286 static struct resource i2c1_resources[] = {
 287         {
 288                 .start = U300_I2C1_BASE,
 289                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 290                 .flags = IORESOURCE_MEM,
 291         },
 292         {
 293                 .start = IRQ_U300_I2C1,
 294                 .end   = IRQ_U300_I2C1,
 295                 .flags = IORESOURCE_IRQ,
 296         },
 297
 298 };
 299
 300 static struct resource wdog_resources[] = {
 301         {
 302                 .start = U300_WDOG_BASE,
 303                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 304                 .flags = IORESOURCE_MEM,
 305         },
 306         {
 307                 .start = IRQ_U300_WDOG,
 308                 .end   = IRQ_U300_WDOG,
 309                 .flags = IORESOURCE_IRQ,
 310         }
 311 };
 312
 313 static struct resource dma_resource[] = {
 314         {
 315                 .start = U300_DMAC_BASE,
 316                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 317                 .flags =  IORESOURCE_MEM,
 318         },
 319         {
 320                 .start = IRQ_U300_DMA,
 321                 .end = IRQ_U300_DMA,
 322                 .flags =  IORESOURCE_IRQ,
 323         }
 324 };
 325
 326 #ifdef CONFIG_MACH_U300_BS335
 327 /* points out all dma slave channels.
 328  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 329  * Select all channels from A to B, end of list is marked with -1,-1
 330  */
 331 static int dma_slave_channels[] = {
 332         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 333         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 334
 335 /* points out all dma memcpy channels. */
 336 static int dma_memcpy_channels[] = {
 337         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 338
 339 #else /* CONFIG_MACH_U300_BS335 */
 340
 341 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 342 static int dma_memcpy_channels[] = {
 343         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 344
 345 #endif
 346
 347 /** register dma for memory access
 348  *
 349  * active  1 means dma intends to access memory
 350  *         0 means dma wont access memory
 351  */
 352 static void coh901318_access_memory_state(struct device *dev, bool active)
 353 {
 354 }
 355
 356 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 357                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 358                         COH901318_CX_CFG_LCR_DISABLE | \
 359                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 360                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 361 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 362                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 363                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 364                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 365                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 366                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 367                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 368                         COH901318_CX_CTRL_TCP_DISABLE | \
 369                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 370                         COH901318_CX_CTRL_HSP_DISABLE | \
 371                         COH901318_CX_CTRL_HSS_DISABLE | \
 372                         COH901318_CX_CTRL_DDMA_LEGACY | \
 373                         COH901318_CX_CTRL_PRDD_SOURCE)
 374 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 375                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 376                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 377                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 378                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 379                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 380                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 381                         COH901318_CX_CTRL_TCP_DISABLE | \
 382                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 383                         COH901318_CX_CTRL_HSP_DISABLE | \
 384                         COH901318_CX_CTRL_HSS_DISABLE | \
 385                         COH901318_CX_CTRL_DDMA_LEGACY | \
 386                         COH901318_CX_CTRL_PRDD_SOURCE)
 387 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 388                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 389                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 390                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 391                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 392                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 393                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 394                         COH901318_CX_CTRL_TCP_DISABLE | \
 395                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 396                         COH901318_CX_CTRL_HSP_DISABLE | \
 397                         COH901318_CX_CTRL_HSS_DISABLE | \
 398                         COH901318_CX_CTRL_DDMA_LEGACY | \
 399                         COH901318_CX_CTRL_PRDD_SOURCE)
 400
 401 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 402         {
 403                 .number = U300_DMA_MSL_TX_0,
 404                 .name = "MSL TX 0",
 405                 .priority_high = 0,
 406                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 407         },
 408         {
 409                 .number = U300_DMA_MSL_TX_1,
 410                 .name = "MSL TX 1",
 411                 .priority_high = 0,
 412                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 413                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 414                                 COH901318_CX_CFG_LCR_DISABLE |
 415                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 416                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 417                 .param.ctrl_lli_chained = 0 |
 418                                 COH901318_CX_CTRL_TC_ENABLE |
 419                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 420                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 421                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 422                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 423                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 424                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 425                                 COH901318_CX_CTRL_TCP_DISABLE |
 426                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 427                                 COH901318_CX_CTRL_HSP_ENABLE |
 428                                 COH901318_CX_CTRL_HSS_DISABLE |
 429                                 COH901318_CX_CTRL_DDMA_LEGACY |
 430                                 COH901318_CX_CTRL_PRDD_SOURCE,
 431                 .param.ctrl_lli = 0 |
 432                                 COH901318_CX_CTRL_TC_ENABLE |
 433                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 434                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 435                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 436                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 437                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 438                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 439                                 COH901318_CX_CTRL_TCP_ENABLE |
 440                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 441                                 COH901318_CX_CTRL_HSP_ENABLE |
 442                                 COH901318_CX_CTRL_HSS_DISABLE |
 443                                 COH901318_CX_CTRL_DDMA_LEGACY |
 444                                 COH901318_CX_CTRL_PRDD_SOURCE,
 445                 .param.ctrl_lli_last = 0 |
 446                                 COH901318_CX_CTRL_TC_ENABLE |
 447                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 448                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 449                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 450                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 451                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 452                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 453                                 COH901318_CX_CTRL_TCP_ENABLE |
 454                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 455                                 COH901318_CX_CTRL_HSP_ENABLE |
 456                                 COH901318_CX_CTRL_HSS_DISABLE |
 457                                 COH901318_CX_CTRL_DDMA_LEGACY |
 458                                 COH901318_CX_CTRL_PRDD_SOURCE,
 459         },
 460         {
 461                 .number = U300_DMA_MSL_TX_2,
 462                 .name = "MSL TX 2",
 463                 .priority_high = 0,
 464                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 465                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 466                                 COH901318_CX_CFG_LCR_DISABLE |
 467                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 468                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 469                 .param.ctrl_lli_chained = 0 |
 470                                 COH901318_CX_CTRL_TC_ENABLE |
 471                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 472                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 473                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 474                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 475                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 476                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 477                                 COH901318_CX_CTRL_TCP_DISABLE |
 478                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 479                                 COH901318_CX_CTRL_HSP_ENABLE |
 480                                 COH901318_CX_CTRL_HSS_DISABLE |
 481                                 COH901318_CX_CTRL_DDMA_LEGACY |
 482                                 COH901318_CX_CTRL_PRDD_SOURCE,
 483                 .param.ctrl_lli = 0 |
 484                                 COH901318_CX_CTRL_TC_ENABLE |
 485                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 486                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 487                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 488                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 489                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 490                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 491                                 COH901318_CX_CTRL_TCP_ENABLE |
 492                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 493                                 COH901318_CX_CTRL_HSP_ENABLE |
 494                                 COH901318_CX_CTRL_HSS_DISABLE |
 495                                 COH901318_CX_CTRL_DDMA_LEGACY |
 496                                 COH901318_CX_CTRL_PRDD_SOURCE,
 497                 .param.ctrl_lli_last = 0 |
 498                                 COH901318_CX_CTRL_TC_ENABLE |
 499                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 500                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 501                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 502                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 503                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 504                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 505                                 COH901318_CX_CTRL_TCP_ENABLE |
 506                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 507                                 COH901318_CX_CTRL_HSP_ENABLE |
 508                                 COH901318_CX_CTRL_HSS_DISABLE |
 509                                 COH901318_CX_CTRL_DDMA_LEGACY |
 510                                 COH901318_CX_CTRL_PRDD_SOURCE,
 511                 .desc_nbr_max = 10,
 512         },
 513         {
 514                 .number = U300_DMA_MSL_TX_3,
 515                 .name = "MSL TX 3",
 516                 .priority_high = 0,
 517                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 518                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 519                                 COH901318_CX_CFG_LCR_DISABLE |
 520                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 521                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 522                 .param.ctrl_lli_chained = 0 |
 523                                 COH901318_CX_CTRL_TC_ENABLE |
 524                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 525                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 526                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 527                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 528                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 529                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 530                                 COH901318_CX_CTRL_TCP_DISABLE |
 531                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 532                                 COH901318_CX_CTRL_HSP_ENABLE |
 533                                 COH901318_CX_CTRL_HSS_DISABLE |
 534                                 COH901318_CX_CTRL_DDMA_LEGACY |
 535                                 COH901318_CX_CTRL_PRDD_SOURCE,
 536                 .param.ctrl_lli = 0 |
 537                                 COH901318_CX_CTRL_TC_ENABLE |
 538                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 539                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 540                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 541                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 542                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 543                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 544                                 COH901318_CX_CTRL_TCP_ENABLE |
 545                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 546                                 COH901318_CX_CTRL_HSP_ENABLE |
 547                                 COH901318_CX_CTRL_HSS_DISABLE |
 548                                 COH901318_CX_CTRL_DDMA_LEGACY |
 549                                 COH901318_CX_CTRL_PRDD_SOURCE,
 550                 .param.ctrl_lli_last = 0 |
 551                                 COH901318_CX_CTRL_TC_ENABLE |
 552                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 553                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 554                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 555                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 556                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 557                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 558                                 COH901318_CX_CTRL_TCP_ENABLE |
 559                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 560                                 COH901318_CX_CTRL_HSP_ENABLE |
 561                                 COH901318_CX_CTRL_HSS_DISABLE |
 562                                 COH901318_CX_CTRL_DDMA_LEGACY |
 563                                 COH901318_CX_CTRL_PRDD_SOURCE,
 564         },
 565         {
 566                 .number = U300_DMA_MSL_TX_4,
 567                 .name = "MSL TX 4",
 568                 .priority_high = 0,
 569                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 570                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 571                                 COH901318_CX_CFG_LCR_DISABLE |
 572                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 573                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 574                 .param.ctrl_lli_chained = 0 |
 575                                 COH901318_CX_CTRL_TC_ENABLE |
 576                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 577                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 578                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 579                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 580                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 581                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 582                                 COH901318_CX_CTRL_TCP_DISABLE |
 583                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 584                                 COH901318_CX_CTRL_HSP_ENABLE |
 585                                 COH901318_CX_CTRL_HSS_DISABLE |
 586                                 COH901318_CX_CTRL_DDMA_LEGACY |
 587                                 COH901318_CX_CTRL_PRDD_SOURCE,
 588                 .param.ctrl_lli = 0 |
 589                                 COH901318_CX_CTRL_TC_ENABLE |
 590                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 591                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 592                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 593                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 594                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 595                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 596                                 COH901318_CX_CTRL_TCP_ENABLE |
 597                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 598                                 COH901318_CX_CTRL_HSP_ENABLE |
 599                                 COH901318_CX_CTRL_HSS_DISABLE |
 600                                 COH901318_CX_CTRL_DDMA_LEGACY |
 601                                 COH901318_CX_CTRL_PRDD_SOURCE,
 602                 .param.ctrl_lli_last = 0 |
 603                                 COH901318_CX_CTRL_TC_ENABLE |
 604                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 605                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 606                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 607                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 608                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 609                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 610                                 COH901318_CX_CTRL_TCP_ENABLE |
 611                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 612                                 COH901318_CX_CTRL_HSP_ENABLE |
 613                                 COH901318_CX_CTRL_HSS_DISABLE |
 614                                 COH901318_CX_CTRL_DDMA_LEGACY |
 615                                 COH901318_CX_CTRL_PRDD_SOURCE,
 616         },
 617         {
 618                 .number = U300_DMA_MSL_TX_5,
 619                 .name = "MSL TX 5",
 620                 .priority_high = 0,
 621                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 622         },
 623         {
 624                 .number = U300_DMA_MSL_TX_6,
 625                 .name = "MSL TX 6",
 626                 .priority_high = 0,
 627                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 628         },
 629         {
 630                 .number = U300_DMA_MSL_RX_0,
 631                 .name = "MSL RX 0",
 632                 .priority_high = 0,
 633                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 634         },
 635         {
 636                 .number = U300_DMA_MSL_RX_1,
 637                 .name = "MSL RX 1",
 638                 .priority_high = 0,
 639                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 640                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 641                                 COH901318_CX_CFG_LCR_DISABLE |
 642                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 643                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 644                 .param.ctrl_lli_chained = 0 |
 645                                 COH901318_CX_CTRL_TC_ENABLE |
 646                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 647                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 648                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 649                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 650                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 651                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 652                                 COH901318_CX_CTRL_TCP_DISABLE |
 653                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 654                                 COH901318_CX_CTRL_HSP_ENABLE |
 655                                 COH901318_CX_CTRL_HSS_DISABLE |
 656                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 657                                 COH901318_CX_CTRL_PRDD_DEST,
 658                 .param.ctrl_lli = 0,
 659                 .param.ctrl_lli_last = 0 |
 660                                 COH901318_CX_CTRL_TC_ENABLE |
 661                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 662                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 663                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 664                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 665                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 666                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 667                                 COH901318_CX_CTRL_TCP_DISABLE |
 668                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 669                                 COH901318_CX_CTRL_HSP_ENABLE |
 670                                 COH901318_CX_CTRL_HSS_DISABLE |
 671                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 672                                 COH901318_CX_CTRL_PRDD_DEST,
 673         },
 674         {
 675                 .number = U300_DMA_MSL_RX_2,
 676                 .name = "MSL RX 2",
 677                 .priority_high = 0,
 678                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 679                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 680                                 COH901318_CX_CFG_LCR_DISABLE |
 681                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 682                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 683                 .param.ctrl_lli_chained = 0 |
 684                                 COH901318_CX_CTRL_TC_ENABLE |
 685                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 686                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 687                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 688                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 689                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 690                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 691                                 COH901318_CX_CTRL_TCP_DISABLE |
 692                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 693                                 COH901318_CX_CTRL_HSP_ENABLE |
 694                                 COH901318_CX_CTRL_HSS_DISABLE |
 695                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 696                                 COH901318_CX_CTRL_PRDD_DEST,
 697                 .param.ctrl_lli = 0 |
 698                                 COH901318_CX_CTRL_TC_ENABLE |
 699                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 700                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 701                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 702                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 703                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 704                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 705                                 COH901318_CX_CTRL_TCP_DISABLE |
 706                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 707                                 COH901318_CX_CTRL_HSP_ENABLE |
 708                                 COH901318_CX_CTRL_HSS_DISABLE |
 709                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 710                                 COH901318_CX_CTRL_PRDD_DEST,
 711                 .param.ctrl_lli_last = 0 |
 712                                 COH901318_CX_CTRL_TC_ENABLE |
 713                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 714                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 715                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 716                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 717                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 718                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 719                                 COH901318_CX_CTRL_TCP_DISABLE |
 720                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 721                                 COH901318_CX_CTRL_HSP_ENABLE |
 722                                 COH901318_CX_CTRL_HSS_DISABLE |
 723                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 724                                 COH901318_CX_CTRL_PRDD_DEST,
 725         },
 726         {
 727                 .number = U300_DMA_MSL_RX_3,
 728                 .name = "MSL RX 3",
 729                 .priority_high = 0,
 730                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 731                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 732                                 COH901318_CX_CFG_LCR_DISABLE |
 733                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 734                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 735                 .param.ctrl_lli_chained = 0 |
 736                                 COH901318_CX_CTRL_TC_ENABLE |
 737                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 738                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 739                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 740                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 741                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 742                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 743                                 COH901318_CX_CTRL_TCP_DISABLE |
 744                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 745                                 COH901318_CX_CTRL_HSP_ENABLE |
 746                                 COH901318_CX_CTRL_HSS_DISABLE |
 747                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 748                                 COH901318_CX_CTRL_PRDD_DEST,
 749                 .param.ctrl_lli = 0 |
 750                                 COH901318_CX_CTRL_TC_ENABLE |
 751                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 752                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 753                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 754                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 755                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 756                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 757                                 COH901318_CX_CTRL_TCP_DISABLE |
 758                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 759                                 COH901318_CX_CTRL_HSP_ENABLE |
 760                                 COH901318_CX_CTRL_HSS_DISABLE |
 761                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 762                                 COH901318_CX_CTRL_PRDD_DEST,
 763                 .param.ctrl_lli_last = 0 |
 764                                 COH901318_CX_CTRL_TC_ENABLE |
 765                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 766                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 767                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 768                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 769                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 770                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 771                                 COH901318_CX_CTRL_TCP_DISABLE |
 772                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 773                                 COH901318_CX_CTRL_HSP_ENABLE |
 774                                 COH901318_CX_CTRL_HSS_DISABLE |
 775                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 776                                 COH901318_CX_CTRL_PRDD_DEST,
 777         },
 778         {
 779                 .number = U300_DMA_MSL_RX_4,
 780                 .name = "MSL RX 4",
 781                 .priority_high = 0,
 782                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 783                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 784                                 COH901318_CX_CFG_LCR_DISABLE |
 785                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 786                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 787                 .param.ctrl_lli_chained = 0 |
 788                                 COH901318_CX_CTRL_TC_ENABLE |
 789                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 790                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 791                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 792                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 793                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 794                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 795                                 COH901318_CX_CTRL_TCP_DISABLE |
 796                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 797                                 COH901318_CX_CTRL_HSP_ENABLE |
 798                                 COH901318_CX_CTRL_HSS_DISABLE |
 799                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 800                                 COH901318_CX_CTRL_PRDD_DEST,
 801                 .param.ctrl_lli = 0 |
 802                                 COH901318_CX_CTRL_TC_ENABLE |
 803                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 804                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 805                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 806                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 807                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 808                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 809                                 COH901318_CX_CTRL_TCP_DISABLE |
 810                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 811                                 COH901318_CX_CTRL_HSP_ENABLE |
 812                                 COH901318_CX_CTRL_HSS_DISABLE |
 813                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 814                                 COH901318_CX_CTRL_PRDD_DEST,
 815                 .param.ctrl_lli_last = 0 |
 816                                 COH901318_CX_CTRL_TC_ENABLE |
 817                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 818                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 819                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 820                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 821                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 822                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 823                                 COH901318_CX_CTRL_TCP_DISABLE |
 824                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 825                                 COH901318_CX_CTRL_HSP_ENABLE |
 826                                 COH901318_CX_CTRL_HSS_DISABLE |
 827                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 828                                 COH901318_CX_CTRL_PRDD_DEST,
 829         },
 830         {
 831                 .number = U300_DMA_MSL_RX_5,
 832                 .name = "MSL RX 5",
 833                 .priority_high = 0,
 834                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 835                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 836                                 COH901318_CX_CFG_LCR_DISABLE |
 837                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 838                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 839                 .param.ctrl_lli_chained = 0 |
 840                                 COH901318_CX_CTRL_TC_ENABLE |
 841                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 842                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 843                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 844                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 845                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 846                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 847                                 COH901318_CX_CTRL_TCP_DISABLE |
 848                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 849                                 COH901318_CX_CTRL_HSP_ENABLE |
 850                                 COH901318_CX_CTRL_HSS_DISABLE |
 851                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 852                                 COH901318_CX_CTRL_PRDD_DEST,
 853                 .param.ctrl_lli = 0 |
 854                                 COH901318_CX_CTRL_TC_ENABLE |
 855                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 856                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 857                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 858                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 859                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 860                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 861                                 COH901318_CX_CTRL_TCP_DISABLE |
 862                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 863                                 COH901318_CX_CTRL_HSP_ENABLE |
 864                                 COH901318_CX_CTRL_HSS_DISABLE |
 865                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 866                                 COH901318_CX_CTRL_PRDD_DEST,
 867                 .param.ctrl_lli_last = 0 |
 868                                 COH901318_CX_CTRL_TC_ENABLE |
 869                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 870                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 871                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 872                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 873                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 874                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 875                                 COH901318_CX_CTRL_TCP_DISABLE |
 876                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 877                                 COH901318_CX_CTRL_HSP_ENABLE |
 878                                 COH901318_CX_CTRL_HSS_DISABLE |
 879                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 880                                 COH901318_CX_CTRL_PRDD_DEST,
 881         },
 882         {
 883                 .number = U300_DMA_MSL_RX_6,
 884                 .name = "MSL RX 6",
 885                 .priority_high = 0,
 886                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 887         },
 888         /*
 889          * Don't set up device address, burst count or size of src
 890          * or dst bus for this peripheral - handled by PrimeCell
 891          * DMA extension.
 892          */
 893         {
 894                 .number = U300_DMA_MMCSD_RX_TX,
 895                 .name = "MMCSD RX TX",
 896                 .priority_high = 0,
 897                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 898                                 COH901318_CX_CFG_LCR_DISABLE |
 899                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 900                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 901                 .param.ctrl_lli_chained = 0 |
 902                                 COH901318_CX_CTRL_TC_ENABLE |
 903                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 904                                 COH901318_CX_CTRL_TCP_ENABLE |
 905                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 906                                 COH901318_CX_CTRL_HSP_ENABLE |
 907                                 COH901318_CX_CTRL_HSS_DISABLE |
 908                                 COH901318_CX_CTRL_DDMA_LEGACY,
 909                 .param.ctrl_lli = 0 |
 910                                 COH901318_CX_CTRL_TC_ENABLE |
 911                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 912                                 COH901318_CX_CTRL_TCP_ENABLE |
 913                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 914                                 COH901318_CX_CTRL_HSP_ENABLE |
 915                                 COH901318_CX_CTRL_HSS_DISABLE |
 916                                 COH901318_CX_CTRL_DDMA_LEGACY,
 917                 .param.ctrl_lli_last = 0 |
 918                                 COH901318_CX_CTRL_TC_ENABLE |
 919                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 920                                 COH901318_CX_CTRL_TCP_DISABLE |
 921                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 922                                 COH901318_CX_CTRL_HSP_ENABLE |
 923                                 COH901318_CX_CTRL_HSS_DISABLE |
 924                                 COH901318_CX_CTRL_DDMA_LEGACY,
 925
 926         },
 927         {
 928                 .number = U300_DMA_MSPRO_TX,
 929                 .name = "MSPRO TX",
 930                 .priority_high = 0,
 931         },
 932         {
 933                 .number = U300_DMA_MSPRO_RX,
 934                 .name = "MSPRO RX",
 935                 .priority_high = 0,
 936         },
 937         /*
 938          * Don't set up device address, burst count or size of src
 939          * or dst bus for this peripheral - handled by PrimeCell
 940          * DMA extension.
 941          */
 942         {
 943                 .number = U300_DMA_UART0_TX,
 944                 .name = "UART0 TX",
 945                 .priority_high = 0,
 946                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 947                                 COH901318_CX_CFG_LCR_DISABLE |
 948                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 949                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 950                 .param.ctrl_lli_chained = 0 |
 951                                 COH901318_CX_CTRL_TC_ENABLE |
 952                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 953                                 COH901318_CX_CTRL_TCP_ENABLE |
 954                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 955                                 COH901318_CX_CTRL_HSP_ENABLE |
 956                                 COH901318_CX_CTRL_HSS_DISABLE |
 957                                 COH901318_CX_CTRL_DDMA_LEGACY,
 958                 .param.ctrl_lli = 0 |
 959                                 COH901318_CX_CTRL_TC_ENABLE |
 960                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 961                                 COH901318_CX_CTRL_TCP_ENABLE |
 962                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 963                                 COH901318_CX_CTRL_HSP_ENABLE |
 964                                 COH901318_CX_CTRL_HSS_DISABLE |
 965                                 COH901318_CX_CTRL_DDMA_LEGACY,
 966                 .param.ctrl_lli_last = 0 |
 967                                 COH901318_CX_CTRL_TC_ENABLE |
 968                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 969                                 COH901318_CX_CTRL_TCP_ENABLE |
 970                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 971                                 COH901318_CX_CTRL_HSP_ENABLE |
 972                                 COH901318_CX_CTRL_HSS_DISABLE |
 973                                 COH901318_CX_CTRL_DDMA_LEGACY,
 974         },
 975         {
 976                 .number = U300_DMA_UART0_RX,
 977                 .name = "UART0 RX",
 978                 .priority_high = 0,
 979                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 980                                 COH901318_CX_CFG_LCR_DISABLE |
 981                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 982                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 983                 .param.ctrl_lli_chained = 0 |
 984                                 COH901318_CX_CTRL_TC_ENABLE |
 985                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 986                                 COH901318_CX_CTRL_TCP_ENABLE |
 987                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 988                                 COH901318_CX_CTRL_HSP_ENABLE |
 989                                 COH901318_CX_CTRL_HSS_DISABLE |
 990                                 COH901318_CX_CTRL_DDMA_LEGACY,
 991                 .param.ctrl_lli = 0 |
 992                                 COH901318_CX_CTRL_TC_ENABLE |
 993                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 994                                 COH901318_CX_CTRL_TCP_ENABLE |
 995                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 996                                 COH901318_CX_CTRL_HSP_ENABLE |
 997                                 COH901318_CX_CTRL_HSS_DISABLE |
 998                                 COH901318_CX_CTRL_DDMA_LEGACY,
 999                 .param.ctrl_lli_last = 0 |
1000                                 COH901318_CX_CTRL_TC_ENABLE |
1001                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1002                                 COH901318_CX_CTRL_TCP_ENABLE |
1003                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1004                                 COH901318_CX_CTRL_HSP_ENABLE |
1005                                 COH901318_CX_CTRL_HSS_DISABLE |
1006                                 COH901318_CX_CTRL_DDMA_LEGACY,
1007         },
1008         {
1009                 .number = U300_DMA_APEX_TX,
1010                 .name = "APEX TX",
1011                 .priority_high = 0,
1012         },
1013         {
1014                 .number = U300_DMA_APEX_RX,
1015                 .name = "APEX RX",
1016                 .priority_high = 0,
1017         },
1018         {
1019                 .number = U300_DMA_PCM_I2S0_TX,
1020                 .name = "PCM I2S0 TX",
1021                 .priority_high = 1,
1022                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1023                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1024                                 COH901318_CX_CFG_LCR_DISABLE |
1025                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1026                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1027                 .param.ctrl_lli_chained = 0 |
1028                                 COH901318_CX_CTRL_TC_ENABLE |
1029                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1030                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1031                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1032                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1033                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1034                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1035                                 COH901318_CX_CTRL_TCP_DISABLE |
1036                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1037                                 COH901318_CX_CTRL_HSP_ENABLE |
1038                                 COH901318_CX_CTRL_HSS_DISABLE |
1039                                 COH901318_CX_CTRL_DDMA_LEGACY |
1040                                 COH901318_CX_CTRL_PRDD_SOURCE,
1041                 .param.ctrl_lli = 0 |
1042                                 COH901318_CX_CTRL_TC_ENABLE |
1043                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1044                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1045                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1046                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1047                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1048                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1049                                 COH901318_CX_CTRL_TCP_ENABLE |
1050                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1051                                 COH901318_CX_CTRL_HSP_ENABLE |
1052                                 COH901318_CX_CTRL_HSS_DISABLE |
1053                                 COH901318_CX_CTRL_DDMA_LEGACY |
1054                                 COH901318_CX_CTRL_PRDD_SOURCE,
1055                 .param.ctrl_lli_last = 0 |
1056                                 COH901318_CX_CTRL_TC_ENABLE |
1057                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1058                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1059                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1060                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1061                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1062                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1063                                 COH901318_CX_CTRL_TCP_ENABLE |
1064                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1065                                 COH901318_CX_CTRL_HSP_ENABLE |
1066                                 COH901318_CX_CTRL_HSS_DISABLE |
1067                                 COH901318_CX_CTRL_DDMA_LEGACY |
1068                                 COH901318_CX_CTRL_PRDD_SOURCE,
1069         },
1070         {
1071                 .number = U300_DMA_PCM_I2S0_RX,
1072                 .name = "PCM I2S0 RX",
1073                 .priority_high = 1,
1074                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1075                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1076                                 COH901318_CX_CFG_LCR_DISABLE |
1077                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1078                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1079                 .param.ctrl_lli_chained = 0 |
1080                                 COH901318_CX_CTRL_TC_ENABLE |
1081                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1082                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1083                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1084                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1085                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1086                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1087                                 COH901318_CX_CTRL_TCP_DISABLE |
1088                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1089                                 COH901318_CX_CTRL_HSP_ENABLE |
1090                                 COH901318_CX_CTRL_HSS_DISABLE |
1091                                 COH901318_CX_CTRL_DDMA_LEGACY |
1092                                 COH901318_CX_CTRL_PRDD_DEST,
1093                 .param.ctrl_lli = 0 |
1094                                 COH901318_CX_CTRL_TC_ENABLE |
1095                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1096                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1097                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1098                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1099                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1100                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1101                                 COH901318_CX_CTRL_TCP_ENABLE |
1102                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1103                                 COH901318_CX_CTRL_HSP_ENABLE |
1104                                 COH901318_CX_CTRL_HSS_DISABLE |
1105                                 COH901318_CX_CTRL_DDMA_LEGACY |
1106                                 COH901318_CX_CTRL_PRDD_DEST,
1107                 .param.ctrl_lli_last = 0 |
1108                                 COH901318_CX_CTRL_TC_ENABLE |
1109                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1110                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1111                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1112                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1113                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1114                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1115                                 COH901318_CX_CTRL_TCP_ENABLE |
1116                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1117                                 COH901318_CX_CTRL_HSP_ENABLE |
1118                                 COH901318_CX_CTRL_HSS_DISABLE |
1119                                 COH901318_CX_CTRL_DDMA_LEGACY |
1120                                 COH901318_CX_CTRL_PRDD_DEST,
1121         },
1122         {
1123                 .number = U300_DMA_PCM_I2S1_TX,
1124                 .name = "PCM I2S1 TX",
1125                 .priority_high = 1,
1126                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1127                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1128                                 COH901318_CX_CFG_LCR_DISABLE |
1129                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1130                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1131                 .param.ctrl_lli_chained = 0 |
1132                                 COH901318_CX_CTRL_TC_ENABLE |
1133                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1134                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1135                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1136                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1137                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1138                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1139                                 COH901318_CX_CTRL_TCP_DISABLE |
1140                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1141                                 COH901318_CX_CTRL_HSP_ENABLE |
1142                                 COH901318_CX_CTRL_HSS_DISABLE |
1143                                 COH901318_CX_CTRL_DDMA_LEGACY |
1144                                 COH901318_CX_CTRL_PRDD_SOURCE,
1145                 .param.ctrl_lli = 0 |
1146                                 COH901318_CX_CTRL_TC_ENABLE |
1147                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1148                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1149                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1150                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1151                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1152                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1153                                 COH901318_CX_CTRL_TCP_ENABLE |
1154                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1155                                 COH901318_CX_CTRL_HSP_ENABLE |
1156                                 COH901318_CX_CTRL_HSS_DISABLE |
1157                                 COH901318_CX_CTRL_DDMA_LEGACY |
1158                                 COH901318_CX_CTRL_PRDD_SOURCE,
1159                 .param.ctrl_lli_last = 0 |
1160                                 COH901318_CX_CTRL_TC_ENABLE |
1161                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1162                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1163                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1164                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1165                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1166                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1167                                 COH901318_CX_CTRL_TCP_ENABLE |
1168                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1169                                 COH901318_CX_CTRL_HSP_ENABLE |
1170                                 COH901318_CX_CTRL_HSS_DISABLE |
1171                                 COH901318_CX_CTRL_DDMA_LEGACY |
1172                                 COH901318_CX_CTRL_PRDD_SOURCE,
1173         },
1174         {
1175                 .number = U300_DMA_PCM_I2S1_RX,
1176                 .name = "PCM I2S1 RX",
1177                 .priority_high = 1,
1178                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1179                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1180                                 COH901318_CX_CFG_LCR_DISABLE |
1181                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1182                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1183                 .param.ctrl_lli_chained = 0 |
1184                                 COH901318_CX_CTRL_TC_ENABLE |
1185                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1186                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1187                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1188                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1189                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1190                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1191                                 COH901318_CX_CTRL_TCP_DISABLE |
1192                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1193                                 COH901318_CX_CTRL_HSP_ENABLE |
1194                                 COH901318_CX_CTRL_HSS_DISABLE |
1195                                 COH901318_CX_CTRL_DDMA_LEGACY |
1196                                 COH901318_CX_CTRL_PRDD_DEST,
1197                 .param.ctrl_lli = 0 |
1198                                 COH901318_CX_CTRL_TC_ENABLE |
1199                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1200                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1201                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1202                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1203                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1204                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1205                                 COH901318_CX_CTRL_TCP_ENABLE |
1206                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1207                                 COH901318_CX_CTRL_HSP_ENABLE |
1208                                 COH901318_CX_CTRL_HSS_DISABLE |
1209                                 COH901318_CX_CTRL_DDMA_LEGACY |
1210                                 COH901318_CX_CTRL_PRDD_DEST,
1211                 .param.ctrl_lli_last = 0 |
1212                                 COH901318_CX_CTRL_TC_ENABLE |
1213                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1214                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1215                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1216                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1217                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1218                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1219                                 COH901318_CX_CTRL_TCP_ENABLE |
1220                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1221                                 COH901318_CX_CTRL_HSP_ENABLE |
1222                                 COH901318_CX_CTRL_HSS_DISABLE |
1223                                 COH901318_CX_CTRL_DDMA_LEGACY |
1224                                 COH901318_CX_CTRL_PRDD_DEST,
1225         },
1226         {
1227                 .number = U300_DMA_XGAM_CDI,
1228                 .name = "XGAM CDI",
1229                 .priority_high = 0,
1230         },
1231         {
1232                 .number = U300_DMA_XGAM_PDI,
1233                 .name = "XGAM PDI",
1234                 .priority_high = 0,
1235         },
1236         /*
1237          * Don't set up device address, burst count or size of src
1238          * or dst bus for this peripheral - handled by PrimeCell
1239          * DMA extension.
1240          */
1241         {
1242                 .number = U300_DMA_SPI_TX,
1243                 .name = "SPI TX",
1244                 .priority_high = 0,
1245                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1246                                 COH901318_CX_CFG_LCR_DISABLE |
1247                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1248                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1249                 .param.ctrl_lli_chained = 0 |
1250                                 COH901318_CX_CTRL_TC_ENABLE |
1251                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1252                                 COH901318_CX_CTRL_TCP_DISABLE |
1253                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1254                                 COH901318_CX_CTRL_HSP_ENABLE |
1255                                 COH901318_CX_CTRL_HSS_DISABLE |
1256                                 COH901318_CX_CTRL_DDMA_LEGACY,
1257                 .param.ctrl_lli = 0 |
1258                                 COH901318_CX_CTRL_TC_ENABLE |
1259                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1260                                 COH901318_CX_CTRL_TCP_DISABLE |
1261                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1262                                 COH901318_CX_CTRL_HSP_ENABLE |
1263                                 COH901318_CX_CTRL_HSS_DISABLE |
1264                                 COH901318_CX_CTRL_DDMA_LEGACY,
1265                 .param.ctrl_lli_last = 0 |
1266                                 COH901318_CX_CTRL_TC_ENABLE |
1267                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1268                                 COH901318_CX_CTRL_TCP_DISABLE |
1269                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1270                                 COH901318_CX_CTRL_HSP_ENABLE |
1271                                 COH901318_CX_CTRL_HSS_DISABLE |
1272                                 COH901318_CX_CTRL_DDMA_LEGACY,
1273         },
1274         {
1275                 .number = U300_DMA_SPI_RX,
1276                 .name = "SPI RX",
1277                 .priority_high = 0,
1278                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1279                                 COH901318_CX_CFG_LCR_DISABLE |
1280                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1281                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1282                 .param.ctrl_lli_chained = 0 |
1283                                 COH901318_CX_CTRL_TC_ENABLE |
1284                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1285                                 COH901318_CX_CTRL_TCP_DISABLE |
1286                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1287                                 COH901318_CX_CTRL_HSP_ENABLE |
1288                                 COH901318_CX_CTRL_HSS_DISABLE |
1289                                 COH901318_CX_CTRL_DDMA_LEGACY,
1290                 .param.ctrl_lli = 0 |
1291                                 COH901318_CX_CTRL_TC_ENABLE |
1292                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1293                                 COH901318_CX_CTRL_TCP_DISABLE |
1294                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1295                                 COH901318_CX_CTRL_HSP_ENABLE |
1296                                 COH901318_CX_CTRL_HSS_DISABLE |
1297                                 COH901318_CX_CTRL_DDMA_LEGACY,
1298                 .param.ctrl_lli_last = 0 |
1299                                 COH901318_CX_CTRL_TC_ENABLE |
1300                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1301                                 COH901318_CX_CTRL_TCP_DISABLE |
1302                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1303                                 COH901318_CX_CTRL_HSP_ENABLE |
1304                                 COH901318_CX_CTRL_HSS_DISABLE |
1305                                 COH901318_CX_CTRL_DDMA_LEGACY,
1306
1307         },
1308         {
1309                 .number = U300_DMA_GENERAL_PURPOSE_0,
1310                 .name = "GENERAL 00",
1311                 .priority_high = 0,
1312
1313                 .param.config = flags_memcpy_config,
1314                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1315                 .param.ctrl_lli = flags_memcpy_lli,
1316                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1317         },
1318         {
1319                 .number = U300_DMA_GENERAL_PURPOSE_1,
1320                 .name = "GENERAL 01",
1321                 .priority_high = 0,
1322
1323                 .param.config = flags_memcpy_config,
1324                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1325                 .param.ctrl_lli = flags_memcpy_lli,
1326                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1327         },
1328         {
1329                 .number = U300_DMA_GENERAL_PURPOSE_2,
1330                 .name = "GENERAL 02",
1331                 .priority_high = 0,
1332
1333                 .param.config = flags_memcpy_config,
1334                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1335                 .param.ctrl_lli = flags_memcpy_lli,
1336                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1337         },
1338         {
1339                 .number = U300_DMA_GENERAL_PURPOSE_3,
1340                 .name = "GENERAL 03",
1341                 .priority_high = 0,
1342
1343                 .param.config = flags_memcpy_config,
1344                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1345                 .param.ctrl_lli = flags_memcpy_lli,
1346                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1347         },
1348         {
1349                 .number = U300_DMA_GENERAL_PURPOSE_4,
1350                 .name = "GENERAL 04",
1351                 .priority_high = 0,
1352
1353                 .param.config = flags_memcpy_config,
1354                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1355                 .param.ctrl_lli = flags_memcpy_lli,
1356                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1357         },
1358         {
1359                 .number = U300_DMA_GENERAL_PURPOSE_5,
1360                 .name = "GENERAL 05",
1361                 .priority_high = 0,
1362
1363                 .param.config = flags_memcpy_config,
1364                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1365                 .param.ctrl_lli = flags_memcpy_lli,
1366                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1367         },
1368         {
1369                 .number = U300_DMA_GENERAL_PURPOSE_6,
1370                 .name = "GENERAL 06",
1371                 .priority_high = 0,
1372
1373                 .param.config = flags_memcpy_config,
1374                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1375                 .param.ctrl_lli = flags_memcpy_lli,
1376                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1377         },
1378         {
1379                 .number = U300_DMA_GENERAL_PURPOSE_7,
1380                 .name = "GENERAL 07",
1381                 .priority_high = 0,
1382
1383                 .param.config = flags_memcpy_config,
1384                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1385                 .param.ctrl_lli = flags_memcpy_lli,
1386                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1387         },
1388         {
1389                 .number = U300_DMA_GENERAL_PURPOSE_8,
1390                 .name = "GENERAL 08",
1391                 .priority_high = 0,
1392
1393                 .param.config = flags_memcpy_config,
1394                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1395                 .param.ctrl_lli = flags_memcpy_lli,
1396                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1397         },
1398 #ifdef CONFIG_MACH_U300_BS335
1399         {
1400                 .number = U300_DMA_UART1_TX,
1401                 .name = "UART1 TX",
1402                 .priority_high = 0,
1403         },
1404         {
1405                 .number = U300_DMA_UART1_RX,
1406                 .name = "UART1 RX",
1407                 .priority_high = 0,
1408         }
1409 #else
1410         {
1411                 .number = U300_DMA_GENERAL_PURPOSE_9,
1412                 .name = "GENERAL 09",
1413                 .priority_high = 0,
1414
1415                 .param.config = flags_memcpy_config,
1416                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1417                 .param.ctrl_lli = flags_memcpy_lli,
1418                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1419         },
1420         {
1421                 .number = U300_DMA_GENERAL_PURPOSE_10,
1422                 .name = "GENERAL 10",
1423                 .priority_high = 0,
1424
1425                 .param.config = flags_memcpy_config,
1426                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1427                 .param.ctrl_lli = flags_memcpy_lli,
1428                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1429         }
1430 #endif
1431 };
1432
1433
1434 static struct coh901318_platform coh901318_platform = {
1435         .chans_slave = dma_slave_channels,
1436         .chans_memcpy = dma_memcpy_channels,
1437         .access_memory_state = coh901318_access_memory_state,
1438         .chan_conf = chan_config,
1439         .max_channels = U300_DMA_CHANNELS,
1440 };
1441
1442 static struct resource pinctrl_resources[] = {
1443         {
1444                 .start = U300_SYSCON_BASE,
1445                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1446                 .flags = IORESOURCE_MEM,
1447         },
1448 };
1449
1450 static struct platform_device wdog_device = {
1451         .name = "coh901327_wdog",
1452         .id = -1,
1453         .num_resources = ARRAY_SIZE(wdog_resources),
1454         .resource = wdog_resources,
1455 };
1456
1457 static struct platform_device i2c0_device = {
1458         .name = "stu300",
1459         .id = 0,
1460         .num_resources = ARRAY_SIZE(i2c0_resources),
1461         .resource = i2c0_resources,
1462 };
1463
1464 static struct platform_device i2c1_device = {
1465         .name = "stu300",
1466         .id = 1,
1467         .num_resources = ARRAY_SIZE(i2c1_resources),
1468         .resource = i2c1_resources,
1469 };
1470
1471 static struct platform_device pinctrl_device = {
1472         .name = "pinctrl-u300",
1473         .id = -1,
1474         .num_resources = ARRAY_SIZE(pinctrl_resources),
1475         .resource = pinctrl_resources,
1476 };
1477
1478 /*
1479  * The different variants have a few different versions of the
1480  * GPIO block, with different number of ports.
1481  */
1482 static struct u300_gpio_platform u300_gpio_plat = {
1483 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1484         .variant = U300_GPIO_COH901335,
1485         .ports = 3,
1486 #endif
1487 #ifdef CONFIG_MACH_U300_BS335
1488         .variant = U300_GPIO_COH901571_3_BS335,
1489         .ports = 7,
1490 #endif
1491 #ifdef CONFIG_MACH_U300_BS365
1492         .variant = U300_GPIO_COH901571_3_BS365,
1493         .ports = 5,
1494 #endif
1495         .gpio_base = 0,
1496         .gpio_irq_base = IRQ_U300_GPIO_BASE,
1497         .pinctrl_device = &pinctrl_device,
1498 };
1499
1500 static struct platform_device gpio_device = {
1501         .name = "u300-gpio",
1502         .id = -1,
1503         .num_resources = ARRAY_SIZE(gpio_resources),
1504         .resource = gpio_resources,
1505         .dev = {
1506                 .platform_data = &u300_gpio_plat,
1507         },
1508 };
1509
1510 static struct platform_device keypad_device = {
1511         .name = "keypad",
1512         .id = -1,
1513         .num_resources = ARRAY_SIZE(keypad_resources),
1514         .resource = keypad_resources,
1515 };
1516
1517 static struct platform_device rtc_device = {
1518         .name = "rtc-coh901331",
1519         .id = -1,
1520         .num_resources = ARRAY_SIZE(rtc_resources),
1521         .resource = rtc_resources,
1522 };
1523
1524 static struct mtd_partition u300_partitions[] = {
1525         {
1526                 .name = "bootrecords",
1527                 .offset = 0,
1528                 .size = SZ_128K,
1529         },
1530         {
1531                 .name = "free",
1532                 .offset = SZ_128K,
1533                 .size = 8064 * SZ_1K,
1534         },
1535         {
1536                 .name = "platform",
1537                 .offset = 8192 * SZ_1K,
1538                 .size = 253952 * SZ_1K,
1539         },
1540 };
1541
1542 static struct fsmc_nand_platform_data nand_platform_data = {
1543         .partitions = u300_partitions,
1544         .nr_partitions = ARRAY_SIZE(u300_partitions),
1545         .options = NAND_SKIP_BBTSCAN,
1546         .width = FSMC_NAND_BW8,
1547         .ale_off = PLAT_NAND_ALE,
1548         .cle_off = PLAT_NAND_CLE,
1549 };
1550
1551 static struct platform_device nand_device = {
1552         .name = "fsmc-nand",
1553         .id = -1,
1554         .resource = fsmc_resources,
1555         .num_resources = ARRAY_SIZE(fsmc_resources),
1556         .dev = {
1557                 .platform_data = &nand_platform_data,
1558         },
1559 };
1560
1561 static struct platform_device dma_device = {
1562         .name           = "coh901318",
1563         .id             = -1,
1564         .resource       = dma_resource,
1565         .num_resources  = ARRAY_SIZE(dma_resource),
1566         .dev = {
1567                 .platform_data = &coh901318_platform,
1568                 .coherent_dma_mask = ~0,
1569         },
1570 };
1571
1572 static unsigned long pin_pullup_conf[] = {
1573         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1574 };
1575
1576 static unsigned long pin_highz_conf[] = {
1577         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1578 };
1579
1580 /* Pin control settings */
1581 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1582         /* anonymous maps for chip power and EMIFs */
1583         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1584         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1585         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1586         /* per-device maps for MMC/SD, SPI and UART */
1587         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1588         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1589         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1590         /* This pin is used for clock return rather than GPIO */
1591         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1592                                     pin_pullup_conf),
1593         /* This pin is used for card detect */
1594         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1595                                     pin_highz_conf),
1596 };
1597
1598 struct u300_mux_hog {
1599         struct device *dev;
1600         struct pinctrl *p;
1601 };
1602
1603 static struct u300_mux_hog u300_mux_hogs[] = {
1604         {
1605                 .dev = &uart0_device.dev,
1606         },
1607         {
1608                 .dev = &pl022_device.dev,
1609         },
1610         {
1611                 .dev = &mmcsd_device.dev,
1612         },
1613 };
1614
1615 static int __init u300_pinctrl_fetch(void)
1616 {
1617         int i;
1618
1619         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1620                 struct pinctrl *p;
1621
1622                 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1623                 if (IS_ERR(p)) {
1624                         pr_err("u300: could not get pinmux hog for dev %s\n",
1625                                dev_name(u300_mux_hogs[i].dev));
1626                         continue;
1627                 }
1628                 u300_mux_hogs[i].p = p;
1629         }
1630         return 0;
1631 }
1632 subsys_initcall(u300_pinctrl_fetch);
1633
1634 /*
1635  * Notice that AMBA devices are initialized before platform devices.
1636  *
1637  */
1638 static struct platform_device *platform_devs[] __initdata = {
1639         &dma_device,
1640         &i2c0_device,
1641         &i2c1_device,
1642         &keypad_device,
1643         &rtc_device,
1644         &gpio_device,
1645         &nand_device,
1646         &wdog_device,
1647 };
1648
1649 /*
1650  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1651  * together so some interrupts are connected to the first one and some
1652  * to the second one.
1653  */
1654 void __init u300_init_irq(void)
1655 {
1656         u32 mask[2] = {0, 0};
1657         struct clk *clk;
1658         int i;
1659
1660         /* initialize clocking early, we want to clock the INTCON */
1661         u300_clock_init();
1662
1663         /* Clock the interrupt controller */
1664         clk = clk_get_sys("intcon", NULL);
1665         BUG_ON(IS_ERR(clk));
1666         clk_enable(clk);
1667
1668         for (i = 0; i < U300_VIC_IRQS_END; i++)
1669                 set_bit(i, (unsigned long *) &mask[0]);
1670         vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1671                  mask[0], mask[0]);
1672         vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1673                  mask[1], mask[1]);
1674 }
1675
1676
1677 /*
1678  * U300 platforms peripheral handling
1679  */
1680 struct db_chip {
1681         u16 chipid;
1682         const char *name;
1683 };
1684
1685 /*
1686  * This is a list of the Digital Baseband chips used in the U300 platform.
1687  */
1688 static struct db_chip db_chips[] __initdata = {
1689         {
1690                 .chipid = 0xb800,
1691                 .name = "DB3000",
1692         },
1693         {
1694                 .chipid = 0xc000,
1695                 .name = "DB3100",
1696         },
1697         {
1698                 .chipid = 0xc800,
1699                 .name = "DB3150",
1700         },
1701         {
1702                 .chipid = 0xd800,
1703                 .name = "DB3200",
1704         },
1705         {
1706                 .chipid = 0xe000,
1707                 .name = "DB3250",
1708         },
1709         {
1710                 .chipid = 0xe800,
1711                 .name = "DB3210",
1712         },
1713         {
1714                 .chipid = 0xf000,
1715                 .name = "DB3350 P1x",
1716         },
1717         {
1718                 .chipid = 0xf100,
1719                 .name = "DB3350 P2x",
1720         },
1721         {
1722                 .chipid = 0x0000, /* List terminator */
1723                 .name = NULL,
1724         }
1725 };
1726
1727 static void __init u300_init_check_chip(void)
1728 {
1729
1730         u16 val;
1731         struct db_chip *chip;
1732         const char *chipname;
1733         const char unknown[] = "UNKNOWN";
1734
1735         /* Read out and print chip ID */
1736         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1737         /* This is in funky bigendian order... */
1738         val = (val & 0xFFU) << 8 | (val >> 8);
1739         chip = db_chips;
1740         chipname = unknown;
1741
1742         for ( ; chip->chipid; chip++) {
1743                 if (chip->chipid == (val & 0xFF00U)) {
1744                         chipname = chip->name;
1745                         break;
1746                 }
1747         }
1748         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1749                "(chip ID 0x%04x)\n", chipname, val);
1750
1751 #ifdef CONFIG_MACH_U300_BS330
1752         if ((val & 0xFF00U) != 0xd800) {
1753                 printk(KERN_ERR "Platform configured for BS330 " \
1754                        "with DB3200 but %s detected, expect problems!",
1755                        chipname);
1756         }
1757 #endif
1758 #ifdef CONFIG_MACH_U300_BS335
1759         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1760                 printk(KERN_ERR "Platform configured for BS335 " \
1761                        " with DB3350 but %s detected, expect problems!",
1762                        chipname);
1763         }
1764 #endif
1765 #ifdef CONFIG_MACH_U300_BS365
1766         if ((val & 0xFF00U) != 0xe800) {
1767                 printk(KERN_ERR "Platform configured for BS365 " \
1768                        "with DB3210 but %s detected, expect problems!",
1769                        chipname);
1770         }
1771 #endif
1772
1773
1774 }
1775
1776 /*
1777  * Some devices and their resources require reserved physical memory from
1778  * the end of the available RAM. This function traverses the list of devices
1779  * and assigns actual addresses to these.
1780  */
1781 static void __init u300_assign_physmem(void)
1782 {
1783         unsigned long curr_start = __pa(high_memory);
1784         int i, j;
1785
1786         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1787                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1788                         struct resource *const res =
1789                           &platform_devs[i]->resource[j];
1790
1791                         if (IORESOURCE_MEM == res->flags &&
1792                                      0 == res->start) {
1793                                 res->start  = curr_start;
1794                                 res->end   += curr_start;
1795                                 curr_start += resource_size(res);
1796
1797                                 printk(KERN_INFO "core.c: Mapping RAM " \
1798                                        "%#x-%#x to device %s:%s\n",
1799                                         res->start, res->end,
1800                                        platform_devs[i]->name, res->name);
1801                         }
1802                 }
1803         }
1804 }
1805
1806 void __init u300_init_devices(void)
1807 {
1808         int i;
1809         u16 val;
1810
1811         /* Check what platform we run and print some status information */
1812         u300_init_check_chip();
1813
1814         /* Set system to run at PLL208, max performance, a known state. */
1815         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1816         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1817         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1818         /* Wait for the PLL208 to lock if not locked in yet */
1819         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1820                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1821         /* Initialize SPI device with some board specifics */
1822         u300_spi_init(&pl022_device);
1823
1824         /* Register the AMBA devices in the AMBA bus abstraction layer */
1825         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1826                 struct amba_device *d = amba_devs[i];
1827                 amba_device_register(d, &iomem_resource);
1828         }
1829
1830         u300_assign_physmem();
1831
1832         /* Initialize pinmuxing */
1833         pinctrl_register_mappings(u300_pinmux_map,
1834                                   ARRAY_SIZE(u300_pinmux_map));
1835
1836         /* Register subdevices on the I2C buses */
1837         u300_i2c_register_board_devices();
1838
1839         /* Register the platform devices */
1840         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1841
1842         /* Register subdevices on the SPI bus */
1843         u300_spi_register_board_devices();
1844
1845         /* Enable SEMI self refresh */
1846         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1847                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1848         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1849 }
1850
1851 /* Forward declare this function from the watchdog */
1852 void coh901327_watchdog_reset(void);
1853
1854 void u300_restart(char mode, const char *cmd)
1855 {
1856         switch (mode) {
1857         case 's':
1858         case 'h':
1859 #ifdef CONFIG_COH901327_WATCHDOG
1860                 coh901327_watchdog_reset();
1861 #endif
1862                 break;
1863         default:
1864                 /* Do nothing */
1865                 break;
1866         }
1867         /* Wait for system do die/reset. */
1868         while (1);
1869 }