arch/arm/mach-omap2/prm44xx.c

   1 /*
   2  * OMAP4 PRM module functions
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/irqs.h>
  22 #include <plat/prcm.h>
  23
  24 #include "iomap.h"
  25 #include "common.h"
  26 #include "vp.h"
  27 #include "prm44xx.h"
  28 #include "prm-regbits-44xx.h"
  29 #include "prcm44xx.h"
  30 #include "prminst44xx.h"
  31
  32 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
  33         OMAP_PRCM_IRQ("wkup",   0,      0),
  34         OMAP_PRCM_IRQ("io",     9,      1),
  35 };
  36
  37 static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
  38         .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  39         .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
  40         .nr_regs                = 2,
  41         .irqs                   = omap4_prcm_irqs,
  42         .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
  43         .irq                    = OMAP44XX_IRQ_PRCM,
  44         .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
  45         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
  46         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
  47         .restore_irqen          = &omap44xx_prm_restore_irqen,
  48 };
  49
  50 /* PRM low-level functions */
  51
  52 /* Read a register in a CM/PRM instance in the PRM module */
  53 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
  54 {
  55         return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
  56 }
  57
  58 /* Write into a register in a CM/PRM instance in the PRM module */
  59 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
  60 {
  61         __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
  62 }
  63
  64 /* Read-modify-write a register in a PRM module. Caller must lock */
  65 u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
  66 {
  67         u32 v;
  68
  69         v = omap4_prm_read_inst_reg(inst, reg);
  70         v &= ~mask;
  71         v |= bits;
  72         omap4_prm_write_inst_reg(v, inst, reg);
  73
  74         return v;
  75 }
  76
  77 /* PRM VP */
  78
  79 /*
  80  * struct omap4_vp - OMAP4 VP register access description.
  81  * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
  82  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
  83  */
  84 struct omap4_vp {
  85         u32 irqstatus_mpu;
  86         u32 tranxdone_status;
  87 };
  88
  89 static struct omap4_vp omap4_vp[] = {
  90         [OMAP4_VP_VDD_MPU_ID] = {
  91                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
  92                 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
  93         },
  94         [OMAP4_VP_VDD_IVA_ID] = {
  95                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  96                 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
  97         },
  98         [OMAP4_VP_VDD_CORE_ID] = {
  99                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 100                 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 101         },
 102 };
 103
 104 u32 omap4_prm_vp_check_txdone(u8 vp_id)
 105 {
 106         struct omap4_vp *vp = &omap4_vp[vp_id];
 107         u32 irqstatus;
 108
 109         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 110                                                 OMAP4430_PRM_OCP_SOCKET_INST,
 111                                                 vp->irqstatus_mpu);
 112         return irqstatus & vp->tranxdone_status;
 113 }
 114
 115 void omap4_prm_vp_clear_txdone(u8 vp_id)
 116 {
 117         struct omap4_vp *vp = &omap4_vp[vp_id];
 118
 119         omap4_prminst_write_inst_reg(vp->tranxdone_status,
 120                                      OMAP4430_PRM_PARTITION,
 121                                      OMAP4430_PRM_OCP_SOCKET_INST,
 122                                      vp->irqstatus_mpu);
 123 };
 124
 125 u32 omap4_prm_vcvp_read(u8 offset)
 126 {
 127         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 128                                            OMAP4430_PRM_DEVICE_INST, offset);
 129 }
 130
 131 void omap4_prm_vcvp_write(u32 val, u8 offset)
 132 {
 133         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
 134                                      OMAP4430_PRM_DEVICE_INST, offset);
 135 }
 136
 137 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 138 {
 139         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 140                                                OMAP4430_PRM_PARTITION,
 141                                                OMAP4430_PRM_DEVICE_INST,
 142                                                offset);
 143 }
 144
 145 static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
 146 {
 147         u32 mask, st;
 148
 149         /* XXX read mask from RAM? */
 150         mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 151                                        irqen_offs);
 152         st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
 153
 154         return mask & st;
 155 }
 156
 157 /**
 158  * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 159  * @events: ptr to two consecutive u32s, preallocated by caller
 160  *
 161  * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
 162  * MPU IRQs, and store the result into the two u32s pointed to by @events.
 163  * No return value.
 164  */
 165 void omap44xx_prm_read_pending_irqs(unsigned long *events)
 166 {
 167         events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
 168                                           OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 169
 170         events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
 171                                           OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
 172 }
 173
 174 /**
 175  * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 176  *
 177  * Force any buffered writes to the PRM IP block to complete.  Needed
 178  * by the PRM IRQ handler, which reads and writes directly to the IP
 179  * block, to avoid race conditions after acknowledging or clearing IRQ
 180  * bits.  No return value.
 181  */
 182 void omap44xx_prm_ocp_barrier(void)
 183 {
 184         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 185                                 OMAP4_REVISION_PRM_OFFSET);
 186 }
 187
 188 /**
 189  * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
 190  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 191  *
 192  * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
 193  * @saved_mask.  @saved_mask must be allocated by the caller.
 194  * Intended to be used in the PRM interrupt handler suspend callback.
 195  * The OCP barrier is needed to ensure the write to disable PRM
 196  * interrupts reaches the PRM before returning; otherwise, spurious
 197  * interrupts might occur.  No return value.
 198  */
 199 void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
 200 {
 201         saved_mask[0] =
 202                 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 203                                         OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 204         saved_mask[1] =
 205                 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 206                                         OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
 207
 208         omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
 209                                  OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 210         omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
 211                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 212
 213         /* OCP barrier */
 214         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 215                                 OMAP4_REVISION_PRM_OFFSET);
 216 }
 217
 218 /**
 219  * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
 220  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 221  *
 222  * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
 223  * @saved_mask.  Intended to be used in the PRM interrupt handler resume
 224  * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
 225  * No OCP barrier should be needed here; any pending PRM interrupts will fire
 226  * once the writes reach the PRM.  No return value.
 227  */
 228 void omap44xx_prm_restore_irqen(u32 *saved_mask)
 229 {
 230         omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
 231                                  OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 232         omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST,
 233                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 234 }
 235
 236 static int __init omap4xxx_prcm_init(void)
 237 {
 238         if (cpu_is_omap44xx())
 239                 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 240         return 0;
 241 }
 242 subsys_initcall(omap4xxx_prcm_init);