arch/arm/mach-at91/at91sam9x5.c

   1 /*
   2  *  Chip-specific setup code for the AT91SAM9x5 family
   3  *
   4  *  Copyright (C) 2010-2012 Atmel Corporation.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11
  12 #include <asm/irq.h>
  13 #include <asm/mach/arch.h>
  14 #include <asm/mach/map.h>
  15 #include <mach/at91sam9x5.h>
  16 #include <mach/at91_pmc.h>
  17 #include <mach/cpu.h>
  18 #include <mach/board.h>
  19
  20 #include "soc.h"
  21 #include "generic.h"
  22 #include "clock.h"
  23 #include "sam9_smc.h"
  24
  25 /* --------------------------------------------------------------------
  26  *  Clocks
  27  * -------------------------------------------------------------------- */
  28
  29 /*
  30  * The peripheral clocks.
  31  */
  32 static struct clk pioAB_clk = {
  33         .name           = "pioAB_clk",
  34         .pmc_mask       = 1 << AT91SAM9X5_ID_PIOAB,
  35         .type           = CLK_TYPE_PERIPHERAL,
  36 };
  37 static struct clk pioCD_clk = {
  38         .name           = "pioCD_clk",
  39         .pmc_mask       = 1 << AT91SAM9X5_ID_PIOCD,
  40         .type           = CLK_TYPE_PERIPHERAL,
  41 };
  42 static struct clk smd_clk = {
  43         .name           = "smd_clk",
  44         .pmc_mask       = 1 << AT91SAM9X5_ID_SMD,
  45         .type           = CLK_TYPE_PERIPHERAL,
  46 };
  47 static struct clk usart0_clk = {
  48         .name           = "usart0_clk",
  49         .pmc_mask       = 1 << AT91SAM9X5_ID_USART0,
  50         .type           = CLK_TYPE_PERIPHERAL,
  51 };
  52 static struct clk usart1_clk = {
  53         .name           = "usart1_clk",
  54         .pmc_mask       = 1 << AT91SAM9X5_ID_USART1,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk usart2_clk = {
  58         .name           = "usart2_clk",
  59         .pmc_mask       = 1 << AT91SAM9X5_ID_USART2,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62 /* USART3 clock - Only for sam9g25/sam9x25 */
  63 static struct clk usart3_clk = {
  64         .name           = "usart3_clk",
  65         .pmc_mask       = 1 << AT91SAM9X5_ID_USART3,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk twi0_clk = {
  69         .name           = "twi0_clk",
  70         .pmc_mask       = 1 << AT91SAM9X5_ID_TWI0,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk twi1_clk = {
  74         .name           = "twi1_clk",
  75         .pmc_mask       = 1 << AT91SAM9X5_ID_TWI1,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk twi2_clk = {
  79         .name           = "twi2_clk",
  80         .pmc_mask       = 1 << AT91SAM9X5_ID_TWI2,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk mmc0_clk = {
  84         .name           = "mci0_clk",
  85         .pmc_mask       = 1 << AT91SAM9X5_ID_MCI0,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk spi0_clk = {
  89         .name           = "spi0_clk",
  90         .pmc_mask       = 1 << AT91SAM9X5_ID_SPI0,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk spi1_clk = {
  94         .name           = "spi1_clk",
  95         .pmc_mask       = 1 << AT91SAM9X5_ID_SPI1,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk uart0_clk = {
  99         .name           = "uart0_clk",
 100         .pmc_mask       = 1 << AT91SAM9X5_ID_UART0,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk uart1_clk = {
 104         .name           = "uart1_clk",
 105         .pmc_mask       = 1 << AT91SAM9X5_ID_UART1,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk tcb0_clk = {
 109         .name           = "tcb0_clk",
 110         .pmc_mask       = 1 << AT91SAM9X5_ID_TCB,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk pwm_clk = {
 114         .name           = "pwm_clk",
 115         .pmc_mask       = 1 << AT91SAM9X5_ID_PWM,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk adc_clk = {
 119         .name           = "adc_clk",
 120         .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
 121         .type   = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk dma0_clk = {
 124         .name           = "dma0_clk",
 125         .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
 126         .type   = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk dma1_clk = {
 129         .name           = "dma1_clk",
 130         .pmc_mask       = 1 << AT91SAM9X5_ID_DMA1,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk uhphs_clk = {
 134         .name           = "uhphs",
 135         .pmc_mask       = 1 << AT91SAM9X5_ID_UHPHS,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk udphs_clk = {
 139         .name           = "udphs_clk",
 140         .pmc_mask       = 1 << AT91SAM9X5_ID_UDPHS,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 /* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
 144 static struct clk macb0_clk = {
 145         .name           = "pclk",
 146         .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC0,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 /* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
 150 static struct clk lcdc_clk = {
 151         .name           = "lcdc_clk",
 152         .pmc_mask       = 1 << AT91SAM9X5_ID_LCDC,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155 /* isi clock - Only for sam9g25 */
 156 static struct clk isi_clk = {
 157         .name           = "isi_clk",
 158         .pmc_mask       = 1 << AT91SAM9X5_ID_ISI,
 159         .type           = CLK_TYPE_PERIPHERAL,
 160 };
 161 static struct clk mmc1_clk = {
 162         .name           = "mci1_clk",
 163         .pmc_mask       = 1 << AT91SAM9X5_ID_MCI1,
 164         .type           = CLK_TYPE_PERIPHERAL,
 165 };
 166 /* emac1 clock - Only for sam9x25 */
 167 static struct clk macb1_clk = {
 168         .name           = "pclk",
 169         .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC1,
 170         .type           = CLK_TYPE_PERIPHERAL,
 171 };
 172 static struct clk ssc_clk = {
 173         .name           = "ssc_clk",
 174         .pmc_mask       = 1 << AT91SAM9X5_ID_SSC,
 175         .type           = CLK_TYPE_PERIPHERAL,
 176 };
 177 /* can0 clock - Only for sam9x35 */
 178 static struct clk can0_clk = {
 179         .name           = "can0_clk",
 180         .pmc_mask       = 1 << AT91SAM9X5_ID_CAN0,
 181         .type           = CLK_TYPE_PERIPHERAL,
 182 };
 183 /* can1 clock - Only for sam9x35 */
 184 static struct clk can1_clk = {
 185         .name           = "can1_clk",
 186         .pmc_mask       = 1 << AT91SAM9X5_ID_CAN1,
 187         .type           = CLK_TYPE_PERIPHERAL,
 188 };
 189
 190 static struct clk *periph_clocks[] __initdata = {
 191         &pioAB_clk,
 192         &pioCD_clk,
 193         &smd_clk,
 194         &usart0_clk,
 195         &usart1_clk,
 196         &usart2_clk,
 197         &twi0_clk,
 198         &twi1_clk,
 199         &twi2_clk,
 200         &mmc0_clk,
 201         &spi0_clk,
 202         &spi1_clk,
 203         &uart0_clk,
 204         &uart1_clk,
 205         &tcb0_clk,
 206         &pwm_clk,
 207         &adc_clk,
 208         &dma0_clk,
 209         &dma1_clk,
 210         &uhphs_clk,
 211         &udphs_clk,
 212         &mmc1_clk,
 213         &ssc_clk,
 214         // irq0
 215 };
 216
 217 static struct clk_lookup periph_clocks_lookups[] = {
 218         /* lookup table for DT entries */
 219         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 220         CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
 221         CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
 222         CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
 223         CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
 224         CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
 225         CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 226         CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 227         CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
 228         CLKDEV_CON_ID("pioA", &pioAB_clk),
 229         CLKDEV_CON_ID("pioB", &pioAB_clk),
 230         CLKDEV_CON_ID("pioC", &pioCD_clk),
 231         CLKDEV_CON_ID("pioD", &pioCD_clk),
 232         /* additional fake clock for macb_hclk */
 233         CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
 234         CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
 235         CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 236         CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 237         CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
 238 };
 239
 240 /*
 241  * The two programmable clocks.
 242  * You must configure pin multiplexing to bring these signals out.
 243  */
 244 static struct clk pck0 = {
 245         .name           = "pck0",
 246         .pmc_mask       = AT91_PMC_PCK0,
 247         .type           = CLK_TYPE_PROGRAMMABLE,
 248         .id             = 0,
 249 };
 250 static struct clk pck1 = {
 251         .name           = "pck1",
 252         .pmc_mask       = AT91_PMC_PCK1,
 253         .type           = CLK_TYPE_PROGRAMMABLE,
 254         .id             = 1,
 255 };
 256
 257 static void __init at91sam9x5_register_clocks(void)
 258 {
 259         int i;
 260
 261         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 262                 clk_register(periph_clocks[i]);
 263
 264         clkdev_add_table(periph_clocks_lookups,
 265                          ARRAY_SIZE(periph_clocks_lookups));
 266
 267         if (cpu_is_at91sam9g25()
 268         || cpu_is_at91sam9x25())
 269                 clk_register(&usart3_clk);
 270
 271         if (cpu_is_at91sam9g25()
 272         || cpu_is_at91sam9x25()
 273         || cpu_is_at91sam9g35()
 274         || cpu_is_at91sam9x35())
 275                 clk_register(&macb0_clk);
 276
 277         if (cpu_is_at91sam9g15()
 278         || cpu_is_at91sam9g35()
 279         || cpu_is_at91sam9x35())
 280                 clk_register(&lcdc_clk);
 281
 282         if (cpu_is_at91sam9g25())
 283                 clk_register(&isi_clk);
 284
 285         if (cpu_is_at91sam9x25())
 286                 clk_register(&macb1_clk);
 287
 288         if (cpu_is_at91sam9x25()
 289         || cpu_is_at91sam9x35()) {
 290                 clk_register(&can0_clk);
 291                 clk_register(&can1_clk);
 292         }
 293
 294         clk_register(&pck0);
 295         clk_register(&pck1);
 296 }
 297
 298 /* --------------------------------------------------------------------
 299  *  AT91SAM9x5 processor initialization
 300  * -------------------------------------------------------------------- */
 301
 302 static void __init at91sam9x5_map_io(void)
 303 {
 304         at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 305 }
 306
 307 void __init at91sam9x5_initialize(void)
 308 {
 309         at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
 310
 311         /* Register GPIO subsystem (using DT) */
 312         at91_gpio_init(NULL, 0);
 313 }
 314
 315 /* --------------------------------------------------------------------
 316  *  Interrupt initialization
 317  * -------------------------------------------------------------------- */
 318 /*
 319  * The default interrupt priority levels (0 = lowest, 7 = highest).
 320  */
 321 static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
 322         7,      /* Advanced Interrupt Controller (FIQ) */
 323         7,      /* System Peripherals */
 324         1,      /* Parallel IO Controller A and B */
 325         1,      /* Parallel IO Controller C and D */
 326         4,      /* Soft Modem */
 327         5,      /* USART 0 */
 328         5,      /* USART 1 */
 329         5,      /* USART 2 */
 330         5,      /* USART 3 */
 331         6,      /* Two-Wire Interface 0 */
 332         6,      /* Two-Wire Interface 1 */
 333         6,      /* Two-Wire Interface 2 */
 334         0,      /* Multimedia Card Interface 0 */
 335         5,      /* Serial Peripheral Interface 0 */
 336         5,      /* Serial Peripheral Interface 1 */
 337         5,      /* UART 0 */
 338         5,      /* UART 1 */
 339         0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
 340         0,      /* Pulse Width Modulation Controller */
 341         0,      /* ADC Controller */
 342         0,      /* DMA Controller 0 */
 343         0,      /* DMA Controller 1 */
 344         2,      /* USB Host High Speed port */
 345         2,      /* USB Device High speed port */
 346         3,      /* Ethernet MAC 0 */
 347         3,      /* LDC Controller or Image Sensor Interface */
 348         0,      /* Multimedia Card Interface 1 */
 349         3,      /* Ethernet MAC 1 */
 350         4,      /* Synchronous Serial Interface */
 351         4,      /* CAN Controller 0 */
 352         4,      /* CAN Controller 1 */
 353         0,      /* Advanced Interrupt Controller (IRQ0) */
 354 };
 355
 356 struct at91_init_soc __initdata at91sam9x5_soc = {
 357         .map_io = at91sam9x5_map_io,
 358         .default_irq_priority = at91sam9x5_default_irq_priority,
 359         .register_clocks = at91sam9x5_register_clocks,
 360         .init = at91sam9x5_initialize,
 361 };