2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * Copyright (C) 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn_helgaas@hp.com>
10 * Note: Above list of copyright holders is incomplete...
12 #include <linux/config.h>
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/smp_lock.h>
22 #include <linux/spinlock.h>
24 #include <asm/machvec.h>
26 #include <asm/segment.h>
27 #include <asm/system.h>
43 #define DBG(x...) printk(x)
48 struct pci_fixup pcibios_fixups[1];
51 * Low-level SAL-based PCI configuration access functions. Note that SAL
52 * calls are already serialized (via sal_lock), so we don't need another
53 * synchronization mechanism here.
56 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
57 ((u64)(seg << 24) | (u64)(bus << 16) | \
58 (u64)(devfn << 8) | (u64)(reg))
62 pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
67 if (!value || (seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
70 result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, devfn, reg), len, &data);
78 pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
80 if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
83 return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, devfn, reg), len, value);
86 struct pci_raw_ops pci_sal_ops = {
88 .write = pci_sal_write
91 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; /* default to SAL */
95 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
97 return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
98 devfn, where, size, value);
102 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
104 return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
105 devfn, where, size, value);
108 static struct pci_ops pci_root_ops = {
116 if (!acpi_pci_irq_init())
117 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
119 printk(KERN_WARNING "PCI: Invalid ACPI-PCI IRQ routing table\n");
123 subsys_initcall(pci_acpi_init);
125 /* Called by ACPI when it finds a new root bus. */
127 static struct pci_controller * __devinit
128 alloc_pci_controller (int seg)
130 struct pci_controller *controller;
132 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
136 memset(controller, 0, sizeof(*controller));
137 controller->segment = seg;
142 alloc_resource (char *name, struct resource *root, unsigned long start, unsigned long end, unsigned long flags)
144 struct resource *res;
146 res = kmalloc(sizeof(*res), GFP_KERNEL);
150 memset(res, 0, sizeof(*res));
156 if (request_resource(root, res))
163 add_io_space (struct acpi_resource_address64 *addr)
169 if (addr->address_translation_offset == 0)
170 return IO_SPACE_BASE(0); /* part of legacy IO space */
172 if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
175 offset = (u64) ioremap(addr->address_translation_offset, 0);
176 for (i = 0; i < num_io_spaces; i++)
177 if (io_space[i].mmio_base == offset &&
178 io_space[i].sparse == sparse)
179 return IO_SPACE_BASE(i);
181 if (num_io_spaces == MAX_IO_SPACES) {
182 printk("Too many IO port spaces\n");
187 io_space[i].mmio_base = offset;
188 io_space[i].sparse = sparse;
190 return IO_SPACE_BASE(i);
193 static acpi_status __devinit
194 count_window (struct acpi_resource *resource, void *data)
196 unsigned int *windows = (unsigned int *) data;
197 struct acpi_resource_address64 addr;
200 status = acpi_resource_to_address64(resource, &addr);
201 if (ACPI_SUCCESS(status))
202 if (addr.resource_type == ACPI_MEMORY_RANGE ||
203 addr.resource_type == ACPI_IO_RANGE)
209 struct pci_root_info {
210 struct pci_controller *controller;
214 static acpi_status __devinit
215 add_window (struct acpi_resource *res, void *data)
217 struct pci_root_info *info = (struct pci_root_info *) data;
218 struct pci_window *window;
219 struct acpi_resource_address64 addr;
221 unsigned long flags, offset = 0;
222 struct resource *root;
224 status = acpi_resource_to_address64(res, &addr);
225 if (ACPI_SUCCESS(status)) {
226 if (addr.resource_type == ACPI_MEMORY_RANGE) {
227 flags = IORESOURCE_MEM;
228 root = &iomem_resource;
229 offset = addr.address_translation_offset;
230 } else if (addr.resource_type == ACPI_IO_RANGE) {
231 flags = IORESOURCE_IO;
232 root = &ioport_resource;
233 offset = add_io_space(&addr);
239 window = &info->controller->window[info->controller->windows++];
240 window->resource.flags |= flags;
241 window->resource.start = addr.min_address_range;
242 window->resource.end = addr.max_address_range;
243 window->offset = offset;
245 if (alloc_resource(info->name, root, addr.min_address_range + offset,
246 addr.max_address_range + offset, flags))
247 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
248 addr.min_address_range + offset, addr.max_address_range + offset,
249 root->name, info->name);
255 struct pci_bus * __devinit
256 pci_acpi_scan_root (struct acpi_device *device, int domain, int bus)
258 struct pci_root_info info;
259 struct pci_controller *controller;
260 unsigned int windows = 0;
263 printk("PCI: Probing PCI hardware on bus (%04x:%02x)\n", domain, bus);
264 controller = alloc_pci_controller(domain);
268 controller->acpi_handle = device->handle;
270 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, &windows);
271 controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL);
272 if (!controller->window)
275 name = kmalloc(16, GFP_KERNEL);
279 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
280 info.controller = controller;
282 acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, &info);
284 return pci_scan_bus(bus, &pci_root_ops, controller);
287 kfree(controller->window);
295 pcibios_fixup_device_resources (struct pci_dev *dev, struct pci_bus *bus)
297 struct pci_controller *controller = PCI_CONTROLLER(dev);
298 struct pci_window *window;
301 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
302 if (!dev->resource[i].start)
305 #define contains(win, res) ((res)->start >= (win)->start && \
306 (res)->end <= (win)->end)
308 for (j = 0; j < controller->windows; j++) {
309 window = &controller->window[j];
310 if (((dev->resource[i].flags & IORESOURCE_MEM &&
311 window->resource.flags & IORESOURCE_MEM) ||
312 (dev->resource[i].flags & IORESOURCE_IO &&
313 window->resource.flags & IORESOURCE_IO)) &&
314 contains(&window->resource, &dev->resource[i])) {
315 dev->resource[i].start += window->offset;
316 dev->resource[i].end += window->offset;
323 * Called after each bus is probed, but before its children are examined.
326 pcibios_fixup_bus (struct pci_bus *b)
328 struct list_head *ln;
330 for (ln = b->devices.next; ln != &b->devices; ln = ln->next)
331 pcibios_fixup_device_resources(pci_dev_b(ln), b);
337 pcibios_update_irq (struct pci_dev *dev, int irq)
339 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
341 /* ??? FIXME -- record old value for shutdown. */
345 pcibios_enable_resources (struct pci_dev *dev, int mask)
354 pci_read_config_word(dev, PCI_COMMAND, &cmd);
356 for (idx=0; idx<6; idx++) {
357 /* Only set up the desired resources. */
358 if (!(mask & (1 << idx)))
361 r = &dev->resource[idx];
362 if (!r->start && r->end) {
364 "PCI: Device %s not available because of resource collisions\n",
368 if (r->flags & IORESOURCE_IO)
369 cmd |= PCI_COMMAND_IO;
370 if (r->flags & IORESOURCE_MEM)
371 cmd |= PCI_COMMAND_MEMORY;
373 if (dev->resource[PCI_ROM_RESOURCE].start)
374 cmd |= PCI_COMMAND_MEMORY;
375 if (cmd != old_cmd) {
376 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
377 pci_write_config_word(dev, PCI_COMMAND, cmd);
383 pcibios_enable_device (struct pci_dev *dev, int mask)
387 ret = pcibios_enable_resources(dev, mask);
391 printk(KERN_INFO "PCI: Found IRQ %d for device %s\n", dev->irq, dev->slot_name);
392 return acpi_pci_irq_enable(dev);
396 pcibios_align_resource (void *data, struct resource *res,
397 unsigned long size, unsigned long align)
402 * PCI BIOS setup, always defaults to SAL interface
405 pcibios_setup (char *str)
411 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
412 enum pci_mmap_state mmap_state, int write_combine)
415 * I/O space cannot be accessed via normal processor loads and stores on this
418 if (mmap_state == pci_mmap_io)
420 * XXX we could relax this for I/O spaces for which ACPI indicates that
421 * the space is 1-to-1 mapped. But at the moment, we don't support
422 * multiple PCI address spaces and the legacy I/O space is not 1-to-1
423 * mapped, so this is moot.
428 * Leave vm_pgoff as-is, the PCI space address is the physical address on this
431 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
434 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
436 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
438 if (remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
439 vma->vm_end - vma->vm_start, vma->vm_page_prot))
446 * pci_cacheline_size - determine cacheline size for PCI devices
449 * We want to use the line-size of the outer-most cache. We assume
450 * that this line-size is the same for all CPUs.
452 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
454 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
457 pci_cacheline_size (void)
459 u64 levels, unique_caches;
461 pal_cache_config_info_t cci;
462 static u8 cacheline_size;
465 return cacheline_size;
467 status = ia64_pal_cache_summary(&levels, &unique_caches);
469 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
470 __FUNCTION__, status);
471 return SMP_CACHE_BYTES;
474 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
477 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
478 __FUNCTION__, status);
479 return SMP_CACHE_BYTES;
481 cacheline_size = 1 << cci.pcci_line_size;
482 return cacheline_size;
486 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
487 * @dev: the PCI device for which MWI is enabled
489 * For ia64, we can get the cacheline sizes from PAL.
491 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
494 pcibios_prep_mwi (struct pci_dev *dev)
496 unsigned long desired_linesize, current_linesize;
500 desired_linesize = pci_cacheline_size();
502 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
503 current_linesize = 4 * pci_linesize;
504 if (desired_linesize != current_linesize) {
505 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
506 dev->slot_name, current_linesize);
507 if (current_linesize > desired_linesize) {
508 printk(" expected %lu bytes instead\n", desired_linesize);
511 printk(" correcting to %lu\n", desired_linesize);
512 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);