drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  *
   8  * Firmware is:
   9  *      Copyright (C) 2000-2003 Broadcom Corporation.
  10  */
  11
  12 #include <linux/config.h>
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/compiler.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/ioport.h>
  23 #include <linux/pci.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/mii.h>
  29 #include <linux/if_vlan.h>
  30 #include <linux/ip.h>
  31 #include <linux/tcp.h>
  32 #include <linux/workqueue.h>
  33
  34 #include <net/checksum.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/io.h>
  38 #include <asm/byteorder.h>
  39 #include <asm/uaccess.h>
  40
  41 #ifdef CONFIG_SPARC64
  42 #include <asm/idprom.h>
  43 #include <asm/oplib.h>
  44 #include <asm/pbm.h>
  45 #endif
  46
  47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  48 #define TG3_VLAN_TAG_USED 1
  49 #else
  50 #define TG3_VLAN_TAG_USED 0
  51 #endif
  52
  53 #ifdef NETIF_F_TSO
  54 #define TG3_TSO_SUPPORT 1
  55 #else
  56 #define TG3_TSO_SUPPORT 0
  57 #endif
  58
  59 #include "tg3.h"
  60
  61 #define DRV_MODULE_NAME         "tg3"
  62 #define PFX DRV_MODULE_NAME     ": "
  63 #define DRV_MODULE_VERSION      "3.15"
  64 #define DRV_MODULE_RELDATE      "January 6, 2005"
  65
  66 #define TG3_DEF_MAC_MODE        0
  67 #define TG3_DEF_RX_MODE         0
  68 #define TG3_DEF_TX_MODE         0
  69 #define TG3_DEF_MSG_ENABLE        \
  70         (NETIF_MSG_DRV          | \
  71          NETIF_MSG_PROBE        | \
  72          NETIF_MSG_LINK         | \
  73          NETIF_MSG_TIMER        | \
  74          NETIF_MSG_IFDOWN       | \
  75          NETIF_MSG_IFUP         | \
  76          NETIF_MSG_RX_ERR       | \
  77          NETIF_MSG_TX_ERR)
  78
  79 /* length of time before we decide the hardware is borked,
  80  * and dev->tx_timeout() should be called to fix the problem
  81  */
  82 #define TG3_TX_TIMEOUT                  (5 * HZ)
  83
  84 /* hardware minimum and maximum for a single frame's data payload */
  85 #define TG3_MIN_MTU                     60
  86 #define TG3_MAX_MTU(tp) \
  87         ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
  88           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500)
  89
  90 /* These numbers seem to be hard coded in the NIC firmware somehow.
  91  * You can't change the ring sizes, but you can change where you place
  92  * them in the NIC onboard memory.
  93  */
  94 #define TG3_RX_RING_SIZE                512
  95 #define TG3_DEF_RX_RING_PENDING         200
  96 #define TG3_RX_JUMBO_RING_SIZE          256
  97 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
  98
  99 /* Do not place this n-ring entries value into the tp struct itself,
 100  * we really want to expose these constants to GCC so that modulo et
 101  * al.  operations are done with shifts and masks instead of with
 102  * hw multiply/modulo instructions.  Another solution would be to
 103  * replace things like '% foo' with '& (foo - 1)'.
 104  */
 105 #define TG3_RX_RCB_RING_SIZE(tp)        \
 106         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || \
 107           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ? \
 108          512 : 1024)
 109
 110 #define TG3_TX_RING_SIZE                512
 111 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 112
 113 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 114                                  TG3_RX_RING_SIZE)
 115 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 116                                  TG3_RX_JUMBO_RING_SIZE)
 117 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 118                                    TG3_RX_RCB_RING_SIZE(tp))
 119 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 120                                  TG3_TX_RING_SIZE)
 121 #define TX_RING_GAP(TP) \
 122         (TG3_TX_RING_SIZE - (TP)->tx_pending)
 123 #define TX_BUFFS_AVAIL(TP)                                              \
 124         (((TP)->tx_cons <= (TP)->tx_prod) ?                             \
 125           (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :            \
 126           (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 130 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 131
 132 /* minimum number of free TX descriptors required to wake up TX process */
 133 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 134
 135 /* number of ETHTOOL_GSTATS u64's */
 136 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 137
 138 static char version[] __devinitdata =
 139         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 140
 141 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 142 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 143 MODULE_LICENSE("GPL");
 144 MODULE_VERSION(DRV_MODULE_VERSION);
 145
 146 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 147 module_param(tg3_debug, int, 0);
 148 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 149
 150 static struct pci_device_id tg3_pci_tbl[] = {
 151         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 152           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 153         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 154           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 155         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 156           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 157         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 158           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 159         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 160           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 161         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 162           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 163         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 164           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 165         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 166           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 167         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 168           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 169         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 170           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 171         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 172           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 173         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 174           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 175         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 176           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 177         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 178           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 179         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 180           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 181         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 182           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 183         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 184           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 185         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 186           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 187         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 188           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 189         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 190           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 191         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 192           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 193         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 194           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 195         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 196           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 197         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 198           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 199         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 200           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 201         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 202           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 203         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 204           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 205         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 206           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 207         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 209         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 210           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 211         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 212           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 213         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 214           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 215         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 216           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 217         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 219         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 221         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 223         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 224           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 225         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 226           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 227         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 229         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 230           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 231         { 0, }
 232 };
 233
 234 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 235
 236 static struct {
 237         const char string[ETH_GSTRING_LEN];
 238 } ethtool_stats_keys[TG3_NUM_STATS] = {
 239         { "rx_octets" },
 240         { "rx_fragments" },
 241         { "rx_ucast_packets" },
 242         { "rx_mcast_packets" },
 243         { "rx_bcast_packets" },
 244         { "rx_fcs_errors" },
 245         { "rx_align_errors" },
 246         { "rx_xon_pause_rcvd" },
 247         { "rx_xoff_pause_rcvd" },
 248         { "rx_mac_ctrl_rcvd" },
 249         { "rx_xoff_entered" },
 250         { "rx_frame_too_long_errors" },
 251         { "rx_jabbers" },
 252         { "rx_undersize_packets" },
 253         { "rx_in_length_errors" },
 254         { "rx_out_length_errors" },
 255         { "rx_64_or_less_octet_packets" },
 256         { "rx_65_to_127_octet_packets" },
 257         { "rx_128_to_255_octet_packets" },
 258         { "rx_256_to_511_octet_packets" },
 259         { "rx_512_to_1023_octet_packets" },
 260         { "rx_1024_to_1522_octet_packets" },
 261         { "rx_1523_to_2047_octet_packets" },
 262         { "rx_2048_to_4095_octet_packets" },
 263         { "rx_4096_to_8191_octet_packets" },
 264         { "rx_8192_to_9022_octet_packets" },
 265
 266         { "tx_octets" },
 267         { "tx_collisions" },
 268
 269         { "tx_xon_sent" },
 270         { "tx_xoff_sent" },
 271         { "tx_flow_control" },
 272         { "tx_mac_errors" },
 273         { "tx_single_collisions" },
 274         { "tx_mult_collisions" },
 275         { "tx_deferred" },
 276         { "tx_excessive_collisions" },
 277         { "tx_late_collisions" },
 278         { "tx_collide_2times" },
 279         { "tx_collide_3times" },
 280         { "tx_collide_4times" },
 281         { "tx_collide_5times" },
 282         { "tx_collide_6times" },
 283         { "tx_collide_7times" },
 284         { "tx_collide_8times" },
 285         { "tx_collide_9times" },
 286         { "tx_collide_10times" },
 287         { "tx_collide_11times" },
 288         { "tx_collide_12times" },
 289         { "tx_collide_13times" },
 290         { "tx_collide_14times" },
 291         { "tx_collide_15times" },
 292         { "tx_ucast_packets" },
 293         { "tx_mcast_packets" },
 294         { "tx_bcast_packets" },
 295         { "tx_carrier_sense_errors" },
 296         { "tx_discards" },
 297         { "tx_errors" },
 298
 299         { "dma_writeq_full" },
 300         { "dma_write_prioq_full" },
 301         { "rxbds_empty" },
 302         { "rx_discards" },
 303         { "rx_errors" },
 304         { "rx_threshold_hit" },
 305
 306         { "dma_readq_full" },
 307         { "dma_read_prioq_full" },
 308         { "tx_comp_queue_full" },
 309
 310         { "ring_set_send_prod_index" },
 311         { "ring_status_update" },
 312         { "nic_irqs" },
 313         { "nic_avoided_irqs" },
 314         { "nic_tx_threshold_hit" }
 315 };
 316
 317 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 318 {
 319         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 320                 unsigned long flags;
 321
 322                 spin_lock_irqsave(&tp->indirect_lock, flags);
 323                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 324                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 325                 spin_unlock_irqrestore(&tp->indirect_lock, flags);
 326         } else {
 327                 writel(val, tp->regs + off);
 328                 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
 329                         readl(tp->regs + off);
 330         }
 331 }
 332
 333 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 334 {
 335         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 336                 unsigned long flags;
 337
 338                 spin_lock_irqsave(&tp->indirect_lock, flags);
 339                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 340                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 341                 spin_unlock_irqrestore(&tp->indirect_lock, flags);
 342         } else {
 343                 void __iomem *dest = tp->regs + off;
 344                 writel(val, dest);
 345                 readl(dest);    /* always flush PCI write */
 346         }
 347 }
 348
 349 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
 350 {
 351         void __iomem *mbox = tp->regs + off;
 352         writel(val, mbox);
 353         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 354                 readl(mbox);
 355 }
 356
 357 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 358 {
 359         void __iomem *mbox = tp->regs + off;
 360         writel(val, mbox);
 361         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 362                 writel(val, mbox);
 363         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 364                 readl(mbox);
 365 }
 366
 367 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tp->regs + (reg))
 368 #define tw32_rx_mbox(reg, val)  _tw32_rx_mbox(tp, reg, val)
 369 #define tw32_tx_mbox(reg, val)  _tw32_tx_mbox(tp, reg, val)
 370
 371 #define tw32(reg,val)           tg3_write_indirect_reg32(tp,(reg),(val))
 372 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 373 #define tw16(reg,val)           writew(((val) & 0xffff), tp->regs + (reg))
 374 #define tw8(reg,val)            writeb(((val) & 0xff), tp->regs + (reg))
 375 #define tr32(reg)               readl(tp->regs + (reg))
 376 #define tr16(reg)               readw(tp->regs + (reg))
 377 #define tr8(reg)                readb(tp->regs + (reg))
 378
 379 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         unsigned long flags;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 385         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 386
 387         /* Always leave this as zero. */
 388         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 389         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 390 }
 391
 392 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 393 {
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&tp->indirect_lock, flags);
 397         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 398         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 399
 400         /* Always leave this as zero. */
 401         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 402         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 403 }
 404
 405 static void tg3_disable_ints(struct tg3 *tp)
 406 {
 407         tw32(TG3PCI_MISC_HOST_CTRL,
 408              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 409         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 410         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 411 }
 412
 413 static inline void tg3_cond_int(struct tg3 *tp)
 414 {
 415         if (tp->hw_status->status & SD_STATUS_UPDATED)
 416                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 417 }
 418
 419 static void tg3_enable_ints(struct tg3 *tp)
 420 {
 421         tw32(TG3PCI_MISC_HOST_CTRL,
 422              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 423         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
 424         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 425
 426         tg3_cond_int(tp);
 427 }
 428
 429 /* tg3_restart_ints
 430  *  similar to tg3_enable_ints, but it can return without flushing the
 431  *  PIO write which reenables interrupts
 432  */
 433 static void tg3_restart_ints(struct tg3 *tp)
 434 {
 435         tw32(TG3PCI_MISC_HOST_CTRL,
 436                 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 437         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
 438         mmiowb();
 439
 440         tg3_cond_int(tp);
 441 }
 442
 443 static inline void tg3_netif_stop(struct tg3 *tp)
 444 {
 445         netif_poll_disable(tp->dev);
 446         netif_tx_disable(tp->dev);
 447 }
 448
 449 static inline void tg3_netif_start(struct tg3 *tp)
 450 {
 451         netif_wake_queue(tp->dev);
 452         /* NOTE: unconditional netif_wake_queue is only appropriate
 453          * so long as all callers are assured to have free tx slots
 454          * (such as after tg3_init_hw)
 455          */
 456         netif_poll_enable(tp->dev);
 457         tg3_cond_int(tp);
 458 }
 459
 460 static void tg3_switch_clocks(struct tg3 *tp)
 461 {
 462         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 463         u32 orig_clock_ctrl;
 464
 465         orig_clock_ctrl = clock_ctrl;
 466         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 467                        CLOCK_CTRL_CLKRUN_OENABLE |
 468                        0x1f);
 469         tp->pci_clock_ctrl = clock_ctrl;
 470
 471         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
 472             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
 473                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 474                         tw32_f(TG3PCI_CLOCK_CTRL,
 475                                clock_ctrl | CLOCK_CTRL_625_CORE);
 476                         udelay(40);
 477                 }
 478         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 479                 tw32_f(TG3PCI_CLOCK_CTRL,
 480                      clock_ctrl |
 481                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 482                 udelay(40);
 483                 tw32_f(TG3PCI_CLOCK_CTRL,
 484                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 485                 udelay(40);
 486         }
 487         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 488         udelay(40);
 489 }
 490
 491 #define PHY_BUSY_LOOPS  5000
 492
 493 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 494 {
 495         u32 frame_val;
 496         unsigned int loops;
 497         int ret;
 498
 499         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 500                 tw32_f(MAC_MI_MODE,
 501                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 502                 udelay(80);
 503         }
 504
 505         *val = 0x0;
 506
 507         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 508                       MI_COM_PHY_ADDR_MASK);
 509         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 510                       MI_COM_REG_ADDR_MASK);
 511         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 512
 513         tw32_f(MAC_MI_COM, frame_val);
 514
 515         loops = PHY_BUSY_LOOPS;
 516         while (loops != 0) {
 517                 udelay(10);
 518                 frame_val = tr32(MAC_MI_COM);
 519
 520                 if ((frame_val & MI_COM_BUSY) == 0) {
 521                         udelay(5);
 522                         frame_val = tr32(MAC_MI_COM);
 523                         break;
 524                 }
 525                 loops -= 1;
 526         }
 527
 528         ret = -EBUSY;
 529         if (loops != 0) {
 530                 *val = frame_val & MI_COM_DATA_MASK;
 531                 ret = 0;
 532         }
 533
 534         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 535                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 536                 udelay(80);
 537         }
 538
 539         return ret;
 540 }
 541
 542 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 543 {
 544         u32 frame_val;
 545         unsigned int loops;
 546         int ret;
 547
 548         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 549                 tw32_f(MAC_MI_MODE,
 550                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 551                 udelay(80);
 552         }
 553
 554         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 555                       MI_COM_PHY_ADDR_MASK);
 556         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 557                       MI_COM_REG_ADDR_MASK);
 558         frame_val |= (val & MI_COM_DATA_MASK);
 559         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 560
 561         tw32_f(MAC_MI_COM, frame_val);
 562
 563         loops = PHY_BUSY_LOOPS;
 564         while (loops != 0) {
 565                 udelay(10);
 566                 frame_val = tr32(MAC_MI_COM);
 567                 if ((frame_val & MI_COM_BUSY) == 0) {
 568                         udelay(5);
 569                         frame_val = tr32(MAC_MI_COM);
 570                         break;
 571                 }
 572                 loops -= 1;
 573         }
 574
 575         ret = -EBUSY;
 576         if (loops != 0)
 577                 ret = 0;
 578
 579         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 580                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 581                 udelay(80);
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 588 {
 589         u32 val;
 590
 591         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 592                 return;
 593
 594         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
 595         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
 596         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
 597 }
 598
 599 static int tg3_bmcr_reset(struct tg3 *tp)
 600 {
 601         u32 phy_control;
 602         int limit, err;
 603
 604         /* OK, reset it, and poll the BMCR_RESET bit until it
 605          * clears or we time out.
 606          */
 607         phy_control = BMCR_RESET;
 608         err = tg3_writephy(tp, MII_BMCR, phy_control);
 609         if (err != 0)
 610                 return -EBUSY;
 611
 612         limit = 5000;
 613         while (limit--) {
 614                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 615                 if (err != 0)
 616                         return -EBUSY;
 617
 618                 if ((phy_control & BMCR_RESET) == 0) {
 619                         udelay(40);
 620                         break;
 621                 }
 622                 udelay(10);
 623         }
 624         if (limit <= 0)
 625                 return -EBUSY;
 626
 627         return 0;
 628 }
 629
 630 static int tg3_wait_macro_done(struct tg3 *tp)
 631 {
 632         int limit = 100;
 633
 634         while (limit--) {
 635                 u32 tmp32;
 636
 637                 tg3_readphy(tp, 0x16, &tmp32);
 638                 if ((tmp32 & 0x1000) == 0)
 639                         break;
 640         }
 641         if (limit <= 0)
 642                 return -EBUSY;
 643
 644         return 0;
 645 }
 646
 647 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 648 {
 649         static const u32 test_pat[4][6] = {
 650         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 651         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 652         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 653         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 654         };
 655         int chan;
 656
 657         for (chan = 0; chan < 4; chan++) {
 658                 int i;
 659
 660                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 661                              (chan * 0x2000) | 0x0200);
 662                 tg3_writephy(tp, 0x16, 0x0002);
 663
 664                 for (i = 0; i < 6; i++)
 665                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 666                                      test_pat[chan][i]);
 667
 668                 tg3_writephy(tp, 0x16, 0x0202);
 669                 if (tg3_wait_macro_done(tp)) {
 670                         *resetp = 1;
 671                         return -EBUSY;
 672                 }
 673
 674                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 675                              (chan * 0x2000) | 0x0200);
 676                 tg3_writephy(tp, 0x16, 0x0082);
 677                 if (tg3_wait_macro_done(tp)) {
 678                         *resetp = 1;
 679                         return -EBUSY;
 680                 }
 681
 682                 tg3_writephy(tp, 0x16, 0x0802);
 683                 if (tg3_wait_macro_done(tp)) {
 684                         *resetp = 1;
 685                         return -EBUSY;
 686                 }
 687
 688                 for (i = 0; i < 6; i += 2) {
 689                         u32 low, high;
 690
 691                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
 692                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
 693                         if (tg3_wait_macro_done(tp)) {
 694                                 *resetp = 1;
 695                                 return -EBUSY;
 696                         }
 697                         low &= 0x7fff;
 698                         high &= 0x000f;
 699                         if (low != test_pat[chan][i] ||
 700                             high != test_pat[chan][i+1]) {
 701                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 702                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 703                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 704
 705                                 return -EBUSY;
 706                         }
 707                 }
 708         }
 709
 710         return 0;
 711 }
 712
 713 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 714 {
 715         int chan;
 716
 717         for (chan = 0; chan < 4; chan++) {
 718                 int i;
 719
 720                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 721                              (chan * 0x2000) | 0x0200);
 722                 tg3_writephy(tp, 0x16, 0x0002);
 723                 for (i = 0; i < 6; i++)
 724                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 725                 tg3_writephy(tp, 0x16, 0x0202);
 726                 if (tg3_wait_macro_done(tp))
 727                         return -EBUSY;
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 734 {
 735         u32 reg32, phy9_orig;
 736         int retries, do_phy_reset, err;
 737
 738         retries = 10;
 739         do_phy_reset = 1;
 740         do {
 741                 if (do_phy_reset) {
 742                         err = tg3_bmcr_reset(tp);
 743                         if (err)
 744                                 return err;
 745                         do_phy_reset = 0;
 746                 }
 747
 748                 /* Disable transmitter and interrupt.  */
 749                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
 750                 reg32 |= 0x3000;
 751                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 752
 753                 /* Set full-duplex, 1000 mbps.  */
 754                 tg3_writephy(tp, MII_BMCR,
 755                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 756
 757                 /* Set to master mode.  */
 758                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
 759                 tg3_writephy(tp, MII_TG3_CTRL,
 760                              (MII_TG3_CTRL_AS_MASTER |
 761                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 762
 763                 /* Enable SM_DSP_CLOCK and 6dB.  */
 764                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 765
 766                 /* Block the PHY control access.  */
 767                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 768                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 769
 770                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 771                 if (!err)
 772                         break;
 773         } while (--retries);
 774
 775         err = tg3_phy_reset_chanpat(tp);
 776         if (err)
 777                 return err;
 778
 779         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 780         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 781
 782         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 783         tg3_writephy(tp, 0x16, 0x0000);
 784
 785         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 786             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 787                 /* Set Extended packet length bit for jumbo frames */
 788                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 789         }
 790         else {
 791                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 792         }
 793
 794         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 795
 796         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
 797         reg32 &= ~0x3000;
 798         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 799
 800         return err;
 801 }
 802
 803 /* This will reset the tigon3 PHY if there is no valid
 804  * link unless the FORCE argument is non-zero.
 805  */
 806 static int tg3_phy_reset(struct tg3 *tp)
 807 {
 808         u32 phy_status;
 809         int err;
 810
 811         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 812         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 813         if (err != 0)
 814                 return -EBUSY;
 815
 816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 818             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 819                 err = tg3_phy_reset_5703_4_5(tp);
 820                 if (err)
 821                         return err;
 822                 goto out;
 823         }
 824
 825         err = tg3_bmcr_reset(tp);
 826         if (err)
 827                 return err;
 828
 829 out:
 830         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 831                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 832                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 833                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 834                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 835                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 836                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 837         }
 838         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 839                 tg3_writephy(tp, 0x1c, 0x8d68);
 840                 tg3_writephy(tp, 0x1c, 0x8d68);
 841         }
 842         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 843                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 844                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 845                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 846                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 847                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 848                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 849                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 850                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 851         }
 852         /* Set Extended packet length bit (bit 14) on all chips that */
 853         /* support jumbo frames */
 854         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 855                 /* Cannot do read-modify-write on 5401 */
 856                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 857         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
 858                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
 859                 u32 phy_reg;
 860
 861                 /* Set bit 14 with read-modify-write to preserve other bits */
 862                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007);
 863                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg);
 864                 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 865         }
 866         tg3_phy_set_wirespeed(tp);
 867         return 0;
 868 }
 869
 870 static void tg3_frob_aux_power(struct tg3 *tp)
 871 {
 872         struct tg3 *tp_peer = tp;
 873
 874         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
 875                 return;
 876
 877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 878                 tp_peer = pci_get_drvdata(tp->pdev_peer);
 879                 if (!tp_peer)
 880                         BUG();
 881         }
 882
 883
 884         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
 885             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
 886                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
 887                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
 888                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 889                              (GRC_LCLCTRL_GPIO_OE0 |
 890                               GRC_LCLCTRL_GPIO_OE1 |
 891                               GRC_LCLCTRL_GPIO_OE2 |
 892                               GRC_LCLCTRL_GPIO_OUTPUT0 |
 893                               GRC_LCLCTRL_GPIO_OUTPUT1));
 894                         udelay(100);
 895                 } else {
 896                         int no_gpio2;
 897                         u32 grc_local_ctrl;
 898
 899                         if (tp_peer != tp &&
 900                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 901                                 return;
 902
 903                         /* On 5753 and variants, GPIO2 cannot be used. */
 904                         no_gpio2 = (tp->nic_sram_data_cfg &
 905                                     NIC_SRAM_DATA_CFG_NO_GPIO2) != 0;
 906
 907                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 908                                          GRC_LCLCTRL_GPIO_OE1 |
 909                                          GRC_LCLCTRL_GPIO_OE2 |
 910                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
 911                                          GRC_LCLCTRL_GPIO_OUTPUT2;
 912                         if (no_gpio2) {
 913                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
 914                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
 915                         }
 916                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 917                                grc_local_ctrl);
 918                         udelay(100);
 919
 920                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 921                                          GRC_LCLCTRL_GPIO_OE1 |
 922                                          GRC_LCLCTRL_GPIO_OE2 |
 923                                          GRC_LCLCTRL_GPIO_OUTPUT0 |
 924                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
 925                                          GRC_LCLCTRL_GPIO_OUTPUT2;
 926                         if (no_gpio2) {
 927                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
 928                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
 929                         }
 930                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 931                                grc_local_ctrl);
 932                         udelay(100);
 933
 934                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 935                                          GRC_LCLCTRL_GPIO_OE1 |
 936                                          GRC_LCLCTRL_GPIO_OE2 |
 937                                          GRC_LCLCTRL_GPIO_OUTPUT0 |
 938                                          GRC_LCLCTRL_GPIO_OUTPUT1;
 939                         if (!no_gpio2) {
 940                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 941                                        grc_local_ctrl);
 942                                 udelay(100);
 943                         }
 944                 }
 945         } else {
 946                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
 947                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 948                         if (tp_peer != tp &&
 949                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 950                                 return;
 951
 952                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 953                              (GRC_LCLCTRL_GPIO_OE1 |
 954                               GRC_LCLCTRL_GPIO_OUTPUT1));
 955                         udelay(100);
 956
 957                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 958                              (GRC_LCLCTRL_GPIO_OE1));
 959                         udelay(100);
 960
 961                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 962                              (GRC_LCLCTRL_GPIO_OE1 |
 963                               GRC_LCLCTRL_GPIO_OUTPUT1));
 964                         udelay(100);
 965                 }
 966         }
 967 }
 968
 969 static int tg3_setup_phy(struct tg3 *, int);
 970
 971 #define RESET_KIND_SHUTDOWN     0
 972 #define RESET_KIND_INIT         1
 973 #define RESET_KIND_SUSPEND      2
 974
 975 static void tg3_write_sig_post_reset(struct tg3 *, int);
 976
 977 static int tg3_set_power_state(struct tg3 *tp, int state)
 978 {
 979         u32 misc_host_ctrl;
 980         u16 power_control, power_caps;
 981         int pm = tp->pm_cap;
 982
 983         /* Make sure register accesses (indirect or otherwise)
 984          * will function correctly.
 985          */
 986         pci_write_config_dword(tp->pdev,
 987                                TG3PCI_MISC_HOST_CTRL,
 988                                tp->misc_host_ctrl);
 989
 990         pci_read_config_word(tp->pdev,
 991                              pm + PCI_PM_CTRL,
 992                              &power_control);
 993         power_control |= PCI_PM_CTRL_PME_STATUS;
 994         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
 995         switch (state) {
 996         case 0:
 997                 power_control |= 0;
 998                 pci_write_config_word(tp->pdev,
 999                                       pm + PCI_PM_CTRL,
1000                                       power_control);
1001                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1002                 udelay(100);
1003
1004                 return 0;
1005
1006         case 1:
1007                 power_control |= 1;
1008                 break;
1009
1010         case 2:
1011                 power_control |= 2;
1012                 break;
1013
1014         case 3:
1015                 power_control |= 3;
1016                 break;
1017
1018         default:
1019                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1020                        "requested.\n",
1021                        tp->dev->name, state);
1022                 return -EINVAL;
1023         };
1024
1025         power_control |= PCI_PM_CTRL_PME_ENABLE;
1026
1027         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1028         tw32(TG3PCI_MISC_HOST_CTRL,
1029              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1030
1031         if (tp->link_config.phy_is_low_power == 0) {
1032                 tp->link_config.phy_is_low_power = 1;
1033                 tp->link_config.orig_speed = tp->link_config.speed;
1034                 tp->link_config.orig_duplex = tp->link_config.duplex;
1035                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1036         }
1037
1038         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1039                 tp->link_config.speed = SPEED_10;
1040                 tp->link_config.duplex = DUPLEX_HALF;
1041                 tp->link_config.autoneg = AUTONEG_ENABLE;
1042                 tg3_setup_phy(tp, 0);
1043         }
1044
1045         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1046
1047         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1048                 u32 mac_mode;
1049
1050                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1051                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1052                         udelay(40);
1053
1054                         mac_mode = MAC_MODE_PORT_MODE_MII;
1055
1056                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1057                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1058                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1059                 } else {
1060                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1061                 }
1062
1063                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
1064                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1065
1066                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1067                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1068                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1069
1070                 tw32_f(MAC_MODE, mac_mode);
1071                 udelay(100);
1072
1073                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1074                 udelay(10);
1075         }
1076
1077         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1078             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1079              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1080                 u32 base_val;
1081
1082                 base_val = tp->pci_clock_ctrl;
1083                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1084                              CLOCK_CTRL_TXCLK_DISABLE);
1085
1086                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1087                      CLOCK_CTRL_ALTCLK |
1088                      CLOCK_CTRL_PWRDOWN_PLL133);
1089                 udelay(40);
1090         } else if (!((GET_ASIC_REV(tp->pci_chip_rev_id) == 5750) &&
1091                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1092                 u32 newbits1, newbits2;
1093
1094                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1095                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1096                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1097                                     CLOCK_CTRL_TXCLK_DISABLE |
1098                                     CLOCK_CTRL_ALTCLK);
1099                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1100                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
1101                            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1102                         newbits1 = CLOCK_CTRL_625_CORE;
1103                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1104                 } else {
1105                         newbits1 = CLOCK_CTRL_ALTCLK;
1106                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1107                 }
1108
1109                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1110                 udelay(40);
1111
1112                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1113                 udelay(40);
1114
1115                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
1116                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
1117                         u32 newbits3;
1118
1119                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1120                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1121                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1122                                             CLOCK_CTRL_TXCLK_DISABLE |
1123                                             CLOCK_CTRL_44MHZ_CORE);
1124                         } else {
1125                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1126                         }
1127
1128                         tw32_f(TG3PCI_CLOCK_CTRL,
1129                                          tp->pci_clock_ctrl | newbits3);
1130                         udelay(40);
1131                 }
1132         }
1133
1134         tg3_frob_aux_power(tp);
1135
1136         /* Finally, set the new power state. */
1137         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1138
1139         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1140
1141         return 0;
1142 }
1143
1144 static void tg3_link_report(struct tg3 *tp)
1145 {
1146         if (!netif_carrier_ok(tp->dev)) {
1147                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1148         } else {
1149                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1150                        tp->dev->name,
1151                        (tp->link_config.active_speed == SPEED_1000 ?
1152                         1000 :
1153                         (tp->link_config.active_speed == SPEED_100 ?
1154                          100 : 10)),
1155                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1156                         "full" : "half"));
1157
1158                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1159                        "%s for RX.\n",
1160                        tp->dev->name,
1161                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1162                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1163         }
1164 }
1165
1166 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1167 {
1168         u32 new_tg3_flags = 0;
1169         u32 old_rx_mode = tp->rx_mode;
1170         u32 old_tx_mode = tp->tx_mode;
1171
1172         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1173                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1174                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1175                                 if (remote_adv & LPA_PAUSE_CAP)
1176                                         new_tg3_flags |=
1177                                                 (TG3_FLAG_RX_PAUSE |
1178                                                 TG3_FLAG_TX_PAUSE);
1179                                 else if (remote_adv & LPA_PAUSE_ASYM)
1180                                         new_tg3_flags |=
1181                                                 (TG3_FLAG_RX_PAUSE);
1182                         } else {
1183                                 if (remote_adv & LPA_PAUSE_CAP)
1184                                         new_tg3_flags |=
1185                                                 (TG3_FLAG_RX_PAUSE |
1186                                                 TG3_FLAG_TX_PAUSE);
1187                         }
1188                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1189                         if ((remote_adv & LPA_PAUSE_CAP) &&
1190                         (remote_adv & LPA_PAUSE_ASYM))
1191                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1192                 }
1193
1194                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1195                 tp->tg3_flags |= new_tg3_flags;
1196         } else {
1197                 new_tg3_flags = tp->tg3_flags;
1198         }
1199
1200         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1201                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1202         else
1203                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1204
1205         if (old_rx_mode != tp->rx_mode) {
1206                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1207         }
1208
1209         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1210                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1211         else
1212                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1213
1214         if (old_tx_mode != tp->tx_mode) {
1215                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1216         }
1217 }
1218
1219 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1220 {
1221         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1222         case MII_TG3_AUX_STAT_10HALF:
1223                 *speed = SPEED_10;
1224                 *duplex = DUPLEX_HALF;
1225                 break;
1226
1227         case MII_TG3_AUX_STAT_10FULL:
1228                 *speed = SPEED_10;
1229                 *duplex = DUPLEX_FULL;
1230                 break;
1231
1232         case MII_TG3_AUX_STAT_100HALF:
1233                 *speed = SPEED_100;
1234                 *duplex = DUPLEX_HALF;
1235                 break;
1236
1237         case MII_TG3_AUX_STAT_100FULL:
1238                 *speed = SPEED_100;
1239                 *duplex = DUPLEX_FULL;
1240                 break;
1241
1242         case MII_TG3_AUX_STAT_1000HALF:
1243                 *speed = SPEED_1000;
1244                 *duplex = DUPLEX_HALF;
1245                 break;
1246
1247         case MII_TG3_AUX_STAT_1000FULL:
1248                 *speed = SPEED_1000;
1249                 *duplex = DUPLEX_FULL;
1250                 break;
1251
1252         default:
1253                 *speed = SPEED_INVALID;
1254                 *duplex = DUPLEX_INVALID;
1255                 break;
1256         };
1257 }
1258
1259 static int tg3_phy_copper_begin(struct tg3 *tp)
1260 {
1261         u32 new_adv;
1262         int i;
1263
1264         if (tp->link_config.phy_is_low_power) {
1265                 /* Entering low power mode.  Disable gigabit and
1266                  * 100baseT advertisements.
1267                  */
1268                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1269
1270                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1271                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1272                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1273                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1274
1275                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1276         } else if (tp->link_config.speed == SPEED_INVALID) {
1277                 tp->link_config.advertising =
1278                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1279                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1280                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1281                          ADVERTISED_Autoneg | ADVERTISED_MII);
1282
1283                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1284                         tp->link_config.advertising &=
1285                                 ~(ADVERTISED_1000baseT_Half |
1286                                   ADVERTISED_1000baseT_Full);
1287
1288                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1289                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1290                         new_adv |= ADVERTISE_10HALF;
1291                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1292                         new_adv |= ADVERTISE_10FULL;
1293                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1294                         new_adv |= ADVERTISE_100HALF;
1295                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1296                         new_adv |= ADVERTISE_100FULL;
1297                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1298
1299                 if (tp->link_config.advertising &
1300                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1301                         new_adv = 0;
1302                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1303                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1304                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1305                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1306                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1307                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1308                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1309                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1310                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1311                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1312                 } else {
1313                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1314                 }
1315         } else {
1316                 /* Asking for a specific link mode. */
1317                 if (tp->link_config.speed == SPEED_1000) {
1318                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1319                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1320
1321                         if (tp->link_config.duplex == DUPLEX_FULL)
1322                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1323                         else
1324                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1325                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1326                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1327                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1328                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1329                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1330                 } else {
1331                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1332
1333                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1334                         if (tp->link_config.speed == SPEED_100) {
1335                                 if (tp->link_config.duplex == DUPLEX_FULL)
1336                                         new_adv |= ADVERTISE_100FULL;
1337                                 else
1338                                         new_adv |= ADVERTISE_100HALF;
1339                         } else {
1340                                 if (tp->link_config.duplex == DUPLEX_FULL)
1341                                         new_adv |= ADVERTISE_10FULL;
1342                                 else
1343                                         new_adv |= ADVERTISE_10HALF;
1344                         }
1345                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1346                 }
1347         }
1348
1349         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1350             tp->link_config.speed != SPEED_INVALID) {
1351                 u32 bmcr, orig_bmcr;
1352
1353                 tp->link_config.active_speed = tp->link_config.speed;
1354                 tp->link_config.active_duplex = tp->link_config.duplex;
1355
1356                 bmcr = 0;
1357                 switch (tp->link_config.speed) {
1358                 default:
1359                 case SPEED_10:
1360                         break;
1361
1362                 case SPEED_100:
1363                         bmcr |= BMCR_SPEED100;
1364                         break;
1365
1366                 case SPEED_1000:
1367                         bmcr |= TG3_BMCR_SPEED1000;
1368                         break;
1369                 };
1370
1371                 if (tp->link_config.duplex == DUPLEX_FULL)
1372                         bmcr |= BMCR_FULLDPLX;
1373
1374                 tg3_readphy(tp, MII_BMCR, &orig_bmcr);
1375                 if (bmcr != orig_bmcr) {
1376                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1377                         for (i = 0; i < 1500; i++) {
1378                                 u32 tmp;
1379
1380                                 udelay(10);
1381                                 tg3_readphy(tp, MII_BMSR, &tmp);
1382                                 tg3_readphy(tp, MII_BMSR, &tmp);
1383                                 if (!(tmp & BMSR_LSTATUS)) {
1384                                         udelay(40);
1385                                         break;
1386                                 }
1387                         }
1388                         tg3_writephy(tp, MII_BMCR, bmcr);
1389                         udelay(40);
1390                 }
1391         } else {
1392                 tg3_writephy(tp, MII_BMCR,
1393                              BMCR_ANENABLE | BMCR_ANRESTART);
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1400 {
1401         int err;
1402
1403         /* Turn off tap power management. */
1404         /* Set Extended packet length bit */
1405         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1406
1407         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1408         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1409
1410         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1411         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1412
1413         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1414         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1415
1416         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1417         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1418
1419         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1420         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1421
1422         udelay(40);
1423
1424         return err;
1425 }
1426
1427 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1428 {
1429         u32 adv_reg, all_mask;
1430
1431         tg3_readphy(tp, MII_ADVERTISE, &adv_reg);
1432         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1433                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1434         if ((adv_reg & all_mask) != all_mask)
1435                 return 0;
1436         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1437                 u32 tg3_ctrl;
1438
1439                 tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl);
1440                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1441                             MII_TG3_CTRL_ADV_1000_FULL);
1442                 if ((tg3_ctrl & all_mask) != all_mask)
1443                         return 0;
1444         }
1445         return 1;
1446 }
1447
1448 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1449 {
1450         int current_link_up;
1451         u32 bmsr, dummy;
1452         u16 current_speed;
1453         u8 current_duplex;
1454         int i, err;
1455
1456         tw32(MAC_EVENT, 0);
1457
1458         tw32_f(MAC_STATUS,
1459              (MAC_STATUS_SYNC_CHANGED |
1460               MAC_STATUS_CFG_CHANGED |
1461               MAC_STATUS_MI_COMPLETION |
1462               MAC_STATUS_LNKSTATE_CHANGED));
1463         udelay(40);
1464
1465         tp->mi_mode = MAC_MI_MODE_BASE;
1466         tw32_f(MAC_MI_MODE, tp->mi_mode);
1467         udelay(80);
1468
1469         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1470
1471         /* Some third-party PHYs need to be reset on link going
1472          * down.
1473          */
1474         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1475              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1476              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1477             netif_carrier_ok(tp->dev)) {
1478                 tg3_readphy(tp, MII_BMSR, &bmsr);
1479                 tg3_readphy(tp, MII_BMSR, &bmsr);
1480                 if (!(bmsr & BMSR_LSTATUS))
1481                         force_reset = 1;
1482         }
1483         if (force_reset)
1484                 tg3_phy_reset(tp);
1485
1486         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1487                 tg3_readphy(tp, MII_BMSR, &bmsr);
1488                 tg3_readphy(tp, MII_BMSR, &bmsr);
1489
1490                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1491                         bmsr = 0;
1492
1493                 if (!(bmsr & BMSR_LSTATUS)) {
1494                         err = tg3_init_5401phy_dsp(tp);
1495                         if (err)
1496                                 return err;
1497
1498                         tg3_readphy(tp, MII_BMSR, &bmsr);
1499                         for (i = 0; i < 1000; i++) {
1500                                 udelay(10);
1501                                 tg3_readphy(tp, MII_BMSR, &bmsr);
1502                                 if (bmsr & BMSR_LSTATUS) {
1503                                         udelay(40);
1504                                         break;
1505                                 }
1506                         }
1507
1508                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1509                             !(bmsr & BMSR_LSTATUS) &&
1510                             tp->link_config.active_speed == SPEED_1000) {
1511                                 err = tg3_phy_reset(tp);
1512                                 if (!err)
1513                                         err = tg3_init_5401phy_dsp(tp);
1514                                 if (err)
1515                                         return err;
1516                         }
1517                 }
1518         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1519                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1520                 /* 5701 {A0,B0} CRC bug workaround */
1521                 tg3_writephy(tp, 0x15, 0x0a75);
1522                 tg3_writephy(tp, 0x1c, 0x8c68);
1523                 tg3_writephy(tp, 0x1c, 0x8d68);
1524                 tg3_writephy(tp, 0x1c, 0x8c68);
1525         }
1526
1527         /* Clear pending interrupts... */
1528         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1529         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1530
1531         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1532                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1533         else
1534                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1535
1536         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1537             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1538                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1539                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1540                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1541                 else
1542                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1543         }
1544
1545         current_link_up = 0;
1546         current_speed = SPEED_INVALID;
1547         current_duplex = DUPLEX_INVALID;
1548
1549         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1550                 u32 val;
1551
1552                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1553                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1554                 if (!(val & (1 << 10))) {
1555                         val |= (1 << 10);
1556                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1557                         goto relink;
1558                 }
1559         }
1560
1561         bmsr = 0;
1562         for (i = 0; i < 100; i++) {
1563                 tg3_readphy(tp, MII_BMSR, &bmsr);
1564                 tg3_readphy(tp, MII_BMSR, &bmsr);
1565                 if (bmsr & BMSR_LSTATUS)
1566                         break;
1567                 udelay(40);
1568         }
1569
1570         if (bmsr & BMSR_LSTATUS) {
1571                 u32 aux_stat, bmcr;
1572
1573                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1574                 for (i = 0; i < 2000; i++) {
1575                         udelay(10);
1576                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1577                         if (aux_stat)
1578                                 break;
1579                 }
1580
1581                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1582                                              &current_speed,
1583                                              &current_duplex);
1584
1585                 bmcr = 0;
1586                 for (i = 0; i < 200; i++) {
1587                         tg3_readphy(tp, MII_BMCR, &bmcr);
1588                         tg3_readphy(tp, MII_BMCR, &bmcr);
1589                         if (bmcr && bmcr != 0x7fff)
1590                                 break;
1591                         udelay(10);
1592                 }
1593
1594                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1595                         if (bmcr & BMCR_ANENABLE) {
1596                                 current_link_up = 1;
1597
1598                                 /* Force autoneg restart if we are exiting
1599                                  * low power mode.
1600                                  */
1601                                 if (!tg3_copper_is_advertising_all(tp))
1602                                         current_link_up = 0;
1603                         } else {
1604                                 current_link_up = 0;
1605                         }
1606                 } else {
1607                         if (!(bmcr & BMCR_ANENABLE) &&
1608                             tp->link_config.speed == current_speed &&
1609                             tp->link_config.duplex == current_duplex) {
1610                                 current_link_up = 1;
1611                         } else {
1612                                 current_link_up = 0;
1613                         }
1614                 }
1615
1616                 tp->link_config.active_speed = current_speed;
1617                 tp->link_config.active_duplex = current_duplex;
1618         }
1619
1620         if (current_link_up == 1 &&
1621             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1622             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1623                 u32 local_adv, remote_adv;
1624
1625                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
1626                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1627
1628                 tg3_readphy(tp, MII_LPA, &remote_adv);
1629                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1630
1631                 /* If we are not advertising full pause capability,
1632                  * something is wrong.  Bring the link down and reconfigure.
1633                  */
1634                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1635                         current_link_up = 0;
1636                 } else {
1637                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1638                 }
1639         }
1640 relink:
1641         if (current_link_up == 0) {
1642                 u32 tmp;
1643
1644                 tg3_phy_copper_begin(tp);
1645
1646                 tg3_readphy(tp, MII_BMSR, &tmp);
1647                 tg3_readphy(tp, MII_BMSR, &tmp);
1648                 if (tmp & BMSR_LSTATUS)
1649                         current_link_up = 1;
1650         }
1651
1652         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1653         if (current_link_up == 1) {
1654                 if (tp->link_config.active_speed == SPEED_100 ||
1655                     tp->link_config.active_speed == SPEED_10)
1656                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1657                 else
1658                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1659         } else
1660                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1661
1662         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1663         if (tp->link_config.active_duplex == DUPLEX_HALF)
1664                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1665
1666         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1667         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1668                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1669                     (current_link_up == 1 &&
1670                      tp->link_config.active_speed == SPEED_10))
1671                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1672         } else {
1673                 if (current_link_up == 1)
1674                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1675         }
1676
1677         /* ??? Without this setting Netgear GA302T PHY does not
1678          * ??? send/receive packets...
1679          */
1680         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1681             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1682                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1683                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1684                 udelay(80);
1685         }
1686
1687         tw32_f(MAC_MODE, tp->mac_mode);
1688         udelay(40);
1689
1690         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1691                 /* Polled via timer. */
1692                 tw32_f(MAC_EVENT, 0);
1693         } else {
1694                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1695         }
1696         udelay(40);
1697
1698         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1699             current_link_up == 1 &&
1700             tp->link_config.active_speed == SPEED_1000 &&
1701             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1702              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1703                 udelay(120);
1704                 tw32_f(MAC_STATUS,
1705                      (MAC_STATUS_SYNC_CHANGED |
1706                       MAC_STATUS_CFG_CHANGED));
1707                 udelay(40);
1708                 tg3_write_mem(tp,
1709                               NIC_SRAM_FIRMWARE_MBOX,
1710                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1711         }
1712
1713         if (current_link_up != netif_carrier_ok(tp->dev)) {
1714                 if (current_link_up)
1715                         netif_carrier_on(tp->dev);
1716                 else
1717                         netif_carrier_off(tp->dev);
1718                 tg3_link_report(tp);
1719         }
1720
1721         return 0;
1722 }
1723
1724 struct tg3_fiber_aneginfo {
1725         int state;
1726 #define ANEG_STATE_UNKNOWN              0
1727 #define ANEG_STATE_AN_ENABLE            1
1728 #define ANEG_STATE_RESTART_INIT         2
1729 #define ANEG_STATE_RESTART              3
1730 #define ANEG_STATE_DISABLE_LINK_OK      4
1731 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1732 #define ANEG_STATE_ABILITY_DETECT       6
1733 #define ANEG_STATE_ACK_DETECT_INIT      7
1734 #define ANEG_STATE_ACK_DETECT           8
1735 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1736 #define ANEG_STATE_COMPLETE_ACK         10
1737 #define ANEG_STATE_IDLE_DETECT_INIT     11
1738 #define ANEG_STATE_IDLE_DETECT          12
1739 #define ANEG_STATE_LINK_OK              13
1740 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1741 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1742
1743         u32 flags;
1744 #define MR_AN_ENABLE            0x00000001
1745 #define MR_RESTART_AN           0x00000002
1746 #define MR_AN_COMPLETE          0x00000004
1747 #define MR_PAGE_RX              0x00000008
1748 #define MR_NP_LOADED            0x00000010
1749 #define MR_TOGGLE_TX            0x00000020
1750 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1751 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1752 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1753 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1754 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1755 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1756 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1757 #define MR_TOGGLE_RX            0x00002000
1758 #define MR_NP_RX                0x00004000
1759
1760 #define MR_LINK_OK              0x80000000
1761
1762         unsigned long link_time, cur_time;
1763
1764         u32 ability_match_cfg;
1765         int ability_match_count;
1766
1767         char ability_match, idle_match, ack_match;
1768
1769         u32 txconfig, rxconfig;
1770 #define ANEG_CFG_NP             0x00000080
1771 #define ANEG_CFG_ACK            0x00000040
1772 #define ANEG_CFG_RF2            0x00000020
1773 #define ANEG_CFG_RF1            0x00000010
1774 #define ANEG_CFG_PS2            0x00000001
1775 #define ANEG_CFG_PS1            0x00008000
1776 #define ANEG_CFG_HD             0x00004000
1777 #define ANEG_CFG_FD             0x00002000
1778 #define ANEG_CFG_INVAL          0x00001f06
1779
1780 };
1781 #define ANEG_OK         0
1782 #define ANEG_DONE       1
1783 #define ANEG_TIMER_ENAB 2
1784 #define ANEG_FAILED     -1
1785
1786 #define ANEG_STATE_SETTLE_TIME  10000
1787
1788 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1789                                    struct tg3_fiber_aneginfo *ap)
1790 {
1791         unsigned long delta;
1792         u32 rx_cfg_reg;
1793         int ret;
1794
1795         if (ap->state == ANEG_STATE_UNKNOWN) {
1796                 ap->rxconfig = 0;
1797                 ap->link_time = 0;
1798                 ap->cur_time = 0;
1799                 ap->ability_match_cfg = 0;
1800                 ap->ability_match_count = 0;
1801                 ap->ability_match = 0;
1802                 ap->idle_match = 0;
1803                 ap->ack_match = 0;
1804         }
1805         ap->cur_time++;
1806
1807         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1808                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1809
1810                 if (rx_cfg_reg != ap->ability_match_cfg) {
1811                         ap->ability_match_cfg = rx_cfg_reg;
1812                         ap->ability_match = 0;
1813                         ap->ability_match_count = 0;
1814                 } else {
1815                         if (++ap->ability_match_count > 1) {
1816                                 ap->ability_match = 1;
1817                                 ap->ability_match_cfg = rx_cfg_reg;
1818                         }
1819                 }
1820                 if (rx_cfg_reg & ANEG_CFG_ACK)
1821                         ap->ack_match = 1;
1822                 else
1823                         ap->ack_match = 0;
1824
1825                 ap->idle_match = 0;
1826         } else {
1827                 ap->idle_match = 1;
1828                 ap->ability_match_cfg = 0;
1829                 ap->ability_match_count = 0;
1830                 ap->ability_match = 0;
1831                 ap->ack_match = 0;
1832
1833                 rx_cfg_reg = 0;
1834         }
1835
1836         ap->rxconfig = rx_cfg_reg;
1837         ret = ANEG_OK;
1838
1839         switch(ap->state) {
1840         case ANEG_STATE_UNKNOWN:
1841                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1842                         ap->state = ANEG_STATE_AN_ENABLE;
1843
1844                 /* fallthru */
1845         case ANEG_STATE_AN_ENABLE:
1846                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1847                 if (ap->flags & MR_AN_ENABLE) {
1848                         ap->link_time = 0;
1849                         ap->cur_time = 0;
1850                         ap->ability_match_cfg = 0;
1851                         ap->ability_match_count = 0;
1852                         ap->ability_match = 0;
1853                         ap->idle_match = 0;
1854                         ap->ack_match = 0;
1855
1856                         ap->state = ANEG_STATE_RESTART_INIT;
1857                 } else {
1858                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1859                 }
1860                 break;
1861
1862         case ANEG_STATE_RESTART_INIT:
1863                 ap->link_time = ap->cur_time;
1864                 ap->flags &= ~(MR_NP_LOADED);
1865                 ap->txconfig = 0;
1866                 tw32(MAC_TX_AUTO_NEG, 0);
1867                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1868                 tw32_f(MAC_MODE, tp->mac_mode);
1869                 udelay(40);
1870
1871                 ret = ANEG_TIMER_ENAB;
1872                 ap->state = ANEG_STATE_RESTART;
1873
1874                 /* fallthru */
1875         case ANEG_STATE_RESTART:
1876                 delta = ap->cur_time - ap->link_time;
1877                 if (delta > ANEG_STATE_SETTLE_TIME) {
1878                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1879                 } else {
1880                         ret = ANEG_TIMER_ENAB;
1881                 }
1882                 break;
1883
1884         case ANEG_STATE_DISABLE_LINK_OK:
1885                 ret = ANEG_DONE;
1886                 break;
1887
1888         case ANEG_STATE_ABILITY_DETECT_INIT:
1889                 ap->flags &= ~(MR_TOGGLE_TX);
1890                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1891                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1892                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1893                 tw32_f(MAC_MODE, tp->mac_mode);
1894                 udelay(40);
1895
1896                 ap->state = ANEG_STATE_ABILITY_DETECT;
1897                 break;
1898
1899         case ANEG_STATE_ABILITY_DETECT:
1900                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1901                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1902                 }
1903                 break;
1904
1905         case ANEG_STATE_ACK_DETECT_INIT:
1906                 ap->txconfig |= ANEG_CFG_ACK;
1907                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1908                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1909                 tw32_f(MAC_MODE, tp->mac_mode);
1910                 udelay(40);
1911
1912                 ap->state = ANEG_STATE_ACK_DETECT;
1913
1914                 /* fallthru */
1915         case ANEG_STATE_ACK_DETECT:
1916                 if (ap->ack_match != 0) {
1917                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1918                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1919                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1920                         } else {
1921                                 ap->state = ANEG_STATE_AN_ENABLE;
1922                         }
1923                 } else if (ap->ability_match != 0 &&
1924                            ap->rxconfig == 0) {
1925                         ap->state = ANEG_STATE_AN_ENABLE;
1926                 }
1927                 break;
1928
1929         case ANEG_STATE_COMPLETE_ACK_INIT:
1930                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1931                         ret = ANEG_FAILED;
1932                         break;
1933                 }
1934                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1935                                MR_LP_ADV_HALF_DUPLEX |
1936                                MR_LP_ADV_SYM_PAUSE |
1937                                MR_LP_ADV_ASYM_PAUSE |
1938                                MR_LP_ADV_REMOTE_FAULT1 |
1939                                MR_LP_ADV_REMOTE_FAULT2 |
1940                                MR_LP_ADV_NEXT_PAGE |
1941                                MR_TOGGLE_RX |
1942                                MR_NP_RX);
1943                 if (ap->rxconfig & ANEG_CFG_FD)
1944                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1945                 if (ap->rxconfig & ANEG_CFG_HD)
1946                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1947                 if (ap->rxconfig & ANEG_CFG_PS1)
1948                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1949                 if (ap->rxconfig & ANEG_CFG_PS2)
1950                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1951                 if (ap->rxconfig & ANEG_CFG_RF1)
1952                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1953                 if (ap->rxconfig & ANEG_CFG_RF2)
1954                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1955                 if (ap->rxconfig & ANEG_CFG_NP)
1956                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1957
1958                 ap->link_time = ap->cur_time;
1959
1960                 ap->flags ^= (MR_TOGGLE_TX);
1961                 if (ap->rxconfig & 0x0008)
1962                         ap->flags |= MR_TOGGLE_RX;
1963                 if (ap->rxconfig & ANEG_CFG_NP)
1964                         ap->flags |= MR_NP_RX;
1965                 ap->flags |= MR_PAGE_RX;
1966
1967                 ap->state = ANEG_STATE_COMPLETE_ACK;
1968                 ret = ANEG_TIMER_ENAB;
1969                 break;
1970
1971         case ANEG_STATE_COMPLETE_ACK:
1972                 if (ap->ability_match != 0 &&
1973                     ap->rxconfig == 0) {
1974                         ap->state = ANEG_STATE_AN_ENABLE;
1975                         break;
1976                 }
1977                 delta = ap->cur_time - ap->link_time;
1978                 if (delta > ANEG_STATE_SETTLE_TIME) {
1979                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1980                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1981                         } else {
1982                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1983                                     !(ap->flags & MR_NP_RX)) {
1984                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1985                                 } else {
1986                                         ret = ANEG_FAILED;
1987                                 }
1988                         }
1989                 }
1990                 break;
1991
1992         case ANEG_STATE_IDLE_DETECT_INIT:
1993                 ap->link_time = ap->cur_time;
1994                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1995                 tw32_f(MAC_MODE, tp->mac_mode);
1996                 udelay(40);
1997
1998                 ap->state = ANEG_STATE_IDLE_DETECT;
1999                 ret = ANEG_TIMER_ENAB;
2000                 break;
2001
2002         case ANEG_STATE_IDLE_DETECT:
2003                 if (ap->ability_match != 0 &&
2004                     ap->rxconfig == 0) {
2005                         ap->state = ANEG_STATE_AN_ENABLE;
2006                         break;
2007                 }
2008                 delta = ap->cur_time - ap->link_time;
2009                 if (delta > ANEG_STATE_SETTLE_TIME) {
2010                         /* XXX another gem from the Broadcom driver :( */
2011                         ap->state = ANEG_STATE_LINK_OK;
2012                 }
2013                 break;
2014
2015         case ANEG_STATE_LINK_OK:
2016                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2017                 ret = ANEG_DONE;
2018                 break;
2019
2020         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2021                 /* ??? unimplemented */
2022                 break;
2023
2024         case ANEG_STATE_NEXT_PAGE_WAIT:
2025                 /* ??? unimplemented */
2026                 break;
2027
2028         default:
2029                 ret = ANEG_FAILED;
2030                 break;
2031         };
2032
2033         return ret;
2034 }
2035
2036 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2037 {
2038         int res = 0;
2039         struct tg3_fiber_aneginfo aninfo;
2040         int status = ANEG_FAILED;
2041         unsigned int tick;
2042         u32 tmp;
2043
2044         tw32_f(MAC_TX_AUTO_NEG, 0);
2045
2046         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2047         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2048         udelay(40);
2049
2050         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2051         udelay(40);
2052
2053         memset(&aninfo, 0, sizeof(aninfo));
2054         aninfo.flags |= MR_AN_ENABLE;
2055         aninfo.state = ANEG_STATE_UNKNOWN;
2056         aninfo.cur_time = 0;
2057         tick = 0;
2058         while (++tick < 195000) {
2059                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2060                 if (status == ANEG_DONE || status == ANEG_FAILED)
2061                         break;
2062
2063                 udelay(1);
2064         }
2065
2066         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2067         tw32_f(MAC_MODE, tp->mac_mode);
2068         udelay(40);
2069
2070         *flags = aninfo.flags;
2071
2072         if (status == ANEG_DONE &&
2073             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2074                              MR_LP_ADV_FULL_DUPLEX)))
2075                 res = 1;
2076
2077         return res;
2078 }
2079
2080 static void tg3_init_bcm8002(struct tg3 *tp)
2081 {
2082         u32 mac_status = tr32(MAC_STATUS);
2083         int i;
2084
2085         /* Reset when initting first time or we have a link. */
2086         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2087             !(mac_status & MAC_STATUS_PCS_SYNCED))
2088                 return;
2089
2090         /* Set PLL lock range. */
2091         tg3_writephy(tp, 0x16, 0x8007);
2092
2093         /* SW reset */
2094         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2095
2096         /* Wait for reset to complete. */
2097         /* XXX schedule_timeout() ... */
2098         for (i = 0; i < 500; i++)
2099                 udelay(10);
2100
2101         /* Config mode; select PMA/Ch 1 regs. */
2102         tg3_writephy(tp, 0x10, 0x8411);
2103
2104         /* Enable auto-lock and comdet, select txclk for tx. */
2105         tg3_writephy(tp, 0x11, 0x0a10);
2106
2107         tg3_writephy(tp, 0x18, 0x00a0);
2108         tg3_writephy(tp, 0x16, 0x41ff);
2109
2110         /* Assert and deassert POR. */
2111         tg3_writephy(tp, 0x13, 0x0400);
2112         udelay(40);
2113         tg3_writephy(tp, 0x13, 0x0000);
2114
2115         tg3_writephy(tp, 0x11, 0x0a50);
2116         udelay(40);
2117         tg3_writephy(tp, 0x11, 0x0a10);
2118
2119         /* Wait for signal to stabilize */
2120         /* XXX schedule_timeout() ... */
2121         for (i = 0; i < 15000; i++)
2122                 udelay(10);
2123
2124         /* Deselect the channel register so we can read the PHYID
2125          * later.
2126          */
2127         tg3_writephy(tp, 0x10, 0x8011);
2128 }
2129
2130 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2131 {
2132         u32 sg_dig_ctrl, sg_dig_status;
2133         u32 serdes_cfg, expected_sg_dig_ctrl;
2134         int workaround, port_a;
2135         int current_link_up;
2136
2137         serdes_cfg = 0;
2138         expected_sg_dig_ctrl = 0;
2139         workaround = 0;
2140         port_a = 1;
2141         current_link_up = 0;
2142
2143         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2144             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2145                 workaround = 1;
2146                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2147                         port_a = 0;
2148
2149                 serdes_cfg = tr32(MAC_SERDES_CFG) &
2150                         ((1 << 23) | (1 << 22) | (1 << 21) | (1 << 20));
2151         }
2152
2153         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2154
2155         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2156                 if (sg_dig_ctrl & (1 << 31)) {
2157                         if (workaround) {
2158                                 u32 val = serdes_cfg;
2159
2160                                 if (port_a)
2161                                         val |= 0xc010880;
2162                                 else
2163                                         val |= 0x4010880;
2164                                 tw32_f(MAC_SERDES_CFG, val);
2165                         }
2166                         tw32_f(SG_DIG_CTRL, 0x01388400);
2167                 }
2168                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2169                         tg3_setup_flow_control(tp, 0, 0);
2170                         current_link_up = 1;
2171                 }
2172                 goto out;
2173         }
2174
2175         /* Want auto-negotiation.  */
2176         expected_sg_dig_ctrl = 0x81388400;
2177
2178         /* Pause capability */
2179         expected_sg_dig_ctrl |= (1 << 11);
2180
2181         /* Asymettric pause */
2182         expected_sg_dig_ctrl |= (1 << 12);
2183
2184         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2185                 if (workaround)
2186                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011880);
2187                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2188                 udelay(5);
2189                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2190
2191                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2192         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2193                                  MAC_STATUS_SIGNAL_DET)) {
2194                 int i;
2195
2196                 /* Giver time to negotiate (~200ms) */
2197                 for (i = 0; i < 40000; i++) {
2198                         sg_dig_status = tr32(SG_DIG_STATUS);
2199                         if (sg_dig_status & (0x3))
2200                                 break;
2201                         udelay(5);
2202                 }
2203                 mac_status = tr32(MAC_STATUS);
2204
2205                 if ((sg_dig_status & (1 << 1)) &&
2206                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2207                         u32 local_adv, remote_adv;
2208
2209                         local_adv = ADVERTISE_PAUSE_CAP;
2210                         remote_adv = 0;
2211                         if (sg_dig_status & (1 << 19))
2212                                 remote_adv |= LPA_PAUSE_CAP;
2213                         if (sg_dig_status & (1 << 20))
2214                                 remote_adv |= LPA_PAUSE_ASYM;
2215
2216                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2217                         current_link_up = 1;
2218                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2219                 } else if (!(sg_dig_status & (1 << 1))) {
2220                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2221                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2222                         else {
2223                                 if (workaround) {
2224                                         u32 val = serdes_cfg;
2225
2226                                         if (port_a)
2227                                                 val |= 0xc010880;
2228                                         else
2229                                                 val |= 0x4010880;
2230
2231                                         tw32_f(MAC_SERDES_CFG, val);
2232                                 }
2233
2234                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2235                                 udelay(40);
2236
2237                                 mac_status = tr32(MAC_STATUS);
2238                                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2239                                         tg3_setup_flow_control(tp, 0, 0);
2240                                         current_link_up = 1;
2241                                 }
2242                         }
2243                 }
2244         }
2245
2246 out:
2247         return current_link_up;
2248 }
2249
2250 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2251 {
2252         int current_link_up = 0;
2253
2254         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2255                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2256                 goto out;
2257         }
2258
2259         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2260                 u32 flags;
2261                 int i;
2262
2263                 if (fiber_autoneg(tp, &flags)) {
2264                         u32 local_adv, remote_adv;
2265
2266                         local_adv = ADVERTISE_PAUSE_CAP;
2267                         remote_adv = 0;
2268                         if (flags & MR_LP_ADV_SYM_PAUSE)
2269                                 remote_adv |= LPA_PAUSE_CAP;
2270                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2271                                 remote_adv |= LPA_PAUSE_ASYM;
2272
2273                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2274
2275                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2276                         current_link_up = 1;
2277                 }
2278                 for (i = 0; i < 30; i++) {
2279                         udelay(20);
2280                         tw32_f(MAC_STATUS,
2281                                (MAC_STATUS_SYNC_CHANGED |
2282                                 MAC_STATUS_CFG_CHANGED));
2283                         udelay(40);
2284                         if ((tr32(MAC_STATUS) &
2285                              (MAC_STATUS_SYNC_CHANGED |
2286                               MAC_STATUS_CFG_CHANGED)) == 0)
2287                                 break;
2288                 }
2289
2290                 mac_status = tr32(MAC_STATUS);
2291                 if (current_link_up == 0 &&
2292                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2293                     !(mac_status & MAC_STATUS_RCVD_CFG))
2294                         current_link_up = 1;
2295         } else {
2296                 /* Forcing 1000FD link up. */
2297                 current_link_up = 1;
2298                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2299
2300                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2301                 udelay(40);
2302         }
2303
2304 out:
2305         return current_link_up;
2306 }
2307
2308 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2309 {
2310         u32 orig_pause_cfg;
2311         u16 orig_active_speed;
2312         u8 orig_active_duplex;
2313         u32 mac_status;
2314         int current_link_up;
2315         int i;
2316
2317         orig_pause_cfg =
2318                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2319                                   TG3_FLAG_TX_PAUSE));
2320         orig_active_speed = tp->link_config.active_speed;
2321         orig_active_duplex = tp->link_config.active_duplex;
2322
2323         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2324             netif_carrier_ok(tp->dev) &&
2325             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2326                 mac_status = tr32(MAC_STATUS);
2327                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2328                                MAC_STATUS_SIGNAL_DET |
2329                                MAC_STATUS_CFG_CHANGED |
2330                                MAC_STATUS_RCVD_CFG);
2331                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2332                                    MAC_STATUS_SIGNAL_DET)) {
2333                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2334                                             MAC_STATUS_CFG_CHANGED));
2335                         return 0;
2336                 }
2337         }
2338
2339         tw32_f(MAC_TX_AUTO_NEG, 0);
2340
2341         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2342         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2343         tw32_f(MAC_MODE, tp->mac_mode);
2344         udelay(40);
2345
2346         if (tp->phy_id == PHY_ID_BCM8002)
2347                 tg3_init_bcm8002(tp);
2348
2349         /* Enable link change event even when serdes polling.  */
2350         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2351         udelay(40);
2352
2353         current_link_up = 0;
2354         mac_status = tr32(MAC_STATUS);
2355
2356         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2357                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2358         else
2359                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2360
2361         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2362         tw32_f(MAC_MODE, tp->mac_mode);
2363         udelay(40);
2364
2365         tp->hw_status->status =
2366                 (SD_STATUS_UPDATED |
2367                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2368
2369         for (i = 0; i < 100; i++) {
2370                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2371                                     MAC_STATUS_CFG_CHANGED));
2372                 udelay(5);
2373                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2374                                          MAC_STATUS_CFG_CHANGED)) == 0)
2375                         break;
2376         }
2377
2378         mac_status = tr32(MAC_STATUS);
2379         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2380                 current_link_up = 0;
2381                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2382                         tw32_f(MAC_MODE, (tp->mac_mode |
2383                                           MAC_MODE_SEND_CONFIGS));
2384                         udelay(1);
2385                         tw32_f(MAC_MODE, tp->mac_mode);
2386                 }
2387         }
2388
2389         if (current_link_up == 1) {
2390                 tp->link_config.active_speed = SPEED_1000;
2391                 tp->link_config.active_duplex = DUPLEX_FULL;
2392                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2393                                     LED_CTRL_LNKLED_OVERRIDE |
2394                                     LED_CTRL_1000MBPS_ON));
2395         } else {
2396                 tp->link_config.active_speed = SPEED_INVALID;
2397                 tp->link_config.active_duplex = DUPLEX_INVALID;
2398                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2399                                     LED_CTRL_LNKLED_OVERRIDE |
2400                                     LED_CTRL_TRAFFIC_OVERRIDE));
2401         }
2402
2403         if (current_link_up != netif_carrier_ok(tp->dev)) {
2404                 if (current_link_up)
2405                         netif_carrier_on(tp->dev);
2406                 else
2407                         netif_carrier_off(tp->dev);
2408                 tg3_link_report(tp);
2409         } else {
2410                 u32 now_pause_cfg =
2411                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2412                                          TG3_FLAG_TX_PAUSE);
2413                 if (orig_pause_cfg != now_pause_cfg ||
2414                     orig_active_speed != tp->link_config.active_speed ||
2415                     orig_active_duplex != tp->link_config.active_duplex)
2416                         tg3_link_report(tp);
2417         }
2418
2419         return 0;
2420 }
2421
2422 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2423 {
2424         int err;
2425
2426         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2427                 err = tg3_setup_fiber_phy(tp, force_reset);
2428         } else {
2429                 err = tg3_setup_copper_phy(tp, force_reset);
2430         }
2431
2432         if (tp->link_config.active_speed == SPEED_1000 &&
2433             tp->link_config.active_duplex == DUPLEX_HALF)
2434                 tw32(MAC_TX_LENGTHS,
2435                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2436                       (6 << TX_LENGTHS_IPG_SHIFT) |
2437                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2438         else
2439                 tw32(MAC_TX_LENGTHS,
2440                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2441                       (6 << TX_LENGTHS_IPG_SHIFT) |
2442                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2443
2444         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
2445             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
2446                 if (netif_carrier_ok(tp->dev)) {
2447                         tw32(HOSTCC_STAT_COAL_TICKS,
2448                              DEFAULT_STAT_COAL_TICKS);
2449                 } else {
2450                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2451                 }
2452         }
2453
2454         return err;
2455 }
2456
2457 /* Tigon3 never reports partial packet sends.  So we do not
2458  * need special logic to handle SKBs that have not had all
2459  * of their frags sent yet, like SunGEM does.
2460  */
2461 static void tg3_tx(struct tg3 *tp)
2462 {
2463         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2464         u32 sw_idx = tp->tx_cons;
2465
2466         while (sw_idx != hw_idx) {
2467                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2468                 struct sk_buff *skb = ri->skb;
2469                 int i;
2470
2471                 if (unlikely(skb == NULL))
2472                         BUG();
2473
2474                 pci_unmap_single(tp->pdev,
2475                                  pci_unmap_addr(ri, mapping),
2476                                  skb_headlen(skb),
2477                                  PCI_DMA_TODEVICE);
2478
2479                 ri->skb = NULL;
2480
2481                 sw_idx = NEXT_TX(sw_idx);
2482
2483                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2484                         if (unlikely(sw_idx == hw_idx))
2485                                 BUG();
2486
2487                         ri = &tp->tx_buffers[sw_idx];
2488                         if (unlikely(ri->skb != NULL))
2489                                 BUG();
2490
2491                         pci_unmap_page(tp->pdev,
2492                                        pci_unmap_addr(ri, mapping),
2493                                        skb_shinfo(skb)->frags[i].size,
2494                                        PCI_DMA_TODEVICE);
2495
2496                         sw_idx = NEXT_TX(sw_idx);
2497                 }
2498
2499                 dev_kfree_skb_irq(skb);
2500         }
2501
2502         tp->tx_cons = sw_idx;
2503
2504         if (netif_queue_stopped(tp->dev) &&
2505             (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2506                 netif_wake_queue(tp->dev);
2507 }
2508
2509 /* Returns size of skb allocated or < 0 on error.
2510  *
2511  * We only need to fill in the address because the other members
2512  * of the RX descriptor are invariant, see tg3_init_rings.
2513  *
2514  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2515  * posting buffers we only dirty the first cache line of the RX
2516  * descriptor (containing the address).  Whereas for the RX status
2517  * buffers the cpu only reads the last cacheline of the RX descriptor
2518  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2519  */
2520 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2521                             int src_idx, u32 dest_idx_unmasked)
2522 {
2523         struct tg3_rx_buffer_desc *desc;
2524         struct ring_info *map, *src_map;
2525         struct sk_buff *skb;
2526         dma_addr_t mapping;
2527         int skb_size, dest_idx;
2528
2529         src_map = NULL;
2530         switch (opaque_key) {
2531         case RXD_OPAQUE_RING_STD:
2532                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2533                 desc = &tp->rx_std[dest_idx];
2534                 map = &tp->rx_std_buffers[dest_idx];
2535                 if (src_idx >= 0)
2536                         src_map = &tp->rx_std_buffers[src_idx];
2537                 skb_size = RX_PKT_BUF_SZ;
2538                 break;
2539
2540         case RXD_OPAQUE_RING_JUMBO:
2541                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2542                 desc = &tp->rx_jumbo[dest_idx];
2543                 map = &tp->rx_jumbo_buffers[dest_idx];
2544                 if (src_idx >= 0)
2545                         src_map = &tp->rx_jumbo_buffers[src_idx];
2546                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2547                 break;
2548
2549         default:
2550                 return -EINVAL;
2551         };
2552
2553         /* Do not overwrite any of the map or rp information
2554          * until we are sure we can commit to a new buffer.
2555          *
2556          * Callers depend upon this behavior and assume that
2557          * we leave everything unchanged if we fail.
2558          */
2559         skb = dev_alloc_skb(skb_size);
2560         if (skb == NULL)
2561                 return -ENOMEM;
2562
2563         skb->dev = tp->dev;
2564         skb_reserve(skb, tp->rx_offset);
2565
2566         mapping = pci_map_single(tp->pdev, skb->data,
2567                                  skb_size - tp->rx_offset,
2568                                  PCI_DMA_FROMDEVICE);
2569
2570         map->skb = skb;
2571         pci_unmap_addr_set(map, mapping, mapping);
2572
2573         if (src_map != NULL)
2574                 src_map->skb = NULL;
2575
2576         desc->addr_hi = ((u64)mapping >> 32);
2577         desc->addr_lo = ((u64)mapping & 0xffffffff);
2578
2579         return skb_size;
2580 }
2581
2582 /* We only need to move over in the address because the other
2583  * members of the RX descriptor are invariant.  See notes above
2584  * tg3_alloc_rx_skb for full details.
2585  */
2586 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2587                            int src_idx, u32 dest_idx_unmasked)
2588 {
2589         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2590         struct ring_info *src_map, *dest_map;
2591         int dest_idx;
2592
2593         switch (opaque_key) {
2594         case RXD_OPAQUE_RING_STD:
2595                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2596                 dest_desc = &tp->rx_std[dest_idx];
2597                 dest_map = &tp->rx_std_buffers[dest_idx];
2598                 src_desc = &tp->rx_std[src_idx];
2599                 src_map = &tp->rx_std_buffers[src_idx];
2600                 break;
2601
2602         case RXD_OPAQUE_RING_JUMBO:
2603                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2604                 dest_desc = &tp->rx_jumbo[dest_idx];
2605                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2606                 src_desc = &tp->rx_jumbo[src_idx];
2607                 src_map = &tp->rx_jumbo_buffers[src_idx];
2608                 break;
2609
2610         default:
2611                 return;
2612         };
2613
2614         dest_map->skb = src_map->skb;
2615         pci_unmap_addr_set(dest_map, mapping,
2616                            pci_unmap_addr(src_map, mapping));
2617         dest_desc->addr_hi = src_desc->addr_hi;
2618         dest_desc->addr_lo = src_desc->addr_lo;
2619
2620         src_map->skb = NULL;
2621 }
2622
2623 #if TG3_VLAN_TAG_USED
2624 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2625 {
2626         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2627 }
2628 #endif
2629
2630 /* The RX ring scheme is composed of multiple rings which post fresh
2631  * buffers to the chip, and one special ring the chip uses to report
2632  * status back to the host.
2633  *
2634  * The special ring reports the status of received packets to the
2635  * host.  The chip does not write into the original descriptor the
2636  * RX buffer was obtained from.  The chip simply takes the original
2637  * descriptor as provided by the host, updates the status and length
2638  * field, then writes this into the next status ring entry.
2639  *
2640  * Each ring the host uses to post buffers to the chip is described
2641  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
2642  * it is first placed into the on-chip ram.  When the packet's length
2643  * is known, it walks down the TG3_BDINFO entries to select the ring.
2644  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2645  * which is within the range of the new packet's length is chosen.
2646  *
2647  * The "separate ring for rx status" scheme may sound queer, but it makes
2648  * sense from a cache coherency perspective.  If only the host writes
2649  * to the buffer post rings, and only the chip writes to the rx status
2650  * rings, then cache lines never move beyond shared-modified state.
2651  * If both the host and chip were to write into the same ring, cache line
2652  * eviction could occur since both entities want it in an exclusive state.
2653  */
2654 static int tg3_rx(struct tg3 *tp, int budget)
2655 {
2656         u32 work_mask;
2657         u32 rx_rcb_ptr = tp->rx_rcb_ptr;
2658         u16 hw_idx, sw_idx;
2659         int received;
2660
2661         hw_idx = tp->hw_status->idx[0].rx_producer;
2662         /*
2663          * We need to order the read of hw_idx and the read of
2664          * the opaque cookie.
2665          */
2666         rmb();
2667         sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2668         work_mask = 0;
2669         received = 0;
2670         while (sw_idx != hw_idx && budget > 0) {
2671                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2672                 unsigned int len;
2673                 struct sk_buff *skb;
2674                 dma_addr_t dma_addr;
2675                 u32 opaque_key, desc_idx, *post_ptr;
2676
2677                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2678                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2679                 if (opaque_key == RXD_OPAQUE_RING_STD) {
2680                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2681                                                   mapping);
2682                         skb = tp->rx_std_buffers[desc_idx].skb;
2683                         post_ptr = &tp->rx_std_ptr;
2684                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2685                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2686                                                   mapping);
2687                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
2688                         post_ptr = &tp->rx_jumbo_ptr;
2689                 }
2690                 else {
2691                         goto next_pkt_nopost;
2692                 }
2693
2694                 work_mask |= opaque_key;
2695
2696                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2697                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2698                 drop_it:
2699                         tg3_recycle_rx(tp, opaque_key,
2700                                        desc_idx, *post_ptr);
2701                 drop_it_no_recycle:
2702                         /* Other statistics kept track of by card. */
2703                         tp->net_stats.rx_dropped++;
2704                         goto next_pkt;
2705                 }
2706
2707                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2708
2709                 if (len > RX_COPY_THRESHOLD) {
2710                         int skb_size;
2711
2712                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2713                                                     desc_idx, *post_ptr);
2714                         if (skb_size < 0)
2715                                 goto drop_it;
2716
2717                         pci_unmap_single(tp->pdev, dma_addr,
2718                                          skb_size - tp->rx_offset,
2719                                          PCI_DMA_FROMDEVICE);
2720
2721                         skb_put(skb, len);
2722                 } else {
2723                         struct sk_buff *copy_skb;
2724
2725                         tg3_recycle_rx(tp, opaque_key,
2726                                        desc_idx, *post_ptr);
2727
2728                         copy_skb = dev_alloc_skb(len + 2);
2729                         if (copy_skb == NULL)
2730                                 goto drop_it_no_recycle;
2731
2732                         copy_skb->dev = tp->dev;
2733                         skb_reserve(copy_skb, 2);
2734                         skb_put(copy_skb, len);
2735                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2736                         memcpy(copy_skb->data, skb->data, len);
2737                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2738
2739                         /* We'll reuse the original ring buffer. */
2740                         skb = copy_skb;
2741                 }
2742
2743                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2744                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2745                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2746                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
2747                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2748                 else
2749                         skb->ip_summed = CHECKSUM_NONE;
2750
2751                 skb->protocol = eth_type_trans(skb, tp->dev);
2752 #if TG3_VLAN_TAG_USED
2753                 if (tp->vlgrp != NULL &&
2754                     desc->type_flags & RXD_FLAG_VLAN) {
2755                         tg3_vlan_rx(tp, skb,
2756                                     desc->err_vlan & RXD_VLAN_MASK);
2757                 } else
2758 #endif
2759                         netif_receive_skb(skb);
2760
2761                 tp->dev->last_rx = jiffies;
2762                 received++;
2763                 budget--;
2764
2765 next_pkt:
2766                 (*post_ptr)++;
2767 next_pkt_nopost:
2768                 rx_rcb_ptr++;
2769                 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2770         }
2771
2772         /* ACK the status ring. */
2773         tp->rx_rcb_ptr = rx_rcb_ptr;
2774         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
2775                      (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
2776
2777         /* Refill RX ring(s). */
2778         if (work_mask & RXD_OPAQUE_RING_STD) {
2779                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2780                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2781                              sw_idx);
2782         }
2783         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2784                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2785                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2786                              sw_idx);
2787         }
2788         mmiowb();
2789
2790         return received;
2791 }
2792
2793 static int tg3_poll(struct net_device *netdev, int *budget)
2794 {
2795         struct tg3 *tp = netdev_priv(netdev);
2796         struct tg3_hw_status *sblk = tp->hw_status;
2797         unsigned long flags;
2798         int done;
2799
2800         spin_lock_irqsave(&tp->lock, flags);
2801
2802         /* handle link change and other phy events */
2803         if (!(tp->tg3_flags &
2804               (TG3_FLAG_USE_LINKCHG_REG |
2805                TG3_FLAG_POLL_SERDES))) {
2806                 if (sblk->status & SD_STATUS_LINK_CHG) {
2807                         sblk->status = SD_STATUS_UPDATED |
2808                                 (sblk->status & ~SD_STATUS_LINK_CHG);
2809                         tg3_setup_phy(tp, 0);
2810                 }
2811         }
2812
2813         /* run TX completion thread */
2814         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2815                 spin_lock(&tp->tx_lock);
2816                 tg3_tx(tp);
2817                 spin_unlock(&tp->tx_lock);
2818         }
2819
2820         spin_unlock_irqrestore(&tp->lock, flags);
2821
2822         /* run RX thread, within the bounds set by NAPI.
2823          * All RX "locking" is done by ensuring outside
2824          * code synchronizes with dev->poll()
2825          */
2826         done = 1;
2827         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2828                 int orig_budget = *budget;
2829                 int work_done;
2830
2831                 if (orig_budget > netdev->quota)
2832                         orig_budget = netdev->quota;
2833
2834                 work_done = tg3_rx(tp, orig_budget);
2835
2836                 *budget -= work_done;
2837                 netdev->quota -= work_done;
2838
2839                 if (work_done >= orig_budget)
2840                         done = 0;
2841         }
2842
2843         /* if no more work, tell net stack and NIC we're done */
2844         if (done) {
2845                 spin_lock_irqsave(&tp->lock, flags);
2846                 __netif_rx_complete(netdev);
2847                 tg3_restart_ints(tp);
2848                 spin_unlock_irqrestore(&tp->lock, flags);
2849         }
2850
2851         return (done ? 0 : 1);
2852 }
2853
2854 static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
2855 {
2856         struct tg3_hw_status *sblk = tp->hw_status;
2857         unsigned int work_exists = 0;
2858
2859         /* check for phy events */
2860         if (!(tp->tg3_flags &
2861               (TG3_FLAG_USE_LINKCHG_REG |
2862                TG3_FLAG_POLL_SERDES))) {
2863                 if (sblk->status & SD_STATUS_LINK_CHG)
2864                         work_exists = 1;
2865         }
2866         /* check for RX/TX work to do */
2867         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
2868             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
2869                 work_exists = 1;
2870
2871         return work_exists;
2872 }
2873
2874 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2875 {
2876         struct net_device *dev = dev_id;
2877         struct tg3 *tp = netdev_priv(dev);
2878         struct tg3_hw_status *sblk = tp->hw_status;
2879         unsigned long flags;
2880         unsigned int handled = 1;
2881
2882         spin_lock_irqsave(&tp->lock, flags);
2883
2884         if (sblk->status & SD_STATUS_UPDATED) {
2885                 /*
2886                  * writing any value to intr-mbox-0 clears PCI INTA# and
2887                  * chip-internal interrupt pending events.
2888                  * writing non-zero to intr-mbox-0 additional tells the
2889                  * NIC to stop sending us irqs, engaging "in-intr-handler"
2890                  * event coalescing.
2891                  */
2892                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2893                              0x00000001);
2894                 /*
2895                  * Flush PCI write.  This also guarantees that our
2896                  * status block has been flushed to host memory.
2897                  */
2898                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2899                 sblk->status &= ~SD_STATUS_UPDATED;
2900
2901                 if (likely(tg3_has_work(dev, tp)))
2902                         netif_rx_schedule(dev);         /* schedule NAPI poll */
2903                 else {
2904                         /* no work, shared interrupt perhaps?  re-enable
2905                          * interrupts, and flush that PCI write
2906                          */
2907                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2908                                 0x00000000);
2909                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2910                 }
2911         } else {        /* shared interrupt */
2912                 handled = 0;
2913         }
2914
2915         spin_unlock_irqrestore(&tp->lock, flags);
2916
2917         return IRQ_RETVAL(handled);
2918 }
2919
2920 static int tg3_init_hw(struct tg3 *);
2921 static int tg3_halt(struct tg3 *);
2922
2923 #ifdef CONFIG_NET_POLL_CONTROLLER
2924 static void tg3_poll_controller(struct net_device *dev)
2925 {
2926         tg3_interrupt(dev->irq, dev, NULL);
2927 }
2928 #endif
2929
2930 static void tg3_reset_task(void *_data)
2931 {
2932         struct tg3 *tp = _data;
2933         unsigned int restart_timer;
2934
2935         tg3_netif_stop(tp);
2936
2937         spin_lock_irq(&tp->lock);
2938         spin_lock(&tp->tx_lock);
2939
2940         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
2941         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
2942
2943         tg3_halt(tp);
2944         tg3_init_hw(tp);
2945
2946         tg3_netif_start(tp);
2947
2948         spin_unlock(&tp->tx_lock);
2949         spin_unlock_irq(&tp->lock);
2950
2951         if (restart_timer)
2952                 mod_timer(&tp->timer, jiffies + 1);
2953 }
2954
2955 static void tg3_tx_timeout(struct net_device *dev)
2956 {
2957         struct tg3 *tp = netdev_priv(dev);
2958
2959         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
2960                dev->name);
2961
2962         schedule_work(&tp->reset_task);
2963 }
2964
2965 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
2966
2967 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
2968                                        u32 guilty_entry, int guilty_len,
2969                                        u32 last_plus_one, u32 *start, u32 mss)
2970 {
2971         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
2972         dma_addr_t new_addr;
2973         u32 entry = *start;
2974         int i;
2975
2976         if (!new_skb) {
2977                 dev_kfree_skb(skb);
2978                 return -1;
2979         }
2980
2981         /* New SKB is guaranteed to be linear. */
2982         entry = *start;
2983         new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
2984                                   PCI_DMA_TODEVICE);
2985         tg3_set_txd(tp, entry, new_addr, new_skb->len,
2986                     (skb->ip_summed == CHECKSUM_HW) ?
2987                     TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
2988         *start = NEXT_TX(entry);
2989
2990         /* Now clean up the sw ring entries. */
2991         i = 0;
2992         while (entry != last_plus_one) {
2993                 int len;
2994
2995                 if (i == 0)
2996                         len = skb_headlen(skb);
2997                 else
2998                         len = skb_shinfo(skb)->frags[i-1].size;
2999                 pci_unmap_single(tp->pdev,
3000                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3001                                  len, PCI_DMA_TODEVICE);
3002                 if (i == 0) {
3003                         tp->tx_buffers[entry].skb = new_skb;
3004                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3005                 } else {
3006                         tp->tx_buffers[entry].skb = NULL;
3007                 }
3008                 entry = NEXT_TX(entry);
3009         }
3010
3011         dev_kfree_skb(skb);
3012
3013         return 0;
3014 }
3015
3016 static void tg3_set_txd(struct tg3 *tp, int entry,
3017                         dma_addr_t mapping, int len, u32 flags,
3018                         u32 mss_and_is_end)
3019 {
3020         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3021         int is_end = (mss_and_is_end & 0x1);
3022         u32 mss = (mss_and_is_end >> 1);
3023         u32 vlan_tag = 0;
3024
3025         if (is_end)
3026                 flags |= TXD_FLAG_END;
3027         if (flags & TXD_FLAG_VLAN) {
3028                 vlan_tag = flags >> 16;
3029                 flags &= 0xffff;
3030         }
3031         vlan_tag |= (mss << TXD_MSS_SHIFT);
3032
3033         txd->addr_hi = ((u64) mapping >> 32);
3034         txd->addr_lo = ((u64) mapping & 0xffffffff);
3035         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3036         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3037 }
3038
3039 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3040 {
3041         u32 base = (u32) mapping & 0xffffffff;
3042
3043         return ((base > 0xffffdcc0) &&
3044                 (base + len + 8 < base));
3045 }
3046
3047 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3048 {
3049         struct tg3 *tp = netdev_priv(dev);
3050         dma_addr_t mapping;
3051         unsigned int i;
3052         u32 len, entry, base_flags, mss;
3053         int would_hit_hwbug;
3054         unsigned long flags;
3055
3056         len = skb_headlen(skb);
3057
3058         /* No BH disabling for tx_lock here.  We are running in BH disabled
3059          * context and TX reclaim runs via tp->poll inside of a software
3060          * interrupt.  Rejoice!
3061          *
3062          * Actually, things are not so simple.  If we are to take a hw
3063          * IRQ here, we can deadlock, consider:
3064          *
3065          *       CPU1           CPU2
3066          *   tg3_start_xmit
3067          *   take tp->tx_lock
3068          *                      tg3_timer
3069          *                      take tp->lock
3070          *   tg3_interrupt
3071          *   spin on tp->lock
3072          *                      spin on tp->tx_lock
3073          *
3074          * So we really do need to disable interrupts when taking
3075          * tx_lock here.
3076          */
3077         local_irq_save(flags);
3078         if (!spin_trylock(&tp->tx_lock)) {
3079                 local_irq_restore(flags);
3080                 return NETDEV_TX_LOCKED;
3081         }
3082
3083         /* This is a hard error, log it. */
3084         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3085                 netif_stop_queue(dev);
3086                 spin_unlock_irqrestore(&tp->tx_lock, flags);
3087                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3088                        dev->name);
3089                 return NETDEV_TX_BUSY;
3090         }
3091
3092         entry = tp->tx_prod;
3093         base_flags = 0;
3094         if (skb->ip_summed == CHECKSUM_HW)
3095                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3096 #if TG3_TSO_SUPPORT != 0
3097         mss = 0;
3098         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3099             (mss = skb_shinfo(skb)->tso_size) != 0) {
3100                 int tcp_opt_len, ip_tcp_len;
3101
3102                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3103                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3104
3105                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3106                                TXD_FLAG_CPU_POST_DMA);
3107
3108                 skb->nh.iph->check = 0;
3109                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3110                 skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr,
3111                                                       skb->nh.iph->daddr,
3112                                                       0, IPPROTO_TCP, 0);
3113
3114                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3115                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3116                                 int tsflags;
3117
3118                                 tsflags = ((skb->nh.iph->ihl - 5) +
3119                                            (tcp_opt_len >> 2));
3120                                 mss |= (tsflags << 11);
3121                         }
3122                 } else {
3123                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3124                                 int tsflags;
3125
3126                                 tsflags = ((skb->nh.iph->ihl - 5) +
3127                                            (tcp_opt_len >> 2));
3128                                 base_flags |= tsflags << 12;
3129                         }
3130                 }
3131         }
3132 #else
3133         mss = 0;
3134 #endif
3135 #if TG3_VLAN_TAG_USED
3136         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3137                 base_flags |= (TXD_FLAG_VLAN |
3138                                (vlan_tx_tag_get(skb) << 16));
3139 #endif
3140
3141         /* Queue skb data, a.k.a. the main skb fragment. */
3142         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3143
3144         tp->tx_buffers[entry].skb = skb;
3145         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3146
3147         would_hit_hwbug = 0;
3148
3149         if (tg3_4g_overflow_test(mapping, len))
3150                 would_hit_hwbug = entry + 1;
3151
3152         tg3_set_txd(tp, entry, mapping, len, base_flags,
3153                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3154
3155         entry = NEXT_TX(entry);
3156
3157         /* Now loop through additional data fragments, and queue them. */
3158         if (skb_shinfo(skb)->nr_frags > 0) {
3159                 unsigned int i, last;
3160
3161                 last = skb_shinfo(skb)->nr_frags - 1;
3162                 for (i = 0; i <= last; i++) {
3163                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3164
3165                         len = frag->size;
3166                         mapping = pci_map_page(tp->pdev,
3167                                                frag->page,
3168                                                frag->page_offset,
3169                                                len, PCI_DMA_TODEVICE);
3170
3171                         tp->tx_buffers[entry].skb = NULL;
3172                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3173
3174                         if (tg3_4g_overflow_test(mapping, len)) {
3175                                 /* Only one should match. */
3176                                 if (would_hit_hwbug)
3177                                         BUG();
3178                                 would_hit_hwbug = entry + 1;
3179                         }
3180
3181                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
3182                                 tg3_set_txd(tp, entry, mapping, len,
3183                                             base_flags, (i == last)|(mss << 1));
3184                         else
3185                                 tg3_set_txd(tp, entry, mapping, len,
3186                                             base_flags, (i == last));
3187
3188                         entry = NEXT_TX(entry);
3189                 }
3190         }
3191
3192         if (would_hit_hwbug) {
3193                 u32 last_plus_one = entry;
3194                 u32 start;
3195                 unsigned int len = 0;
3196
3197                 would_hit_hwbug -= 1;
3198                 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3199                 entry &= (TG3_TX_RING_SIZE - 1);
3200                 start = entry;
3201                 i = 0;
3202                 while (entry != last_plus_one) {
3203                         if (i == 0)
3204                                 len = skb_headlen(skb);
3205                         else
3206                                 len = skb_shinfo(skb)->frags[i-1].size;
3207
3208                         if (entry == would_hit_hwbug)
3209                                 break;
3210
3211                         i++;
3212                         entry = NEXT_TX(entry);
3213
3214                 }
3215
3216                 /* If the workaround fails due to memory/mapping
3217                  * failure, silently drop this packet.
3218                  */
3219                 if (tigon3_4gb_hwbug_workaround(tp, skb,
3220                                                 entry, len,
3221                                                 last_plus_one,
3222                                                 &start, mss))
3223                         goto out_unlock;
3224
3225                 entry = start;
3226         }
3227
3228         /* Packets are ready, update Tx producer idx local and on card. */
3229         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3230
3231         tp->tx_prod = entry;
3232         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3233                 netif_stop_queue(dev);
3234
3235 out_unlock:
3236         mmiowb();
3237         spin_unlock_irqrestore(&tp->tx_lock, flags);
3238
3239         dev->trans_start = jiffies;
3240
3241         return NETDEV_TX_OK;
3242 }
3243
3244 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3245                                int new_mtu)
3246 {
3247         dev->mtu = new_mtu;
3248
3249         if (new_mtu > ETH_DATA_LEN)
3250                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3251         else
3252                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3253 }
3254
3255 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3256 {
3257         struct tg3 *tp = netdev_priv(dev);
3258
3259         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3260                 return -EINVAL;
3261
3262         if (!netif_running(dev)) {
3263                 /* We'll just catch it later when the
3264                  * device is up'd.
3265                  */
3266                 tg3_set_mtu(dev, tp, new_mtu);
3267                 return 0;
3268         }
3269
3270         tg3_netif_stop(tp);
3271         spin_lock_irq(&tp->lock);
3272         spin_lock(&tp->tx_lock);
3273
3274         tg3_halt(tp);
3275
3276         tg3_set_mtu(dev, tp, new_mtu);
3277
3278         tg3_init_hw(tp);
3279
3280         tg3_netif_start(tp);
3281
3282         spin_unlock(&tp->tx_lock);
3283         spin_unlock_irq(&tp->lock);
3284
3285         return 0;
3286 }
3287
3288 /* Free up pending packets in all rx/tx rings.
3289  *
3290  * The chip has been shut down and the driver detached from
3291  * the networking, so no interrupts or new tx packets will
3292  * end up in the driver.  tp->{tx,}lock is not held and we are not
3293  * in an interrupt context and thus may sleep.
3294  */
3295 static void tg3_free_rings(struct tg3 *tp)
3296 {
3297         struct ring_info *rxp;
3298         int i;
3299
3300         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3301                 rxp = &tp->rx_std_buffers[i];
3302
3303                 if (rxp->skb == NULL)
3304                         continue;
3305                 pci_unmap_single(tp->pdev,
3306                                  pci_unmap_addr(rxp, mapping),
3307                                  RX_PKT_BUF_SZ - tp->rx_offset,
3308                                  PCI_DMA_FROMDEVICE);
3309                 dev_kfree_skb_any(rxp->skb);
3310                 rxp->skb = NULL;
3311         }
3312
3313         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3314                 rxp = &tp->rx_jumbo_buffers[i];
3315
3316                 if (rxp->skb == NULL)
3317                         continue;
3318                 pci_unmap_single(tp->pdev,
3319                                  pci_unmap_addr(rxp, mapping),
3320                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3321                                  PCI_DMA_FROMDEVICE);
3322                 dev_kfree_skb_any(rxp->skb);
3323                 rxp->skb = NULL;
3324         }
3325
3326         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3327                 struct tx_ring_info *txp;
3328                 struct sk_buff *skb;
3329                 int j;
3330
3331                 txp = &tp->tx_buffers[i];
3332                 skb = txp->skb;
3333
3334                 if (skb == NULL) {
3335                         i++;
3336                         continue;
3337                 }
3338
3339                 pci_unmap_single(tp->pdev,
3340                                  pci_unmap_addr(txp, mapping),
3341                                  skb_headlen(skb),
3342                                  PCI_DMA_TODEVICE);
3343                 txp->skb = NULL;
3344
3345                 i++;
3346
3347                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3348                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3349                         pci_unmap_page(tp->pdev,
3350                                        pci_unmap_addr(txp, mapping),
3351                                        skb_shinfo(skb)->frags[j].size,
3352                                        PCI_DMA_TODEVICE);
3353                         i++;
3354                 }
3355
3356                 dev_kfree_skb_any(skb);
3357         }
3358 }
3359
3360 /* Initialize tx/rx rings for packet processing.
3361  *
3362  * The chip has been shut down and the driver detached from
3363  * the networking, so no interrupts or new tx packets will
3364  * end up in the driver.  tp->{tx,}lock are held and thus
3365  * we may not sleep.
3366  */
3367 static void tg3_init_rings(struct tg3 *tp)
3368 {
3369         u32 i;
3370
3371         /* Free up all the SKBs. */
3372         tg3_free_rings(tp);
3373
3374         /* Zero out all descriptors. */
3375         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3376         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3377         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3378         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3379
3380         /* Initialize invariants of the rings, we only set this
3381          * stuff once.  This works because the card does not
3382          * write into the rx buffer posting rings.
3383          */
3384         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3385                 struct tg3_rx_buffer_desc *rxd;
3386
3387                 rxd = &tp->rx_std[i];
3388                 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3389                         << RXD_LEN_SHIFT;
3390                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3391                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3392                                (i << RXD_OPAQUE_INDEX_SHIFT));
3393         }
3394
3395         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3396                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3397                         struct tg3_rx_buffer_desc *rxd;
3398
3399                         rxd = &tp->rx_jumbo[i];
3400                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3401                                 << RXD_LEN_SHIFT;
3402                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3403                                 RXD_FLAG_JUMBO;
3404                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3405                                (i << RXD_OPAQUE_INDEX_SHIFT));
3406                 }
3407         }
3408
3409         /* Now allocate fresh SKBs for each rx ring. */
3410         for (i = 0; i < tp->rx_pending; i++) {
3411                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3412                                      -1, i) < 0)
3413                         break;
3414         }
3415
3416         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3417                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3418                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3419                                              -1, i) < 0)
3420                                 break;
3421                 }
3422         }
3423 }
3424
3425 /*
3426  * Must not be invoked with interrupt sources disabled and
3427  * the hardware shutdown down.
3428  */
3429 static void tg3_free_consistent(struct tg3 *tp)
3430 {
3431         if (tp->rx_std_buffers) {
3432                 kfree(tp->rx_std_buffers);
3433                 tp->rx_std_buffers = NULL;
3434         }
3435         if (tp->rx_std) {
3436                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3437                                     tp->rx_std, tp->rx_std_mapping);
3438                 tp->rx_std = NULL;
3439         }
3440         if (tp->rx_jumbo) {
3441                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3442                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3443                 tp->rx_jumbo = NULL;
3444         }
3445         if (tp->rx_rcb) {
3446                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3447                                     tp->rx_rcb, tp->rx_rcb_mapping);
3448                 tp->rx_rcb = NULL;
3449         }
3450         if (tp->tx_ring) {
3451                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3452                         tp->tx_ring, tp->tx_desc_mapping);
3453                 tp->tx_ring = NULL;
3454         }
3455         if (tp->hw_status) {
3456                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3457                                     tp->hw_status, tp->status_mapping);
3458                 tp->hw_status = NULL;
3459         }
3460         if (tp->hw_stats) {
3461                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3462                                     tp->hw_stats, tp->stats_mapping);
3463                 tp->hw_stats = NULL;
3464         }
3465 }
3466
3467 /*
3468  * Must not be invoked with interrupt sources disabled and
3469  * the hardware shutdown down.  Can sleep.
3470  */
3471 static int tg3_alloc_consistent(struct tg3 *tp)
3472 {
3473         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3474                                       (TG3_RX_RING_SIZE +
3475                                        TG3_RX_JUMBO_RING_SIZE)) +
3476                                      (sizeof(struct tx_ring_info) *
3477                                       TG3_TX_RING_SIZE),
3478                                      GFP_KERNEL);
3479         if (!tp->rx_std_buffers)
3480                 return -ENOMEM;
3481
3482         memset(tp->rx_std_buffers, 0,
3483                (sizeof(struct ring_info) *
3484                 (TG3_RX_RING_SIZE +
3485                  TG3_RX_JUMBO_RING_SIZE)) +
3486                (sizeof(struct tx_ring_info) *
3487                 TG3_TX_RING_SIZE));
3488
3489         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3490         tp->tx_buffers = (struct tx_ring_info *)
3491                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3492
3493         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3494                                           &tp->rx_std_mapping);
3495         if (!tp->rx_std)
3496                 goto err_out;
3497
3498         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3499                                             &tp->rx_jumbo_mapping);
3500
3501         if (!tp->rx_jumbo)
3502                 goto err_out;
3503
3504         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3505                                           &tp->rx_rcb_mapping);
3506         if (!tp->rx_rcb)
3507                 goto err_out;
3508
3509         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3510                                            &tp->tx_desc_mapping);
3511         if (!tp->tx_ring)
3512                 goto err_out;
3513
3514         tp->hw_status = pci_alloc_consistent(tp->pdev,
3515                                              TG3_HW_STATUS_SIZE,
3516                                              &tp->status_mapping);
3517         if (!tp->hw_status)
3518                 goto err_out;
3519
3520         tp->hw_stats = pci_alloc_consistent(tp->pdev,
3521                                             sizeof(struct tg3_hw_stats),
3522                                             &tp->stats_mapping);
3523         if (!tp->hw_stats)
3524                 goto err_out;
3525
3526         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3527         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3528
3529         return 0;
3530
3531 err_out:
3532         tg3_free_consistent(tp);
3533         return -ENOMEM;
3534 }
3535
3536 #define MAX_WAIT_CNT 1000
3537
3538 /* To stop a block, clear the enable bit and poll till it
3539  * clears.  tp->lock is held.
3540  */
3541 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
3542 {
3543         unsigned int i;
3544         u32 val;
3545
3546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
3547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
3548                 switch (ofs) {
3549                 case RCVLSC_MODE:
3550                 case DMAC_MODE:
3551                 case MBFREE_MODE:
3552                 case BUFMGR_MODE:
3553                 case MEMARB_MODE:
3554                         /* We can't enable/disable these bits of the
3555                          * 5705/5750, just say success.
3556                          */
3557                         return 0;
3558
3559                 default:
3560                         break;
3561                 };
3562         }
3563
3564         val = tr32(ofs);
3565         val &= ~enable_bit;
3566         tw32_f(ofs, val);
3567
3568         for (i = 0; i < MAX_WAIT_CNT; i++) {
3569                 udelay(100);
3570                 val = tr32(ofs);
3571                 if ((val & enable_bit) == 0)
3572                         break;
3573         }
3574
3575         if (i == MAX_WAIT_CNT) {
3576                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3577                        "ofs=%lx enable_bit=%x\n",
3578                        ofs, enable_bit);
3579                 return -ENODEV;
3580         }
3581
3582         return 0;
3583 }
3584
3585 /* tp->lock is held. */
3586 static int tg3_abort_hw(struct tg3 *tp)
3587 {
3588         int i, err;
3589
3590         tg3_disable_ints(tp);
3591
3592         tp->rx_mode &= ~RX_MODE_ENABLE;
3593         tw32_f(MAC_RX_MODE, tp->rx_mode);
3594         udelay(10);
3595
3596         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
3597         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
3598         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
3599         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
3600         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
3601         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
3602
3603         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
3604         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
3605         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
3606         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
3607         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
3608         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
3609         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
3610         if (err)
3611                 goto out;
3612
3613         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3614         tw32_f(MAC_MODE, tp->mac_mode);
3615         udelay(40);
3616
3617         tp->tx_mode &= ~TX_MODE_ENABLE;
3618         tw32_f(MAC_TX_MODE, tp->tx_mode);
3619
3620         for (i = 0; i < MAX_WAIT_CNT; i++) {
3621                 udelay(100);
3622                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3623                         break;
3624         }
3625         if (i >= MAX_WAIT_CNT) {
3626                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3627                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3628                        tp->dev->name, tr32(MAC_TX_MODE));
3629                 return -ENODEV;
3630         }
3631
3632         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
3633         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
3634         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
3635
3636         tw32(FTQ_RESET, 0xffffffff);
3637         tw32(FTQ_RESET, 0x00000000);
3638
3639         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
3640         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
3641         if (err)
3642                 goto out;
3643
3644         if (tp->hw_status)
3645                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3646         if (tp->hw_stats)
3647                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3648
3649 out:
3650         return err;
3651 }
3652
3653 /* tp->lock is held. */
3654 static int tg3_nvram_lock(struct tg3 *tp)
3655 {
3656         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3657                 int i;
3658
3659                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3660                 for (i = 0; i < 8000; i++) {
3661                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3662                                 break;
3663                         udelay(20);
3664                 }
3665                 if (i == 8000)
3666                         return -ENODEV;
3667         }
3668         return 0;
3669 }
3670
3671 /* tp->lock is held. */
3672 static void tg3_nvram_unlock(struct tg3 *tp)
3673 {
3674         if (tp->tg3_flags & TG3_FLAG_NVRAM)
3675                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3676 }
3677
3678 /* tp->lock is held. */
3679 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3680 {
3681         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3682                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3683
3684         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3685                 switch (kind) {
3686                 case RESET_KIND_INIT:
3687                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3688                                       DRV_STATE_START);
3689                         break;
3690
3691                 case RESET_KIND_SHUTDOWN:
3692                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3693                                       DRV_STATE_UNLOAD);
3694                         break;
3695
3696                 case RESET_KIND_SUSPEND:
3697                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3698                                       DRV_STATE_SUSPEND);
3699                         break;
3700
3701                 default:
3702                         break;
3703                 };
3704         }
3705 }
3706
3707 /* tp->lock is held. */
3708 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3709 {
3710         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3711                 switch (kind) {
3712                 case RESET_KIND_INIT:
3713                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3714                                       DRV_STATE_START_DONE);
3715                         break;
3716
3717                 case RESET_KIND_SHUTDOWN:
3718                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3719                                       DRV_STATE_UNLOAD_DONE);
3720                         break;
3721
3722                 default:
3723                         break;
3724                 };
3725         }
3726 }
3727
3728 /* tp->lock is held. */
3729 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3730 {
3731         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3732                 switch (kind) {
3733                 case RESET_KIND_INIT:
3734                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3735                                       DRV_STATE_START);
3736                         break;
3737
3738                 case RESET_KIND_SHUTDOWN:
3739                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3740                                       DRV_STATE_UNLOAD);
3741                         break;
3742
3743                 case RESET_KIND_SUSPEND:
3744                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3745                                       DRV_STATE_SUSPEND);
3746                         break;
3747
3748                 default:
3749                         break;
3750                 };
3751         }
3752 }
3753
3754 static void tg3_stop_fw(struct tg3 *);
3755
3756 /* tp->lock is held. */
3757 static int tg3_chip_reset(struct tg3 *tp)
3758 {
3759         u32 val;
3760         u32 flags_save;
3761         int i;
3762
3763         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3764                 tg3_nvram_lock(tp);
3765
3766         /*
3767          * We must avoid the readl() that normally takes place.
3768          * It locks machines, causes machine checks, and other
3769          * fun things.  So, temporarily disable the 5701
3770          * hardware workaround, while we do the reset.
3771          */
3772         flags_save = tp->tg3_flags;
3773         tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3774
3775         /* do the reset */
3776         val = GRC_MISC_CFG_CORECLK_RESET;
3777
3778         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3779                 if (tr32(0x7e2c) == 0x60) {
3780                         tw32(0x7e2c, 0x20);
3781                 }
3782                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3783                         tw32(GRC_MISC_CFG, (1 << 29));
3784                         val |= (1 << 29);
3785                 }
3786         }
3787
3788         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
3789             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
3790                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3791         tw32(GRC_MISC_CFG, val);
3792
3793         /* restore 5701 hardware bug workaround flag */
3794         tp->tg3_flags = flags_save;
3795
3796         /* Unfortunately, we have to delay before the PCI read back.
3797          * Some 575X chips even will not respond to a PCI cfg access
3798          * when the reset command is given to the chip.
3799          *
3800          * How do these hardware designers expect things to work
3801          * properly if the PCI write is posted for a long period
3802          * of time?  It is always necessary to have some method by
3803          * which a register read back can occur to push the write
3804          * out which does the reset.
3805          *
3806          * For most tg3 variants the trick below was working.
3807          * Ho hum...
3808          */
3809         udelay(120);
3810
3811         /* Flush PCI posted writes.  The normal MMIO registers
3812          * are inaccessible at this time so this is the only
3813          * way to make this reliably (actually, this is no longer
3814          * the case, see above).  I tried to use indirect
3815          * register read/write but this upset some 5701 variants.
3816          */
3817         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
3818
3819         udelay(120);
3820
3821         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3822                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
3823                         int i;
3824                         u32 cfg_val;
3825
3826                         /* Wait for link training to complete.  */
3827                         for (i = 0; i < 5000; i++)
3828                                 udelay(100);
3829
3830                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
3831                         pci_write_config_dword(tp->pdev, 0xc4,
3832                                                cfg_val | (1 << 15));
3833                 }
3834                 /* Set PCIE max payload size and clear error status.  */
3835                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
3836         }
3837
3838         /* Re-enable indirect register accesses. */
3839         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
3840                                tp->misc_host_ctrl);
3841
3842         /* Set MAX PCI retry to zero. */
3843         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
3844         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
3845             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
3846                 val |= PCISTATE_RETRY_SAME_DMA;
3847         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
3848
3849         pci_restore_state(tp->pdev);
3850
3851         /* Make sure PCI-X relaxed ordering bit is clear. */
3852         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
3853         val &= ~PCIX_CAPS_RELAXED_ORDERING;
3854         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
3855
3856         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
3857
3858         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
3859                 tg3_stop_fw(tp);
3860                 tw32(0x5000, 0x400);
3861         }
3862
3863         tw32(GRC_MODE, tp->grc_mode);
3864
3865         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
3866                 u32 val = tr32(0xc4);
3867
3868                 tw32(0xc4, val | (1 << 15));
3869         }
3870
3871         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
3872             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3873                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
3874                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
3875                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
3876                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
3877         }
3878
3879         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3880                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
3881                 tw32_f(MAC_MODE, tp->mac_mode);
3882         } else
3883                 tw32_f(MAC_MODE, 0);
3884         udelay(40);
3885
3886         /* Wait for firmware initialization to complete. */
3887         for (i = 0; i < 100000; i++) {
3888                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
3889                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3890                         break;
3891                 udelay(10);
3892         }
3893         if (i >= 100000 &&
3894             !(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
3895                 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
3896                        "firmware will not restart magic=%08x\n",
3897                        tp->dev->name, val);
3898                 return -ENODEV;
3899         }
3900
3901         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
3902             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3903                 u32 val = tr32(0x7c00);
3904
3905                 tw32(0x7c00, val | (1 << 25));
3906         }
3907
3908         /* Reprobe ASF enable state.  */
3909         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
3910         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
3911         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
3912         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
3913                 u32 nic_cfg;
3914
3915                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
3916                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
3917                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
3918                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
3919                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
3920                 }
3921         }
3922
3923         return 0;
3924 }
3925
3926 /* tp->lock is held. */
3927 static void tg3_stop_fw(struct tg3 *tp)
3928 {
3929         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3930                 u32 val;
3931                 int i;
3932
3933                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
3934                 val = tr32(GRC_RX_CPU_EVENT);
3935                 val |= (1 << 14);
3936                 tw32(GRC_RX_CPU_EVENT, val);
3937
3938                 /* Wait for RX cpu to ACK the event.  */
3939                 for (i = 0; i < 100; i++) {
3940                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
3941                                 break;
3942                         udelay(1);
3943                 }
3944         }
3945 }
3946
3947 /* tp->lock is held. */
3948 static int tg3_halt(struct tg3 *tp)
3949 {
3950         int err;
3951
3952         tg3_stop_fw(tp);
3953
3954         tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN);
3955
3956         tg3_abort_hw(tp);
3957         err = tg3_chip_reset(tp);
3958
3959         tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN);
3960         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3961
3962         if (err)
3963                 return err;
3964
3965         return 0;
3966 }
3967
3968 #define TG3_FW_RELEASE_MAJOR    0x0
3969 #define TG3_FW_RELASE_MINOR     0x0
3970 #define TG3_FW_RELEASE_FIX      0x0
3971 #define TG3_FW_START_ADDR       0x08000000
3972 #define TG3_FW_TEXT_ADDR        0x08000000
3973 #define TG3_FW_TEXT_LEN         0x9c0
3974 #define TG3_FW_RODATA_ADDR      0x080009c0
3975 #define TG3_FW_RODATA_LEN       0x60
3976 #define TG3_FW_DATA_ADDR        0x08000a40
3977 #define TG3_FW_DATA_LEN         0x20
3978 #define TG3_FW_SBSS_ADDR        0x08000a60
3979 #define TG3_FW_SBSS_LEN         0xc
3980 #define TG3_FW_BSS_ADDR         0x08000a70
3981 #define TG3_FW_BSS_LEN          0x10
3982
3983 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
3984         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
3985         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
3986         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
3987         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
3988         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
3989         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
3990         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
3991         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
3992         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
3993         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
3994         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
3995         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
3996         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
3997         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
3998         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
3999         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4000         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4001         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4002         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4003         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4004         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4005         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4006         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4007         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4008         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4009         0, 0, 0, 0, 0, 0,
4010         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4011         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4012         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4013         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4014         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4015         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4016         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4017         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4018         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4019         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4020         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4021         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4022         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4023         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4024         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4025         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4026         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4027         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4028         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4029         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4030         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4031         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4032         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4033         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4034         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4035         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4036         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4037         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4038         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4039         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4040         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4041         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4042         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4043         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4044         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4045         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4046         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4047         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4048         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4049         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4050         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4051         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4052         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4053         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4054         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4055         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4056         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4057         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4058         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4059         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4060         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4061         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4062         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4063         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4064         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4065         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4066         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4067         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4068         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4069         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4070         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4071         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4072         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4073         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4074         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4075 };
4076
4077 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4078         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4079         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4080         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4081         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4082         0x00000000
4083 };
4084
4085 #if 0 /* All zeros, don't eat up space with it. */
4086 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4087         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4088         0x00000000, 0x00000000, 0x00000000, 0x00000000
4089 };
4090 #endif
4091
4092 #define RX_CPU_SCRATCH_BASE     0x30000
4093 #define RX_CPU_SCRATCH_SIZE     0x04000
4094 #define TX_CPU_SCRATCH_BASE     0x34000
4095 #define TX_CPU_SCRATCH_SIZE     0x04000
4096
4097 /* tp->lock is held. */
4098 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4099 {
4100         int i;
4101
4102         if (offset == TX_CPU_BASE &&
4103             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
4104                 BUG();
4105
4106         if (offset == RX_CPU_BASE) {
4107                 for (i = 0; i < 10000; i++) {
4108                         tw32(offset + CPU_STATE, 0xffffffff);
4109                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4110                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4111                                 break;
4112                 }
4113
4114                 tw32(offset + CPU_STATE, 0xffffffff);
4115                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4116                 udelay(10);
4117         } else {
4118                 for (i = 0; i < 10000; i++) {
4119                         tw32(offset + CPU_STATE, 0xffffffff);
4120                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4121                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4122                                 break;
4123                 }
4124         }
4125
4126         if (i >= 10000) {
4127                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4128                        "and %s CPU\n",
4129                        tp->dev->name,
4130                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4131                 return -ENODEV;
4132         }
4133         return 0;
4134 }
4135
4136 struct fw_info {
4137         unsigned int text_base;
4138         unsigned int text_len;
4139         u32 *text_data;
4140         unsigned int rodata_base;
4141         unsigned int rodata_len;
4142         u32 *rodata_data;
4143         unsigned int data_base;
4144         unsigned int data_len;
4145         u32 *data_data;
4146 };
4147
4148 /* tp->lock is held. */
4149 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4150                                  int cpu_scratch_size, struct fw_info *info)
4151 {
4152         int err, i;
4153         u32 orig_tg3_flags = tp->tg3_flags;
4154         void (*write_op)(struct tg3 *, u32, u32);
4155
4156         if (cpu_base == TX_CPU_BASE &&
4157             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4158                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4159                        "TX cpu firmware on %s which is 5705.\n",
4160                        tp->dev->name);
4161                 return -EINVAL;
4162         }
4163
4164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
4165                 write_op = tg3_write_mem;
4166         else
4167                 write_op = tg3_write_indirect_reg32;
4168
4169         /* Force use of PCI config space for indirect register
4170          * write calls.
4171          */
4172         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4173
4174         err = tg3_halt_cpu(tp, cpu_base);
4175         if (err)
4176                 goto out;
4177
4178         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4179                 write_op(tp, cpu_scratch_base + i, 0);
4180         tw32(cpu_base + CPU_STATE, 0xffffffff);
4181         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4182         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4183                 write_op(tp, (cpu_scratch_base +
4184                               (info->text_base & 0xffff) +
4185                               (i * sizeof(u32))),
4186                          (info->text_data ?
4187                           info->text_data[i] : 0));
4188         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4189                 write_op(tp, (cpu_scratch_base +
4190                               (info->rodata_base & 0xffff) +
4191                               (i * sizeof(u32))),
4192                          (info->rodata_data ?
4193                           info->rodata_data[i] : 0));
4194         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4195                 write_op(tp, (cpu_scratch_base +
4196                               (info->data_base & 0xffff) +
4197                               (i * sizeof(u32))),
4198                          (info->data_data ?
4199                           info->data_data[i] : 0));
4200
4201         err = 0;
4202
4203 out:
4204         tp->tg3_flags = orig_tg3_flags;
4205         return err;
4206 }
4207
4208 /* tp->lock is held. */
4209 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4210 {
4211         struct fw_info info;
4212         int err, i;
4213
4214         info.text_base = TG3_FW_TEXT_ADDR;
4215         info.text_len = TG3_FW_TEXT_LEN;
4216         info.text_data = &tg3FwText[0];
4217         info.rodata_base = TG3_FW_RODATA_ADDR;
4218         info.rodata_len = TG3_FW_RODATA_LEN;
4219         info.rodata_data = &tg3FwRodata[0];
4220         info.data_base = TG3_FW_DATA_ADDR;
4221         info.data_len = TG3_FW_DATA_LEN;
4222         info.data_data = NULL;
4223
4224         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4225                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4226                                     &info);
4227         if (err)
4228                 return err;
4229
4230         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4231                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4232                                     &info);
4233         if (err)
4234                 return err;
4235
4236         /* Now startup only the RX cpu. */
4237         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4238         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4239
4240         for (i = 0; i < 5; i++) {
4241                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4242                         break;
4243                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4244                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4245                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4246                 udelay(1000);
4247         }
4248         if (i >= 5) {
4249                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4250                        "to set RX CPU PC, is %08x should be %08x\n",
4251                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4252                        TG3_FW_TEXT_ADDR);
4253                 return -ENODEV;
4254         }
4255         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4256         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4257
4258         return 0;
4259 }
4260
4261 #if TG3_TSO_SUPPORT != 0
4262
4263 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4264 #define TG3_TSO_FW_RELASE_MINOR         0x6
4265 #define TG3_TSO_FW_RELEASE_FIX          0x0
4266 #define TG3_TSO_FW_START_ADDR           0x08000000
4267 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4268 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4269 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4270 #define TG3_TSO_FW_RODATA_LEN           0x60
4271 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4272 #define TG3_TSO_FW_DATA_LEN             0x30
4273 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4274 #define TG3_TSO_FW_SBSS_LEN             0x2c
4275 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4276 #define TG3_TSO_FW_BSS_LEN              0x894
4277
4278 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4279         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4280         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4281         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4282         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4283         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4284         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4285         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4286         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4287         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4288         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4289         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4290         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4291         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4292         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4293         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4294         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4295         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4296         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4297         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4298         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4299         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4300         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4301         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4302         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4303         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4304         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4305         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4306         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4307         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4308         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4309         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4310         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4311         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4312         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4313         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4314         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4315         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4316         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4317         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4318         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4319         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4320         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4321         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4322         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4323         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4324         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4325         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4326         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4327         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4328         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4329         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4330         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4331         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4332         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4333         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4334         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4335         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4336         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4337         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4338         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4339         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4340         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4341         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4342         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4343         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4344         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4345         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4346         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4347         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4348         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4349         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4350         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4351         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4352         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4353         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4354         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4355         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4356         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4357         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4358         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4359         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4360         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4361         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4362         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4363         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4364         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4365         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4366         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4367         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4368         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4369         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4370         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4371         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4372         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4373         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4374         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4375         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4376         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4377         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4378         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4379         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4380         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4381         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4382         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4383         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4384         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4385         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4386         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4387         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4388         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4389         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4390         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4391         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4392         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4393         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4394         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4395         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4396         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4397         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4398         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4399         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4400         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4401         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4402         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4403         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4404         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4405         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4406         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4407         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4408         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4409         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4410         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4411         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4412         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4413         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4414         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4415         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4416         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4417         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4418         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4419         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4420         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4421         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4422         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4423         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4424         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4425         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4426         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4427         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4428         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4429         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4430         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4431         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4432         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4433         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4434         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4435         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4436         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4437         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4438         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4439         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4440         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4441         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4442         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4443         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4444         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4445         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4446         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4447         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4448         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4449         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4450         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4451         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4452         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4453         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4454         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4455         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4456         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4457         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4458         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4459         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4460         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4461         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4462         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4463         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4464         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4465         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4466         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4467         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4468         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4469         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4470         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4471         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4472         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4473         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4474         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4475         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4476         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4477         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4478         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4479         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4480         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4481         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4482         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4483         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4484         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4485         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4486         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4487         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4488         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4489         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4490         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4491         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4492         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4493         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4494         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4495         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4496         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4497         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4498         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4499         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4500         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4501         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4502         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4503         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4504         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4505         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4506         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4507         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4508         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4509         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4510         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4511         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4512         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4513         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4514         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4515         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4516         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4517         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4518         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4519         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4520         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4521         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4522         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4523         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4524         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4525         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4526         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4527         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4528         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4529         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4530         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4531         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4532         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4533         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4534         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4535         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4536         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4537         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4538         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4539         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4540         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4541         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4542         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4543         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4544         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4545         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4546         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4547         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4548         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4549         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4550         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4551         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4552         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4553         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4554         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4555         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4556         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4557         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4558         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4559         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4560         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4561         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4562         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4563 };
4564
4565 static u32 tg3TsoFwRodata[] = {
4566         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4567         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4568         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4569         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4570         0x00000000,
4571 };
4572
4573 static u32 tg3TsoFwData[] = {
4574         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4575         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4576         0x00000000,
4577 };
4578
4579 /* 5705 needs a special version of the TSO firmware.  */
4580 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
4581 #define TG3_TSO5_FW_RELASE_MINOR        0x2
4582 #define TG3_TSO5_FW_RELEASE_FIX         0x0
4583 #define TG3_TSO5_FW_START_ADDR          0x00010000
4584 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
4585 #define TG3_TSO5_FW_TEXT_LEN            0xe90
4586 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
4587 #define TG3_TSO5_FW_RODATA_LEN          0x50
4588 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
4589 #define TG3_TSO5_FW_DATA_LEN            0x20
4590 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
4591 #define TG3_TSO5_FW_SBSS_LEN            0x28
4592 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
4593 #define TG3_TSO5_FW_BSS_LEN             0x88
4594
4595 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4596         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4597         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4598         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4599         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4600         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4601         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4602         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4603         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4604         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4605         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4606         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4607         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4608         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4609         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4610         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4611         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4612         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4613         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4614         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4615         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4616         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4617         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4618         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4619         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4620         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4621         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4622         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4623         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4624         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4625         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4626         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4627         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4628         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4629         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4630         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4631         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4632         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4633         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4634         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4635         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4636         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4637         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4638         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4639         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4640         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4641         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4642         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4643         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4644         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4645         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4646         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4647         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4648         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4649         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4650         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4651         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4652         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4653         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4654         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4655         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4656         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4657         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4658         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4659         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4660         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4661         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4662         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4663         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4664         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4665         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4666         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4667         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4668         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4669         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4670         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4671         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4672         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4673         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4674         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4675         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4676         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4677         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4678         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4679         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4680         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4681         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4682         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4683         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4684         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4685         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4686         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4687         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4688         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4689         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4690         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4691         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4692         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4693         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4694         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4695         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4696         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4697         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4698         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4699         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4700         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4701         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4702         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4703         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4704         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4705         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4706         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4707         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4708         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4709         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4710         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4711         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4712         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4713         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4714         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4715         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4716         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4717         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4718         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4719         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4720         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4721         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4722         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4723         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4724         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4725         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4726         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4727         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4728         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4729         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4730         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4731         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4732         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4733         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4734         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4735         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4736         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4737         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4738         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4739         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4740         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4741         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4742         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4743         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4744         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4745         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4746         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4747         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4748         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4749         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4750         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4751         0x00000000, 0x00000000, 0x00000000,
4752 };
4753
4754 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4755         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4756         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4757         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4758         0x00000000, 0x00000000, 0x00000000,
4759 };
4760
4761 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4762         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4763         0x00000000, 0x00000000, 0x00000000,
4764 };
4765
4766 /* tp->lock is held. */
4767 static int tg3_load_tso_firmware(struct tg3 *tp)
4768 {
4769         struct fw_info info;
4770         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4771         int err, i;
4772
4773         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
4774                 return 0;
4775
4776         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4777                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4778                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4779                 info.text_data = &tg3Tso5FwText[0];
4780                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4781                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4782                 info.rodata_data = &tg3Tso5FwRodata[0];
4783                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4784                 info.data_len = TG3_TSO5_FW_DATA_LEN;
4785                 info.data_data = &tg3Tso5FwData[0];
4786                 cpu_base = RX_CPU_BASE;
4787                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4788                 cpu_scratch_size = (info.text_len +
4789                                     info.rodata_len +
4790                                     info.data_len +
4791                                     TG3_TSO5_FW_SBSS_LEN +
4792                                     TG3_TSO5_FW_BSS_LEN);
4793         } else {
4794                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4795                 info.text_len = TG3_TSO_FW_TEXT_LEN;
4796                 info.text_data = &tg3TsoFwText[0];
4797                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
4798                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
4799                 info.rodata_data = &tg3TsoFwRodata[0];
4800                 info.data_base = TG3_TSO_FW_DATA_ADDR;
4801                 info.data_len = TG3_TSO_FW_DATA_LEN;
4802                 info.data_data = &tg3TsoFwData[0];
4803                 cpu_base = TX_CPU_BASE;
4804                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
4805                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
4806         }
4807
4808         err = tg3_load_firmware_cpu(tp, cpu_base,
4809                                     cpu_scratch_base, cpu_scratch_size,
4810                                     &info);
4811         if (err)
4812                 return err;
4813
4814         /* Now startup the cpu. */
4815         tw32(cpu_base + CPU_STATE, 0xffffffff);
4816         tw32_f(cpu_base + CPU_PC,    info.text_base);
4817
4818         for (i = 0; i < 5; i++) {
4819                 if (tr32(cpu_base + CPU_PC) == info.text_base)
4820                         break;
4821                 tw32(cpu_base + CPU_STATE, 0xffffffff);
4822                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
4823                 tw32_f(cpu_base + CPU_PC,    info.text_base);
4824                 udelay(1000);
4825         }
4826         if (i >= 5) {
4827                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
4828                        "to set CPU PC, is %08x should be %08x\n",
4829                        tp->dev->name, tr32(cpu_base + CPU_PC),
4830                        info.text_base);
4831                 return -ENODEV;
4832         }
4833         tw32(cpu_base + CPU_STATE, 0xffffffff);
4834         tw32_f(cpu_base + CPU_MODE,  0x00000000);
4835         return 0;
4836 }
4837
4838 #endif /* TG3_TSO_SUPPORT != 0 */
4839
4840 /* tp->lock is held. */
4841 static void __tg3_set_mac_addr(struct tg3 *tp)
4842 {
4843         u32 addr_high, addr_low;
4844         int i;
4845
4846         addr_high = ((tp->dev->dev_addr[0] << 8) |
4847                      tp->dev->dev_addr[1]);
4848         addr_low = ((tp->dev->dev_addr[2] << 24) |
4849                     (tp->dev->dev_addr[3] << 16) |
4850                     (tp->dev->dev_addr[4] <<  8) |
4851                     (tp->dev->dev_addr[5] <<  0));
4852         for (i = 0; i < 4; i++) {
4853                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
4854                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
4855         }
4856
4857         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
4858             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
4859             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
4860                 for (i = 0; i < 12; i++) {
4861                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
4862                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
4863                 }
4864         }
4865
4866         addr_high = (tp->dev->dev_addr[0] +
4867                      tp->dev->dev_addr[1] +
4868                      tp->dev->dev_addr[2] +
4869                      tp->dev->dev_addr[3] +
4870                      tp->dev->dev_addr[4] +
4871                      tp->dev->dev_addr[5]) &
4872                 TX_BACKOFF_SEED_MASK;
4873         tw32(MAC_TX_BACKOFF_SEED, addr_high);
4874 }
4875
4876 static int tg3_set_mac_addr(struct net_device *dev, void *p)
4877 {
4878         struct tg3 *tp = netdev_priv(dev);
4879         struct sockaddr *addr = p;
4880
4881         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4882
4883         spin_lock_irq(&tp->lock);
4884         __tg3_set_mac_addr(tp);
4885         spin_unlock_irq(&tp->lock);
4886
4887         return 0;
4888 }
4889
4890 /* tp->lock is held. */
4891 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
4892                            dma_addr_t mapping, u32 maxlen_flags,
4893                            u32 nic_addr)
4894 {
4895         tg3_write_mem(tp,
4896                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
4897                       ((u64) mapping >> 32));
4898         tg3_write_mem(tp,
4899                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
4900                       ((u64) mapping & 0xffffffff));
4901         tg3_write_mem(tp,
4902                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
4903                        maxlen_flags);
4904
4905         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)
4906                 tg3_write_mem(tp,
4907                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
4908                               nic_addr);
4909 }
4910
4911 static void __tg3_set_rx_mode(struct net_device *);
4912
4913 /* tp->lock is held. */
4914 static int tg3_reset_hw(struct tg3 *tp)
4915 {
4916         u32 val, rdmac_mode;
4917         int i, err, limit;
4918
4919         tg3_disable_ints(tp);
4920
4921         tg3_stop_fw(tp);
4922
4923         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
4924
4925         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
4926                 err = tg3_abort_hw(tp);
4927                 if (err)
4928                         return err;
4929         }
4930
4931         err = tg3_chip_reset(tp);
4932         if (err)
4933                 return err;
4934
4935         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
4936
4937         /* This works around an issue with Athlon chipsets on
4938          * B3 tigon3 silicon.  This bit has no effect on any
4939          * other revision.  But do not set this on PCI Express
4940          * chips.
4941          */
4942         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
4943                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
4944         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4945
4946         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4947             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
4948                 val = tr32(TG3PCI_PCISTATE);
4949                 val |= PCISTATE_RETRY_SAME_DMA;
4950                 tw32(TG3PCI_PCISTATE, val);
4951         }
4952
4953         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
4954                 /* Enable some hw fixes.  */
4955                 val = tr32(TG3PCI_MSI_DATA);
4956                 val |= (1 << 26) | (1 << 28) | (1 << 29);
4957                 tw32(TG3PCI_MSI_DATA, val);
4958         }
4959
4960         /* Descriptor ring init may make accesses to the
4961          * NIC SRAM area to setup the TX descriptors, so we
4962          * can only do this after the hardware has been
4963          * successfully reset.
4964          */
4965         tg3_init_rings(tp);
4966
4967         /* This value is determined during the probe time DMA
4968          * engine test, tg3_test_dma.
4969          */
4970         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
4971
4972         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
4973                           GRC_MODE_4X_NIC_SEND_RINGS |
4974                           GRC_MODE_NO_TX_PHDR_CSUM |
4975                           GRC_MODE_NO_RX_PHDR_CSUM);
4976         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
4977         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
4978                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
4979         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
4980                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
4981
4982         tw32(GRC_MODE,
4983              tp->grc_mode |
4984              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
4985
4986         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
4987         val = tr32(GRC_MISC_CFG);
4988         val &= ~0xff;
4989         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
4990         tw32(GRC_MISC_CFG, val);
4991
4992         /* Initialize MBUF/DESC pool. */
4993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
4994                 /* Do nothing.  */
4995         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
4996                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4997                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
4998                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
4999                 else
5000                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5001                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5002                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5003         }
5004 #if TG3_TSO_SUPPORT != 0
5005         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5006                 int fw_len;
5007
5008                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5009                           TG3_TSO5_FW_RODATA_LEN +
5010                           TG3_TSO5_FW_DATA_LEN +
5011                           TG3_TSO5_FW_SBSS_LEN +
5012                           TG3_TSO5_FW_BSS_LEN);
5013                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5014                 tw32(BUFMGR_MB_POOL_ADDR,
5015                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5016                 tw32(BUFMGR_MB_POOL_SIZE,
5017                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5018         }
5019 #endif
5020
5021         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5022                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5023                      tp->bufmgr_config.mbuf_read_dma_low_water);
5024                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5025                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5026                 tw32(BUFMGR_MB_HIGH_WATER,
5027                      tp->bufmgr_config.mbuf_high_water);
5028         } else {
5029                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5030                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5031                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5032                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5033                 tw32(BUFMGR_MB_HIGH_WATER,
5034                      tp->bufmgr_config.mbuf_high_water_jumbo);
5035         }
5036         tw32(BUFMGR_DMA_LOW_WATER,
5037              tp->bufmgr_config.dma_low_water);
5038         tw32(BUFMGR_DMA_HIGH_WATER,
5039              tp->bufmgr_config.dma_high_water);
5040
5041         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5042         for (i = 0; i < 2000; i++) {
5043                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5044                         break;
5045                 udelay(10);
5046         }
5047         if (i >= 2000) {
5048                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5049                        tp->dev->name);
5050                 return -ENODEV;
5051         }
5052
5053         /* Setup replenish threshold. */
5054         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5055
5056         /* Initialize TG3_BDINFO's at:
5057          *  RCVDBDI_STD_BD:     standard eth size rx ring
5058          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5059          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5060          *
5061          * like so:
5062          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5063          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5064          *                              ring attribute flags
5065          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5066          *
5067          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5068          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5069          *
5070          * The size of each ring is fixed in the firmware, but the location is
5071          * configurable.
5072          */
5073         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5074              ((u64) tp->rx_std_mapping >> 32));
5075         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5076              ((u64) tp->rx_std_mapping & 0xffffffff));
5077         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5078              NIC_SRAM_RX_BUFFER_DESC);
5079
5080         /* Don't even try to program the JUMBO/MINI buffer descriptor
5081          * configs on 5705.
5082          */
5083         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
5084             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5085                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5086                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5087         } else {
5088                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5089                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5090
5091                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5092                      BDINFO_FLAGS_DISABLED);
5093
5094                 /* Setup replenish threshold. */
5095                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5096
5097                 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5098                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5099                              ((u64) tp->rx_jumbo_mapping >> 32));
5100                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5101                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5102                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5103                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5104                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5105                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5106                 } else {
5107                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5108                              BDINFO_FLAGS_DISABLED);
5109                 }
5110
5111         }
5112
5113         /* There is only one send ring on 5705/5750, no need to explicitly
5114          * disable the others.
5115          */
5116         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5117             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
5118                 /* Clear out send RCB ring in SRAM. */
5119                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5120                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5121                                       BDINFO_FLAGS_DISABLED);
5122         }
5123
5124         tp->tx_prod = 0;
5125         tp->tx_cons = 0;
5126         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5127         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5128
5129         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5130                        tp->tx_desc_mapping,
5131                        (TG3_TX_RING_SIZE <<
5132                         BDINFO_FLAGS_MAXLEN_SHIFT),
5133                        NIC_SRAM_TX_BUFFER_DESC);
5134
5135         /* There is only one receive return ring on 5705/5750, no need
5136          * to explicitly disable the others.
5137          */
5138         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5139             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
5140                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5141                      i += TG3_BDINFO_SIZE) {
5142                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5143                                       BDINFO_FLAGS_DISABLED);
5144                 }
5145         }
5146
5147         tp->rx_rcb_ptr = 0;
5148         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5149
5150         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5151                        tp->rx_rcb_mapping,
5152                        (TG3_RX_RCB_RING_SIZE(tp) <<
5153                         BDINFO_FLAGS_MAXLEN_SHIFT),
5154                        0);
5155
5156         tp->rx_std_ptr = tp->rx_pending;
5157         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5158                      tp->rx_std_ptr);
5159
5160         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5161                                                 tp->rx_jumbo_pending : 0;
5162         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5163                      tp->rx_jumbo_ptr);
5164
5165         /* Initialize MAC address and backoff seed. */
5166         __tg3_set_mac_addr(tp);
5167
5168         /* MTU + ethernet header + FCS + optional VLAN tag */
5169         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5170
5171         /* The slot time is changed by tg3_setup_phy if we
5172          * run at gigabit with half duplex.
5173          */
5174         tw32(MAC_TX_LENGTHS,
5175              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5176              (6 << TX_LENGTHS_IPG_SHIFT) |
5177              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5178
5179         /* Receive rules. */
5180         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5181         tw32(RCVLPC_CONFIG, 0x0181);
5182
5183         /* Calculate RDMAC_MODE setting early, we need it to determine
5184          * the RCVLPC_STATE_ENABLE mask.
5185          */
5186         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5187                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5188                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5189                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5190                       RDMAC_MODE_LNGREAD_ENAB);
5191         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5192                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5193         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5194              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5195             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5196                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5197                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5198                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5199                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5200                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5201                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5202                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5203                 }
5204         }
5205
5206 #if TG3_TSO_SUPPORT != 0
5207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
5208                 rdmac_mode |= (1 << 27);
5209 #endif
5210
5211         /* Receive/send statistics. */
5212         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5213             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5214                 val = tr32(RCVLPC_STATS_ENABLE);
5215                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5216                 tw32(RCVLPC_STATS_ENABLE, val);
5217         } else {
5218                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5219         }
5220         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5221         tw32(SNDDATAI_STATSENAB, 0xffffff);
5222         tw32(SNDDATAI_STATSCTRL,
5223              (SNDDATAI_SCTRL_ENABLE |
5224               SNDDATAI_SCTRL_FASTUPD));
5225
5226         /* Setup host coalescing engine. */
5227         tw32(HOSTCC_MODE, 0);
5228         for (i = 0; i < 2000; i++) {
5229                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5230                         break;
5231                 udelay(10);
5232         }
5233
5234         tw32(HOSTCC_RXCOL_TICKS, 0);
5235         tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
5236         tw32(HOSTCC_RXMAX_FRAMES, 1);
5237         tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
5238         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5239             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
5240                 tw32(HOSTCC_RXCOAL_TICK_INT, 0);
5241                 tw32(HOSTCC_TXCOAL_TICK_INT, 0);
5242         }
5243         tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
5244         tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
5245
5246         /* set status block DMA address */
5247         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5248              ((u64) tp->status_mapping >> 32));
5249         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5250              ((u64) tp->status_mapping & 0xffffffff));
5251
5252         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5253             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
5254                 /* Status/statistics block address.  See tg3_timer,
5255                  * the tg3_periodic_fetch_stats call there, and
5256                  * tg3_get_stats to see how this works for 5705/5750 chips.
5257                  */
5258                 tw32(HOSTCC_STAT_COAL_TICKS,
5259                      DEFAULT_STAT_COAL_TICKS);
5260                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5261                      ((u64) tp->stats_mapping >> 32));
5262                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5263                      ((u64) tp->stats_mapping & 0xffffffff));
5264                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5265                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5266         }
5267
5268         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5269
5270         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5271         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5272         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5273             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
5274                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5275
5276         /* Clear statistics/status block in chip, and status block in ram. */
5277         for (i = NIC_SRAM_STATS_BLK;
5278              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5279              i += sizeof(u32)) {
5280                 tg3_write_mem(tp, i, 0);
5281                 udelay(40);
5282         }
5283         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5284
5285         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5286                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5287         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5288         udelay(40);
5289
5290         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
5291         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
5292                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5293                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5294         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5295         udelay(100);
5296
5297         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5298         tr32(MAILBOX_INTERRUPT_0);
5299
5300         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5301             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
5302                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5303                 udelay(40);
5304         }
5305
5306         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5307                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5308                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5309                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5310                WDMAC_MODE_LNGREAD_ENAB);
5311
5312         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5313              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5314             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5315                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5316                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5317                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5318                         /* nothing */
5319                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5320                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5321                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5322                         val |= WDMAC_MODE_RX_ACCEL;
5323                 }
5324         }
5325
5326         tw32_f(WDMAC_MODE, val);
5327         udelay(40);
5328
5329         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5330                 val = tr32(TG3PCI_X_CAPS);
5331                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5332                         val &= ~PCIX_CAPS_BURST_MASK;
5333                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5334                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5335                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5336                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5337                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5338                                 val |= (tp->split_mode_max_reqs <<
5339                                         PCIX_CAPS_SPLIT_SHIFT);
5340                 }
5341                 tw32(TG3PCI_X_CAPS, val);
5342         }
5343
5344         tw32_f(RDMAC_MODE, rdmac_mode);
5345         udelay(40);
5346
5347         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5348         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
5349             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
5350                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5351         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5352         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5353         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5354         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5355         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5356 #if TG3_TSO_SUPPORT != 0
5357         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
5358                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5359 #endif
5360         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5361         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5362
5363         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5364                 err = tg3_load_5701_a0_firmware_fix(tp);
5365                 if (err)
5366                         return err;
5367         }
5368
5369 #if TG3_TSO_SUPPORT != 0
5370         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5371                 err = tg3_load_tso_firmware(tp);
5372                 if (err)
5373                         return err;
5374         }
5375 #endif
5376
5377         tp->tx_mode = TX_MODE_ENABLE;
5378         tw32_f(MAC_TX_MODE, tp->tx_mode);
5379         udelay(100);
5380
5381         tp->rx_mode = RX_MODE_ENABLE;
5382         tw32_f(MAC_RX_MODE, tp->rx_mode);
5383         udelay(10);
5384
5385         if (tp->link_config.phy_is_low_power) {
5386                 tp->link_config.phy_is_low_power = 0;
5387                 tp->link_config.speed = tp->link_config.orig_speed;
5388                 tp->link_config.duplex = tp->link_config.orig_duplex;
5389                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5390         }
5391
5392         tp->mi_mode = MAC_MI_MODE_BASE;
5393         tw32_f(MAC_MI_MODE, tp->mi_mode);
5394         udelay(80);
5395
5396         tw32(MAC_LED_CTRL, tp->led_ctrl);
5397
5398         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5399         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5400                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5401                 udelay(10);
5402         }
5403         tw32_f(MAC_RX_MODE, tp->rx_mode);
5404         udelay(10);
5405
5406         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5407                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5408                         /* Set drive transmission level to 1.2V  */
5409                         val = tr32(MAC_SERDES_CFG);
5410                         val &= 0xfffff000;
5411                         val |= 0x880;
5412                         tw32(MAC_SERDES_CFG, val);
5413                 }
5414                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5415                         tw32(MAC_SERDES_CFG, 0x616000);
5416         }
5417
5418         /* Prevent chip from dropping frames when flow control
5419          * is enabled.
5420          */
5421         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5422
5423         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5424             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5425                 /* Use hardware link auto-negotiation */
5426                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5427         }
5428
5429         err = tg3_setup_phy(tp, 1);
5430         if (err)
5431                 return err;
5432
5433         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5434                 u32 tmp;
5435
5436                 /* Clear CRC stats. */
5437                 tg3_readphy(tp, 0x1e, &tmp);
5438                 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5439                 tg3_readphy(tp, 0x14, &tmp);
5440         }
5441
5442         __tg3_set_rx_mode(tp->dev);
5443
5444         /* Initialize receive rules. */
5445         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
5446         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5447         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
5448         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5449
5450         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
5451             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
5452                 limit = 8;
5453         else
5454                 limit = 16;
5455         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5456                 limit -= 4;
5457         switch (limit) {
5458         case 16:
5459                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
5460         case 15:
5461                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
5462         case 14:
5463                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
5464         case 13:
5465                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
5466         case 12:
5467                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
5468         case 11:
5469                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
5470         case 10:
5471                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
5472         case 9:
5473                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
5474         case 8:
5475                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
5476         case 7:
5477                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
5478         case 6:
5479                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
5480         case 5:
5481                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
5482         case 4:
5483                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
5484         case 3:
5485                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
5486         case 2:
5487         case 1:
5488
5489         default:
5490                 break;
5491         };
5492
5493         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5494
5495         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5496                 tg3_enable_ints(tp);
5497
5498         return 0;
5499 }
5500
5501 /* Called at device open time to get the chip ready for
5502  * packet processing.  Invoked with tp->lock held.
5503  */
5504 static int tg3_init_hw(struct tg3 *tp)
5505 {
5506         int err;
5507
5508         /* Force the chip into D0. */
5509         err = tg3_set_power_state(tp, 0);
5510         if (err)
5511                 goto out;
5512
5513         tg3_switch_clocks(tp);
5514
5515         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5516
5517         err = tg3_reset_hw(tp);
5518
5519 out:
5520         return err;
5521 }
5522
5523 #define TG3_STAT_ADD32(PSTAT, REG) \
5524 do {    u32 __val = tr32(REG); \
5525         (PSTAT)->low += __val; \
5526         if ((PSTAT)->low < __val) \
5527                 (PSTAT)->high += 1; \
5528 } while (0)
5529
5530 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5531 {
5532         struct tg3_hw_stats *sp = tp->hw_stats;
5533
5534         if (!netif_carrier_ok(tp->dev))
5535                 return;
5536
5537         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5538         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5539         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5540         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5541         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5542         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5543         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5544         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5545         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5546         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5547         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5548         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5549         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5550
5551         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5552         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5553         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5554         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5555         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5556         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5557         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5558         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5559         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5560         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5561         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5562         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5563         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5564         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5565 }
5566
5567 static void tg3_timer(unsigned long __opaque)
5568 {
5569         struct tg3 *tp = (struct tg3 *) __opaque;
5570         unsigned long flags;
5571
5572         spin_lock_irqsave(&tp->lock, flags);
5573         spin_lock(&tp->tx_lock);
5574
5575         /* All of this garbage is because when using non-tagged
5576          * IRQ status the mailbox/status_block protocol the chip
5577          * uses with the cpu is race prone.
5578          */
5579         if (tp->hw_status->status & SD_STATUS_UPDATED) {
5580                 tw32(GRC_LOCAL_CTRL,
5581                      tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5582         } else {
5583                 tw32(HOSTCC_MODE, tp->coalesce_mode |
5584                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5585         }
5586
5587         if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5588                 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5589                 spin_unlock(&tp->tx_lock);
5590                 spin_unlock_irqrestore(&tp->lock, flags);
5591                 schedule_work(&tp->reset_task);
5592                 return;
5593         }
5594
5595         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
5596             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
5597                 tg3_periodic_fetch_stats(tp);
5598
5599         /* This part only runs once per second. */
5600         if (!--tp->timer_counter) {
5601                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5602                         u32 mac_stat;
5603                         int phy_event;
5604
5605                         mac_stat = tr32(MAC_STATUS);
5606
5607                         phy_event = 0;
5608                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5609                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5610                                         phy_event = 1;
5611                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5612                                 phy_event = 1;
5613
5614                         if (phy_event)
5615                                 tg3_setup_phy(tp, 0);
5616                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5617                         u32 mac_stat = tr32(MAC_STATUS);
5618                         int need_setup = 0;
5619
5620                         if (netif_carrier_ok(tp->dev) &&
5621                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5622                                 need_setup = 1;
5623                         }
5624                         if (! netif_carrier_ok(tp->dev) &&
5625                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
5626                                          MAC_STATUS_SIGNAL_DET))) {
5627                                 need_setup = 1;
5628                         }
5629                         if (need_setup) {
5630                                 tw32_f(MAC_MODE,
5631                                      (tp->mac_mode &
5632                                       ~MAC_MODE_PORT_MODE_MASK));
5633                                 udelay(40);
5634                                 tw32_f(MAC_MODE, tp->mac_mode);
5635                                 udelay(40);
5636                                 tg3_setup_phy(tp, 0);
5637                         }
5638                 }
5639
5640                 tp->timer_counter = tp->timer_multiplier;
5641         }
5642
5643         /* Heartbeat is only sent once every 120 seconds.  */
5644         if (!--tp->asf_counter) {
5645                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5646                         u32 val;
5647
5648                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5649                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5650                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5651                         val = tr32(GRC_RX_CPU_EVENT);
5652                         val |= (1 << 14);
5653                         tw32(GRC_RX_CPU_EVENT, val);
5654                 }
5655                 tp->asf_counter = tp->asf_multiplier;
5656         }
5657
5658         spin_unlock(&tp->tx_lock);
5659         spin_unlock_irqrestore(&tp->lock, flags);
5660
5661         tp->timer.expires = jiffies + tp->timer_offset;
5662         add_timer(&tp->timer);
5663 }
5664
5665 static int tg3_open(struct net_device *dev)
5666 {
5667         struct tg3 *tp = netdev_priv(dev);
5668         int err;
5669
5670         spin_lock_irq(&tp->lock);
5671         spin_lock(&tp->tx_lock);
5672
5673         tg3_disable_ints(tp);
5674         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
5675
5676         spin_unlock(&tp->tx_lock);
5677         spin_unlock_irq(&tp->lock);
5678
5679         /* The placement of this call is tied
5680          * to the setup and use of Host TX descriptors.
5681          */
5682         err = tg3_alloc_consistent(tp);
5683         if (err)
5684                 return err;
5685
5686         err = request_irq(dev->irq, tg3_interrupt,
5687                           SA_SHIRQ, dev->name, dev);
5688
5689         if (err) {
5690                 tg3_free_consistent(tp);
5691                 return err;
5692         }
5693
5694         spin_lock_irq(&tp->lock);
5695         spin_lock(&tp->tx_lock);
5696
5697         err = tg3_init_hw(tp);
5698         if (err) {
5699                 tg3_halt(tp);
5700                 tg3_free_rings(tp);
5701         } else {
5702                 tp->timer_offset = HZ / 10;
5703                 tp->timer_counter = tp->timer_multiplier = 10;
5704                 tp->asf_counter = tp->asf_multiplier = (10 * 120);
5705
5706                 init_timer(&tp->timer);
5707                 tp->timer.expires = jiffies + tp->timer_offset;
5708                 tp->timer.data = (unsigned long) tp;
5709                 tp->timer.function = tg3_timer;
5710                 add_timer(&tp->timer);
5711
5712                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
5713         }
5714
5715         spin_unlock(&tp->tx_lock);
5716         spin_unlock_irq(&tp->lock);
5717
5718         if (err) {
5719                 free_irq(dev->irq, dev);
5720                 tg3_free_consistent(tp);
5721                 return err;
5722         }
5723
5724         spin_lock_irq(&tp->lock);
5725         spin_lock(&tp->tx_lock);
5726
5727         tg3_enable_ints(tp);
5728
5729         spin_unlock(&tp->tx_lock);
5730         spin_unlock_irq(&tp->lock);
5731
5732         netif_start_queue(dev);
5733
5734         return 0;
5735 }
5736
5737 #if 0
5738 /*static*/ void tg3_dump_state(struct tg3 *tp)
5739 {
5740         u32 val32, val32_2, val32_3, val32_4, val32_5;
5741         u16 val16;
5742         int i;
5743
5744         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
5745         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
5746         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
5747                val16, val32);
5748
5749         /* MAC block */
5750         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
5751                tr32(MAC_MODE), tr32(MAC_STATUS));
5752         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
5753                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
5754         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
5755                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
5756         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
5757                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
5758
5759         /* Send data initiator control block */
5760         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
5761                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
5762         printk("       SNDDATAI_STATSCTRL[%08x]\n",
5763                tr32(SNDDATAI_STATSCTRL));
5764
5765         /* Send data completion control block */
5766         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
5767
5768         /* Send BD ring selector block */
5769         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
5770                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
5771
5772         /* Send BD initiator control block */
5773         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
5774                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
5775
5776         /* Send BD completion control block */
5777         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
5778
5779         /* Receive list placement control block */
5780         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
5781                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
5782         printk("       RCVLPC_STATSCTRL[%08x]\n",
5783                tr32(RCVLPC_STATSCTRL));
5784
5785         /* Receive data and receive BD initiator control block */
5786         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
5787                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
5788
5789         /* Receive data completion control block */
5790         printk("DEBUG: RCVDCC_MODE[%08x]\n",
5791                tr32(RCVDCC_MODE));
5792
5793         /* Receive BD initiator control block */
5794         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
5795                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
5796
5797         /* Receive BD completion control block */
5798         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
5799                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
5800
5801         /* Receive list selector control block */
5802         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
5803                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
5804
5805         /* Mbuf cluster free block */
5806         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
5807                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
5808
5809         /* Host coalescing control block */
5810         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
5811                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
5812         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
5813                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
5814                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
5815         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
5816                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
5817                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
5818         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
5819                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
5820         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
5821                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
5822
5823         /* Memory arbiter control block */
5824         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
5825                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
5826
5827         /* Buffer manager control block */
5828         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
5829                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
5830         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
5831                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
5832         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
5833                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
5834                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
5835                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
5836
5837         /* Read DMA control block */
5838         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
5839                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
5840
5841         /* Write DMA control block */
5842         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
5843                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
5844
5845         /* DMA completion block */
5846         printk("DEBUG: DMAC_MODE[%08x]\n",
5847                tr32(DMAC_MODE));
5848
5849         /* GRC block */
5850         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
5851                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
5852         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
5853                tr32(GRC_LOCAL_CTRL));
5854
5855         /* TG3_BDINFOs */
5856         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
5857                tr32(RCVDBDI_JUMBO_BD + 0x0),
5858                tr32(RCVDBDI_JUMBO_BD + 0x4),
5859                tr32(RCVDBDI_JUMBO_BD + 0x8),
5860                tr32(RCVDBDI_JUMBO_BD + 0xc));
5861         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
5862                tr32(RCVDBDI_STD_BD + 0x0),
5863                tr32(RCVDBDI_STD_BD + 0x4),
5864                tr32(RCVDBDI_STD_BD + 0x8),
5865                tr32(RCVDBDI_STD_BD + 0xc));
5866         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
5867                tr32(RCVDBDI_MINI_BD + 0x0),
5868                tr32(RCVDBDI_MINI_BD + 0x4),
5869                tr32(RCVDBDI_MINI_BD + 0x8),
5870                tr32(RCVDBDI_MINI_BD + 0xc));
5871
5872         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
5873         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
5874         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
5875         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
5876         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
5877                val32, val32_2, val32_3, val32_4);
5878
5879         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
5880         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
5881         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
5882         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
5883         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
5884                val32, val32_2, val32_3, val32_4);
5885
5886         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
5887         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
5888         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
5889         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
5890         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
5891         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
5892                val32, val32_2, val32_3, val32_4, val32_5);
5893
5894         /* SW status block */
5895         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5896                tp->hw_status->status,
5897                tp->hw_status->status_tag,
5898                tp->hw_status->rx_jumbo_consumer,
5899                tp->hw_status->rx_consumer,
5900                tp->hw_status->rx_mini_consumer,
5901                tp->hw_status->idx[0].rx_producer,
5902                tp->hw_status->idx[0].tx_consumer);
5903
5904         /* SW statistics block */
5905         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
5906                ((u32 *)tp->hw_stats)[0],
5907                ((u32 *)tp->hw_stats)[1],
5908                ((u32 *)tp->hw_stats)[2],
5909                ((u32 *)tp->hw_stats)[3]);
5910
5911         /* Mailboxes */
5912         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
5913                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
5914                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
5915                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
5916                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
5917
5918         /* NIC side send descriptors. */
5919         for (i = 0; i < 6; i++) {
5920                 unsigned long txd;
5921
5922                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
5923                         + (i * sizeof(struct tg3_tx_buffer_desc));
5924                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
5925                        i,
5926                        readl(txd + 0x0), readl(txd + 0x4),
5927                        readl(txd + 0x8), readl(txd + 0xc));
5928         }
5929
5930         /* NIC side RX descriptors. */
5931         for (i = 0; i < 6; i++) {
5932                 unsigned long rxd;
5933
5934                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
5935                         + (i * sizeof(struct tg3_rx_buffer_desc));
5936                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
5937                        i,
5938                        readl(rxd + 0x0), readl(rxd + 0x4),
5939                        readl(rxd + 0x8), readl(rxd + 0xc));
5940                 rxd += (4 * sizeof(u32));
5941                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
5942                        i,
5943                        readl(rxd + 0x0), readl(rxd + 0x4),
5944                        readl(rxd + 0x8), readl(rxd + 0xc));
5945         }
5946
5947         for (i = 0; i < 6; i++) {
5948                 unsigned long rxd;
5949
5950                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
5951                         + (i * sizeof(struct tg3_rx_buffer_desc));
5952                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
5953                        i,
5954                        readl(rxd + 0x0), readl(rxd + 0x4),
5955                        readl(rxd + 0x8), readl(rxd + 0xc));
5956                 rxd += (4 * sizeof(u32));
5957                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
5958                        i,
5959                        readl(rxd + 0x0), readl(rxd + 0x4),
5960                        readl(rxd + 0x8), readl(rxd + 0xc));
5961         }
5962 }
5963 #endif
5964
5965 static struct net_device_stats *tg3_get_stats(struct net_device *);
5966 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
5967
5968 static int tg3_close(struct net_device *dev)
5969 {
5970         struct tg3 *tp = netdev_priv(dev);
5971
5972         netif_stop_queue(dev);
5973
5974         del_timer_sync(&tp->timer);
5975
5976         spin_lock_irq(&tp->lock);
5977         spin_lock(&tp->tx_lock);
5978 #if 0
5979         tg3_dump_state(tp);
5980 #endif
5981
5982         tg3_disable_ints(tp);
5983
5984         tg3_halt(tp);
5985         tg3_free_rings(tp);
5986         tp->tg3_flags &=
5987                 ~(TG3_FLAG_INIT_COMPLETE |
5988                   TG3_FLAG_GOT_SERDES_FLOWCTL);
5989         netif_carrier_off(tp->dev);
5990
5991         spin_unlock(&tp->tx_lock);
5992         spin_unlock_irq(&tp->lock);
5993
5994         free_irq(dev->irq, dev);
5995
5996         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
5997                sizeof(tp->net_stats_prev));
5998         memcpy(&tp->estats_prev, tg3_get_estats(tp),
5999                sizeof(tp->estats_prev));
6000
6001         tg3_free_consistent(tp);
6002
6003         return 0;
6004 }
6005
6006 static inline unsigned long get_stat64(tg3_stat64_t *val)
6007 {
6008         unsigned long ret;
6009
6010 #if (BITS_PER_LONG == 32)
6011         ret = val->low;
6012 #else
6013         ret = ((u64)val->high << 32) | ((u64)val->low);
6014 #endif
6015         return ret;
6016 }
6017
6018 static unsigned long calc_crc_errors(struct tg3 *tp)
6019 {
6020         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6021
6022         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6023             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6024              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6025                 unsigned long flags;
6026                 u32 val;
6027
6028                 spin_lock_irqsave(&tp->lock, flags);
6029                 tg3_readphy(tp, 0x1e, &val);
6030                 tg3_writephy(tp, 0x1e, val | 0x8000);
6031                 tg3_readphy(tp, 0x14, &val);
6032                 spin_unlock_irqrestore(&tp->lock, flags);
6033
6034                 tp->phy_crc_errors += val;
6035
6036                 return tp->phy_crc_errors;
6037         }
6038
6039         return get_stat64(&hw_stats->rx_fcs_errors);
6040 }
6041
6042 #define ESTAT_ADD(member) \
6043         estats->member =        old_estats->member + \
6044                                 get_stat64(&hw_stats->member)
6045
6046 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6047 {
6048         struct tg3_ethtool_stats *estats = &tp->estats;
6049         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6050         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6051
6052         if (!hw_stats)
6053                 return old_estats;
6054
6055         ESTAT_ADD(rx_octets);
6056         ESTAT_ADD(rx_fragments);
6057         ESTAT_ADD(rx_ucast_packets);
6058         ESTAT_ADD(rx_mcast_packets);
6059         ESTAT_ADD(rx_bcast_packets);
6060         ESTAT_ADD(rx_fcs_errors);
6061         ESTAT_ADD(rx_align_errors);
6062         ESTAT_ADD(rx_xon_pause_rcvd);
6063         ESTAT_ADD(rx_xoff_pause_rcvd);
6064         ESTAT_ADD(rx_mac_ctrl_rcvd);
6065         ESTAT_ADD(rx_xoff_entered);
6066         ESTAT_ADD(rx_frame_too_long_errors);
6067         ESTAT_ADD(rx_jabbers);
6068         ESTAT_ADD(rx_undersize_packets);
6069         ESTAT_ADD(rx_in_length_errors);
6070         ESTAT_ADD(rx_out_length_errors);
6071         ESTAT_ADD(rx_64_or_less_octet_packets);
6072         ESTAT_ADD(rx_65_to_127_octet_packets);
6073         ESTAT_ADD(rx_128_to_255_octet_packets);
6074         ESTAT_ADD(rx_256_to_511_octet_packets);
6075         ESTAT_ADD(rx_512_to_1023_octet_packets);
6076         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6077         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6078         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6079         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6080         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6081
6082         ESTAT_ADD(tx_octets);
6083         ESTAT_ADD(tx_collisions);
6084         ESTAT_ADD(tx_xon_sent);
6085         ESTAT_ADD(tx_xoff_sent);
6086         ESTAT_ADD(tx_flow_control);
6087         ESTAT_ADD(tx_mac_errors);
6088         ESTAT_ADD(tx_single_collisions);
6089         ESTAT_ADD(tx_mult_collisions);
6090         ESTAT_ADD(tx_deferred);
6091         ESTAT_ADD(tx_excessive_collisions);
6092         ESTAT_ADD(tx_late_collisions);
6093         ESTAT_ADD(tx_collide_2times);
6094         ESTAT_ADD(tx_collide_3times);
6095         ESTAT_ADD(tx_collide_4times);
6096         ESTAT_ADD(tx_collide_5times);
6097         ESTAT_ADD(tx_collide_6times);
6098         ESTAT_ADD(tx_collide_7times);
6099         ESTAT_ADD(tx_collide_8times);
6100         ESTAT_ADD(tx_collide_9times);
6101         ESTAT_ADD(tx_collide_10times);
6102         ESTAT_ADD(tx_collide_11times);
6103         ESTAT_ADD(tx_collide_12times);
6104         ESTAT_ADD(tx_collide_13times);
6105         ESTAT_ADD(tx_collide_14times);
6106         ESTAT_ADD(tx_collide_15times);
6107         ESTAT_ADD(tx_ucast_packets);
6108         ESTAT_ADD(tx_mcast_packets);
6109         ESTAT_ADD(tx_bcast_packets);
6110         ESTAT_ADD(tx_carrier_sense_errors);
6111         ESTAT_ADD(tx_discards);
6112         ESTAT_ADD(tx_errors);
6113
6114         ESTAT_ADD(dma_writeq_full);
6115         ESTAT_ADD(dma_write_prioq_full);
6116         ESTAT_ADD(rxbds_empty);
6117         ESTAT_ADD(rx_discards);
6118         ESTAT_ADD(rx_errors);
6119         ESTAT_ADD(rx_threshold_hit);
6120
6121         ESTAT_ADD(dma_readq_full);
6122         ESTAT_ADD(dma_read_prioq_full);
6123         ESTAT_ADD(tx_comp_queue_full);
6124
6125         ESTAT_ADD(ring_set_send_prod_index);
6126         ESTAT_ADD(ring_status_update);
6127         ESTAT_ADD(nic_irqs);
6128         ESTAT_ADD(nic_avoided_irqs);
6129         ESTAT_ADD(nic_tx_threshold_hit);
6130
6131         return estats;
6132 }
6133
6134 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6135 {
6136         struct tg3 *tp = netdev_priv(dev);
6137         struct net_device_stats *stats = &tp->net_stats;
6138         struct net_device_stats *old_stats = &tp->net_stats_prev;
6139         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6140
6141         if (!hw_stats)
6142                 return old_stats;
6143
6144         stats->rx_packets = old_stats->rx_packets +
6145                 get_stat64(&hw_stats->rx_ucast_packets) +
6146                 get_stat64(&hw_stats->rx_mcast_packets) +
6147                 get_stat64(&hw_stats->rx_bcast_packets);
6148
6149         stats->tx_packets = old_stats->tx_packets +
6150                 get_stat64(&hw_stats->tx_ucast_packets) +
6151                 get_stat64(&hw_stats->tx_mcast_packets) +
6152                 get_stat64(&hw_stats->tx_bcast_packets);
6153
6154         stats->rx_bytes = old_stats->rx_bytes +
6155                 get_stat64(&hw_stats->rx_octets);
6156         stats->tx_bytes = old_stats->tx_bytes +
6157                 get_stat64(&hw_stats->tx_octets);
6158
6159         stats->rx_errors = old_stats->rx_errors +
6160                 get_stat64(&hw_stats->rx_errors) +
6161                 get_stat64(&hw_stats->rx_discards);
6162         stats->tx_errors = old_stats->tx_errors +
6163                 get_stat64(&hw_stats->tx_errors) +
6164                 get_stat64(&hw_stats->tx_mac_errors) +
6165                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6166                 get_stat64(&hw_stats->tx_discards);
6167
6168         stats->multicast = old_stats->multicast +
6169                 get_stat64(&hw_stats->rx_mcast_packets);
6170         stats->collisions = old_stats->collisions +
6171                 get_stat64(&hw_stats->tx_collisions);
6172
6173         stats->rx_length_errors = old_stats->rx_length_errors +
6174                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6175                 get_stat64(&hw_stats->rx_undersize_packets);
6176
6177         stats->rx_over_errors = old_stats->rx_over_errors +
6178                 get_stat64(&hw_stats->rxbds_empty);
6179         stats->rx_frame_errors = old_stats->rx_frame_errors +
6180                 get_stat64(&hw_stats->rx_align_errors);
6181         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6182                 get_stat64(&hw_stats->tx_discards);
6183         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6184                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6185
6186         stats->rx_crc_errors = old_stats->rx_crc_errors +
6187                 calc_crc_errors(tp);
6188
6189         return stats;
6190 }
6191
6192 static inline u32 calc_crc(unsigned char *buf, int len)
6193 {
6194         u32 reg;
6195         u32 tmp;
6196         int j, k;
6197
6198         reg = 0xffffffff;
6199
6200         for (j = 0; j < len; j++) {
6201                 reg ^= buf[j];
6202
6203                 for (k = 0; k < 8; k++) {
6204                         tmp = reg & 0x01;
6205
6206                         reg >>= 1;
6207
6208                         if (tmp) {
6209                                 reg ^= 0xedb88320;
6210                         }
6211                 }
6212         }
6213
6214         return ~reg;
6215 }
6216
6217 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6218 {
6219         /* accept or reject all multicast frames */
6220         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6221         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6222         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6223         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6224 }
6225
6226 static void __tg3_set_rx_mode(struct net_device *dev)
6227 {
6228         struct tg3 *tp = netdev_priv(dev);
6229         u32 rx_mode;
6230
6231         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6232                                   RX_MODE_KEEP_VLAN_TAG);
6233
6234         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6235          * flag clear.
6236          */
6237 #if TG3_VLAN_TAG_USED
6238         if (!tp->vlgrp &&
6239             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6240                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6241 #else
6242         /* By definition, VLAN is disabled always in this
6243          * case.
6244          */
6245         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6246                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6247 #endif
6248
6249         if (dev->flags & IFF_PROMISC) {
6250                 /* Promiscuous mode. */
6251                 rx_mode |= RX_MODE_PROMISC;
6252         } else if (dev->flags & IFF_ALLMULTI) {
6253                 /* Accept all multicast. */
6254                 tg3_set_multi (tp, 1);
6255         } else if (dev->mc_count < 1) {
6256                 /* Reject all multicast. */
6257                 tg3_set_multi (tp, 0);
6258         } else {
6259                 /* Accept one or more multicast(s). */
6260                 struct dev_mc_list *mclist;
6261                 unsigned int i;
6262                 u32 mc_filter[4] = { 0, };
6263                 u32 regidx;
6264                 u32 bit;
6265                 u32 crc;
6266
6267                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6268                      i++, mclist = mclist->next) {
6269
6270                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6271                         bit = ~crc & 0x7f;
6272                         regidx = (bit & 0x60) >> 5;
6273                         bit &= 0x1f;
6274                         mc_filter[regidx] |= (1 << bit);
6275                 }
6276
6277                 tw32(MAC_HASH_REG_0, mc_filter[0]);
6278                 tw32(MAC_HASH_REG_1, mc_filter[1]);
6279                 tw32(MAC_HASH_REG_2, mc_filter[2]);
6280                 tw32(MAC_HASH_REG_3, mc_filter[3]);
6281         }
6282
6283         if (rx_mode != tp->rx_mode) {
6284                 tp->rx_mode = rx_mode;
6285                 tw32_f(MAC_RX_MODE, rx_mode);
6286                 udelay(10);
6287         }
6288 }
6289
6290 static void tg3_set_rx_mode(struct net_device *dev)
6291 {
6292         struct tg3 *tp = netdev_priv(dev);
6293
6294         spin_lock_irq(&tp->lock);
6295         spin_lock(&tp->tx_lock);
6296         __tg3_set_rx_mode(dev);
6297         spin_unlock(&tp->tx_lock);
6298         spin_unlock_irq(&tp->lock);
6299 }
6300
6301 #define TG3_REGDUMP_LEN         (32 * 1024)
6302
6303 static int tg3_get_regs_len(struct net_device *dev)
6304 {
6305         return TG3_REGDUMP_LEN;
6306 }
6307
6308 static void tg3_get_regs(struct net_device *dev,
6309                 struct ethtool_regs *regs, void *_p)
6310 {
6311         u32 *p = _p;
6312         struct tg3 *tp = netdev_priv(dev);
6313         u8 *orig_p = _p;
6314         int i;
6315
6316         regs->version = 0;
6317
6318         memset(p, 0, TG3_REGDUMP_LEN);
6319
6320         spin_lock_irq(&tp->lock);
6321         spin_lock(&tp->tx_lock);
6322
6323 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
6324 #define GET_REG32_LOOP(base,len)                \
6325 do {    p = (u32 *)(orig_p + (base));           \
6326         for (i = 0; i < len; i += 4)            \
6327                 __GET_REG32((base) + i);        \
6328 } while (0)
6329 #define GET_REG32_1(reg)                        \
6330 do {    p = (u32 *)(orig_p + (reg));            \
6331         __GET_REG32((reg));                     \
6332 } while (0)
6333
6334         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6335         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6336         GET_REG32_LOOP(MAC_MODE, 0x4f0);
6337         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6338         GET_REG32_1(SNDDATAC_MODE);
6339         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6340         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6341         GET_REG32_1(SNDBDC_MODE);
6342         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6343         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6344         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6345         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6346         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6347         GET_REG32_1(RCVDCC_MODE);
6348         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6349         GET_REG32_LOOP(RCVCC_MODE, 0x14);
6350         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6351         GET_REG32_1(MBFREE_MODE);
6352         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6353         GET_REG32_LOOP(MEMARB_MODE, 0x10);
6354         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6355         GET_REG32_LOOP(RDMAC_MODE, 0x08);
6356         GET_REG32_LOOP(WDMAC_MODE, 0x08);
6357         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6358         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6359         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6360         GET_REG32_LOOP(FTQ_RESET, 0x120);
6361         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6362         GET_REG32_1(DMAC_MODE);
6363         GET_REG32_LOOP(GRC_MODE, 0x4c);
6364         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6365                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6366
6367 #undef __GET_REG32
6368 #undef GET_REG32_LOOP
6369 #undef GET_REG32_1
6370
6371         spin_unlock(&tp->tx_lock);
6372         spin_unlock_irq(&tp->lock);
6373 }
6374
6375 static int tg3_get_eeprom_len(struct net_device *dev)
6376 {
6377         return EEPROM_CHIP_SIZE;
6378 }
6379
6380 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
6381                                         u32 offset, u32 *val);
6382 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6383 {
6384         struct tg3 *tp = netdev_priv(dev);
6385         int ret;
6386         u8  *pd;
6387         u32 i, offset, len, val, b_offset, b_count;
6388
6389         offset = eeprom->offset;
6390         len = eeprom->len;
6391         eeprom->len = 0;
6392
6393         ret = tg3_nvram_read_using_eeprom(tp, 0, &eeprom->magic);
6394         if (ret)
6395                 return ret;
6396         eeprom->magic = swab32(eeprom->magic);
6397
6398         if (offset & 3) {
6399                 /* adjustments to start on required 4 byte boundary */
6400                 b_offset = offset & 3;
6401                 b_count = 4 - b_offset;
6402                 if (b_count > len) {
6403                         /* i.e. offset=1 len=2 */
6404                         b_count = len;
6405                 }
6406                 ret = tg3_nvram_read_using_eeprom(tp, offset-b_offset, &val);
6407                 if (ret)
6408                         return ret;
6409                 memcpy(data, ((char*)&val) + b_offset, b_count);
6410                 len -= b_count;
6411                 offset += b_count;
6412                 eeprom->len += b_count;
6413         }
6414
6415         /* read bytes upto the last 4 byte boundary */
6416         pd = &data[eeprom->len];
6417         for (i = 0; i < (len - (len & 3)); i += 4) {
6418                 ret = tg3_nvram_read_using_eeprom(tp, offset + i,
6419                                 (u32*)(pd + i));
6420                 if (ret) {
6421                         eeprom->len += i;
6422                         return ret;
6423                 }
6424         }
6425         eeprom->len += i;
6426
6427         if (len & 3) {
6428                 /* read last bytes not ending on 4 byte boundary */
6429                 pd = &data[eeprom->len];
6430                 b_count = len & 3;
6431                 b_offset = offset + len - b_count;
6432                 ret = tg3_nvram_read_using_eeprom(tp, b_offset, &val);
6433                 if (ret)
6434                         return ret;
6435                 memcpy(pd, ((char*)&val), b_count);
6436                 eeprom->len += b_count;
6437         }
6438         return 0;
6439 }
6440
6441 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6442 {
6443         struct tg3 *tp = netdev_priv(dev);
6444
6445         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
6446                                         tp->link_config.phy_is_low_power)
6447                 return -EAGAIN;
6448
6449         cmd->supported = (SUPPORTED_Autoneg);
6450
6451         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6452                 cmd->supported |= (SUPPORTED_1000baseT_Half |
6453                                    SUPPORTED_1000baseT_Full);
6454
6455         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6456                 cmd->supported |= (SUPPORTED_100baseT_Half |
6457                                   SUPPORTED_100baseT_Full |
6458                                   SUPPORTED_10baseT_Half |
6459                                   SUPPORTED_10baseT_Full |
6460                                   SUPPORTED_MII);
6461         else
6462                 cmd->supported |= SUPPORTED_FIBRE;
6463
6464         cmd->advertising = tp->link_config.advertising;
6465         cmd->speed = tp->link_config.active_speed;
6466         cmd->duplex = tp->link_config.active_duplex;
6467         cmd->port = 0;
6468         cmd->phy_address = PHY_ADDR;
6469         cmd->transceiver = 0;
6470         cmd->autoneg = tp->link_config.autoneg;
6471         cmd->maxtxpkt = 0;
6472         cmd->maxrxpkt = 0;
6473         return 0;
6474 }
6475
6476 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6477 {
6478         struct tg3 *tp = netdev_priv(dev);
6479
6480         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
6481             tp->link_config.phy_is_low_power)
6482                 return -EAGAIN;
6483
6484         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6485                 /* These are the only valid advertisement bits allowed.  */
6486                 if (cmd->autoneg == AUTONEG_ENABLE &&
6487                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6488                                           ADVERTISED_1000baseT_Full |
6489                                           ADVERTISED_Autoneg |
6490                                           ADVERTISED_FIBRE)))
6491                         return -EINVAL;
6492         }
6493
6494         spin_lock_irq(&tp->lock);
6495         spin_lock(&tp->tx_lock);
6496
6497         tp->link_config.autoneg = cmd->autoneg;
6498         if (cmd->autoneg == AUTONEG_ENABLE) {
6499                 tp->link_config.advertising = cmd->advertising;
6500                 tp->link_config.speed = SPEED_INVALID;
6501                 tp->link_config.duplex = DUPLEX_INVALID;
6502         } else {
6503                 tp->link_config.advertising = 0;
6504                 tp->link_config.speed = cmd->speed;
6505                 tp->link_config.duplex = cmd->duplex;
6506         }
6507
6508         tg3_setup_phy(tp, 1);
6509         spin_unlock(&tp->tx_lock);
6510         spin_unlock_irq(&tp->lock);
6511
6512         return 0;
6513 }
6514
6515 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6516 {
6517         struct tg3 *tp = netdev_priv(dev);
6518
6519         strcpy(info->driver, DRV_MODULE_NAME);
6520         strcpy(info->version, DRV_MODULE_VERSION);
6521         strcpy(info->bus_info, pci_name(tp->pdev));
6522 }
6523
6524 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6525 {
6526         struct tg3 *tp = netdev_priv(dev);
6527
6528         wol->supported = WAKE_MAGIC;
6529         wol->wolopts = 0;
6530         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6531                 wol->wolopts = WAKE_MAGIC;
6532         memset(&wol->sopass, 0, sizeof(wol->sopass));
6533 }
6534
6535 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6536 {
6537         struct tg3 *tp = netdev_priv(dev);
6538
6539         if (wol->wolopts & ~WAKE_MAGIC)
6540                 return -EINVAL;
6541         if ((wol->wolopts & WAKE_MAGIC) &&
6542             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
6543             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
6544                 return -EINVAL;
6545
6546         spin_lock_irq(&tp->lock);
6547         if (wol->wolopts & WAKE_MAGIC)
6548                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6549         else
6550                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
6551         spin_unlock_irq(&tp->lock);
6552
6553         return 0;
6554 }
6555
6556 static u32 tg3_get_msglevel(struct net_device *dev)
6557 {
6558         struct tg3 *tp = netdev_priv(dev);
6559         return tp->msg_enable;
6560 }
6561
6562 static void tg3_set_msglevel(struct net_device *dev, u32 value)
6563 {
6564         struct tg3 *tp = netdev_priv(dev);
6565         tp->msg_enable = value;
6566 }
6567
6568 #if TG3_TSO_SUPPORT != 0
6569 static int tg3_set_tso(struct net_device *dev, u32 value)
6570 {
6571         struct tg3 *tp = netdev_priv(dev);
6572
6573         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6574                 if (value)
6575                         return -EINVAL;
6576                 return 0;
6577         }
6578         return ethtool_op_set_tso(dev, value);
6579 }
6580 #endif
6581
6582 static int tg3_nway_reset(struct net_device *dev)
6583 {
6584         struct tg3 *tp = netdev_priv(dev);
6585         u32 bmcr;
6586         int r;
6587
6588         spin_lock_irq(&tp->lock);
6589         tg3_readphy(tp, MII_BMCR, &bmcr);
6590         tg3_readphy(tp, MII_BMCR, &bmcr);
6591         r = -EINVAL;
6592         if (bmcr & BMCR_ANENABLE) {
6593                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
6594                 r = 0;
6595         }
6596         spin_unlock_irq(&tp->lock);
6597
6598         return r;
6599 }
6600
6601 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6602 {
6603         struct tg3 *tp = netdev_priv(dev);
6604
6605         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
6606         ering->rx_mini_max_pending = 0;
6607         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
6608
6609         ering->rx_pending = tp->rx_pending;
6610         ering->rx_mini_pending = 0;
6611         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
6612         ering->tx_pending = tp->tx_pending;
6613 }
6614
6615 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6616 {
6617         struct tg3 *tp = netdev_priv(dev);
6618
6619         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
6620             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
6621             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
6622                 return -EINVAL;
6623
6624         tg3_netif_stop(tp);
6625         spin_lock_irq(&tp->lock);
6626         spin_lock(&tp->tx_lock);
6627
6628         tp->rx_pending = ering->rx_pending;
6629
6630         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
6631             tp->rx_pending > 63)
6632                 tp->rx_pending = 63;
6633         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
6634         tp->tx_pending = ering->tx_pending;
6635
6636         tg3_halt(tp);
6637         tg3_init_hw(tp);
6638         tg3_netif_start(tp);
6639         spin_unlock(&tp->tx_lock);
6640         spin_unlock_irq(&tp->lock);
6641
6642         return 0;
6643 }
6644
6645 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6646 {
6647         struct tg3 *tp = netdev_priv(dev);
6648
6649         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
6650         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
6651         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
6652 }
6653
6654 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6655 {
6656         struct tg3 *tp = netdev_priv(dev);
6657
6658         tg3_netif_stop(tp);
6659         spin_lock_irq(&tp->lock);
6660         spin_lock(&tp->tx_lock);
6661         if (epause->autoneg)
6662                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
6663         else
6664                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
6665         if (epause->rx_pause)
6666                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
6667         else
6668                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
6669         if (epause->tx_pause)
6670                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
6671         else
6672                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
6673         tg3_halt(tp);
6674         tg3_init_hw(tp);
6675         tg3_netif_start(tp);
6676         spin_unlock(&tp->tx_lock);
6677         spin_unlock_irq(&tp->lock);
6678
6679         return 0;
6680 }
6681
6682 static u32 tg3_get_rx_csum(struct net_device *dev)
6683 {
6684         struct tg3 *tp = netdev_priv(dev);
6685         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
6686 }
6687
6688 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
6689 {
6690         struct tg3 *tp = netdev_priv(dev);
6691
6692         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
6693                 if (data != 0)
6694                         return -EINVAL;
6695                 return 0;
6696         }
6697
6698         spin_lock_irq(&tp->lock);
6699         if (data)
6700                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
6701         else
6702                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
6703         spin_unlock_irq(&tp->lock);
6704
6705         return 0;
6706 }
6707
6708 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
6709 {
6710         struct tg3 *tp = netdev_priv(dev);
6711
6712         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
6713                 if (data != 0)
6714                         return -EINVAL;
6715                 return 0;
6716         }
6717
6718         if (data)
6719                 dev->features |= NETIF_F_IP_CSUM;
6720         else
6721                 dev->features &= ~NETIF_F_IP_CSUM;
6722
6723         return 0;
6724 }
6725
6726 static int tg3_get_stats_count (struct net_device *dev)
6727 {
6728         return TG3_NUM_STATS;
6729 }
6730
6731 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
6732 {
6733         switch (stringset) {
6734         case ETH_SS_STATS:
6735                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
6736                 break;
6737         default:
6738                 WARN_ON(1);     /* we need a WARN() */
6739                 break;
6740         }
6741 }
6742
6743 static void tg3_get_ethtool_stats (struct net_device *dev,
6744                                    struct ethtool_stats *estats, u64 *tmp_stats)
6745 {
6746         struct tg3 *tp = netdev_priv(dev);
6747         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
6748 }
6749
6750 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6751 {
6752         struct mii_ioctl_data *data = if_mii(ifr);
6753         struct tg3 *tp = netdev_priv(dev);
6754         int err;
6755
6756         switch(cmd) {
6757         case SIOCGMIIPHY:
6758                 data->phy_id = PHY_ADDR;
6759
6760                 /* fallthru */
6761         case SIOCGMIIREG: {
6762                 u32 mii_regval;
6763
6764                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
6765                         break;                  /* We have no PHY */
6766
6767                 spin_lock_irq(&tp->lock);
6768                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
6769                 spin_unlock_irq(&tp->lock);
6770
6771                 data->val_out = mii_regval;
6772
6773                 return err;
6774         }
6775
6776         case SIOCSMIIREG:
6777                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
6778                         break;                  /* We have no PHY */
6779
6780                 if (!capable(CAP_NET_ADMIN))
6781                         return -EPERM;
6782
6783                 spin_lock_irq(&tp->lock);
6784                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
6785                 spin_unlock_irq(&tp->lock);
6786
6787                 return err;
6788
6789         default:
6790                 /* do nothing */
6791                 break;
6792         }
6793         return -EOPNOTSUPP;
6794 }
6795
6796 #if TG3_VLAN_TAG_USED
6797 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
6798 {
6799         struct tg3 *tp = netdev_priv(dev);
6800
6801         spin_lock_irq(&tp->lock);
6802         spin_lock(&tp->tx_lock);
6803
6804         tp->vlgrp = grp;
6805
6806         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
6807         __tg3_set_rx_mode(dev);
6808
6809         spin_unlock(&tp->tx_lock);
6810         spin_unlock_irq(&tp->lock);
6811 }
6812
6813 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
6814 {
6815         struct tg3 *tp = netdev_priv(dev);
6816
6817         spin_lock_irq(&tp->lock);
6818         spin_lock(&tp->tx_lock);
6819         if (tp->vlgrp)
6820                 tp->vlgrp->vlan_devices[vid] = NULL;
6821         spin_unlock(&tp->tx_lock);
6822         spin_unlock_irq(&tp->lock);
6823 }
6824 #endif
6825
6826 static struct ethtool_ops tg3_ethtool_ops = {
6827         .get_settings           = tg3_get_settings,
6828         .set_settings           = tg3_set_settings,
6829         .get_drvinfo            = tg3_get_drvinfo,
6830         .get_regs_len           = tg3_get_regs_len,
6831         .get_regs               = tg3_get_regs,
6832         .get_wol                = tg3_get_wol,
6833         .set_wol                = tg3_set_wol,
6834         .get_msglevel           = tg3_get_msglevel,
6835         .set_msglevel           = tg3_set_msglevel,
6836         .nway_reset             = tg3_nway_reset,
6837         .get_link               = ethtool_op_get_link,
6838         .get_eeprom_len         = tg3_get_eeprom_len,
6839         .get_eeprom             = tg3_get_eeprom,
6840         .get_ringparam          = tg3_get_ringparam,
6841         .set_ringparam          = tg3_set_ringparam,
6842         .get_pauseparam         = tg3_get_pauseparam,
6843         .set_pauseparam         = tg3_set_pauseparam,
6844         .get_rx_csum            = tg3_get_rx_csum,
6845         .set_rx_csum            = tg3_set_rx_csum,
6846         .get_tx_csum            = ethtool_op_get_tx_csum,
6847         .set_tx_csum            = tg3_set_tx_csum,
6848         .get_sg                 = ethtool_op_get_sg,
6849         .set_sg                 = ethtool_op_set_sg,
6850 #if TG3_TSO_SUPPORT != 0
6851         .get_tso                = ethtool_op_get_tso,
6852         .set_tso                = tg3_set_tso,
6853 #endif
6854         .get_strings            = tg3_get_strings,
6855         .get_stats_count        = tg3_get_stats_count,
6856         .get_ethtool_stats      = tg3_get_ethtool_stats,
6857 };
6858
6859 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
6860 static void __devinit tg3_nvram_init(struct tg3 *tp)
6861 {
6862         int j;
6863
6864         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
6865                 return;
6866
6867         tw32_f(GRC_EEPROM_ADDR,
6868              (EEPROM_ADDR_FSM_RESET |
6869               (EEPROM_DEFAULT_CLOCK_PERIOD <<
6870                EEPROM_ADDR_CLKPERD_SHIFT)));
6871
6872         /* XXX schedule_timeout() ... */
6873         for (j = 0; j < 100; j++)
6874                 udelay(10);
6875
6876         /* Enable seeprom accesses. */
6877         tw32_f(GRC_LOCAL_CTRL,
6878              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
6879         udelay(100);
6880
6881         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
6882             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
6883                 u32 nvcfg1;
6884
6885                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6886                         u32 nvaccess = tr32(NVRAM_ACCESS);
6887
6888                         tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
6889                 }
6890
6891                 nvcfg1 = tr32(NVRAM_CFG1);
6892
6893                 tp->tg3_flags |= TG3_FLAG_NVRAM;
6894                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
6895                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
6896                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
6897                 } else {
6898                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
6899                         tw32(NVRAM_CFG1, nvcfg1);
6900                 }
6901
6902                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6903                         u32 nvaccess = tr32(NVRAM_ACCESS);
6904
6905                         tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
6906                 }
6907         } else {
6908                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
6909         }
6910 }
6911
6912 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
6913                                         u32 offset, u32 *val)
6914 {
6915         u32 tmp;
6916         int i;
6917
6918         if (offset > EEPROM_ADDR_ADDR_MASK ||
6919             (offset % 4) != 0)
6920                 return -EINVAL;
6921
6922         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
6923                                         EEPROM_ADDR_DEVID_MASK |
6924                                         EEPROM_ADDR_READ);
6925         tw32(GRC_EEPROM_ADDR,
6926              tmp |
6927              (0 << EEPROM_ADDR_DEVID_SHIFT) |
6928              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
6929               EEPROM_ADDR_ADDR_MASK) |
6930              EEPROM_ADDR_READ | EEPROM_ADDR_START);
6931
6932         for (i = 0; i < 10000; i++) {
6933                 tmp = tr32(GRC_EEPROM_ADDR);
6934
6935                 if (tmp & EEPROM_ADDR_COMPLETE)
6936                         break;
6937                 udelay(100);
6938         }
6939         if (!(tmp & EEPROM_ADDR_COMPLETE))
6940                 return -EBUSY;
6941
6942         *val = tr32(GRC_EEPROM_DATA);
6943         return 0;
6944 }
6945
6946 static int __devinit tg3_nvram_read(struct tg3 *tp,
6947                                     u32 offset, u32 *val)
6948 {
6949         int i;
6950
6951         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
6952                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
6953                 return -EINVAL;
6954         }
6955
6956         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
6957                 return tg3_nvram_read_using_eeprom(tp, offset, val);
6958
6959         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
6960                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
6961                           NVRAM_BUFFERED_PAGE_POS) +
6962                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
6963
6964         if (offset > NVRAM_ADDR_MSK)
6965                 return -EINVAL;
6966
6967         tg3_nvram_lock(tp);
6968
6969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6970                 u32 nvaccess = tr32(NVRAM_ACCESS);
6971
6972                 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
6973         }
6974
6975         tw32(NVRAM_ADDR, offset);
6976         tw32(NVRAM_CMD,
6977              NVRAM_CMD_RD | NVRAM_CMD_GO |
6978              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
6979
6980         /* Wait for done bit to clear. */
6981         for (i = 0; i < 1000; i++) {
6982                 udelay(10);
6983                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
6984                         udelay(10);
6985                         *val = swab32(tr32(NVRAM_RDDATA));
6986                         break;
6987                 }
6988         }
6989
6990         tg3_nvram_unlock(tp);
6991
6992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6993                 u32 nvaccess = tr32(NVRAM_ACCESS);
6994
6995                 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
6996         }
6997
6998         if (i >= 1000)
6999                 return -EBUSY;
7000
7001         return 0;
7002 }
7003
7004 struct subsys_tbl_ent {
7005         u16 subsys_vendor, subsys_devid;
7006         u32 phy_id;
7007 };
7008
7009 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
7010         /* Broadcom boards. */
7011         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
7012         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
7013         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
7014         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
7015         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
7016         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
7017         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
7018         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
7019         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
7020         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
7021         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
7022
7023         /* 3com boards. */
7024         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
7025         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
7026         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
7027         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
7028         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
7029
7030         /* DELL boards. */
7031         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
7032         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
7033         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
7034         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
7035
7036         /* Compaq boards. */
7037         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
7038         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
7039         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
7040         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
7041         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
7042
7043         /* IBM boards. */
7044         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
7045 };
7046
7047 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
7048 {
7049         int i;
7050
7051         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
7052                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
7053                      tp->pdev->subsystem_vendor) &&
7054                     (subsys_id_to_phy_id[i].subsys_devid ==
7055                      tp->pdev->subsystem_device))
7056                         return &subsys_id_to_phy_id[i];
7057         }
7058         return NULL;
7059 }
7060
7061 static int __devinit tg3_phy_probe(struct tg3 *tp)
7062 {
7063         u32 eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
7064         u32 hw_phy_id, hw_phy_id_masked;
7065         u32 val;
7066         int eeprom_signature_found, eeprom_phy_serdes, err;
7067
7068         tp->phy_id = PHY_ID_INVALID;
7069         eeprom_phy_id = PHY_ID_INVALID;
7070         eeprom_phy_serdes = 0;
7071         eeprom_signature_found = 0;
7072         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7073         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7074                 u32 nic_cfg, led_cfg;
7075                 u32 nic_phy_id, cfg2;
7076
7077                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7078                 tp->nic_sram_data_cfg = nic_cfg;
7079
7080                 eeprom_signature_found = 1;
7081
7082                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
7083                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
7084                         eeprom_phy_serdes = 1;
7085
7086                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
7087                 if (nic_phy_id != 0) {
7088                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
7089                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
7090
7091                         eeprom_phy_id  = (id1 >> 16) << 10;
7092                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
7093                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
7094                 } else
7095                         eeprom_phy_id = 0;
7096
7097                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7098                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &led_cfg);
7099                         led_cfg &= (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7100                                     SHASTA_EXT_LED_MODE_MASK);
7101                 } else
7102                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
7103
7104                 switch (led_cfg) {
7105                 default:
7106                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
7107                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7108                         break;
7109
7110                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
7111                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7112                         break;
7113
7114                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
7115                         tp->led_ctrl = LED_CTRL_MODE_MAC;
7116                         break;
7117
7118                 case SHASTA_EXT_LED_SHARED:
7119                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
7120                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7121                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
7122                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7123                                                  LED_CTRL_MODE_PHY_2);
7124                         break;
7125
7126                 case SHASTA_EXT_LED_MAC:
7127                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
7128                         break;
7129
7130                 case SHASTA_EXT_LED_COMBO:
7131                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
7132                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
7133                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7134                                                  LED_CTRL_MODE_PHY_2);
7135                         break;
7136
7137                 };
7138
7139                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7140                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
7141                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
7142                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7143
7144                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
7145                      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
7146                      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
7147                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
7148                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
7149
7150                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7151                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7152                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
7153                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7154                 }
7155                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
7156                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
7157
7158                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &cfg2);
7159                 if (cfg2 & (1 << 17))
7160                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
7161         }
7162
7163         /* Reading the PHY ID register can conflict with ASF
7164          * firwmare access to the PHY hardware.
7165          */
7166         err = 0;
7167         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7168                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
7169         } else {
7170                 /* Now read the physical PHY_ID from the chip and verify
7171                  * that it is sane.  If it doesn't look good, we fall back
7172                  * to either the hard-coded table based PHY_ID and failing
7173                  * that the value found in the eeprom area.
7174                  */
7175                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
7176                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
7177
7178                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
7179                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
7180                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
7181
7182                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
7183         }
7184
7185         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
7186                 tp->phy_id = hw_phy_id;
7187                 if (hw_phy_id_masked == PHY_ID_BCM8002)
7188                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7189         } else {
7190                 if (eeprom_signature_found) {
7191                         tp->phy_id = eeprom_phy_id;
7192                         if (eeprom_phy_serdes)
7193                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7194                 } else {
7195                         struct subsys_tbl_ent *p;
7196
7197                         /* No eeprom signature?  Try the hardcoded
7198                          * subsys device table.
7199                          */
7200                         p = lookup_by_subsys(tp);
7201                         if (!p)
7202                                 return -ENODEV;
7203
7204                         tp->phy_id = p->phy_id;
7205                         if (!tp->phy_id ||
7206                             tp->phy_id == PHY_ID_BCM8002)
7207                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7208                 }
7209         }
7210
7211         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7212             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
7213                 u32 bmsr, adv_reg, tg3_ctrl;
7214
7215                 tg3_readphy(tp, MII_BMSR, &bmsr);
7216                 tg3_readphy(tp, MII_BMSR, &bmsr);
7217
7218                 if (bmsr & BMSR_LSTATUS)
7219                         goto skip_phy_reset;
7220
7221                 err = tg3_phy_reset(tp);
7222                 if (err)
7223                         return err;
7224
7225                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
7226                            ADVERTISE_100HALF | ADVERTISE_100FULL |
7227                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
7228                 tg3_ctrl = 0;
7229                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
7230                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
7231                                     MII_TG3_CTRL_ADV_1000_FULL);
7232                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
7233                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
7234                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
7235                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
7236                 }
7237
7238                 if (!tg3_copper_is_advertising_all(tp)) {
7239                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
7240
7241                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7242                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
7243
7244                         tg3_writephy(tp, MII_BMCR,
7245                                      BMCR_ANENABLE | BMCR_ANRESTART);
7246                 }
7247                 tg3_phy_set_wirespeed(tp);
7248
7249                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
7250                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7251                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
7252         }
7253
7254 skip_phy_reset:
7255         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
7256                 err = tg3_init_5401phy_dsp(tp);
7257                 if (err)
7258                         return err;
7259         }
7260
7261         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
7262                 err = tg3_init_5401phy_dsp(tp);
7263         }
7264
7265         if (!eeprom_signature_found)
7266                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7267
7268         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7269                 tp->link_config.advertising =
7270                         (ADVERTISED_1000baseT_Half |
7271                          ADVERTISED_1000baseT_Full |
7272                          ADVERTISED_Autoneg |
7273                          ADVERTISED_FIBRE);
7274         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
7275                 tp->link_config.advertising &=
7276                         ~(ADVERTISED_1000baseT_Half |
7277                           ADVERTISED_1000baseT_Full);
7278
7279         return err;
7280 }
7281
7282 static void __devinit tg3_read_partno(struct tg3 *tp)
7283 {
7284         unsigned char vpd_data[256];
7285         int i;
7286
7287         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7288                 /* Sun decided not to put the necessary bits in the
7289                  * NVRAM of their onboard tg3 parts :(
7290                  */
7291                 strcpy(tp->board_part_number, "Sun 570X");
7292                 return;
7293         }
7294
7295         for (i = 0; i < 256; i += 4) {
7296                 u32 tmp;
7297
7298                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
7299                         goto out_not_found;
7300
7301                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
7302                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
7303                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
7304                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
7305         }
7306
7307         /* Now parse and find the part number. */
7308         for (i = 0; i < 256; ) {
7309                 unsigned char val = vpd_data[i];
7310                 int block_end;
7311
7312                 if (val == 0x82 || val == 0x91) {
7313                         i = (i + 3 +
7314                              (vpd_data[i + 1] +
7315                               (vpd_data[i + 2] << 8)));
7316                         continue;
7317                 }
7318
7319                 if (val != 0x90)
7320                         goto out_not_found;
7321
7322                 block_end = (i + 3 +
7323                              (vpd_data[i + 1] +
7324                               (vpd_data[i + 2] << 8)));
7325                 i += 3;
7326                 while (i < block_end) {
7327                         if (vpd_data[i + 0] == 'P' &&
7328                             vpd_data[i + 1] == 'N') {
7329                                 int partno_len = vpd_data[i + 2];
7330
7331                                 if (partno_len > 24)
7332                                         goto out_not_found;
7333
7334                                 memcpy(tp->board_part_number,
7335                                        &vpd_data[i + 3],
7336                                        partno_len);
7337
7338                                 /* Success. */
7339                                 return;
7340                         }
7341                 }
7342
7343                 /* Part number not found. */
7344                 goto out_not_found;
7345         }
7346
7347 out_not_found:
7348         strcpy(tp->board_part_number, "none");
7349 }
7350
7351 #ifdef CONFIG_SPARC64
7352 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
7353 {
7354         struct pci_dev *pdev = tp->pdev;
7355         struct pcidev_cookie *pcp = pdev->sysdata;
7356
7357         if (pcp != NULL) {
7358                 int node = pcp->prom_node;
7359                 u32 venid;
7360                 int err;
7361
7362                 err = prom_getproperty(node, "subsystem-vendor-id",
7363                                        (char *) &venid, sizeof(venid));
7364                 if (err == 0 || err == -1)
7365                         return 0;
7366                 if (venid == PCI_VENDOR_ID_SUN)
7367                         return 1;
7368         }
7369         return 0;
7370 }
7371 #endif
7372
7373 static int __devinit tg3_get_invariants(struct tg3 *tp)
7374 {
7375         u32 misc_ctrl_reg;
7376         u32 cacheline_sz_reg;
7377         u32 pci_state_reg, grc_misc_cfg;
7378         u32 val;
7379         u16 pci_cmd;
7380         int err;
7381
7382 #ifdef CONFIG_SPARC64
7383         if (tg3_is_sun_570X(tp))
7384                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
7385 #endif
7386
7387         /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
7388          * reordering to the mailbox registers done by the host
7389          * controller can cause major troubles.  We read back from
7390          * every mailbox register write to force the writes to be
7391          * posted to the chip in order.
7392          */
7393         if (pci_find_device(PCI_VENDOR_ID_INTEL,
7394                             PCI_DEVICE_ID_INTEL_82801AA_8, NULL) ||
7395             pci_find_device(PCI_VENDOR_ID_INTEL,
7396                             PCI_DEVICE_ID_INTEL_82801AB_8, NULL) ||
7397             pci_find_device(PCI_VENDOR_ID_INTEL,
7398                             PCI_DEVICE_ID_INTEL_82801BA_11, NULL) ||
7399             pci_find_device(PCI_VENDOR_ID_INTEL,
7400                             PCI_DEVICE_ID_INTEL_82801BA_6, NULL) ||
7401             pci_find_device(PCI_VENDOR_ID_AMD,
7402                             PCI_DEVICE_ID_AMD_FE_GATE_700C, NULL))
7403                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
7404
7405         /* Force memory write invalidate off.  If we leave it on,
7406          * then on 5700_BX chips we have to enable a workaround.
7407          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
7408          * to match the cacheline size.  The Broadcom driver have this
7409          * workaround but turns MWI off all the times so never uses
7410          * it.  This seems to suggest that the workaround is insufficient.
7411          */
7412         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7413         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
7414         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7415
7416         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
7417          * has the register indirect write enable bit set before
7418          * we try to access any of the MMIO registers.  It is also
7419          * critical that the PCI-X hw workaround situation is decided
7420          * before that as well.
7421          */
7422         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7423                               &misc_ctrl_reg);
7424
7425         tp->pci_chip_rev_id = (misc_ctrl_reg >>
7426                                MISC_HOST_CTRL_CHIPREV_SHIFT);
7427
7428         /* Initialize misc host control in PCI block. */
7429         tp->misc_host_ctrl |= (misc_ctrl_reg &
7430                                MISC_HOST_CTRL_CHIPREV);
7431         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7432                                tp->misc_host_ctrl);
7433
7434         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
7435                               &cacheline_sz_reg);
7436
7437         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
7438         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
7439         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
7440         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
7441
7442         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
7443                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
7444
7445         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
7446             tp->pci_lat_timer < 64) {
7447                 tp->pci_lat_timer = 64;
7448
7449                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
7450                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
7451                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
7452                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
7453
7454                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
7455                                        cacheline_sz_reg);
7456         }
7457
7458         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
7459                               &pci_state_reg);
7460
7461         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
7462                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
7463
7464                 /* If this is a 5700 BX chipset, and we are in PCI-X
7465                  * mode, enable register write workaround.
7466                  *
7467                  * The workaround is to use indirect register accesses
7468                  * for all chip writes not to mailbox registers.
7469                  */
7470                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
7471                         u32 pm_reg;
7472                         u16 pci_cmd;
7473
7474                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
7475
7476                         /* The chip can have it's power management PCI config
7477                          * space registers clobbered due to this bug.
7478                          * So explicitly force the chip into D0 here.
7479                          */
7480                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
7481                                               &pm_reg);
7482                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
7483                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
7484                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
7485                                                pm_reg);
7486
7487                         /* Also, force SERR#/PERR# in PCI command. */
7488                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7489                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
7490                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7491                 }
7492         }
7493
7494         /* Back to back register writes can cause problems on this chip,
7495          * the workaround is to read back all reg writes except those to
7496          * mailbox regs.  See tg3_write_indirect_reg32().
7497          *
7498          * PCI Express 5750_A0 rev chips need this workaround too.
7499          */
7500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
7501             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7502              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
7503                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
7504
7505         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
7506                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
7507         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
7508                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
7509
7510         /* Chip-specific fixup from Broadcom driver */
7511         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
7512             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
7513                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
7514                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
7515         }
7516
7517         /* Force the chip into D0. */
7518         err = tg3_set_power_state(tp, 0);
7519         if (err) {
7520                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
7521                        pci_name(tp->pdev));
7522                 return err;
7523         }
7524
7525         /* 5700 B0 chips do not support checksumming correctly due
7526          * to hardware bugs.
7527          */
7528         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
7529                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
7530
7531         /* Pseudo-header checksum is done by hardware logic and not
7532          * the offload processers, so make the chip do the pseudo-
7533          * header checksums on receive.  For transmit it is more
7534          * convenient to do the pseudo-header checksum in software
7535          * as Linux does that on transmit for us in all cases.
7536          */
7537         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
7538         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
7539
7540         /* Derive initial jumbo mode from MTU assigned in
7541          * ether_setup() via the alloc_etherdev() call
7542          */
7543         if (tp->dev->mtu > ETH_DATA_LEN)
7544                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
7545
7546         /* Determine WakeOnLan speed to use. */
7547         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7548             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
7549             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
7550             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
7551                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
7552         } else {
7553                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
7554         }
7555
7556         /* A few boards don't want Ethernet@WireSpeed phy feature */
7557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
7558             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
7559              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
7560              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
7561                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
7562
7563         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
7564             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
7565                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
7566         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
7567                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
7568
7569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
7570             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
7571                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
7572
7573         /* Only 5701 and later support tagged irq status mode.
7574          * Also, 5788 chips cannot use tagged irq status.
7575          *
7576          * However, since we are using NAPI avoid tagged irq status
7577          * because the interrupt condition is more difficult to
7578          * fully clear in that mode.
7579          */
7580         tp->coalesce_mode = 0;
7581
7582         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
7583             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
7584                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
7585
7586         /* Initialize MAC MI mode, polling disabled. */
7587         tw32_f(MAC_MI_MODE, tp->mi_mode);
7588         udelay(80);
7589
7590         /* Initialize data/descriptor byte/word swapping. */
7591         val = tr32(GRC_MODE);
7592         val &= GRC_MODE_HOST_STACKUP;
7593         tw32(GRC_MODE, val | tp->grc_mode);
7594
7595         tg3_switch_clocks(tp);
7596
7597         /* Clear this out for sanity. */
7598         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7599
7600         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
7601                               &pci_state_reg);
7602         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
7603             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
7604                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
7605
7606                 if (chiprevid == CHIPREV_ID_5701_A0 ||
7607                     chiprevid == CHIPREV_ID_5701_B0 ||
7608                     chiprevid == CHIPREV_ID_5701_B2 ||
7609                     chiprevid == CHIPREV_ID_5701_B5) {
7610                         void __iomem *sram_base;
7611
7612                         /* Write some dummy words into the SRAM status block
7613                          * area, see if it reads back correctly.  If the return
7614                          * value is bad, force enable the PCIX workaround.
7615                          */
7616                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
7617
7618                         writel(0x00000000, sram_base);
7619                         writel(0x00000000, sram_base + 4);
7620                         writel(0xffffffff, sram_base + 4);
7621                         if (readl(sram_base) != 0x00000000)
7622                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
7623                 }
7624         }
7625
7626         udelay(50);
7627         tg3_nvram_init(tp);
7628
7629         grc_misc_cfg = tr32(GRC_MISC_CFG);
7630         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
7631
7632         /* Broadcom's driver says that CIOBE multisplit has a bug */
7633 #if 0
7634         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7635             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
7636                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
7637                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
7638         }
7639 #endif
7640         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7641             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
7642              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
7643                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
7644
7645         /* these are limited to 10/100 only */
7646         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
7647              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
7648             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7649              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
7650              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
7651               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
7652               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
7653             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
7654              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
7655               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
7656                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
7657
7658         err = tg3_phy_probe(tp);
7659         if (err) {
7660                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
7661                        pci_name(tp->pdev), err);
7662                 /* ... but do not return immediately ... */
7663         }
7664
7665         tg3_read_partno(tp);
7666
7667         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7668                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
7669         } else {
7670                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7671                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
7672                 else
7673                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
7674         }
7675
7676         /* 5700 {AX,BX} chips have a broken status block link
7677          * change bit implementation, so we must use the
7678          * status register in those cases.
7679          */
7680         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7681                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
7682         else
7683                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
7684
7685         /* The led_ctrl is set during tg3_phy_probe, here we might
7686          * have to force the link status polling mechanism based
7687          * upon subsystem IDs.
7688          */
7689         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
7690             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7691                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
7692                                   TG3_FLAG_USE_LINKCHG_REG);
7693         }
7694
7695         /* For all SERDES we poll the MAC status register. */
7696         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7697                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
7698         else
7699                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
7700
7701         /* 5700 BX chips need to have their TX producer index mailboxes
7702          * written twice to workaround a bug.
7703          */
7704         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
7705                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
7706         else
7707                 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
7708
7709         /* It seems all chips can get confused if TX buffers
7710          * straddle the 4GB address boundary in some cases.
7711          */
7712         tp->dev->hard_start_xmit = tg3_start_xmit;
7713
7714         tp->rx_offset = 2;
7715         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
7716             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
7717                 tp->rx_offset = 0;
7718
7719         /* By default, disable wake-on-lan.  User can change this
7720          * using ETHTOOL_SWOL.
7721          */
7722         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7723
7724         return err;
7725 }
7726
7727 #ifdef CONFIG_SPARC64
7728 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
7729 {
7730         struct net_device *dev = tp->dev;
7731         struct pci_dev *pdev = tp->pdev;
7732         struct pcidev_cookie *pcp = pdev->sysdata;
7733
7734         if (pcp != NULL) {
7735                 int node = pcp->prom_node;
7736
7737                 if (prom_getproplen(node, "local-mac-address") == 6) {
7738                         prom_getproperty(node, "local-mac-address",
7739                                          dev->dev_addr, 6);
7740                         return 0;
7741                 }
7742         }
7743         return -ENODEV;
7744 }
7745
7746 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
7747 {
7748         struct net_device *dev = tp->dev;
7749
7750         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
7751         return 0;
7752 }
7753 #endif
7754
7755 static int __devinit tg3_get_device_address(struct tg3 *tp)
7756 {
7757         struct net_device *dev = tp->dev;
7758         u32 hi, lo, mac_offset;
7759
7760 #ifdef CONFIG_SPARC64
7761         if (!tg3_get_macaddr_sparc(tp))
7762                 return 0;
7763 #endif
7764
7765         mac_offset = 0x7c;
7766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7767             !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
7768                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
7769                         mac_offset = 0xcc;
7770                 if (tg3_nvram_lock(tp))
7771                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
7772                 else
7773                         tg3_nvram_unlock(tp);
7774         }
7775
7776         /* First try to get it from MAC address mailbox. */
7777         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
7778         if ((hi >> 16) == 0x484b) {
7779                 dev->dev_addr[0] = (hi >>  8) & 0xff;
7780                 dev->dev_addr[1] = (hi >>  0) & 0xff;
7781
7782                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
7783                 dev->dev_addr[2] = (lo >> 24) & 0xff;
7784                 dev->dev_addr[3] = (lo >> 16) & 0xff;
7785                 dev->dev_addr[4] = (lo >>  8) & 0xff;
7786                 dev->dev_addr[5] = (lo >>  0) & 0xff;
7787         }
7788         /* Next, try NVRAM. */
7789         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
7790                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
7791                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
7792                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
7793                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
7794                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
7795                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
7796                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
7797                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
7798         }
7799         /* Finally just fetch it out of the MAC control regs. */
7800         else {
7801                 hi = tr32(MAC_ADDR_0_HIGH);
7802                 lo = tr32(MAC_ADDR_0_LOW);
7803
7804                 dev->dev_addr[5] = lo & 0xff;
7805                 dev->dev_addr[4] = (lo >> 8) & 0xff;
7806                 dev->dev_addr[3] = (lo >> 16) & 0xff;
7807                 dev->dev_addr[2] = (lo >> 24) & 0xff;
7808                 dev->dev_addr[1] = hi & 0xff;
7809                 dev->dev_addr[0] = (hi >> 8) & 0xff;
7810         }
7811
7812         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7813 #ifdef CONFIG_SPARC64
7814                 if (!tg3_get_default_macaddr_sparc(tp))
7815                         return 0;
7816 #endif
7817                 return -EINVAL;
7818         }
7819         return 0;
7820 }
7821
7822 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
7823 {
7824         struct tg3_internal_buffer_desc test_desc;
7825         u32 sram_dma_descs;
7826         int i, ret;
7827
7828         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
7829
7830         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
7831         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
7832         tw32(RDMAC_STATUS, 0);
7833         tw32(WDMAC_STATUS, 0);
7834
7835         tw32(BUFMGR_MODE, 0);
7836         tw32(FTQ_RESET, 0);
7837
7838         test_desc.addr_hi = ((u64) buf_dma) >> 32;
7839         test_desc.addr_lo = buf_dma & 0xffffffff;
7840         test_desc.nic_mbuf = 0x00002100;
7841         test_desc.len = size;
7842
7843         /*
7844          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
7845          * the *second* time the tg3 driver was getting loaded after an
7846          * initial scan.
7847          *
7848          * Broadcom tells me:
7849          *   ...the DMA engine is connected to the GRC block and a DMA
7850          *   reset may affect the GRC block in some unpredictable way...
7851          *   The behavior of resets to individual blocks has not been tested.
7852          *
7853          * Broadcom noted the GRC reset will also reset all sub-components.
7854          */
7855         if (to_device) {
7856                 test_desc.cqid_sqid = (13 << 8) | 2;
7857
7858                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
7859                 udelay(40);
7860         } else {
7861                 test_desc.cqid_sqid = (16 << 8) | 7;
7862
7863                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
7864                 udelay(40);
7865         }
7866         test_desc.flags = 0x00000005;
7867
7868         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
7869                 u32 val;
7870
7871                 val = *(((u32 *)&test_desc) + i);
7872                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
7873                                        sram_dma_descs + (i * sizeof(u32)));
7874                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
7875         }
7876         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
7877
7878         if (to_device) {
7879                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
7880         } else {
7881                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
7882         }
7883
7884         ret = -ENODEV;
7885         for (i = 0; i < 40; i++) {
7886                 u32 val;
7887
7888                 if (to_device)
7889                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
7890                 else
7891                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
7892                 if ((val & 0xffff) == sram_dma_descs) {
7893                         ret = 0;
7894                         break;
7895                 }
7896
7897                 udelay(100);
7898         }
7899
7900         return ret;
7901 }
7902
7903 #define TEST_BUFFER_SIZE        0x400
7904
7905 static int __devinit tg3_test_dma(struct tg3 *tp)
7906 {
7907         dma_addr_t buf_dma;
7908         u32 *buf;
7909         int ret;
7910
7911         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
7912         if (!buf) {
7913                 ret = -ENOMEM;
7914                 goto out_nofree;
7915         }
7916
7917         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
7918                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
7919
7920 #ifndef CONFIG_X86
7921         {
7922                 u8 byte;
7923                 int cacheline_size;
7924                 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
7925
7926                 if (byte == 0)
7927                         cacheline_size = 1024;
7928                 else
7929                         cacheline_size = (int) byte * 4;
7930
7931                 switch (cacheline_size) {
7932                 case 16:
7933                 case 32:
7934                 case 64:
7935                 case 128:
7936                         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
7937                             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7938                                 tp->dma_rwctrl |=
7939                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
7940                                 break;
7941                         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7942                                 tp->dma_rwctrl &=
7943                                         ~(DMA_RWCTRL_PCI_WRITE_CMD);
7944                                 tp->dma_rwctrl |=
7945                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
7946                                 break;
7947                         }
7948                         /* fallthrough */
7949                 case 256:
7950                         if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
7951                             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7952                                 tp->dma_rwctrl |=
7953                                         DMA_RWCTRL_WRITE_BNDRY_256;
7954                         else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7955                                 tp->dma_rwctrl |=
7956                                         DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
7957                 };
7958         }
7959 #endif
7960
7961         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7962                 /* DMA read watermark not used on PCIE */
7963                 tp->dma_rwctrl |= 0x00180000;
7964         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7965                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
7966                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
7967                         tp->dma_rwctrl |= 0x003f0000;
7968                 else
7969                         tp->dma_rwctrl |= 0x003f000f;
7970         } else {
7971                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
7972                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7973                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
7974
7975                         if (ccval == 0x6 || ccval == 0x7)
7976                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
7977
7978                         /* Set bit 23 to renable PCIX hw bug fix */
7979                         tp->dma_rwctrl |= 0x009f0000;
7980                 } else {
7981                         tp->dma_rwctrl |= 0x001b000f;
7982                 }
7983         }
7984
7985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
7986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7987                 tp->dma_rwctrl &= 0xfffffff0;
7988
7989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
7991                 /* Remove this if it causes problems for some boards. */
7992                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
7993
7994                 /* On 5700/5701 chips, we need to set this bit.
7995                  * Otherwise the chip will issue cacheline transactions
7996                  * to streamable DMA memory with not all the byte
7997                  * enables turned on.  This is an error on several
7998                  * RISC PCI controllers, in particular sparc64.
7999                  *
8000                  * On 5703/5704 chips, this bit has been reassigned
8001                  * a different meaning.  In particular, it is used
8002                  * on those chips to enable a PCI-X workaround.
8003                  */
8004                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
8005         }
8006
8007         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8008
8009 #if 0
8010         /* Unneeded, already done by tg3_get_invariants.  */
8011         tg3_switch_clocks(tp);
8012 #endif
8013
8014         ret = 0;
8015         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8016             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
8017                 goto out;
8018
8019         while (1) {
8020                 u32 *p = buf, i;
8021
8022                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
8023                         p[i] = i;
8024
8025                 /* Send the buffer to the chip. */
8026                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
8027                 if (ret) {
8028                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
8029                         break;
8030                 }
8031
8032 #if 0
8033                 /* validate data reached card RAM correctly. */
8034                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8035                         u32 val;
8036                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
8037                         if (le32_to_cpu(val) != p[i]) {
8038                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
8039                                 /* ret = -ENODEV here? */
8040                         }
8041                         p[i] = 0;
8042                 }
8043 #endif
8044                 /* Now read it back. */
8045                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
8046                 if (ret) {
8047                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
8048
8049                         break;
8050                 }
8051
8052                 /* Verify it. */
8053                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8054                         if (p[i] == i)
8055                                 continue;
8056
8057                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
8058                             DMA_RWCTRL_WRITE_BNDRY_DISAB) {
8059                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
8060                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8061                                 break;
8062                         } else {
8063                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
8064                                 ret = -ENODEV;
8065                                 goto out;
8066                         }
8067                 }
8068
8069                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
8070                         /* Success. */
8071                         ret = 0;
8072                         break;
8073                 }
8074         }
8075
8076 out:
8077         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
8078 out_nofree:
8079         return ret;
8080 }
8081
8082 static void __devinit tg3_init_link_config(struct tg3 *tp)
8083 {
8084         tp->link_config.advertising =
8085                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
8086                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
8087                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
8088                  ADVERTISED_Autoneg | ADVERTISED_MII);
8089         tp->link_config.speed = SPEED_INVALID;
8090         tp->link_config.duplex = DUPLEX_INVALID;
8091         tp->link_config.autoneg = AUTONEG_ENABLE;
8092         netif_carrier_off(tp->dev);
8093         tp->link_config.active_speed = SPEED_INVALID;
8094         tp->link_config.active_duplex = DUPLEX_INVALID;
8095         tp->link_config.phy_is_low_power = 0;
8096         tp->link_config.orig_speed = SPEED_INVALID;
8097         tp->link_config.orig_duplex = DUPLEX_INVALID;
8098         tp->link_config.orig_autoneg = AUTONEG_INVALID;
8099 }
8100
8101 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
8102 {
8103         tp->bufmgr_config.mbuf_read_dma_low_water =
8104                 DEFAULT_MB_RDMA_LOW_WATER;
8105         tp->bufmgr_config.mbuf_mac_rx_low_water =
8106                 DEFAULT_MB_MACRX_LOW_WATER;
8107         tp->bufmgr_config.mbuf_high_water =
8108                 DEFAULT_MB_HIGH_WATER;
8109
8110         tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
8111                 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
8112         tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
8113                 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
8114         tp->bufmgr_config.mbuf_high_water_jumbo =
8115                 DEFAULT_MB_HIGH_WATER_JUMBO;
8116
8117         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
8118         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
8119 }
8120
8121 static char * __devinit tg3_phy_string(struct tg3 *tp)
8122 {
8123         switch (tp->phy_id & PHY_ID_MASK) {
8124         case PHY_ID_BCM5400:    return "5400";
8125         case PHY_ID_BCM5401:    return "5401";
8126         case PHY_ID_BCM5411:    return "5411";
8127         case PHY_ID_BCM5701:    return "5701";
8128         case PHY_ID_BCM5703:    return "5703";
8129         case PHY_ID_BCM5704:    return "5704";
8130         case PHY_ID_BCM5705:    return "5705";
8131         case PHY_ID_BCM5750:    return "5750";
8132         case PHY_ID_BCM8002:    return "8002/serdes";
8133         case 0:                 return "serdes";
8134         default:                return "unknown";
8135         };
8136 }
8137
8138 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
8139 {
8140         struct pci_dev *peer;
8141         unsigned int func, devnr = tp->pdev->devfn & ~7;
8142
8143         for (func = 0; func < 8; func++) {
8144                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
8145                 if (peer && peer != tp->pdev)
8146                         break;
8147                 pci_dev_put(peer);
8148         }
8149         if (!peer || peer == tp->pdev)
8150                 BUG();
8151
8152         /*
8153          * We don't need to keep the refcount elevated; there's no way
8154          * to remove one half of this device without removing the other
8155          */
8156         pci_dev_put(peer);
8157
8158         return peer;
8159 }
8160
8161 static int __devinit tg3_init_one(struct pci_dev *pdev,
8162                                   const struct pci_device_id *ent)
8163 {
8164         static int tg3_version_printed = 0;
8165         unsigned long tg3reg_base, tg3reg_len;
8166         struct net_device *dev;
8167         struct tg3 *tp;
8168         int i, err, pci_using_dac, pm_cap;
8169
8170         if (tg3_version_printed++ == 0)
8171                 printk(KERN_INFO "%s", version);
8172
8173         err = pci_enable_device(pdev);
8174         if (err) {
8175                 printk(KERN_ERR PFX "Cannot enable PCI device, "
8176                        "aborting.\n");
8177                 return err;
8178         }
8179
8180         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8181                 printk(KERN_ERR PFX "Cannot find proper PCI device "
8182                        "base address, aborting.\n");
8183                 err = -ENODEV;
8184                 goto err_out_disable_pdev;
8185         }
8186
8187         err = pci_request_regions(pdev, DRV_MODULE_NAME);
8188         if (err) {
8189                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
8190                        "aborting.\n");
8191                 goto err_out_disable_pdev;
8192         }
8193
8194         pci_set_master(pdev);
8195
8196         /* Find power-management capability. */
8197         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
8198         if (pm_cap == 0) {
8199                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
8200                        "aborting.\n");
8201                 err = -EIO;
8202                 goto err_out_free_res;
8203         }
8204
8205         /* Configure DMA attributes. */
8206         err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
8207         if (!err) {
8208                 pci_using_dac = 1;
8209                 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
8210                 if (err < 0) {
8211                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
8212                                "for consistent allocations\n");
8213                         goto err_out_free_res;
8214                 }
8215         } else {
8216                 err = pci_set_dma_mask(pdev, 0xffffffffULL);
8217                 if (err) {
8218                         printk(KERN_ERR PFX "No usable DMA configuration, "
8219                                "aborting.\n");
8220                         goto err_out_free_res;
8221                 }
8222                 pci_using_dac = 0;
8223         }
8224
8225         tg3reg_base = pci_resource_start(pdev, 0);
8226         tg3reg_len = pci_resource_len(pdev, 0);
8227
8228         dev = alloc_etherdev(sizeof(*tp));
8229         if (!dev) {
8230                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
8231                 err = -ENOMEM;
8232                 goto err_out_free_res;
8233         }
8234
8235         SET_MODULE_OWNER(dev);
8236         SET_NETDEV_DEV(dev, &pdev->dev);
8237
8238         if (pci_using_dac)
8239                 dev->features |= NETIF_F_HIGHDMA;
8240         dev->features |= NETIF_F_LLTX;
8241 #if TG3_VLAN_TAG_USED
8242         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8243         dev->vlan_rx_register = tg3_vlan_rx_register;
8244         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
8245 #endif
8246
8247         tp = netdev_priv(dev);
8248         tp->pdev = pdev;
8249         tp->dev = dev;
8250         tp->pm_cap = pm_cap;
8251         tp->mac_mode = TG3_DEF_MAC_MODE;
8252         tp->rx_mode = TG3_DEF_RX_MODE;
8253         tp->tx_mode = TG3_DEF_TX_MODE;
8254         tp->mi_mode = MAC_MI_MODE_BASE;
8255         if (tg3_debug > 0)
8256                 tp->msg_enable = tg3_debug;
8257         else
8258                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
8259
8260         /* The word/byte swap controls here control register access byte
8261          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
8262          * setting below.
8263          */
8264         tp->misc_host_ctrl =
8265                 MISC_HOST_CTRL_MASK_PCI_INT |
8266                 MISC_HOST_CTRL_WORD_SWAP |
8267                 MISC_HOST_CTRL_INDIR_ACCESS |
8268                 MISC_HOST_CTRL_PCISTATE_RW;
8269
8270         /* The NONFRM (non-frame) byte/word swap controls take effect
8271          * on descriptor entries, anything which isn't packet data.
8272          *
8273          * The StrongARM chips on the board (one for tx, one for rx)
8274          * are running in big-endian mode.
8275          */
8276         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
8277                         GRC_MODE_WSWAP_NONFRM_DATA);
8278 #ifdef __BIG_ENDIAN
8279         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
8280 #endif
8281         spin_lock_init(&tp->lock);
8282         spin_lock_init(&tp->tx_lock);
8283         spin_lock_init(&tp->indirect_lock);
8284         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
8285
8286         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
8287         if (tp->regs == 0UL) {
8288                 printk(KERN_ERR PFX "Cannot map device registers, "
8289                        "aborting.\n");
8290                 err = -ENOMEM;
8291                 goto err_out_free_dev;
8292         }
8293
8294         tg3_init_link_config(tp);
8295
8296         tg3_init_bufmgr_config(tp);
8297
8298         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
8299         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
8300         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
8301
8302         dev->open = tg3_open;
8303         dev->stop = tg3_close;
8304         dev->get_stats = tg3_get_stats;
8305         dev->set_multicast_list = tg3_set_rx_mode;
8306         dev->set_mac_address = tg3_set_mac_addr;
8307         dev->do_ioctl = tg3_ioctl;
8308         dev->tx_timeout = tg3_tx_timeout;
8309         dev->poll = tg3_poll;
8310         dev->ethtool_ops = &tg3_ethtool_ops;
8311         dev->weight = 64;
8312         dev->watchdog_timeo = TG3_TX_TIMEOUT;
8313         dev->change_mtu = tg3_change_mtu;
8314         dev->irq = pdev->irq;
8315 #ifdef CONFIG_NET_POLL_CONTROLLER
8316         dev->poll_controller = tg3_poll_controller;
8317 #endif
8318
8319         err = tg3_get_invariants(tp);
8320         if (err) {
8321                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
8322                        "aborting.\n");
8323                 goto err_out_iounmap;
8324         }
8325
8326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
8327             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8328                 tp->bufmgr_config.mbuf_read_dma_low_water =
8329                         DEFAULT_MB_RDMA_LOW_WATER_5705;
8330                 tp->bufmgr_config.mbuf_mac_rx_low_water =
8331                         DEFAULT_MB_MACRX_LOW_WATER_5705;
8332                 tp->bufmgr_config.mbuf_high_water =
8333                         DEFAULT_MB_HIGH_WATER_5705;
8334         }
8335
8336 #if TG3_TSO_SUPPORT != 0
8337         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8338             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8339             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
8340             ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 &&
8341              GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)) {
8342                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8343         } else {
8344                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8345         }
8346
8347         /* TSO is off by default, user can enable using ethtool.  */
8348 #if 0
8349         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
8350                 dev->features |= NETIF_F_TSO;
8351 #endif
8352
8353 #endif
8354
8355         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
8356             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8357             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
8358                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
8359                 tp->rx_pending = 63;
8360         }
8361
8362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8363                 tp->pdev_peer = tg3_find_5704_peer(tp);
8364
8365         err = tg3_get_device_address(tp);
8366         if (err) {
8367                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
8368                        "aborting.\n");
8369                 goto err_out_iounmap;
8370         }
8371
8372         /*
8373          * Reset chip in case UNDI or EFI driver did not shutdown
8374          * DMA self test will enable WDMAC and we'll see (spurious)
8375          * pending DMA on the PCI bus at that point.
8376          */
8377         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
8378             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8379                 pci_save_state(tp->pdev);
8380                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
8381                 tg3_halt(tp);
8382         }
8383
8384         err = tg3_test_dma(tp);
8385         if (err) {
8386                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
8387                 goto err_out_iounmap;
8388         }
8389
8390         /* Tigon3 can do ipv4 only... and some chips have buggy
8391          * checksumming.
8392          */
8393         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
8394                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8395                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8396         } else
8397                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8398
8399         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
8400                 dev->features &= ~NETIF_F_HIGHDMA;
8401
8402         /* flow control autonegotiation is default behavior */
8403         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8404
8405         err = register_netdev(dev);
8406         if (err) {
8407                 printk(KERN_ERR PFX "Cannot register net device, "
8408                        "aborting.\n");
8409                 goto err_out_iounmap;
8410         }
8411
8412         pci_set_drvdata(pdev, dev);
8413
8414         /* Now that we have fully setup the chip, save away a snapshot
8415          * of the PCI config space.  We need to restore this after
8416          * GRC_MISC_CFG core clock resets and some resume events.
8417          */
8418         pci_save_state(tp->pdev);
8419
8420         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
8421                dev->name,
8422                tp->board_part_number,
8423                tp->pci_chip_rev_id,
8424                tg3_phy_string(tp),
8425                ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
8426                ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
8427                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
8428                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
8429                ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
8430                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
8431
8432         for (i = 0; i < 6; i++)
8433                 printk("%2.2x%c", dev->dev_addr[i],
8434                        i == 5 ? '\n' : ':');
8435
8436         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
8437                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
8438                "TSOcap[%d] \n",
8439                dev->name,
8440                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
8441                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
8442                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
8443                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
8444                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
8445                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
8446                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
8447
8448         return 0;
8449
8450 err_out_iounmap:
8451         iounmap(tp->regs);
8452
8453 err_out_free_dev:
8454         free_netdev(dev);
8455
8456 err_out_free_res:
8457         pci_release_regions(pdev);
8458
8459 err_out_disable_pdev:
8460         pci_disable_device(pdev);
8461         pci_set_drvdata(pdev, NULL);
8462         return err;
8463 }
8464
8465 static void __devexit tg3_remove_one(struct pci_dev *pdev)
8466 {
8467         struct net_device *dev = pci_get_drvdata(pdev);
8468
8469         if (dev) {
8470                 struct tg3 *tp = netdev_priv(dev);
8471
8472                 unregister_netdev(dev);
8473                 iounmap(tp->regs);
8474                 free_netdev(dev);
8475                 pci_release_regions(pdev);
8476                 pci_disable_device(pdev);
8477                 pci_set_drvdata(pdev, NULL);
8478         }
8479 }
8480
8481 static int tg3_suspend(struct pci_dev *pdev, u32 state)
8482 {
8483         struct net_device *dev = pci_get_drvdata(pdev);
8484         struct tg3 *tp = netdev_priv(dev);
8485         int err;
8486
8487         if (!netif_running(dev))
8488                 return 0;
8489
8490         tg3_netif_stop(tp);
8491
8492         del_timer_sync(&tp->timer);
8493
8494         spin_lock_irq(&tp->lock);
8495         spin_lock(&tp->tx_lock);
8496         tg3_disable_ints(tp);
8497         spin_unlock(&tp->tx_lock);
8498         spin_unlock_irq(&tp->lock);
8499
8500         netif_device_detach(dev);
8501
8502         spin_lock_irq(&tp->lock);
8503         spin_lock(&tp->tx_lock);
8504         tg3_halt(tp);
8505         spin_unlock(&tp->tx_lock);
8506         spin_unlock_irq(&tp->lock);
8507
8508         err = tg3_set_power_state(tp, state);
8509         if (err) {
8510                 spin_lock_irq(&tp->lock);
8511                 spin_lock(&tp->tx_lock);
8512
8513                 tg3_init_hw(tp);
8514
8515                 tp->timer.expires = jiffies + tp->timer_offset;
8516                 add_timer(&tp->timer);
8517
8518                 netif_device_attach(dev);
8519                 tg3_netif_start(tp);
8520
8521                 spin_unlock(&tp->tx_lock);
8522                 spin_unlock_irq(&tp->lock);
8523         }
8524
8525         return err;
8526 }
8527
8528 static int tg3_resume(struct pci_dev *pdev)
8529 {
8530         struct net_device *dev = pci_get_drvdata(pdev);
8531         struct tg3 *tp = netdev_priv(dev);
8532         int err;
8533
8534         if (!netif_running(dev))
8535                 return 0;
8536
8537         pci_restore_state(tp->pdev);
8538
8539         err = tg3_set_power_state(tp, 0);
8540         if (err)
8541                 return err;
8542
8543         netif_device_attach(dev);
8544
8545         spin_lock_irq(&tp->lock);
8546         spin_lock(&tp->tx_lock);
8547
8548         tg3_init_hw(tp);
8549
8550         tp->timer.expires = jiffies + tp->timer_offset;
8551         add_timer(&tp->timer);
8552
8553         tg3_enable_ints(tp);
8554
8555         tg3_netif_start(tp);
8556
8557         spin_unlock(&tp->tx_lock);
8558         spin_unlock_irq(&tp->lock);
8559
8560         return 0;
8561 }
8562
8563 static struct pci_driver tg3_driver = {
8564         .name           = DRV_MODULE_NAME,
8565         .id_table       = tg3_pci_tbl,
8566         .probe          = tg3_init_one,
8567         .remove         = __devexit_p(tg3_remove_one),
8568         .suspend        = tg3_suspend,
8569         .resume         = tg3_resume
8570 };
8571
8572 static int __init tg3_init(void)
8573 {
8574         return pci_module_init(&tg3_driver);
8575 }
8576
8577 static void __exit tg3_cleanup(void)
8578 {
8579         pci_unregister_driver(&tg3_driver);
8580 }
8581
8582 module_init(tg3_init);
8583 module_exit(tg3_cleanup);